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drm/radeon/kms: rs400/480 should set common registers.
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
3ce0a23d 39
70967ab9
BH		 40#include <linux/firmware.h>
41#include <linux/platform_device.h>
42
551ebd83
DA		 43#include "r100_reg_safe.h"
44#include "rn50_reg_safe.h"
45
70967ab9
BH		 46/* Firmware Names */
47#define FIRMWARE_R100 "radeon/R100_cp.bin"
48#define FIRMWARE_R200 "radeon/R200_cp.bin"
49#define FIRMWARE_R300 "radeon/R300_cp.bin"
50#define FIRMWARE_R420 "radeon/R420_cp.bin"
51#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
52#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
53#define FIRMWARE_R520 "radeon/R520_cp.bin"
54
55MODULE_FIRMWARE(FIRMWARE_R100);
56MODULE_FIRMWARE(FIRMWARE_R200);
57MODULE_FIRMWARE(FIRMWARE_R300);
58MODULE_FIRMWARE(FIRMWARE_R420);
59MODULE_FIRMWARE(FIRMWARE_RS690);
60MODULE_FIRMWARE(FIRMWARE_RS600);
61MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 62
551ebd83
DA		 63#include "r100_track.h"
64
771fe6b9
JG		 65/* This files gather functions specifics to:
66 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 67 */
771fe6b9 68
05a05c50
AD		 69/* hpd for digital panel detect/disconnect */
70bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71{
72 bool connected = false;
73
74 switch (hpd) {
75 case RADEON_HPD_1:
76 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
77 connected = true;
78 break;
79 case RADEON_HPD_2:
80 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
81 connected = true;
82 break;
83 default:
84 break;
85 }
86 return connected;
87}
88
89void r100_hpd_set_polarity(struct radeon_device *rdev,
90 enum radeon_hpd_id hpd)
91{
92 u32 tmp;
93 bool connected = r100_hpd_sense(rdev, hpd);
94
95 switch (hpd) {
96 case RADEON_HPD_1:
97 tmp = RREG32(RADEON_FP_GEN_CNTL);
98 if (connected)
99 tmp &= ~RADEON_FP_DETECT_INT_POL;
100 else
101 tmp |= RADEON_FP_DETECT_INT_POL;
102 WREG32(RADEON_FP_GEN_CNTL, tmp);
103 break;
104 case RADEON_HPD_2:
105 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106 if (connected)
107 tmp &= ~RADEON_FP2_DETECT_INT_POL;
108 else
109 tmp |= RADEON_FP2_DETECT_INT_POL;
110 WREG32(RADEON_FP2_GEN_CNTL, tmp);
111 break;
112 default:
113 break;
114 }
115}
116
117void r100_hpd_init(struct radeon_device *rdev)
118{
119 struct drm_device *dev = rdev->ddev;
120 struct drm_connector *connector;
121
122 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
123 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
124 switch (radeon_connector->hpd.hpd) {
125 case RADEON_HPD_1:
126 rdev->irq.hpd[0] = true;
127 break;
128 case RADEON_HPD_2:
129 rdev->irq.hpd[1] = true;
130 break;
131 default:
132 break;
133 }
134 }
003e69f9
JG		 135 if (rdev->irq.installed)
136 r100_irq_set(rdev);
05a05c50
AD		 137}
138
139void r100_hpd_fini(struct radeon_device *rdev)
140{
141 struct drm_device *dev = rdev->ddev;
142 struct drm_connector *connector;
143
144 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
145 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
146 switch (radeon_connector->hpd.hpd) {
147 case RADEON_HPD_1:
148 rdev->irq.hpd[0] = false;
149 break;
150 case RADEON_HPD_2:
151 rdev->irq.hpd[1] = false;
152 break;
153 default:
154 break;
155 }
156 }
157}
158
771fe6b9
JG		 159/*
160 * PCI GART
161 */
162void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
163{
164 /* TODO: can we do somethings here ? */
165 /* It seems hw only cache one entry so we should discard this
166 * entry otherwise if first GPU GART read hit this entry it
167 * could end up in wrong address. */
168}
169
4aac0473 170int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 171{
771fe6b9
JG		 172 int r;
173
4aac0473
JG		 174 if (rdev->gart.table.ram.ptr) {
175 WARN(1, "R100 PCI GART already initialized.\n");
176 return 0;
177 }
771fe6b9
JG		 178 /* Initialize common gart structure */
179 r = radeon_gart_init(rdev);
4aac0473 180 if (r)
771fe6b9 181 return r;
4aac0473
JG		 182 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
183 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
184 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
185 return radeon_gart_table_ram_alloc(rdev);
186}
187
17e15b0c
DA		 188/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
189void r100_enable_bm(struct radeon_device *rdev)
190{
191 uint32_t tmp;
192 /* Enable bus mastering */
193 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
194 WREG32(RADEON_BUS_CNTL, tmp);
195}
196
4aac0473
JG		 197int r100_pci_gart_enable(struct radeon_device *rdev)
198{
199 uint32_t tmp;
200
82568565 201 radeon_gart_restore(rdev);
771fe6b9
JG		 202 /* discard memory request outside of configured range */
203 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
204 WREG32(RADEON_AIC_CNTL, tmp);
205 /* set address range for PCI address translate */
d594e46a
JG		 206 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
207 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 208 /* set PCI GART page-table base address */
209 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
210 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
211 WREG32(RADEON_AIC_CNTL, tmp);
212 r100_pci_gart_tlb_flush(rdev);
213 rdev->gart.ready = true;
214 return 0;
215}
216
217void r100_pci_gart_disable(struct radeon_device *rdev)
218{
219 uint32_t tmp;
220
221 /* discard memory request outside of configured range */
222 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
223 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
224 WREG32(RADEON_AIC_LO_ADDR, 0);
225 WREG32(RADEON_AIC_HI_ADDR, 0);
226}
227
228int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
229{
230 if (i < 0 || i > rdev->gart.num_gpu_pages) {
231 return -EINVAL;
232 }
ed10f95d 233 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 234 return 0;
235}
236
4aac0473 237void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 238{
f9274562 239 radeon_gart_fini(rdev);
4aac0473
JG		 240 r100_pci_gart_disable(rdev);
241 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 242}
243
7ed220d7
MD		 244int r100_irq_set(struct radeon_device *rdev)
245{
246 uint32_t tmp = 0;
247
003e69f9
JG		 248 if (!rdev->irq.installed) {
249 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250 WREG32(R_000040_GEN_INT_CNTL, 0);
251 return -EINVAL;
252 }
7ed220d7
MD		 253 if (rdev->irq.sw_int) {
254 tmp |= RADEON_SW_INT_ENABLE;
255 }
256 if (rdev->irq.crtc_vblank_int[0]) {
257 tmp |= RADEON_CRTC_VBLANK_MASK;
258 }
259 if (rdev->irq.crtc_vblank_int[1]) {
260 tmp |= RADEON_CRTC2_VBLANK_MASK;
261 }
05a05c50
AD		 262 if (rdev->irq.hpd[0]) {
263 tmp |= RADEON_FP_DETECT_MASK;
264 }
265 if (rdev->irq.hpd[1]) {
266 tmp |= RADEON_FP2_DETECT_MASK;
267 }
7ed220d7
MD		 268 WREG32(RADEON_GEN_INT_CNTL, tmp);
269 return 0;
270}
271
9f022ddf
JG		 272void r100_irq_disable(struct radeon_device *rdev)
273{
274 u32 tmp;
275
276 WREG32(R_000040_GEN_INT_CNTL, 0);
277 /* Wait and acknowledge irq */
278 mdelay(1);
279 tmp = RREG32(R_000044_GEN_INT_STATUS);
280 WREG32(R_000044_GEN_INT_STATUS, tmp);
281}
282
7ed220d7
MD		 283static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
284{
285 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 286 uint32_t irq_mask = RADEON_SW_INT_TEST |
287 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
288 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 289
290 if (irqs) {
291 WREG32(RADEON_GEN_INT_STATUS, irqs);
292 }
293 return irqs & irq_mask;
294}
295
296int r100_irq_process(struct radeon_device *rdev)
297{
3e5cb98d 298 uint32_t status, msi_rearm;
d4877cf2 299 bool queue_hotplug = false;
7ed220d7
MD		 300
301 status = r100_irq_ack(rdev);
302 if (!status) {
303 return IRQ_NONE;
304 }
a513c184
JG		 305 if (rdev->shutdown) {
306 return IRQ_NONE;
307 }
7ed220d7
MD		 308 while (status) {
309 /* SW interrupt */
310 if (status & RADEON_SW_INT_TEST) {
311 radeon_fence_process(rdev);
312 }
313 /* Vertical blank interrupts */
314 if (status & RADEON_CRTC_VBLANK_STAT) {
315 drm_handle_vblank(rdev->ddev, 0);
839461d3 316 rdev->pm.vblank_sync = true;
73a6d3fc 317 wake_up(&rdev->irq.vblank_queue);
7ed220d7
MD		 318 }
319 if (status & RADEON_CRTC2_VBLANK_STAT) {
320 drm_handle_vblank(rdev->ddev, 1);
839461d3 321 rdev->pm.vblank_sync = true;
73a6d3fc 322 wake_up(&rdev->irq.vblank_queue);
7ed220d7 323 }
05a05c50 324 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 325 queue_hotplug = true;
326 DRM_DEBUG("HPD1\n");
05a05c50
AD		 327 }
328 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 329 queue_hotplug = true;
330 DRM_DEBUG("HPD2\n");
05a05c50 331 }
7ed220d7
MD		 332 status = r100_irq_ack(rdev);
333 }
d4877cf2
AD		 334 if (queue_hotplug)
335 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 336 if (rdev->msi_enabled) {
337 switch (rdev->family) {
338 case CHIP_RS400:
339 case CHIP_RS480:
340 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
341 WREG32(RADEON_AIC_CNTL, msi_rearm);
342 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
343 break;
344 default:
345 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
346 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
347 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
348 break;
349 }
350 }
7ed220d7
MD		 351 return IRQ_HANDLED;
352}
353
354u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
355{
356 if (crtc == 0)
357 return RREG32(RADEON_CRTC_CRNT_FRAME);
358 else
359 return RREG32(RADEON_CRTC2_CRNT_FRAME);
360}
361
9e5b2af7
PN		 362/* Who ever call radeon_fence_emit should call ring_lock and ask
363 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 364void r100_fence_ring_emit(struct radeon_device *rdev,
365 struct radeon_fence *fence)
366{
9e5b2af7
PN		 367 /* We have to make sure that caches are flushed before
368 * CPU might read something from VRAM. */
369 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
370 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
371 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
372 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 373 /* Wait until IDLE & CLEAN */
4612dc97
AD		 374 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
375 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 376 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
377 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
378 RADEON_HDP_READ_BUFFER_INVALIDATE);
379 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
380 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 381 /* Emit fence sequence & fire IRQ */
382 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
383 radeon_ring_write(rdev, fence->seq);
384 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
385 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
386}
387
771fe6b9
JG		 388int r100_wb_init(struct radeon_device *rdev)
389{
390 int r;
391
392 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 393 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
394 RADEON_GEM_DOMAIN_GTT,
395 &rdev->wb.wb_obj);
771fe6b9 396 if (r) {
4c788679 397 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 398 return r;
399 }
4c788679
JG		 400 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
401 if (unlikely(r != 0))
402 return r;
403 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
404 &rdev->wb.gpu_addr);
771fe6b9 405 if (r) {
4c788679
JG		 406 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
407 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 408 return r;
409 }
4c788679
JG		 410 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
411 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 412 if (r) {
4c788679 413 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 414 return r;
415 }
416 }
9f022ddf
JG		 417 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
418 WREG32(R_00070C_CP_RB_RPTR_ADDR,
419 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
420 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 421 return 0;
422}
423
9f022ddf
JG		 424void r100_wb_disable(struct radeon_device *rdev)
425{
426 WREG32(R_000770_SCRATCH_UMSK, 0);
427}
428
771fe6b9
JG		 429void r100_wb_fini(struct radeon_device *rdev)
430{
4c788679
JG		 431 int r;
432
9f022ddf 433 r100_wb_disable(rdev);
771fe6b9 434 if (rdev->wb.wb_obj) {
4c788679
JG		 435 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
436 if (unlikely(r != 0)) {
437 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
438 return;
439 }
440 radeon_bo_kunmap(rdev->wb.wb_obj);
441 radeon_bo_unpin(rdev->wb.wb_obj);
442 radeon_bo_unreserve(rdev->wb.wb_obj);
443 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 444 rdev->wb.wb = NULL;
445 rdev->wb.wb_obj = NULL;
446 }
447}
448
449int r100_copy_blit(struct radeon_device *rdev,
450 uint64_t src_offset,
451 uint64_t dst_offset,
452 unsigned num_pages,
453 struct radeon_fence *fence)
454{
455 uint32_t cur_pages;
456 uint32_t stride_bytes = PAGE_SIZE;
457 uint32_t pitch;
458 uint32_t stride_pixels;
459 unsigned ndw;
460 int num_loops;
461 int r = 0;
462
463 /* radeon limited to 16k stride */
464 stride_bytes &= 0x3fff;
465 /* radeon pitch is /64 */
466 pitch = stride_bytes / 64;
467 stride_pixels = stride_bytes / 4;
468 num_loops = DIV_ROUND_UP(num_pages, 8191);
469
470 /* Ask for enough room for blit + flush + fence */
471 ndw = 64 + (10 * num_loops);
472 r = radeon_ring_lock(rdev, ndw);
473 if (r) {
474 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
475 return -EINVAL;
476 }
477 while (num_pages > 0) {
478 cur_pages = num_pages;
479 if (cur_pages > 8191) {
480 cur_pages = 8191;
481 }
482 num_pages -= cur_pages;
483
484 /* pages are in Y direction - height
485 page width in X direction - width */
486 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
487 radeon_ring_write(rdev,
488 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
489 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
490 RADEON_GMC_SRC_CLIPPING |
491 RADEON_GMC_DST_CLIPPING |
492 RADEON_GMC_BRUSH_NONE |
493 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
494 RADEON_GMC_SRC_DATATYPE_COLOR |
495 RADEON_ROP3_S |
496 RADEON_DP_SRC_SOURCE_MEMORY |
497 RADEON_GMC_CLR_CMP_CNTL_DIS |
498 RADEON_GMC_WR_MSK_DIS);
499 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
500 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
501 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
502 radeon_ring_write(rdev, 0);
503 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
504 radeon_ring_write(rdev, num_pages);
505 radeon_ring_write(rdev, num_pages);
506 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
507 }
508 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
509 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
510 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
511 radeon_ring_write(rdev,
512 RADEON_WAIT_2D_IDLECLEAN |
513 RADEON_WAIT_HOST_IDLECLEAN |
514 RADEON_WAIT_DMA_GUI_IDLE);
515 if (fence) {
516 r = radeon_fence_emit(rdev, fence);
517 }
518 radeon_ring_unlock_commit(rdev);
519 return r;
520}
521
45600232
JG		 522static int r100_cp_wait_for_idle(struct radeon_device *rdev)
523{
524 unsigned i;
525 u32 tmp;
526
527 for (i = 0; i < rdev->usec_timeout; i++) {
528 tmp = RREG32(R_000E40_RBBM_STATUS);
529 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
530 return 0;
531 }
532 udelay(1);
533 }
534 return -1;
535}
536
771fe6b9
JG		 537void r100_ring_start(struct radeon_device *rdev)
538{
539 int r;
540
541 r = radeon_ring_lock(rdev, 2);
542 if (r) {
543 return;
544 }
545 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
546 radeon_ring_write(rdev,
547 RADEON_ISYNC_ANY2D_IDLE3D |
548 RADEON_ISYNC_ANY3D_IDLE2D |
549 RADEON_ISYNC_WAIT_IDLEGUI |
550 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
551 radeon_ring_unlock_commit(rdev);
552}
553
70967ab9
BH		 554
555/* Load the microcode for the CP */
556static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 557{
70967ab9
BH		 558 struct platform_device *pdev;
559 const char *fw_name = NULL;
560 int err;
771fe6b9 561
70967ab9 562 DRM_DEBUG("\n");
771fe6b9 563
70967ab9
BH		 564 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
565 err = IS_ERR(pdev);
566 if (err) {
567 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
568 return -EINVAL;
569 }
771fe6b9
JG		 570 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
571 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
572 (rdev->family == CHIP_RS200)) {
573 DRM_INFO("Loading R100 Microcode\n");
70967ab9 574 fw_name = FIRMWARE_R100;
771fe6b9
JG		 575 } else if ((rdev->family == CHIP_R200) ||
576 (rdev->family == CHIP_RV250) ||
577 (rdev->family == CHIP_RV280) ||
578 (rdev->family == CHIP_RS300)) {
579 DRM_INFO("Loading R200 Microcode\n");
70967ab9 580 fw_name = FIRMWARE_R200;
771fe6b9
JG		 581 } else if ((rdev->family == CHIP_R300) ||
582 (rdev->family == CHIP_R350) ||
583 (rdev->family == CHIP_RV350) ||
584 (rdev->family == CHIP_RV380) ||
585 (rdev->family == CHIP_RS400) ||
586 (rdev->family == CHIP_RS480)) {
587 DRM_INFO("Loading R300 Microcode\n");
70967ab9 588 fw_name = FIRMWARE_R300;
771fe6b9
JG		 589 } else if ((rdev->family == CHIP_R420) ||
590 (rdev->family == CHIP_R423) ||
591 (rdev->family == CHIP_RV410)) {
592 DRM_INFO("Loading R400 Microcode\n");
70967ab9 593 fw_name = FIRMWARE_R420;
771fe6b9
JG		 594 } else if ((rdev->family == CHIP_RS690) ||
595 (rdev->family == CHIP_RS740)) {
596 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 597 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 598 } else if (rdev->family == CHIP_RS600) {
599 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 600 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 601 } else if ((rdev->family == CHIP_RV515) ||
602 (rdev->family == CHIP_R520) ||
603 (rdev->family == CHIP_RV530) ||
604 (rdev->family == CHIP_R580) ||
605 (rdev->family == CHIP_RV560) ||
606 (rdev->family == CHIP_RV570)) {
607 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 608 fw_name = FIRMWARE_R520;
609 }
610
3ce0a23d 611 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 612 platform_device_unregister(pdev);
613 if (err) {
614 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
615 fw_name);
3ce0a23d 616 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 617 printk(KERN_ERR
618 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 619 rdev->me_fw->size, fw_name);
70967ab9 620 err = -EINVAL;
3ce0a23d
JG		 621 release_firmware(rdev->me_fw);
622 rdev->me_fw = NULL;
70967ab9
BH		 623 }
624 return err;
625}
d4550907 626
70967ab9
BH		 627static void r100_cp_load_microcode(struct radeon_device *rdev)
628{
629 const __be32 *fw_data;
630 int i, size;
631
632 if (r100_gui_wait_for_idle(rdev)) {
633 printk(KERN_WARNING "Failed to wait GUI idle while "
634 "programming pipes. Bad things might happen.\n");
635 }
636
3ce0a23d
JG		 637 if (rdev->me_fw) {
638 size = rdev->me_fw->size / 4;
639 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 640 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
641 for (i = 0; i < size; i += 2) {
642 WREG32(RADEON_CP_ME_RAM_DATAH,
643 be32_to_cpup(&fw_data[i]));
644 WREG32(RADEON_CP_ME_RAM_DATAL,
645 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 646 }
647 }
648}
649
650int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
651{
652 unsigned rb_bufsz;
653 unsigned rb_blksz;
654 unsigned max_fetch;
655 unsigned pre_write_timer;
656 unsigned pre_write_limit;
657 unsigned indirect2_start;
658 unsigned indirect1_start;
659 uint32_t tmp;
660 int r;
661
662 if (r100_debugfs_cp_init(rdev)) {
663 DRM_ERROR("Failed to register debugfs file for CP !\n");
664 }
665 /* Reset CP */
666 tmp = RREG32(RADEON_CP_CSQ_STAT);
667 if ((tmp & (1 << 31))) {
668 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
669 WREG32(RADEON_CP_CSQ_MODE, 0);
670 WREG32(RADEON_CP_CSQ_CNTL, 0);
671 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
672 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
673 mdelay(2);
674 WREG32(RADEON_RBBM_SOFT_RESET, 0);
675 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
676 mdelay(2);
677 tmp = RREG32(RADEON_CP_CSQ_STAT);
678 if ((tmp & (1 << 31))) {
679 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
680 }
681 } else {
682 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
683 }
70967ab9 684
3ce0a23d 685 if (!rdev->me_fw) {
70967ab9
BH		 686 r = r100_cp_init_microcode(rdev);
687 if (r) {
688 DRM_ERROR("Failed to load firmware!\n");
689 return r;
690 }
691 }
692
771fe6b9
JG		 693 /* Align ring size */
694 rb_bufsz = drm_order(ring_size / 8);
695 ring_size = (1 << (rb_bufsz + 1)) * 4;
696 r100_cp_load_microcode(rdev);
697 r = radeon_ring_init(rdev, ring_size);
698 if (r) {
699 return r;
700 }
701 /* Each time the cp read 1024 bytes (16 dword/quadword) update
702 * the rptr copy in system ram */
703 rb_blksz = 9;
704 /* cp will read 128bytes at a time (4 dwords) */
705 max_fetch = 1;
706 rdev->cp.align_mask = 16 - 1;
707 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
708 pre_write_timer = 64;
709 /* Force CP_RB_WPTR write if written more than one time before the
710 * delay expire
711 */
712 pre_write_limit = 0;
713 /* Setup the cp cache like this (cache size is 96 dwords) :
714 * RING 0 to 15
715 * INDIRECT1 16 to 79
716 * INDIRECT2 80 to 95
717 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
719 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
720 * Idea being that most of the gpu cmd will be through indirect1 buffer
721 * so it gets the bigger cache.
722 */
723 indirect2_start = 80;
724 indirect1_start = 16;
725 /* cp setup */
726 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 727 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 728 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
729 REG_SET(RADEON_MAX_FETCH, max_fetch) |
730 RADEON_RB_NO_UPDATE);
d6f28938
AD		 731#ifdef __BIG_ENDIAN
732 tmp |= RADEON_BUF_SWAP_32BIT;
733#endif
734 WREG32(RADEON_CP_RB_CNTL, tmp);
735
771fe6b9
JG		 736 /* Set ring address */
737 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
738 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
739 /* Force read & write ptr to 0 */
771fe6b9
JG		 740 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
741 WREG32(RADEON_CP_RB_RPTR_WR, 0);
742 WREG32(RADEON_CP_RB_WPTR, 0);
743 WREG32(RADEON_CP_RB_CNTL, tmp);
744 udelay(10);
745 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
746 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
9e5786bd
DA		 747 /* protect against crazy HW on resume */
748 rdev->cp.wptr &= rdev->cp.ptr_mask;
771fe6b9
JG		 749 /* Set cp mode to bus mastering & enable cp*/
750 WREG32(RADEON_CP_CSQ_MODE,
751 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
752 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
753 WREG32(0x718, 0);
754 WREG32(0x744, 0x00004D4D);
755 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
756 radeon_ring_start(rdev);
757 r = radeon_ring_test(rdev);
758 if (r) {
759 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
760 return r;
761 }
762 rdev->cp.ready = true;
763 return 0;
764}
765
766void r100_cp_fini(struct radeon_device *rdev)
767{
45600232
JG		 768 if (r100_cp_wait_for_idle(rdev)) {
769 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
770 }
771fe6b9 771 /* Disable ring */
a18d7ea1 772 r100_cp_disable(rdev);
771fe6b9
JG		 773 radeon_ring_fini(rdev);
774 DRM_INFO("radeon: cp finalized\n");
775}
776
777void r100_cp_disable(struct radeon_device *rdev)
778{
779 /* Disable ring */
780 rdev->cp.ready = false;
781 WREG32(RADEON_CP_CSQ_MODE, 0);
782 WREG32(RADEON_CP_CSQ_CNTL, 0);
783 if (r100_gui_wait_for_idle(rdev)) {
784 printk(KERN_WARNING "Failed to wait GUI idle while "
785 "programming pipes. Bad things might happen.\n");
786 }
787}
788
789int r100_cp_reset(struct radeon_device *rdev)
790{
791 uint32_t tmp;
792 bool reinit_cp;
793 int i;
794
795 reinit_cp = rdev->cp.ready;
796 rdev->cp.ready = false;
797 WREG32(RADEON_CP_CSQ_MODE, 0);
798 WREG32(RADEON_CP_CSQ_CNTL, 0);
799 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
800 (void)RREG32(RADEON_RBBM_SOFT_RESET);
801 udelay(200);
802 WREG32(RADEON_RBBM_SOFT_RESET, 0);
803 /* Wait to prevent race in RBBM_STATUS */
804 mdelay(1);
805 for (i = 0; i < rdev->usec_timeout; i++) {
806 tmp = RREG32(RADEON_RBBM_STATUS);
807 if (!(tmp & (1 << 16))) {
808 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
809 tmp);
810 if (reinit_cp) {
811 return r100_cp_init(rdev, rdev->cp.ring_size);
812 }
813 return 0;
814 }
815 DRM_UDELAY(1);
816 }
817 tmp = RREG32(RADEON_RBBM_STATUS);
818 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
819 return -1;
820}
821
3ce0a23d
JG		 822void r100_cp_commit(struct radeon_device *rdev)
823{
824 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
825 (void)RREG32(RADEON_CP_RB_WPTR);
826}
827
771fe6b9
JG		 828
829/*
830 * CS functions
831 */
832int r100_cs_parse_packet0(struct radeon_cs_parser *p,
833 struct radeon_cs_packet *pkt,
068a117c 834 const unsigned *auth, unsigned n,
771fe6b9
JG		 835 radeon_packet0_check_t check)
836{
837 unsigned reg;
838 unsigned i, j, m;
839 unsigned idx;
840 int r;
841
842 idx = pkt->idx + 1;
843 reg = pkt->reg;
068a117c
JG		 844 /* Check that register fall into register range
845 * determined by the number of entry (n) in the
846 * safe register bitmap.
847 */
771fe6b9
JG		 848 if (pkt->one_reg_wr) {
849 if ((reg >> 7) > n) {
850 return -EINVAL;
851 }
852 } else {
853 if (((reg + (pkt->count << 2)) >> 7) > n) {
854 return -EINVAL;
855 }
856 }
857 for (i = 0; i <= pkt->count; i++, idx++) {
858 j = (reg >> 7);
859 m = 1 << ((reg >> 2) & 31);
860 if (auth[j] & m) {
861 r = check(p, pkt, idx, reg);
862 if (r) {
863 return r;
864 }
865 }
866 if (pkt->one_reg_wr) {
867 if (!(auth[j] & m)) {
868 break;
869 }
870 } else {
871 reg += 4;
872 }
873 }
874 return 0;
875}
876
771fe6b9
JG		 877void r100_cs_dump_packet(struct radeon_cs_parser *p,
878 struct radeon_cs_packet *pkt)
879{
771fe6b9
JG		 880 volatile uint32_t *ib;
881 unsigned i;
882 unsigned idx;
883
884 ib = p->ib->ptr;
771fe6b9
JG		 885 idx = pkt->idx;
886 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
887 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
888 }
889}
890
891/**
892 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
893 * @parser: parser structure holding parsing context.
894 * @pkt: where to store packet informations
895 *
896 * Assume that chunk_ib_index is properly set. Will return -EINVAL
897 * if packet is bigger than remaining ib size. or if packets is unknown.
898 **/
899int r100_cs_packet_parse(struct radeon_cs_parser *p,
900 struct radeon_cs_packet *pkt,
901 unsigned idx)
902{
903 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 904 uint32_t header;
771fe6b9
JG		 905
906 if (idx >= ib_chunk->length_dw) {
907 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
908 idx, ib_chunk->length_dw);
909 return -EINVAL;
910 }
513bcb46 911 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 912 pkt->idx = idx;
913 pkt->type = CP_PACKET_GET_TYPE(header);
914 pkt->count = CP_PACKET_GET_COUNT(header);
915 switch (pkt->type) {
916 case PACKET_TYPE0:
917 pkt->reg = CP_PACKET0_GET_REG(header);
918 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
919 break;
920 case PACKET_TYPE3:
921 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
922 break;
923 case PACKET_TYPE2:
924 pkt->count = -1;
925 break;
926 default:
927 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
928 return -EINVAL;
929 }
930 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
931 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
932 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
933 return -EINVAL;
934 }
935 return 0;
936}
937
531369e6
DA		 938/**
939 * r100_cs_packet_next_vline() - parse userspace VLINE packet
940 * @parser: parser structure holding parsing context.
941 *
942 * Userspace sends a special sequence for VLINE waits.
943 * PACKET0 - VLINE_START_END + value
944 * PACKET0 - WAIT_UNTIL +_value
945 * RELOC (P3) - crtc_id in reloc.
946 *
947 * This function parses this and relocates the VLINE START END
948 * and WAIT UNTIL packets to the correct crtc.
949 * It also detects a switched off crtc and nulls out the
950 * wait in that case.
951 */
952int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
953{
531369e6
DA		 954 struct drm_mode_object *obj;
955 struct drm_crtc *crtc;
956 struct radeon_crtc *radeon_crtc;
957 struct radeon_cs_packet p3reloc, waitreloc;
958 int crtc_id;
959 int r;
960 uint32_t header, h_idx, reg;
513bcb46 961 volatile uint32_t *ib;
531369e6 962
513bcb46 963 ib = p->ib->ptr;
531369e6
DA		 964
965 /* parse the wait until */
966 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
967 if (r)
968 return r;
969
970 /* check its a wait until and only 1 count */
971 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
972 waitreloc.count != 0) {
973 DRM_ERROR("vline wait had illegal wait until segment\n");
974 r = -EINVAL;
975 return r;
976 }
977
513bcb46 978 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 979 DRM_ERROR("vline wait had illegal wait until\n");
980 r = -EINVAL;
981 return r;
982 }
983
984 /* jump over the NOP */
90ebd065 985 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 986 if (r)
987 return r;
988
989 h_idx = p->idx - 2;
90ebd065
AD		 990 p->idx += waitreloc.count + 2;
991 p->idx += p3reloc.count + 2;
531369e6 992
513bcb46
DA		 993 header = radeon_get_ib_value(p, h_idx);
994 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 995 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 996 mutex_lock(&p->rdev->ddev->mode_config.mutex);
997 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
998 if (!obj) {
999 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1000 r = -EINVAL;
1001 goto out;
1002 }
1003 crtc = obj_to_crtc(obj);
1004 radeon_crtc = to_radeon_crtc(crtc);
1005 crtc_id = radeon_crtc->crtc_id;
1006
1007 if (!crtc->enabled) {
1008 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1009 ib[h_idx + 2] = PACKET2(0);
1010 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1011 } else if (crtc_id == 1) {
1012 switch (reg) {
1013 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1014 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1015 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1016 break;
1017 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1018 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1019 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1020 break;
1021 default:
1022 DRM_ERROR("unknown crtc reloc\n");
1023 r = -EINVAL;
1024 goto out;
1025 }
513bcb46
DA		 1026 ib[h_idx] = header;
1027 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1028 }
1029out:
1030 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1031 return r;
1032}
1033
771fe6b9
JG		 1034/**
1035 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1036 * @parser: parser structure holding parsing context.
1037 * @data: pointer to relocation data
1038 * @offset_start: starting offset
1039 * @offset_mask: offset mask (to align start offset on)
1040 * @reloc: reloc informations
1041 *
1042 * Check next packet is relocation packet3, do bo validation and compute
1043 * GPU offset using the provided start.
1044 **/
1045int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1046 struct radeon_cs_reloc **cs_reloc)
1047{
771fe6b9
JG		 1048 struct radeon_cs_chunk *relocs_chunk;
1049 struct radeon_cs_packet p3reloc;
1050 unsigned idx;
1051 int r;
1052
1053 if (p->chunk_relocs_idx == -1) {
1054 DRM_ERROR("No relocation chunk !\n");
1055 return -EINVAL;
1056 }
1057 *cs_reloc = NULL;
771fe6b9
JG		 1058 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1059 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1060 if (r) {
1061 return r;
1062 }
1063 p->idx += p3reloc.count + 2;
1064 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1065 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1066 p3reloc.idx);
1067 r100_cs_dump_packet(p, &p3reloc);
1068 return -EINVAL;
1069 }
513bcb46 1070 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1071 if (idx >= relocs_chunk->length_dw) {
1072 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1073 idx, relocs_chunk->length_dw);
1074 r100_cs_dump_packet(p, &p3reloc);
1075 return -EINVAL;
1076 }
1077 /* FIXME: we assume reloc size is 4 dwords */
1078 *cs_reloc = p->relocs_ptr[(idx / 4)];
1079 return 0;
1080}
1081
551ebd83
DA		 1082static int r100_get_vtx_size(uint32_t vtx_fmt)
1083{
1084 int vtx_size;
1085 vtx_size = 2;
1086 /* ordered according to bits in spec */
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1088 vtx_size++;
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1090 vtx_size += 3;
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1092 vtx_size++;
1093 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1094 vtx_size++;
1095 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1096 vtx_size += 3;
1097 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1098 vtx_size++;
1099 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1100 vtx_size++;
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1102 vtx_size += 2;
1103 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1104 vtx_size += 2;
1105 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1106 vtx_size++;
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1108 vtx_size += 2;
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1110 vtx_size++;
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1112 vtx_size += 2;
1113 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1114 vtx_size++;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1116 vtx_size++;
1117 /* blend weight */
1118 if (vtx_fmt & (0x7 << 15))
1119 vtx_size += (vtx_fmt >> 15) & 0x7;
1120 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1121 vtx_size += 3;
1122 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1123 vtx_size += 2;
1124 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1125 vtx_size++;
1126 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1127 vtx_size++;
1128 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1129 vtx_size++;
1130 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1131 vtx_size++;
1132 return vtx_size;
1133}
1134
771fe6b9 1135static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1136 struct radeon_cs_packet *pkt,
1137 unsigned idx, unsigned reg)
771fe6b9 1138{
771fe6b9 1139 struct radeon_cs_reloc *reloc;
551ebd83 1140 struct r100_cs_track *track;
771fe6b9
JG		 1141 volatile uint32_t *ib;
1142 uint32_t tmp;
771fe6b9 1143 int r;
551ebd83 1144 int i, face;
e024e110 1145 u32 tile_flags = 0;
513bcb46 1146 u32 idx_value;
771fe6b9
JG		 1147
1148 ib = p->ib->ptr;
551ebd83
DA		 1149 track = (struct r100_cs_track *)p->track;
1150
513bcb46
DA		 1151 idx_value = radeon_get_ib_value(p, idx);
1152
551ebd83
DA		 1153 switch (reg) {
1154 case RADEON_CRTC_GUI_TRIG_VLINE:
1155 r = r100_cs_packet_parse_vline(p);
1156 if (r) {
1157 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1158 idx, reg);
1159 r100_cs_dump_packet(p, pkt);
1160 return r;
1161 }
1162 break;
771fe6b9
JG		 1163 /* FIXME: only allow PACKET3 blit? easier to check for out of
1164 * range access */
551ebd83
DA		 1165 case RADEON_DST_PITCH_OFFSET:
1166 case RADEON_SRC_PITCH_OFFSET:
1167 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1168 if (r)
1169 return r;
1170 break;
1171 case RADEON_RB3D_DEPTHOFFSET:
1172 r = r100_cs_packet_next_reloc(p, &reloc);
1173 if (r) {
1174 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1175 idx, reg);
1176 r100_cs_dump_packet(p, pkt);
1177 return r;
1178 }
1179 track->zb.robj = reloc->robj;
513bcb46
DA		 1180 track->zb.offset = idx_value;
1181 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1182 break;
1183 case RADEON_RB3D_COLOROFFSET:
1184 r = r100_cs_packet_next_reloc(p, &reloc);
1185 if (r) {
1186 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1187 idx, reg);
1188 r100_cs_dump_packet(p, pkt);
1189 return r;
1190 }
1191 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1192 track->cb[0].offset = idx_value;
1193 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1194 break;
1195 case RADEON_PP_TXOFFSET_0:
1196 case RADEON_PP_TXOFFSET_1:
1197 case RADEON_PP_TXOFFSET_2:
1198 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1199 r = r100_cs_packet_next_reloc(p, &reloc);
1200 if (r) {
1201 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1202 idx, reg);
1203 r100_cs_dump_packet(p, pkt);
1204 return r;
1205 }
513bcb46 1206 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1207 track->textures[i].robj = reloc->robj;
1208 break;
1209 case RADEON_PP_CUBIC_OFFSET_T0_0:
1210 case RADEON_PP_CUBIC_OFFSET_T0_1:
1211 case RADEON_PP_CUBIC_OFFSET_T0_2:
1212 case RADEON_PP_CUBIC_OFFSET_T0_3:
1213 case RADEON_PP_CUBIC_OFFSET_T0_4:
1214 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1215 r = r100_cs_packet_next_reloc(p, &reloc);
1216 if (r) {
1217 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1218 idx, reg);
1219 r100_cs_dump_packet(p, pkt);
1220 return r;
1221 }
513bcb46
DA		 1222 track->textures[0].cube_info[i].offset = idx_value;
1223 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1224 track->textures[0].cube_info[i].robj = reloc->robj;
1225 break;
1226 case RADEON_PP_CUBIC_OFFSET_T1_0:
1227 case RADEON_PP_CUBIC_OFFSET_T1_1:
1228 case RADEON_PP_CUBIC_OFFSET_T1_2:
1229 case RADEON_PP_CUBIC_OFFSET_T1_3:
1230 case RADEON_PP_CUBIC_OFFSET_T1_4:
1231 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1232 r = r100_cs_packet_next_reloc(p, &reloc);
1233 if (r) {
1234 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1235 idx, reg);
1236 r100_cs_dump_packet(p, pkt);
1237 return r;
1238 }
513bcb46
DA		 1239 track->textures[1].cube_info[i].offset = idx_value;
1240 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1241 track->textures[1].cube_info[i].robj = reloc->robj;
1242 break;
1243 case RADEON_PP_CUBIC_OFFSET_T2_0:
1244 case RADEON_PP_CUBIC_OFFSET_T2_1:
1245 case RADEON_PP_CUBIC_OFFSET_T2_2:
1246 case RADEON_PP_CUBIC_OFFSET_T2_3:
1247 case RADEON_PP_CUBIC_OFFSET_T2_4:
1248 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1249 r = r100_cs_packet_next_reloc(p, &reloc);
1250 if (r) {
1251 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1252 idx, reg);
1253 r100_cs_dump_packet(p, pkt);
1254 return r;
1255 }
513bcb46
DA		 1256 track->textures[2].cube_info[i].offset = idx_value;
1257 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1258 track->textures[2].cube_info[i].robj = reloc->robj;
1259 break;
1260 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1261 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1262 break;
1263 case RADEON_RB3D_COLORPITCH:
1264 r = r100_cs_packet_next_reloc(p, &reloc);
1265 if (r) {
1266 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1267 idx, reg);
1268 r100_cs_dump_packet(p, pkt);
1269 return r;
1270 }
e024e110 1271
551ebd83
DA		 1272 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1273 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1274 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1275 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1276
513bcb46 1277 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1278 tmp |= tile_flags;
1279 ib[idx] = tmp;
e024e110 1280
513bcb46 1281 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1282 break;
1283 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1284 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1285 break;
1286 case RADEON_RB3D_CNTL:
513bcb46 1287 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1288 case 7:
1289 case 8:
1290 case 9:
1291 case 11:
1292 case 12:
1293 track->cb[0].cpp = 1;
e024e110 1294 break;
551ebd83
DA		 1295 case 3:
1296 case 4:
1297 case 15:
1298 track->cb[0].cpp = 2;
1299 break;
1300 case 6:
1301 track->cb[0].cpp = 4;
1302 break;
1303 default:
1304 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1305 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1306 return -EINVAL;
1307 }
513bcb46 1308 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1309 break;
1310 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1311 switch (idx_value & 0xf) {
551ebd83
DA		 1312 case 0:
1313 track->zb.cpp = 2;
1314 break;
1315 case 2:
1316 case 3:
1317 case 4:
1318 case 5:
1319 case 9:
1320 case 11:
1321 track->zb.cpp = 4;
17782d99 1322 break;
771fe6b9 1323 default:
771fe6b9
JG		 1324 break;
1325 }
551ebd83
DA		 1326 break;
1327 case RADEON_RB3D_ZPASS_ADDR:
1328 r = r100_cs_packet_next_reloc(p, &reloc);
1329 if (r) {
1330 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1331 idx, reg);
1332 r100_cs_dump_packet(p, pkt);
1333 return r;
1334 }
513bcb46 1335 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1336 break;
1337 case RADEON_PP_CNTL:
1338 {
513bcb46 1339 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1340 for (i = 0; i < track->num_texture; i++)
1341 track->textures[i].enabled = !!(temp & (1 << i));
1342 }
1343 break;
1344 case RADEON_SE_VF_CNTL:
513bcb46 1345 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1346 break;
1347 case RADEON_SE_VTX_FMT:
513bcb46 1348 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1349 break;
1350 case RADEON_PP_TEX_SIZE_0:
1351 case RADEON_PP_TEX_SIZE_1:
1352 case RADEON_PP_TEX_SIZE_2:
1353 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1354 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1355 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1356 break;
1357 case RADEON_PP_TEX_PITCH_0:
1358 case RADEON_PP_TEX_PITCH_1:
1359 case RADEON_PP_TEX_PITCH_2:
1360 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1361 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1362 break;
1363 case RADEON_PP_TXFILTER_0:
1364 case RADEON_PP_TXFILTER_1:
1365 case RADEON_PP_TXFILTER_2:
1366 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1367 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1368 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1369 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1370 if (tmp == 2 || tmp == 6)
1371 track->textures[i].roundup_w = false;
513bcb46 1372 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1373 if (tmp == 2 || tmp == 6)
1374 track->textures[i].roundup_h = false;
1375 break;
1376 case RADEON_PP_TXFORMAT_0:
1377 case RADEON_PP_TXFORMAT_1:
1378 case RADEON_PP_TXFORMAT_2:
1379 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1380 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1381 track->textures[i].use_pitch = 1;
1382 } else {
1383 track->textures[i].use_pitch = 0;
513bcb46
DA		 1384 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1385 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1386 }
513bcb46 1387 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1388 track->textures[i].tex_coord_type = 2;
513bcb46 1389 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1390 case RADEON_TXFORMAT_I8:
1391 case RADEON_TXFORMAT_RGB332:
1392 case RADEON_TXFORMAT_Y8:
1393 track->textures[i].cpp = 1;
1394 break;
1395 case RADEON_TXFORMAT_AI88:
1396 case RADEON_TXFORMAT_ARGB1555:
1397 case RADEON_TXFORMAT_RGB565:
1398 case RADEON_TXFORMAT_ARGB4444:
1399 case RADEON_TXFORMAT_VYUY422:
1400 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1401 case RADEON_TXFORMAT_SHADOW16:
1402 case RADEON_TXFORMAT_LDUDV655:
1403 case RADEON_TXFORMAT_DUDV88:
1404 track->textures[i].cpp = 2;
771fe6b9 1405 break;
551ebd83
DA		 1406 case RADEON_TXFORMAT_ARGB8888:
1407 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1408 case RADEON_TXFORMAT_SHADOW32:
1409 case RADEON_TXFORMAT_LDUDUV8888:
1410 track->textures[i].cpp = 4;
1411 break;
d785d78b
DA		 1412 case RADEON_TXFORMAT_DXT1:
1413 track->textures[i].cpp = 1;
1414 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1415 break;
1416 case RADEON_TXFORMAT_DXT23:
1417 case RADEON_TXFORMAT_DXT45:
1418 track->textures[i].cpp = 1;
1419 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1420 break;
551ebd83 1421 }
513bcb46
DA		 1422 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1423 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1424 break;
1425 case RADEON_PP_CUBIC_FACES_0:
1426 case RADEON_PP_CUBIC_FACES_1:
1427 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1428 tmp = idx_value;
551ebd83
DA		 1429 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1430 for (face = 0; face < 4; face++) {
1431 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1432 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1433 }
551ebd83
DA		 1434 break;
1435 default:
1436 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1437 reg, idx);
1438 return -EINVAL;
771fe6b9
JG		 1439 }
1440 return 0;
1441}
1442
068a117c
JG		 1443int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1444 struct radeon_cs_packet *pkt,
4c788679 1445 struct radeon_bo *robj)
068a117c 1446{
068a117c 1447 unsigned idx;
513bcb46 1448 u32 value;
068a117c 1449 idx = pkt->idx + 1;
513bcb46 1450 value = radeon_get_ib_value(p, idx + 2);
4c788679 1451 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1452 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1453 "(need %u have %lu) !\n",
513bcb46 1454 value + 1,
4c788679 1455 radeon_bo_size(robj));
068a117c
JG		 1456 return -EINVAL;
1457 }
1458 return 0;
1459}
1460
771fe6b9
JG		 1461static int r100_packet3_check(struct radeon_cs_parser *p,
1462 struct radeon_cs_packet *pkt)
1463{
771fe6b9 1464 struct radeon_cs_reloc *reloc;
551ebd83 1465 struct r100_cs_track *track;
771fe6b9 1466 unsigned idx;
771fe6b9
JG		 1467 volatile uint32_t *ib;
1468 int r;
1469
1470 ib = p->ib->ptr;
771fe6b9 1471 idx = pkt->idx + 1;
551ebd83 1472 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1473 switch (pkt->opcode) {
1474 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1475 r = r100_packet3_load_vbpntr(p, pkt, idx);
1476 if (r)
1477 return r;
771fe6b9
JG		 1478 break;
1479 case PACKET3_INDX_BUFFER:
1480 r = r100_cs_packet_next_reloc(p, &reloc);
1481 if (r) {
1482 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1483 r100_cs_dump_packet(p, pkt);
1484 return r;
1485 }
513bcb46 1486 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1487 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1488 if (r) {
1489 return r;
1490 }
771fe6b9
JG		 1491 break;
1492 case 0x23:
771fe6b9
JG		 1493 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1494 r = r100_cs_packet_next_reloc(p, &reloc);
1495 if (r) {
1496 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1497 r100_cs_dump_packet(p, pkt);
1498 return r;
1499 }
513bcb46 1500 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1501 track->num_arrays = 1;
513bcb46 1502 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1503
1504 track->arrays[0].robj = reloc->robj;
1505 track->arrays[0].esize = track->vtx_size;
1506
513bcb46 1507 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1508
513bcb46 1509 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1510 track->immd_dwords = pkt->count - 1;
1511 r = r100_cs_track_check(p->rdev, track);
1512 if (r)
1513 return r;
771fe6b9
JG		 1514 break;
1515 case PACKET3_3D_DRAW_IMMD:
513bcb46 1516 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1517 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1518 return -EINVAL;
1519 }
cf57fc7a 1520 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1521 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1522 track->immd_dwords = pkt->count - 1;
1523 r = r100_cs_track_check(p->rdev, track);
1524 if (r)
1525 return r;
1526 break;
771fe6b9
JG		 1527 /* triggers drawing using in-packet vertex data */
1528 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1529 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1530 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1531 return -EINVAL;
1532 }
513bcb46 1533 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1534 track->immd_dwords = pkt->count;
1535 r = r100_cs_track_check(p->rdev, track);
1536 if (r)
1537 return r;
1538 break;
771fe6b9
JG		 1539 /* triggers drawing using in-packet vertex data */
1540 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1541 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1542 r = r100_cs_track_check(p->rdev, track);
1543 if (r)
1544 return r;
1545 break;
771fe6b9
JG		 1546 /* triggers drawing of vertex buffers setup elsewhere */
1547 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1548 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1549 r = r100_cs_track_check(p->rdev, track);
1550 if (r)
1551 return r;
1552 break;
771fe6b9
JG		 1553 /* triggers drawing using indices to vertex buffer */
1554 case PACKET3_3D_DRAW_VBUF:
513bcb46 1555 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1556 r = r100_cs_track_check(p->rdev, track);
1557 if (r)
1558 return r;
1559 break;
771fe6b9
JG		 1560 /* triggers drawing of vertex buffers setup elsewhere */
1561 case PACKET3_3D_DRAW_INDX:
513bcb46 1562 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1563 r = r100_cs_track_check(p->rdev, track);
1564 if (r)
1565 return r;
1566 break;
771fe6b9
JG		 1567 /* triggers drawing using indices to vertex buffer */
1568 case PACKET3_NOP:
1569 break;
1570 default:
1571 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1572 return -EINVAL;
1573 }
1574 return 0;
1575}
1576
1577int r100_cs_parse(struct radeon_cs_parser *p)
1578{
1579 struct radeon_cs_packet pkt;
9f022ddf 1580 struct r100_cs_track *track;
771fe6b9
JG		 1581 int r;
1582
9f022ddf
JG		 1583 track = kzalloc(sizeof(*track), GFP_KERNEL);
1584 r100_cs_track_clear(p->rdev, track);
1585 p->track = track;
771fe6b9
JG		 1586 do {
1587 r = r100_cs_packet_parse(p, &pkt, p->idx);
1588 if (r) {
1589 return r;
1590 }
1591 p->idx += pkt.count + 2;
1592 switch (pkt.type) {
068a117c 1593 case PACKET_TYPE0:
551ebd83
DA		 1594 if (p->rdev->family >= CHIP_R200)
1595 r = r100_cs_parse_packet0(p, &pkt,
1596 p->rdev->config.r100.reg_safe_bm,
1597 p->rdev->config.r100.reg_safe_bm_size,
1598 &r200_packet0_check);
1599 else
1600 r = r100_cs_parse_packet0(p, &pkt,
1601 p->rdev->config.r100.reg_safe_bm,
1602 p->rdev->config.r100.reg_safe_bm_size,
1603 &r100_packet0_check);
068a117c
JG		 1604 break;
1605 case PACKET_TYPE2:
1606 break;
1607 case PACKET_TYPE3:
1608 r = r100_packet3_check(p, &pkt);
1609 break;
1610 default:
1611 DRM_ERROR("Unknown packet type %d !\n",
1612 pkt.type);
1613 return -EINVAL;
771fe6b9
JG		 1614 }
1615 if (r) {
1616 return r;
1617 }
1618 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1619 return 0;
1620}
1621
1622
1623/*
1624 * Global GPU functions
1625 */
1626void r100_errata(struct radeon_device *rdev)
1627{
1628 rdev->pll_errata = 0;
1629
1630 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1631 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1632 }
1633
1634 if (rdev->family == CHIP_RV100 ||
1635 rdev->family == CHIP_RS100 ||
1636 rdev->family == CHIP_RS200) {
1637 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1638 }
1639}
1640
1641/* Wait for vertical sync on primary CRTC */
1642void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1643{
1644 uint32_t crtc_gen_cntl, tmp;
1645 int i;
1646
1647 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1648 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1649 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1650 return;
1651 }
1652 /* Clear the CRTC_VBLANK_SAVE bit */
1653 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1654 for (i = 0; i < rdev->usec_timeout; i++) {
1655 tmp = RREG32(RADEON_CRTC_STATUS);
1656 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1657 return;
1658 }
1659 DRM_UDELAY(1);
1660 }
1661}
1662
1663/* Wait for vertical sync on secondary CRTC */
1664void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1665{
1666 uint32_t crtc2_gen_cntl, tmp;
1667 int i;
1668
1669 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1670 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1671 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1672 return;
1673
1674 /* Clear the CRTC_VBLANK_SAVE bit */
1675 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1676 for (i = 0; i < rdev->usec_timeout; i++) {
1677 tmp = RREG32(RADEON_CRTC2_STATUS);
1678 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1679 return;
1680 }
1681 DRM_UDELAY(1);
1682 }
1683}
1684
1685int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1686{
1687 unsigned i;
1688 uint32_t tmp;
1689
1690 for (i = 0; i < rdev->usec_timeout; i++) {
1691 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1692 if (tmp >= n) {
1693 return 0;
1694 }
1695 DRM_UDELAY(1);
1696 }
1697 return -1;
1698}
1699
1700int r100_gui_wait_for_idle(struct radeon_device *rdev)
1701{
1702 unsigned i;
1703 uint32_t tmp;
1704
1705 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1706 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1707 " Bad things might happen.\n");
1708 }
1709 for (i = 0; i < rdev->usec_timeout; i++) {
1710 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1711 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1712 return 0;
1713 }
1714 DRM_UDELAY(1);
1715 }
1716 return -1;
1717}
1718
1719int r100_mc_wait_for_idle(struct radeon_device *rdev)
1720{
1721 unsigned i;
1722 uint32_t tmp;
1723
1724 for (i = 0; i < rdev->usec_timeout; i++) {
1725 /* read MC_STATUS */
4612dc97
AD		 1726 tmp = RREG32(RADEON_MC_STATUS);
1727 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1728 return 0;
1729 }
1730 DRM_UDELAY(1);
1731 }
1732 return -1;
1733}
1734
1735void r100_gpu_init(struct radeon_device *rdev)
1736{
1737 /* TODO: anythings to do here ? pipes ? */
1738 r100_hdp_reset(rdev);
1739}
1740
1741void r100_hdp_reset(struct radeon_device *rdev)
1742{
1743 uint32_t tmp;
1744
1745 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1746 tmp |= (7 << 28);
1747 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1748 (void)RREG32(RADEON_HOST_PATH_CNTL);
1749 udelay(200);
1750 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1751 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1752 (void)RREG32(RADEON_HOST_PATH_CNTL);
1753}
1754
1755int r100_rb2d_reset(struct radeon_device *rdev)
1756{
1757 uint32_t tmp;
1758 int i;
1759
1760 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1761 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1762 udelay(200);
1763 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1764 /* Wait to prevent race in RBBM_STATUS */
1765 mdelay(1);
1766 for (i = 0; i < rdev->usec_timeout; i++) {
1767 tmp = RREG32(RADEON_RBBM_STATUS);
1768 if (!(tmp & (1 << 26))) {
1769 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1770 tmp);
1771 return 0;
1772 }
1773 DRM_UDELAY(1);
1774 }
1775 tmp = RREG32(RADEON_RBBM_STATUS);
1776 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1777 return -1;
1778}
1779
1780int r100_gpu_reset(struct radeon_device *rdev)
1781{
1782 uint32_t status;
1783
1784 /* reset order likely matter */
1785 status = RREG32(RADEON_RBBM_STATUS);
1786 /* reset HDP */
1787 r100_hdp_reset(rdev);
1788 /* reset rb2d */
1789 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1790 r100_rb2d_reset(rdev);
1791 }
1792 /* TODO: reset 3D engine */
1793 /* reset CP */
1794 status = RREG32(RADEON_RBBM_STATUS);
1795 if (status & (1 << 16)) {
1796 r100_cp_reset(rdev);
1797 }
1798 /* Check if GPU is idle */
1799 status = RREG32(RADEON_RBBM_STATUS);
4612dc97 1800 if (status & RADEON_RBBM_ACTIVE) {
771fe6b9
JG		 1801 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1802 return -1;
1803 }
1804 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1805 return 0;
1806}
1807
92cde00c
AD		 1808void r100_set_common_regs(struct radeon_device *rdev)
1809{
2739d49c
AD		 1810 struct drm_device *dev = rdev->ddev;
1811 bool force_dac2 = false;
1812
92cde00c
AD		 1813 /* set these so they don't interfere with anything */
1814 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1815 WREG32(RADEON_SUBPIC_CNTL, 0);
1816 WREG32(RADEON_VIPH_CONTROL, 0);
1817 WREG32(RADEON_I2C_CNTL_1, 0);
1818 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1819 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1820 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 1821
1822 /* always set up dac2 on rn50 and some rv100 as lots
1823 * of servers seem to wire it up to a VGA port but
1824 * don't report it in the bios connector
1825 * table.
1826 */
1827 switch (dev->pdev->device) {
1828 /* RN50 */
1829 case 0x515e:
1830 case 0x5969:
1831 force_dac2 = true;
1832 break;
1833 /* RV100*/
1834 case 0x5159:
1835 case 0x515a:
1836 /* DELL triple head servers */
1837 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1838 ((dev->pdev->subsystem_device == 0x016c) ||
1839 (dev->pdev->subsystem_device == 0x016d) ||
1840 (dev->pdev->subsystem_device == 0x016e) ||
1841 (dev->pdev->subsystem_device == 0x016f) ||
1842 (dev->pdev->subsystem_device == 0x0170) ||
1843 (dev->pdev->subsystem_device == 0x017d) ||
1844 (dev->pdev->subsystem_device == 0x017e) ||
1845 (dev->pdev->subsystem_device == 0x0183) ||
1846 (dev->pdev->subsystem_device == 0x018a) ||
1847 (dev->pdev->subsystem_device == 0x019a)))
1848 force_dac2 = true;
1849 break;
1850 }
1851
1852 if (force_dac2) {
1853 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1854 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1855 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1856
1857 /* For CRT on DAC2, don't turn it on if BIOS didn't
1858 enable it, even it's detected.
1859 */
1860
1861 /* force it to crtc0 */
1862 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1863 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1864 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1865
1866 /* set up the TV DAC */
1867 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1868 RADEON_TV_DAC_STD_MASK |
1869 RADEON_TV_DAC_RDACPD |
1870 RADEON_TV_DAC_GDACPD |
1871 RADEON_TV_DAC_BDACPD |
1872 RADEON_TV_DAC_BGADJ_MASK |
1873 RADEON_TV_DAC_DACADJ_MASK);
1874 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1875 RADEON_TV_DAC_NHOLD |
1876 RADEON_TV_DAC_STD_PS2 |
1877 (0x58 << 16));
1878
1879 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1880 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1881 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1882 }
92cde00c 1883}
771fe6b9
JG		 1884
1885/*
1886 * VRAM info
1887 */
1888static void r100_vram_get_type(struct radeon_device *rdev)
1889{
1890 uint32_t tmp;
1891
1892 rdev->mc.vram_is_ddr = false;
1893 if (rdev->flags & RADEON_IS_IGP)
1894 rdev->mc.vram_is_ddr = true;
1895 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1896 rdev->mc.vram_is_ddr = true;
1897 if ((rdev->family == CHIP_RV100) ||
1898 (rdev->family == CHIP_RS100) ||
1899 (rdev->family == CHIP_RS200)) {
1900 tmp = RREG32(RADEON_MEM_CNTL);
1901 if (tmp & RV100_HALF_MODE) {
1902 rdev->mc.vram_width = 32;
1903 } else {
1904 rdev->mc.vram_width = 64;
1905 }
1906 if (rdev->flags & RADEON_SINGLE_CRTC) {
1907 rdev->mc.vram_width /= 4;
1908 rdev->mc.vram_is_ddr = true;
1909 }
1910 } else if (rdev->family <= CHIP_RV280) {
1911 tmp = RREG32(RADEON_MEM_CNTL);
1912 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1913 rdev->mc.vram_width = 128;
1914 } else {
1915 rdev->mc.vram_width = 64;
1916 }
1917 } else {
1918 /* newer IGPs */
1919 rdev->mc.vram_width = 128;
1920 }
1921}
1922
2a0f8918 1923static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1924{
2a0f8918
DA		 1925 u32 aper_size;
1926 u8 byte;
1927
1928 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1929
1930 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1931 * that is has the 2nd generation multifunction PCI interface
1932 */
1933 if (rdev->family == CHIP_RV280 ||
1934 rdev->family >= CHIP_RV350) {
1935 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1936 ~RADEON_HDP_APER_CNTL);
1937 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1938 return aper_size * 2;
1939 }
1940
1941 /* Older cards have all sorts of funny issues to deal with. First
1942 * check if it's a multifunction card by reading the PCI config
1943 * header type... Limit those to one aperture size
1944 */
1945 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1946 if (byte & 0x80) {
1947 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1948 DRM_INFO("Limiting VRAM to one aperture\n");
1949 return aper_size;
1950 }
1951
1952 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1953 * have set it up. We don't write this as it's broken on some ASICs but
1954 * we expect the BIOS to have done the right thing (might be too optimistic...)
1955 */
1956 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1957 return aper_size * 2;
1958 return aper_size;
1959}
1960
1961void r100_vram_init_sizes(struct radeon_device *rdev)
1962{
1963 u64 config_aper_size;
2a0f8918 1964
d594e46a 1965 /* work out accessible VRAM */
d594e46a
JG		 1966 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1967 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3
JG		 1968 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1969 /* FIXME we don't use the second aperture yet when we could use it */
1970 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1971 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 1972 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1973 if (rdev->flags & RADEON_IS_IGP) {
1974 uint32_t tom;
1975 /* read NB_TOM to get the amount of ram stolen for the GPU */
1976 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1977 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 1978 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1979 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1980 } else {
7a50f01a 1981 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1982 /* Some production boards of m6 will report 0
1983 * if it's 8 MB
1984 */
7a50f01a
DA		 1985 if (rdev->mc.real_vram_size == 0) {
1986 rdev->mc.real_vram_size = 8192 * 1024;
1987 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1988 }
d594e46a
JG		 1989 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1990 * Novell bug 204882 + along with lots of ubuntu ones
1991 */
7a50f01a
DA		 1992 if (config_aper_size > rdev->mc.real_vram_size)
1993 rdev->mc.mc_vram_size = config_aper_size;
1994 else
1995 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1996 }
d594e46a
JG		 1997 /* FIXME remove this once we support unmappable VRAM */
1998 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
7a50f01a 1999 rdev->mc.mc_vram_size = rdev->mc.aper_size;
7a50f01a 2000 rdev->mc.real_vram_size = rdev->mc.aper_size;
d594e46a 2001 }
2a0f8918
DA		 2002}
2003
28d52043
DA		 2004void r100_vga_set_state(struct radeon_device *rdev, bool state)
2005{
2006 uint32_t temp;
2007
2008 temp = RREG32(RADEON_CONFIG_CNTL);
2009 if (state == false) {
2010 temp &= ~(1<<8);
2011 temp |= (1<<9);
2012 } else {
2013 temp &= ~(1<<9);
2014 }
2015 WREG32(RADEON_CONFIG_CNTL, temp);
2016}
2017
d594e46a 2018void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2019{
d594e46a 2020 u64 base;
2a0f8918 2021
d594e46a 2022 r100_vram_get_type(rdev);
2a0f8918 2023 r100_vram_init_sizes(rdev);
d594e46a
JG		 2024 base = rdev->mc.aper_base;
2025 if (rdev->flags & RADEON_IS_IGP)
2026 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2027 radeon_vram_location(rdev, &rdev->mc, base);
2028 if (!(rdev->flags & RADEON_IS_AGP))
2029 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2030 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2031}
2032
2033
2034/*
2035 * Indirect registers accessor
2036 */
2037void r100_pll_errata_after_index(struct radeon_device *rdev)
2038{
2039 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2040 return;
2041 }
2042 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2043 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2044}
2045
2046static void r100_pll_errata_after_data(struct radeon_device *rdev)
2047{
2048 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2049 * or the chip could hang on a subsequent access
2050 */
2051 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2052 udelay(5000);
2053 }
2054
2055 /* This function is required to workaround a hardware bug in some (all?)
2056 * revisions of the R300. This workaround should be called after every
2057 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2058 * may not be correct.
2059 */
2060 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2061 uint32_t save, tmp;
2062
2063 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2064 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2065 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2066 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2067 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2068 }
2069}
2070
2071uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2072{
2073 uint32_t data;
2074
2075 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2076 r100_pll_errata_after_index(rdev);
2077 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2078 r100_pll_errata_after_data(rdev);
2079 return data;
2080}
2081
2082void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2083{
2084 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2085 r100_pll_errata_after_index(rdev);
2086 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2087 r100_pll_errata_after_data(rdev);
2088}
2089
d4550907 2090void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2091{
551ebd83
DA		 2092 if (ASIC_IS_RN50(rdev)) {
2093 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2094 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2095 } else if (rdev->family < CHIP_R200) {
2096 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2097 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2098 } else {
d4550907 2099 r200_set_safe_registers(rdev);
551ebd83 2100 }
068a117c
JG		 2101}
2102
771fe6b9
JG		 2103/*
2104 * Debugfs info
2105 */
2106#if defined(CONFIG_DEBUG_FS)
2107static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2108{
2109 struct drm_info_node *node = (struct drm_info_node *) m->private;
2110 struct drm_device *dev = node->minor->dev;
2111 struct radeon_device *rdev = dev->dev_private;
2112 uint32_t reg, value;
2113 unsigned i;
2114
2115 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2116 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2117 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2118 for (i = 0; i < 64; i++) {
2119 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2120 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2121 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2122 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2123 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2124 }
2125 return 0;
2126}
2127
2128static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2129{
2130 struct drm_info_node *node = (struct drm_info_node *) m->private;
2131 struct drm_device *dev = node->minor->dev;
2132 struct radeon_device *rdev = dev->dev_private;
2133 uint32_t rdp, wdp;
2134 unsigned count, i, j;
2135
2136 radeon_ring_free_size(rdev);
2137 rdp = RREG32(RADEON_CP_RB_RPTR);
2138 wdp = RREG32(RADEON_CP_RB_WPTR);
2139 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2140 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2141 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2142 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2143 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2144 seq_printf(m, "%u dwords in ring\n", count);
2145 for (j = 0; j <= count; j++) {
2146 i = (rdp + j) & rdev->cp.ptr_mask;
2147 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2148 }
2149 return 0;
2150}
2151
2152
2153static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2154{
2155 struct drm_info_node *node = (struct drm_info_node *) m->private;
2156 struct drm_device *dev = node->minor->dev;
2157 struct radeon_device *rdev = dev->dev_private;
2158 uint32_t csq_stat, csq2_stat, tmp;
2159 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2160 unsigned i;
2161
2162 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2163 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2164 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2165 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2166 r_rptr = (csq_stat >> 0) & 0x3ff;
2167 r_wptr = (csq_stat >> 10) & 0x3ff;
2168 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2169 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2170 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2171 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2172 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2173 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2174 seq_printf(m, "Ring rptr %u\n", r_rptr);
2175 seq_printf(m, "Ring wptr %u\n", r_wptr);
2176 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2177 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2178 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2179 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2180 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2181 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2182 seq_printf(m, "Ring fifo:\n");
2183 for (i = 0; i < 256; i++) {
2184 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2185 tmp = RREG32(RADEON_CP_CSQ_DATA);
2186 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2187 }
2188 seq_printf(m, "Indirect1 fifo:\n");
2189 for (i = 256; i <= 512; i++) {
2190 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2191 tmp = RREG32(RADEON_CP_CSQ_DATA);
2192 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2193 }
2194 seq_printf(m, "Indirect2 fifo:\n");
2195 for (i = 640; i < ib1_wptr; i++) {
2196 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2197 tmp = RREG32(RADEON_CP_CSQ_DATA);
2198 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2199 }
2200 return 0;
2201}
2202
2203static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2204{
2205 struct drm_info_node *node = (struct drm_info_node *) m->private;
2206 struct drm_device *dev = node->minor->dev;
2207 struct radeon_device *rdev = dev->dev_private;
2208 uint32_t tmp;
2209
2210 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2211 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2212 tmp = RREG32(RADEON_MC_FB_LOCATION);
2213 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2214 tmp = RREG32(RADEON_BUS_CNTL);
2215 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2216 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2217 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2218 tmp = RREG32(RADEON_AGP_BASE);
2219 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2220 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2221 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2222 tmp = RREG32(0x01D0);
2223 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2224 tmp = RREG32(RADEON_AIC_LO_ADDR);
2225 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2226 tmp = RREG32(RADEON_AIC_HI_ADDR);
2227 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2228 tmp = RREG32(0x01E4);
2229 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2230 return 0;
2231}
2232
2233static struct drm_info_list r100_debugfs_rbbm_list[] = {
2234 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2235};
2236
2237static struct drm_info_list r100_debugfs_cp_list[] = {
2238 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2239 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2240};
2241
2242static struct drm_info_list r100_debugfs_mc_info_list[] = {
2243 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2244};
2245#endif
2246
2247int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2248{
2249#if defined(CONFIG_DEBUG_FS)
2250 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2251#else
2252 return 0;
2253#endif
2254}
2255
2256int r100_debugfs_cp_init(struct radeon_device *rdev)
2257{
2258#if defined(CONFIG_DEBUG_FS)
2259 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2260#else
2261 return 0;
2262#endif
2263}
2264
2265int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2266{
2267#if defined(CONFIG_DEBUG_FS)
2268 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2269#else
2270 return 0;
2271#endif
2272}
e024e110
DA		 2273
2274int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2275 uint32_t tiling_flags, uint32_t pitch,
2276 uint32_t offset, uint32_t obj_size)
2277{
2278 int surf_index = reg * 16;
2279 int flags = 0;
2280
2281 /* r100/r200 divide by 16 */
2282 if (rdev->family < CHIP_R300)
2283 flags = pitch / 16;
2284 else
2285 flags = pitch / 8;
2286
2287 if (rdev->family <= CHIP_RS200) {
2288 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2289 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2290 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2291 if (tiling_flags & RADEON_TILING_MACRO)
2292 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2293 } else if (rdev->family <= CHIP_RV280) {
2294 if (tiling_flags & (RADEON_TILING_MACRO))
2295 flags |= R200_SURF_TILE_COLOR_MACRO;
2296 if (tiling_flags & RADEON_TILING_MICRO)
2297 flags |= R200_SURF_TILE_COLOR_MICRO;
2298 } else {
2299 if (tiling_flags & RADEON_TILING_MACRO)
2300 flags |= R300_SURF_TILE_MACRO;
2301 if (tiling_flags & RADEON_TILING_MICRO)
2302 flags |= R300_SURF_TILE_MICRO;
2303 }
2304
c88f9f0c
MD		 2305 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2306 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2307 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2308 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2309
e024e110
DA		 2310 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2311 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2312 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2313 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2314 return 0;
2315}
2316
2317void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2318{
2319 int surf_index = reg * 16;
2320 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2321}
c93bb85b
JG		 2322
2323void r100_bandwidth_update(struct radeon_device *rdev)
2324{
2325 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2326 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2327 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2328 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2329 fixed20_12 memtcas_ff[8] = {
2330 fixed_init(1),
2331 fixed_init(2),
2332 fixed_init(3),
2333 fixed_init(0),
2334 fixed_init_half(1),
2335 fixed_init_half(2),
2336 fixed_init(0),
2337 };
2338 fixed20_12 memtcas_rs480_ff[8] = {
2339 fixed_init(0),
2340 fixed_init(1),
2341 fixed_init(2),
2342 fixed_init(3),
2343 fixed_init(0),
2344 fixed_init_half(1),
2345 fixed_init_half(2),
2346 fixed_init_half(3),
2347 };
2348 fixed20_12 memtcas2_ff[8] = {
2349 fixed_init(0),
2350 fixed_init(1),
2351 fixed_init(2),
2352 fixed_init(3),
2353 fixed_init(4),
2354 fixed_init(5),
2355 fixed_init(6),
2356 fixed_init(7),
2357 };
2358 fixed20_12 memtrbs[8] = {
2359 fixed_init(1),
2360 fixed_init_half(1),
2361 fixed_init(2),
2362 fixed_init_half(2),
2363 fixed_init(3),
2364 fixed_init_half(3),
2365 fixed_init(4),
2366 fixed_init_half(4)
2367 };
2368 fixed20_12 memtrbs_r4xx[8] = {
2369 fixed_init(4),
2370 fixed_init(5),
2371 fixed_init(6),
2372 fixed_init(7),
2373 fixed_init(8),
2374 fixed_init(9),
2375 fixed_init(10),
2376 fixed_init(11)
2377 };
2378 fixed20_12 min_mem_eff;
2379 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2380 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2381 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2382 disp_drain_rate2, read_return_rate;
2383 fixed20_12 time_disp1_drop_priority;
2384 int c;
2385 int cur_size = 16; /* in octawords */
2386 int critical_point = 0, critical_point2;
2387/* uint32_t read_return_rate, time_disp1_drop_priority; */
2388 int stop_req, max_stop_req;
2389 struct drm_display_mode *mode1 = NULL;
2390 struct drm_display_mode *mode2 = NULL;
2391 uint32_t pixel_bytes1 = 0;
2392 uint32_t pixel_bytes2 = 0;
2393
f46c0120
AD		 2394 radeon_update_display_priority(rdev);
2395
c93bb85b
JG		 2396 if (rdev->mode_info.crtcs[0]->base.enabled) {
2397 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2398 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2399 }
dfee5614
DA		 2400 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2401 if (rdev->mode_info.crtcs[1]->base.enabled) {
2402 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2403 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2404 }
c93bb85b
JG		 2405 }
2406
2407 min_mem_eff.full = rfixed_const_8(0);
2408 /* get modes */
2409 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2410 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2411 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2412 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2413 /* check crtc enables */
2414 if (mode2)
2415 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2416 if (mode1)
2417 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2418 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2419 }
2420
2421 /*
2422 * determine is there is enough bw for current mode
2423 */
f47299c5
AD		 2424 sclk_ff = rdev->pm.sclk;
2425 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2426
2427 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2428 temp_ff.full = rfixed_const(temp);
2429 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2430
2431 pix_clk.full = 0;
2432 pix_clk2.full = 0;
2433 peak_disp_bw.full = 0;
2434 if (mode1) {
2435 temp_ff.full = rfixed_const(1000);
2436 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2437 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2438 temp_ff.full = rfixed_const(pixel_bytes1);
2439 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2440 }
2441 if (mode2) {
2442 temp_ff.full = rfixed_const(1000);
2443 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2444 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2445 temp_ff.full = rfixed_const(pixel_bytes2);
2446 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2447 }
2448
2449 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2450 if (peak_disp_bw.full >= mem_bw.full) {
2451 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2452 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2453 }
2454
2455 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2456 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2457 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2458 mem_trcd = ((temp >> 2) & 0x3) + 1;
2459 mem_trp = ((temp & 0x3)) + 1;
2460 mem_tras = ((temp & 0x70) >> 4) + 1;
2461 } else if (rdev->family == CHIP_R300 ||
2462 rdev->family == CHIP_R350) { /* r300, r350 */
2463 mem_trcd = (temp & 0x7) + 1;
2464 mem_trp = ((temp >> 8) & 0x7) + 1;
2465 mem_tras = ((temp >> 11) & 0xf) + 4;
2466 } else if (rdev->family == CHIP_RV350 ||
2467 rdev->family <= CHIP_RV380) {
2468 /* rv3x0 */
2469 mem_trcd = (temp & 0x7) + 3;
2470 mem_trp = ((temp >> 8) & 0x7) + 3;
2471 mem_tras = ((temp >> 11) & 0xf) + 6;
2472 } else if (rdev->family == CHIP_R420 ||
2473 rdev->family == CHIP_R423 ||
2474 rdev->family == CHIP_RV410) {
2475 /* r4xx */
2476 mem_trcd = (temp & 0xf) + 3;
2477 if (mem_trcd > 15)
2478 mem_trcd = 15;
2479 mem_trp = ((temp >> 8) & 0xf) + 3;
2480 if (mem_trp > 15)
2481 mem_trp = 15;
2482 mem_tras = ((temp >> 12) & 0x1f) + 6;
2483 if (mem_tras > 31)
2484 mem_tras = 31;
2485 } else { /* RV200, R200 */
2486 mem_trcd = (temp & 0x7) + 1;
2487 mem_trp = ((temp >> 8) & 0x7) + 1;
2488 mem_tras = ((temp >> 12) & 0xf) + 4;
2489 }
2490 /* convert to FF */
2491 trcd_ff.full = rfixed_const(mem_trcd);
2492 trp_ff.full = rfixed_const(mem_trp);
2493 tras_ff.full = rfixed_const(mem_tras);
2494
2495 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2496 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2497 data = (temp & (7 << 20)) >> 20;
2498 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2499 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2500 tcas_ff = memtcas_rs480_ff[data];
2501 else
2502 tcas_ff = memtcas_ff[data];
2503 } else
2504 tcas_ff = memtcas2_ff[data];
2505
2506 if (rdev->family == CHIP_RS400 ||
2507 rdev->family == CHIP_RS480) {
2508 /* extra cas latency stored in bits 23-25 0-4 clocks */
2509 data = (temp >> 23) & 0x7;
2510 if (data < 5)
2511 tcas_ff.full += rfixed_const(data);
2512 }
2513
2514 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2515 /* on the R300, Tcas is included in Trbs.
2516 */
2517 temp = RREG32(RADEON_MEM_CNTL);
2518 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2519 if (data == 1) {
2520 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2521 temp = RREG32(R300_MC_IND_INDEX);
2522 temp &= ~R300_MC_IND_ADDR_MASK;
2523 temp |= R300_MC_READ_CNTL_CD_mcind;
2524 WREG32(R300_MC_IND_INDEX, temp);
2525 temp = RREG32(R300_MC_IND_DATA);
2526 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2527 } else {
2528 temp = RREG32(R300_MC_READ_CNTL_AB);
2529 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2530 }
2531 } else {
2532 temp = RREG32(R300_MC_READ_CNTL_AB);
2533 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2534 }
2535 if (rdev->family == CHIP_RV410 ||
2536 rdev->family == CHIP_R420 ||
2537 rdev->family == CHIP_R423)
2538 trbs_ff = memtrbs_r4xx[data];
2539 else
2540 trbs_ff = memtrbs[data];
2541 tcas_ff.full += trbs_ff.full;
2542 }
2543
2544 sclk_eff_ff.full = sclk_ff.full;
2545
2546 if (rdev->flags & RADEON_IS_AGP) {
2547 fixed20_12 agpmode_ff;
2548 agpmode_ff.full = rfixed_const(radeon_agpmode);
2549 temp_ff.full = rfixed_const_666(16);
2550 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2551 }
2552 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2553
2554 if (ASIC_IS_R300(rdev)) {
2555 sclk_delay_ff.full = rfixed_const(250);
2556 } else {
2557 if ((rdev->family == CHIP_RV100) ||
2558 rdev->flags & RADEON_IS_IGP) {
2559 if (rdev->mc.vram_is_ddr)
2560 sclk_delay_ff.full = rfixed_const(41);
2561 else
2562 sclk_delay_ff.full = rfixed_const(33);
2563 } else {
2564 if (rdev->mc.vram_width == 128)
2565 sclk_delay_ff.full = rfixed_const(57);
2566 else
2567 sclk_delay_ff.full = rfixed_const(41);
2568 }
2569 }
2570
2571 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2572
2573 if (rdev->mc.vram_is_ddr) {
2574 if (rdev->mc.vram_width == 32) {
2575 k1.full = rfixed_const(40);
2576 c = 3;
2577 } else {
2578 k1.full = rfixed_const(20);
2579 c = 1;
2580 }
2581 } else {
2582 k1.full = rfixed_const(40);
2583 c = 3;
2584 }
2585
2586 temp_ff.full = rfixed_const(2);
2587 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2588 temp_ff.full = rfixed_const(c);
2589 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2590 temp_ff.full = rfixed_const(4);
2591 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2592 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2593 mc_latency_mclk.full += k1.full;
2594
2595 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2596 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2597
2598 /*
2599 HW cursor time assuming worst case of full size colour cursor.
2600 */
2601 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2602 temp_ff.full += trcd_ff.full;
2603 if (temp_ff.full < tras_ff.full)
2604 temp_ff.full = tras_ff.full;
2605 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2606
2607 temp_ff.full = rfixed_const(cur_size);
2608 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2609 /*
2610 Find the total latency for the display data.
2611 */
b5fc9010 2612 disp_latency_overhead.full = rfixed_const(8);
c93bb85b
JG		 2613 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2614 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2615 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2616
2617 if (mc_latency_mclk.full > mc_latency_sclk.full)
2618 disp_latency.full = mc_latency_mclk.full;
2619 else
2620 disp_latency.full = mc_latency_sclk.full;
2621
2622 /* setup Max GRPH_STOP_REQ default value */
2623 if (ASIC_IS_RV100(rdev))
2624 max_stop_req = 0x5c;
2625 else
2626 max_stop_req = 0x7c;
2627
2628 if (mode1) {
2629 /* CRTC1
2630 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2631 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2632 */
2633 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2634
2635 if (stop_req > max_stop_req)
2636 stop_req = max_stop_req;
2637
2638 /*
2639 Find the drain rate of the display buffer.
2640 */
2641 temp_ff.full = rfixed_const((16/pixel_bytes1));
2642 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2643
2644 /*
2645 Find the critical point of the display buffer.
2646 */
2647 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2648 crit_point_ff.full += rfixed_const_half(0);
2649
2650 critical_point = rfixed_trunc(crit_point_ff);
2651
2652 if (rdev->disp_priority == 2) {
2653 critical_point = 0;
2654 }
2655
2656 /*
2657 The critical point should never be above max_stop_req-4. Setting
2658 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2659 */
2660 if (max_stop_req - critical_point < 4)
2661 critical_point = 0;
2662
2663 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2664 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2665 critical_point = 0x10;
2666 }
2667
2668 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2669 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2670 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2671 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2672 if ((rdev->family == CHIP_R350) &&
2673 (stop_req > 0x15)) {
2674 stop_req -= 0x10;
2675 }
2676 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2677 temp |= RADEON_GRPH_BUFFER_SIZE;
2678 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2679 RADEON_GRPH_CRITICAL_AT_SOF |
2680 RADEON_GRPH_STOP_CNTL);
2681 /*
2682 Write the result into the register.
2683 */
2684 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2685 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2686
2687#if 0
2688 if ((rdev->family == CHIP_RS400) ||
2689 (rdev->family == CHIP_RS480)) {
2690 /* attempt to program RS400 disp regs correctly ??? */
2691 temp = RREG32(RS400_DISP1_REG_CNTL);
2692 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2693 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2694 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2695 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2696 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2697 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2698 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2699 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2700 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2701 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2702 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2703 }
2704#endif
2705
2706 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2707 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2708 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2709 }
2710
2711 if (mode2) {
2712 u32 grph2_cntl;
2713 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2714
2715 if (stop_req > max_stop_req)
2716 stop_req = max_stop_req;
2717
2718 /*
2719 Find the drain rate of the display buffer.
2720 */
2721 temp_ff.full = rfixed_const((16/pixel_bytes2));
2722 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2723
2724 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2725 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2726 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2727 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2728 if ((rdev->family == CHIP_R350) &&
2729 (stop_req > 0x15)) {
2730 stop_req -= 0x10;
2731 }
2732 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2733 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2734 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2735 RADEON_GRPH_CRITICAL_AT_SOF |
2736 RADEON_GRPH_STOP_CNTL);
2737
2738 if ((rdev->family == CHIP_RS100) ||
2739 (rdev->family == CHIP_RS200))
2740 critical_point2 = 0;
2741 else {
2742 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2743 temp_ff.full = rfixed_const(temp);
2744 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2745 if (sclk_ff.full < temp_ff.full)
2746 temp_ff.full = sclk_ff.full;
2747
2748 read_return_rate.full = temp_ff.full;
2749
2750 if (mode1) {
2751 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2752 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2753 } else {
2754 time_disp1_drop_priority.full = 0;
2755 }
2756 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2757 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2758 crit_point_ff.full += rfixed_const_half(0);
2759
2760 critical_point2 = rfixed_trunc(crit_point_ff);
2761
2762 if (rdev->disp_priority == 2) {
2763 critical_point2 = 0;
2764 }
2765
2766 if (max_stop_req - critical_point2 < 4)
2767 critical_point2 = 0;
2768
2769 }
2770
2771 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2772 /* some R300 cards have problem with this set to 0 */
2773 critical_point2 = 0x10;
2774 }
2775
2776 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2777 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2778
2779 if ((rdev->family == CHIP_RS400) ||
2780 (rdev->family == CHIP_RS480)) {
2781#if 0
2782 /* attempt to program RS400 disp2 regs correctly ??? */
2783 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2784 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2785 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2786 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2787 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2788 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2789 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2790 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2791 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2792 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2793 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2794 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2795#endif
2796 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2797 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2798 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2799 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2800 }
2801
2802 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2803 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2804 }
2805}
551ebd83
DA		 2806
2807static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2808{
2809 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 2810 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 2811 DRM_ERROR("width %d\n", t->width);
ceb776bc 2812 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 2813 DRM_ERROR("height %d\n", t->height);
ceb776bc 2814 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 2815 DRM_ERROR("num levels %d\n", t->num_levels);
2816 DRM_ERROR("depth %d\n", t->txdepth);
2817 DRM_ERROR("bpp %d\n", t->cpp);
2818 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2819 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2820 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 2821 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 2822}
2823
2824static int r100_cs_track_cube(struct radeon_device *rdev,
2825 struct r100_cs_track *track, unsigned idx)
2826{
2827 unsigned face, w, h;
4c788679 2828 struct radeon_bo *cube_robj;
551ebd83
DA		 2829 unsigned long size;
2830
2831 for (face = 0; face < 5; face++) {
2832 cube_robj = track->textures[idx].cube_info[face].robj;
2833 w = track->textures[idx].cube_info[face].width;
2834 h = track->textures[idx].cube_info[face].height;
2835
2836 size = w * h;
2837 size *= track->textures[idx].cpp;
2838
2839 size += track->textures[idx].cube_info[face].offset;
2840
4c788679 2841 if (size > radeon_bo_size(cube_robj)) {
551ebd83 2842 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
4c788679 2843 size, radeon_bo_size(cube_robj));
551ebd83
DA		 2844 r100_cs_track_texture_print(&track->textures[idx]);
2845 return -1;
2846 }
2847 }
2848 return 0;
2849}
2850
d785d78b
DA		 2851static int r100_track_compress_size(int compress_format, int w, int h)
2852{
2853 int block_width, block_height, block_bytes;
2854 int wblocks, hblocks;
2855 int min_wblocks;
2856 int sz;
2857
2858 block_width = 4;
2859 block_height = 4;
2860
2861 switch (compress_format) {
2862 case R100_TRACK_COMP_DXT1:
2863 block_bytes = 8;
2864 min_wblocks = 4;
2865 break;
2866 default:
2867 case R100_TRACK_COMP_DXT35:
2868 block_bytes = 16;
2869 min_wblocks = 2;
2870 break;
2871 }
2872
2873 hblocks = (h + block_height - 1) / block_height;
2874 wblocks = (w + block_width - 1) / block_width;
2875 if (wblocks < min_wblocks)
2876 wblocks = min_wblocks;
2877 sz = wblocks * hblocks * block_bytes;
2878 return sz;
2879}
2880
551ebd83
DA		 2881static int r100_cs_track_texture_check(struct radeon_device *rdev,
2882 struct r100_cs_track *track)
2883{
4c788679 2884 struct radeon_bo *robj;
551ebd83
DA		 2885 unsigned long size;
2886 unsigned u, i, w, h;
2887 int ret;
2888
2889 for (u = 0; u < track->num_texture; u++) {
2890 if (!track->textures[u].enabled)
2891 continue;
2892 robj = track->textures[u].robj;
2893 if (robj == NULL) {
2894 DRM_ERROR("No texture bound to unit %u\n", u);
2895 return -EINVAL;
2896 }
2897 size = 0;
2898 for (i = 0; i <= track->textures[u].num_levels; i++) {
2899 if (track->textures[u].use_pitch) {
2900 if (rdev->family < CHIP_R300)
2901 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2902 else
2903 w = track->textures[u].pitch / (1 << i);
2904 } else {
ceb776bc 2905 w = track->textures[u].width;
551ebd83
DA		 2906 if (rdev->family >= CHIP_RV515)
2907 w |= track->textures[u].width_11;
ceb776bc 2908 w = w / (1 << i);
551ebd83
DA		 2909 if (track->textures[u].roundup_w)
2910 w = roundup_pow_of_two(w);
2911 }
ceb776bc 2912 h = track->textures[u].height;
551ebd83
DA		 2913 if (rdev->family >= CHIP_RV515)
2914 h |= track->textures[u].height_11;
ceb776bc 2915 h = h / (1 << i);
551ebd83
DA		 2916 if (track->textures[u].roundup_h)
2917 h = roundup_pow_of_two(h);
d785d78b
DA		 2918 if (track->textures[u].compress_format) {
2919
2920 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2921 /* compressed textures are block based */
2922 } else
2923 size += w * h;
551ebd83
DA		 2924 }
2925 size *= track->textures[u].cpp;
d785d78b 2926
551ebd83
DA		 2927 switch (track->textures[u].tex_coord_type) {
2928 case 0:
2929 break;
2930 case 1:
2931 size *= (1 << track->textures[u].txdepth);
2932 break;
2933 case 2:
2934 if (track->separate_cube) {
2935 ret = r100_cs_track_cube(rdev, track, u);
2936 if (ret)
2937 return ret;
2938 } else
2939 size *= 6;
2940 break;
2941 default:
2942 DRM_ERROR("Invalid texture coordinate type %u for unit "
2943 "%u\n", track->textures[u].tex_coord_type, u);
2944 return -EINVAL;
2945 }
4c788679 2946 if (size > radeon_bo_size(robj)) {
551ebd83 2947 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 2948 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 2949 r100_cs_track_texture_print(&track->textures[u]);
2950 return -EINVAL;
2951 }
2952 }
2953 return 0;
2954}
2955
2956int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2957{
2958 unsigned i;
2959 unsigned long size;
2960 unsigned prim_walk;
2961 unsigned nverts;
2962
2963 for (i = 0; i < track->num_cb; i++) {
2964 if (track->cb[i].robj == NULL) {
46c64d4b
MO		 2965 if (!(track->fastfill || track->color_channel_mask ||
2966 track->blend_read_enable)) {
2967 continue;
2968 }
551ebd83
DA		 2969 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2970 return -EINVAL;
2971 }
2972 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2973 size += track->cb[i].offset;
4c788679 2974 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 2975 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2976 "(need %lu have %lu) !\n", i, size,
4c788679 2977 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 2978 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2979 i, track->cb[i].pitch, track->cb[i].cpp,
2980 track->cb[i].offset, track->maxy);
2981 return -EINVAL;
2982 }
2983 }
2984 if (track->z_enabled) {
2985 if (track->zb.robj == NULL) {
2986 DRM_ERROR("[drm] No buffer for z buffer !\n");
2987 return -EINVAL;
2988 }
2989 size = track->zb.pitch * track->zb.cpp * track->maxy;
2990 size += track->zb.offset;
4c788679 2991 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 2992 DRM_ERROR("[drm] Buffer too small for z buffer "
2993 "(need %lu have %lu) !\n", size,
4c788679 2994 radeon_bo_size(track->zb.robj));
551ebd83
DA		 2995 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2996 track->zb.pitch, track->zb.cpp,
2997 track->zb.offset, track->maxy);
2998 return -EINVAL;
2999 }
3000 }
3001 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3002 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3003 switch (prim_walk) {
3004 case 1:
3005 for (i = 0; i < track->num_arrays; i++) {
3006 size = track->arrays[i].esize * track->max_indx * 4;
3007 if (track->arrays[i].robj == NULL) {
3008 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3009 "bound\n", prim_walk, i);
3010 return -EINVAL;
3011 }
4c788679
JG		 3012 if (size > radeon_bo_size(track->arrays[i].robj)) {
3013 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3014 "need %lu dwords have %lu dwords\n",
3015 prim_walk, i, size >> 2,
3016 radeon_bo_size(track->arrays[i].robj)
3017 >> 2);
551ebd83
DA		 3018 DRM_ERROR("Max indices %u\n", track->max_indx);
3019 return -EINVAL;
3020 }
3021 }
3022 break;
3023 case 2:
3024 for (i = 0; i < track->num_arrays; i++) {
3025 size = track->arrays[i].esize * (nverts - 1) * 4;
3026 if (track->arrays[i].robj == NULL) {
3027 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3028 "bound\n", prim_walk, i);
3029 return -EINVAL;
3030 }
4c788679
JG		 3031 if (size > radeon_bo_size(track->arrays[i].robj)) {
3032 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3033 "need %lu dwords have %lu dwords\n",
3034 prim_walk, i, size >> 2,
3035 radeon_bo_size(track->arrays[i].robj)
3036 >> 2);
551ebd83
DA		 3037 return -EINVAL;
3038 }
3039 }
3040 break;
3041 case 3:
3042 size = track->vtx_size * nverts;
3043 if (size != track->immd_dwords) {
3044 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3045 track->immd_dwords, size);
3046 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3047 nverts, track->vtx_size);
3048 return -EINVAL;
3049 }
3050 break;
3051 default:
3052 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3053 prim_walk);
3054 return -EINVAL;
3055 }
3056 return r100_cs_track_texture_check(rdev, track);
3057}
3058
3059void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3060{
3061 unsigned i, face;
3062
3063 if (rdev->family < CHIP_R300) {
3064 track->num_cb = 1;
3065 if (rdev->family <= CHIP_RS200)
3066 track->num_texture = 3;
3067 else
3068 track->num_texture = 6;
3069 track->maxy = 2048;
3070 track->separate_cube = 1;
3071 } else {
3072 track->num_cb = 4;
3073 track->num_texture = 16;
3074 track->maxy = 4096;
3075 track->separate_cube = 0;
3076 }
3077
3078 for (i = 0; i < track->num_cb; i++) {
3079 track->cb[i].robj = NULL;
3080 track->cb[i].pitch = 8192;
3081 track->cb[i].cpp = 16;
3082 track->cb[i].offset = 0;
3083 }
3084 track->z_enabled = true;
3085 track->zb.robj = NULL;
3086 track->zb.pitch = 8192;
3087 track->zb.cpp = 4;
3088 track->zb.offset = 0;
3089 track->vtx_size = 0x7F;
3090 track->immd_dwords = 0xFFFFFFFFUL;
3091 track->num_arrays = 11;
3092 track->max_indx = 0x00FFFFFFUL;
3093 for (i = 0; i < track->num_arrays; i++) {
3094 track->arrays[i].robj = NULL;
3095 track->arrays[i].esize = 0x7F;
3096 }
3097 for (i = 0; i < track->num_texture; i++) {
d785d78b 3098 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3099 track->textures[i].pitch = 16536;
3100 track->textures[i].width = 16536;
3101 track->textures[i].height = 16536;
3102 track->textures[i].width_11 = 1 << 11;
3103 track->textures[i].height_11 = 1 << 11;
3104 track->textures[i].num_levels = 12;
3105 if (rdev->family <= CHIP_RS200) {
3106 track->textures[i].tex_coord_type = 0;
3107 track->textures[i].txdepth = 0;
3108 } else {
3109 track->textures[i].txdepth = 16;
3110 track->textures[i].tex_coord_type = 1;
3111 }
3112 track->textures[i].cpp = 64;
3113 track->textures[i].robj = NULL;
3114 /* CS IB emission code makes sure texture unit are disabled */
3115 track->textures[i].enabled = false;
3116 track->textures[i].roundup_w = true;
3117 track->textures[i].roundup_h = true;
3118 if (track->separate_cube)
3119 for (face = 0; face < 5; face++) {
3120 track->textures[i].cube_info[face].robj = NULL;
3121 track->textures[i].cube_info[face].width = 16536;
3122 track->textures[i].cube_info[face].height = 16536;
3123 track->textures[i].cube_info[face].offset = 0;
3124 }
3125 }
3126}
3ce0a23d
JG		 3127
3128int r100_ring_test(struct radeon_device *rdev)
3129{
3130 uint32_t scratch;
3131 uint32_t tmp = 0;
3132 unsigned i;
3133 int r;
3134
3135 r = radeon_scratch_get(rdev, &scratch);
3136 if (r) {
3137 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3138 return r;
3139 }
3140 WREG32(scratch, 0xCAFEDEAD);
3141 r = radeon_ring_lock(rdev, 2);
3142 if (r) {
3143 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3144 radeon_scratch_free(rdev, scratch);
3145 return r;
3146 }
3147 radeon_ring_write(rdev, PACKET0(scratch, 0));
3148 radeon_ring_write(rdev, 0xDEADBEEF);
3149 radeon_ring_unlock_commit(rdev);
3150 for (i = 0; i < rdev->usec_timeout; i++) {
3151 tmp = RREG32(scratch);
3152 if (tmp == 0xDEADBEEF) {
3153 break;
3154 }
3155 DRM_UDELAY(1);
3156 }
3157 if (i < rdev->usec_timeout) {
3158 DRM_INFO("ring test succeeded in %d usecs\n", i);
3159 } else {
3160 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3161 scratch, tmp);
3162 r = -EINVAL;
3163 }
3164 radeon_scratch_free(rdev, scratch);
3165 return r;
3166}
3167
3168void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3169{
3170 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3171 radeon_ring_write(rdev, ib->gpu_addr);
3172 radeon_ring_write(rdev, ib->length_dw);
3173}
3174
3175int r100_ib_test(struct radeon_device *rdev)
3176{
3177 struct radeon_ib *ib;
3178 uint32_t scratch;
3179 uint32_t tmp = 0;
3180 unsigned i;
3181 int r;
3182
3183 r = radeon_scratch_get(rdev, &scratch);
3184 if (r) {
3185 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3186 return r;
3187 }
3188 WREG32(scratch, 0xCAFEDEAD);
3189 r = radeon_ib_get(rdev, &ib);
3190 if (r) {
3191 return r;
3192 }
3193 ib->ptr[0] = PACKET0(scratch, 0);
3194 ib->ptr[1] = 0xDEADBEEF;
3195 ib->ptr[2] = PACKET2(0);
3196 ib->ptr[3] = PACKET2(0);
3197 ib->ptr[4] = PACKET2(0);
3198 ib->ptr[5] = PACKET2(0);
3199 ib->ptr[6] = PACKET2(0);
3200 ib->ptr[7] = PACKET2(0);
3201 ib->length_dw = 8;
3202 r = radeon_ib_schedule(rdev, ib);
3203 if (r) {
3204 radeon_scratch_free(rdev, scratch);
3205 radeon_ib_free(rdev, &ib);
3206 return r;
3207 }
3208 r = radeon_fence_wait(ib->fence, false);
3209 if (r) {
3210 return r;
3211 }
3212 for (i = 0; i < rdev->usec_timeout; i++) {
3213 tmp = RREG32(scratch);
3214 if (tmp == 0xDEADBEEF) {
3215 break;
3216 }
3217 DRM_UDELAY(1);
3218 }
3219 if (i < rdev->usec_timeout) {
3220 DRM_INFO("ib test succeeded in %u usecs\n", i);
3221 } else {
3222 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3223 scratch, tmp);
3224 r = -EINVAL;
3225 }
3226 radeon_scratch_free(rdev, scratch);
3227 radeon_ib_free(rdev, &ib);
3228 return r;
3229}
9f022ddf
JG		 3230
3231void r100_ib_fini(struct radeon_device *rdev)
3232{
3233 radeon_ib_pool_fini(rdev);
3234}
3235
3236int r100_ib_init(struct radeon_device *rdev)
3237{
3238 int r;
3239
3240 r = radeon_ib_pool_init(rdev);
3241 if (r) {
3242 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3243 r100_ib_fini(rdev);
3244 return r;
3245 }
3246 r = r100_ib_test(rdev);
3247 if (r) {
3248 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3249 r100_ib_fini(rdev);
3250 return r;
3251 }
3252 return 0;
3253}
3254
3255void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3256{
3257 /* Shutdown CP we shouldn't need to do that but better be safe than
3258 * sorry
3259 */
3260 rdev->cp.ready = false;
3261 WREG32(R_000740_CP_CSQ_CNTL, 0);
3262
3263 /* Save few CRTC registers */
ca6ffc64 3264 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3265 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3266 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3267 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3268 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3269 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3270 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3271 }
3272
3273 /* Disable VGA aperture access */
ca6ffc64 3274 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3275 /* Disable cursor, overlay, crtc */
3276 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3277 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3278 S_000054_CRTC_DISPLAY_DIS(1));
3279 WREG32(R_000050_CRTC_GEN_CNTL,
3280 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3281 S_000050_CRTC_DISP_REQ_EN_B(1));
3282 WREG32(R_000420_OV0_SCALE_CNTL,
3283 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3284 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3285 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3286 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3287 S_000360_CUR2_LOCK(1));
3288 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3289 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3290 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3291 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3292 WREG32(R_000360_CUR2_OFFSET,
3293 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3294 }
3295}
3296
3297void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3298{
3299 /* Update base address for crtc */
d594e46a 3300 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3301 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3302 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3303 }
3304 /* Restore CRTC registers */
ca6ffc64 3305 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3306 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3307 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3308 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3309 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3310 }
3311}
ca6ffc64
JG		 3312
3313void r100_vga_render_disable(struct radeon_device *rdev)
3314{
d4550907 3315 u32 tmp;
ca6ffc64 3316
d4550907 3317 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3318 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3319}
d4550907
JG		 3320
3321static void r100_debugfs(struct radeon_device *rdev)
3322{
3323 int r;
3324
3325 r = r100_debugfs_mc_info_init(rdev);
3326 if (r)
3327 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3328}
3329
3330static void r100_mc_program(struct radeon_device *rdev)
3331{
3332 struct r100_mc_save save;
3333
3334 /* Stops all mc clients */
3335 r100_mc_stop(rdev, &save);
3336 if (rdev->flags & RADEON_IS_AGP) {
3337 WREG32(R_00014C_MC_AGP_LOCATION,
3338 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3339 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3340 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3341 if (rdev->family > CHIP_RV200)
3342 WREG32(R_00015C_AGP_BASE_2,
3343 upper_32_bits(rdev->mc.agp_base) & 0xff);
3344 } else {
3345 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3346 WREG32(R_000170_AGP_BASE, 0);
3347 if (rdev->family > CHIP_RV200)
3348 WREG32(R_00015C_AGP_BASE_2, 0);
3349 }
3350 /* Wait for mc idle */
3351 if (r100_mc_wait_for_idle(rdev))
3352 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3353 /* Program MC, should be a 32bits limited address space */
3354 WREG32(R_000148_MC_FB_LOCATION,
3355 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3356 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3357 r100_mc_resume(rdev, &save);
3358}
3359
3360void r100_clock_startup(struct radeon_device *rdev)
3361{
3362 u32 tmp;
3363
3364 if (radeon_dynclks != -1 && radeon_dynclks)
3365 radeon_legacy_set_clock_gating(rdev, 1);
3366 /* We need to force on some of the block */
3367 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3368 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3369 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3370 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3371 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3372}
3373
3374static int r100_startup(struct radeon_device *rdev)
3375{
3376 int r;
3377
92cde00c
AD		 3378 /* set common regs */
3379 r100_set_common_regs(rdev);
3380 /* program mc */
d4550907
JG		 3381 r100_mc_program(rdev);
3382 /* Resume clock */
3383 r100_clock_startup(rdev);
3384 /* Initialize GPU configuration (# pipes, ...) */
3385 r100_gpu_init(rdev);
3386 /* Initialize GART (initialize after TTM so we can allocate
3387 * memory through TTM but finalize after TTM) */
17e15b0c 3388 r100_enable_bm(rdev);
d4550907
JG		 3389 if (rdev->flags & RADEON_IS_PCI) {
3390 r = r100_pci_gart_enable(rdev);
3391 if (r)
3392 return r;
3393 }
3394 /* Enable IRQ */
d4550907 3395 r100_irq_set(rdev);
cafe6609 3396 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3397 /* 1M ring buffer */
3398 r = r100_cp_init(rdev, 1024 * 1024);
3399 if (r) {
3400 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3401 return r;
3402 }
3403 r = r100_wb_init(rdev);
3404 if (r)
3405 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3406 r = r100_ib_init(rdev);
3407 if (r) {
3408 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3409 return r;
3410 }
3411 return 0;
3412}
3413
3414int r100_resume(struct radeon_device *rdev)
3415{
3416 /* Make sur GART are not working */
3417 if (rdev->flags & RADEON_IS_PCI)
3418 r100_pci_gart_disable(rdev);
3419 /* Resume clock before doing reset */
3420 r100_clock_startup(rdev);
3421 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3422 if (radeon_gpu_reset(rdev)) {
3423 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3424 RREG32(R_000E40_RBBM_STATUS),
3425 RREG32(R_0007C0_CP_STAT));
3426 }
3427 /* post */
3428 radeon_combios_asic_init(rdev->ddev);
3429 /* Resume clock after posting */
3430 r100_clock_startup(rdev);
550e2d92
DA		 3431 /* Initialize surface registers */
3432 radeon_surface_init(rdev);
d4550907
JG		 3433 return r100_startup(rdev);
3434}
3435
3436int r100_suspend(struct radeon_device *rdev)
3437{
3438 r100_cp_disable(rdev);
3439 r100_wb_disable(rdev);
3440 r100_irq_disable(rdev);
3441 if (rdev->flags & RADEON_IS_PCI)
3442 r100_pci_gart_disable(rdev);
3443 return 0;
3444}
3445
3446void r100_fini(struct radeon_device *rdev)
3447{
29fb52ca 3448 radeon_pm_fini(rdev);
d4550907
JG		 3449 r100_cp_fini(rdev);
3450 r100_wb_fini(rdev);
3451 r100_ib_fini(rdev);
3452 radeon_gem_fini(rdev);
3453 if (rdev->flags & RADEON_IS_PCI)
3454 r100_pci_gart_fini(rdev);
d0269ed8 3455 radeon_agp_fini(rdev);
d4550907
JG		 3456 radeon_irq_kms_fini(rdev);
3457 radeon_fence_driver_fini(rdev);
4c788679 3458 radeon_bo_fini(rdev);
d4550907
JG		 3459 radeon_atombios_fini(rdev);
3460 kfree(rdev->bios);
3461 rdev->bios = NULL;
3462}
3463
d4550907
JG		 3464int r100_init(struct radeon_device *rdev)
3465{
3466 int r;
3467
d4550907
JG		 3468 /* Register debugfs file specific to this group of asics */
3469 r100_debugfs(rdev);
3470 /* Disable VGA */
3471 r100_vga_render_disable(rdev);
3472 /* Initialize scratch registers */
3473 radeon_scratch_init(rdev);
3474 /* Initialize surface registers */
3475 radeon_surface_init(rdev);
3476 /* TODO: disable VGA need to use VGA request */
3477 /* BIOS*/
3478 if (!radeon_get_bios(rdev)) {
3479 if (ASIC_IS_AVIVO(rdev))
3480 return -EINVAL;
3481 }
3482 if (rdev->is_atom_bios) {
3483 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3484 return -EINVAL;
3485 } else {
3486 r = radeon_combios_init(rdev);
3487 if (r)
3488 return r;
3489 }
3490 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3491 if (radeon_gpu_reset(rdev)) {
3492 dev_warn(rdev->dev,
3493 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3494 RREG32(R_000E40_RBBM_STATUS),
3495 RREG32(R_0007C0_CP_STAT));
3496 }
3497 /* check if cards are posted or not */
72542d77
DA		 3498 if (radeon_boot_test_post_card(rdev) == false)
3499 return -EINVAL;
d4550907
JG		 3500 /* Set asic errata */
3501 r100_errata(rdev);
3502 /* Initialize clocks */
3503 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 3504 /* Initialize power management */
3505 radeon_pm_init(rdev);
d594e46a
JG		 3506 /* initialize AGP */
3507 if (rdev->flags & RADEON_IS_AGP) {
3508 r = radeon_agp_init(rdev);
3509 if (r) {
3510 radeon_agp_disable(rdev);
3511 }
3512 }
3513 /* initialize VRAM */
3514 r100_mc_init(rdev);
d4550907
JG		 3515 /* Fence driver */
3516 r = radeon_fence_driver_init(rdev);
3517 if (r)
3518 return r;
3519 r = radeon_irq_kms_init(rdev);
3520 if (r)
3521 return r;
3522 /* Memory manager */
4c788679 3523 r = radeon_bo_init(rdev);
d4550907
JG		 3524 if (r)
3525 return r;
3526 if (rdev->flags & RADEON_IS_PCI) {
3527 r = r100_pci_gart_init(rdev);
3528 if (r)
3529 return r;
3530 }
3531 r100_set_safe_registers(rdev);
3532 rdev->accel_working = true;
3533 r = r100_startup(rdev);
3534 if (r) {
3535 /* Somethings want wront with the accel init stop accel */
3536 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907
JG		 3537 r100_cp_fini(rdev);
3538 r100_wb_fini(rdev);
3539 r100_ib_fini(rdev);
655efd3d 3540 radeon_irq_kms_fini(rdev);
d4550907
JG		 3541 if (rdev->flags & RADEON_IS_PCI)
3542 r100_pci_gart_fini(rdev);
d4550907
JG		 3543 rdev->accel_working = false;
3544 }
3545 return 0;
3546}
Linux 6.x block layer and io_uring tree(s)