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drm/radeon: add vce dpm support for KV/KB
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH		 30#include <drm/drmP.h>
31#include <drm/radeon_drm.h>
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
49e02b73 39#include "atom.h"
3ce0a23d 40
70967ab9 41#include <linux/firmware.h>
e0cd3608 42#include <linux/module.h>
70967ab9 43
551ebd83
DA		 44#include "r100_reg_safe.h"
45#include "rn50_reg_safe.h"
46
70967ab9
BH		 47/* Firmware Names */
48#define FIRMWARE_R100 "radeon/R100_cp.bin"
49#define FIRMWARE_R200 "radeon/R200_cp.bin"
50#define FIRMWARE_R300 "radeon/R300_cp.bin"
51#define FIRMWARE_R420 "radeon/R420_cp.bin"
52#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54#define FIRMWARE_R520 "radeon/R520_cp.bin"
55
56MODULE_FIRMWARE(FIRMWARE_R100);
57MODULE_FIRMWARE(FIRMWARE_R200);
58MODULE_FIRMWARE(FIRMWARE_R300);
59MODULE_FIRMWARE(FIRMWARE_R420);
60MODULE_FIRMWARE(FIRMWARE_RS690);
61MODULE_FIRMWARE(FIRMWARE_RS600);
62MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 63
551ebd83
DA		 64#include "r100_track.h"
65
48ef779f
AD		 66/* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
68 * and others in some cases.
69 */
70
2b48b968
AD		 71static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
72{
73 if (crtc == 0) {
74 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
75 return true;
76 else
77 return false;
78 } else {
79 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
80 return true;
81 else
82 return false;
83 }
84}
85
86static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
87{
88 u32 vline1, vline2;
89
90 if (crtc == 0) {
91 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
92 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 } else {
94 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
95 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 }
97 if (vline1 != vline2)
98 return true;
99 else
100 return false;
101}
102
48ef779f
AD		 103/**
104 * r100_wait_for_vblank - vblank wait asic callback.
105 *
106 * @rdev: radeon_device pointer
107 * @crtc: crtc to wait for vblank on
108 *
109 * Wait for vblank on the requested crtc (r1xx-r4xx).
110 */
3ae19b75
AD		 111void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
112{
2b48b968 113 unsigned i = 0;
3ae19b75 114
94f768fd
AD		 115 if (crtc >= rdev->num_crtc)
116 return;
117
118 if (crtc == 0) {
2b48b968
AD		 119 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
120 return;
3ae19b75 121 } else {
2b48b968
AD		 122 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
123 return;
124 }
125
126 /* depending on when we hit vblank, we may be close to active; if so,
127 * wait for another frame.
128 */
129 while (r100_is_in_vblank(rdev, crtc)) {
130 if (i++ % 100 == 0) {
131 if (!r100_is_counter_moving(rdev, crtc))
132 break;
133 }
134 }
135
136 while (!r100_is_in_vblank(rdev, crtc)) {
137 if (i++ % 100 == 0) {
138 if (!r100_is_counter_moving(rdev, crtc))
139 break;
3ae19b75
AD		 140 }
141 }
142}
143
48ef779f
AD		 144/**
145 * r100_pre_page_flip - pre-pageflip callback.
146 *
147 * @rdev: radeon_device pointer
148 * @crtc: crtc to prepare for pageflip on
149 *
150 * Pre-pageflip callback (r1xx-r4xx).
151 * Enables the pageflip irq (vblank irq).
771fe6b9 152 */
6f34be50
AD		 153void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
154{
6f34be50
AD		 155 /* enable the pflip int */
156 radeon_irq_kms_pflip_irq_get(rdev, crtc);
157}
158
48ef779f
AD		 159/**
160 * r100_post_page_flip - pos-pageflip callback.
161 *
162 * @rdev: radeon_device pointer
163 * @crtc: crtc to cleanup pageflip on
164 *
165 * Post-pageflip callback (r1xx-r4xx).
166 * Disables the pageflip irq (vblank irq).
167 */
6f34be50
AD		 168void r100_post_page_flip(struct radeon_device *rdev, int crtc)
169{
170 /* disable the pflip int */
171 radeon_irq_kms_pflip_irq_put(rdev, crtc);
172}
173
48ef779f
AD		 174/**
175 * r100_page_flip - pageflip callback.
176 *
177 * @rdev: radeon_device pointer
178 * @crtc_id: crtc to cleanup pageflip on
179 * @crtc_base: new address of the crtc (GPU MC address)
180 *
181 * Does the actual pageflip (r1xx-r4xx).
182 * During vblank we take the crtc lock and wait for the update_pending
183 * bit to go high, when it does, we release the lock, and allow the
184 * double buffered update to take place.
185 * Returns the current update pending status.
186 */
6f34be50
AD		 187u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
188{
189 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
190 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 191 int i;
6f34be50
AD		 192
193 /* Lock the graphics update lock */
194 /* update the scanout addresses */
195 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
196
acb32506 197 /* Wait for update_pending to go high. */
f6496479
AD		 198 for (i = 0; i < rdev->usec_timeout; i++) {
199 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
200 break;
201 udelay(1);
202 }
acb32506 203 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 204
205 /* Unlock the lock, so double-buffering can take place inside vblank */
206 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
207 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
208
209 /* Return current update_pending status: */
210 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
211}
212
48ef779f
AD		 213/**
214 * r100_pm_get_dynpm_state - look up dynpm power state callback.
215 *
216 * @rdev: radeon_device pointer
217 *
218 * Look up the optimal power state based on the
219 * current state of the GPU (r1xx-r5xx).
220 * Used for dynpm only.
221 */
ce8f5370 222void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 223{
224 int i;
ce8f5370
AD		 225 rdev->pm.dynpm_can_upclock = true;
226 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 227
ce8f5370
AD		 228 switch (rdev->pm.dynpm_planned_action) {
229 case DYNPM_ACTION_MINIMUM:
a48b9b4e 230 rdev->pm.requested_power_state_index = 0;
ce8f5370 231 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 232 break;
ce8f5370 233 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 234 if (rdev->pm.current_power_state_index == 0) {
235 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 236 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 237 } else {
238 if (rdev->pm.active_crtc_count > 1) {
239 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 240 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 241 continue;
242 else if (i >= rdev->pm.current_power_state_index) {
243 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
244 break;
245 } else {
246 rdev->pm.requested_power_state_index = i;
247 break;
248 }
249 }
250 } else
251 rdev->pm.requested_power_state_index =
252 rdev->pm.current_power_state_index - 1;
253 }
d7311171
AD		 254 /* don't use the power state if crtcs are active and no display flag is set */
255 if ((rdev->pm.active_crtc_count > 0) &&
256 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
257 RADEON_PM_MODE_NO_DISPLAY)) {
258 rdev->pm.requested_power_state_index++;
259 }
a48b9b4e 260 break;
ce8f5370 261 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 262 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 264 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 265 } else {
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 269 continue;
270 else if (i <= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
272 break;
273 } else {
274 rdev->pm.requested_power_state_index = i;
275 break;
276 }
277 }
278 } else
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index + 1;
281 }
282 break;
ce8f5370 283 case DYNPM_ACTION_DEFAULT:
58e21dff 284 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 285 rdev->pm.dynpm_can_upclock = false;
58e21dff 286 break;
ce8f5370 287 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 288 default:
289 DRM_ERROR("Requested mode for not defined action\n");
290 return;
291 }
292 /* only one clock mode per power state */
293 rdev->pm.requested_clock_mode_index = 0;
294
d9fdaafb 295 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 296 rdev->pm.power_state[rdev->pm.requested_power_state_index].
297 clock_info[rdev->pm.requested_clock_mode_index].sclk,
298 rdev->pm.power_state[rdev->pm.requested_power_state_index].
299 clock_info[rdev->pm.requested_clock_mode_index].mclk,
300 rdev->pm.power_state[rdev->pm.requested_power_state_index].
301 pcie_lanes);
a48b9b4e
AD		 302}
303
48ef779f
AD		 304/**
305 * r100_pm_init_profile - Initialize power profiles callback.
306 *
307 * @rdev: radeon_device pointer
308 *
309 * Initialize the power states used in profile mode
310 * (r1xx-r3xx).
311 * Used for profile mode only.
312 */
ce8f5370
AD		 313void r100_pm_init_profile(struct radeon_device *rdev)
314{
315 /* default */
316 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
320 /* low sh */
321 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 325 /* mid sh */
326 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 330 /* high sh */
331 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
335 /* low mh */
336 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 340 /* mid mh */
341 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 345 /* high mh */
346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 350}
351
48ef779f
AD		 352/**
353 * r100_pm_misc - set additional pm hw parameters callback.
354 *
355 * @rdev: radeon_device pointer
356 *
357 * Set non-clock parameters associated with a power state
358 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
359 */
49e02b73
AD		 360void r100_pm_misc(struct radeon_device *rdev)
361{
49e02b73
AD		 362 int requested_index = rdev->pm.requested_power_state_index;
363 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
364 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
365 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
366
367 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
368 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
369 tmp = RREG32(voltage->gpio.reg);
370 if (voltage->active_high)
371 tmp |= voltage->gpio.mask;
372 else
373 tmp &= ~(voltage->gpio.mask);
374 WREG32(voltage->gpio.reg, tmp);
375 if (voltage->delay)
376 udelay(voltage->delay);
377 } else {
378 tmp = RREG32(voltage->gpio.reg);
379 if (voltage->active_high)
380 tmp &= ~voltage->gpio.mask;
381 else
382 tmp |= voltage->gpio.mask;
383 WREG32(voltage->gpio.reg, tmp);
384 if (voltage->delay)
385 udelay(voltage->delay);
386 }
387 }
388
389 sclk_cntl = RREG32_PLL(SCLK_CNTL);
390 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
391 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
392 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
393 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
394 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
395 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
396 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
397 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
398 else
399 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
400 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
401 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
402 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
403 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
404 } else
405 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
406
407 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
408 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
409 if (voltage->delay) {
410 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
411 switch (voltage->delay) {
412 case 33:
413 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
414 break;
415 case 66:
416 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
417 break;
418 case 99:
419 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
420 break;
421 case 132:
422 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
423 break;
424 }
425 } else
426 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
427 } else
428 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
429
430 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
431 sclk_cntl &= ~FORCE_HDP;
432 else
433 sclk_cntl |= FORCE_HDP;
434
435 WREG32_PLL(SCLK_CNTL, sclk_cntl);
436 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
437 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
438
439 /* set pcie lanes */
440 if ((rdev->flags & RADEON_IS_PCIE) &&
441 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 442 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 443 (ps->pcie_lanes !=
444 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
445 radeon_set_pcie_lanes(rdev,
446 ps->pcie_lanes);
d9fdaafb 447 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 448 }
49e02b73
AD		 449}
450
48ef779f
AD		 451/**
452 * r100_pm_prepare - pre-power state change callback.
453 *
454 * @rdev: radeon_device pointer
455 *
456 * Prepare for a power state change (r1xx-r4xx).
457 */
49e02b73
AD		 458void r100_pm_prepare(struct radeon_device *rdev)
459{
460 struct drm_device *ddev = rdev->ddev;
461 struct drm_crtc *crtc;
462 struct radeon_crtc *radeon_crtc;
463 u32 tmp;
464
465 /* disable any active CRTCs */
466 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
467 radeon_crtc = to_radeon_crtc(crtc);
468 if (radeon_crtc->enabled) {
469 if (radeon_crtc->crtc_id) {
470 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
471 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
472 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
473 } else {
474 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
475 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
477 }
478 }
479 }
480}
481
48ef779f
AD		 482/**
483 * r100_pm_finish - post-power state change callback.
484 *
485 * @rdev: radeon_device pointer
486 *
487 * Clean up after a power state change (r1xx-r4xx).
488 */
49e02b73
AD		 489void r100_pm_finish(struct radeon_device *rdev)
490{
491 struct drm_device *ddev = rdev->ddev;
492 struct drm_crtc *crtc;
493 struct radeon_crtc *radeon_crtc;
494 u32 tmp;
495
496 /* enable any active CRTCs */
497 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
498 radeon_crtc = to_radeon_crtc(crtc);
499 if (radeon_crtc->enabled) {
500 if (radeon_crtc->crtc_id) {
501 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
502 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
503 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
504 } else {
505 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
506 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
507 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
508 }
509 }
510 }
511}
512
48ef779f
AD		 513/**
514 * r100_gui_idle - gui idle callback.
515 *
516 * @rdev: radeon_device pointer
517 *
518 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
519 * Returns true if idle, false if not.
520 */
def9ba9c
AD		 521bool r100_gui_idle(struct radeon_device *rdev)
522{
523 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
524 return false;
525 else
526 return true;
527}
528
05a05c50 529/* hpd for digital panel detect/disconnect */
48ef779f
AD		 530/**
531 * r100_hpd_sense - hpd sense callback.
532 *
533 * @rdev: radeon_device pointer
534 * @hpd: hpd (hotplug detect) pin
535 *
536 * Checks if a digital monitor is connected (r1xx-r4xx).
537 * Returns true if connected, false if not connected.
538 */
05a05c50
AD		 539bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
540{
541 bool connected = false;
542
543 switch (hpd) {
544 case RADEON_HPD_1:
545 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
546 connected = true;
547 break;
548 case RADEON_HPD_2:
549 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
550 connected = true;
551 break;
552 default:
553 break;
554 }
555 return connected;
556}
557
48ef779f
AD		 558/**
559 * r100_hpd_set_polarity - hpd set polarity callback.
560 *
561 * @rdev: radeon_device pointer
562 * @hpd: hpd (hotplug detect) pin
563 *
564 * Set the polarity of the hpd pin (r1xx-r4xx).
565 */
05a05c50
AD		 566void r100_hpd_set_polarity(struct radeon_device *rdev,
567 enum radeon_hpd_id hpd)
568{
569 u32 tmp;
570 bool connected = r100_hpd_sense(rdev, hpd);
571
572 switch (hpd) {
573 case RADEON_HPD_1:
574 tmp = RREG32(RADEON_FP_GEN_CNTL);
575 if (connected)
576 tmp &= ~RADEON_FP_DETECT_INT_POL;
577 else
578 tmp |= RADEON_FP_DETECT_INT_POL;
579 WREG32(RADEON_FP_GEN_CNTL, tmp);
580 break;
581 case RADEON_HPD_2:
582 tmp = RREG32(RADEON_FP2_GEN_CNTL);
583 if (connected)
584 tmp &= ~RADEON_FP2_DETECT_INT_POL;
585 else
586 tmp |= RADEON_FP2_DETECT_INT_POL;
587 WREG32(RADEON_FP2_GEN_CNTL, tmp);
588 break;
589 default:
590 break;
591 }
592}
593
48ef779f
AD		 594/**
595 * r100_hpd_init - hpd setup callback.
596 *
597 * @rdev: radeon_device pointer
598 *
599 * Setup the hpd pins used by the card (r1xx-r4xx).
600 * Set the polarity, and enable the hpd interrupts.
601 */
05a05c50
AD		 602void r100_hpd_init(struct radeon_device *rdev)
603{
604 struct drm_device *dev = rdev->ddev;
605 struct drm_connector *connector;
fb98257a 606 unsigned enable = 0;
05a05c50
AD		 607
608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
609 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 610 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 611 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 612 }
fb98257a 613 radeon_irq_kms_enable_hpd(rdev, enable);
05a05c50
AD		 614}
615
48ef779f
AD		 616/**
617 * r100_hpd_fini - hpd tear down callback.
618 *
619 * @rdev: radeon_device pointer
620 *
621 * Tear down the hpd pins used by the card (r1xx-r4xx).
622 * Disable the hpd interrupts.
623 */
05a05c50
AD		 624void r100_hpd_fini(struct radeon_device *rdev)
625{
626 struct drm_device *dev = rdev->ddev;
627 struct drm_connector *connector;
fb98257a 628 unsigned disable = 0;
05a05c50
AD		 629
630 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
631 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 632 disable |= 1 << radeon_connector->hpd.hpd;
05a05c50 633 }
fb98257a 634 radeon_irq_kms_disable_hpd(rdev, disable);
05a05c50
AD		 635}
636
771fe6b9
JG		 637/*
638 * PCI GART
639 */
640void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
641{
642 /* TODO: can we do somethings here ? */
643 /* It seems hw only cache one entry so we should discard this
644 * entry otherwise if first GPU GART read hit this entry it
645 * could end up in wrong address. */
646}
647
4aac0473 648int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 649{
771fe6b9
JG		 650 int r;
651
c9a1be96 652 if (rdev->gart.ptr) {
fce7d61b 653 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 654 return 0;
655 }
771fe6b9
JG		 656 /* Initialize common gart structure */
657 r = radeon_gart_init(rdev);
4aac0473 658 if (r)
771fe6b9 659 return r;
4aac0473 660 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850
AD		 661 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
662 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 663 return radeon_gart_table_ram_alloc(rdev);
664}
665
666int r100_pci_gart_enable(struct radeon_device *rdev)
667{
668 uint32_t tmp;
669
82568565 670 radeon_gart_restore(rdev);
771fe6b9
JG		 671 /* discard memory request outside of configured range */
672 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
673 WREG32(RADEON_AIC_CNTL, tmp);
674 /* set address range for PCI address translate */
d594e46a
JG		 675 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
676 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 677 /* set PCI GART page-table base address */
678 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
680 WREG32(RADEON_AIC_CNTL, tmp);
681 r100_pci_gart_tlb_flush(rdev);
43caf451 682 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 683 (unsigned)(rdev->mc.gtt_size >> 20),
684 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 685 rdev->gart.ready = true;
686 return 0;
687}
688
689void r100_pci_gart_disable(struct radeon_device *rdev)
690{
691 uint32_t tmp;
692
693 /* discard memory request outside of configured range */
694 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
695 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
696 WREG32(RADEON_AIC_LO_ADDR, 0);
697 WREG32(RADEON_AIC_HI_ADDR, 0);
698}
699
700int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
701{
c9a1be96
JG		 702 u32 *gtt = rdev->gart.ptr;
703
771fe6b9
JG		 704 if (i < 0 || i > rdev->gart.num_gpu_pages) {
705 return -EINVAL;
706 }
c9a1be96 707 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 708 return 0;
709}
710
4aac0473 711void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 712{
f9274562 713 radeon_gart_fini(rdev);
4aac0473
JG		 714 r100_pci_gart_disable(rdev);
715 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 716}
717
7ed220d7
MD		 718int r100_irq_set(struct radeon_device *rdev)
719{
720 uint32_t tmp = 0;
721
003e69f9 722 if (!rdev->irq.installed) {
fce7d61b 723 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 724 WREG32(R_000040_GEN_INT_CNTL, 0);
725 return -EINVAL;
726 }
736fc37f 727 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7ed220d7
MD		 728 tmp |= RADEON_SW_INT_ENABLE;
729 }
6f34be50 730 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 731 atomic_read(&rdev->irq.pflip[0])) {
7ed220d7
MD		 732 tmp |= RADEON_CRTC_VBLANK_MASK;
733 }
6f34be50 734 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 735 atomic_read(&rdev->irq.pflip[1])) {
7ed220d7
MD		 736 tmp |= RADEON_CRTC2_VBLANK_MASK;
737 }
05a05c50
AD		 738 if (rdev->irq.hpd[0]) {
739 tmp |= RADEON_FP_DETECT_MASK;
740 }
741 if (rdev->irq.hpd[1]) {
742 tmp |= RADEON_FP2_DETECT_MASK;
743 }
7ed220d7
MD		 744 WREG32(RADEON_GEN_INT_CNTL, tmp);
745 return 0;
746}
747
9f022ddf
JG		 748void r100_irq_disable(struct radeon_device *rdev)
749{
750 u32 tmp;
751
752 WREG32(R_000040_GEN_INT_CNTL, 0);
753 /* Wait and acknowledge irq */
754 mdelay(1);
755 tmp = RREG32(R_000044_GEN_INT_STATUS);
756 WREG32(R_000044_GEN_INT_STATUS, tmp);
757}
758
cbdd4501 759static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 760{
761 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 762 uint32_t irq_mask = RADEON_SW_INT_TEST |
763 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
764 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 765
766 if (irqs) {
767 WREG32(RADEON_GEN_INT_STATUS, irqs);
768 }
769 return irqs & irq_mask;
770}
771
772int r100_irq_process(struct radeon_device *rdev)
773{
3e5cb98d 774 uint32_t status, msi_rearm;
d4877cf2 775 bool queue_hotplug = false;
7ed220d7
MD		 776
777 status = r100_irq_ack(rdev);
778 if (!status) {
779 return IRQ_NONE;
780 }
a513c184
JG		 781 if (rdev->shutdown) {
782 return IRQ_NONE;
783 }
7ed220d7
MD		 784 while (status) {
785 /* SW interrupt */
786 if (status & RADEON_SW_INT_TEST) {
7465280c 787 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7
MD		 788 }
789 /* Vertical blank interrupts */
790 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 791 if (rdev->irq.crtc_vblank_int[0]) {
792 drm_handle_vblank(rdev->ddev, 0);
793 rdev->pm.vblank_sync = true;
794 wake_up(&rdev->irq.vblank_queue);
795 }
736fc37f 796 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 797 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 798 }
799 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 800 if (rdev->irq.crtc_vblank_int[1]) {
801 drm_handle_vblank(rdev->ddev, 1);
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
804 }
736fc37f 805 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 806 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 807 }
05a05c50 808 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 809 queue_hotplug = true;
810 DRM_DEBUG("HPD1\n");
05a05c50
AD		 811 }
812 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 813 queue_hotplug = true;
814 DRM_DEBUG("HPD2\n");
05a05c50 815 }
7ed220d7
MD		 816 status = r100_irq_ack(rdev);
817 }
d4877cf2 818 if (queue_hotplug)
32c87fca 819 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 820 if (rdev->msi_enabled) {
821 switch (rdev->family) {
822 case CHIP_RS400:
823 case CHIP_RS480:
824 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
825 WREG32(RADEON_AIC_CNTL, msi_rearm);
826 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
827 break;
828 default:
b7f5b7de 829 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 830 break;
831 }
832 }
7ed220d7
MD		 833 return IRQ_HANDLED;
834}
835
836u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
837{
838 if (crtc == 0)
839 return RREG32(RADEON_CRTC_CRNT_FRAME);
840 else
841 return RREG32(RADEON_CRTC2_CRNT_FRAME);
842}
843
9e5b2af7
PN		 844/* Who ever call radeon_fence_emit should call ring_lock and ask
845 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 846void r100_fence_ring_emit(struct radeon_device *rdev,
847 struct radeon_fence *fence)
848{
e32eb50d 849 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 850
9e5b2af7
PN		 851 /* We have to make sure that caches are flushed before
852 * CPU might read something from VRAM. */
e32eb50d
CK		 853 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
854 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
855 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
856 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 857 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 858 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
859 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
860 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
861 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
cafe6609 862 RADEON_HDP_READ_BUFFER_INVALIDATE);
e32eb50d
CK		 863 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
864 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
771fe6b9 865 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 866 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
867 radeon_ring_write(ring, fence->seq);
868 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
869 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 870}
871
1654b817 872bool r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 873 struct radeon_ring *ring,
15d3332f 874 struct radeon_semaphore *semaphore,
7b1f2485 875 bool emit_wait)
15d3332f
CK		 876{
877 /* Unused on older asics, since we don't have semaphores or multiple rings */
878 BUG();
1654b817 879 return false;
15d3332f
CK		 880}
881
771fe6b9
JG		 882int r100_copy_blit(struct radeon_device *rdev,
883 uint64_t src_offset,
884 uint64_t dst_offset,
003cefe0 885 unsigned num_gpu_pages,
876dc9f3 886 struct radeon_fence **fence)
771fe6b9 887{
e32eb50d 888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9 889 uint32_t cur_pages;
003cefe0 890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 891 uint32_t pitch;
892 uint32_t stride_pixels;
893 unsigned ndw;
894 int num_loops;
895 int r = 0;
896
897 /* radeon limited to 16k stride */
898 stride_bytes &= 0x3fff;
899 /* radeon pitch is /64 */
900 pitch = stride_bytes / 64;
901 stride_pixels = stride_bytes / 4;
003cefe0 902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 903
904 /* Ask for enough room for blit + flush + fence */
905 ndw = 64 + (10 * num_loops);
e32eb50d 906 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 907 if (r) {
908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
909 return -EINVAL;
910 }
003cefe0
AD		 911 while (num_gpu_pages > 0) {
912 cur_pages = num_gpu_pages;
771fe6b9
JG		 913 if (cur_pages > 8191) {
914 cur_pages = 8191;
915 }
003cefe0 916 num_gpu_pages -= cur_pages;
771fe6b9
JG		 917
918 /* pages are in Y direction - height
919 page width in X direction - width */
e32eb50d
CK		 920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
921 radeon_ring_write(ring,
771fe6b9
JG		 922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
923 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
924 RADEON_GMC_SRC_CLIPPING |
925 RADEON_GMC_DST_CLIPPING |
926 RADEON_GMC_BRUSH_NONE |
927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
928 RADEON_GMC_SRC_DATATYPE_COLOR |
929 RADEON_ROP3_S |
930 RADEON_DP_SRC_SOURCE_MEMORY |
931 RADEON_GMC_CLR_CMP_CNTL_DIS |
932 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
936 radeon_ring_write(ring, 0);
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, num_gpu_pages);
939 radeon_ring_write(ring, num_gpu_pages);
940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
941 }
942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
945 radeon_ring_write(ring,
771fe6b9
JG		 946 RADEON_WAIT_2D_IDLECLEAN |
947 RADEON_WAIT_HOST_IDLECLEAN |
948 RADEON_WAIT_DMA_GUI_IDLE);
949 if (fence) {
876dc9f3 950 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
771fe6b9 951 }
e32eb50d 952 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 953 return r;
954}
955
45600232
JG		 956static int r100_cp_wait_for_idle(struct radeon_device *rdev)
957{
958 unsigned i;
959 u32 tmp;
960
961 for (i = 0; i < rdev->usec_timeout; i++) {
962 tmp = RREG32(R_000E40_RBBM_STATUS);
963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
964 return 0;
965 }
966 udelay(1);
967 }
968 return -1;
969}
970
f712812e 971void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 972{
973 int r;
974
e32eb50d 975 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 976 if (r) {
977 return;
978 }
e32eb50d
CK		 979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
980 radeon_ring_write(ring,
771fe6b9
JG		 981 RADEON_ISYNC_ANY2D_IDLE3D |
982 RADEON_ISYNC_ANY3D_IDLE2D |
983 RADEON_ISYNC_WAIT_IDLEGUI |
984 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
e32eb50d 985 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 986}
987
70967ab9
BH		 988
989/* Load the microcode for the CP */
990static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 991{
70967ab9
BH		 992 const char *fw_name = NULL;
993 int err;
771fe6b9 994
d9fdaafb 995 DRM_DEBUG_KMS("\n");
771fe6b9 996
771fe6b9
JG		 997 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
998 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
999 (rdev->family == CHIP_RS200)) {
1000 DRM_INFO("Loading R100 Microcode\n");
70967ab9 1001 fw_name = FIRMWARE_R100;
771fe6b9
JG		 1002 } else if ((rdev->family == CHIP_R200) ||
1003 (rdev->family == CHIP_RV250) ||
1004 (rdev->family == CHIP_RV280) ||
1005 (rdev->family == CHIP_RS300)) {
1006 DRM_INFO("Loading R200 Microcode\n");
70967ab9 1007 fw_name = FIRMWARE_R200;
771fe6b9
JG		 1008 } else if ((rdev->family == CHIP_R300) ||
1009 (rdev->family == CHIP_R350) ||
1010 (rdev->family == CHIP_RV350) ||
1011 (rdev->family == CHIP_RV380) ||
1012 (rdev->family == CHIP_RS400) ||
1013 (rdev->family == CHIP_RS480)) {
1014 DRM_INFO("Loading R300 Microcode\n");
70967ab9 1015 fw_name = FIRMWARE_R300;
771fe6b9
JG		 1016 } else if ((rdev->family == CHIP_R420) ||
1017 (rdev->family == CHIP_R423) ||
1018 (rdev->family == CHIP_RV410)) {
1019 DRM_INFO("Loading R400 Microcode\n");
70967ab9 1020 fw_name = FIRMWARE_R420;
771fe6b9
JG		 1021 } else if ((rdev->family == CHIP_RS690) ||
1022 (rdev->family == CHIP_RS740)) {
1023 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1024 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1025 } else if (rdev->family == CHIP_RS600) {
1026 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1027 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1028 } else if ((rdev->family == CHIP_RV515) ||
1029 (rdev->family == CHIP_R520) ||
1030 (rdev->family == CHIP_RV530) ||
1031 (rdev->family == CHIP_R580) ||
1032 (rdev->family == CHIP_RV560) ||
1033 (rdev->family == CHIP_RV570)) {
1034 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1035 fw_name = FIRMWARE_R520;
1036 }
1037
0a168933 1038 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
70967ab9
BH		 1039 if (err) {
1040 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1041 fw_name);
3ce0a23d 1042 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1043 printk(KERN_ERR
1044 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1045 rdev->me_fw->size, fw_name);
70967ab9 1046 err = -EINVAL;
3ce0a23d
JG		 1047 release_firmware(rdev->me_fw);
1048 rdev->me_fw = NULL;
70967ab9
BH		 1049 }
1050 return err;
1051}
d4550907 1052
ea31bf69
AD		 1053u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1054 struct radeon_ring *ring)
1055{
1056 u32 rptr;
1057
1058 if (rdev->wb.enabled)
1059 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1060 else
1061 rptr = RREG32(RADEON_CP_RB_RPTR);
1062
1063 return rptr;
1064}
1065
1066u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1067 struct radeon_ring *ring)
1068{
1069 u32 wptr;
1070
1071 wptr = RREG32(RADEON_CP_RB_WPTR);
1072
1073 return wptr;
1074}
1075
1076void r100_gfx_set_wptr(struct radeon_device *rdev,
1077 struct radeon_ring *ring)
1078{
1079 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1080 (void)RREG32(RADEON_CP_RB_WPTR);
1081}
1082
70967ab9
BH		 1083static void r100_cp_load_microcode(struct radeon_device *rdev)
1084{
1085 const __be32 *fw_data;
1086 int i, size;
1087
1088 if (r100_gui_wait_for_idle(rdev)) {
1089 printk(KERN_WARNING "Failed to wait GUI idle while "
1090 "programming pipes. Bad things might happen.\n");
1091 }
1092
3ce0a23d
JG		 1093 if (rdev->me_fw) {
1094 size = rdev->me_fw->size / 4;
1095 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1096 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1097 for (i = 0; i < size; i += 2) {
1098 WREG32(RADEON_CP_ME_RAM_DATAH,
1099 be32_to_cpup(&fw_data[i]));
1100 WREG32(RADEON_CP_ME_RAM_DATAL,
1101 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1102 }
1103 }
1104}
1105
1106int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1107{
e32eb50d 1108 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1109 unsigned rb_bufsz;
1110 unsigned rb_blksz;
1111 unsigned max_fetch;
1112 unsigned pre_write_timer;
1113 unsigned pre_write_limit;
1114 unsigned indirect2_start;
1115 unsigned indirect1_start;
1116 uint32_t tmp;
1117 int r;
1118
1119 if (r100_debugfs_cp_init(rdev)) {
1120 DRM_ERROR("Failed to register debugfs file for CP !\n");
1121 }
3ce0a23d 1122 if (!rdev->me_fw) {
70967ab9
BH		 1123 r = r100_cp_init_microcode(rdev);
1124 if (r) {
1125 DRM_ERROR("Failed to load firmware!\n");
1126 return r;
1127 }
1128 }
1129
771fe6b9 1130 /* Align ring size */
b72a8925 1131 rb_bufsz = order_base_2(ring_size / 8);
771fe6b9
JG		 1132 ring_size = (1 << (rb_bufsz + 1)) * 4;
1133 r100_cp_load_microcode(rdev);
e32eb50d 1134 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 1135 RADEON_CP_PACKET2);
771fe6b9
JG		 1136 if (r) {
1137 return r;
1138 }
1139 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1140 * the rptr copy in system ram */
1141 rb_blksz = 9;
1142 /* cp will read 128bytes at a time (4 dwords) */
1143 max_fetch = 1;
e32eb50d 1144 ring->align_mask = 16 - 1;
771fe6b9
JG		 1145 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1146 pre_write_timer = 64;
1147 /* Force CP_RB_WPTR write if written more than one time before the
1148 * delay expire
1149 */
1150 pre_write_limit = 0;
1151 /* Setup the cp cache like this (cache size is 96 dwords) :
1152 * RING 0 to 15
1153 * INDIRECT1 16 to 79
1154 * INDIRECT2 80 to 95
1155 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1156 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1157 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1158 * Idea being that most of the gpu cmd will be through indirect1 buffer
1159 * so it gets the bigger cache.
1160 */
1161 indirect2_start = 80;
1162 indirect1_start = 16;
1163 /* cp setup */
1164 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1165 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1166 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1167 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1168#ifdef __BIG_ENDIAN
1169 tmp |= RADEON_BUF_SWAP_32BIT;
1170#endif
724c80e1 1171 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1172
771fe6b9 1173 /* Set ring address */
e32eb50d
CK		 1174 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1175 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1176 /* Force read & write ptr to 0 */
724c80e1 1177 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1178 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1179 ring->wptr = 0;
1180 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1181
1182 /* set the wb address whether it's enabled or not */
1183 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1184 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1185 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1186
1187 if (rdev->wb.enabled)
1188 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1189 else {
1190 tmp |= RADEON_RB_NO_UPDATE;
1191 WREG32(R_000770_SCRATCH_UMSK, 0);
1192 }
1193
771fe6b9
JG		 1194 WREG32(RADEON_CP_RB_CNTL, tmp);
1195 udelay(10);
e32eb50d 1196 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1197 /* Set cp mode to bus mastering & enable cp*/
1198 WREG32(RADEON_CP_CSQ_MODE,
1199 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1200 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1201 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1202 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1203 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1204
1205 /* at this point everything should be setup correctly to enable master */
1206 pci_set_master(rdev->pdev);
1207
f712812e
AD		 1208 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1209 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1210 if (r) {
1211 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1212 return r;
1213 }
e32eb50d 1214 ring->ready = true;
53595338 1215 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
c7eff978 1216
16c58081
SK		 1217 if (!ring->rptr_save_reg /* not resuming from suspend */
1218 && radeon_ring_supports_scratch_reg(rdev, ring)) {
c7eff978
AD		 1219 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1220 if (r) {
1221 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1222 ring->rptr_save_reg = 0;
1223 }
1224 }
771fe6b9
JG		 1225 return 0;
1226}
1227
1228void r100_cp_fini(struct radeon_device *rdev)
1229{
45600232
JG		 1230 if (r100_cp_wait_for_idle(rdev)) {
1231 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1232 }
771fe6b9 1233 /* Disable ring */
a18d7ea1 1234 r100_cp_disable(rdev);
c7eff978 1235 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
e32eb50d 1236 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1237 DRM_INFO("radeon: cp finalized\n");
1238}
1239
1240void r100_cp_disable(struct radeon_device *rdev)
1241{
1242 /* Disable ring */
53595338 1243 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1244 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1245 WREG32(RADEON_CP_CSQ_MODE, 0);
1246 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1247 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1248 if (r100_gui_wait_for_idle(rdev)) {
1249 printk(KERN_WARNING "Failed to wait GUI idle while "
1250 "programming pipes. Bad things might happen.\n");
1251 }
1252}
1253
771fe6b9
JG		 1254/*
1255 * CS functions
1256 */
0242f74d
AD		 1257int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1258 struct radeon_cs_packet *pkt,
1259 unsigned idx,
1260 unsigned reg)
1261{
1262 int r;
1263 u32 tile_flags = 0;
1264 u32 tmp;
1265 struct radeon_cs_reloc *reloc;
1266 u32 value;
1267
012e976d 1268 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1269 if (r) {
1270 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1271 idx, reg);
c3ad63af 1272 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1273 return r;
1274 }
1275
1276 value = radeon_get_ib_value(p, idx);
1277 tmp = value & 0x003fffff;
1278 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1279
1280 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1281 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1282 tile_flags |= RADEON_DST_TILE_MACRO;
1283 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1284 if (reg == RADEON_SRC_PITCH_OFFSET) {
1285 DRM_ERROR("Cannot src blit from microtiled surface\n");
c3ad63af 1286 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1287 return -EINVAL;
1288 }
1289 tile_flags |= RADEON_DST_TILE_MICRO;
1290 }
1291
1292 tmp |= tile_flags;
1293 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1294 } else
1295 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1296 return 0;
1297}
1298
1299int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1300 struct radeon_cs_packet *pkt,
1301 int idx)
1302{
1303 unsigned c, i;
1304 struct radeon_cs_reloc *reloc;
1305 struct r100_cs_track *track;
1306 int r = 0;
1307 volatile uint32_t *ib;
1308 u32 idx_value;
1309
1310 ib = p->ib.ptr;
1311 track = (struct r100_cs_track *)p->track;
1312 c = radeon_get_ib_value(p, idx++) & 0x1F;
1313 if (c > 16) {
1314 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1315 pkt->opcode);
c3ad63af 1316 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1317 return -EINVAL;
1318 }
1319 track->num_arrays = c;
1320 for (i = 0; i < (c - 1); i+=2, idx+=3) {
012e976d 1321 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1322 if (r) {
1323 DRM_ERROR("No reloc for packet3 %d\n",
1324 pkt->opcode);
c3ad63af 1325 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1326 return r;
1327 }
1328 idx_value = radeon_get_ib_value(p, idx);
1329 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1330
1331 track->arrays[i + 0].esize = idx_value >> 8;
1332 track->arrays[i + 0].robj = reloc->robj;
1333 track->arrays[i + 0].esize &= 0x7F;
012e976d 1334 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1335 if (r) {
1336 DRM_ERROR("No reloc for packet3 %d\n",
1337 pkt->opcode);
c3ad63af 1338 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1339 return r;
1340 }
1341 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1342 track->arrays[i + 1].robj = reloc->robj;
1343 track->arrays[i + 1].esize = idx_value >> 24;
1344 track->arrays[i + 1].esize &= 0x7F;
1345 }
1346 if (c & 1) {
012e976d 1347 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1348 if (r) {
1349 DRM_ERROR("No reloc for packet3 %d\n",
1350 pkt->opcode);
c3ad63af 1351 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1352 return r;
1353 }
1354 idx_value = radeon_get_ib_value(p, idx);
1355 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1356 track->arrays[i + 0].robj = reloc->robj;
1357 track->arrays[i + 0].esize = idx_value >> 8;
1358 track->arrays[i + 0].esize &= 0x7F;
1359 }
1360 return r;
1361}
1362
771fe6b9
JG		 1363int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1364 struct radeon_cs_packet *pkt,
068a117c 1365 const unsigned *auth, unsigned n,
771fe6b9
JG		 1366 radeon_packet0_check_t check)
1367{
1368 unsigned reg;
1369 unsigned i, j, m;
1370 unsigned idx;
1371 int r;
1372
1373 idx = pkt->idx + 1;
1374 reg = pkt->reg;
068a117c
JG		 1375 /* Check that register fall into register range
1376 * determined by the number of entry (n) in the
1377 * safe register bitmap.
1378 */
771fe6b9
JG		 1379 if (pkt->one_reg_wr) {
1380 if ((reg >> 7) > n) {
1381 return -EINVAL;
1382 }
1383 } else {
1384 if (((reg + (pkt->count << 2)) >> 7) > n) {
1385 return -EINVAL;
1386 }
1387 }
1388 for (i = 0; i <= pkt->count; i++, idx++) {
1389 j = (reg >> 7);
1390 m = 1 << ((reg >> 2) & 31);
1391 if (auth[j] & m) {
1392 r = check(p, pkt, idx, reg);
1393 if (r) {
1394 return r;
1395 }
1396 }
1397 if (pkt->one_reg_wr) {
1398 if (!(auth[j] & m)) {
1399 break;
1400 }
1401 } else {
1402 reg += 4;
1403 }
1404 }
1405 return 0;
1406}
1407
531369e6
DA		 1408/**
1409 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1410 * @parser: parser structure holding parsing context.
1411 *
1412 * Userspace sends a special sequence for VLINE waits.
1413 * PACKET0 - VLINE_START_END + value
1414 * PACKET0 - WAIT_UNTIL +_value
1415 * RELOC (P3) - crtc_id in reloc.
1416 *
1417 * This function parses this and relocates the VLINE START END
1418 * and WAIT UNTIL packets to the correct crtc.
1419 * It also detects a switched off crtc and nulls out the
1420 * wait in that case.
1421 */
1422int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1423{
531369e6
DA		 1424 struct drm_mode_object *obj;
1425 struct drm_crtc *crtc;
1426 struct radeon_crtc *radeon_crtc;
1427 struct radeon_cs_packet p3reloc, waitreloc;
1428 int crtc_id;
1429 int r;
1430 uint32_t header, h_idx, reg;
513bcb46 1431 volatile uint32_t *ib;
531369e6 1432
f2e39221 1433 ib = p->ib.ptr;
531369e6
DA		 1434
1435 /* parse the wait until */
c38f34b5 1436 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
531369e6
DA		 1437 if (r)
1438 return r;
1439
1440 /* check its a wait until and only 1 count */
1441 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1442 waitreloc.count != 0) {
1443 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1444 return -EINVAL;
531369e6
DA		 1445 }
1446
513bcb46 1447 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1448 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1449 return -EINVAL;
531369e6
DA		 1450 }
1451
1452 /* jump over the NOP */
c38f34b5 1453 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1454 if (r)
1455 return r;
1456
1457 h_idx = p->idx - 2;
90ebd065
AD		 1458 p->idx += waitreloc.count + 2;
1459 p->idx += p3reloc.count + 2;
531369e6 1460
513bcb46
DA		 1461 header = radeon_get_ib_value(p, h_idx);
1462 crtc_id = radeon_get_ib_value(p, h_idx + 5);
4e872ae2 1463 reg = R100_CP_PACKET0_GET_REG(header);
531369e6
DA		 1464 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1465 if (!obj) {
1466 DRM_ERROR("cannot find crtc %d\n", crtc_id);
10e10d34 1467 return -ENOENT;
531369e6
DA		 1468 }
1469 crtc = obj_to_crtc(obj);
1470 radeon_crtc = to_radeon_crtc(crtc);
1471 crtc_id = radeon_crtc->crtc_id;
1472
1473 if (!crtc->enabled) {
1474 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1475 ib[h_idx + 2] = PACKET2(0);
1476 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1477 } else if (crtc_id == 1) {
1478 switch (reg) {
1479 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1480 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1481 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1482 break;
1483 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1484 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1485 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1486 break;
1487 default:
1488 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1489 return -EINVAL;
531369e6 1490 }
513bcb46
DA		 1491 ib[h_idx] = header;
1492 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1493 }
a3a88a66
PB		 1494
1495 return 0;
531369e6
DA		 1496}
1497
551ebd83
DA		 1498static int r100_get_vtx_size(uint32_t vtx_fmt)
1499{
1500 int vtx_size;
1501 vtx_size = 2;
1502 /* ordered according to bits in spec */
1503 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1504 vtx_size++;
1505 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1506 vtx_size += 3;
1507 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1508 vtx_size++;
1509 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1510 vtx_size++;
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1512 vtx_size += 3;
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1514 vtx_size++;
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1516 vtx_size++;
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1518 vtx_size += 2;
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1520 vtx_size += 2;
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1522 vtx_size++;
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1524 vtx_size += 2;
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1526 vtx_size++;
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1528 vtx_size += 2;
1529 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1530 vtx_size++;
1531 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1532 vtx_size++;
1533 /* blend weight */
1534 if (vtx_fmt & (0x7 << 15))
1535 vtx_size += (vtx_fmt >> 15) & 0x7;
1536 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1537 vtx_size += 3;
1538 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1539 vtx_size += 2;
1540 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1541 vtx_size++;
1542 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1543 vtx_size++;
1544 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1545 vtx_size++;
1546 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1547 vtx_size++;
1548 return vtx_size;
1549}
1550
771fe6b9 1551static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1552 struct radeon_cs_packet *pkt,
1553 unsigned idx, unsigned reg)
771fe6b9 1554{
771fe6b9 1555 struct radeon_cs_reloc *reloc;
551ebd83 1556 struct r100_cs_track *track;
771fe6b9
JG		 1557 volatile uint32_t *ib;
1558 uint32_t tmp;
771fe6b9 1559 int r;
551ebd83 1560 int i, face;
e024e110 1561 u32 tile_flags = 0;
513bcb46 1562 u32 idx_value;
771fe6b9 1563
f2e39221 1564 ib = p->ib.ptr;
551ebd83
DA		 1565 track = (struct r100_cs_track *)p->track;
1566
513bcb46
DA		 1567 idx_value = radeon_get_ib_value(p, idx);
1568
551ebd83
DA		 1569 switch (reg) {
1570 case RADEON_CRTC_GUI_TRIG_VLINE:
1571 r = r100_cs_packet_parse_vline(p);
1572 if (r) {
1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1574 idx, reg);
c3ad63af 1575 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1576 return r;
1577 }
1578 break;
771fe6b9
JG		 1579 /* FIXME: only allow PACKET3 blit? easier to check for out of
1580 * range access */
551ebd83
DA		 1581 case RADEON_DST_PITCH_OFFSET:
1582 case RADEON_SRC_PITCH_OFFSET:
1583 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1584 if (r)
1585 return r;
1586 break;
1587 case RADEON_RB3D_DEPTHOFFSET:
012e976d 1588 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1589 if (r) {
1590 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1591 idx, reg);
c3ad63af 1592 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1593 return r;
1594 }
1595 track->zb.robj = reloc->robj;
513bcb46 1596 track->zb.offset = idx_value;
40b4a759 1597 track->zb_dirty = true;
513bcb46 1598 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1599 break;
1600 case RADEON_RB3D_COLOROFFSET:
012e976d 1601 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1602 if (r) {
1603 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1604 idx, reg);
c3ad63af 1605 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1606 return r;
1607 }
1608 track->cb[0].robj = reloc->robj;
513bcb46 1609 track->cb[0].offset = idx_value;
40b4a759 1610 track->cb_dirty = true;
513bcb46 1611 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1612 break;
1613 case RADEON_PP_TXOFFSET_0:
1614 case RADEON_PP_TXOFFSET_1:
1615 case RADEON_PP_TXOFFSET_2:
1616 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
012e976d 1617 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1618 if (r) {
1619 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1620 idx, reg);
c3ad63af 1621 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1622 return r;
1623 }
f2746f83
AD		 1624 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1625 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1626 tile_flags |= RADEON_TXO_MACRO_TILE;
1627 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1628 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1629
1630 tmp = idx_value & ~(0x7 << 2);
1631 tmp |= tile_flags;
1632 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1633 } else
1634 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1635 track->textures[i].robj = reloc->robj;
40b4a759 1636 track->tex_dirty = true;
551ebd83
DA		 1637 break;
1638 case RADEON_PP_CUBIC_OFFSET_T0_0:
1639 case RADEON_PP_CUBIC_OFFSET_T0_1:
1640 case RADEON_PP_CUBIC_OFFSET_T0_2:
1641 case RADEON_PP_CUBIC_OFFSET_T0_3:
1642 case RADEON_PP_CUBIC_OFFSET_T0_4:
1643 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
012e976d 1644 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1645 if (r) {
1646 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1647 idx, reg);
c3ad63af 1648 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1649 return r;
1650 }
513bcb46
DA		 1651 track->textures[0].cube_info[i].offset = idx_value;
1652 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1653 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1654 track->tex_dirty = true;
551ebd83
DA		 1655 break;
1656 case RADEON_PP_CUBIC_OFFSET_T1_0:
1657 case RADEON_PP_CUBIC_OFFSET_T1_1:
1658 case RADEON_PP_CUBIC_OFFSET_T1_2:
1659 case RADEON_PP_CUBIC_OFFSET_T1_3:
1660 case RADEON_PP_CUBIC_OFFSET_T1_4:
1661 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
012e976d 1662 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1663 if (r) {
1664 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1665 idx, reg);
c3ad63af 1666 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1667 return r;
1668 }
513bcb46
DA		 1669 track->textures[1].cube_info[i].offset = idx_value;
1670 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1671 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1672 track->tex_dirty = true;
551ebd83
DA		 1673 break;
1674 case RADEON_PP_CUBIC_OFFSET_T2_0:
1675 case RADEON_PP_CUBIC_OFFSET_T2_1:
1676 case RADEON_PP_CUBIC_OFFSET_T2_2:
1677 case RADEON_PP_CUBIC_OFFSET_T2_3:
1678 case RADEON_PP_CUBIC_OFFSET_T2_4:
1679 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
012e976d 1680 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1681 if (r) {
1682 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1683 idx, reg);
c3ad63af 1684 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1685 return r;
1686 }
513bcb46
DA		 1687 track->textures[2].cube_info[i].offset = idx_value;
1688 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1689 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1690 track->tex_dirty = true;
551ebd83
DA		 1691 break;
1692 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1693 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1694 track->cb_dirty = true;
1695 track->zb_dirty = true;
551ebd83
DA		 1696 break;
1697 case RADEON_RB3D_COLORPITCH:
012e976d 1698 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1699 if (r) {
1700 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1701 idx, reg);
c3ad63af 1702 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1703 return r;
1704 }
c9068eb2
AD		 1705 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1706 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1707 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1708 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1709 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1710
1711 tmp = idx_value & ~(0x7 << 16);
1712 tmp |= tile_flags;
1713 ib[idx] = tmp;
1714 } else
1715 ib[idx] = idx_value;
e024e110 1716
513bcb46 1717 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1718 track->cb_dirty = true;
551ebd83
DA		 1719 break;
1720 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1721 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1722 track->zb_dirty = true;
551ebd83
DA		 1723 break;
1724 case RADEON_RB3D_CNTL:
513bcb46 1725 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1726 case 7:
1727 case 8:
1728 case 9:
1729 case 11:
1730 case 12:
1731 track->cb[0].cpp = 1;
e024e110 1732 break;
551ebd83
DA		 1733 case 3:
1734 case 4:
1735 case 15:
1736 track->cb[0].cpp = 2;
1737 break;
1738 case 6:
1739 track->cb[0].cpp = 4;
1740 break;
1741 default:
1742 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1743 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1744 return -EINVAL;
1745 }
513bcb46 1746 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1747 track->cb_dirty = true;
1748 track->zb_dirty = true;
551ebd83
DA		 1749 break;
1750 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1751 switch (idx_value & 0xf) {
551ebd83
DA		 1752 case 0:
1753 track->zb.cpp = 2;
1754 break;
1755 case 2:
1756 case 3:
1757 case 4:
1758 case 5:
1759 case 9:
1760 case 11:
1761 track->zb.cpp = 4;
17782d99 1762 break;
771fe6b9 1763 default:
771fe6b9
JG		 1764 break;
1765 }
40b4a759 1766 track->zb_dirty = true;
551ebd83
DA		 1767 break;
1768 case RADEON_RB3D_ZPASS_ADDR:
012e976d 1769 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1770 if (r) {
1771 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1772 idx, reg);
c3ad63af 1773 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1774 return r;
1775 }
513bcb46 1776 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1777 break;
1778 case RADEON_PP_CNTL:
1779 {
513bcb46 1780 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1781 for (i = 0; i < track->num_texture; i++)
1782 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1783 track->tex_dirty = true;
551ebd83
DA		 1784 }
1785 break;
1786 case RADEON_SE_VF_CNTL:
513bcb46 1787 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1788 break;
1789 case RADEON_SE_VTX_FMT:
513bcb46 1790 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1791 break;
1792 case RADEON_PP_TEX_SIZE_0:
1793 case RADEON_PP_TEX_SIZE_1:
1794 case RADEON_PP_TEX_SIZE_2:
1795 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1796 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1797 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1798 track->tex_dirty = true;
551ebd83
DA		 1799 break;
1800 case RADEON_PP_TEX_PITCH_0:
1801 case RADEON_PP_TEX_PITCH_1:
1802 case RADEON_PP_TEX_PITCH_2:
1803 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1804 track->textures[i].pitch = idx_value + 32;
40b4a759 1805 track->tex_dirty = true;
551ebd83
DA		 1806 break;
1807 case RADEON_PP_TXFILTER_0:
1808 case RADEON_PP_TXFILTER_1:
1809 case RADEON_PP_TXFILTER_2:
1810 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1812 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1813 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1814 if (tmp == 2 || tmp == 6)
1815 track->textures[i].roundup_w = false;
513bcb46 1816 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1817 if (tmp == 2 || tmp == 6)
1818 track->textures[i].roundup_h = false;
40b4a759 1819 track->tex_dirty = true;
551ebd83
DA		 1820 break;
1821 case RADEON_PP_TXFORMAT_0:
1822 case RADEON_PP_TXFORMAT_1:
1823 case RADEON_PP_TXFORMAT_2:
1824 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1825 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1826 track->textures[i].use_pitch = 1;
1827 } else {
1828 track->textures[i].use_pitch = 0;
513bcb46
DA		 1829 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1830 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1831 }
513bcb46 1832 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1833 track->textures[i].tex_coord_type = 2;
513bcb46 1834 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1835 case RADEON_TXFORMAT_I8:
1836 case RADEON_TXFORMAT_RGB332:
1837 case RADEON_TXFORMAT_Y8:
1838 track->textures[i].cpp = 1;
f9da52d5 1839 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1840 break;
1841 case RADEON_TXFORMAT_AI88:
1842 case RADEON_TXFORMAT_ARGB1555:
1843 case RADEON_TXFORMAT_RGB565:
1844 case RADEON_TXFORMAT_ARGB4444:
1845 case RADEON_TXFORMAT_VYUY422:
1846 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1847 case RADEON_TXFORMAT_SHADOW16:
1848 case RADEON_TXFORMAT_LDUDV655:
1849 case RADEON_TXFORMAT_DUDV88:
1850 track->textures[i].cpp = 2;
f9da52d5 1851 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1852 break;
551ebd83
DA		 1853 case RADEON_TXFORMAT_ARGB8888:
1854 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1855 case RADEON_TXFORMAT_SHADOW32:
1856 case RADEON_TXFORMAT_LDUDUV8888:
1857 track->textures[i].cpp = 4;
f9da52d5 1858 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1859 break;
d785d78b
DA		 1860 case RADEON_TXFORMAT_DXT1:
1861 track->textures[i].cpp = 1;
1862 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1863 break;
1864 case RADEON_TXFORMAT_DXT23:
1865 case RADEON_TXFORMAT_DXT45:
1866 track->textures[i].cpp = 1;
1867 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1868 break;
551ebd83 1869 }
513bcb46
DA		 1870 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1871 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1872 track->tex_dirty = true;
551ebd83
DA		 1873 break;
1874 case RADEON_PP_CUBIC_FACES_0:
1875 case RADEON_PP_CUBIC_FACES_1:
1876 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1877 tmp = idx_value;
551ebd83
DA		 1878 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1879 for (face = 0; face < 4; face++) {
1880 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1881 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1882 }
40b4a759 1883 track->tex_dirty = true;
551ebd83
DA		 1884 break;
1885 default:
1886 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1887 reg, idx);
1888 return -EINVAL;
771fe6b9
JG		 1889 }
1890 return 0;
1891}
1892
068a117c
JG		 1893int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1894 struct radeon_cs_packet *pkt,
4c788679 1895 struct radeon_bo *robj)
068a117c 1896{
068a117c 1897 unsigned idx;
513bcb46 1898 u32 value;
068a117c 1899 idx = pkt->idx + 1;
513bcb46 1900 value = radeon_get_ib_value(p, idx + 2);
4c788679 1901 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1902 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1903 "(need %u have %lu) !\n",
513bcb46 1904 value + 1,
4c788679 1905 radeon_bo_size(robj));
068a117c
JG		 1906 return -EINVAL;
1907 }
1908 return 0;
1909}
1910
771fe6b9
JG		 1911static int r100_packet3_check(struct radeon_cs_parser *p,
1912 struct radeon_cs_packet *pkt)
1913{
771fe6b9 1914 struct radeon_cs_reloc *reloc;
551ebd83 1915 struct r100_cs_track *track;
771fe6b9 1916 unsigned idx;
771fe6b9
JG		 1917 volatile uint32_t *ib;
1918 int r;
1919
f2e39221 1920 ib = p->ib.ptr;
771fe6b9 1921 idx = pkt->idx + 1;
551ebd83 1922 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1923 switch (pkt->opcode) {
1924 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1925 r = r100_packet3_load_vbpntr(p, pkt, idx);
1926 if (r)
1927 return r;
771fe6b9
JG		 1928 break;
1929 case PACKET3_INDX_BUFFER:
012e976d 1930 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1931 if (r) {
1932 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1933 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1934 return r;
1935 }
513bcb46 1936 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1937 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1938 if (r) {
1939 return r;
1940 }
771fe6b9
JG		 1941 break;
1942 case 0x23:
771fe6b9 1943 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
012e976d 1944 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1945 if (r) {
1946 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1947 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1948 return r;
1949 }
513bcb46 1950 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1951 track->num_arrays = 1;
513bcb46 1952 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1953
1954 track->arrays[0].robj = reloc->robj;
1955 track->arrays[0].esize = track->vtx_size;
1956
513bcb46 1957 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1958
513bcb46 1959 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1960 track->immd_dwords = pkt->count - 1;
1961 r = r100_cs_track_check(p->rdev, track);
1962 if (r)
1963 return r;
771fe6b9
JG		 1964 break;
1965 case PACKET3_3D_DRAW_IMMD:
513bcb46 1966 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1967 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1968 return -EINVAL;
1969 }
cf57fc7a 1970 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1972 track->immd_dwords = pkt->count - 1;
1973 r = r100_cs_track_check(p->rdev, track);
1974 if (r)
1975 return r;
1976 break;
771fe6b9
JG		 1977 /* triggers drawing using in-packet vertex data */
1978 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1979 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1980 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1981 return -EINVAL;
1982 }
513bcb46 1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1984 track->immd_dwords = pkt->count;
1985 r = r100_cs_track_check(p->rdev, track);
1986 if (r)
1987 return r;
1988 break;
771fe6b9
JG		 1989 /* triggers drawing using in-packet vertex data */
1990 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1991 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1992 r = r100_cs_track_check(p->rdev, track);
1993 if (r)
1994 return r;
1995 break;
771fe6b9
JG		 1996 /* triggers drawing of vertex buffers setup elsewhere */
1997 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1999 r = r100_cs_track_check(p->rdev, track);
2000 if (r)
2001 return r;
2002 break;
771fe6b9
JG		 2003 /* triggers drawing using indices to vertex buffer */
2004 case PACKET3_3D_DRAW_VBUF:
513bcb46 2005 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2006 r = r100_cs_track_check(p->rdev, track);
2007 if (r)
2008 return r;
2009 break;
771fe6b9
JG		 2010 /* triggers drawing of vertex buffers setup elsewhere */
2011 case PACKET3_3D_DRAW_INDX:
513bcb46 2012 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2013 r = r100_cs_track_check(p->rdev, track);
2014 if (r)
2015 return r;
2016 break;
771fe6b9 2017 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 2018 case PACKET3_3D_CLEAR_HIZ:
2019 case PACKET3_3D_CLEAR_ZMASK:
2020 if (p->rdev->hyperz_filp != p->filp)
2021 return -EINVAL;
2022 break;
771fe6b9
JG		 2023 case PACKET3_NOP:
2024 break;
2025 default:
2026 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2027 return -EINVAL;
2028 }
2029 return 0;
2030}
2031
2032int r100_cs_parse(struct radeon_cs_parser *p)
2033{
2034 struct radeon_cs_packet pkt;
9f022ddf 2035 struct r100_cs_track *track;
771fe6b9
JG		 2036 int r;
2037
9f022ddf 2038 track = kzalloc(sizeof(*track), GFP_KERNEL);
ce067913
DC		 2039 if (!track)
2040 return -ENOMEM;
9f022ddf
JG		 2041 r100_cs_track_clear(p->rdev, track);
2042 p->track = track;
771fe6b9 2043 do {
c38f34b5 2044 r = radeon_cs_packet_parse(p, &pkt, p->idx);
771fe6b9
JG		 2045 if (r) {
2046 return r;
2047 }
2048 p->idx += pkt.count + 2;
2049 switch (pkt.type) {
4e872ae2 2050 case RADEON_PACKET_TYPE0:
66b3543e
IH		 2051 if (p->rdev->family >= CHIP_R200)
2052 r = r100_cs_parse_packet0(p, &pkt,
2053 p->rdev->config.r100.reg_safe_bm,
2054 p->rdev->config.r100.reg_safe_bm_size,
2055 &r200_packet0_check);
2056 else
2057 r = r100_cs_parse_packet0(p, &pkt,
2058 p->rdev->config.r100.reg_safe_bm,
2059 p->rdev->config.r100.reg_safe_bm_size,
2060 &r100_packet0_check);
2061 break;
4e872ae2 2062 case RADEON_PACKET_TYPE2:
66b3543e 2063 break;
4e872ae2 2064 case RADEON_PACKET_TYPE3:
66b3543e
IH		 2065 r = r100_packet3_check(p, &pkt);
2066 break;
2067 default:
2068 DRM_ERROR("Unknown packet type %d !\n",
2069 pkt.type);
2070 return -EINVAL;
771fe6b9 2071 }
66b3543e 2072 if (r)
771fe6b9 2073 return r;
771fe6b9
JG		 2074 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2075 return 0;
2076}
2077
0242f74d 2078static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
771fe6b9 2079{
0242f74d
AD		 2080 DRM_ERROR("pitch %d\n", t->pitch);
2081 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2082 DRM_ERROR("width %d\n", t->width);
2083 DRM_ERROR("width_11 %d\n", t->width_11);
2084 DRM_ERROR("height %d\n", t->height);
2085 DRM_ERROR("height_11 %d\n", t->height_11);
2086 DRM_ERROR("num levels %d\n", t->num_levels);
2087 DRM_ERROR("depth %d\n", t->txdepth);
2088 DRM_ERROR("bpp %d\n", t->cpp);
2089 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2090 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2091 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2092 DRM_ERROR("compress format %d\n", t->compress_format);
771fe6b9
JG		 2093}
2094
0242f74d 2095static int r100_track_compress_size(int compress_format, int w, int h)
771fe6b9 2096{
0242f74d
AD		 2097 int block_width, block_height, block_bytes;
2098 int wblocks, hblocks;
2099 int min_wblocks;
2100 int sz;
771fe6b9 2101
0242f74d
AD		 2102 block_width = 4;
2103 block_height = 4;
2104
2105 switch (compress_format) {
2106 case R100_TRACK_COMP_DXT1:
2107 block_bytes = 8;
2108 min_wblocks = 4;
2109 break;
2110 default:
2111 case R100_TRACK_COMP_DXT35:
2112 block_bytes = 16;
2113 min_wblocks = 2;
2114 break;
771fe6b9 2115 }
0242f74d
AD		 2116
2117 hblocks = (h + block_height - 1) / block_height;
2118 wblocks = (w + block_width - 1) / block_width;
2119 if (wblocks < min_wblocks)
2120 wblocks = min_wblocks;
2121 sz = wblocks * hblocks * block_bytes;
2122 return sz;
771fe6b9
JG		 2123}
2124
0242f74d
AD		 2125static int r100_cs_track_cube(struct radeon_device *rdev,
2126 struct r100_cs_track *track, unsigned idx)
771fe6b9 2127{
0242f74d
AD		 2128 unsigned face, w, h;
2129 struct radeon_bo *cube_robj;
2130 unsigned long size;
2131 unsigned compress_format = track->textures[idx].compress_format;
771fe6b9 2132
0242f74d
AD		 2133 for (face = 0; face < 5; face++) {
2134 cube_robj = track->textures[idx].cube_info[face].robj;
2135 w = track->textures[idx].cube_info[face].width;
2136 h = track->textures[idx].cube_info[face].height;
771fe6b9 2137
0242f74d
AD		 2138 if (compress_format) {
2139 size = r100_track_compress_size(compress_format, w, h);
2140 } else
2141 size = w * h;
2142 size *= track->textures[idx].cpp;
2143
2144 size += track->textures[idx].cube_info[face].offset;
2145
2146 if (size > radeon_bo_size(cube_robj)) {
2147 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2148 size, radeon_bo_size(cube_robj));
2149 r100_cs_track_texture_print(&track->textures[idx]);
2150 return -1;
771fe6b9 2151 }
771fe6b9 2152 }
0242f74d 2153 return 0;
771fe6b9
JG		 2154}
2155
0242f74d
AD		 2156static int r100_cs_track_texture_check(struct radeon_device *rdev,
2157 struct r100_cs_track *track)
771fe6b9 2158{
0242f74d
AD		 2159 struct radeon_bo *robj;
2160 unsigned long size;
2161 unsigned u, i, w, h, d;
2162 int ret;
771fe6b9 2163
0242f74d
AD		 2164 for (u = 0; u < track->num_texture; u++) {
2165 if (!track->textures[u].enabled)
2166 continue;
2167 if (track->textures[u].lookup_disable)
2168 continue;
2169 robj = track->textures[u].robj;
2170 if (robj == NULL) {
2171 DRM_ERROR("No texture bound to unit %u\n", u);
2172 return -EINVAL;
771fe6b9 2173 }
0242f74d
AD		 2174 size = 0;
2175 for (i = 0; i <= track->textures[u].num_levels; i++) {
2176 if (track->textures[u].use_pitch) {
2177 if (rdev->family < CHIP_R300)
2178 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2179 else
2180 w = track->textures[u].pitch / (1 << i);
2181 } else {
2182 w = track->textures[u].width;
2183 if (rdev->family >= CHIP_RV515)
2184 w |= track->textures[u].width_11;
2185 w = w / (1 << i);
2186 if (track->textures[u].roundup_w)
2187 w = roundup_pow_of_two(w);
2188 }
2189 h = track->textures[u].height;
2190 if (rdev->family >= CHIP_RV515)
2191 h |= track->textures[u].height_11;
2192 h = h / (1 << i);
2193 if (track->textures[u].roundup_h)
2194 h = roundup_pow_of_two(h);
2195 if (track->textures[u].tex_coord_type == 1) {
2196 d = (1 << track->textures[u].txdepth) / (1 << i);
2197 if (!d)
2198 d = 1;
2199 } else {
2200 d = 1;
2201 }
2202 if (track->textures[u].compress_format) {
771fe6b9 2203
0242f74d
AD		 2204 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2205 /* compressed textures are block based */
2206 } else
2207 size += w * h * d;
2208 }
2209 size *= track->textures[u].cpp;
771fe6b9 2210
0242f74d
AD		 2211 switch (track->textures[u].tex_coord_type) {
2212 case 0:
2213 case 1:
2214 break;
2215 case 2:
2216 if (track->separate_cube) {
2217 ret = r100_cs_track_cube(rdev, track, u);
2218 if (ret)
2219 return ret;
2220 } else
2221 size *= 6;
2222 break;
2223 default:
2224 DRM_ERROR("Invalid texture coordinate type %u for unit "
2225 "%u\n", track->textures[u].tex_coord_type, u);
2226 return -EINVAL;
2227 }
2228 if (size > radeon_bo_size(robj)) {
2229 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2230 "%lu\n", u, size, radeon_bo_size(robj));
2231 r100_cs_track_texture_print(&track->textures[u]);
2232 return -EINVAL;
771fe6b9 2233 }
771fe6b9 2234 }
0242f74d 2235 return 0;
771fe6b9
JG		 2236}
2237
0242f74d 2238int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
771fe6b9
JG		 2239{
2240 unsigned i;
0242f74d
AD		 2241 unsigned long size;
2242 unsigned prim_walk;
2243 unsigned nverts;
2244 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
771fe6b9 2245
0242f74d
AD		 2246 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2247 !track->blend_read_enable)
2248 num_cb = 0;
2249
2250 for (i = 0; i < num_cb; i++) {
2251 if (track->cb[i].robj == NULL) {
2252 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2253 return -EINVAL;
2254 }
2255 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2256 size += track->cb[i].offset;
2257 if (size > radeon_bo_size(track->cb[i].robj)) {
2258 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2259 "(need %lu have %lu) !\n", i, size,
2260 radeon_bo_size(track->cb[i].robj));
2261 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2262 i, track->cb[i].pitch, track->cb[i].cpp,
2263 track->cb[i].offset, track->maxy);
2264 return -EINVAL;
771fe6b9 2265 }
771fe6b9 2266 }
0242f74d 2267 track->cb_dirty = false;
771fe6b9 2268
0242f74d
AD		 2269 if (track->zb_dirty && track->z_enabled) {
2270 if (track->zb.robj == NULL) {
2271 DRM_ERROR("[drm] No buffer for z buffer !\n");
2272 return -EINVAL;
2273 }
2274 size = track->zb.pitch * track->zb.cpp * track->maxy;
2275 size += track->zb.offset;
2276 if (size > radeon_bo_size(track->zb.robj)) {
2277 DRM_ERROR("[drm] Buffer too small for z buffer "
2278 "(need %lu have %lu) !\n", size,
2279 radeon_bo_size(track->zb.robj));
2280 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2281 track->zb.pitch, track->zb.cpp,
2282 track->zb.offset, track->maxy);
2283 return -EINVAL;
2284 }
225758d8 2285 }
0242f74d 2286 track->zb_dirty = false;
771fe6b9 2287
0242f74d
AD		 2288 if (track->aa_dirty && track->aaresolve) {
2289 if (track->aa.robj == NULL) {
2290 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2291 return -EINVAL;
2292 }
2293 /* I believe the format comes from colorbuffer0. */
2294 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2295 size += track->aa.offset;
2296 if (size > radeon_bo_size(track->aa.robj)) {
2297 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2298 "(need %lu have %lu) !\n", i, size,
2299 radeon_bo_size(track->aa.robj));
2300 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2301 i, track->aa.pitch, track->cb[0].cpp,
2302 track->aa.offset, track->maxy);
2303 return -EINVAL;
2304 }
2305 }
2306 track->aa_dirty = false;
771fe6b9 2307
0242f74d
AD		 2308 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2309 if (track->vap_vf_cntl & (1 << 14)) {
2310 nverts = track->vap_alt_nverts;
2311 } else {
2312 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2739d49c 2313 }
0242f74d
AD		 2314 switch (prim_walk) {
2315 case 1:
2316 for (i = 0; i < track->num_arrays; i++) {
2317 size = track->arrays[i].esize * track->max_indx * 4;
2318 if (track->arrays[i].robj == NULL) {
2319 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2320 "bound\n", prim_walk, i);
2321 return -EINVAL;
2322 }
2323 if (size > radeon_bo_size(track->arrays[i].robj)) {
2324 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2325 "need %lu dwords have %lu dwords\n",
2326 prim_walk, i, size >> 2,
2327 radeon_bo_size(track->arrays[i].robj)
2328 >> 2);
2329 DRM_ERROR("Max indices %u\n", track->max_indx);
2330 return -EINVAL;
2331 }
771fe6b9 2332 }
0242f74d
AD		 2333 break;
2334 case 2:
2335 for (i = 0; i < track->num_arrays; i++) {
2336 size = track->arrays[i].esize * (nverts - 1) * 4;
2337 if (track->arrays[i].robj == NULL) {
2338 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2339 "bound\n", prim_walk, i);
2340 return -EINVAL;
2341 }
2342 if (size > radeon_bo_size(track->arrays[i].robj)) {
2343 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2344 "need %lu dwords have %lu dwords\n",
2345 prim_walk, i, size >> 2,
2346 radeon_bo_size(track->arrays[i].robj)
2347 >> 2);
2348 return -EINVAL;
2349 }
771fe6b9 2350 }
0242f74d
AD		 2351 break;
2352 case 3:
2353 size = track->vtx_size * nverts;
2354 if (size != track->immd_dwords) {
2355 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2356 track->immd_dwords, size);
2357 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2358 nverts, track->vtx_size);
2359 return -EINVAL;
771fe6b9 2360 }
0242f74d
AD		 2361 break;
2362 default:
2363 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2364 prim_walk);
2365 return -EINVAL;
2a0f8918
DA		 2366 }
2367
0242f74d
AD		 2368 if (track->tex_dirty) {
2369 track->tex_dirty = false;
2370 return r100_cs_track_texture_check(rdev, track);
2a0f8918 2371 }
0242f74d 2372 return 0;
2a0f8918
DA		 2373}
2374
0242f74d 2375void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2a0f8918 2376{
0242f74d 2377 unsigned i, face;
2a0f8918 2378
0242f74d
AD		 2379 track->cb_dirty = true;
2380 track->zb_dirty = true;
2381 track->tex_dirty = true;
2382 track->aa_dirty = true;
b7d8cce5 2383
0242f74d
AD		 2384 if (rdev->family < CHIP_R300) {
2385 track->num_cb = 1;
2386 if (rdev->family <= CHIP_RS200)
2387 track->num_texture = 3;
7a50f01a 2388 else
0242f74d
AD		 2389 track->num_texture = 6;
2390 track->maxy = 2048;
2391 track->separate_cube = 1;
28d52043 2392 } else {
0242f74d
AD		 2393 track->num_cb = 4;
2394 track->num_texture = 16;
2395 track->maxy = 4096;
2396 track->separate_cube = 0;
2397 track->aaresolve = false;
2398 track->aa.robj = NULL;
28d52043 2399 }
2a0f8918 2400
0242f74d
AD		 2401 for (i = 0; i < track->num_cb; i++) {
2402 track->cb[i].robj = NULL;
2403 track->cb[i].pitch = 8192;
2404 track->cb[i].cpp = 16;
2405 track->cb[i].offset = 0;
771fe6b9 2406 }
0242f74d
AD		 2407 track->z_enabled = true;
2408 track->zb.robj = NULL;
2409 track->zb.pitch = 8192;
2410 track->zb.cpp = 4;
2411 track->zb.offset = 0;
2412 track->vtx_size = 0x7F;
2413 track->immd_dwords = 0xFFFFFFFFUL;
2414 track->num_arrays = 11;
2415 track->max_indx = 0x00FFFFFFUL;
2416 for (i = 0; i < track->num_arrays; i++) {
2417 track->arrays[i].robj = NULL;
2418 track->arrays[i].esize = 0x7F;
771fe6b9 2419 }
0242f74d
AD		 2420 for (i = 0; i < track->num_texture; i++) {
2421 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2422 track->textures[i].pitch = 16536;
2423 track->textures[i].width = 16536;
2424 track->textures[i].height = 16536;
2425 track->textures[i].width_11 = 1 << 11;
2426 track->textures[i].height_11 = 1 << 11;
2427 track->textures[i].num_levels = 12;
2428 if (rdev->family <= CHIP_RS200) {
2429 track->textures[i].tex_coord_type = 0;
2430 track->textures[i].txdepth = 0;
2431 } else {
2432 track->textures[i].txdepth = 16;
2433 track->textures[i].tex_coord_type = 1;
2434 }
2435 track->textures[i].cpp = 64;
2436 track->textures[i].robj = NULL;
2437 /* CS IB emission code makes sure texture unit are disabled */
2438 track->textures[i].enabled = false;
2439 track->textures[i].lookup_disable = false;
2440 track->textures[i].roundup_w = true;
2441 track->textures[i].roundup_h = true;
2442 if (track->separate_cube)
2443 for (face = 0; face < 5; face++) {
2444 track->textures[i].cube_info[face].robj = NULL;
2445 track->textures[i].cube_info[face].width = 16536;
2446 track->textures[i].cube_info[face].height = 16536;
2447 track->textures[i].cube_info[face].offset = 0;
2448 }
771fe6b9
JG		 2449 }
2450}
2451
0242f74d
AD		 2452/*
2453 * Global GPU functions
2454 */
1109ca09 2455static void r100_errata(struct radeon_device *rdev)
771fe6b9 2456{
0242f74d 2457 rdev->pll_errata = 0;
771fe6b9 2458
0242f74d
AD		 2459 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2460 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2461 }
771fe6b9 2462
0242f74d
AD		 2463 if (rdev->family == CHIP_RV100 ||
2464 rdev->family == CHIP_RS100 ||
2465 rdev->family == CHIP_RS200) {
2466 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2467 }
771fe6b9
JG		 2468}
2469
1109ca09 2470static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
771fe6b9 2471{
0242f74d
AD		 2472 unsigned i;
2473 uint32_t tmp;
771fe6b9 2474
0242f74d
AD		 2475 for (i = 0; i < rdev->usec_timeout; i++) {
2476 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2477 if (tmp >= n) {
2478 return 0;
2479 }
2480 DRM_UDELAY(1);
771fe6b9 2481 }
0242f74d 2482 return -1;
771fe6b9
JG		 2483}
2484
0242f74d 2485int r100_gui_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2486{
771fe6b9 2487 unsigned i;
0242f74d 2488 uint32_t tmp;
771fe6b9 2489
0242f74d
AD		 2490 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2491 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2492 " Bad things might happen.\n");
771fe6b9 2493 }
0242f74d
AD		 2494 for (i = 0; i < rdev->usec_timeout; i++) {
2495 tmp = RREG32(RADEON_RBBM_STATUS);
2496 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2497 return 0;
2498 }
2499 DRM_UDELAY(1);
771fe6b9 2500 }
0242f74d 2501 return -1;
771fe6b9
JG		 2502}
2503
0242f74d 2504int r100_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2505{
0242f74d 2506 unsigned i;
771fe6b9
JG		 2507 uint32_t tmp;
2508
0242f74d
AD		 2509 for (i = 0; i < rdev->usec_timeout; i++) {
2510 /* read MC_STATUS */
2511 tmp = RREG32(RADEON_MC_STATUS);
2512 if (tmp & RADEON_MC_IDLE) {
2513 return 0;
2514 }
2515 DRM_UDELAY(1);
2516 }
2517 return -1;
771fe6b9
JG		 2518}
2519
0242f74d 2520bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2521{
0242f74d 2522 u32 rbbm_status;
771fe6b9 2523
0242f74d
AD		 2524 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2525 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2526 radeon_ring_lockup_update(ring);
2527 return false;
2528 }
2529 /* force CP activities */
2530 radeon_ring_force_activity(rdev, ring);
2531 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2532}
2533
74da01dc
AD		 2534/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2535void r100_enable_bm(struct radeon_device *rdev)
2536{
2537 uint32_t tmp;
2538 /* Enable bus mastering */
2539 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2540 WREG32(RADEON_BUS_CNTL, tmp);
2541}
2542
0242f74d 2543void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2544{
0242f74d
AD		 2545 u32 tmp;
2546
2547 /* disable bus mastering */
2548 tmp = RREG32(R_000030_BUS_CNTL);
2549 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2550 mdelay(1);
2551 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2552 mdelay(1);
2553 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2554 tmp = RREG32(RADEON_BUS_CNTL);
2555 mdelay(1);
2556 pci_clear_master(rdev->pdev);
2557 mdelay(1);
771fe6b9 2558}
e024e110 2559
0242f74d 2560int r100_asic_reset(struct radeon_device *rdev)
e024e110 2561{
0242f74d
AD		 2562 struct r100_mc_save save;
2563 u32 status, tmp;
2564 int ret = 0;
e024e110 2565
0242f74d
AD		 2566 status = RREG32(R_000E40_RBBM_STATUS);
2567 if (!G_000E40_GUI_ACTIVE(status)) {
2568 return 0;
e024e110 2569 }
0242f74d
AD		 2570 r100_mc_stop(rdev, &save);
2571 status = RREG32(R_000E40_RBBM_STATUS);
2572 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2573 /* stop CP */
2574 WREG32(RADEON_CP_CSQ_CNTL, 0);
2575 tmp = RREG32(RADEON_CP_RB_CNTL);
2576 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2577 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2578 WREG32(RADEON_CP_RB_WPTR, 0);
2579 WREG32(RADEON_CP_RB_CNTL, tmp);
2580 /* save PCI state */
2581 pci_save_state(rdev->pdev);
2582 /* disable bus mastering */
2583 r100_bm_disable(rdev);
2584 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2585 S_0000F0_SOFT_RESET_RE(1) |
2586 S_0000F0_SOFT_RESET_PP(1) |
2587 S_0000F0_SOFT_RESET_RB(1));
2588 RREG32(R_0000F0_RBBM_SOFT_RESET);
2589 mdelay(500);
2590 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2591 mdelay(1);
2592 status = RREG32(R_000E40_RBBM_STATUS);
2593 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2594 /* reset CP */
2595 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2596 RREG32(R_0000F0_RBBM_SOFT_RESET);
2597 mdelay(500);
2598 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2599 mdelay(1);
2600 status = RREG32(R_000E40_RBBM_STATUS);
2601 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2602 /* restore PCI & busmastering */
2603 pci_restore_state(rdev->pdev);
2604 r100_enable_bm(rdev);
2605 /* Check if GPU is idle */
2606 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2607 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2608 dev_err(rdev->dev, "failed to reset GPU\n");
2609 ret = -1;
2610 } else
2611 dev_info(rdev->dev, "GPU reset succeed\n");
2612 r100_mc_resume(rdev, &save);
2613 return ret;
2614}
e024e110 2615
0242f74d
AD		 2616void r100_set_common_regs(struct radeon_device *rdev)
2617{
2618 struct drm_device *dev = rdev->ddev;
2619 bool force_dac2 = false;
2620 u32 tmp;
f5c5f040 2621
0242f74d
AD		 2622 /* set these so they don't interfere with anything */
2623 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2624 WREG32(RADEON_SUBPIC_CNTL, 0);
2625 WREG32(RADEON_VIPH_CONTROL, 0);
2626 WREG32(RADEON_I2C_CNTL_1, 0);
2627 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2628 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2629 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
f5c5f040 2630
0242f74d
AD		 2631 /* always set up dac2 on rn50 and some rv100 as lots
2632 * of servers seem to wire it up to a VGA port but
2633 * don't report it in the bios connector
2634 * table.
2635 */
2636 switch (dev->pdev->device) {
2637 /* RN50 */
2638 case 0x515e:
2639 case 0x5969:
2640 force_dac2 = true;
2641 break;
2642 /* RV100*/
2643 case 0x5159:
2644 case 0x515a:
2645 /* DELL triple head servers */
2646 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2647 ((dev->pdev->subsystem_device == 0x016c) ||
2648 (dev->pdev->subsystem_device == 0x016d) ||
2649 (dev->pdev->subsystem_device == 0x016e) ||
2650 (dev->pdev->subsystem_device == 0x016f) ||
2651 (dev->pdev->subsystem_device == 0x0170) ||
2652 (dev->pdev->subsystem_device == 0x017d) ||
2653 (dev->pdev->subsystem_device == 0x017e) ||
2654 (dev->pdev->subsystem_device == 0x0183) ||
2655 (dev->pdev->subsystem_device == 0x018a) ||
2656 (dev->pdev->subsystem_device == 0x019a)))
2657 force_dac2 = true;
2658 break;
2659 }
f5c5f040 2660
0242f74d
AD		 2661 if (force_dac2) {
2662 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2663 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2664 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
e024e110 2665
0242f74d
AD		 2666 /* For CRT on DAC2, don't turn it on if BIOS didn't
2667 enable it, even it's detected.
2668 */
c93bb85b 2669
0242f74d
AD		 2670 /* force it to crtc0 */
2671 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2672 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2673 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
c93bb85b 2674
0242f74d
AD		 2675 /* set up the TV DAC */
2676 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2677 RADEON_TV_DAC_STD_MASK |
2678 RADEON_TV_DAC_RDACPD |
2679 RADEON_TV_DAC_GDACPD |
2680 RADEON_TV_DAC_BDACPD |
2681 RADEON_TV_DAC_BGADJ_MASK |
2682 RADEON_TV_DAC_DACADJ_MASK);
2683 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2684 RADEON_TV_DAC_NHOLD |
2685 RADEON_TV_DAC_STD_PS2 |
2686 (0x58 << 16));
f46c0120 2687
0242f74d
AD		 2688 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2689 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2690 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
c93bb85b 2691 }
0242f74d
AD		 2692
2693 /* switch PM block to ACPI mode */
2694 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2695 tmp &= ~RADEON_PM_MODE_SEL;
2696 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2697
2698}
2699
2700/*
2701 * VRAM info
2702 */
2703static void r100_vram_get_type(struct radeon_device *rdev)
2704{
2705 uint32_t tmp;
2706
2707 rdev->mc.vram_is_ddr = false;
2708 if (rdev->flags & RADEON_IS_IGP)
2709 rdev->mc.vram_is_ddr = true;
2710 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2711 rdev->mc.vram_is_ddr = true;
2712 if ((rdev->family == CHIP_RV100) ||
2713 (rdev->family == CHIP_RS100) ||
2714 (rdev->family == CHIP_RS200)) {
2715 tmp = RREG32(RADEON_MEM_CNTL);
2716 if (tmp & RV100_HALF_MODE) {
2717 rdev->mc.vram_width = 32;
2718 } else {
2719 rdev->mc.vram_width = 64;
2720 }
2721 if (rdev->flags & RADEON_SINGLE_CRTC) {
2722 rdev->mc.vram_width /= 4;
2723 rdev->mc.vram_is_ddr = true;
dfee5614 2724 }
0242f74d
AD		 2725 } else if (rdev->family <= CHIP_RV280) {
2726 tmp = RREG32(RADEON_MEM_CNTL);
2727 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2728 rdev->mc.vram_width = 128;
2729 } else {
2730 rdev->mc.vram_width = 64;
2731 }
2732 } else {
2733 /* newer IGPs */
2734 rdev->mc.vram_width = 128;
c93bb85b 2735 }
0242f74d 2736}
c93bb85b 2737
0242f74d
AD		 2738static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2739{
2740 u32 aper_size;
2741 u8 byte;
2742
2743 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2744
2745 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2746 * that is has the 2nd generation multifunction PCI interface
2747 */
2748 if (rdev->family == CHIP_RV280 ||
2749 rdev->family >= CHIP_RV350) {
2750 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2751 ~RADEON_HDP_APER_CNTL);
2752 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2753 return aper_size * 2;
c93bb85b
JG		 2754 }
2755
0242f74d
AD		 2756 /* Older cards have all sorts of funny issues to deal with. First
2757 * check if it's a multifunction card by reading the PCI config
2758 * header type... Limit those to one aperture size
c93bb85b 2759 */
0242f74d
AD		 2760 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2761 if (byte & 0x80) {
2762 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2763 DRM_INFO("Limiting VRAM to one aperture\n");
2764 return aper_size;
2765 }
c93bb85b 2766
0242f74d
AD		 2767 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2768 * have set it up. We don't write this as it's broken on some ASICs but
2769 * we expect the BIOS to have done the right thing (might be too optimistic...)
2770 */
2771 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2772 return aper_size * 2;
2773 return aper_size;
2774}
c93bb85b 2775
0242f74d
AD		 2776void r100_vram_init_sizes(struct radeon_device *rdev)
2777{
2778 u64 config_aper_size;
c93bb85b 2779
0242f74d
AD		 2780 /* work out accessible VRAM */
2781 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2782 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2783 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2784 /* FIXME we don't use the second aperture yet when we could use it */
2785 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2786 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2787 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2788 if (rdev->flags & RADEON_IS_IGP) {
2789 uint32_t tom;
2790 /* read NB_TOM to get the amount of ram stolen for the GPU */
2791 tom = RREG32(RADEON_NB_TOM);
2792 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2793 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2794 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2795 } else {
2796 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2797 /* Some production boards of m6 will report 0
2798 * if it's 8 MB
2799 */
2800 if (rdev->mc.real_vram_size == 0) {
2801 rdev->mc.real_vram_size = 8192 * 1024;
2802 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2803 }
2804 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2805 * Novell bug 204882 + along with lots of ubuntu ones
2806 */
2807 if (rdev->mc.aper_size > config_aper_size)
2808 config_aper_size = rdev->mc.aper_size;
2809
2810 if (config_aper_size > rdev->mc.real_vram_size)
2811 rdev->mc.mc_vram_size = config_aper_size;
2812 else
2813 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
c93bb85b 2814 }
0242f74d 2815}
c93bb85b 2816
0242f74d
AD		 2817void r100_vga_set_state(struct radeon_device *rdev, bool state)
2818{
2819 uint32_t temp;
2820
2821 temp = RREG32(RADEON_CONFIG_CNTL);
2822 if (state == false) {
2823 temp &= ~RADEON_CFG_VGA_RAM_EN;
2824 temp |= RADEON_CFG_VGA_IO_DIS;
2825 } else {
2826 temp &= ~RADEON_CFG_VGA_IO_DIS;
c93bb85b 2827 }
0242f74d
AD		 2828 WREG32(RADEON_CONFIG_CNTL, temp);
2829}
c93bb85b 2830
1109ca09 2831static void r100_mc_init(struct radeon_device *rdev)
0242f74d
AD		 2832{
2833 u64 base;
c93bb85b 2834
0242f74d
AD		 2835 r100_vram_get_type(rdev);
2836 r100_vram_init_sizes(rdev);
2837 base = rdev->mc.aper_base;
2838 if (rdev->flags & RADEON_IS_IGP)
2839 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2840 radeon_vram_location(rdev, &rdev->mc, base);
2841 rdev->mc.gtt_base_align = 0;
2842 if (!(rdev->flags & RADEON_IS_AGP))
2843 radeon_gtt_location(rdev, &rdev->mc);
2844 radeon_update_bandwidth_info(rdev);
2845}
2846
2847
2848/*
2849 * Indirect registers accessor
2850 */
2851void r100_pll_errata_after_index(struct radeon_device *rdev)
2852{
2853 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2854 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2855 (void)RREG32(RADEON_CRTC_GEN_CNTL);
c93bb85b 2856 }
0242f74d 2857}
c93bb85b 2858
0242f74d
AD		 2859static void r100_pll_errata_after_data(struct radeon_device *rdev)
2860{
2861 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2862 * or the chip could hang on a subsequent access
2863 */
2864 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2865 mdelay(5);
c93bb85b
JG		 2866 }
2867
0242f74d
AD		 2868 /* This function is required to workaround a hardware bug in some (all?)
2869 * revisions of the R300. This workaround should be called after every
2870 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2871 * may not be correct.
2872 */
2873 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2874 uint32_t save, tmp;
c93bb85b 2875
0242f74d
AD		 2876 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2877 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2878 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2879 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2880 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
c93bb85b 2881 }
0242f74d 2882}
c93bb85b 2883
0242f74d
AD		 2884uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2885{
0a5b7b0b 2886 unsigned long flags;
0242f74d 2887 uint32_t data;
c93bb85b 2888
0a5b7b0b 2889 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2890 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2891 r100_pll_errata_after_index(rdev);
2892 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2893 r100_pll_errata_after_data(rdev);
0a5b7b0b 2894 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2895 return data;
2896}
c93bb85b 2897
0242f74d
AD		 2898void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2899{
0a5b7b0b
AD		 2900 unsigned long flags;
2901
2902 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2903 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2904 r100_pll_errata_after_index(rdev);
2905 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2906 r100_pll_errata_after_data(rdev);
0a5b7b0b 2907 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
0242f74d
AD		 2908}
2909
1109ca09 2910static void r100_set_safe_registers(struct radeon_device *rdev)
0242f74d
AD		 2911{
2912 if (ASIC_IS_RN50(rdev)) {
2913 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2914 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2915 } else if (rdev->family < CHIP_R200) {
2916 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2917 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
c93bb85b 2918 } else {
0242f74d 2919 r200_set_safe_registers(rdev);
c93bb85b 2920 }
0242f74d 2921}
c93bb85b 2922
0242f74d
AD		 2923/*
2924 * Debugfs info
2925 */
2926#if defined(CONFIG_DEBUG_FS)
2927static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2928{
2929 struct drm_info_node *node = (struct drm_info_node *) m->private;
2930 struct drm_device *dev = node->minor->dev;
2931 struct radeon_device *rdev = dev->dev_private;
2932 uint32_t reg, value;
2933 unsigned i;
c93bb85b 2934
0242f74d
AD		 2935 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2936 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2937 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2938 for (i = 0; i < 64; i++) {
2939 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2940 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2941 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2942 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2943 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2944 }
2945 return 0;
2946}
c93bb85b 2947
0242f74d
AD		 2948static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2949{
2950 struct drm_info_node *node = (struct drm_info_node *) m->private;
2951 struct drm_device *dev = node->minor->dev;
2952 struct radeon_device *rdev = dev->dev_private;
2953 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2954 uint32_t rdp, wdp;
2955 unsigned count, i, j;
c93bb85b 2956
0242f74d
AD		 2957 radeon_ring_free_size(rdev, ring);
2958 rdp = RREG32(RADEON_CP_RB_RPTR);
2959 wdp = RREG32(RADEON_CP_RB_WPTR);
2960 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2961 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2962 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2963 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2964 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2965 seq_printf(m, "%u dwords in ring\n", count);
0eb3448a
AI		 2966 if (ring->ready) {
2967 for (j = 0; j <= count; j++) {
2968 i = (rdp + j) & ring->ptr_mask;
2969 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2970 }
0242f74d
AD		 2971 }
2972 return 0;
2973}
c93bb85b 2974
c93bb85b 2975
0242f74d
AD		 2976static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2977{
2978 struct drm_info_node *node = (struct drm_info_node *) m->private;
2979 struct drm_device *dev = node->minor->dev;
2980 struct radeon_device *rdev = dev->dev_private;
2981 uint32_t csq_stat, csq2_stat, tmp;
2982 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2983 unsigned i;
c93bb85b 2984
0242f74d
AD		 2985 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2986 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2987 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2988 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2989 r_rptr = (csq_stat >> 0) & 0x3ff;
2990 r_wptr = (csq_stat >> 10) & 0x3ff;
2991 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2992 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2993 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2994 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2995 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2996 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2997 seq_printf(m, "Ring rptr %u\n", r_rptr);
2998 seq_printf(m, "Ring wptr %u\n", r_wptr);
2999 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3000 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3001 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3002 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3003 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3004 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3005 seq_printf(m, "Ring fifo:\n");
3006 for (i = 0; i < 256; i++) {
3007 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3008 tmp = RREG32(RADEON_CP_CSQ_DATA);
3009 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3010 }
3011 seq_printf(m, "Indirect1 fifo:\n");
3012 for (i = 256; i <= 512; i++) {
3013 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3014 tmp = RREG32(RADEON_CP_CSQ_DATA);
3015 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3016 }
3017 seq_printf(m, "Indirect2 fifo:\n");
3018 for (i = 640; i < ib1_wptr; i++) {
3019 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3020 tmp = RREG32(RADEON_CP_CSQ_DATA);
3021 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3022 }
3023 return 0;
3024}
3025
3026static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3027{
3028 struct drm_info_node *node = (struct drm_info_node *) m->private;
3029 struct drm_device *dev = node->minor->dev;
3030 struct radeon_device *rdev = dev->dev_private;
3031 uint32_t tmp;
c93bb85b 3032
0242f74d
AD		 3033 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3034 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3035 tmp = RREG32(RADEON_MC_FB_LOCATION);
3036 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3037 tmp = RREG32(RADEON_BUS_CNTL);
3038 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3039 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3040 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3041 tmp = RREG32(RADEON_AGP_BASE);
3042 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3043 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3044 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3045 tmp = RREG32(0x01D0);
3046 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3047 tmp = RREG32(RADEON_AIC_LO_ADDR);
3048 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3049 tmp = RREG32(RADEON_AIC_HI_ADDR);
3050 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3051 tmp = RREG32(0x01E4);
3052 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3053 return 0;
3054}
c93bb85b 3055
0242f74d
AD		 3056static struct drm_info_list r100_debugfs_rbbm_list[] = {
3057 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3058};
c93bb85b 3059
0242f74d
AD		 3060static struct drm_info_list r100_debugfs_cp_list[] = {
3061 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3062 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3063};
c93bb85b 3064
0242f74d
AD		 3065static struct drm_info_list r100_debugfs_mc_info_list[] = {
3066 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3067};
3068#endif
c93bb85b 3069
0242f74d
AD		 3070int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3071{
3072#if defined(CONFIG_DEBUG_FS)
3073 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3074#else
3075 return 0;
3076#endif
3077}
c93bb85b 3078
0242f74d
AD		 3079int r100_debugfs_cp_init(struct radeon_device *rdev)
3080{
3081#if defined(CONFIG_DEBUG_FS)
3082 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3083#else
3084 return 0;
3085#endif
3086}
c93bb85b 3087
0242f74d
AD		 3088int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3089{
3090#if defined(CONFIG_DEBUG_FS)
3091 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3092#else
3093 return 0;
3094#endif
3095}
c93bb85b 3096
0242f74d
AD		 3097int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3098 uint32_t tiling_flags, uint32_t pitch,
3099 uint32_t offset, uint32_t obj_size)
3100{
3101 int surf_index = reg * 16;
3102 int flags = 0;
c93bb85b 3103
0242f74d
AD		 3104 if (rdev->family <= CHIP_RS200) {
3105 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3106 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3107 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3108 if (tiling_flags & RADEON_TILING_MACRO)
3109 flags |= RADEON_SURF_TILE_COLOR_MACRO;
67d5ced5
AD		 3110 /* setting pitch to 0 disables tiling */
3111 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3112 == 0)
3113 pitch = 0;
0242f74d
AD		 3114 } else if (rdev->family <= CHIP_RV280) {
3115 if (tiling_flags & (RADEON_TILING_MACRO))
3116 flags |= R200_SURF_TILE_COLOR_MACRO;
3117 if (tiling_flags & RADEON_TILING_MICRO)
3118 flags |= R200_SURF_TILE_COLOR_MICRO;
3119 } else {
3120 if (tiling_flags & RADEON_TILING_MACRO)
3121 flags |= R300_SURF_TILE_MACRO;
3122 if (tiling_flags & RADEON_TILING_MICRO)
3123 flags |= R300_SURF_TILE_MICRO;
3124 }
c93bb85b 3125
0242f74d
AD		 3126 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3127 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3128 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3129 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3130
0242f74d
AD		 3131 /* r100/r200 divide by 16 */
3132 if (rdev->family < CHIP_R300)
3133 flags |= pitch / 16;
3134 else
3135 flags |= pitch / 8;
c93bb85b 3136
c93bb85b 3137
0242f74d
AD		 3138 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3139 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3140 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3141 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3142 return 0;
3143}
c93bb85b 3144
0242f74d
AD		 3145void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3146{
3147 int surf_index = reg * 16;
3148 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3149}
c93bb85b 3150
0242f74d
AD		 3151void r100_bandwidth_update(struct radeon_device *rdev)
3152{
3153 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3154 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3155 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3156 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3157 fixed20_12 memtcas_ff[8] = {
3158 dfixed_init(1),
3159 dfixed_init(2),
3160 dfixed_init(3),
3161 dfixed_init(0),
3162 dfixed_init_half(1),
3163 dfixed_init_half(2),
3164 dfixed_init(0),
3165 };
3166 fixed20_12 memtcas_rs480_ff[8] = {
3167 dfixed_init(0),
3168 dfixed_init(1),
3169 dfixed_init(2),
3170 dfixed_init(3),
3171 dfixed_init(0),
3172 dfixed_init_half(1),
3173 dfixed_init_half(2),
3174 dfixed_init_half(3),
3175 };
3176 fixed20_12 memtcas2_ff[8] = {
3177 dfixed_init(0),
3178 dfixed_init(1),
3179 dfixed_init(2),
3180 dfixed_init(3),
3181 dfixed_init(4),
3182 dfixed_init(5),
3183 dfixed_init(6),
3184 dfixed_init(7),
3185 };
3186 fixed20_12 memtrbs[8] = {
3187 dfixed_init(1),
3188 dfixed_init_half(1),
3189 dfixed_init(2),
3190 dfixed_init_half(2),
3191 dfixed_init(3),
3192 dfixed_init_half(3),
3193 dfixed_init(4),
3194 dfixed_init_half(4)
3195 };
3196 fixed20_12 memtrbs_r4xx[8] = {
3197 dfixed_init(4),
3198 dfixed_init(5),
3199 dfixed_init(6),
3200 dfixed_init(7),
3201 dfixed_init(8),
3202 dfixed_init(9),
3203 dfixed_init(10),
3204 dfixed_init(11)
3205 };
3206 fixed20_12 min_mem_eff;
3207 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3208 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3209 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3210 disp_drain_rate2, read_return_rate;
3211 fixed20_12 time_disp1_drop_priority;
3212 int c;
3213 int cur_size = 16; /* in octawords */
3214 int critical_point = 0, critical_point2;
3215/* uint32_t read_return_rate, time_disp1_drop_priority; */
3216 int stop_req, max_stop_req;
3217 struct drm_display_mode *mode1 = NULL;
3218 struct drm_display_mode *mode2 = NULL;
3219 uint32_t pixel_bytes1 = 0;
3220 uint32_t pixel_bytes2 = 0;
c93bb85b 3221
0242f74d 3222 radeon_update_display_priority(rdev);
c93bb85b 3223
0242f74d
AD		 3224 if (rdev->mode_info.crtcs[0]->base.enabled) {
3225 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3226 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3227 }
3228 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3229 if (rdev->mode_info.crtcs[1]->base.enabled) {
3230 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3231 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3232 }
3233 }
c93bb85b 3234
0242f74d
AD		 3235 min_mem_eff.full = dfixed_const_8(0);
3236 /* get modes */
3237 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3238 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3239 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3240 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3241 /* check crtc enables */
3242 if (mode2)
3243 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3244 if (mode1)
3245 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3246 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3247 }
c93bb85b 3248
0242f74d
AD		 3249 /*
3250 * determine is there is enough bw for current mode
3251 */
3252 sclk_ff = rdev->pm.sclk;
3253 mclk_ff = rdev->pm.mclk;
c93bb85b 3254
0242f74d
AD		 3255 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3256 temp_ff.full = dfixed_const(temp);
3257 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b 3258
0242f74d
AD		 3259 pix_clk.full = 0;
3260 pix_clk2.full = 0;
3261 peak_disp_bw.full = 0;
3262 if (mode1) {
3263 temp_ff.full = dfixed_const(1000);
3264 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3265 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3266 temp_ff.full = dfixed_const(pixel_bytes1);
3267 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3268 }
3269 if (mode2) {
3270 temp_ff.full = dfixed_const(1000);
3271 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3272 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3273 temp_ff.full = dfixed_const(pixel_bytes2);
3274 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3275 }
c93bb85b 3276
0242f74d
AD		 3277 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3278 if (peak_disp_bw.full >= mem_bw.full) {
3279 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3280 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3281 }
c93bb85b 3282
0242f74d
AD		 3283 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3284 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3285 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3286 mem_trcd = ((temp >> 2) & 0x3) + 1;
3287 mem_trp = ((temp & 0x3)) + 1;
3288 mem_tras = ((temp & 0x70) >> 4) + 1;
3289 } else if (rdev->family == CHIP_R300 ||
3290 rdev->family == CHIP_R350) { /* r300, r350 */
3291 mem_trcd = (temp & 0x7) + 1;
3292 mem_trp = ((temp >> 8) & 0x7) + 1;
3293 mem_tras = ((temp >> 11) & 0xf) + 4;
3294 } else if (rdev->family == CHIP_RV350 ||
3295 rdev->family <= CHIP_RV380) {
3296 /* rv3x0 */
3297 mem_trcd = (temp & 0x7) + 3;
3298 mem_trp = ((temp >> 8) & 0x7) + 3;
3299 mem_tras = ((temp >> 11) & 0xf) + 6;
3300 } else if (rdev->family == CHIP_R420 ||
3301 rdev->family == CHIP_R423 ||
3302 rdev->family == CHIP_RV410) {
3303 /* r4xx */
3304 mem_trcd = (temp & 0xf) + 3;
3305 if (mem_trcd > 15)
3306 mem_trcd = 15;
3307 mem_trp = ((temp >> 8) & 0xf) + 3;
3308 if (mem_trp > 15)
3309 mem_trp = 15;
3310 mem_tras = ((temp >> 12) & 0x1f) + 6;
3311 if (mem_tras > 31)
3312 mem_tras = 31;
3313 } else { /* RV200, R200 */
3314 mem_trcd = (temp & 0x7) + 1;
3315 mem_trp = ((temp >> 8) & 0x7) + 1;
3316 mem_tras = ((temp >> 12) & 0xf) + 4;
3317 }
3318 /* convert to FF */
3319 trcd_ff.full = dfixed_const(mem_trcd);
3320 trp_ff.full = dfixed_const(mem_trp);
3321 tras_ff.full = dfixed_const(mem_tras);
c93bb85b 3322
0242f74d
AD		 3323 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3324 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3325 data = (temp & (7 << 20)) >> 20;
3326 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3327 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3328 tcas_ff = memtcas_rs480_ff[data];
3329 else
3330 tcas_ff = memtcas_ff[data];
3331 } else
3332 tcas_ff = memtcas2_ff[data];
c93bb85b 3333
0242f74d
AD		 3334 if (rdev->family == CHIP_RS400 ||
3335 rdev->family == CHIP_RS480) {
3336 /* extra cas latency stored in bits 23-25 0-4 clocks */
3337 data = (temp >> 23) & 0x7;
3338 if (data < 5)
3339 tcas_ff.full += dfixed_const(data);
c93bb85b 3340 }
551ebd83 3341
0242f74d
AD		 3342 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3343 /* on the R300, Tcas is included in Trbs.
3344 */
3345 temp = RREG32(RADEON_MEM_CNTL);
3346 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3347 if (data == 1) {
3348 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3349 temp = RREG32(R300_MC_IND_INDEX);
3350 temp &= ~R300_MC_IND_ADDR_MASK;
3351 temp |= R300_MC_READ_CNTL_CD_mcind;
3352 WREG32(R300_MC_IND_INDEX, temp);
3353 temp = RREG32(R300_MC_IND_DATA);
3354 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3355 } else {
3356 temp = RREG32(R300_MC_READ_CNTL_AB);
3357 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3358 }
3359 } else {
3360 temp = RREG32(R300_MC_READ_CNTL_AB);
3361 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3362 }
3363 if (rdev->family == CHIP_RV410 ||
3364 rdev->family == CHIP_R420 ||
3365 rdev->family == CHIP_R423)
3366 trbs_ff = memtrbs_r4xx[data];
3367 else
3368 trbs_ff = memtrbs[data];
3369 tcas_ff.full += trbs_ff.full;
3370 }
551ebd83 3371
0242f74d 3372 sclk_eff_ff.full = sclk_ff.full;
d785d78b 3373
0242f74d
AD		 3374 if (rdev->flags & RADEON_IS_AGP) {
3375 fixed20_12 agpmode_ff;
3376 agpmode_ff.full = dfixed_const(radeon_agpmode);
3377 temp_ff.full = dfixed_const_666(16);
3378 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3379 }
3380 /* TODO PCIE lanes may affect this - agpmode == 16?? */
d785d78b 3381
0242f74d
AD		 3382 if (ASIC_IS_R300(rdev)) {
3383 sclk_delay_ff.full = dfixed_const(250);
3384 } else {
3385 if ((rdev->family == CHIP_RV100) ||
3386 rdev->flags & RADEON_IS_IGP) {
3387 if (rdev->mc.vram_is_ddr)
3388 sclk_delay_ff.full = dfixed_const(41);
3389 else
3390 sclk_delay_ff.full = dfixed_const(33);
3391 } else {
3392 if (rdev->mc.vram_width == 128)
3393 sclk_delay_ff.full = dfixed_const(57);
3394 else
3395 sclk_delay_ff.full = dfixed_const(41);
3396 }
d785d78b
DA		 3397 }
3398
0242f74d 3399 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
d785d78b 3400
0242f74d
AD		 3401 if (rdev->mc.vram_is_ddr) {
3402 if (rdev->mc.vram_width == 32) {
3403 k1.full = dfixed_const(40);
3404 c = 3;
3405 } else {
3406 k1.full = dfixed_const(20);
3407 c = 1;
3408 }
3409 } else {
3410 k1.full = dfixed_const(40);
3411 c = 3;
3412 }
37cf6b03 3413
0242f74d
AD		 3414 temp_ff.full = dfixed_const(2);
3415 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3416 temp_ff.full = dfixed_const(c);
3417 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3418 temp_ff.full = dfixed_const(4);
3419 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3420 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3421 mc_latency_mclk.full += k1.full;
37cf6b03 3422
0242f74d
AD		 3423 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3424 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
37cf6b03 3425
0242f74d
AD		 3426 /*
3427 HW cursor time assuming worst case of full size colour cursor.
3428 */
3429 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3430 temp_ff.full += trcd_ff.full;
3431 if (temp_ff.full < tras_ff.full)
3432 temp_ff.full = tras_ff.full;
3433 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
37cf6b03 3434
0242f74d
AD		 3435 temp_ff.full = dfixed_const(cur_size);
3436 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3437 /*
3438 Find the total latency for the display data.
3439 */
3440 disp_latency_overhead.full = dfixed_const(8);
3441 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3442 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3443 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
37cf6b03 3444
0242f74d
AD		 3445 if (mc_latency_mclk.full > mc_latency_sclk.full)
3446 disp_latency.full = mc_latency_mclk.full;
3447 else
3448 disp_latency.full = mc_latency_sclk.full;
551ebd83 3449
0242f74d
AD		 3450 /* setup Max GRPH_STOP_REQ default value */
3451 if (ASIC_IS_RV100(rdev))
3452 max_stop_req = 0x5c;
3453 else
3454 max_stop_req = 0x7c;
d785d78b 3455
0242f74d
AD		 3456 if (mode1) {
3457 /* CRTC1
3458 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3459 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3460 */
3461 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
d785d78b 3462
0242f74d
AD		 3463 if (stop_req > max_stop_req)
3464 stop_req = max_stop_req;
551ebd83 3465
0242f74d
AD		 3466 /*
3467 Find the drain rate of the display buffer.
3468 */
3469 temp_ff.full = dfixed_const((16/pixel_bytes1));
3470 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
551ebd83 3471
0242f74d
AD		 3472 /*
3473 Find the critical point of the display buffer.
3474 */
3475 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3476 crit_point_ff.full += dfixed_const_half(0);
a41ceb1c 3477
0242f74d
AD		 3478 critical_point = dfixed_trunc(crit_point_ff);
3479
3480 if (rdev->disp_priority == 2) {
3481 critical_point = 0;
551ebd83 3482 }
40b4a759 3483
0242f74d
AD		 3484 /*
3485 The critical point should never be above max_stop_req-4. Setting
3486 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3487 */
3488 if (max_stop_req - critical_point < 4)
3489 critical_point = 0;
3490
3491 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3492 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3493 critical_point = 0x10;
551ebd83 3494 }
0242f74d
AD		 3495
3496 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3497 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3498 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3499 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3500 if ((rdev->family == CHIP_R350) &&
3501 (stop_req > 0x15)) {
3502 stop_req -= 0x10;
551ebd83 3503 }
0242f74d
AD		 3504 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3505 temp |= RADEON_GRPH_BUFFER_SIZE;
3506 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3507 RADEON_GRPH_CRITICAL_AT_SOF |
3508 RADEON_GRPH_STOP_CNTL);
3509 /*
3510 Write the result into the register.
3511 */
3512 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3513 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
40b4a759 3514
0242f74d
AD		 3515#if 0
3516 if ((rdev->family == CHIP_RS400) ||
3517 (rdev->family == CHIP_RS480)) {
3518 /* attempt to program RS400 disp regs correctly ??? */
3519 temp = RREG32(RS400_DISP1_REG_CNTL);
3520 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3521 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3522 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3523 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3524 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3525 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3526 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3527 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3528 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3529 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3530 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
fff1ce4d 3531 }
0242f74d 3532#endif
fff1ce4d 3533
0242f74d
AD		 3534 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3535 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3536 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
cae94b0a 3537 }
0242f74d
AD		 3538
3539 if (mode2) {
3540 u32 grph2_cntl;
3541 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3542
3543 if (stop_req > max_stop_req)
3544 stop_req = max_stop_req;
3545
3546 /*
3547 Find the drain rate of the display buffer.
3548 */
3549 temp_ff.full = dfixed_const((16/pixel_bytes2));
3550 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3551
3552 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3553 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3554 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3555 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3556 if ((rdev->family == CHIP_R350) &&
3557 (stop_req > 0x15)) {
3558 stop_req -= 0x10;
551ebd83 3559 }
0242f74d
AD		 3560 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3561 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3562 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3563 RADEON_GRPH_CRITICAL_AT_SOF |
3564 RADEON_GRPH_STOP_CNTL);
3565
3566 if ((rdev->family == CHIP_RS100) ||
3567 (rdev->family == CHIP_RS200))
3568 critical_point2 = 0;
3569 else {
3570 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3571 temp_ff.full = dfixed_const(temp);
3572 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3573 if (sclk_ff.full < temp_ff.full)
3574 temp_ff.full = sclk_ff.full;
3575
3576 read_return_rate.full = temp_ff.full;
3577
3578 if (mode1) {
3579 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3580 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3581 } else {
3582 time_disp1_drop_priority.full = 0;
551ebd83 3583 }
0242f74d
AD		 3584 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3585 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3586 crit_point_ff.full += dfixed_const_half(0);
3587
3588 critical_point2 = dfixed_trunc(crit_point_ff);
3589
3590 if (rdev->disp_priority == 2) {
3591 critical_point2 = 0;
551ebd83 3592 }
40b4a759 3593
0242f74d
AD		 3594 if (max_stop_req - critical_point2 < 4)
3595 critical_point2 = 0;
551ebd83 3596
0242f74d 3597 }
551ebd83 3598
0242f74d
AD		 3599 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3600 /* some R300 cards have problem with this set to 0 */
3601 critical_point2 = 0x10;
3602 }
40b4a759 3603
0242f74d
AD		 3604 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3605 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
551ebd83 3606
0242f74d
AD		 3607 if ((rdev->family == CHIP_RS400) ||
3608 (rdev->family == CHIP_RS480)) {
3609#if 0
3610 /* attempt to program RS400 disp2 regs correctly ??? */
3611 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3612 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3613 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3614 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3615 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3616 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3617 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3618 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3619 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3620 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3621 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3622 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3623#endif
3624 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3625 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3626 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3627 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
551ebd83 3628 }
0242f74d
AD		 3629
3630 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3631 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
551ebd83
DA		 3632 }
3633}
3ce0a23d 3634
e32eb50d 3635int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3636{
3637 uint32_t scratch;
3638 uint32_t tmp = 0;
3639 unsigned i;
3640 int r;
3641
3642 r = radeon_scratch_get(rdev, &scratch);
3643 if (r) {
3644 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3645 return r;
3646 }
3647 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3648 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3649 if (r) {
3650 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3651 radeon_scratch_free(rdev, scratch);
3652 return r;
3653 }
e32eb50d
CK		 3654 radeon_ring_write(ring, PACKET0(scratch, 0));
3655 radeon_ring_write(ring, 0xDEADBEEF);
3656 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 3657 for (i = 0; i < rdev->usec_timeout; i++) {
3658 tmp = RREG32(scratch);
3659 if (tmp == 0xDEADBEEF) {
3660 break;
3661 }
3662 DRM_UDELAY(1);
3663 }
3664 if (i < rdev->usec_timeout) {
3665 DRM_INFO("ring test succeeded in %d usecs\n", i);
3666 } else {
369d7ec1 3667 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3668 scratch, tmp);
3669 r = -EINVAL;
3670 }
3671 radeon_scratch_free(rdev, scratch);
3672 return r;
3673}
3674
3675void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3676{
e32eb50d 3677 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3678
c7eff978
AD		 3679 if (ring->rptr_save_reg) {
3680 u32 next_rptr = ring->wptr + 2 + 3;
3681 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3682 radeon_ring_write(ring, next_rptr);
3683 }
3684
e32eb50d
CK		 3685 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3686 radeon_ring_write(ring, ib->gpu_addr);
3687 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3688}
3689
f712812e 3690int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3691{
f2e39221 3692 struct radeon_ib ib;
3ce0a23d
JG		 3693 uint32_t scratch;
3694 uint32_t tmp = 0;
3695 unsigned i;
3696 int r;
3697
3698 r = radeon_scratch_get(rdev, &scratch);
3699 if (r) {
3700 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3701 return r;
3702 }
3703 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3704 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3ce0a23d 3705 if (r) {
af026c5b
MD		 3706 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3707 goto free_scratch;
3ce0a23d 3708 }
f2e39221
JG		 3709 ib.ptr[0] = PACKET0(scratch, 0);
3710 ib.ptr[1] = 0xDEADBEEF;
3711 ib.ptr[2] = PACKET2(0);
3712 ib.ptr[3] = PACKET2(0);
3713 ib.ptr[4] = PACKET2(0);
3714 ib.ptr[5] = PACKET2(0);
3715 ib.ptr[6] = PACKET2(0);
3716 ib.ptr[7] = PACKET2(0);
3717 ib.length_dw = 8;
4ef72566 3718 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3719 if (r) {
af026c5b
MD		 3720 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3721 goto free_ib;
3ce0a23d 3722 }
f2e39221 3723 r = radeon_fence_wait(ib.fence, false);
3ce0a23d 3724 if (r) {
af026c5b
MD		 3725 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3726 goto free_ib;
3ce0a23d
JG		 3727 }
3728 for (i = 0; i < rdev->usec_timeout; i++) {
3729 tmp = RREG32(scratch);
3730 if (tmp == 0xDEADBEEF) {
3731 break;
3732 }
3733 DRM_UDELAY(1);
3734 }
3735 if (i < rdev->usec_timeout) {
3736 DRM_INFO("ib test succeeded in %u usecs\n", i);
3737 } else {
62f288cf 3738 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3739 scratch, tmp);
3740 r = -EINVAL;
3741 }
af026c5b 3742free_ib:
3ce0a23d 3743 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3744free_scratch:
3745 radeon_scratch_free(rdev, scratch);
3ce0a23d
JG		 3746 return r;
3747}
9f022ddf 3748
9f022ddf
JG		 3749void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3750{
3751 /* Shutdown CP we shouldn't need to do that but better be safe than
3752 * sorry
3753 */
e32eb50d 3754 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3755 WREG32(R_000740_CP_CSQ_CNTL, 0);
3756
3757 /* Save few CRTC registers */
ca6ffc64 3758 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3759 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3760 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3761 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3762 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3763 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3764 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3765 }
3766
3767 /* Disable VGA aperture access */
ca6ffc64 3768 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3769 /* Disable cursor, overlay, crtc */
3770 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3771 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3772 S_000054_CRTC_DISPLAY_DIS(1));
3773 WREG32(R_000050_CRTC_GEN_CNTL,
3774 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3775 S_000050_CRTC_DISP_REQ_EN_B(1));
3776 WREG32(R_000420_OV0_SCALE_CNTL,
3777 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3778 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3779 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3780 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3781 S_000360_CUR2_LOCK(1));
3782 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3783 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3784 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3785 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3786 WREG32(R_000360_CUR2_OFFSET,
3787 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3788 }
3789}
3790
3791void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3792{
3793 /* Update base address for crtc */
d594e46a 3794 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3795 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3796 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3797 }
3798 /* Restore CRTC registers */
ca6ffc64 3799 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3800 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3801 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3802 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3803 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3804 }
3805}
ca6ffc64
JG		 3806
3807void r100_vga_render_disable(struct radeon_device *rdev)
3808{
d4550907 3809 u32 tmp;
ca6ffc64 3810
d4550907 3811 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3812 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3813}
d4550907
JG		 3814
3815static void r100_debugfs(struct radeon_device *rdev)
3816{
3817 int r;
3818
3819 r = r100_debugfs_mc_info_init(rdev);
3820 if (r)
3821 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3822}
3823
3824static void r100_mc_program(struct radeon_device *rdev)
3825{
3826 struct r100_mc_save save;
3827
3828 /* Stops all mc clients */
3829 r100_mc_stop(rdev, &save);
3830 if (rdev->flags & RADEON_IS_AGP) {
3831 WREG32(R_00014C_MC_AGP_LOCATION,
3832 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3833 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3834 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3835 if (rdev->family > CHIP_RV200)
3836 WREG32(R_00015C_AGP_BASE_2,
3837 upper_32_bits(rdev->mc.agp_base) & 0xff);
3838 } else {
3839 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3840 WREG32(R_000170_AGP_BASE, 0);
3841 if (rdev->family > CHIP_RV200)
3842 WREG32(R_00015C_AGP_BASE_2, 0);
3843 }
3844 /* Wait for mc idle */
3845 if (r100_mc_wait_for_idle(rdev))
3846 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3847 /* Program MC, should be a 32bits limited address space */
3848 WREG32(R_000148_MC_FB_LOCATION,
3849 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3850 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3851 r100_mc_resume(rdev, &save);
3852}
3853
1109ca09 3854static void r100_clock_startup(struct radeon_device *rdev)
d4550907
JG		 3855{
3856 u32 tmp;
3857
3858 if (radeon_dynclks != -1 && radeon_dynclks)
3859 radeon_legacy_set_clock_gating(rdev, 1);
3860 /* We need to force on some of the block */
3861 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3862 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3863 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3864 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3865 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3866}
3867
3868static int r100_startup(struct radeon_device *rdev)
3869{
3870 int r;
3871
92cde00c
AD		 3872 /* set common regs */
3873 r100_set_common_regs(rdev);
3874 /* program mc */
d4550907
JG		 3875 r100_mc_program(rdev);
3876 /* Resume clock */
3877 r100_clock_startup(rdev);
d4550907
JG		 3878 /* Initialize GART (initialize after TTM so we can allocate
3879 * memory through TTM but finalize after TTM) */
17e15b0c 3880 r100_enable_bm(rdev);
d4550907
JG		 3881 if (rdev->flags & RADEON_IS_PCI) {
3882 r = r100_pci_gart_enable(rdev);
3883 if (r)
3884 return r;
3885 }
724c80e1
AD		 3886
3887 /* allocate wb buffer */
3888 r = radeon_wb_init(rdev);
3889 if (r)
3890 return r;
3891
30eb77f4
JG		 3892 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3893 if (r) {
3894 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3895 return r;
3896 }
3897
d4550907 3898 /* Enable IRQ */
e49f3959
AH		 3899 if (!rdev->irq.installed) {
3900 r = radeon_irq_kms_init(rdev);
3901 if (r)
3902 return r;
3903 }
3904
d4550907 3905 r100_irq_set(rdev);
cafe6609 3906 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3907 /* 1M ring buffer */
3908 r = r100_cp_init(rdev, 1024 * 1024);
3909 if (r) {
ec4f2ac4 3910 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3911 return r;
3912 }
b15ba512 3913
2898c348
CK		 3914 r = radeon_ib_pool_init(rdev);
3915 if (r) {
3916 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3917 return r;
2898c348 3918 }
b15ba512 3919
d4550907
JG		 3920 return 0;
3921}
3922
3923int r100_resume(struct radeon_device *rdev)
3924{
6b7746e8
JG		 3925 int r;
3926
d4550907
JG		 3927 /* Make sur GART are not working */
3928 if (rdev->flags & RADEON_IS_PCI)
3929 r100_pci_gart_disable(rdev);
3930 /* Resume clock before doing reset */
3931 r100_clock_startup(rdev);
3932 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3933 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3934 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3935 RREG32(R_000E40_RBBM_STATUS),
3936 RREG32(R_0007C0_CP_STAT));
3937 }
3938 /* post */
3939 radeon_combios_asic_init(rdev->ddev);
3940 /* Resume clock after posting */
3941 r100_clock_startup(rdev);
550e2d92
DA		 3942 /* Initialize surface registers */
3943 radeon_surface_init(rdev);
b15ba512 3944
6c7bccea
AD		 3945 radeon_pm_resume(rdev);
3946
b15ba512 3947 rdev->accel_working = true;
6b7746e8
JG		 3948 r = r100_startup(rdev);
3949 if (r) {
3950 rdev->accel_working = false;
3951 }
3952 return r;
d4550907
JG		 3953}
3954
3955int r100_suspend(struct radeon_device *rdev)
3956{
6c7bccea 3957 radeon_pm_suspend(rdev);
d4550907 3958 r100_cp_disable(rdev);
724c80e1 3959 radeon_wb_disable(rdev);
d4550907
JG		 3960 r100_irq_disable(rdev);
3961 if (rdev->flags & RADEON_IS_PCI)
3962 r100_pci_gart_disable(rdev);
3963 return 0;
3964}
3965
3966void r100_fini(struct radeon_device *rdev)
3967{
6c7bccea 3968 radeon_pm_fini(rdev);
d4550907 3969 r100_cp_fini(rdev);
724c80e1 3970 radeon_wb_fini(rdev);
2898c348 3971 radeon_ib_pool_fini(rdev);
d4550907
JG		 3972 radeon_gem_fini(rdev);
3973 if (rdev->flags & RADEON_IS_PCI)
3974 r100_pci_gart_fini(rdev);
d0269ed8 3975 radeon_agp_fini(rdev);
d4550907
JG		 3976 radeon_irq_kms_fini(rdev);
3977 radeon_fence_driver_fini(rdev);
4c788679 3978 radeon_bo_fini(rdev);
d4550907
JG		 3979 radeon_atombios_fini(rdev);
3980 kfree(rdev->bios);
3981 rdev->bios = NULL;
3982}
3983
4c712e6c
DA		 3984/*
3985 * Due to how kexec works, it can leave the hw fully initialised when it
3986 * boots the new kernel. However doing our init sequence with the CP and
3987 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3988 * do some quick sanity checks and restore sane values to avoid this
3989 * problem.
3990 */
3991void r100_restore_sanity(struct radeon_device *rdev)
3992{
3993 u32 tmp;
3994
3995 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3996 if (tmp) {
3997 WREG32(RADEON_CP_CSQ_CNTL, 0);
3998 }
3999 tmp = RREG32(RADEON_CP_RB_CNTL);
4000 if (tmp) {
4001 WREG32(RADEON_CP_RB_CNTL, 0);
4002 }
4003 tmp = RREG32(RADEON_SCRATCH_UMSK);
4004 if (tmp) {
4005 WREG32(RADEON_SCRATCH_UMSK, 0);
4006 }
4007}
4008
d4550907
JG		 4009int r100_init(struct radeon_device *rdev)
4010{
4011 int r;
4012
d4550907
JG		 4013 /* Register debugfs file specific to this group of asics */
4014 r100_debugfs(rdev);
4015 /* Disable VGA */
4016 r100_vga_render_disable(rdev);
4017 /* Initialize scratch registers */
4018 radeon_scratch_init(rdev);
4019 /* Initialize surface registers */
4020 radeon_surface_init(rdev);
4c712e6c
DA		 4021 /* sanity check some register to avoid hangs like after kexec */
4022 r100_restore_sanity(rdev);
d4550907
JG		 4023 /* TODO: disable VGA need to use VGA request */
4024 /* BIOS*/
4025 if (!radeon_get_bios(rdev)) {
4026 if (ASIC_IS_AVIVO(rdev))
4027 return -EINVAL;
4028 }
4029 if (rdev->is_atom_bios) {
4030 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4031 return -EINVAL;
4032 } else {
4033 r = radeon_combios_init(rdev);
4034 if (r)
4035 return r;
4036 }
4037 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4038 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4039 dev_warn(rdev->dev,
4040 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4041 RREG32(R_000E40_RBBM_STATUS),
4042 RREG32(R_0007C0_CP_STAT));
4043 }
4044 /* check if cards are posted or not */
72542d77
DA		 4045 if (radeon_boot_test_post_card(rdev) == false)
4046 return -EINVAL;
d4550907
JG		 4047 /* Set asic errata */
4048 r100_errata(rdev);
4049 /* Initialize clocks */
4050 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4051 /* initialize AGP */
4052 if (rdev->flags & RADEON_IS_AGP) {
4053 r = radeon_agp_init(rdev);
4054 if (r) {
4055 radeon_agp_disable(rdev);
4056 }
4057 }
4058 /* initialize VRAM */
4059 r100_mc_init(rdev);
d4550907 4060 /* Fence driver */
30eb77f4 4061 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4062 if (r)
4063 return r;
d4550907 4064 /* Memory manager */
4c788679 4065 r = radeon_bo_init(rdev);
d4550907
JG		 4066 if (r)
4067 return r;
4068 if (rdev->flags & RADEON_IS_PCI) {
4069 r = r100_pci_gart_init(rdev);
4070 if (r)
4071 return r;
4072 }
4073 r100_set_safe_registers(rdev);
b15ba512 4074
6c7bccea
AD		 4075 /* Initialize power management */
4076 radeon_pm_init(rdev);
4077
d4550907
JG		 4078 rdev->accel_working = true;
4079 r = r100_startup(rdev);
4080 if (r) {
4081 /* Somethings want wront with the accel init stop accel */
4082 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4083 r100_cp_fini(rdev);
724c80e1 4084 radeon_wb_fini(rdev);
2898c348 4085 radeon_ib_pool_fini(rdev);
655efd3d 4086 radeon_irq_kms_fini(rdev);
d4550907
JG		 4087 if (rdev->flags & RADEON_IS_PCI)
4088 r100_pci_gart_fini(rdev);
d4550907
JG		 4089 rdev->accel_working = false;
4090 }
4091 return 0;
4092}
6fcbef7a 4093
2ef9bdfe
DV		 4094uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4095 bool always_indirect)
6fcbef7a 4096{
2ef9bdfe 4097 if (reg < rdev->rmmio_size && !always_indirect)
6fcbef7a
AK		 4098 return readl(((void __iomem *)rdev->rmmio) + reg);
4099 else {
2c385151
DV		 4100 unsigned long flags;
4101 uint32_t ret;
4102
4103 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
6fcbef7a 4104 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2c385151
DV		 4105 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4106 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4107
4108 return ret;
6fcbef7a
AK		 4109 }
4110}
4111
2ef9bdfe
DV		 4112void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4113 bool always_indirect)
6fcbef7a 4114{
2ef9bdfe 4115 if (reg < rdev->rmmio_size && !always_indirect)
6fcbef7a
AK		 4116 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4117 else {
2c385151
DV		 4118 unsigned long flags;
4119
4120 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
6fcbef7a
AK		 4121 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4122 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2c385151 4123 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
6fcbef7a
AK		 4124 }
4125}
4126
4127u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4128{
4129 if (reg < rdev->rio_mem_size)
4130 return ioread32(rdev->rio_mem + reg);
4131 else {
4132 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4133 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4134 }
4135}
4136
4137void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4138{
4139 if (reg < rdev->rio_mem_size)
4140 iowrite32(v, rdev->rio_mem + reg);
4141 else {
4142 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4143 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4144 }
4145}
Linux 6.x block layer and io_uring tree(s)