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drm/radeon: add 2-level VM pagetables support v9
[linux-2.6-block.git] / drivers / gpu / drm / radeon / ni.c
CommitLineData
0af62b01
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
e0cd3608 27#include <linux/module.h>
0af62b01
AD		 28#include "drmP.h"
29#include "radeon.h"
30#include "radeon_asic.h"
31#include "radeon_drm.h"
32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
0c88a02e 35#include "cayman_blit_shaders.h"
0af62b01 36
b9952a8a
AD		 37extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
755d819e
AD		 40extern void evergreen_mc_program(struct radeon_device *rdev);
41extern void evergreen_irq_suspend(struct radeon_device *rdev);
42extern int evergreen_mc_init(struct radeon_device *rdev);
d054ac16 43extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
b07759bf 44extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
c420c745
AD		 45extern void si_rlc_fini(struct radeon_device *rdev);
46extern int si_rlc_init(struct radeon_device *rdev);
b9952a8a 47
0af62b01
AD		 48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
50#define EVERGREEN_RLC_UCODE_SIZE 768
51#define BTC_MC_UCODE_SIZE 6024
52
9b8253ce
AD		 53#define CAYMAN_PFP_UCODE_SIZE 2176
54#define CAYMAN_PM4_UCODE_SIZE 2176
55#define CAYMAN_RLC_UCODE_SIZE 1024
56#define CAYMAN_MC_UCODE_SIZE 6037
57
c420c745
AD		 58#define ARUBA_RLC_UCODE_SIZE 1536
59
0af62b01
AD		 60/* Firmware Names */
61MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
62MODULE_FIRMWARE("radeon/BARTS_me.bin");
63MODULE_FIRMWARE("radeon/BARTS_mc.bin");
64MODULE_FIRMWARE("radeon/BTC_rlc.bin");
65MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
66MODULE_FIRMWARE("radeon/TURKS_me.bin");
67MODULE_FIRMWARE("radeon/TURKS_mc.bin");
68MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
69MODULE_FIRMWARE("radeon/CAICOS_me.bin");
70MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
9b8253ce
AD		 71MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
72MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
73MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
74MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
c420c745
AD		 75MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
76MODULE_FIRMWARE("radeon/ARUBA_me.bin");
77MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
0af62b01
AD		 78
79#define BTC_IO_MC_REGS_SIZE 29
80
81static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
82 {0x00000077, 0xff010100},
83 {0x00000078, 0x00000000},
84 {0x00000079, 0x00001434},
85 {0x0000007a, 0xcc08ec08},
86 {0x0000007b, 0x00040000},
87 {0x0000007c, 0x000080c0},
88 {0x0000007d, 0x09000000},
89 {0x0000007e, 0x00210404},
90 {0x00000081, 0x08a8e800},
91 {0x00000082, 0x00030444},
92 {0x00000083, 0x00000000},
93 {0x00000085, 0x00000001},
94 {0x00000086, 0x00000002},
95 {0x00000087, 0x48490000},
96 {0x00000088, 0x20244647},
97 {0x00000089, 0x00000005},
98 {0x0000008b, 0x66030000},
99 {0x0000008c, 0x00006603},
100 {0x0000008d, 0x00000100},
101 {0x0000008f, 0x00001c0a},
102 {0x00000090, 0xff000001},
103 {0x00000094, 0x00101101},
104 {0x00000095, 0x00000fff},
105 {0x00000096, 0x00116fff},
106 {0x00000097, 0x60010000},
107 {0x00000098, 0x10010000},
108 {0x00000099, 0x00006000},
109 {0x0000009a, 0x00001000},
110 {0x0000009f, 0x00946a00}
111};
112
113static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
114 {0x00000077, 0xff010100},
115 {0x00000078, 0x00000000},
116 {0x00000079, 0x00001434},
117 {0x0000007a, 0xcc08ec08},
118 {0x0000007b, 0x00040000},
119 {0x0000007c, 0x000080c0},
120 {0x0000007d, 0x09000000},
121 {0x0000007e, 0x00210404},
122 {0x00000081, 0x08a8e800},
123 {0x00000082, 0x00030444},
124 {0x00000083, 0x00000000},
125 {0x00000085, 0x00000001},
126 {0x00000086, 0x00000002},
127 {0x00000087, 0x48490000},
128 {0x00000088, 0x20244647},
129 {0x00000089, 0x00000005},
130 {0x0000008b, 0x66030000},
131 {0x0000008c, 0x00006603},
132 {0x0000008d, 0x00000100},
133 {0x0000008f, 0x00001c0a},
134 {0x00000090, 0xff000001},
135 {0x00000094, 0x00101101},
136 {0x00000095, 0x00000fff},
137 {0x00000096, 0x00116fff},
138 {0x00000097, 0x60010000},
139 {0x00000098, 0x10010000},
140 {0x00000099, 0x00006000},
141 {0x0000009a, 0x00001000},
142 {0x0000009f, 0x00936a00}
143};
144
145static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
146 {0x00000077, 0xff010100},
147 {0x00000078, 0x00000000},
148 {0x00000079, 0x00001434},
149 {0x0000007a, 0xcc08ec08},
150 {0x0000007b, 0x00040000},
151 {0x0000007c, 0x000080c0},
152 {0x0000007d, 0x09000000},
153 {0x0000007e, 0x00210404},
154 {0x00000081, 0x08a8e800},
155 {0x00000082, 0x00030444},
156 {0x00000083, 0x00000000},
157 {0x00000085, 0x00000001},
158 {0x00000086, 0x00000002},
159 {0x00000087, 0x48490000},
160 {0x00000088, 0x20244647},
161 {0x00000089, 0x00000005},
162 {0x0000008b, 0x66030000},
163 {0x0000008c, 0x00006603},
164 {0x0000008d, 0x00000100},
165 {0x0000008f, 0x00001c0a},
166 {0x00000090, 0xff000001},
167 {0x00000094, 0x00101101},
168 {0x00000095, 0x00000fff},
169 {0x00000096, 0x00116fff},
170 {0x00000097, 0x60010000},
171 {0x00000098, 0x10010000},
172 {0x00000099, 0x00006000},
173 {0x0000009a, 0x00001000},
174 {0x0000009f, 0x00916a00}
175};
176
9b8253ce
AD		 177static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
178 {0x00000077, 0xff010100},
179 {0x00000078, 0x00000000},
180 {0x00000079, 0x00001434},
181 {0x0000007a, 0xcc08ec08},
182 {0x0000007b, 0x00040000},
183 {0x0000007c, 0x000080c0},
184 {0x0000007d, 0x09000000},
185 {0x0000007e, 0x00210404},
186 {0x00000081, 0x08a8e800},
187 {0x00000082, 0x00030444},
188 {0x00000083, 0x00000000},
189 {0x00000085, 0x00000001},
190 {0x00000086, 0x00000002},
191 {0x00000087, 0x48490000},
192 {0x00000088, 0x20244647},
193 {0x00000089, 0x00000005},
194 {0x0000008b, 0x66030000},
195 {0x0000008c, 0x00006603},
196 {0x0000008d, 0x00000100},
197 {0x0000008f, 0x00001c0a},
198 {0x00000090, 0xff000001},
199 {0x00000094, 0x00101101},
200 {0x00000095, 0x00000fff},
201 {0x00000096, 0x00116fff},
202 {0x00000097, 0x60010000},
203 {0x00000098, 0x10010000},
204 {0x00000099, 0x00006000},
205 {0x0000009a, 0x00001000},
206 {0x0000009f, 0x00976b00}
207};
208
755d819e 209int ni_mc_load_microcode(struct radeon_device *rdev)
0af62b01
AD		 210{
211 const __be32 *fw_data;
212 u32 mem_type, running, blackout = 0;
213 u32 *io_mc_regs;
9b8253ce 214 int i, ucode_size, regs_size;
0af62b01
AD		 215
216 if (!rdev->mc_fw)
217 return -EINVAL;
218
219 switch (rdev->family) {
220 case CHIP_BARTS:
221 io_mc_regs = (u32 *)&barts_io_mc_regs;
9b8253ce
AD		 222 ucode_size = BTC_MC_UCODE_SIZE;
223 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 224 break;
225 case CHIP_TURKS:
226 io_mc_regs = (u32 *)&turks_io_mc_regs;
9b8253ce
AD		 227 ucode_size = BTC_MC_UCODE_SIZE;
228 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 229 break;
230 case CHIP_CAICOS:
231 default:
232 io_mc_regs = (u32 *)&caicos_io_mc_regs;
9b8253ce
AD		 233 ucode_size = BTC_MC_UCODE_SIZE;
234 regs_size = BTC_IO_MC_REGS_SIZE;
235 break;
236 case CHIP_CAYMAN:
237 io_mc_regs = (u32 *)&cayman_io_mc_regs;
238 ucode_size = CAYMAN_MC_UCODE_SIZE;
239 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 240 break;
241 }
242
243 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
244 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
245
246 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
247 if (running) {
248 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
249 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
250 }
251
252 /* reset the engine and set to writable */
253 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
254 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
255
256 /* load mc io regs */
9b8253ce 257 for (i = 0; i < regs_size; i++) {
0af62b01
AD		 258 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
259 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
260 }
261 /* load the MC ucode */
262 fw_data = (const __be32 *)rdev->mc_fw->data;
9b8253ce 263 for (i = 0; i < ucode_size; i++)
0af62b01
AD		 264 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
265
266 /* put the engine back into the active state */
267 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
268 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
270
271 /* wait for training to complete */
0e2c978e
AD		 272 for (i = 0; i < rdev->usec_timeout; i++) {
273 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
274 break;
275 udelay(1);
276 }
0af62b01
AD		 277
278 if (running)
279 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
280 }
281
282 return 0;
283}
284
285int ni_init_microcode(struct radeon_device *rdev)
286{
287 struct platform_device *pdev;
288 const char *chip_name;
289 const char *rlc_chip_name;
290 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
291 char fw_name[30];
292 int err;
293
294 DRM_DEBUG("\n");
295
296 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
297 err = IS_ERR(pdev);
298 if (err) {
299 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
300 return -EINVAL;
301 }
302
303 switch (rdev->family) {
304 case CHIP_BARTS:
305 chip_name = "BARTS";
306 rlc_chip_name = "BTC";
9b8253ce
AD		 307 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
308 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
309 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
310 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 311 break;
312 case CHIP_TURKS:
313 chip_name = "TURKS";
314 rlc_chip_name = "BTC";
9b8253ce
AD		 315 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
316 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
317 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
318 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 319 break;
320 case CHIP_CAICOS:
321 chip_name = "CAICOS";
322 rlc_chip_name = "BTC";
9b8253ce
AD		 323 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
324 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
325 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
326 mc_req_size = BTC_MC_UCODE_SIZE * 4;
327 break;
328 case CHIP_CAYMAN:
329 chip_name = "CAYMAN";
330 rlc_chip_name = "CAYMAN";
331 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
332 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
333 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
334 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
0af62b01 335 break;
c420c745
AD		 336 case CHIP_ARUBA:
337 chip_name = "ARUBA";
338 rlc_chip_name = "ARUBA";
339 /* pfp/me same size as CAYMAN */
340 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
341 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
342 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
343 mc_req_size = 0;
344 break;
0af62b01
AD		 345 default: BUG();
346 }
347
0af62b01
AD		 348 DRM_INFO("Loading %s Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (rdev->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
357 rdev->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (rdev->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
369 rdev->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372
373 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
374 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
375 if (err)
376 goto out;
377 if (rdev->rlc_fw->size != rlc_req_size) {
378 printk(KERN_ERR
379 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
380 rdev->rlc_fw->size, fw_name);
381 err = -EINVAL;
382 }
383
c420c745
AD		 384 /* no MC ucode on TN */
385 if (!(rdev->flags & RADEON_IS_IGP)) {
386 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
387 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
388 if (err)
389 goto out;
390 if (rdev->mc_fw->size != mc_req_size) {
391 printk(KERN_ERR
392 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
393 rdev->mc_fw->size, fw_name);
394 err = -EINVAL;
395 }
0af62b01
AD		 396 }
397out:
398 platform_device_unregister(pdev);
399
400 if (err) {
401 if (err != -EINVAL)
402 printk(KERN_ERR
403 "ni_cp: Failed to load firmware \"%s\"\n",
404 fw_name);
405 release_firmware(rdev->pfp_fw);
406 rdev->pfp_fw = NULL;
407 release_firmware(rdev->me_fw);
408 rdev->me_fw = NULL;
409 release_firmware(rdev->rlc_fw);
410 rdev->rlc_fw = NULL;
411 release_firmware(rdev->mc_fw);
412 rdev->mc_fw = NULL;
413 }
414 return err;
415}
416
fecf1d07
AD		 417/*
418 * Core functions
419 */
fecf1d07
AD		 420static void cayman_gpu_init(struct radeon_device *rdev)
421{
fecf1d07
AD		 422 u32 gb_addr_config = 0;
423 u32 mc_shared_chmap, mc_arb_ramcfg;
fecf1d07
AD		 424 u32 cgts_tcc_disable;
425 u32 sx_debug_1;
426 u32 smx_dc_ctl0;
fecf1d07
AD		 427 u32 cgts_sm_ctrl_reg;
428 u32 hdp_host_path_cntl;
429 u32 tmp;
416a2bd2 430 u32 disabled_rb_mask;
fecf1d07
AD		 431 int i, j;
432
433 switch (rdev->family) {
434 case CHIP_CAYMAN:
fecf1d07
AD		 435 rdev->config.cayman.max_shader_engines = 2;
436 rdev->config.cayman.max_pipes_per_simd = 4;
437 rdev->config.cayman.max_tile_pipes = 8;
438 rdev->config.cayman.max_simds_per_se = 12;
439 rdev->config.cayman.max_backends_per_se = 4;
440 rdev->config.cayman.max_texture_channel_caches = 8;
441 rdev->config.cayman.max_gprs = 256;
442 rdev->config.cayman.max_threads = 256;
443 rdev->config.cayman.max_gs_threads = 32;
444 rdev->config.cayman.max_stack_entries = 512;
445 rdev->config.cayman.sx_num_of_sets = 8;
446 rdev->config.cayman.sx_max_export_size = 256;
447 rdev->config.cayman.sx_max_export_pos_size = 64;
448 rdev->config.cayman.sx_max_export_smx_size = 192;
449 rdev->config.cayman.max_hw_contexts = 8;
450 rdev->config.cayman.sq_num_cf_insts = 2;
451
452 rdev->config.cayman.sc_prim_fifo_size = 0x100;
453 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
454 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 455 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
fecf1d07 456 break;
7b76e479
AD		 457 case CHIP_ARUBA:
458 default:
459 rdev->config.cayman.max_shader_engines = 1;
460 rdev->config.cayman.max_pipes_per_simd = 4;
461 rdev->config.cayman.max_tile_pipes = 2;
462 if ((rdev->pdev->device == 0x9900) ||
d430f7db
AD		 463 (rdev->pdev->device == 0x9901) ||
464 (rdev->pdev->device == 0x9905) ||
465 (rdev->pdev->device == 0x9906) ||
466 (rdev->pdev->device == 0x9907) ||
467 (rdev->pdev->device == 0x9908) ||
468 (rdev->pdev->device == 0x9909) ||
469 (rdev->pdev->device == 0x9910) ||
470 (rdev->pdev->device == 0x9917)) {
7b76e479
AD		 471 rdev->config.cayman.max_simds_per_se = 6;
472 rdev->config.cayman.max_backends_per_se = 2;
473 } else if ((rdev->pdev->device == 0x9903) ||
d430f7db
AD		 474 (rdev->pdev->device == 0x9904) ||
475 (rdev->pdev->device == 0x990A) ||
476 (rdev->pdev->device == 0x9913) ||
477 (rdev->pdev->device == 0x9918)) {
7b76e479
AD		 478 rdev->config.cayman.max_simds_per_se = 4;
479 rdev->config.cayman.max_backends_per_se = 2;
d430f7db
AD		 480 } else if ((rdev->pdev->device == 0x9919) ||
481 (rdev->pdev->device == 0x9990) ||
482 (rdev->pdev->device == 0x9991) ||
483 (rdev->pdev->device == 0x9994) ||
484 (rdev->pdev->device == 0x99A0)) {
7b76e479
AD		 485 rdev->config.cayman.max_simds_per_se = 3;
486 rdev->config.cayman.max_backends_per_se = 1;
487 } else {
488 rdev->config.cayman.max_simds_per_se = 2;
489 rdev->config.cayman.max_backends_per_se = 1;
490 }
491 rdev->config.cayman.max_texture_channel_caches = 2;
492 rdev->config.cayman.max_gprs = 256;
493 rdev->config.cayman.max_threads = 256;
494 rdev->config.cayman.max_gs_threads = 32;
495 rdev->config.cayman.max_stack_entries = 512;
496 rdev->config.cayman.sx_num_of_sets = 8;
497 rdev->config.cayman.sx_max_export_size = 256;
498 rdev->config.cayman.sx_max_export_pos_size = 64;
499 rdev->config.cayman.sx_max_export_smx_size = 192;
500 rdev->config.cayman.max_hw_contexts = 8;
501 rdev->config.cayman.sq_num_cf_insts = 2;
502
503 rdev->config.cayman.sc_prim_fifo_size = 0x40;
504 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
505 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 506 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
7b76e479 507 break;
fecf1d07
AD		 508 }
509
510 /* Initialize HDP */
511 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
512 WREG32((0x2c14 + j), 0x00000000);
513 WREG32((0x2c18 + j), 0x00000000);
514 WREG32((0x2c1c + j), 0x00000000);
515 WREG32((0x2c20 + j), 0x00000000);
516 WREG32((0x2c24 + j), 0x00000000);
517 }
518
519 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
520
d054ac16
AD		 521 evergreen_fix_pci_max_read_req_size(rdev);
522
fecf1d07
AD		 523 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
524 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
525
fecf1d07
AD		 526 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
527 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
528 if (rdev->config.cayman.mem_row_size_in_kb > 4)
529 rdev->config.cayman.mem_row_size_in_kb = 4;
530 /* XXX use MC settings? */
531 rdev->config.cayman.shader_engine_tile_size = 32;
532 rdev->config.cayman.num_gpus = 1;
533 rdev->config.cayman.multi_gpu_tile_size = 64;
534
fecf1d07
AD		 535 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
536 rdev->config.cayman.num_tile_pipes = (1 << tmp);
537 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
538 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
539 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
540 rdev->config.cayman.num_shader_engines = tmp + 1;
541 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
542 rdev->config.cayman.num_gpus = tmp + 1;
543 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
544 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
545 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
546 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
547
416a2bd2 548
fecf1d07
AD		 549 /* setup tiling info dword. gb_addr_config is not adequate since it does
550 * not have bank info, so create a custom tiling dword.
551 * bits 3:0 num_pipes
552 * bits 7:4 num_banks
553 * bits 11:8 group_size
554 * bits 15:12 row_size
555 */
556 rdev->config.cayman.tile_config = 0;
557 switch (rdev->config.cayman.num_tile_pipes) {
558 case 1:
559 default:
560 rdev->config.cayman.tile_config |= (0 << 0);
561 break;
562 case 2:
563 rdev->config.cayman.tile_config |= (1 << 0);
564 break;
565 case 4:
566 rdev->config.cayman.tile_config |= (2 << 0);
567 break;
568 case 8:
569 rdev->config.cayman.tile_config |= (3 << 0);
570 break;
571 }
7b76e479
AD		 572
573 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
574 if (rdev->flags & RADEON_IS_IGP)
1f73cca7 575 rdev->config.cayman.tile_config |= 1 << 4;
29d65406 576 else {
5b23c904
AD		 577 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578 case 0: /* four banks */
29d65406 579 rdev->config.cayman.tile_config |= 0 << 4;
5b23c904
AD		 580 break;
581 case 1: /* eight banks */
582 rdev->config.cayman.tile_config |= 1 << 4;
583 break;
584 case 2: /* sixteen banks */
585 default:
586 rdev->config.cayman.tile_config |= 2 << 4;
587 break;
588 }
29d65406 589 }
fecf1d07 590 rdev->config.cayman.tile_config |=
cde5083b 591 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
fecf1d07
AD		 592 rdev->config.cayman.tile_config |=
593 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
594
416a2bd2
AD		 595 tmp = 0;
596 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
597 u32 rb_disable_bitmap;
598
599 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
600 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
601 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
602 tmp <<= 4;
603 tmp |= rb_disable_bitmap;
604 }
605 /* enabled rb are just the one not disabled :) */
606 disabled_rb_mask = tmp;
607
608 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
609 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
610
fecf1d07
AD		 611 WREG32(GB_ADDR_CONFIG, gb_addr_config);
612 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
613 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
614
416a2bd2
AD		 615 tmp = gb_addr_config & NUM_PIPES_MASK;
616 tmp = r6xx_remap_render_backend(rdev, tmp,
617 rdev->config.cayman.max_backends_per_se *
618 rdev->config.cayman.max_shader_engines,
619 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
620 WREG32(GB_BACKEND_MAP, tmp);
fecf1d07 621
416a2bd2
AD		 622 cgts_tcc_disable = 0xffff0000;
623 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
624 cgts_tcc_disable &= ~(1 << (16 + i));
fecf1d07
AD		 625 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
626 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
fecf1d07
AD		 627 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
628 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
629
630 /* reprogram the shader complex */
631 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
632 for (i = 0; i < 16; i++)
633 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
634 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
635
636 /* set HW defaults for 3D engine */
637 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
638
639 sx_debug_1 = RREG32(SX_DEBUG_1);
640 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
641 WREG32(SX_DEBUG_1, sx_debug_1);
642
643 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
644 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
285e042d 645 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
fecf1d07
AD		 646 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
647
648 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
649
650 /* need to be explicitly zero-ed */
651 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
652 WREG32(SQ_LSTMP_RING_BASE, 0);
653 WREG32(SQ_HSTMP_RING_BASE, 0);
654 WREG32(SQ_ESTMP_RING_BASE, 0);
655 WREG32(SQ_GSTMP_RING_BASE, 0);
656 WREG32(SQ_VSTMP_RING_BASE, 0);
657 WREG32(SQ_PSTMP_RING_BASE, 0);
658
659 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
660
285e042d
DA		 661 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
662 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
663 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
fecf1d07 664
285e042d
DA		 665 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
666 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
667 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
fecf1d07
AD		 668
669
670 WREG32(VGT_NUM_INSTANCES, 1);
671
672 WREG32(CP_PERFMON_CNTL, 0);
673
285e042d 674 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
fecf1d07
AD		 675 FETCH_FIFO_HIWATER(0x4) |
676 DONE_FIFO_HIWATER(0xe0) |
677 ALU_UPDATE_FIFO_HIWATER(0x8)));
678
679 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
680 WREG32(SQ_CONFIG, (VC_ENABLE |
681 EXPORT_SRC_C |
682 GFX_PRIO(0) |
683 CS1_PRIO(0) |
684 CS2_PRIO(1)));
685 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
686
687 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
688 FORCE_EOV_MAX_REZ_CNT(255)));
689
690 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
691 AUTO_INVLD_EN(ES_AND_GS_AUTO));
692
693 WREG32(VGT_GS_VERTEX_REUSE, 16);
694 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
695
696 WREG32(CB_PERF_CTR0_SEL_0, 0);
697 WREG32(CB_PERF_CTR0_SEL_1, 0);
698 WREG32(CB_PERF_CTR1_SEL_0, 0);
699 WREG32(CB_PERF_CTR1_SEL_1, 0);
700 WREG32(CB_PERF_CTR2_SEL_0, 0);
701 WREG32(CB_PERF_CTR2_SEL_1, 0);
702 WREG32(CB_PERF_CTR3_SEL_0, 0);
703 WREG32(CB_PERF_CTR3_SEL_1, 0);
704
0b65f83f
DA		 705 tmp = RREG32(HDP_MISC_CNTL);
706 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
707 WREG32(HDP_MISC_CNTL, tmp);
708
fecf1d07
AD		 709 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
710 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
711
712 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
713
714 udelay(50);
715}
716
fa8198ea
AD		 717/*
718 * GART
719 */
720void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
721{
722 /* flush hdp cache */
723 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
724
725 /* bits 0-7 are the VM contexts0-7 */
726 WREG32(VM_INVALIDATE_REQUEST, 1);
727}
728
1109ca09 729static int cayman_pcie_gart_enable(struct radeon_device *rdev)
fa8198ea 730{
721604a1 731 int i, r;
fa8198ea 732
c9a1be96 733 if (rdev->gart.robj == NULL) {
fa8198ea
AD		 734 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
735 return -EINVAL;
736 }
737 r = radeon_gart_table_vram_pin(rdev);
738 if (r)
739 return r;
740 radeon_gart_restore(rdev);
741 /* Setup TLB control */
721604a1
JG		 742 WREG32(MC_VM_MX_L1_TLB_CNTL,
743 (0xA << 7) |
744 ENABLE_L1_TLB |
fa8198ea
AD		 745 ENABLE_L1_FRAGMENT_PROCESSING |
746 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
721604a1 747 ENABLE_ADVANCED_DRIVER_MODEL |
fa8198ea
AD		 748 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
749 /* Setup L2 cache */
750 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
751 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
752 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
753 EFFECTIVE_L2_QUEUE_SIZE(7) |
754 CONTEXT1_IDENTITY_ACCESS_MODE(1));
755 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
756 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
757 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
758 /* setup context0 */
759 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
760 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
761 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
762 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
763 (u32)(rdev->dummy_page.addr >> 12));
764 WREG32(VM_CONTEXT0_CNTL2, 0);
765 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
766 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
721604a1
JG		 767
768 WREG32(0x15D4, 0);
769 WREG32(0x15D8, 0);
770 WREG32(0x15DC, 0);
771
772 /* empty context1-7 */
773 for (i = 1; i < 8; i++) {
774 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
775 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
776 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
777 rdev->gart.table_addr >> 12);
778 }
779
780 /* enable context1-7 */
781 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
782 (u32)(rdev->dummy_page.addr >> 12));
fa8198ea
AD		 783 WREG32(VM_CONTEXT1_CNTL2, 0);
784 WREG32(VM_CONTEXT1_CNTL, 0);
fa87e62d 785 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
721604a1 786 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
fa8198ea
AD		 787
788 cayman_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 789 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
790 (unsigned)(rdev->mc.gtt_size >> 20),
791 (unsigned long long)rdev->gart.table_addr);
fa8198ea
AD		 792 rdev->gart.ready = true;
793 return 0;
794}
795
1109ca09 796static void cayman_pcie_gart_disable(struct radeon_device *rdev)
fa8198ea 797{
fa8198ea
AD		 798 /* Disable all tables */
799 WREG32(VM_CONTEXT0_CNTL, 0);
800 WREG32(VM_CONTEXT1_CNTL, 0);
801 /* Setup TLB control */
802 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
803 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
804 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
805 /* Setup L2 cache */
806 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
807 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
808 EFFECTIVE_L2_QUEUE_SIZE(7) |
809 CONTEXT1_IDENTITY_ACCESS_MODE(1));
810 WREG32(VM_L2_CNTL2, 0);
811 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
812 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
c9a1be96 813 radeon_gart_table_vram_unpin(rdev);
fa8198ea
AD		 814}
815
1109ca09 816static void cayman_pcie_gart_fini(struct radeon_device *rdev)
fa8198ea
AD		 817{
818 cayman_pcie_gart_disable(rdev);
819 radeon_gart_table_vram_free(rdev);
820 radeon_gart_fini(rdev);
821}
822
1b37078b
AD		 823void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
824 int ring, u32 cp_int_cntl)
825{
826 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
827
828 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
829 WREG32(CP_INT_CNTL, cp_int_cntl);
830}
831
0c88a02e
AD		 832/*
833 * CP.
834 */
b40e7e16
AD		 835void cayman_fence_ring_emit(struct radeon_device *rdev,
836 struct radeon_fence *fence)
837{
838 struct radeon_ring *ring = &rdev->ring[fence->ring];
839 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
840
721604a1
JG		 841 /* flush read cache over gart for this vmid */
842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
843 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
844 radeon_ring_write(ring, 0);
b40e7e16
AD		 845 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
846 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
847 radeon_ring_write(ring, 0xFFFFFFFF);
848 radeon_ring_write(ring, 0);
849 radeon_ring_write(ring, 10); /* poll interval */
850 /* EVENT_WRITE_EOP - flush caches, send int */
851 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
852 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
853 radeon_ring_write(ring, addr & 0xffffffff);
854 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
855 radeon_ring_write(ring, fence->seq);
856 radeon_ring_write(ring, 0);
857}
858
721604a1
JG		 859void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
860{
876dc9f3 861 struct radeon_ring *ring = &rdev->ring[ib->ring];
721604a1
JG		 862
863 /* set to DX10/11 mode */
864 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
865 radeon_ring_write(ring, 1);
45df6803
CK		 866
867 if (ring->rptr_save_reg) {
868 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
869 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
870 radeon_ring_write(ring, ((ring->rptr_save_reg -
871 PACKET3_SET_CONFIG_REG_START) >> 2));
872 radeon_ring_write(ring, next_rptr);
873 }
874
721604a1
JG		 875 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
876 radeon_ring_write(ring,
877#ifdef __BIG_ENDIAN
878 (2 << 0) |
879#endif
880 (ib->gpu_addr & 0xFFFFFFFC));
881 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
4bf3dd92
CK		 882 radeon_ring_write(ring, ib->length_dw |
883 (ib->vm ? (ib->vm->id << 24) : 0));
721604a1
JG		 884
885 /* flush read cache over gart for this vmid */
886 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
887 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 888 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
721604a1
JG		 889 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
890 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
891 radeon_ring_write(ring, 0xFFFFFFFF);
892 radeon_ring_write(ring, 0);
893 radeon_ring_write(ring, 10); /* poll interval */
894}
895
0c88a02e
AD		 896static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
897{
898 if (enable)
899 WREG32(CP_ME_CNTL, 0);
900 else {
38f1cff0 901 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0c88a02e
AD		 902 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
903 WREG32(SCRATCH_UMSK, 0);
904 }
905}
906
907static int cayman_cp_load_microcode(struct radeon_device *rdev)
908{
909 const __be32 *fw_data;
910 int i;
911
912 if (!rdev->me_fw || !rdev->pfp_fw)
913 return -EINVAL;
914
915 cayman_cp_enable(rdev, false);
916
917 fw_data = (const __be32 *)rdev->pfp_fw->data;
918 WREG32(CP_PFP_UCODE_ADDR, 0);
919 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
920 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
921 WREG32(CP_PFP_UCODE_ADDR, 0);
922
923 fw_data = (const __be32 *)rdev->me_fw->data;
924 WREG32(CP_ME_RAM_WADDR, 0);
925 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
926 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
927
928 WREG32(CP_PFP_UCODE_ADDR, 0);
929 WREG32(CP_ME_RAM_WADDR, 0);
930 WREG32(CP_ME_RAM_RADDR, 0);
931 return 0;
932}
933
934static int cayman_cp_start(struct radeon_device *rdev)
935{
e32eb50d 936 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0c88a02e
AD		 937 int r, i;
938
e32eb50d 939 r = radeon_ring_lock(rdev, ring, 7);
0c88a02e
AD		 940 if (r) {
941 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
942 return r;
943 }
e32eb50d
CK		 944 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
945 radeon_ring_write(ring, 0x1);
946 radeon_ring_write(ring, 0x0);
947 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
948 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
949 radeon_ring_write(ring, 0);
950 radeon_ring_write(ring, 0);
951 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 952
953 cayman_cp_enable(rdev, true);
954
e32eb50d 955 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
0c88a02e
AD		 956 if (r) {
957 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
958 return r;
959 }
960
961 /* setup clear context state */
e32eb50d
CK		 962 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
963 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
0c88a02e
AD		 964
965 for (i = 0; i < cayman_default_size; i++)
e32eb50d 966 radeon_ring_write(ring, cayman_default_state[i]);
0c88a02e 967
e32eb50d
CK		 968 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
969 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
0c88a02e
AD		 970
971 /* set clear context state */
e32eb50d
CK		 972 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
973 radeon_ring_write(ring, 0);
0c88a02e
AD		 974
975 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 976 radeon_ring_write(ring, 0xc0026f00);
977 radeon_ring_write(ring, 0x00000000);
978 radeon_ring_write(ring, 0x00000000);
979 radeon_ring_write(ring, 0x00000000);
0c88a02e
AD		 980
981 /* Clear consts */
e32eb50d
CK		 982 radeon_ring_write(ring, 0xc0036f00);
983 radeon_ring_write(ring, 0x00000bc4);
984 radeon_ring_write(ring, 0xffffffff);
985 radeon_ring_write(ring, 0xffffffff);
986 radeon_ring_write(ring, 0xffffffff);
0c88a02e 987
e32eb50d
CK		 988 radeon_ring_write(ring, 0xc0026900);
989 radeon_ring_write(ring, 0x00000316);
990 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
991 radeon_ring_write(ring, 0x00000010); /* */
9b91d18d 992
e32eb50d 993 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 994
995 /* XXX init other rings */
996
997 return 0;
998}
999
755d819e
AD		 1000static void cayman_cp_fini(struct radeon_device *rdev)
1001{
45df6803 1002 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e 1003 cayman_cp_enable(rdev, false);
45df6803
CK		 1004 radeon_ring_fini(rdev, ring);
1005 radeon_scratch_free(rdev, ring->rptr_save_reg);
755d819e
AD		 1006}
1007
1109ca09 1008static int cayman_cp_resume(struct radeon_device *rdev)
0c88a02e 1009{
b90ca986
CK		 1010 static const int ridx[] = {
1011 RADEON_RING_TYPE_GFX_INDEX,
1012 CAYMAN_RING_TYPE_CP1_INDEX,
1013 CAYMAN_RING_TYPE_CP2_INDEX
1014 };
1015 static const unsigned cp_rb_cntl[] = {
1016 CP_RB0_CNTL,
1017 CP_RB1_CNTL,
1018 CP_RB2_CNTL,
1019 };
1020 static const unsigned cp_rb_rptr_addr[] = {
1021 CP_RB0_RPTR_ADDR,
1022 CP_RB1_RPTR_ADDR,
1023 CP_RB2_RPTR_ADDR
1024 };
1025 static const unsigned cp_rb_rptr_addr_hi[] = {
1026 CP_RB0_RPTR_ADDR_HI,
1027 CP_RB1_RPTR_ADDR_HI,
1028 CP_RB2_RPTR_ADDR_HI
1029 };
1030 static const unsigned cp_rb_base[] = {
1031 CP_RB0_BASE,
1032 CP_RB1_BASE,
1033 CP_RB2_BASE
1034 };
e32eb50d 1035 struct radeon_ring *ring;
b90ca986 1036 int i, r;
0c88a02e
AD		 1037
1038 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1039 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1040 SOFT_RESET_PA |
1041 SOFT_RESET_SH |
1042 SOFT_RESET_VGT |
a49a50da 1043 SOFT_RESET_SPI |
0c88a02e
AD		 1044 SOFT_RESET_SX));
1045 RREG32(GRBM_SOFT_RESET);
1046 mdelay(15);
1047 WREG32(GRBM_SOFT_RESET, 0);
1048 RREG32(GRBM_SOFT_RESET);
1049
15d3332f 1050 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1051 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
0c88a02e
AD		 1052
1053 /* Set the write pointer delay */
1054 WREG32(CP_RB_WPTR_DELAY, 0);
1055
1056 WREG32(CP_DEBUG, (1 << 27));
1057
0c88a02e 1058 /* set the wb address wether it's enabled or not */
0c88a02e 1059 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
b90ca986 1060 WREG32(SCRATCH_UMSK, 0xff);
0c88a02e 1061
b90ca986
CK		 1062 for (i = 0; i < 3; ++i) {
1063 uint32_t rb_cntl;
1064 uint64_t addr;
0c88a02e 1065
b90ca986
CK		 1066 /* Set ring buffer size */
1067 ring = &rdev->ring[ridx[i]];
1068 rb_cntl = drm_order(ring->ring_size / 8);
1069 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
0c88a02e 1070#ifdef __BIG_ENDIAN
b90ca986 1071 rb_cntl |= BUF_SWAP_32BIT;
0c88a02e 1072#endif
b90ca986 1073 WREG32(cp_rb_cntl[i], rb_cntl);
0c88a02e 1074
b90ca986
CK		 1075 /* set the wb address wether it's enabled or not */
1076 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1077 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1078 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1079 }
0c88a02e 1080
b90ca986
CK		 1081 /* set the rb base addr, this causes an internal reset of ALL rings */
1082 for (i = 0; i < 3; ++i) {
1083 ring = &rdev->ring[ridx[i]];
1084 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1085 }
0c88a02e 1086
b90ca986
CK		 1087 for (i = 0; i < 3; ++i) {
1088 /* Initialize the ring buffer's read and write pointers */
1089 ring = &rdev->ring[ridx[i]];
1090 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
0c88a02e 1091
b90ca986
CK		 1092 ring->rptr = ring->wptr = 0;
1093 WREG32(ring->rptr_reg, ring->rptr);
1094 WREG32(ring->wptr_reg, ring->wptr);
0c88a02e 1095
b90ca986
CK		 1096 mdelay(1);
1097 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1098 }
0c88a02e
AD		 1099
1100 /* start the rings */
1101 cayman_cp_start(rdev);
e32eb50d
CK		 1102 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1103 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1104 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e 1105 /* this only test cp0 */
f712812e 1106 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
0c88a02e 1107 if (r) {
e32eb50d
CK		 1108 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1109 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1110 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e
AD		 1111 return r;
1112 }
1113
1114 return 0;
1115}
1116
b9952a8a
AD		 1117static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1118{
1119 struct evergreen_mc_save save;
1120 u32 grbm_reset = 0;
1121
1122 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1123 return 0;
1124
1125 dev_info(rdev->dev, "GPU softreset \n");
1126 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1127 RREG32(GRBM_STATUS));
1128 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1129 RREG32(GRBM_STATUS_SE0));
1130 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1131 RREG32(GRBM_STATUS_SE1));
1132 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1133 RREG32(SRBM_STATUS));
440a7cd8
JG		 1134 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1135 RREG32(CP_STALLED_STAT1));
1136 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1137 RREG32(CP_STALLED_STAT2));
1138 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1139 RREG32(CP_BUSY_STAT));
1140 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1141 RREG32(CP_STAT));
721604a1
JG		 1142 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1143 RREG32(0x14F8));
1144 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1145 RREG32(0x14D8));
1146 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1147 RREG32(0x14FC));
1148 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1149 RREG32(0x14DC));
1150
b9952a8a
AD		 1151 evergreen_mc_stop(rdev, &save);
1152 if (evergreen_mc_wait_for_idle(rdev)) {
1153 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1154 }
1155 /* Disable CP parsing/prefetching */
1156 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1157
1158 /* reset all the gfx blocks */
1159 grbm_reset = (SOFT_RESET_CP |
1160 SOFT_RESET_CB |
1161 SOFT_RESET_DB |
1162 SOFT_RESET_GDS |
1163 SOFT_RESET_PA |
1164 SOFT_RESET_SC |
1165 SOFT_RESET_SPI |
1166 SOFT_RESET_SH |
1167 SOFT_RESET_SX |
1168 SOFT_RESET_TC |
1169 SOFT_RESET_TA |
1170 SOFT_RESET_VGT |
1171 SOFT_RESET_IA);
1172
1173 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1174 WREG32(GRBM_SOFT_RESET, grbm_reset);
1175 (void)RREG32(GRBM_SOFT_RESET);
1176 udelay(50);
1177 WREG32(GRBM_SOFT_RESET, 0);
1178 (void)RREG32(GRBM_SOFT_RESET);
1179 /* Wait a little for things to settle down */
1180 udelay(50);
721604a1 1181
b9952a8a
AD		 1182 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1183 RREG32(GRBM_STATUS));
1184 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1185 RREG32(GRBM_STATUS_SE0));
1186 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1187 RREG32(GRBM_STATUS_SE1));
1188 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1189 RREG32(SRBM_STATUS));
440a7cd8
JG		 1190 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1191 RREG32(CP_STALLED_STAT1));
1192 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1193 RREG32(CP_STALLED_STAT2));
1194 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1195 RREG32(CP_BUSY_STAT));
1196 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1197 RREG32(CP_STAT));
b9952a8a
AD		 1198 evergreen_mc_resume(rdev, &save);
1199 return 0;
1200}
1201
1202int cayman_asic_reset(struct radeon_device *rdev)
1203{
1204 return cayman_gpu_soft_reset(rdev);
1205}
1206
755d819e
AD		 1207static int cayman_startup(struct radeon_device *rdev)
1208{
e32eb50d 1209 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1210 int r;
1211
b07759bf
IH		 1212 /* enable pcie gen2 link */
1213 evergreen_pcie_gen2_enable(rdev);
1214
c420c745
AD		 1215 if (rdev->flags & RADEON_IS_IGP) {
1216 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1217 r = ni_init_microcode(rdev);
1218 if (r) {
1219 DRM_ERROR("Failed to load firmware!\n");
1220 return r;
1221 }
1222 }
1223 } else {
1224 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1225 r = ni_init_microcode(rdev);
1226 if (r) {
1227 DRM_ERROR("Failed to load firmware!\n");
1228 return r;
1229 }
1230 }
1231
1232 r = ni_mc_load_microcode(rdev);
755d819e 1233 if (r) {
c420c745 1234 DRM_ERROR("Failed to load MC firmware!\n");
755d819e
AD		 1235 return r;
1236 }
1237 }
755d819e 1238
16cdf04d
AD		 1239 r = r600_vram_scratch_init(rdev);
1240 if (r)
1241 return r;
1242
755d819e
AD		 1243 evergreen_mc_program(rdev);
1244 r = cayman_pcie_gart_enable(rdev);
1245 if (r)
1246 return r;
1247 cayman_gpu_init(rdev);
1248
cb92d452 1249 r = evergreen_blit_init(rdev);
755d819e 1250 if (r) {
fb3d9e97 1251 r600_blit_fini(rdev);
27cd7769 1252 rdev->asic->copy.copy = NULL;
755d819e
AD		 1253 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1254 }
755d819e 1255
c420c745
AD		 1256 /* allocate rlc buffers */
1257 if (rdev->flags & RADEON_IS_IGP) {
1258 r = si_rlc_init(rdev);
1259 if (r) {
1260 DRM_ERROR("Failed to init rlc BOs!\n");
1261 return r;
1262 }
1263 }
1264
755d819e
AD		 1265 /* allocate wb buffer */
1266 r = radeon_wb_init(rdev);
1267 if (r)
1268 return r;
1269
30eb77f4
JG		 1270 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1271 if (r) {
1272 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1273 return r;
1274 }
1275
1276 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1277 if (r) {
1278 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1279 return r;
1280 }
1281
1282 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1283 if (r) {
1284 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1285 return r;
1286 }
1287
755d819e
AD		 1288 /* Enable IRQ */
1289 r = r600_irq_init(rdev);
1290 if (r) {
1291 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1292 radeon_irq_kms_fini(rdev);
1293 return r;
1294 }
1295 evergreen_irq_set(rdev);
1296
e32eb50d 1297 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1298 CP_RB0_RPTR, CP_RB0_WPTR,
1299 0, 0xfffff, RADEON_CP_PACKET2);
755d819e
AD		 1300 if (r)
1301 return r;
1302 r = cayman_cp_load_microcode(rdev);
1303 if (r)
1304 return r;
1305 r = cayman_cp_resume(rdev);
1306 if (r)
1307 return r;
1308
2898c348
CK		 1309 r = radeon_ib_pool_init(rdev);
1310 if (r) {
1311 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 1312 return r;
2898c348 1313 }
b15ba512 1314
c6105f24
CK		 1315 r = radeon_vm_manager_init(rdev);
1316 if (r) {
1317 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
721604a1 1318 return r;
c6105f24 1319 }
721604a1 1320
6b53a050
RM		 1321 r = r600_audio_init(rdev);
1322 if (r)
1323 return r;
1324
755d819e
AD		 1325 return 0;
1326}
1327
1328int cayman_resume(struct radeon_device *rdev)
1329{
1330 int r;
1331
1332 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1333 * posting will perform necessary task to bring back GPU into good
1334 * shape.
1335 */
1336 /* post card */
1337 atom_asic_init(rdev->mode_info.atom_context);
1338
b15ba512 1339 rdev->accel_working = true;
755d819e
AD		 1340 r = cayman_startup(rdev);
1341 if (r) {
1342 DRM_ERROR("cayman startup failed on resume\n");
6b7746e8 1343 rdev->accel_working = false;
755d819e
AD		 1344 return r;
1345 }
755d819e 1346 return r;
755d819e
AD		 1347}
1348
1349int cayman_suspend(struct radeon_device *rdev)
1350{
6b53a050 1351 r600_audio_fini(rdev);
755d819e 1352 cayman_cp_enable(rdev, false);
e32eb50d 1353 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
755d819e
AD		 1354 evergreen_irq_suspend(rdev);
1355 radeon_wb_disable(rdev);
1356 cayman_pcie_gart_disable(rdev);
755d819e
AD		 1357 return 0;
1358}
1359
1360/* Plan is to move initialization in that function and use
1361 * helper function so that radeon_device_init pretty much
1362 * do nothing more than calling asic specific function. This
1363 * should also allow to remove a bunch of callback function
1364 * like vram_info.
1365 */
1366int cayman_init(struct radeon_device *rdev)
1367{
e32eb50d 1368 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1369 int r;
1370
755d819e
AD		 1371 /* Read BIOS */
1372 if (!radeon_get_bios(rdev)) {
1373 if (ASIC_IS_AVIVO(rdev))
1374 return -EINVAL;
1375 }
1376 /* Must be an ATOMBIOS */
1377 if (!rdev->is_atom_bios) {
1378 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1379 return -EINVAL;
1380 }
1381 r = radeon_atombios_init(rdev);
1382 if (r)
1383 return r;
1384
1385 /* Post card if necessary */
1386 if (!radeon_card_posted(rdev)) {
1387 if (!rdev->bios) {
1388 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1389 return -EINVAL;
1390 }
1391 DRM_INFO("GPU not posted. posting now...\n");
1392 atom_asic_init(rdev->mode_info.atom_context);
1393 }
1394 /* Initialize scratch registers */
1395 r600_scratch_init(rdev);
1396 /* Initialize surface registers */
1397 radeon_surface_init(rdev);
1398 /* Initialize clocks */
1399 radeon_get_clock_info(rdev->ddev);
1400 /* Fence driver */
30eb77f4 1401 r = radeon_fence_driver_init(rdev);
755d819e
AD		 1402 if (r)
1403 return r;
1404 /* initialize memory controller */
1405 r = evergreen_mc_init(rdev);
1406 if (r)
1407 return r;
1408 /* Memory manager */
1409 r = radeon_bo_init(rdev);
1410 if (r)
1411 return r;
1412
1413 r = radeon_irq_kms_init(rdev);
1414 if (r)
1415 return r;
1416
e32eb50d
CK		 1417 ring->ring_obj = NULL;
1418 r600_ring_init(rdev, ring, 1024 * 1024);
755d819e
AD		 1419
1420 rdev->ih.ring_obj = NULL;
1421 r600_ih_ring_init(rdev, 64 * 1024);
1422
1423 r = r600_pcie_gart_init(rdev);
1424 if (r)
1425 return r;
1426
1427 rdev->accel_working = true;
1428 r = cayman_startup(rdev);
1429 if (r) {
1430 dev_err(rdev->dev, "disabling GPU acceleration\n");
1431 cayman_cp_fini(rdev);
1432 r600_irq_fini(rdev);
c420c745
AD		 1433 if (rdev->flags & RADEON_IS_IGP)
1434 si_rlc_fini(rdev);
755d819e 1435 radeon_wb_fini(rdev);
2898c348 1436 radeon_ib_pool_fini(rdev);
721604a1 1437 radeon_vm_manager_fini(rdev);
755d819e
AD		 1438 radeon_irq_kms_fini(rdev);
1439 cayman_pcie_gart_fini(rdev);
1440 rdev->accel_working = false;
1441 }
755d819e
AD		 1442
1443 /* Don't start up if the MC ucode is missing.
1444 * The default clocks and voltages before the MC ucode
1445 * is loaded are not suffient for advanced operations.
c420c745
AD		 1446 *
1447 * We can skip this check for TN, because there is no MC
1448 * ucode.
755d819e 1449 */
c420c745 1450 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
755d819e
AD		 1451 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1452 return -EINVAL;
1453 }
1454
1455 return 0;
1456}
1457
1458void cayman_fini(struct radeon_device *rdev)
1459{
fb3d9e97 1460 r600_blit_fini(rdev);
755d819e
AD		 1461 cayman_cp_fini(rdev);
1462 r600_irq_fini(rdev);
c420c745
AD		 1463 if (rdev->flags & RADEON_IS_IGP)
1464 si_rlc_fini(rdev);
755d819e 1465 radeon_wb_fini(rdev);
721604a1 1466 radeon_vm_manager_fini(rdev);
2898c348 1467 radeon_ib_pool_fini(rdev);
755d819e
AD		 1468 radeon_irq_kms_fini(rdev);
1469 cayman_pcie_gart_fini(rdev);
16cdf04d 1470 r600_vram_scratch_fini(rdev);
755d819e
AD		 1471 radeon_gem_fini(rdev);
1472 radeon_fence_driver_fini(rdev);
1473 radeon_bo_fini(rdev);
1474 radeon_atombios_fini(rdev);
1475 kfree(rdev->bios);
1476 rdev->bios = NULL;
1477}
1478
721604a1
JG		 1479/*
1480 * vm
1481 */
1482int cayman_vm_init(struct radeon_device *rdev)
1483{
1484 /* number of VMs */
1485 rdev->vm_manager.nvm = 8;
1486 /* base offset of vram pages */
e71270fd
AD		 1487 if (rdev->flags & RADEON_IS_IGP) {
1488 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1489 tmp <<= 22;
1490 rdev->vm_manager.vram_base_offset = tmp;
1491 } else
1492 rdev->vm_manager.vram_base_offset = 0;
721604a1
JG		 1493 return 0;
1494}
1495
1496void cayman_vm_fini(struct radeon_device *rdev)
1497{
1498}
1499
dce34bfd 1500#define R600_ENTRY_VALID (1 << 0)
721604a1
JG		 1501#define R600_PTE_SYSTEM (1 << 1)
1502#define R600_PTE_SNOOPED (1 << 2)
1503#define R600_PTE_READABLE (1 << 5)
1504#define R600_PTE_WRITEABLE (1 << 6)
1505
089a786e 1506uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
721604a1
JG		 1507{
1508 uint32_t r600_flags = 0;
dce34bfd 1509 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
721604a1
JG		 1510 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1511 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1512 if (flags & RADEON_VM_PAGE_SYSTEM) {
1513 r600_flags |= R600_PTE_SYSTEM;
1514 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1515 }
1516 return r600_flags;
1517}
1518
7a083293
AD		 1519/**
1520 * cayman_vm_set_page - update the page tables using the CP
1521 *
1522 * @rdev: radeon_device pointer
dce34bfd
CK		 1523 * @pe: addr of the page entry
1524 * @addr: dst addr to write into pe
1525 * @count: number of page entries to update
1526 * @incr: increase next addr by incr bytes
1527 * @flags: access flags
7a083293
AD		 1528 *
1529 * Update the page tables using the CP (cayman-si).
1530 */
dce34bfd
CK		 1531void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1532 uint64_t addr, unsigned count,
1533 uint32_t incr, uint32_t flags)
721604a1 1534{
2a6f1abb 1535 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
dce34bfd 1536 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
089a786e
CK		 1537 int i;
1538
dce34bfd
CK		 1539 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, 1 + count * 2));
1540 radeon_ring_write(ring, pe);
1541 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1542 for (i = 0; i < count; ++i) {
1543 uint64_t value = 0;
1544 if (flags & RADEON_VM_PAGE_SYSTEM) {
1545 value = radeon_vm_map_gart(rdev, addr);
1546 value &= 0xFFFFFFFFFFFFF000ULL;
1547 addr += incr;
1548
1549 } else if (flags & RADEON_VM_PAGE_VALID) {
1550 value = addr;
1551 addr += incr;
2a6f1abb 1552 }
dce34bfd
CK		 1553
1554 value |= r600_flags;
1555 radeon_ring_write(ring, value);
1556 radeon_ring_write(ring, upper_32_bits(value));
2a6f1abb 1557 }
721604a1 1558}
9b40e5d8 1559
7a083293
AD		 1560/**
1561 * cayman_vm_flush - vm flush using the CP
1562 *
1563 * @rdev: radeon_device pointer
1564 *
1565 * Update the page table base and flush the VM TLB
1566 * using the CP (cayman-si).
1567 */
9b40e5d8
CK		 1568void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib)
1569{
1570 struct radeon_ring *ring = &rdev->ring[ib->ring];
ee60e29f 1571 struct radeon_vm *vm = ib->vm;
9b40e5d8 1572
ee60e29f 1573 if (vm == NULL)
9b40e5d8
CK		 1574 return;
1575
ee60e29f
CK		 1576 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0));
1577 radeon_ring_write(ring, 0);
1578
1579 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0));
1580 radeon_ring_write(ring, vm->last_pfn);
1581
1582 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
fa87e62d 1583 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 1584
9b40e5d8
CK		 1585 /* flush hdp cache */
1586 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1587 radeon_ring_write(ring, 0x1);
1588
1589 /* bits 0-7 are the VM contexts0-7 */
1590 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
1591 radeon_ring_write(ring, 1 << ib->vm->id);
1592}
Linux 6.x block layer and io_uring tree(s)