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drm/radeon: fix HD6790, HD6570 backend programming
[linux-2.6-block.git] / drivers / gpu / drm / radeon / ni.c
CommitLineData
0af62b01
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
e0cd3608 27#include <linux/module.h>
0af62b01
AD		 28#include "drmP.h"
29#include "radeon.h"
30#include "radeon_asic.h"
31#include "radeon_drm.h"
32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
0c88a02e 35#include "cayman_blit_shaders.h"
0af62b01 36
b9952a8a
AD		 37extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
755d819e
AD		 40extern void evergreen_mc_program(struct radeon_device *rdev);
41extern void evergreen_irq_suspend(struct radeon_device *rdev);
42extern int evergreen_mc_init(struct radeon_device *rdev);
d054ac16 43extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
b07759bf 44extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
c420c745
AD		 45extern void si_rlc_fini(struct radeon_device *rdev);
46extern int si_rlc_init(struct radeon_device *rdev);
b9952a8a 47
0af62b01
AD		 48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
50#define EVERGREEN_RLC_UCODE_SIZE 768
51#define BTC_MC_UCODE_SIZE 6024
52
9b8253ce
AD		 53#define CAYMAN_PFP_UCODE_SIZE 2176
54#define CAYMAN_PM4_UCODE_SIZE 2176
55#define CAYMAN_RLC_UCODE_SIZE 1024
56#define CAYMAN_MC_UCODE_SIZE 6037
57
c420c745
AD		 58#define ARUBA_RLC_UCODE_SIZE 1536
59
0af62b01
AD		 60/* Firmware Names */
61MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
62MODULE_FIRMWARE("radeon/BARTS_me.bin");
63MODULE_FIRMWARE("radeon/BARTS_mc.bin");
64MODULE_FIRMWARE("radeon/BTC_rlc.bin");
65MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
66MODULE_FIRMWARE("radeon/TURKS_me.bin");
67MODULE_FIRMWARE("radeon/TURKS_mc.bin");
68MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
69MODULE_FIRMWARE("radeon/CAICOS_me.bin");
70MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
9b8253ce
AD		 71MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
72MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
73MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
74MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
c420c745
AD		 75MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
76MODULE_FIRMWARE("radeon/ARUBA_me.bin");
77MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
0af62b01
AD		 78
79#define BTC_IO_MC_REGS_SIZE 29
80
81static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
82 {0x00000077, 0xff010100},
83 {0x00000078, 0x00000000},
84 {0x00000079, 0x00001434},
85 {0x0000007a, 0xcc08ec08},
86 {0x0000007b, 0x00040000},
87 {0x0000007c, 0x000080c0},
88 {0x0000007d, 0x09000000},
89 {0x0000007e, 0x00210404},
90 {0x00000081, 0x08a8e800},
91 {0x00000082, 0x00030444},
92 {0x00000083, 0x00000000},
93 {0x00000085, 0x00000001},
94 {0x00000086, 0x00000002},
95 {0x00000087, 0x48490000},
96 {0x00000088, 0x20244647},
97 {0x00000089, 0x00000005},
98 {0x0000008b, 0x66030000},
99 {0x0000008c, 0x00006603},
100 {0x0000008d, 0x00000100},
101 {0x0000008f, 0x00001c0a},
102 {0x00000090, 0xff000001},
103 {0x00000094, 0x00101101},
104 {0x00000095, 0x00000fff},
105 {0x00000096, 0x00116fff},
106 {0x00000097, 0x60010000},
107 {0x00000098, 0x10010000},
108 {0x00000099, 0x00006000},
109 {0x0000009a, 0x00001000},
110 {0x0000009f, 0x00946a00}
111};
112
113static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
114 {0x00000077, 0xff010100},
115 {0x00000078, 0x00000000},
116 {0x00000079, 0x00001434},
117 {0x0000007a, 0xcc08ec08},
118 {0x0000007b, 0x00040000},
119 {0x0000007c, 0x000080c0},
120 {0x0000007d, 0x09000000},
121 {0x0000007e, 0x00210404},
122 {0x00000081, 0x08a8e800},
123 {0x00000082, 0x00030444},
124 {0x00000083, 0x00000000},
125 {0x00000085, 0x00000001},
126 {0x00000086, 0x00000002},
127 {0x00000087, 0x48490000},
128 {0x00000088, 0x20244647},
129 {0x00000089, 0x00000005},
130 {0x0000008b, 0x66030000},
131 {0x0000008c, 0x00006603},
132 {0x0000008d, 0x00000100},
133 {0x0000008f, 0x00001c0a},
134 {0x00000090, 0xff000001},
135 {0x00000094, 0x00101101},
136 {0x00000095, 0x00000fff},
137 {0x00000096, 0x00116fff},
138 {0x00000097, 0x60010000},
139 {0x00000098, 0x10010000},
140 {0x00000099, 0x00006000},
141 {0x0000009a, 0x00001000},
142 {0x0000009f, 0x00936a00}
143};
144
145static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
146 {0x00000077, 0xff010100},
147 {0x00000078, 0x00000000},
148 {0x00000079, 0x00001434},
149 {0x0000007a, 0xcc08ec08},
150 {0x0000007b, 0x00040000},
151 {0x0000007c, 0x000080c0},
152 {0x0000007d, 0x09000000},
153 {0x0000007e, 0x00210404},
154 {0x00000081, 0x08a8e800},
155 {0x00000082, 0x00030444},
156 {0x00000083, 0x00000000},
157 {0x00000085, 0x00000001},
158 {0x00000086, 0x00000002},
159 {0x00000087, 0x48490000},
160 {0x00000088, 0x20244647},
161 {0x00000089, 0x00000005},
162 {0x0000008b, 0x66030000},
163 {0x0000008c, 0x00006603},
164 {0x0000008d, 0x00000100},
165 {0x0000008f, 0x00001c0a},
166 {0x00000090, 0xff000001},
167 {0x00000094, 0x00101101},
168 {0x00000095, 0x00000fff},
169 {0x00000096, 0x00116fff},
170 {0x00000097, 0x60010000},
171 {0x00000098, 0x10010000},
172 {0x00000099, 0x00006000},
173 {0x0000009a, 0x00001000},
174 {0x0000009f, 0x00916a00}
175};
176
9b8253ce
AD		 177static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
178 {0x00000077, 0xff010100},
179 {0x00000078, 0x00000000},
180 {0x00000079, 0x00001434},
181 {0x0000007a, 0xcc08ec08},
182 {0x0000007b, 0x00040000},
183 {0x0000007c, 0x000080c0},
184 {0x0000007d, 0x09000000},
185 {0x0000007e, 0x00210404},
186 {0x00000081, 0x08a8e800},
187 {0x00000082, 0x00030444},
188 {0x00000083, 0x00000000},
189 {0x00000085, 0x00000001},
190 {0x00000086, 0x00000002},
191 {0x00000087, 0x48490000},
192 {0x00000088, 0x20244647},
193 {0x00000089, 0x00000005},
194 {0x0000008b, 0x66030000},
195 {0x0000008c, 0x00006603},
196 {0x0000008d, 0x00000100},
197 {0x0000008f, 0x00001c0a},
198 {0x00000090, 0xff000001},
199 {0x00000094, 0x00101101},
200 {0x00000095, 0x00000fff},
201 {0x00000096, 0x00116fff},
202 {0x00000097, 0x60010000},
203 {0x00000098, 0x10010000},
204 {0x00000099, 0x00006000},
205 {0x0000009a, 0x00001000},
206 {0x0000009f, 0x00976b00}
207};
208
755d819e 209int ni_mc_load_microcode(struct radeon_device *rdev)
0af62b01
AD		 210{
211 const __be32 *fw_data;
212 u32 mem_type, running, blackout = 0;
213 u32 *io_mc_regs;
9b8253ce 214 int i, ucode_size, regs_size;
0af62b01
AD		 215
216 if (!rdev->mc_fw)
217 return -EINVAL;
218
219 switch (rdev->family) {
220 case CHIP_BARTS:
221 io_mc_regs = (u32 *)&barts_io_mc_regs;
9b8253ce
AD		 222 ucode_size = BTC_MC_UCODE_SIZE;
223 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 224 break;
225 case CHIP_TURKS:
226 io_mc_regs = (u32 *)&turks_io_mc_regs;
9b8253ce
AD		 227 ucode_size = BTC_MC_UCODE_SIZE;
228 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 229 break;
230 case CHIP_CAICOS:
231 default:
232 io_mc_regs = (u32 *)&caicos_io_mc_regs;
9b8253ce
AD		 233 ucode_size = BTC_MC_UCODE_SIZE;
234 regs_size = BTC_IO_MC_REGS_SIZE;
235 break;
236 case CHIP_CAYMAN:
237 io_mc_regs = (u32 *)&cayman_io_mc_regs;
238 ucode_size = CAYMAN_MC_UCODE_SIZE;
239 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 240 break;
241 }
242
243 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
244 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
245
246 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
247 if (running) {
248 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
249 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
250 }
251
252 /* reset the engine and set to writable */
253 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
254 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
255
256 /* load mc io regs */
9b8253ce 257 for (i = 0; i < regs_size; i++) {
0af62b01
AD		 258 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
259 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
260 }
261 /* load the MC ucode */
262 fw_data = (const __be32 *)rdev->mc_fw->data;
9b8253ce 263 for (i = 0; i < ucode_size; i++)
0af62b01
AD		 264 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
265
266 /* put the engine back into the active state */
267 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
268 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
270
271 /* wait for training to complete */
0e2c978e
AD		 272 for (i = 0; i < rdev->usec_timeout; i++) {
273 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
274 break;
275 udelay(1);
276 }
0af62b01
AD		 277
278 if (running)
279 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
280 }
281
282 return 0;
283}
284
285int ni_init_microcode(struct radeon_device *rdev)
286{
287 struct platform_device *pdev;
288 const char *chip_name;
289 const char *rlc_chip_name;
290 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
291 char fw_name[30];
292 int err;
293
294 DRM_DEBUG("\n");
295
296 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
297 err = IS_ERR(pdev);
298 if (err) {
299 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
300 return -EINVAL;
301 }
302
303 switch (rdev->family) {
304 case CHIP_BARTS:
305 chip_name = "BARTS";
306 rlc_chip_name = "BTC";
9b8253ce
AD		 307 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
308 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
309 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
310 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 311 break;
312 case CHIP_TURKS:
313 chip_name = "TURKS";
314 rlc_chip_name = "BTC";
9b8253ce
AD		 315 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
316 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
317 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
318 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 319 break;
320 case CHIP_CAICOS:
321 chip_name = "CAICOS";
322 rlc_chip_name = "BTC";
9b8253ce
AD		 323 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
324 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
325 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
326 mc_req_size = BTC_MC_UCODE_SIZE * 4;
327 break;
328 case CHIP_CAYMAN:
329 chip_name = "CAYMAN";
330 rlc_chip_name = "CAYMAN";
331 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
332 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
333 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
334 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
0af62b01 335 break;
c420c745
AD		 336 case CHIP_ARUBA:
337 chip_name = "ARUBA";
338 rlc_chip_name = "ARUBA";
339 /* pfp/me same size as CAYMAN */
340 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
341 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
342 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
343 mc_req_size = 0;
344 break;
0af62b01
AD		 345 default: BUG();
346 }
347
0af62b01
AD		 348 DRM_INFO("Loading %s Microcode\n", chip_name);
349
350 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
352 if (err)
353 goto out;
354 if (rdev->pfp_fw->size != pfp_req_size) {
355 printk(KERN_ERR
356 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
357 rdev->pfp_fw->size, fw_name);
358 err = -EINVAL;
359 goto out;
360 }
361
362 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
364 if (err)
365 goto out;
366 if (rdev->me_fw->size != me_req_size) {
367 printk(KERN_ERR
368 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
369 rdev->me_fw->size, fw_name);
370 err = -EINVAL;
371 }
372
373 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
374 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
375 if (err)
376 goto out;
377 if (rdev->rlc_fw->size != rlc_req_size) {
378 printk(KERN_ERR
379 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
380 rdev->rlc_fw->size, fw_name);
381 err = -EINVAL;
382 }
383
c420c745
AD		 384 /* no MC ucode on TN */
385 if (!(rdev->flags & RADEON_IS_IGP)) {
386 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
387 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
388 if (err)
389 goto out;
390 if (rdev->mc_fw->size != mc_req_size) {
391 printk(KERN_ERR
392 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
393 rdev->mc_fw->size, fw_name);
394 err = -EINVAL;
395 }
0af62b01
AD		 396 }
397out:
398 platform_device_unregister(pdev);
399
400 if (err) {
401 if (err != -EINVAL)
402 printk(KERN_ERR
403 "ni_cp: Failed to load firmware \"%s\"\n",
404 fw_name);
405 release_firmware(rdev->pfp_fw);
406 rdev->pfp_fw = NULL;
407 release_firmware(rdev->me_fw);
408 rdev->me_fw = NULL;
409 release_firmware(rdev->rlc_fw);
410 rdev->rlc_fw = NULL;
411 release_firmware(rdev->mc_fw);
412 rdev->mc_fw = NULL;
413 }
414 return err;
415}
416
fecf1d07
AD		 417/*
418 * Core functions
419 */
420static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
421 u32 num_tile_pipes,
422 u32 num_backends_per_asic,
423 u32 *backend_disable_mask_per_asic,
424 u32 num_shader_engines)
425{
426 u32 backend_map = 0;
427 u32 enabled_backends_mask = 0;
428 u32 enabled_backends_count = 0;
429 u32 num_backends_per_se;
430 u32 cur_pipe;
431 u32 swizzle_pipe[CAYMAN_MAX_PIPES];
432 u32 cur_backend = 0;
433 u32 i;
434 bool force_no_swizzle;
435
436 /* force legal values */
437 if (num_tile_pipes < 1)
438 num_tile_pipes = 1;
439 if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
440 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
441 if (num_shader_engines < 1)
442 num_shader_engines = 1;
443 if (num_shader_engines > rdev->config.cayman.max_shader_engines)
444 num_shader_engines = rdev->config.cayman.max_shader_engines;
c289cff1 445 if (num_backends_per_asic < num_shader_engines)
fecf1d07
AD		 446 num_backends_per_asic = num_shader_engines;
447 if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
448 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
449
450 /* make sure we have the same number of backends per se */
451 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
452 /* set up the number of backends per se */
453 num_backends_per_se = num_backends_per_asic / num_shader_engines;
454 if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
455 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
456 num_backends_per_asic = num_backends_per_se * num_shader_engines;
457 }
458
459 /* create enable mask and count for enabled backends */
460 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
461 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
462 enabled_backends_mask |= (1 << i);
463 ++enabled_backends_count;
464 }
465 if (enabled_backends_count == num_backends_per_asic)
466 break;
467 }
468
469 /* force the backends mask to match the current number of backends */
470 if (enabled_backends_count != num_backends_per_asic) {
471 u32 this_backend_enabled;
472 u32 shader_engine;
473 u32 backend_per_se;
474
475 enabled_backends_mask = 0;
476 enabled_backends_count = 0;
477 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
478 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
479 /* calc the current se */
480 shader_engine = i / rdev->config.cayman.max_backends_per_se;
481 /* calc the backend per se */
482 backend_per_se = i % rdev->config.cayman.max_backends_per_se;
483 /* default to not enabled */
484 this_backend_enabled = 0;
485 if ((shader_engine < num_shader_engines) &&
486 (backend_per_se < num_backends_per_se))
487 this_backend_enabled = 1;
488 if (this_backend_enabled) {
489 enabled_backends_mask |= (1 << i);
490 *backend_disable_mask_per_asic &= ~(1 << i);
491 ++enabled_backends_count;
492 }
493 }
494 }
495
496
497 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
498 switch (rdev->family) {
499 case CHIP_CAYMAN:
7b76e479 500 case CHIP_ARUBA:
fecf1d07
AD		 501 force_no_swizzle = true;
502 break;
503 default:
504 force_no_swizzle = false;
505 break;
506 }
507 if (force_no_swizzle) {
508 bool last_backend_enabled = false;
509
510 force_no_swizzle = false;
511 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
512 if (((enabled_backends_mask >> i) & 1) == 1) {
513 if (last_backend_enabled)
514 force_no_swizzle = true;
515 last_backend_enabled = true;
516 } else
517 last_backend_enabled = false;
518 }
519 }
520
521 switch (num_tile_pipes) {
522 case 1:
523 case 3:
524 case 5:
525 case 7:
526 DRM_ERROR("odd number of pipes!\n");
527 break;
528 case 2:
529 swizzle_pipe[0] = 0;
530 swizzle_pipe[1] = 1;
531 break;
532 case 4:
533 if (force_no_swizzle) {
534 swizzle_pipe[0] = 0;
535 swizzle_pipe[1] = 1;
536 swizzle_pipe[2] = 2;
537 swizzle_pipe[3] = 3;
538 } else {
539 swizzle_pipe[0] = 0;
540 swizzle_pipe[1] = 2;
541 swizzle_pipe[2] = 1;
542 swizzle_pipe[3] = 3;
543 }
544 break;
545 case 6:
546 if (force_no_swizzle) {
547 swizzle_pipe[0] = 0;
548 swizzle_pipe[1] = 1;
549 swizzle_pipe[2] = 2;
550 swizzle_pipe[3] = 3;
551 swizzle_pipe[4] = 4;
552 swizzle_pipe[5] = 5;
553 } else {
554 swizzle_pipe[0] = 0;
555 swizzle_pipe[1] = 2;
556 swizzle_pipe[2] = 4;
557 swizzle_pipe[3] = 1;
558 swizzle_pipe[4] = 3;
559 swizzle_pipe[5] = 5;
560 }
561 break;
562 case 8:
563 if (force_no_swizzle) {
564 swizzle_pipe[0] = 0;
565 swizzle_pipe[1] = 1;
566 swizzle_pipe[2] = 2;
567 swizzle_pipe[3] = 3;
568 swizzle_pipe[4] = 4;
569 swizzle_pipe[5] = 5;
570 swizzle_pipe[6] = 6;
571 swizzle_pipe[7] = 7;
572 } else {
573 swizzle_pipe[0] = 0;
574 swizzle_pipe[1] = 2;
575 swizzle_pipe[2] = 4;
576 swizzle_pipe[3] = 6;
577 swizzle_pipe[4] = 1;
578 swizzle_pipe[5] = 3;
579 swizzle_pipe[6] = 5;
580 swizzle_pipe[7] = 7;
581 }
582 break;
583 }
584
585 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
586 while (((1 << cur_backend) & enabled_backends_mask) == 0)
587 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
588
589 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
590
591 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
592 }
593
594 return backend_map;
595}
596
fecf1d07
AD		 597static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
598 u32 disable_mask_per_se,
599 u32 max_disable_mask_per_se,
600 u32 num_shader_engines)
601{
602 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
603 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
604
605 if (num_shader_engines == 1)
606 return disable_mask_per_asic;
607 else if (num_shader_engines == 2)
608 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
609 else
610 return 0xffffffff;
611}
612
613static void cayman_gpu_init(struct radeon_device *rdev)
614{
615 u32 cc_rb_backend_disable = 0;
616 u32 cc_gc_shader_pipe_config;
617 u32 gb_addr_config = 0;
618 u32 mc_shared_chmap, mc_arb_ramcfg;
619 u32 gb_backend_map;
620 u32 cgts_tcc_disable;
621 u32 sx_debug_1;
622 u32 smx_dc_ctl0;
623 u32 gc_user_shader_pipe_config;
624 u32 gc_user_rb_backend_disable;
625 u32 cgts_user_tcc_disable;
626 u32 cgts_sm_ctrl_reg;
627 u32 hdp_host_path_cntl;
628 u32 tmp;
629 int i, j;
630
631 switch (rdev->family) {
632 case CHIP_CAYMAN:
fecf1d07
AD		 633 rdev->config.cayman.max_shader_engines = 2;
634 rdev->config.cayman.max_pipes_per_simd = 4;
635 rdev->config.cayman.max_tile_pipes = 8;
636 rdev->config.cayman.max_simds_per_se = 12;
637 rdev->config.cayman.max_backends_per_se = 4;
638 rdev->config.cayman.max_texture_channel_caches = 8;
639 rdev->config.cayman.max_gprs = 256;
640 rdev->config.cayman.max_threads = 256;
641 rdev->config.cayman.max_gs_threads = 32;
642 rdev->config.cayman.max_stack_entries = 512;
643 rdev->config.cayman.sx_num_of_sets = 8;
644 rdev->config.cayman.sx_max_export_size = 256;
645 rdev->config.cayman.sx_max_export_pos_size = 64;
646 rdev->config.cayman.sx_max_export_smx_size = 192;
647 rdev->config.cayman.max_hw_contexts = 8;
648 rdev->config.cayman.sq_num_cf_insts = 2;
649
650 rdev->config.cayman.sc_prim_fifo_size = 0x100;
651 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
652 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
653 break;
7b76e479
AD		 654 case CHIP_ARUBA:
655 default:
656 rdev->config.cayman.max_shader_engines = 1;
657 rdev->config.cayman.max_pipes_per_simd = 4;
658 rdev->config.cayman.max_tile_pipes = 2;
659 if ((rdev->pdev->device == 0x9900) ||
660 (rdev->pdev->device == 0x9901)) {
661 rdev->config.cayman.max_simds_per_se = 6;
662 rdev->config.cayman.max_backends_per_se = 2;
663 } else if ((rdev->pdev->device == 0x9903) ||
664 (rdev->pdev->device == 0x9904)) {
665 rdev->config.cayman.max_simds_per_se = 4;
666 rdev->config.cayman.max_backends_per_se = 2;
667 } else if ((rdev->pdev->device == 0x9990) ||
668 (rdev->pdev->device == 0x9991)) {
669 rdev->config.cayman.max_simds_per_se = 3;
670 rdev->config.cayman.max_backends_per_se = 1;
671 } else {
672 rdev->config.cayman.max_simds_per_se = 2;
673 rdev->config.cayman.max_backends_per_se = 1;
674 }
675 rdev->config.cayman.max_texture_channel_caches = 2;
676 rdev->config.cayman.max_gprs = 256;
677 rdev->config.cayman.max_threads = 256;
678 rdev->config.cayman.max_gs_threads = 32;
679 rdev->config.cayman.max_stack_entries = 512;
680 rdev->config.cayman.sx_num_of_sets = 8;
681 rdev->config.cayman.sx_max_export_size = 256;
682 rdev->config.cayman.sx_max_export_pos_size = 64;
683 rdev->config.cayman.sx_max_export_smx_size = 192;
684 rdev->config.cayman.max_hw_contexts = 8;
685 rdev->config.cayman.sq_num_cf_insts = 2;
686
687 rdev->config.cayman.sc_prim_fifo_size = 0x40;
688 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
689 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
690 break;
fecf1d07
AD		 691 }
692
693 /* Initialize HDP */
694 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
695 WREG32((0x2c14 + j), 0x00000000);
696 WREG32((0x2c18 + j), 0x00000000);
697 WREG32((0x2c1c + j), 0x00000000);
698 WREG32((0x2c20 + j), 0x00000000);
699 WREG32((0x2c24 + j), 0x00000000);
700 }
701
702 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
703
d054ac16
AD		 704 evergreen_fix_pci_max_read_req_size(rdev);
705
fecf1d07
AD		 706 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
707 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
708
709 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
710 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
7b76e479
AD		 711 cgts_tcc_disable = 0xffff0000;
712 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
713 cgts_tcc_disable &= ~(1 << (16 + i));
fecf1d07
AD		 714 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
715 gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
716 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
717
718 rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
719 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
720 rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
721 rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
722 tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
723 rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
724 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
725 rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
726 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
727 rdev->config.cayman.backend_disable_mask_per_asic =
728 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
729 rdev->config.cayman.num_shader_engines);
730 rdev->config.cayman.backend_map =
731 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
732 rdev->config.cayman.num_backends_per_se *
733 rdev->config.cayman.num_shader_engines,
734 &rdev->config.cayman.backend_disable_mask_per_asic,
735 rdev->config.cayman.num_shader_engines);
736 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
737 rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
738 tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
739 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
740 if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
741 rdev->config.cayman.mem_max_burst_length_bytes = 512;
742 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
743 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
744 if (rdev->config.cayman.mem_row_size_in_kb > 4)
745 rdev->config.cayman.mem_row_size_in_kb = 4;
746 /* XXX use MC settings? */
747 rdev->config.cayman.shader_engine_tile_size = 32;
748 rdev->config.cayman.num_gpus = 1;
749 rdev->config.cayman.multi_gpu_tile_size = 64;
750
751 //gb_addr_config = 0x02011003
752#if 0
753 gb_addr_config = RREG32(GB_ADDR_CONFIG);
754#else
755 gb_addr_config = 0;
756 switch (rdev->config.cayman.num_tile_pipes) {
757 case 1:
758 default:
759 gb_addr_config |= NUM_PIPES(0);
760 break;
761 case 2:
762 gb_addr_config |= NUM_PIPES(1);
763 break;
764 case 4:
765 gb_addr_config |= NUM_PIPES(2);
766 break;
767 case 8:
768 gb_addr_config |= NUM_PIPES(3);
769 break;
770 }
771
772 tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
773 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
774 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
775 tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
776 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
777 switch (rdev->config.cayman.num_gpus) {
778 case 1:
779 default:
780 gb_addr_config |= NUM_GPUS(0);
781 break;
782 case 2:
783 gb_addr_config |= NUM_GPUS(1);
784 break;
785 case 4:
786 gb_addr_config |= NUM_GPUS(2);
787 break;
788 }
789 switch (rdev->config.cayman.multi_gpu_tile_size) {
790 case 16:
791 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
792 break;
793 case 32:
794 default:
795 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
796 break;
797 case 64:
798 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
799 break;
800 case 128:
801 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
802 break;
803 }
804 switch (rdev->config.cayman.mem_row_size_in_kb) {
805 case 1:
806 default:
807 gb_addr_config |= ROW_SIZE(0);
808 break;
809 case 2:
810 gb_addr_config |= ROW_SIZE(1);
811 break;
812 case 4:
813 gb_addr_config |= ROW_SIZE(2);
814 break;
815 }
816#endif
817
818 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
819 rdev->config.cayman.num_tile_pipes = (1 << tmp);
820 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
821 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
822 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
823 rdev->config.cayman.num_shader_engines = tmp + 1;
824 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
825 rdev->config.cayman.num_gpus = tmp + 1;
826 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
827 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
828 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
829 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
830
831 //gb_backend_map = 0x76541032;
832#if 0
833 gb_backend_map = RREG32(GB_BACKEND_MAP);
834#else
835 gb_backend_map =
836 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
837 rdev->config.cayman.num_backends_per_se *
838 rdev->config.cayman.num_shader_engines,
839 &rdev->config.cayman.backend_disable_mask_per_asic,
840 rdev->config.cayman.num_shader_engines);
841#endif
842 /* setup tiling info dword. gb_addr_config is not adequate since it does
843 * not have bank info, so create a custom tiling dword.
844 * bits 3:0 num_pipes
845 * bits 7:4 num_banks
846 * bits 11:8 group_size
847 * bits 15:12 row_size
848 */
849 rdev->config.cayman.tile_config = 0;
850 switch (rdev->config.cayman.num_tile_pipes) {
851 case 1:
852 default:
853 rdev->config.cayman.tile_config |= (0 << 0);
854 break;
855 case 2:
856 rdev->config.cayman.tile_config |= (1 << 0);
857 break;
858 case 4:
859 rdev->config.cayman.tile_config |= (2 << 0);
860 break;
861 case 8:
862 rdev->config.cayman.tile_config |= (3 << 0);
863 break;
864 }
7b76e479
AD		 865
866 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
867 if (rdev->flags & RADEON_IS_IGP)
1f73cca7 868 rdev->config.cayman.tile_config |= 1 << 4;
29d65406
AD		 869 else {
870 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
871 rdev->config.cayman.tile_config |= 1 << 4;
872 else
873 rdev->config.cayman.tile_config |= 0 << 4;
874 }
fecf1d07 875 rdev->config.cayman.tile_config |=
cde5083b 876 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
fecf1d07
AD		 877 rdev->config.cayman.tile_config |=
878 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
879
e55b9422 880 rdev->config.cayman.backend_map = gb_backend_map;
fecf1d07
AD		 881 WREG32(GB_BACKEND_MAP, gb_backend_map);
882 WREG32(GB_ADDR_CONFIG, gb_addr_config);
883 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
884 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
885
fecf1d07
AD		 886 /* primary versions */
887 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
888 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
889 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
890
891 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
892 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
893
894 /* user versions */
895 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
896 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
897 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
898
899 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
900 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
901
902 /* reprogram the shader complex */
903 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
904 for (i = 0; i < 16; i++)
905 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
906 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
907
908 /* set HW defaults for 3D engine */
909 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
910
911 sx_debug_1 = RREG32(SX_DEBUG_1);
912 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
913 WREG32(SX_DEBUG_1, sx_debug_1);
914
915 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
916 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
285e042d 917 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
fecf1d07
AD		 918 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
919
920 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
921
922 /* need to be explicitly zero-ed */
923 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
924 WREG32(SQ_LSTMP_RING_BASE, 0);
925 WREG32(SQ_HSTMP_RING_BASE, 0);
926 WREG32(SQ_ESTMP_RING_BASE, 0);
927 WREG32(SQ_GSTMP_RING_BASE, 0);
928 WREG32(SQ_VSTMP_RING_BASE, 0);
929 WREG32(SQ_PSTMP_RING_BASE, 0);
930
931 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
932
285e042d
DA		 933 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
934 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
935 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
fecf1d07 936
285e042d
DA		 937 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
938 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
939 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
fecf1d07
AD		 940
941
942 WREG32(VGT_NUM_INSTANCES, 1);
943
944 WREG32(CP_PERFMON_CNTL, 0);
945
285e042d 946 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
fecf1d07
AD		 947 FETCH_FIFO_HIWATER(0x4) |
948 DONE_FIFO_HIWATER(0xe0) |
949 ALU_UPDATE_FIFO_HIWATER(0x8)));
950
951 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
952 WREG32(SQ_CONFIG, (VC_ENABLE |
953 EXPORT_SRC_C |
954 GFX_PRIO(0) |
955 CS1_PRIO(0) |
956 CS2_PRIO(1)));
957 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
958
959 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
960 FORCE_EOV_MAX_REZ_CNT(255)));
961
962 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
963 AUTO_INVLD_EN(ES_AND_GS_AUTO));
964
965 WREG32(VGT_GS_VERTEX_REUSE, 16);
966 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
967
968 WREG32(CB_PERF_CTR0_SEL_0, 0);
969 WREG32(CB_PERF_CTR0_SEL_1, 0);
970 WREG32(CB_PERF_CTR1_SEL_0, 0);
971 WREG32(CB_PERF_CTR1_SEL_1, 0);
972 WREG32(CB_PERF_CTR2_SEL_0, 0);
973 WREG32(CB_PERF_CTR2_SEL_1, 0);
974 WREG32(CB_PERF_CTR3_SEL_0, 0);
975 WREG32(CB_PERF_CTR3_SEL_1, 0);
976
0b65f83f
DA		 977 tmp = RREG32(HDP_MISC_CNTL);
978 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
979 WREG32(HDP_MISC_CNTL, tmp);
980
fecf1d07
AD		 981 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
982 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
983
984 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
985
986 udelay(50);
987}
988
fa8198ea
AD		 989/*
990 * GART
991 */
992void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
993{
994 /* flush hdp cache */
995 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
996
997 /* bits 0-7 are the VM contexts0-7 */
998 WREG32(VM_INVALIDATE_REQUEST, 1);
999}
1000
1001int cayman_pcie_gart_enable(struct radeon_device *rdev)
1002{
721604a1 1003 int i, r;
fa8198ea 1004
c9a1be96 1005 if (rdev->gart.robj == NULL) {
fa8198ea
AD		 1006 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1007 return -EINVAL;
1008 }
1009 r = radeon_gart_table_vram_pin(rdev);
1010 if (r)
1011 return r;
1012 radeon_gart_restore(rdev);
1013 /* Setup TLB control */
721604a1
JG		 1014 WREG32(MC_VM_MX_L1_TLB_CNTL,
1015 (0xA << 7) |
1016 ENABLE_L1_TLB |
fa8198ea
AD		 1017 ENABLE_L1_FRAGMENT_PROCESSING |
1018 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
721604a1 1019 ENABLE_ADVANCED_DRIVER_MODEL |
fa8198ea
AD		 1020 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1021 /* Setup L2 cache */
1022 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1023 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1024 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1025 EFFECTIVE_L2_QUEUE_SIZE(7) |
1026 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1027 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1028 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1029 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1030 /* setup context0 */
1031 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1032 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1033 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1034 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1035 (u32)(rdev->dummy_page.addr >> 12));
1036 WREG32(VM_CONTEXT0_CNTL2, 0);
1037 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1038 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
721604a1
JG		 1039
1040 WREG32(0x15D4, 0);
1041 WREG32(0x15D8, 0);
1042 WREG32(0x15DC, 0);
1043
1044 /* empty context1-7 */
1045 for (i = 1; i < 8; i++) {
1046 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1047 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
1048 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1049 rdev->gart.table_addr >> 12);
1050 }
1051
1052 /* enable context1-7 */
1053 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1054 (u32)(rdev->dummy_page.addr >> 12));
fa8198ea
AD		 1055 WREG32(VM_CONTEXT1_CNTL2, 0);
1056 WREG32(VM_CONTEXT1_CNTL, 0);
721604a1
JG		 1057 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1058 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
fa8198ea
AD		 1059
1060 cayman_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1061 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1062 (unsigned)(rdev->mc.gtt_size >> 20),
1063 (unsigned long long)rdev->gart.table_addr);
fa8198ea
AD		 1064 rdev->gart.ready = true;
1065 return 0;
1066}
1067
1068void cayman_pcie_gart_disable(struct radeon_device *rdev)
1069{
fa8198ea
AD		 1070 /* Disable all tables */
1071 WREG32(VM_CONTEXT0_CNTL, 0);
1072 WREG32(VM_CONTEXT1_CNTL, 0);
1073 /* Setup TLB control */
1074 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1075 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1076 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1077 /* Setup L2 cache */
1078 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1079 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1080 EFFECTIVE_L2_QUEUE_SIZE(7) |
1081 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1082 WREG32(VM_L2_CNTL2, 0);
1083 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1084 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
c9a1be96 1085 radeon_gart_table_vram_unpin(rdev);
fa8198ea
AD		 1086}
1087
1088void cayman_pcie_gart_fini(struct radeon_device *rdev)
1089{
1090 cayman_pcie_gart_disable(rdev);
1091 radeon_gart_table_vram_free(rdev);
1092 radeon_gart_fini(rdev);
1093}
1094
1b37078b
AD		 1095void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1096 int ring, u32 cp_int_cntl)
1097{
1098 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1099
1100 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1101 WREG32(CP_INT_CNTL, cp_int_cntl);
1102}
1103
0c88a02e
AD		 1104/*
1105 * CP.
1106 */
b40e7e16
AD		 1107void cayman_fence_ring_emit(struct radeon_device *rdev,
1108 struct radeon_fence *fence)
1109{
1110 struct radeon_ring *ring = &rdev->ring[fence->ring];
1111 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1112
721604a1
JG		 1113 /* flush read cache over gart for this vmid */
1114 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1115 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1116 radeon_ring_write(ring, 0);
b40e7e16
AD		 1117 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1118 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1119 radeon_ring_write(ring, 0xFFFFFFFF);
1120 radeon_ring_write(ring, 0);
1121 radeon_ring_write(ring, 10); /* poll interval */
1122 /* EVENT_WRITE_EOP - flush caches, send int */
1123 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1124 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1125 radeon_ring_write(ring, addr & 0xffffffff);
1126 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1127 radeon_ring_write(ring, fence->seq);
1128 radeon_ring_write(ring, 0);
1129}
1130
721604a1
JG		 1131void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1132{
1133 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1134
1135 /* set to DX10/11 mode */
1136 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1137 radeon_ring_write(ring, 1);
1138 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1139 radeon_ring_write(ring,
1140#ifdef __BIG_ENDIAN
1141 (2 << 0) |
1142#endif
1143 (ib->gpu_addr & 0xFFFFFFFC));
1144 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1145 radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1146
1147 /* flush read cache over gart for this vmid */
1148 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1149 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1150 radeon_ring_write(ring, ib->vm_id);
1151 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1152 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1153 radeon_ring_write(ring, 0xFFFFFFFF);
1154 radeon_ring_write(ring, 0);
1155 radeon_ring_write(ring, 10); /* poll interval */
1156}
1157
0c88a02e
AD		 1158static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1159{
1160 if (enable)
1161 WREG32(CP_ME_CNTL, 0);
1162 else {
38f1cff0 1163 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0c88a02e
AD		 1164 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1165 WREG32(SCRATCH_UMSK, 0);
1166 }
1167}
1168
1169static int cayman_cp_load_microcode(struct radeon_device *rdev)
1170{
1171 const __be32 *fw_data;
1172 int i;
1173
1174 if (!rdev->me_fw || !rdev->pfp_fw)
1175 return -EINVAL;
1176
1177 cayman_cp_enable(rdev, false);
1178
1179 fw_data = (const __be32 *)rdev->pfp_fw->data;
1180 WREG32(CP_PFP_UCODE_ADDR, 0);
1181 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1182 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1183 WREG32(CP_PFP_UCODE_ADDR, 0);
1184
1185 fw_data = (const __be32 *)rdev->me_fw->data;
1186 WREG32(CP_ME_RAM_WADDR, 0);
1187 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1188 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1189
1190 WREG32(CP_PFP_UCODE_ADDR, 0);
1191 WREG32(CP_ME_RAM_WADDR, 0);
1192 WREG32(CP_ME_RAM_RADDR, 0);
1193 return 0;
1194}
1195
1196static int cayman_cp_start(struct radeon_device *rdev)
1197{
e32eb50d 1198 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0c88a02e
AD		 1199 int r, i;
1200
e32eb50d 1201 r = radeon_ring_lock(rdev, ring, 7);
0c88a02e
AD		 1202 if (r) {
1203 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1204 return r;
1205 }
e32eb50d
CK		 1206 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1207 radeon_ring_write(ring, 0x1);
1208 radeon_ring_write(ring, 0x0);
1209 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1210 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1211 radeon_ring_write(ring, 0);
1212 radeon_ring_write(ring, 0);
1213 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 1214
1215 cayman_cp_enable(rdev, true);
1216
e32eb50d 1217 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
0c88a02e
AD		 1218 if (r) {
1219 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1220 return r;
1221 }
1222
1223 /* setup clear context state */
e32eb50d
CK		 1224 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1225 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
0c88a02e
AD		 1226
1227 for (i = 0; i < cayman_default_size; i++)
e32eb50d 1228 radeon_ring_write(ring, cayman_default_state[i]);
0c88a02e 1229
e32eb50d
CK		 1230 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1231 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
0c88a02e
AD		 1232
1233 /* set clear context state */
e32eb50d
CK		 1234 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1235 radeon_ring_write(ring, 0);
0c88a02e
AD		 1236
1237 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1238 radeon_ring_write(ring, 0xc0026f00);
1239 radeon_ring_write(ring, 0x00000000);
1240 radeon_ring_write(ring, 0x00000000);
1241 radeon_ring_write(ring, 0x00000000);
0c88a02e
AD		 1242
1243 /* Clear consts */
e32eb50d
CK		 1244 radeon_ring_write(ring, 0xc0036f00);
1245 radeon_ring_write(ring, 0x00000bc4);
1246 radeon_ring_write(ring, 0xffffffff);
1247 radeon_ring_write(ring, 0xffffffff);
1248 radeon_ring_write(ring, 0xffffffff);
0c88a02e 1249
e32eb50d
CK		 1250 radeon_ring_write(ring, 0xc0026900);
1251 radeon_ring_write(ring, 0x00000316);
1252 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1253 radeon_ring_write(ring, 0x00000010); /* */
9b91d18d 1254
e32eb50d 1255 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 1256
1257 /* XXX init other rings */
1258
1259 return 0;
1260}
1261
755d819e
AD		 1262static void cayman_cp_fini(struct radeon_device *rdev)
1263{
1264 cayman_cp_enable(rdev, false);
e32eb50d 1265 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
755d819e
AD		 1266}
1267
0c88a02e
AD		 1268int cayman_cp_resume(struct radeon_device *rdev)
1269{
e32eb50d 1270 struct radeon_ring *ring;
0c88a02e
AD		 1271 u32 tmp;
1272 u32 rb_bufsz;
1273 int r;
1274
1275 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1276 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1277 SOFT_RESET_PA |
1278 SOFT_RESET_SH |
1279 SOFT_RESET_VGT |
a49a50da 1280 SOFT_RESET_SPI |
0c88a02e
AD		 1281 SOFT_RESET_SX));
1282 RREG32(GRBM_SOFT_RESET);
1283 mdelay(15);
1284 WREG32(GRBM_SOFT_RESET, 0);
1285 RREG32(GRBM_SOFT_RESET);
1286
15d3332f 1287 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1288 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
0c88a02e
AD		 1289
1290 /* Set the write pointer delay */
1291 WREG32(CP_RB_WPTR_DELAY, 0);
1292
1293 WREG32(CP_DEBUG, (1 << 27));
1294
1295 /* ring 0 - compute and gfx */
1296 /* Set ring buffer size */
e32eb50d
CK		 1297 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1298 rb_bufsz = drm_order(ring->ring_size / 8);
0c88a02e
AD		 1299 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1300#ifdef __BIG_ENDIAN
1301 tmp |= BUF_SWAP_32BIT;
1302#endif
1303 WREG32(CP_RB0_CNTL, tmp);
1304
1305 /* Initialize the ring buffer's read and write pointers */
1306 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
e32eb50d
CK		 1307 ring->wptr = 0;
1308 WREG32(CP_RB0_WPTR, ring->wptr);
0c88a02e
AD		 1309
1310 /* set the wb address wether it's enabled or not */
1311 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1312 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1313 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1314
1315 if (rdev->wb.enabled)
1316 WREG32(SCRATCH_UMSK, 0xff);
1317 else {
1318 tmp |= RB_NO_UPDATE;
1319 WREG32(SCRATCH_UMSK, 0);
1320 }
1321
1322 mdelay(1);
1323 WREG32(CP_RB0_CNTL, tmp);
1324
e32eb50d 1325 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
0c88a02e 1326
e32eb50d 1327 ring->rptr = RREG32(CP_RB0_RPTR);
0c88a02e
AD		 1328
1329 /* ring1 - compute only */
1330 /* Set ring buffer size */
e32eb50d
CK		 1331 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1332 rb_bufsz = drm_order(ring->ring_size / 8);
0c88a02e
AD		 1333 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1334#ifdef __BIG_ENDIAN
1335 tmp |= BUF_SWAP_32BIT;
1336#endif
1337 WREG32(CP_RB1_CNTL, tmp);
1338
1339 /* Initialize the ring buffer's read and write pointers */
1340 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
e32eb50d
CK		 1341 ring->wptr = 0;
1342 WREG32(CP_RB1_WPTR, ring->wptr);
0c88a02e
AD		 1343
1344 /* set the wb address wether it's enabled or not */
1345 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1346 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1347
1348 mdelay(1);
1349 WREG32(CP_RB1_CNTL, tmp);
1350
e32eb50d 1351 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
0c88a02e 1352
e32eb50d 1353 ring->rptr = RREG32(CP_RB1_RPTR);
0c88a02e
AD		 1354
1355 /* ring2 - compute only */
1356 /* Set ring buffer size */
e32eb50d
CK		 1357 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1358 rb_bufsz = drm_order(ring->ring_size / 8);
0c88a02e
AD		 1359 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1360#ifdef __BIG_ENDIAN
1361 tmp |= BUF_SWAP_32BIT;
1362#endif
1363 WREG32(CP_RB2_CNTL, tmp);
1364
1365 /* Initialize the ring buffer's read and write pointers */
1366 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
e32eb50d
CK		 1367 ring->wptr = 0;
1368 WREG32(CP_RB2_WPTR, ring->wptr);
0c88a02e
AD		 1369
1370 /* set the wb address wether it's enabled or not */
1371 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1372 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1373
1374 mdelay(1);
1375 WREG32(CP_RB2_CNTL, tmp);
1376
e32eb50d 1377 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
0c88a02e 1378
e32eb50d 1379 ring->rptr = RREG32(CP_RB2_RPTR);
0c88a02e
AD		 1380
1381 /* start the rings */
1382 cayman_cp_start(rdev);
e32eb50d
CK		 1383 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1384 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1385 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e 1386 /* this only test cp0 */
f712812e 1387 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
0c88a02e 1388 if (r) {
e32eb50d
CK		 1389 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1390 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1391 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e
AD		 1392 return r;
1393 }
1394
1395 return 0;
1396}
1397
b9952a8a
AD		 1398static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1399{
1400 struct evergreen_mc_save save;
1401 u32 grbm_reset = 0;
1402
1403 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1404 return 0;
1405
1406 dev_info(rdev->dev, "GPU softreset \n");
1407 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1408 RREG32(GRBM_STATUS));
1409 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1410 RREG32(GRBM_STATUS_SE0));
1411 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1412 RREG32(GRBM_STATUS_SE1));
1413 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1414 RREG32(SRBM_STATUS));
721604a1
JG		 1415 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1416 RREG32(0x14F8));
1417 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1418 RREG32(0x14D8));
1419 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1420 RREG32(0x14FC));
1421 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1422 RREG32(0x14DC));
1423
b9952a8a
AD		 1424 evergreen_mc_stop(rdev, &save);
1425 if (evergreen_mc_wait_for_idle(rdev)) {
1426 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1427 }
1428 /* Disable CP parsing/prefetching */
1429 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1430
1431 /* reset all the gfx blocks */
1432 grbm_reset = (SOFT_RESET_CP |
1433 SOFT_RESET_CB |
1434 SOFT_RESET_DB |
1435 SOFT_RESET_GDS |
1436 SOFT_RESET_PA |
1437 SOFT_RESET_SC |
1438 SOFT_RESET_SPI |
1439 SOFT_RESET_SH |
1440 SOFT_RESET_SX |
1441 SOFT_RESET_TC |
1442 SOFT_RESET_TA |
1443 SOFT_RESET_VGT |
1444 SOFT_RESET_IA);
1445
1446 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1447 WREG32(GRBM_SOFT_RESET, grbm_reset);
1448 (void)RREG32(GRBM_SOFT_RESET);
1449 udelay(50);
1450 WREG32(GRBM_SOFT_RESET, 0);
1451 (void)RREG32(GRBM_SOFT_RESET);
1452 /* Wait a little for things to settle down */
1453 udelay(50);
721604a1 1454
b9952a8a
AD		 1455 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1456 RREG32(GRBM_STATUS));
1457 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1458 RREG32(GRBM_STATUS_SE0));
1459 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1460 RREG32(GRBM_STATUS_SE1));
1461 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1462 RREG32(SRBM_STATUS));
1463 evergreen_mc_resume(rdev, &save);
1464 return 0;
1465}
1466
1467int cayman_asic_reset(struct radeon_device *rdev)
1468{
1469 return cayman_gpu_soft_reset(rdev);
1470}
1471
755d819e
AD		 1472static int cayman_startup(struct radeon_device *rdev)
1473{
e32eb50d 1474 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1475 int r;
1476
b07759bf
IH		 1477 /* enable pcie gen2 link */
1478 evergreen_pcie_gen2_enable(rdev);
1479
c420c745
AD		 1480 if (rdev->flags & RADEON_IS_IGP) {
1481 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1482 r = ni_init_microcode(rdev);
1483 if (r) {
1484 DRM_ERROR("Failed to load firmware!\n");
1485 return r;
1486 }
1487 }
1488 } else {
1489 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1490 r = ni_init_microcode(rdev);
1491 if (r) {
1492 DRM_ERROR("Failed to load firmware!\n");
1493 return r;
1494 }
1495 }
1496
1497 r = ni_mc_load_microcode(rdev);
755d819e 1498 if (r) {
c420c745 1499 DRM_ERROR("Failed to load MC firmware!\n");
755d819e
AD		 1500 return r;
1501 }
1502 }
755d819e 1503
16cdf04d
AD		 1504 r = r600_vram_scratch_init(rdev);
1505 if (r)
1506 return r;
1507
755d819e
AD		 1508 evergreen_mc_program(rdev);
1509 r = cayman_pcie_gart_enable(rdev);
1510 if (r)
1511 return r;
1512 cayman_gpu_init(rdev);
1513
cb92d452 1514 r = evergreen_blit_init(rdev);
755d819e 1515 if (r) {
fb3d9e97 1516 r600_blit_fini(rdev);
27cd7769 1517 rdev->asic->copy.copy = NULL;
755d819e
AD		 1518 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1519 }
755d819e 1520
c420c745
AD		 1521 /* allocate rlc buffers */
1522 if (rdev->flags & RADEON_IS_IGP) {
1523 r = si_rlc_init(rdev);
1524 if (r) {
1525 DRM_ERROR("Failed to init rlc BOs!\n");
1526 return r;
1527 }
1528 }
1529
755d819e
AD		 1530 /* allocate wb buffer */
1531 r = radeon_wb_init(rdev);
1532 if (r)
1533 return r;
1534
30eb77f4
JG		 1535 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1536 if (r) {
1537 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1538 return r;
1539 }
1540
1541 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1542 if (r) {
1543 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1544 return r;
1545 }
1546
1547 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1548 if (r) {
1549 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1550 return r;
1551 }
1552
755d819e
AD		 1553 /* Enable IRQ */
1554 r = r600_irq_init(rdev);
1555 if (r) {
1556 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1557 radeon_irq_kms_fini(rdev);
1558 return r;
1559 }
1560 evergreen_irq_set(rdev);
1561
e32eb50d 1562 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1563 CP_RB0_RPTR, CP_RB0_WPTR,
1564 0, 0xfffff, RADEON_CP_PACKET2);
755d819e
AD		 1565 if (r)
1566 return r;
1567 r = cayman_cp_load_microcode(rdev);
1568 if (r)
1569 return r;
1570 r = cayman_cp_resume(rdev);
1571 if (r)
1572 return r;
1573
b15ba512
JG		 1574 r = radeon_ib_pool_start(rdev);
1575 if (r)
1576 return r;
1577
7bd560e8
CK		 1578 r = radeon_ib_ring_tests(rdev);
1579 if (r)
b15ba512 1580 return r;
b15ba512 1581
721604a1
JG		 1582 r = radeon_vm_manager_start(rdev);
1583 if (r)
1584 return r;
1585
755d819e
AD		 1586 return 0;
1587}
1588
1589int cayman_resume(struct radeon_device *rdev)
1590{
1591 int r;
1592
1593 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1594 * posting will perform necessary task to bring back GPU into good
1595 * shape.
1596 */
1597 /* post card */
1598 atom_asic_init(rdev->mode_info.atom_context);
1599
b15ba512 1600 rdev->accel_working = true;
755d819e
AD		 1601 r = cayman_startup(rdev);
1602 if (r) {
1603 DRM_ERROR("cayman startup failed on resume\n");
6b7746e8 1604 rdev->accel_working = false;
755d819e
AD		 1605 return r;
1606 }
755d819e 1607 return r;
755d819e
AD		 1608}
1609
1610int cayman_suspend(struct radeon_device *rdev)
1611{
755d819e 1612 /* FIXME: we should wait for ring to be empty */
b15ba512 1613 radeon_ib_pool_suspend(rdev);
721604a1 1614 radeon_vm_manager_suspend(rdev);
b15ba512 1615 r600_blit_suspend(rdev);
755d819e 1616 cayman_cp_enable(rdev, false);
e32eb50d 1617 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
755d819e
AD		 1618 evergreen_irq_suspend(rdev);
1619 radeon_wb_disable(rdev);
1620 cayman_pcie_gart_disable(rdev);
755d819e
AD		 1621 return 0;
1622}
1623
1624/* Plan is to move initialization in that function and use
1625 * helper function so that radeon_device_init pretty much
1626 * do nothing more than calling asic specific function. This
1627 * should also allow to remove a bunch of callback function
1628 * like vram_info.
1629 */
1630int cayman_init(struct radeon_device *rdev)
1631{
e32eb50d 1632 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1633 int r;
1634
755d819e
AD		 1635 /* Read BIOS */
1636 if (!radeon_get_bios(rdev)) {
1637 if (ASIC_IS_AVIVO(rdev))
1638 return -EINVAL;
1639 }
1640 /* Must be an ATOMBIOS */
1641 if (!rdev->is_atom_bios) {
1642 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1643 return -EINVAL;
1644 }
1645 r = radeon_atombios_init(rdev);
1646 if (r)
1647 return r;
1648
1649 /* Post card if necessary */
1650 if (!radeon_card_posted(rdev)) {
1651 if (!rdev->bios) {
1652 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1653 return -EINVAL;
1654 }
1655 DRM_INFO("GPU not posted. posting now...\n");
1656 atom_asic_init(rdev->mode_info.atom_context);
1657 }
1658 /* Initialize scratch registers */
1659 r600_scratch_init(rdev);
1660 /* Initialize surface registers */
1661 radeon_surface_init(rdev);
1662 /* Initialize clocks */
1663 radeon_get_clock_info(rdev->ddev);
1664 /* Fence driver */
30eb77f4 1665 r = radeon_fence_driver_init(rdev);
755d819e
AD		 1666 if (r)
1667 return r;
1668 /* initialize memory controller */
1669 r = evergreen_mc_init(rdev);
1670 if (r)
1671 return r;
1672 /* Memory manager */
1673 r = radeon_bo_init(rdev);
1674 if (r)
1675 return r;
1676
1677 r = radeon_irq_kms_init(rdev);
1678 if (r)
1679 return r;
1680
e32eb50d
CK		 1681 ring->ring_obj = NULL;
1682 r600_ring_init(rdev, ring, 1024 * 1024);
755d819e
AD		 1683
1684 rdev->ih.ring_obj = NULL;
1685 r600_ih_ring_init(rdev, 64 * 1024);
1686
1687 r = r600_pcie_gart_init(rdev);
1688 if (r)
1689 return r;
1690
b15ba512 1691 r = radeon_ib_pool_init(rdev);
755d819e 1692 rdev->accel_working = true;
b15ba512
JG		 1693 if (r) {
1694 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1695 rdev->accel_working = false;
1696 }
721604a1
JG		 1697 r = radeon_vm_manager_init(rdev);
1698 if (r) {
1699 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1700 }
b15ba512 1701
755d819e
AD		 1702 r = cayman_startup(rdev);
1703 if (r) {
1704 dev_err(rdev->dev, "disabling GPU acceleration\n");
1705 cayman_cp_fini(rdev);
1706 r600_irq_fini(rdev);
c420c745
AD		 1707 if (rdev->flags & RADEON_IS_IGP)
1708 si_rlc_fini(rdev);
755d819e 1709 radeon_wb_fini(rdev);
b15ba512 1710 r100_ib_fini(rdev);
721604a1 1711 radeon_vm_manager_fini(rdev);
755d819e
AD		 1712 radeon_irq_kms_fini(rdev);
1713 cayman_pcie_gart_fini(rdev);
1714 rdev->accel_working = false;
1715 }
755d819e
AD		 1716
1717 /* Don't start up if the MC ucode is missing.
1718 * The default clocks and voltages before the MC ucode
1719 * is loaded are not suffient for advanced operations.
c420c745
AD		 1720 *
1721 * We can skip this check for TN, because there is no MC
1722 * ucode.
755d819e 1723 */
c420c745 1724 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
755d819e
AD		 1725 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1726 return -EINVAL;
1727 }
1728
1729 return 0;
1730}
1731
1732void cayman_fini(struct radeon_device *rdev)
1733{
fb3d9e97 1734 r600_blit_fini(rdev);
755d819e
AD		 1735 cayman_cp_fini(rdev);
1736 r600_irq_fini(rdev);
c420c745
AD		 1737 if (rdev->flags & RADEON_IS_IGP)
1738 si_rlc_fini(rdev);
755d819e 1739 radeon_wb_fini(rdev);
721604a1 1740 radeon_vm_manager_fini(rdev);
b15ba512 1741 r100_ib_fini(rdev);
755d819e
AD		 1742 radeon_irq_kms_fini(rdev);
1743 cayman_pcie_gart_fini(rdev);
16cdf04d 1744 r600_vram_scratch_fini(rdev);
755d819e
AD		 1745 radeon_gem_fini(rdev);
1746 radeon_fence_driver_fini(rdev);
1747 radeon_bo_fini(rdev);
1748 radeon_atombios_fini(rdev);
1749 kfree(rdev->bios);
1750 rdev->bios = NULL;
1751}
1752
721604a1
JG		 1753/*
1754 * vm
1755 */
1756int cayman_vm_init(struct radeon_device *rdev)
1757{
1758 /* number of VMs */
1759 rdev->vm_manager.nvm = 8;
1760 /* base offset of vram pages */
e71270fd
AD		 1761 if (rdev->flags & RADEON_IS_IGP) {
1762 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1763 tmp <<= 22;
1764 rdev->vm_manager.vram_base_offset = tmp;
1765 } else
1766 rdev->vm_manager.vram_base_offset = 0;
721604a1
JG		 1767 return 0;
1768}
1769
1770void cayman_vm_fini(struct radeon_device *rdev)
1771{
1772}
1773
1774int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1775{
1776 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1777 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1778 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1779 /* flush hdp cache */
1780 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1781 /* bits 0-7 are the VM contexts0-7 */
1782 WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1783 return 0;
1784}
1785
1786void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1787{
1788 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1789 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1790 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1791 /* flush hdp cache */
1792 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1793 /* bits 0-7 are the VM contexts0-7 */
1794 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1795}
1796
1797void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1798{
1799 if (vm->id == -1)
1800 return;
1801
1802 /* flush hdp cache */
1803 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1804 /* bits 0-7 are the VM contexts0-7 */
1805 WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1806}
1807
1808#define R600_PTE_VALID (1 << 0)
1809#define R600_PTE_SYSTEM (1 << 1)
1810#define R600_PTE_SNOOPED (1 << 2)
1811#define R600_PTE_READABLE (1 << 5)
1812#define R600_PTE_WRITEABLE (1 << 6)
1813
1814uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1815 struct radeon_vm *vm,
1816 uint32_t flags)
1817{
1818 uint32_t r600_flags = 0;
1819
1820 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1821 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1822 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1823 if (flags & RADEON_VM_PAGE_SYSTEM) {
1824 r600_flags |= R600_PTE_SYSTEM;
1825 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1826 }
1827 return r600_flags;
1828}
1829
1830void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1831 unsigned pfn, uint64_t addr, uint32_t flags)
1832{
1833 void __iomem *ptr = (void *)vm->pt;
1834
1835 addr = addr & 0xFFFFFFFFFFFFF000ULL;
1836 addr |= flags;
1837 writeq(addr, ptr + (pfn * 8));
1838}
Linux 6.x block layer and io_uring tree(s)