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drm/radeon: use the reset mask to determine if rings are hung
[linux-2.6-block.git] / drivers / gpu / drm / radeon / ni.c
CommitLineData
0af62b01
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
e0cd3608 27#include <linux/module.h>
760285e7 28#include <drm/drmP.h>
0af62b01
AD		 29#include "radeon.h"
30#include "radeon_asic.h"
760285e7 31#include <drm/radeon_drm.h>
0af62b01
AD		 32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
0c88a02e 35#include "cayman_blit_shaders.h"
0af62b01 36
168757ea 37extern bool evergreen_is_display_hung(struct radeon_device *rdev);
187e3593 38extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
b9952a8a
AD		 39extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
40extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
41extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
755d819e
AD		 42extern void evergreen_mc_program(struct radeon_device *rdev);
43extern void evergreen_irq_suspend(struct radeon_device *rdev);
44extern int evergreen_mc_init(struct radeon_device *rdev);
d054ac16 45extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
b07759bf 46extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
c420c745
AD		 47extern void si_rlc_fini(struct radeon_device *rdev);
48extern int si_rlc_init(struct radeon_device *rdev);
b9952a8a 49
0af62b01
AD		 50#define EVERGREEN_PFP_UCODE_SIZE 1120
51#define EVERGREEN_PM4_UCODE_SIZE 1376
52#define EVERGREEN_RLC_UCODE_SIZE 768
53#define BTC_MC_UCODE_SIZE 6024
54
9b8253ce
AD		 55#define CAYMAN_PFP_UCODE_SIZE 2176
56#define CAYMAN_PM4_UCODE_SIZE 2176
57#define CAYMAN_RLC_UCODE_SIZE 1024
58#define CAYMAN_MC_UCODE_SIZE 6037
59
c420c745
AD		 60#define ARUBA_RLC_UCODE_SIZE 1536
61
0af62b01
AD		 62/* Firmware Names */
63MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
64MODULE_FIRMWARE("radeon/BARTS_me.bin");
65MODULE_FIRMWARE("radeon/BARTS_mc.bin");
66MODULE_FIRMWARE("radeon/BTC_rlc.bin");
67MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
68MODULE_FIRMWARE("radeon/TURKS_me.bin");
69MODULE_FIRMWARE("radeon/TURKS_mc.bin");
70MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
71MODULE_FIRMWARE("radeon/CAICOS_me.bin");
72MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
9b8253ce
AD		 73MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
74MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
75MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
76MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
c420c745
AD		 77MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
78MODULE_FIRMWARE("radeon/ARUBA_me.bin");
79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
0af62b01
AD		 80
81#define BTC_IO_MC_REGS_SIZE 29
82
83static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
84 {0x00000077, 0xff010100},
85 {0x00000078, 0x00000000},
86 {0x00000079, 0x00001434},
87 {0x0000007a, 0xcc08ec08},
88 {0x0000007b, 0x00040000},
89 {0x0000007c, 0x000080c0},
90 {0x0000007d, 0x09000000},
91 {0x0000007e, 0x00210404},
92 {0x00000081, 0x08a8e800},
93 {0x00000082, 0x00030444},
94 {0x00000083, 0x00000000},
95 {0x00000085, 0x00000001},
96 {0x00000086, 0x00000002},
97 {0x00000087, 0x48490000},
98 {0x00000088, 0x20244647},
99 {0x00000089, 0x00000005},
100 {0x0000008b, 0x66030000},
101 {0x0000008c, 0x00006603},
102 {0x0000008d, 0x00000100},
103 {0x0000008f, 0x00001c0a},
104 {0x00000090, 0xff000001},
105 {0x00000094, 0x00101101},
106 {0x00000095, 0x00000fff},
107 {0x00000096, 0x00116fff},
108 {0x00000097, 0x60010000},
109 {0x00000098, 0x10010000},
110 {0x00000099, 0x00006000},
111 {0x0000009a, 0x00001000},
112 {0x0000009f, 0x00946a00}
113};
114
115static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
116 {0x00000077, 0xff010100},
117 {0x00000078, 0x00000000},
118 {0x00000079, 0x00001434},
119 {0x0000007a, 0xcc08ec08},
120 {0x0000007b, 0x00040000},
121 {0x0000007c, 0x000080c0},
122 {0x0000007d, 0x09000000},
123 {0x0000007e, 0x00210404},
124 {0x00000081, 0x08a8e800},
125 {0x00000082, 0x00030444},
126 {0x00000083, 0x00000000},
127 {0x00000085, 0x00000001},
128 {0x00000086, 0x00000002},
129 {0x00000087, 0x48490000},
130 {0x00000088, 0x20244647},
131 {0x00000089, 0x00000005},
132 {0x0000008b, 0x66030000},
133 {0x0000008c, 0x00006603},
134 {0x0000008d, 0x00000100},
135 {0x0000008f, 0x00001c0a},
136 {0x00000090, 0xff000001},
137 {0x00000094, 0x00101101},
138 {0x00000095, 0x00000fff},
139 {0x00000096, 0x00116fff},
140 {0x00000097, 0x60010000},
141 {0x00000098, 0x10010000},
142 {0x00000099, 0x00006000},
143 {0x0000009a, 0x00001000},
144 {0x0000009f, 0x00936a00}
145};
146
147static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
148 {0x00000077, 0xff010100},
149 {0x00000078, 0x00000000},
150 {0x00000079, 0x00001434},
151 {0x0000007a, 0xcc08ec08},
152 {0x0000007b, 0x00040000},
153 {0x0000007c, 0x000080c0},
154 {0x0000007d, 0x09000000},
155 {0x0000007e, 0x00210404},
156 {0x00000081, 0x08a8e800},
157 {0x00000082, 0x00030444},
158 {0x00000083, 0x00000000},
159 {0x00000085, 0x00000001},
160 {0x00000086, 0x00000002},
161 {0x00000087, 0x48490000},
162 {0x00000088, 0x20244647},
163 {0x00000089, 0x00000005},
164 {0x0000008b, 0x66030000},
165 {0x0000008c, 0x00006603},
166 {0x0000008d, 0x00000100},
167 {0x0000008f, 0x00001c0a},
168 {0x00000090, 0xff000001},
169 {0x00000094, 0x00101101},
170 {0x00000095, 0x00000fff},
171 {0x00000096, 0x00116fff},
172 {0x00000097, 0x60010000},
173 {0x00000098, 0x10010000},
174 {0x00000099, 0x00006000},
175 {0x0000009a, 0x00001000},
176 {0x0000009f, 0x00916a00}
177};
178
9b8253ce
AD		 179static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
180 {0x00000077, 0xff010100},
181 {0x00000078, 0x00000000},
182 {0x00000079, 0x00001434},
183 {0x0000007a, 0xcc08ec08},
184 {0x0000007b, 0x00040000},
185 {0x0000007c, 0x000080c0},
186 {0x0000007d, 0x09000000},
187 {0x0000007e, 0x00210404},
188 {0x00000081, 0x08a8e800},
189 {0x00000082, 0x00030444},
190 {0x00000083, 0x00000000},
191 {0x00000085, 0x00000001},
192 {0x00000086, 0x00000002},
193 {0x00000087, 0x48490000},
194 {0x00000088, 0x20244647},
195 {0x00000089, 0x00000005},
196 {0x0000008b, 0x66030000},
197 {0x0000008c, 0x00006603},
198 {0x0000008d, 0x00000100},
199 {0x0000008f, 0x00001c0a},
200 {0x00000090, 0xff000001},
201 {0x00000094, 0x00101101},
202 {0x00000095, 0x00000fff},
203 {0x00000096, 0x00116fff},
204 {0x00000097, 0x60010000},
205 {0x00000098, 0x10010000},
206 {0x00000099, 0x00006000},
207 {0x0000009a, 0x00001000},
208 {0x0000009f, 0x00976b00}
209};
210
755d819e 211int ni_mc_load_microcode(struct radeon_device *rdev)
0af62b01
AD		 212{
213 const __be32 *fw_data;
214 u32 mem_type, running, blackout = 0;
215 u32 *io_mc_regs;
9b8253ce 216 int i, ucode_size, regs_size;
0af62b01
AD		 217
218 if (!rdev->mc_fw)
219 return -EINVAL;
220
221 switch (rdev->family) {
222 case CHIP_BARTS:
223 io_mc_regs = (u32 *)&barts_io_mc_regs;
9b8253ce
AD		 224 ucode_size = BTC_MC_UCODE_SIZE;
225 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 226 break;
227 case CHIP_TURKS:
228 io_mc_regs = (u32 *)&turks_io_mc_regs;
9b8253ce
AD		 229 ucode_size = BTC_MC_UCODE_SIZE;
230 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 231 break;
232 case CHIP_CAICOS:
233 default:
234 io_mc_regs = (u32 *)&caicos_io_mc_regs;
9b8253ce
AD		 235 ucode_size = BTC_MC_UCODE_SIZE;
236 regs_size = BTC_IO_MC_REGS_SIZE;
237 break;
238 case CHIP_CAYMAN:
239 io_mc_regs = (u32 *)&cayman_io_mc_regs;
240 ucode_size = CAYMAN_MC_UCODE_SIZE;
241 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 242 break;
243 }
244
245 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
246 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
247
248 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
249 if (running) {
250 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
251 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
252 }
253
254 /* reset the engine and set to writable */
255 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
256 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
257
258 /* load mc io regs */
9b8253ce 259 for (i = 0; i < regs_size; i++) {
0af62b01
AD		 260 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
261 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
262 }
263 /* load the MC ucode */
264 fw_data = (const __be32 *)rdev->mc_fw->data;
9b8253ce 265 for (i = 0; i < ucode_size; i++)
0af62b01
AD		 266 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
267
268 /* put the engine back into the active state */
269 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
270 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
271 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
272
273 /* wait for training to complete */
0e2c978e
AD		 274 for (i = 0; i < rdev->usec_timeout; i++) {
275 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
276 break;
277 udelay(1);
278 }
0af62b01
AD		 279
280 if (running)
281 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
282 }
283
284 return 0;
285}
286
287int ni_init_microcode(struct radeon_device *rdev)
288{
289 struct platform_device *pdev;
290 const char *chip_name;
291 const char *rlc_chip_name;
292 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
293 char fw_name[30];
294 int err;
295
296 DRM_DEBUG("\n");
297
298 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
299 err = IS_ERR(pdev);
300 if (err) {
301 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
302 return -EINVAL;
303 }
304
305 switch (rdev->family) {
306 case CHIP_BARTS:
307 chip_name = "BARTS";
308 rlc_chip_name = "BTC";
9b8253ce
AD		 309 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
310 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
311 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
312 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 313 break;
314 case CHIP_TURKS:
315 chip_name = "TURKS";
316 rlc_chip_name = "BTC";
9b8253ce
AD		 317 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
318 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
319 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
320 mc_req_size = BTC_MC_UCODE_SIZE * 4;
0af62b01
AD		 321 break;
322 case CHIP_CAICOS:
323 chip_name = "CAICOS";
324 rlc_chip_name = "BTC";
9b8253ce
AD		 325 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
326 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
327 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
328 mc_req_size = BTC_MC_UCODE_SIZE * 4;
329 break;
330 case CHIP_CAYMAN:
331 chip_name = "CAYMAN";
332 rlc_chip_name = "CAYMAN";
333 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
334 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
335 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
336 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
0af62b01 337 break;
c420c745
AD		 338 case CHIP_ARUBA:
339 chip_name = "ARUBA";
340 rlc_chip_name = "ARUBA";
341 /* pfp/me same size as CAYMAN */
342 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
343 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
344 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
345 mc_req_size = 0;
346 break;
0af62b01
AD		 347 default: BUG();
348 }
349
0af62b01
AD		 350 DRM_INFO("Loading %s Microcode\n", chip_name);
351
352 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
353 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
354 if (err)
355 goto out;
356 if (rdev->pfp_fw->size != pfp_req_size) {
357 printk(KERN_ERR
358 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
359 rdev->pfp_fw->size, fw_name);
360 err = -EINVAL;
361 goto out;
362 }
363
364 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
365 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
366 if (err)
367 goto out;
368 if (rdev->me_fw->size != me_req_size) {
369 printk(KERN_ERR
370 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
371 rdev->me_fw->size, fw_name);
372 err = -EINVAL;
373 }
374
375 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
376 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
377 if (err)
378 goto out;
379 if (rdev->rlc_fw->size != rlc_req_size) {
380 printk(KERN_ERR
381 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
382 rdev->rlc_fw->size, fw_name);
383 err = -EINVAL;
384 }
385
c420c745
AD		 386 /* no MC ucode on TN */
387 if (!(rdev->flags & RADEON_IS_IGP)) {
388 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
389 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
390 if (err)
391 goto out;
392 if (rdev->mc_fw->size != mc_req_size) {
393 printk(KERN_ERR
394 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
395 rdev->mc_fw->size, fw_name);
396 err = -EINVAL;
397 }
0af62b01
AD		 398 }
399out:
400 platform_device_unregister(pdev);
401
402 if (err) {
403 if (err != -EINVAL)
404 printk(KERN_ERR
405 "ni_cp: Failed to load firmware \"%s\"\n",
406 fw_name);
407 release_firmware(rdev->pfp_fw);
408 rdev->pfp_fw = NULL;
409 release_firmware(rdev->me_fw);
410 rdev->me_fw = NULL;
411 release_firmware(rdev->rlc_fw);
412 rdev->rlc_fw = NULL;
413 release_firmware(rdev->mc_fw);
414 rdev->mc_fw = NULL;
415 }
416 return err;
417}
418
fecf1d07
AD		 419/*
420 * Core functions
421 */
fecf1d07
AD		 422static void cayman_gpu_init(struct radeon_device *rdev)
423{
fecf1d07
AD		 424 u32 gb_addr_config = 0;
425 u32 mc_shared_chmap, mc_arb_ramcfg;
fecf1d07
AD		 426 u32 cgts_tcc_disable;
427 u32 sx_debug_1;
428 u32 smx_dc_ctl0;
fecf1d07
AD		 429 u32 cgts_sm_ctrl_reg;
430 u32 hdp_host_path_cntl;
431 u32 tmp;
416a2bd2 432 u32 disabled_rb_mask;
fecf1d07
AD		 433 int i, j;
434
435 switch (rdev->family) {
436 case CHIP_CAYMAN:
fecf1d07
AD		 437 rdev->config.cayman.max_shader_engines = 2;
438 rdev->config.cayman.max_pipes_per_simd = 4;
439 rdev->config.cayman.max_tile_pipes = 8;
440 rdev->config.cayman.max_simds_per_se = 12;
441 rdev->config.cayman.max_backends_per_se = 4;
442 rdev->config.cayman.max_texture_channel_caches = 8;
443 rdev->config.cayman.max_gprs = 256;
444 rdev->config.cayman.max_threads = 256;
445 rdev->config.cayman.max_gs_threads = 32;
446 rdev->config.cayman.max_stack_entries = 512;
447 rdev->config.cayman.sx_num_of_sets = 8;
448 rdev->config.cayman.sx_max_export_size = 256;
449 rdev->config.cayman.sx_max_export_pos_size = 64;
450 rdev->config.cayman.sx_max_export_smx_size = 192;
451 rdev->config.cayman.max_hw_contexts = 8;
452 rdev->config.cayman.sq_num_cf_insts = 2;
453
454 rdev->config.cayman.sc_prim_fifo_size = 0x100;
455 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
456 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 457 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
fecf1d07 458 break;
7b76e479
AD		 459 case CHIP_ARUBA:
460 default:
461 rdev->config.cayman.max_shader_engines = 1;
462 rdev->config.cayman.max_pipes_per_simd = 4;
463 rdev->config.cayman.max_tile_pipes = 2;
464 if ((rdev->pdev->device == 0x9900) ||
d430f7db
AD		 465 (rdev->pdev->device == 0x9901) ||
466 (rdev->pdev->device == 0x9905) ||
467 (rdev->pdev->device == 0x9906) ||
468 (rdev->pdev->device == 0x9907) ||
469 (rdev->pdev->device == 0x9908) ||
470 (rdev->pdev->device == 0x9909) ||
471 (rdev->pdev->device == 0x9910) ||
472 (rdev->pdev->device == 0x9917)) {
7b76e479
AD		 473 rdev->config.cayman.max_simds_per_se = 6;
474 rdev->config.cayman.max_backends_per_se = 2;
475 } else if ((rdev->pdev->device == 0x9903) ||
d430f7db
AD		 476 (rdev->pdev->device == 0x9904) ||
477 (rdev->pdev->device == 0x990A) ||
478 (rdev->pdev->device == 0x9913) ||
479 (rdev->pdev->device == 0x9918)) {
7b76e479
AD		 480 rdev->config.cayman.max_simds_per_se = 4;
481 rdev->config.cayman.max_backends_per_se = 2;
d430f7db
AD		 482 } else if ((rdev->pdev->device == 0x9919) ||
483 (rdev->pdev->device == 0x9990) ||
484 (rdev->pdev->device == 0x9991) ||
485 (rdev->pdev->device == 0x9994) ||
486 (rdev->pdev->device == 0x99A0)) {
7b76e479
AD		 487 rdev->config.cayman.max_simds_per_se = 3;
488 rdev->config.cayman.max_backends_per_se = 1;
489 } else {
490 rdev->config.cayman.max_simds_per_se = 2;
491 rdev->config.cayman.max_backends_per_se = 1;
492 }
493 rdev->config.cayman.max_texture_channel_caches = 2;
494 rdev->config.cayman.max_gprs = 256;
495 rdev->config.cayman.max_threads = 256;
496 rdev->config.cayman.max_gs_threads = 32;
497 rdev->config.cayman.max_stack_entries = 512;
498 rdev->config.cayman.sx_num_of_sets = 8;
499 rdev->config.cayman.sx_max_export_size = 256;
500 rdev->config.cayman.sx_max_export_pos_size = 64;
501 rdev->config.cayman.sx_max_export_smx_size = 192;
502 rdev->config.cayman.max_hw_contexts = 8;
503 rdev->config.cayman.sq_num_cf_insts = 2;
504
505 rdev->config.cayman.sc_prim_fifo_size = 0x40;
506 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
507 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 508 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
7b76e479 509 break;
fecf1d07
AD		 510 }
511
512 /* Initialize HDP */
513 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
514 WREG32((0x2c14 + j), 0x00000000);
515 WREG32((0x2c18 + j), 0x00000000);
516 WREG32((0x2c1c + j), 0x00000000);
517 WREG32((0x2c20 + j), 0x00000000);
518 WREG32((0x2c24 + j), 0x00000000);
519 }
520
521 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
522
d054ac16
AD		 523 evergreen_fix_pci_max_read_req_size(rdev);
524
fecf1d07
AD		 525 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
526 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
527
fecf1d07
AD		 528 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
529 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
530 if (rdev->config.cayman.mem_row_size_in_kb > 4)
531 rdev->config.cayman.mem_row_size_in_kb = 4;
532 /* XXX use MC settings? */
533 rdev->config.cayman.shader_engine_tile_size = 32;
534 rdev->config.cayman.num_gpus = 1;
535 rdev->config.cayman.multi_gpu_tile_size = 64;
536
fecf1d07
AD		 537 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
538 rdev->config.cayman.num_tile_pipes = (1 << tmp);
539 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
540 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
541 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
542 rdev->config.cayman.num_shader_engines = tmp + 1;
543 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
544 rdev->config.cayman.num_gpus = tmp + 1;
545 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
546 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
547 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
548 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
549
416a2bd2 550
fecf1d07
AD		 551 /* setup tiling info dword. gb_addr_config is not adequate since it does
552 * not have bank info, so create a custom tiling dword.
553 * bits 3:0 num_pipes
554 * bits 7:4 num_banks
555 * bits 11:8 group_size
556 * bits 15:12 row_size
557 */
558 rdev->config.cayman.tile_config = 0;
559 switch (rdev->config.cayman.num_tile_pipes) {
560 case 1:
561 default:
562 rdev->config.cayman.tile_config |= (0 << 0);
563 break;
564 case 2:
565 rdev->config.cayman.tile_config |= (1 << 0);
566 break;
567 case 4:
568 rdev->config.cayman.tile_config |= (2 << 0);
569 break;
570 case 8:
571 rdev->config.cayman.tile_config |= (3 << 0);
572 break;
573 }
7b76e479
AD		 574
575 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
576 if (rdev->flags & RADEON_IS_IGP)
1f73cca7 577 rdev->config.cayman.tile_config |= 1 << 4;
29d65406 578 else {
5b23c904
AD		 579 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
580 case 0: /* four banks */
29d65406 581 rdev->config.cayman.tile_config |= 0 << 4;
5b23c904
AD		 582 break;
583 case 1: /* eight banks */
584 rdev->config.cayman.tile_config |= 1 << 4;
585 break;
586 case 2: /* sixteen banks */
587 default:
588 rdev->config.cayman.tile_config |= 2 << 4;
589 break;
590 }
29d65406 591 }
fecf1d07 592 rdev->config.cayman.tile_config |=
cde5083b 593 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
fecf1d07
AD		 594 rdev->config.cayman.tile_config |=
595 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
596
416a2bd2
AD		 597 tmp = 0;
598 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
599 u32 rb_disable_bitmap;
600
601 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
602 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
603 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
604 tmp <<= 4;
605 tmp |= rb_disable_bitmap;
606 }
607 /* enabled rb are just the one not disabled :) */
608 disabled_rb_mask = tmp;
609
610 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
611 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
612
fecf1d07
AD		 613 WREG32(GB_ADDR_CONFIG, gb_addr_config);
614 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
615 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
f60cbd11
AD		 616 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
617 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
fecf1d07 618
416a2bd2
AD		 619 tmp = gb_addr_config & NUM_PIPES_MASK;
620 tmp = r6xx_remap_render_backend(rdev, tmp,
621 rdev->config.cayman.max_backends_per_se *
622 rdev->config.cayman.max_shader_engines,
623 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
624 WREG32(GB_BACKEND_MAP, tmp);
fecf1d07 625
416a2bd2
AD		 626 cgts_tcc_disable = 0xffff0000;
627 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
628 cgts_tcc_disable &= ~(1 << (16 + i));
fecf1d07
AD		 629 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
630 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
fecf1d07
AD		 631 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
632 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
633
634 /* reprogram the shader complex */
635 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
636 for (i = 0; i < 16; i++)
637 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
638 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
639
640 /* set HW defaults for 3D engine */
641 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
642
643 sx_debug_1 = RREG32(SX_DEBUG_1);
644 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
645 WREG32(SX_DEBUG_1, sx_debug_1);
646
647 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
648 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
285e042d 649 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
fecf1d07
AD		 650 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
651
652 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
653
654 /* need to be explicitly zero-ed */
655 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
656 WREG32(SQ_LSTMP_RING_BASE, 0);
657 WREG32(SQ_HSTMP_RING_BASE, 0);
658 WREG32(SQ_ESTMP_RING_BASE, 0);
659 WREG32(SQ_GSTMP_RING_BASE, 0);
660 WREG32(SQ_VSTMP_RING_BASE, 0);
661 WREG32(SQ_PSTMP_RING_BASE, 0);
662
663 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
664
285e042d
DA		 665 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
666 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
667 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
fecf1d07 668
285e042d
DA		 669 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
670 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
671 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
fecf1d07
AD		 672
673
674 WREG32(VGT_NUM_INSTANCES, 1);
675
676 WREG32(CP_PERFMON_CNTL, 0);
677
285e042d 678 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
fecf1d07
AD		 679 FETCH_FIFO_HIWATER(0x4) |
680 DONE_FIFO_HIWATER(0xe0) |
681 ALU_UPDATE_FIFO_HIWATER(0x8)));
682
683 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
684 WREG32(SQ_CONFIG, (VC_ENABLE |
685 EXPORT_SRC_C |
686 GFX_PRIO(0) |
687 CS1_PRIO(0) |
688 CS2_PRIO(1)));
689 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
690
691 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
692 FORCE_EOV_MAX_REZ_CNT(255)));
693
694 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
695 AUTO_INVLD_EN(ES_AND_GS_AUTO));
696
697 WREG32(VGT_GS_VERTEX_REUSE, 16);
698 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
699
700 WREG32(CB_PERF_CTR0_SEL_0, 0);
701 WREG32(CB_PERF_CTR0_SEL_1, 0);
702 WREG32(CB_PERF_CTR1_SEL_0, 0);
703 WREG32(CB_PERF_CTR1_SEL_1, 0);
704 WREG32(CB_PERF_CTR2_SEL_0, 0);
705 WREG32(CB_PERF_CTR2_SEL_1, 0);
706 WREG32(CB_PERF_CTR3_SEL_0, 0);
707 WREG32(CB_PERF_CTR3_SEL_1, 0);
708
0b65f83f
DA		 709 tmp = RREG32(HDP_MISC_CNTL);
710 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
711 WREG32(HDP_MISC_CNTL, tmp);
712
fecf1d07
AD		 713 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
714 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
715
716 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
717
718 udelay(50);
719}
720
fa8198ea
AD		 721/*
722 * GART
723 */
724void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
725{
726 /* flush hdp cache */
727 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
728
729 /* bits 0-7 are the VM contexts0-7 */
730 WREG32(VM_INVALIDATE_REQUEST, 1);
731}
732
1109ca09 733static int cayman_pcie_gart_enable(struct radeon_device *rdev)
fa8198ea 734{
721604a1 735 int i, r;
fa8198ea 736
c9a1be96 737 if (rdev->gart.robj == NULL) {
fa8198ea
AD		 738 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
739 return -EINVAL;
740 }
741 r = radeon_gart_table_vram_pin(rdev);
742 if (r)
743 return r;
744 radeon_gart_restore(rdev);
745 /* Setup TLB control */
721604a1
JG		 746 WREG32(MC_VM_MX_L1_TLB_CNTL,
747 (0xA << 7) |
748 ENABLE_L1_TLB |
fa8198ea
AD		 749 ENABLE_L1_FRAGMENT_PROCESSING |
750 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
721604a1 751 ENABLE_ADVANCED_DRIVER_MODEL |
fa8198ea
AD		 752 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
753 /* Setup L2 cache */
754 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
755 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
756 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
757 EFFECTIVE_L2_QUEUE_SIZE(7) |
758 CONTEXT1_IDENTITY_ACCESS_MODE(1));
759 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
760 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
761 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
762 /* setup context0 */
763 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
764 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
765 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
766 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
767 (u32)(rdev->dummy_page.addr >> 12));
768 WREG32(VM_CONTEXT0_CNTL2, 0);
769 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
770 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
721604a1
JG		 771
772 WREG32(0x15D4, 0);
773 WREG32(0x15D8, 0);
774 WREG32(0x15DC, 0);
775
776 /* empty context1-7 */
23d4f1f2
AD		 777 /* Assign the pt base to something valid for now; the pts used for
778 * the VMs are determined by the application and setup and assigned
779 * on the fly in the vm part of radeon_gart.c
780 */
721604a1
JG		 781 for (i = 1; i < 8; i++) {
782 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
c1a7ca0d 783 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
721604a1
JG		 784 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
785 rdev->gart.table_addr >> 12);
786 }
787
788 /* enable context1-7 */
789 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
790 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 791 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 792 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
ae133a11
CK		 793 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
794 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
795 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
796 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
797 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
798 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
799 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
800 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
801 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
802 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
803 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
804 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
fa8198ea
AD		 805
806 cayman_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 807 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
808 (unsigned)(rdev->mc.gtt_size >> 20),
809 (unsigned long long)rdev->gart.table_addr);
fa8198ea
AD		 810 rdev->gart.ready = true;
811 return 0;
812}
813
1109ca09 814static void cayman_pcie_gart_disable(struct radeon_device *rdev)
fa8198ea 815{
fa8198ea
AD		 816 /* Disable all tables */
817 WREG32(VM_CONTEXT0_CNTL, 0);
818 WREG32(VM_CONTEXT1_CNTL, 0);
819 /* Setup TLB control */
820 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
821 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
822 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
823 /* Setup L2 cache */
824 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
825 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
826 EFFECTIVE_L2_QUEUE_SIZE(7) |
827 CONTEXT1_IDENTITY_ACCESS_MODE(1));
828 WREG32(VM_L2_CNTL2, 0);
829 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
830 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
c9a1be96 831 radeon_gart_table_vram_unpin(rdev);
fa8198ea
AD		 832}
833
1109ca09 834static void cayman_pcie_gart_fini(struct radeon_device *rdev)
fa8198ea
AD		 835{
836 cayman_pcie_gart_disable(rdev);
837 radeon_gart_table_vram_free(rdev);
838 radeon_gart_fini(rdev);
839}
840
1b37078b
AD		 841void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
842 int ring, u32 cp_int_cntl)
843{
844 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
845
846 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
847 WREG32(CP_INT_CNTL, cp_int_cntl);
848}
849
0c88a02e
AD		 850/*
851 * CP.
852 */
b40e7e16
AD		 853void cayman_fence_ring_emit(struct radeon_device *rdev,
854 struct radeon_fence *fence)
855{
856 struct radeon_ring *ring = &rdev->ring[fence->ring];
857 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
858
721604a1
JG		 859 /* flush read cache over gart for this vmid */
860 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
861 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
862 radeon_ring_write(ring, 0);
b40e7e16
AD		 863 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
864 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
865 radeon_ring_write(ring, 0xFFFFFFFF);
866 radeon_ring_write(ring, 0);
867 radeon_ring_write(ring, 10); /* poll interval */
868 /* EVENT_WRITE_EOP - flush caches, send int */
869 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
870 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
871 radeon_ring_write(ring, addr & 0xffffffff);
872 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
873 radeon_ring_write(ring, fence->seq);
874 radeon_ring_write(ring, 0);
875}
876
721604a1
JG		 877void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
878{
876dc9f3 879 struct radeon_ring *ring = &rdev->ring[ib->ring];
721604a1
JG		 880
881 /* set to DX10/11 mode */
882 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
883 radeon_ring_write(ring, 1);
45df6803
CK		 884
885 if (ring->rptr_save_reg) {
886 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
887 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
888 radeon_ring_write(ring, ((ring->rptr_save_reg -
889 PACKET3_SET_CONFIG_REG_START) >> 2));
890 radeon_ring_write(ring, next_rptr);
891 }
892
721604a1
JG		 893 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
894 radeon_ring_write(ring,
895#ifdef __BIG_ENDIAN
896 (2 << 0) |
897#endif
898 (ib->gpu_addr & 0xFFFFFFFC));
899 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
4bf3dd92
CK		 900 radeon_ring_write(ring, ib->length_dw |
901 (ib->vm ? (ib->vm->id << 24) : 0));
721604a1
JG		 902
903 /* flush read cache over gart for this vmid */
904 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
905 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
4bf3dd92 906 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
721604a1
JG		 907 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
908 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
909 radeon_ring_write(ring, 0xFFFFFFFF);
910 radeon_ring_write(ring, 0);
911 radeon_ring_write(ring, 10); /* poll interval */
912}
913
0c88a02e
AD		 914static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
915{
916 if (enable)
917 WREG32(CP_ME_CNTL, 0);
918 else {
38f1cff0 919 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0c88a02e
AD		 920 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
921 WREG32(SCRATCH_UMSK, 0);
f60cbd11 922 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c88a02e
AD		 923 }
924}
925
926static int cayman_cp_load_microcode(struct radeon_device *rdev)
927{
928 const __be32 *fw_data;
929 int i;
930
931 if (!rdev->me_fw || !rdev->pfp_fw)
932 return -EINVAL;
933
934 cayman_cp_enable(rdev, false);
935
936 fw_data = (const __be32 *)rdev->pfp_fw->data;
937 WREG32(CP_PFP_UCODE_ADDR, 0);
938 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
939 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
940 WREG32(CP_PFP_UCODE_ADDR, 0);
941
942 fw_data = (const __be32 *)rdev->me_fw->data;
943 WREG32(CP_ME_RAM_WADDR, 0);
944 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
945 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
946
947 WREG32(CP_PFP_UCODE_ADDR, 0);
948 WREG32(CP_ME_RAM_WADDR, 0);
949 WREG32(CP_ME_RAM_RADDR, 0);
950 return 0;
951}
952
953static int cayman_cp_start(struct radeon_device *rdev)
954{
e32eb50d 955 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0c88a02e
AD		 956 int r, i;
957
e32eb50d 958 r = radeon_ring_lock(rdev, ring, 7);
0c88a02e
AD		 959 if (r) {
960 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
961 return r;
962 }
e32eb50d
CK		 963 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
964 radeon_ring_write(ring, 0x1);
965 radeon_ring_write(ring, 0x0);
966 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
967 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
968 radeon_ring_write(ring, 0);
969 radeon_ring_write(ring, 0);
970 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 971
972 cayman_cp_enable(rdev, true);
973
e32eb50d 974 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
0c88a02e
AD		 975 if (r) {
976 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
977 return r;
978 }
979
980 /* setup clear context state */
e32eb50d
CK		 981 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
982 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
0c88a02e
AD		 983
984 for (i = 0; i < cayman_default_size; i++)
e32eb50d 985 radeon_ring_write(ring, cayman_default_state[i]);
0c88a02e 986
e32eb50d
CK		 987 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
988 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
0c88a02e
AD		 989
990 /* set clear context state */
e32eb50d
CK		 991 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
992 radeon_ring_write(ring, 0);
0c88a02e
AD		 993
994 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 995 radeon_ring_write(ring, 0xc0026f00);
996 radeon_ring_write(ring, 0x00000000);
997 radeon_ring_write(ring, 0x00000000);
998 radeon_ring_write(ring, 0x00000000);
0c88a02e
AD		 999
1000 /* Clear consts */
e32eb50d
CK		 1001 radeon_ring_write(ring, 0xc0036f00);
1002 radeon_ring_write(ring, 0x00000bc4);
1003 radeon_ring_write(ring, 0xffffffff);
1004 radeon_ring_write(ring, 0xffffffff);
1005 radeon_ring_write(ring, 0xffffffff);
0c88a02e 1006
e32eb50d
CK		 1007 radeon_ring_write(ring, 0xc0026900);
1008 radeon_ring_write(ring, 0x00000316);
1009 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1010 radeon_ring_write(ring, 0x00000010); /* */
9b91d18d 1011
e32eb50d 1012 radeon_ring_unlock_commit(rdev, ring);
0c88a02e
AD		 1013
1014 /* XXX init other rings */
1015
1016 return 0;
1017}
1018
755d819e
AD		 1019static void cayman_cp_fini(struct radeon_device *rdev)
1020{
45df6803 1021 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e 1022 cayman_cp_enable(rdev, false);
45df6803
CK		 1023 radeon_ring_fini(rdev, ring);
1024 radeon_scratch_free(rdev, ring->rptr_save_reg);
755d819e
AD		 1025}
1026
1109ca09 1027static int cayman_cp_resume(struct radeon_device *rdev)
0c88a02e 1028{
b90ca986
CK		 1029 static const int ridx[] = {
1030 RADEON_RING_TYPE_GFX_INDEX,
1031 CAYMAN_RING_TYPE_CP1_INDEX,
1032 CAYMAN_RING_TYPE_CP2_INDEX
1033 };
1034 static const unsigned cp_rb_cntl[] = {
1035 CP_RB0_CNTL,
1036 CP_RB1_CNTL,
1037 CP_RB2_CNTL,
1038 };
1039 static const unsigned cp_rb_rptr_addr[] = {
1040 CP_RB0_RPTR_ADDR,
1041 CP_RB1_RPTR_ADDR,
1042 CP_RB2_RPTR_ADDR
1043 };
1044 static const unsigned cp_rb_rptr_addr_hi[] = {
1045 CP_RB0_RPTR_ADDR_HI,
1046 CP_RB1_RPTR_ADDR_HI,
1047 CP_RB2_RPTR_ADDR_HI
1048 };
1049 static const unsigned cp_rb_base[] = {
1050 CP_RB0_BASE,
1051 CP_RB1_BASE,
1052 CP_RB2_BASE
1053 };
e32eb50d 1054 struct radeon_ring *ring;
b90ca986 1055 int i, r;
0c88a02e
AD		 1056
1057 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1058 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1059 SOFT_RESET_PA |
1060 SOFT_RESET_SH |
1061 SOFT_RESET_VGT |
a49a50da 1062 SOFT_RESET_SPI |
0c88a02e
AD		 1063 SOFT_RESET_SX));
1064 RREG32(GRBM_SOFT_RESET);
1065 mdelay(15);
1066 WREG32(GRBM_SOFT_RESET, 0);
1067 RREG32(GRBM_SOFT_RESET);
1068
15d3332f 1069 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1070 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
0c88a02e
AD		 1071
1072 /* Set the write pointer delay */
1073 WREG32(CP_RB_WPTR_DELAY, 0);
1074
1075 WREG32(CP_DEBUG, (1 << 27));
1076
48fc7f7e 1077 /* set the wb address whether it's enabled or not */
0c88a02e 1078 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
b90ca986 1079 WREG32(SCRATCH_UMSK, 0xff);
0c88a02e 1080
b90ca986
CK		 1081 for (i = 0; i < 3; ++i) {
1082 uint32_t rb_cntl;
1083 uint64_t addr;
0c88a02e 1084
b90ca986
CK		 1085 /* Set ring buffer size */
1086 ring = &rdev->ring[ridx[i]];
1087 rb_cntl = drm_order(ring->ring_size / 8);
1088 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8;
0c88a02e 1089#ifdef __BIG_ENDIAN
b90ca986 1090 rb_cntl |= BUF_SWAP_32BIT;
0c88a02e 1091#endif
b90ca986 1092 WREG32(cp_rb_cntl[i], rb_cntl);
0c88a02e 1093
48fc7f7e 1094 /* set the wb address whether it's enabled or not */
b90ca986
CK		 1095 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1096 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1097 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1098 }
0c88a02e 1099
b90ca986
CK		 1100 /* set the rb base addr, this causes an internal reset of ALL rings */
1101 for (i = 0; i < 3; ++i) {
1102 ring = &rdev->ring[ridx[i]];
1103 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1104 }
0c88a02e 1105
b90ca986
CK		 1106 for (i = 0; i < 3; ++i) {
1107 /* Initialize the ring buffer's read and write pointers */
1108 ring = &rdev->ring[ridx[i]];
1109 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
0c88a02e 1110
b90ca986
CK		 1111 ring->rptr = ring->wptr = 0;
1112 WREG32(ring->rptr_reg, ring->rptr);
1113 WREG32(ring->wptr_reg, ring->wptr);
0c88a02e 1114
b90ca986
CK		 1115 mdelay(1);
1116 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1117 }
0c88a02e
AD		 1118
1119 /* start the rings */
1120 cayman_cp_start(rdev);
e32eb50d
CK		 1121 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1122 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1123 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e 1124 /* this only test cp0 */
f712812e 1125 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
0c88a02e 1126 if (r) {
e32eb50d
CK		 1127 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1128 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1129 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e
AD		 1130 return r;
1131 }
1132
1133 return 0;
1134}
1135
f60cbd11
AD		 1136/*
1137 * DMA
1138 * Starting with R600, the GPU has an asynchronous
1139 * DMA engine. The programming model is very similar
1140 * to the 3D engine (ring buffer, IBs, etc.), but the
1141 * DMA controller has it's own packet format that is
1142 * different form the PM4 format used by the 3D engine.
1143 * It supports copying data, writing embedded data,
1144 * solid fills, and a number of other things. It also
1145 * has support for tiling/detiling of buffers.
1146 * Cayman and newer support two asynchronous DMA engines.
1147 */
1148/**
1149 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
1150 *
1151 * @rdev: radeon_device pointer
1152 * @ib: IB object to schedule
1153 *
1154 * Schedule an IB in the DMA ring (cayman-SI).
1155 */
1156void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
1157 struct radeon_ib *ib)
1158{
1159 struct radeon_ring *ring = &rdev->ring[ib->ring];
1160
1161 if (rdev->wb.enabled) {
1162 u32 next_rptr = ring->wptr + 4;
1163 while ((next_rptr & 7) != 5)
1164 next_rptr++;
1165 next_rptr += 3;
1166 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
1167 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1168 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
1169 radeon_ring_write(ring, next_rptr);
1170 }
1171
1172 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
1173 * Pad as necessary with NOPs.
1174 */
1175 while ((ring->wptr & 7) != 5)
1176 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1177 radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, ib->vm ? ib->vm->id : 0, 0));
1178 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
1179 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
1180
1181}
1182
1183/**
1184 * cayman_dma_stop - stop the async dma engines
1185 *
1186 * @rdev: radeon_device pointer
1187 *
1188 * Stop the async dma engines (cayman-SI).
1189 */
1190void cayman_dma_stop(struct radeon_device *rdev)
1191{
1192 u32 rb_cntl;
1193
1194 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1195
1196 /* dma0 */
1197 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1198 rb_cntl &= ~DMA_RB_ENABLE;
1199 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
1200
1201 /* dma1 */
1202 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1203 rb_cntl &= ~DMA_RB_ENABLE;
1204 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
1205
1206 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
1207 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
1208}
1209
1210/**
1211 * cayman_dma_resume - setup and start the async dma engines
1212 *
1213 * @rdev: radeon_device pointer
1214 *
1215 * Set up the DMA ring buffers and enable them. (cayman-SI).
1216 * Returns 0 for success, error for failure.
1217 */
1218int cayman_dma_resume(struct radeon_device *rdev)
1219{
1220 struct radeon_ring *ring;
b3dfcb20 1221 u32 rb_cntl, dma_cntl, ib_cntl;
f60cbd11
AD		 1222 u32 rb_bufsz;
1223 u32 reg_offset, wb_offset;
1224 int i, r;
1225
1226 /* Reset dma */
1227 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
1228 RREG32(SRBM_SOFT_RESET);
1229 udelay(50);
1230 WREG32(SRBM_SOFT_RESET, 0);
1231
1232 for (i = 0; i < 2; i++) {
1233 if (i == 0) {
1234 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1235 reg_offset = DMA0_REGISTER_OFFSET;
1236 wb_offset = R600_WB_DMA_RPTR_OFFSET;
1237 } else {
1238 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1239 reg_offset = DMA1_REGISTER_OFFSET;
1240 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
1241 }
1242
1243 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
1244 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1245
1246 /* Set ring buffer size in dwords */
1247 rb_bufsz = drm_order(ring->ring_size / 4);
1248 rb_cntl = rb_bufsz << 1;
1249#ifdef __BIG_ENDIAN
1250 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
1251#endif
1252 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);
1253
1254 /* Initialize the ring buffer's read and write pointers */
1255 WREG32(DMA_RB_RPTR + reg_offset, 0);
1256 WREG32(DMA_RB_WPTR + reg_offset, 0);
1257
1258 /* set the wb address whether it's enabled or not */
1259 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,
1260 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
1261 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,
1262 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
1263
1264 if (rdev->wb.enabled)
1265 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
1266
1267 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
1268
1269 /* enable DMA IBs */
b3dfcb20
MD		 1270 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
1271#ifdef __BIG_ENDIAN
1272 ib_cntl |= DMA_IB_SWAP_ENABLE;
1273#endif
1274 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
f60cbd11
AD		 1275
1276 dma_cntl = RREG32(DMA_CNTL + reg_offset);
1277 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
1278 WREG32(DMA_CNTL + reg_offset, dma_cntl);
1279
1280 ring->wptr = 0;
1281 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
1282
1283 ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
1284
1285 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
1286
1287 ring->ready = true;
1288
1289 r = radeon_ring_test(rdev, ring->idx, ring);
1290 if (r) {
1291 ring->ready = false;
1292 return r;
1293 }
1294 }
1295
1296 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1297
1298 return 0;
1299}
1300
1301/**
1302 * cayman_dma_fini - tear down the async dma engines
1303 *
1304 * @rdev: radeon_device pointer
1305 *
1306 * Stop the async dma engines and free the rings (cayman-SI).
1307 */
1308void cayman_dma_fini(struct radeon_device *rdev)
1309{
1310 cayman_dma_stop(rdev);
1311 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
1312 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1313}
1314
168757ea 1315static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
271d6fed 1316{
168757ea 1317 u32 reset_mask = 0;
187e3593 1318 u32 tmp;
271d6fed 1319
168757ea
AD		 1320 /* GRBM_STATUS */
1321 tmp = RREG32(GRBM_STATUS);
1322 if (tmp & (PA_BUSY | SC_BUSY |
1323 SH_BUSY | SX_BUSY |
1324 TA_BUSY | VGT_BUSY |
1325 DB_BUSY | CB_BUSY |
1326 GDS_BUSY | SPI_BUSY |
1327 IA_BUSY | IA_BUSY_NO_DMA))
1328 reset_mask |= RADEON_RESET_GFX;
1329
1330 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1331 CP_BUSY | CP_COHERENCY_BUSY))
1332 reset_mask |= RADEON_RESET_CP;
1333
1334 if (tmp & GRBM_EE_BUSY)
1335 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1336
1337 /* DMA_STATUS_REG 0 */
1338 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1339 if (!(tmp & DMA_IDLE))
1340 reset_mask |= RADEON_RESET_DMA;
1341
1342 /* DMA_STATUS_REG 1 */
1343 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1344 if (!(tmp & DMA_IDLE))
1345 reset_mask |= RADEON_RESET_DMA1;
1346
1347 /* SRBM_STATUS2 */
1348 tmp = RREG32(SRBM_STATUS2);
1349 if (tmp & DMA_BUSY)
1350 reset_mask |= RADEON_RESET_DMA;
1351
1352 if (tmp & DMA1_BUSY)
1353 reset_mask |= RADEON_RESET_DMA1;
1354
1355 /* SRBM_STATUS */
1356 tmp = RREG32(SRBM_STATUS);
1357 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1358 reset_mask |= RADEON_RESET_RLC;
1359
1360 if (tmp & IH_BUSY)
1361 reset_mask |= RADEON_RESET_IH;
1362
1363 if (tmp & SEM_BUSY)
1364 reset_mask |= RADEON_RESET_SEM;
1365
1366 if (tmp & GRBM_RQ_PENDING)
1367 reset_mask |= RADEON_RESET_GRBM;
1368
1369 if (tmp & VMC_BUSY)
1370 reset_mask |= RADEON_RESET_VMC;
19fc42ed 1371
168757ea
AD		 1372 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1373 MCC_BUSY | MCD_BUSY))
1374 reset_mask |= RADEON_RESET_MC;
1375
1376 if (evergreen_is_display_hung(rdev))
1377 reset_mask |= RADEON_RESET_DISPLAY;
1378
1379 /* VM_L2_STATUS */
1380 tmp = RREG32(VM_L2_STATUS);
1381 if (tmp & L2_BUSY)
1382 reset_mask |= RADEON_RESET_VMC;
1383
1384 return reset_mask;
1385}
1386
1387static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1388{
1389 struct evergreen_mc_save save;
1390 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1391 u32 tmp;
19fc42ed 1392
271d6fed 1393 if (reset_mask == 0)
168757ea 1394 return;
271d6fed
AD		 1395
1396 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1397
187e3593 1398 evergreen_print_gpu_status_regs(rdev);
271d6fed
AD		 1399 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1400 RREG32(0x14F8));
1401 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1402 RREG32(0x14D8));
1403 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1404 RREG32(0x14FC));
1405 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1406 RREG32(0x14DC));
1407
187e3593
AD		 1408 /* Disable CP parsing/prefetching */
1409 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1410
1411 if (reset_mask & RADEON_RESET_DMA) {
1412 /* dma0 */
1413 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1414 tmp &= ~DMA_RB_ENABLE;
1415 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
168757ea 1416 }
187e3593 1417
168757ea 1418 if (reset_mask & RADEON_RESET_DMA1) {
187e3593
AD		 1419 /* dma1 */
1420 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1421 tmp &= ~DMA_RB_ENABLE;
1422 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1423 }
1424
90fb8779
AD		 1425 udelay(50);
1426
1427 evergreen_mc_stop(rdev, &save);
1428 if (evergreen_mc_wait_for_idle(rdev)) {
1429 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1430 }
1431
187e3593
AD		 1432 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1433 grbm_soft_reset = SOFT_RESET_CB |
1434 SOFT_RESET_DB |
1435 SOFT_RESET_GDS |
1436 SOFT_RESET_PA |
1437 SOFT_RESET_SC |
1438 SOFT_RESET_SPI |
1439 SOFT_RESET_SH |
1440 SOFT_RESET_SX |
1441 SOFT_RESET_TC |
1442 SOFT_RESET_TA |
1443 SOFT_RESET_VGT |
1444 SOFT_RESET_IA;
1445 }
1446
1447 if (reset_mask & RADEON_RESET_CP) {
1448 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1449
1450 srbm_soft_reset |= SOFT_RESET_GRBM;
1451 }
271d6fed
AD		 1452
1453 if (reset_mask & RADEON_RESET_DMA)
168757ea
AD		 1454 srbm_soft_reset |= SOFT_RESET_DMA;
1455
1456 if (reset_mask & RADEON_RESET_DMA1)
1457 srbm_soft_reset |= SOFT_RESET_DMA1;
1458
1459 if (reset_mask & RADEON_RESET_DISPLAY)
1460 srbm_soft_reset |= SOFT_RESET_DC;
1461
1462 if (reset_mask & RADEON_RESET_RLC)
1463 srbm_soft_reset |= SOFT_RESET_RLC;
1464
1465 if (reset_mask & RADEON_RESET_SEM)
1466 srbm_soft_reset |= SOFT_RESET_SEM;
1467
1468 if (reset_mask & RADEON_RESET_IH)
1469 srbm_soft_reset |= SOFT_RESET_IH;
1470
1471 if (reset_mask & RADEON_RESET_GRBM)
1472 srbm_soft_reset |= SOFT_RESET_GRBM;
1473
1474 if (reset_mask & RADEON_RESET_VMC)
1475 srbm_soft_reset |= SOFT_RESET_VMC;
1476
1477 if (reset_mask & RADEON_RESET_MC)
1478 srbm_soft_reset |= SOFT_RESET_MC;
187e3593
AD		 1479
1480 if (grbm_soft_reset) {
1481 tmp = RREG32(GRBM_SOFT_RESET);
1482 tmp |= grbm_soft_reset;
1483 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1484 WREG32(GRBM_SOFT_RESET, tmp);
1485 tmp = RREG32(GRBM_SOFT_RESET);
1486
1487 udelay(50);
1488
1489 tmp &= ~grbm_soft_reset;
1490 WREG32(GRBM_SOFT_RESET, tmp);
1491 tmp = RREG32(GRBM_SOFT_RESET);
1492 }
1493
1494 if (srbm_soft_reset) {
1495 tmp = RREG32(SRBM_SOFT_RESET);
1496 tmp |= srbm_soft_reset;
1497 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1498 WREG32(SRBM_SOFT_RESET, tmp);
1499 tmp = RREG32(SRBM_SOFT_RESET);
1500
1501 udelay(50);
1502
1503 tmp &= ~srbm_soft_reset;
1504 WREG32(SRBM_SOFT_RESET, tmp);
1505 tmp = RREG32(SRBM_SOFT_RESET);
1506 }
271d6fed
AD		 1507
1508 /* Wait a little for things to settle down */
1509 udelay(50);
1510
b9952a8a 1511 evergreen_mc_resume(rdev, &save);
187e3593
AD		 1512 udelay(50);
1513
187e3593 1514 evergreen_print_gpu_status_regs(rdev);
b9952a8a
AD		 1515}
1516
1517int cayman_asic_reset(struct radeon_device *rdev)
1518{
168757ea
AD		 1519 u32 reset_mask;
1520
1521 reset_mask = cayman_gpu_check_soft_reset(rdev);
1522
1523 if (reset_mask)
1524 r600_set_bios_scratch_engine_hung(rdev, true);
1525
1526 cayman_gpu_soft_reset(rdev, reset_mask);
1527
1528 reset_mask = cayman_gpu_check_soft_reset(rdev);
1529
1530 if (!reset_mask)
1531 r600_set_bios_scratch_engine_hung(rdev, false);
1532
1533 return 0;
b9952a8a
AD		 1534}
1535
123bc183
AD		 1536/**
1537 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1538 *
1539 * @rdev: radeon_device pointer
1540 * @ring: radeon_ring structure holding ring information
1541 *
1542 * Check if the GFX engine is locked up.
1543 * Returns true if the engine appears to be locked up, false if not.
1544 */
1545bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1546{
1547 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1548
1549 if (!(reset_mask & (RADEON_RESET_GFX |
1550 RADEON_RESET_COMPUTE |
1551 RADEON_RESET_CP))) {
1552 radeon_ring_lockup_update(ring);
1553 return false;
1554 }
1555 /* force CP activities */
1556 radeon_ring_force_activity(rdev, ring);
1557 return radeon_ring_test_lockup(rdev, ring);
1558}
1559
f60cbd11
AD		 1560/**
1561 * cayman_dma_is_lockup - Check if the DMA engine is locked up
1562 *
1563 * @rdev: radeon_device pointer
1564 * @ring: radeon_ring structure holding ring information
1565 *
123bc183 1566 * Check if the async DMA engine is locked up.
f60cbd11
AD		 1567 * Returns true if the engine appears to be locked up, false if not.
1568 */
1569bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1570{
123bc183
AD		 1571 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1572 u32 mask;
f60cbd11
AD		 1573
1574 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
123bc183 1575 mask = RADEON_RESET_DMA;
f60cbd11 1576 else
123bc183
AD		 1577 mask = RADEON_RESET_DMA1;
1578
1579 if (!(reset_mask & mask)) {
f60cbd11
AD		 1580 radeon_ring_lockup_update(ring);
1581 return false;
1582 }
1583 /* force ring activities */
1584 radeon_ring_force_activity(rdev, ring);
1585 return radeon_ring_test_lockup(rdev, ring);
1586}
1587
755d819e
AD		 1588static int cayman_startup(struct radeon_device *rdev)
1589{
e32eb50d 1590 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1591 int r;
1592
b07759bf
IH		 1593 /* enable pcie gen2 link */
1594 evergreen_pcie_gen2_enable(rdev);
1595
c420c745
AD		 1596 if (rdev->flags & RADEON_IS_IGP) {
1597 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1598 r = ni_init_microcode(rdev);
1599 if (r) {
1600 DRM_ERROR("Failed to load firmware!\n");
1601 return r;
1602 }
1603 }
1604 } else {
1605 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1606 r = ni_init_microcode(rdev);
1607 if (r) {
1608 DRM_ERROR("Failed to load firmware!\n");
1609 return r;
1610 }
1611 }
1612
1613 r = ni_mc_load_microcode(rdev);
755d819e 1614 if (r) {
c420c745 1615 DRM_ERROR("Failed to load MC firmware!\n");
755d819e
AD		 1616 return r;
1617 }
1618 }
755d819e 1619
16cdf04d
AD		 1620 r = r600_vram_scratch_init(rdev);
1621 if (r)
1622 return r;
1623
755d819e
AD		 1624 evergreen_mc_program(rdev);
1625 r = cayman_pcie_gart_enable(rdev);
1626 if (r)
1627 return r;
1628 cayman_gpu_init(rdev);
1629
cb92d452 1630 r = evergreen_blit_init(rdev);
755d819e 1631 if (r) {
fb3d9e97 1632 r600_blit_fini(rdev);
27cd7769 1633 rdev->asic->copy.copy = NULL;
755d819e
AD		 1634 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1635 }
755d819e 1636
c420c745
AD		 1637 /* allocate rlc buffers */
1638 if (rdev->flags & RADEON_IS_IGP) {
1639 r = si_rlc_init(rdev);
1640 if (r) {
1641 DRM_ERROR("Failed to init rlc BOs!\n");
1642 return r;
1643 }
1644 }
1645
755d819e
AD		 1646 /* allocate wb buffer */
1647 r = radeon_wb_init(rdev);
1648 if (r)
1649 return r;
1650
30eb77f4
JG		 1651 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1652 if (r) {
1653 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1654 return r;
1655 }
1656
1657 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1658 if (r) {
1659 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1660 return r;
1661 }
1662
1663 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1664 if (r) {
1665 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1666 return r;
1667 }
1668
f60cbd11
AD		 1669 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1670 if (r) {
1671 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1672 return r;
1673 }
1674
1675 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
1676 if (r) {
1677 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1678 return r;
1679 }
1680
755d819e
AD		 1681 /* Enable IRQ */
1682 r = r600_irq_init(rdev);
1683 if (r) {
1684 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1685 radeon_irq_kms_fini(rdev);
1686 return r;
1687 }
1688 evergreen_irq_set(rdev);
1689
e32eb50d 1690 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1691 CP_RB0_RPTR, CP_RB0_WPTR,
1692 0, 0xfffff, RADEON_CP_PACKET2);
755d819e
AD		 1693 if (r)
1694 return r;
f60cbd11
AD		 1695
1696 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1697 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1698 DMA_RB_RPTR + DMA0_REGISTER_OFFSET,
1699 DMA_RB_WPTR + DMA0_REGISTER_OFFSET,
1700 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1701 if (r)
1702 return r;
1703
1704 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1705 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
1706 DMA_RB_RPTR + DMA1_REGISTER_OFFSET,
1707 DMA_RB_WPTR + DMA1_REGISTER_OFFSET,
1708 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1709 if (r)
1710 return r;
1711
755d819e
AD		 1712 r = cayman_cp_load_microcode(rdev);
1713 if (r)
1714 return r;
1715 r = cayman_cp_resume(rdev);
1716 if (r)
1717 return r;
1718
f60cbd11
AD		 1719 r = cayman_dma_resume(rdev);
1720 if (r)
1721 return r;
1722
2898c348
CK		 1723 r = radeon_ib_pool_init(rdev);
1724 if (r) {
1725 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 1726 return r;
2898c348 1727 }
b15ba512 1728
c6105f24
CK		 1729 r = radeon_vm_manager_init(rdev);
1730 if (r) {
1731 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
721604a1 1732 return r;
c6105f24 1733 }
721604a1 1734
6b53a050
RM		 1735 r = r600_audio_init(rdev);
1736 if (r)
1737 return r;
1738
755d819e
AD		 1739 return 0;
1740}
1741
1742int cayman_resume(struct radeon_device *rdev)
1743{
1744 int r;
1745
1746 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1747 * posting will perform necessary task to bring back GPU into good
1748 * shape.
1749 */
1750 /* post card */
1751 atom_asic_init(rdev->mode_info.atom_context);
1752
b15ba512 1753 rdev->accel_working = true;
755d819e
AD		 1754 r = cayman_startup(rdev);
1755 if (r) {
1756 DRM_ERROR("cayman startup failed on resume\n");
6b7746e8 1757 rdev->accel_working = false;
755d819e
AD		 1758 return r;
1759 }
755d819e 1760 return r;
755d819e
AD		 1761}
1762
1763int cayman_suspend(struct radeon_device *rdev)
1764{
6b53a050 1765 r600_audio_fini(rdev);
755d819e 1766 cayman_cp_enable(rdev, false);
f60cbd11 1767 cayman_dma_stop(rdev);
755d819e
AD		 1768 evergreen_irq_suspend(rdev);
1769 radeon_wb_disable(rdev);
1770 cayman_pcie_gart_disable(rdev);
755d819e
AD		 1771 return 0;
1772}
1773
1774/* Plan is to move initialization in that function and use
1775 * helper function so that radeon_device_init pretty much
1776 * do nothing more than calling asic specific function. This
1777 * should also allow to remove a bunch of callback function
1778 * like vram_info.
1779 */
1780int cayman_init(struct radeon_device *rdev)
1781{
e32eb50d 1782 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1783 int r;
1784
755d819e
AD		 1785 /* Read BIOS */
1786 if (!radeon_get_bios(rdev)) {
1787 if (ASIC_IS_AVIVO(rdev))
1788 return -EINVAL;
1789 }
1790 /* Must be an ATOMBIOS */
1791 if (!rdev->is_atom_bios) {
1792 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1793 return -EINVAL;
1794 }
1795 r = radeon_atombios_init(rdev);
1796 if (r)
1797 return r;
1798
1799 /* Post card if necessary */
1800 if (!radeon_card_posted(rdev)) {
1801 if (!rdev->bios) {
1802 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1803 return -EINVAL;
1804 }
1805 DRM_INFO("GPU not posted. posting now...\n");
1806 atom_asic_init(rdev->mode_info.atom_context);
1807 }
1808 /* Initialize scratch registers */
1809 r600_scratch_init(rdev);
1810 /* Initialize surface registers */
1811 radeon_surface_init(rdev);
1812 /* Initialize clocks */
1813 radeon_get_clock_info(rdev->ddev);
1814 /* Fence driver */
30eb77f4 1815 r = radeon_fence_driver_init(rdev);
755d819e
AD		 1816 if (r)
1817 return r;
1818 /* initialize memory controller */
1819 r = evergreen_mc_init(rdev);
1820 if (r)
1821 return r;
1822 /* Memory manager */
1823 r = radeon_bo_init(rdev);
1824 if (r)
1825 return r;
1826
1827 r = radeon_irq_kms_init(rdev);
1828 if (r)
1829 return r;
1830
e32eb50d
CK		 1831 ring->ring_obj = NULL;
1832 r600_ring_init(rdev, ring, 1024 * 1024);
755d819e 1833
f60cbd11
AD		 1834 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1835 ring->ring_obj = NULL;
1836 r600_ring_init(rdev, ring, 64 * 1024);
1837
1838 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
1839 ring->ring_obj = NULL;
1840 r600_ring_init(rdev, ring, 64 * 1024);
1841
755d819e
AD		 1842 rdev->ih.ring_obj = NULL;
1843 r600_ih_ring_init(rdev, 64 * 1024);
1844
1845 r = r600_pcie_gart_init(rdev);
1846 if (r)
1847 return r;
1848
1849 rdev->accel_working = true;
1850 r = cayman_startup(rdev);
1851 if (r) {
1852 dev_err(rdev->dev, "disabling GPU acceleration\n");
1853 cayman_cp_fini(rdev);
f60cbd11 1854 cayman_dma_fini(rdev);
755d819e 1855 r600_irq_fini(rdev);
c420c745
AD		 1856 if (rdev->flags & RADEON_IS_IGP)
1857 si_rlc_fini(rdev);
755d819e 1858 radeon_wb_fini(rdev);
2898c348 1859 radeon_ib_pool_fini(rdev);
721604a1 1860 radeon_vm_manager_fini(rdev);
755d819e
AD		 1861 radeon_irq_kms_fini(rdev);
1862 cayman_pcie_gart_fini(rdev);
1863 rdev->accel_working = false;
1864 }
755d819e
AD		 1865
1866 /* Don't start up if the MC ucode is missing.
1867 * The default clocks and voltages before the MC ucode
1868 * is loaded are not suffient for advanced operations.
c420c745
AD		 1869 *
1870 * We can skip this check for TN, because there is no MC
1871 * ucode.
755d819e 1872 */
c420c745 1873 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
755d819e
AD		 1874 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1875 return -EINVAL;
1876 }
1877
1878 return 0;
1879}
1880
1881void cayman_fini(struct radeon_device *rdev)
1882{
fb3d9e97 1883 r600_blit_fini(rdev);
755d819e 1884 cayman_cp_fini(rdev);
f60cbd11 1885 cayman_dma_fini(rdev);
755d819e 1886 r600_irq_fini(rdev);
c420c745
AD		 1887 if (rdev->flags & RADEON_IS_IGP)
1888 si_rlc_fini(rdev);
755d819e 1889 radeon_wb_fini(rdev);
721604a1 1890 radeon_vm_manager_fini(rdev);
2898c348 1891 radeon_ib_pool_fini(rdev);
755d819e
AD		 1892 radeon_irq_kms_fini(rdev);
1893 cayman_pcie_gart_fini(rdev);
16cdf04d 1894 r600_vram_scratch_fini(rdev);
755d819e
AD		 1895 radeon_gem_fini(rdev);
1896 radeon_fence_driver_fini(rdev);
1897 radeon_bo_fini(rdev);
1898 radeon_atombios_fini(rdev);
1899 kfree(rdev->bios);
1900 rdev->bios = NULL;
1901}
1902
721604a1
JG		 1903/*
1904 * vm
1905 */
1906int cayman_vm_init(struct radeon_device *rdev)
1907{
1908 /* number of VMs */
1909 rdev->vm_manager.nvm = 8;
1910 /* base offset of vram pages */
e71270fd
AD		 1911 if (rdev->flags & RADEON_IS_IGP) {
1912 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1913 tmp <<= 22;
1914 rdev->vm_manager.vram_base_offset = tmp;
1915 } else
1916 rdev->vm_manager.vram_base_offset = 0;
721604a1
JG		 1917 return 0;
1918}
1919
1920void cayman_vm_fini(struct radeon_device *rdev)
1921{
1922}
1923
dce34bfd 1924#define R600_ENTRY_VALID (1 << 0)
721604a1
JG		 1925#define R600_PTE_SYSTEM (1 << 1)
1926#define R600_PTE_SNOOPED (1 << 2)
1927#define R600_PTE_READABLE (1 << 5)
1928#define R600_PTE_WRITEABLE (1 << 6)
1929
089a786e 1930uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
721604a1
JG		 1931{
1932 uint32_t r600_flags = 0;
dce34bfd 1933 r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_ENTRY_VALID : 0;
721604a1
JG		 1934 r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1935 r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1936 if (flags & RADEON_VM_PAGE_SYSTEM) {
1937 r600_flags |= R600_PTE_SYSTEM;
1938 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1939 }
1940 return r600_flags;
1941}
1942
7a083293
AD		 1943/**
1944 * cayman_vm_set_page - update the page tables using the CP
1945 *
1946 * @rdev: radeon_device pointer
dce34bfd
CK		 1947 * @pe: addr of the page entry
1948 * @addr: dst addr to write into pe
1949 * @count: number of page entries to update
1950 * @incr: increase next addr by incr bytes
1951 * @flags: access flags
7a083293
AD		 1952 *
1953 * Update the page tables using the CP (cayman-si).
1954 */
dce34bfd
CK		 1955void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1956 uint64_t addr, unsigned count,
1957 uint32_t incr, uint32_t flags)
721604a1 1958{
2a6f1abb 1959 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
dce34bfd 1960 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
3b6b59b6
AD		 1961 uint64_t value;
1962 unsigned ndw;
1963
1964 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
1965 while (count) {
1966 ndw = 1 + count * 2;
1967 if (ndw > 0x3FFF)
1968 ndw = 0x3FFF;
1969
1970 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw));
1971 radeon_ring_write(ring, pe);
1972 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1973 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1974 if (flags & RADEON_VM_PAGE_SYSTEM) {
1975 value = radeon_vm_map_gart(rdev, addr);
1976 value &= 0xFFFFFFFFFFFFF000ULL;
1977 } else if (flags & RADEON_VM_PAGE_VALID) {
1978 value = addr;
1979 } else {
1980 value = 0;
1981 }
f9fdffa5 1982 addr += incr;
3b6b59b6
AD		 1983 value |= r600_flags;
1984 radeon_ring_write(ring, value);
1985 radeon_ring_write(ring, upper_32_bits(value));
1986 }
1987 }
1988 } else {
1989 while (count) {
1990 ndw = count * 2;
1991 if (ndw > 0xFFFFE)
1992 ndw = 0xFFFFE;
1993
1994 /* for non-physically contiguous pages (system) */
1995 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw));
1996 radeon_ring_write(ring, pe);
1997 radeon_ring_write(ring, upper_32_bits(pe) & 0xff);
1998 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1999 if (flags & RADEON_VM_PAGE_SYSTEM) {
2000 value = radeon_vm_map_gart(rdev, addr);
2001 value &= 0xFFFFFFFFFFFFF000ULL;
2002 } else if (flags & RADEON_VM_PAGE_VALID) {
2003 value = addr;
2004 } else {
2005 value = 0;
2006 }
f9fdffa5 2007 addr += incr;
3b6b59b6
AD		 2008 value |= r600_flags;
2009 radeon_ring_write(ring, value);
2010 radeon_ring_write(ring, upper_32_bits(value));
f9fdffa5 2011 }
f9fdffa5 2012 }
2a6f1abb 2013 }
721604a1 2014}
9b40e5d8 2015
7a083293
AD		 2016/**
2017 * cayman_vm_flush - vm flush using the CP
2018 *
2019 * @rdev: radeon_device pointer
2020 *
2021 * Update the page table base and flush the VM TLB
2022 * using the CP (cayman-si).
2023 */
498522b4 2024void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
721604a1 2025{
498522b4 2026 struct radeon_ring *ring = &rdev->ring[ridx];
9b40e5d8 2027
ee60e29f 2028 if (vm == NULL)
9b40e5d8
CK		 2029 return;
2030
ee60e29f 2031 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
fa87e62d 2032 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
ee60e29f 2033
9b40e5d8
CK		 2034 /* flush hdp cache */
2035 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2036 radeon_ring_write(ring, 0x1);
2037
2038 /* bits 0-7 are the VM contexts0-7 */
2039 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
498522b4 2040 radeon_ring_write(ring, 1 << vm->id);
58f8cf56
CK		 2041
2042 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2043 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2044 radeon_ring_write(ring, 0x0);
721604a1 2045}
f60cbd11
AD		 2046
2047void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2048{
2049 struct radeon_ring *ring = &rdev->ring[ridx];
2050
2051 if (vm == NULL)
2052 return;
2053
2054 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2055 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2));
2056 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2057
2058 /* flush hdp cache */
2059 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2060 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
2061 radeon_ring_write(ring, 1);
2062
2063 /* bits 0-7 are the VM contexts0-7 */
2064 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
2065 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));
2066 radeon_ring_write(ring, 1 << vm->id);
2067}
2068
Linux 6.x block layer and io_uring tree(s)