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Merge tag 'pm+acpi-4.1-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / ni.c
CommitLineData
0af62b01
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
0af62b01 25#include <linux/slab.h>
e0cd3608 26#include <linux/module.h>
760285e7 27#include <drm/drmP.h>
0af62b01
AD		 28#include "radeon.h"
29#include "radeon_asic.h"
bfc1f97d 30#include "radeon_audio.h"
760285e7 31#include <drm/radeon_drm.h>
0af62b01
AD		 32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
0c88a02e 35#include "cayman_blit_shaders.h"
138e4e16 36#include "radeon_ucode.h"
2948f5e6
AD		 37#include "clearstate_cayman.h"
38
1fd11777 39static const u32 tn_rlc_save_restore_register_list[] =
2948f5e6
AD		 40{
41 0x98fc,
42 0x98f0,
43 0x9834,
44 0x9838,
45 0x9870,
46 0x9874,
47 0x8a14,
48 0x8b24,
49 0x8bcc,
50 0x8b10,
51 0x8c30,
52 0x8d00,
53 0x8d04,
54 0x8c00,
55 0x8c04,
56 0x8c10,
57 0x8c14,
58 0x8d8c,
59 0x8cf0,
60 0x8e38,
61 0x9508,
62 0x9688,
63 0x9608,
64 0x960c,
65 0x9610,
66 0x9614,
67 0x88c4,
68 0x8978,
69 0x88d4,
70 0x900c,
71 0x9100,
72 0x913c,
73 0x90e8,
74 0x9354,
75 0xa008,
76 0x98f8,
77 0x9148,
78 0x914c,
79 0x3f94,
80 0x98f4,
81 0x9b7c,
82 0x3f8c,
83 0x8950,
84 0x8954,
85 0x8a18,
86 0x8b28,
87 0x9144,
88 0x3f90,
89 0x915c,
90 0x9160,
91 0x9178,
92 0x917c,
93 0x9180,
94 0x918c,
95 0x9190,
96 0x9194,
97 0x9198,
98 0x919c,
99 0x91a8,
100 0x91ac,
101 0x91b0,
102 0x91b4,
103 0x91b8,
104 0x91c4,
105 0x91c8,
106 0x91cc,
107 0x91d0,
108 0x91d4,
109 0x91e0,
110 0x91e4,
111 0x91ec,
112 0x91f0,
113 0x91f4,
114 0x9200,
115 0x9204,
116 0x929c,
117 0x8030,
118 0x9150,
119 0x9a60,
120 0x920c,
121 0x9210,
122 0x9228,
123 0x922c,
124 0x9244,
125 0x9248,
126 0x91e8,
127 0x9294,
128 0x9208,
129 0x9224,
130 0x9240,
131 0x9220,
132 0x923c,
133 0x9258,
134 0x9744,
135 0xa200,
136 0xa204,
137 0xa208,
138 0xa20c,
139 0x8d58,
140 0x9030,
141 0x9034,
142 0x9038,
143 0x903c,
144 0x9040,
145 0x9654,
146 0x897c,
147 0xa210,
148 0xa214,
149 0x9868,
150 0xa02c,
151 0x9664,
152 0x9698,
153 0x949c,
154 0x8e10,
155 0x8e18,
156 0x8c50,
157 0x8c58,
158 0x8c60,
159 0x8c68,
160 0x89b4,
161 0x9830,
162 0x802c,
163};
0af62b01 164
168757ea 165extern bool evergreen_is_display_hung(struct radeon_device *rdev);
187e3593 166extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
b9952a8a
AD		 167extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
168extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
169extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
755d819e
AD		 170extern void evergreen_mc_program(struct radeon_device *rdev);
171extern void evergreen_irq_suspend(struct radeon_device *rdev);
172extern int evergreen_mc_init(struct radeon_device *rdev);
d054ac16 173extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
b07759bf 174extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
f52382d7 175extern void evergreen_program_aspm(struct radeon_device *rdev);
2948f5e6
AD		 176extern void sumo_rlc_fini(struct radeon_device *rdev);
177extern int sumo_rlc_init(struct radeon_device *rdev);
b5470b03 178extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
b9952a8a 179
0af62b01
AD		 180/* Firmware Names */
181MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
182MODULE_FIRMWARE("radeon/BARTS_me.bin");
183MODULE_FIRMWARE("radeon/BARTS_mc.bin");
6596afd4 184MODULE_FIRMWARE("radeon/BARTS_smc.bin");
0af62b01
AD		 185MODULE_FIRMWARE("radeon/BTC_rlc.bin");
186MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
187MODULE_FIRMWARE("radeon/TURKS_me.bin");
188MODULE_FIRMWARE("radeon/TURKS_mc.bin");
6596afd4 189MODULE_FIRMWARE("radeon/TURKS_smc.bin");
0af62b01
AD		 190MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
191MODULE_FIRMWARE("radeon/CAICOS_me.bin");
192MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
6596afd4 193MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
9b8253ce
AD		 194MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
195MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
196MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
197MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
69e0b57a 198MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
c420c745
AD		 199MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
200MODULE_FIRMWARE("radeon/ARUBA_me.bin");
201MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
0af62b01 202
a2c96a21
AD		 203
204static const u32 cayman_golden_registers2[] =
205{
206 0x3e5c, 0xffffffff, 0x00000000,
207 0x3e48, 0xffffffff, 0x00000000,
208 0x3e4c, 0xffffffff, 0x00000000,
209 0x3e64, 0xffffffff, 0x00000000,
210 0x3e50, 0xffffffff, 0x00000000,
211 0x3e60, 0xffffffff, 0x00000000
212};
213
214static const u32 cayman_golden_registers[] =
215{
216 0x5eb4, 0xffffffff, 0x00000002,
217 0x5e78, 0x8f311ff1, 0x001000f0,
218 0x3f90, 0xffff0000, 0xff000000,
219 0x9148, 0xffff0000, 0xff000000,
220 0x3f94, 0xffff0000, 0xff000000,
221 0x914c, 0xffff0000, 0xff000000,
222 0xc78, 0x00000080, 0x00000080,
223 0xbd4, 0x70073777, 0x00011003,
224 0xd02c, 0xbfffff1f, 0x08421000,
225 0xd0b8, 0x73773777, 0x02011003,
226 0x5bc0, 0x00200000, 0x50100000,
227 0x98f8, 0x33773777, 0x02011003,
228 0x98fc, 0xffffffff, 0x76541032,
229 0x7030, 0x31000311, 0x00000011,
230 0x2f48, 0x33773777, 0x42010001,
231 0x6b28, 0x00000010, 0x00000012,
232 0x7728, 0x00000010, 0x00000012,
233 0x10328, 0x00000010, 0x00000012,
234 0x10f28, 0x00000010, 0x00000012,
235 0x11b28, 0x00000010, 0x00000012,
236 0x12728, 0x00000010, 0x00000012,
237 0x240c, 0x000007ff, 0x00000000,
238 0x8a14, 0xf000001f, 0x00000007,
239 0x8b24, 0x3fff3fff, 0x00ff0fff,
240 0x8b10, 0x0000ff0f, 0x00000000,
241 0x28a4c, 0x07ffffff, 0x06000000,
242 0x10c, 0x00000001, 0x00010003,
243 0xa02c, 0xffffffff, 0x0000009b,
244 0x913c, 0x0000010f, 0x01000100,
245 0x8c04, 0xf8ff00ff, 0x40600060,
246 0x28350, 0x00000f01, 0x00000000,
247 0x9508, 0x3700001f, 0x00000002,
248 0x960c, 0xffffffff, 0x54763210,
249 0x88c4, 0x001f3ae3, 0x00000082,
250 0x88d0, 0xffffffff, 0x0f40df40,
251 0x88d4, 0x0000001f, 0x00000010,
252 0x8974, 0xffffffff, 0x00000000
253};
254
255static const u32 dvst_golden_registers2[] =
256{
257 0x8f8, 0xffffffff, 0,
258 0x8fc, 0x00380000, 0,
259 0x8f8, 0xffffffff, 1,
260 0x8fc, 0x0e000000, 0
261};
262
263static const u32 dvst_golden_registers[] =
264{
265 0x690, 0x3fff3fff, 0x20c00033,
266 0x918c, 0x0fff0fff, 0x00010006,
267 0x91a8, 0x0fff0fff, 0x00010006,
268 0x9150, 0xffffdfff, 0x6e944040,
269 0x917c, 0x0fff0fff, 0x00030002,
270 0x9198, 0x0fff0fff, 0x00030002,
271 0x915c, 0x0fff0fff, 0x00010000,
272 0x3f90, 0xffff0001, 0xff000000,
273 0x9178, 0x0fff0fff, 0x00070000,
274 0x9194, 0x0fff0fff, 0x00070000,
275 0x9148, 0xffff0001, 0xff000000,
276 0x9190, 0x0fff0fff, 0x00090008,
277 0x91ac, 0x0fff0fff, 0x00090008,
278 0x3f94, 0xffff0000, 0xff000000,
279 0x914c, 0xffff0000, 0xff000000,
280 0x929c, 0x00000fff, 0x00000001,
281 0x55e4, 0xff607fff, 0xfc000100,
282 0x8a18, 0xff000fff, 0x00000100,
283 0x8b28, 0xff000fff, 0x00000100,
284 0x9144, 0xfffc0fff, 0x00000100,
285 0x6ed8, 0x00010101, 0x00010000,
286 0x9830, 0xffffffff, 0x00000000,
287 0x9834, 0xf00fffff, 0x00000400,
288 0x9838, 0xfffffffe, 0x00000000,
289 0xd0c0, 0xff000fff, 0x00000100,
290 0xd02c, 0xbfffff1f, 0x08421000,
291 0xd0b8, 0x73773777, 0x12010001,
292 0x5bb0, 0x000000f0, 0x00000070,
293 0x98f8, 0x73773777, 0x12010001,
294 0x98fc, 0xffffffff, 0x00000010,
295 0x9b7c, 0x00ff0000, 0x00fc0000,
296 0x8030, 0x00001f0f, 0x0000100a,
297 0x2f48, 0x73773777, 0x12010001,
298 0x2408, 0x00030000, 0x000c007f,
299 0x8a14, 0xf000003f, 0x00000007,
300 0x8b24, 0x3fff3fff, 0x00ff0fff,
301 0x8b10, 0x0000ff0f, 0x00000000,
302 0x28a4c, 0x07ffffff, 0x06000000,
303 0x4d8, 0x00000fff, 0x00000100,
304 0xa008, 0xffffffff, 0x00010000,
305 0x913c, 0xffff03ff, 0x01000100,
306 0x8c00, 0x000000ff, 0x00000003,
307 0x8c04, 0xf8ff00ff, 0x40600060,
308 0x8cf0, 0x1fff1fff, 0x08e00410,
309 0x28350, 0x00000f01, 0x00000000,
310 0x9508, 0xf700071f, 0x00000002,
311 0x960c, 0xffffffff, 0x54763210,
312 0x20ef8, 0x01ff01ff, 0x00000002,
313 0x20e98, 0xfffffbff, 0x00200000,
314 0x2015c, 0xffffffff, 0x00000f40,
315 0x88c4, 0x001f3ae3, 0x00000082,
316 0x8978, 0x3fffffff, 0x04050140,
317 0x88d4, 0x0000001f, 0x00000010,
318 0x8974, 0xffffffff, 0x00000000
319};
320
321static const u32 scrapper_golden_registers[] =
322{
323 0x690, 0x3fff3fff, 0x20c00033,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x918c, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x91a8, 0x0fff0fff, 0x00010006,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x9150, 0xffffdfff, 0x6e944040,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x917c, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x9198, 0x0fff0fff, 0x00030002,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x915c, 0x0fff0fff, 0x00010000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x3f90, 0xffff0001, 0xff000000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9178, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9194, 0x0fff0fff, 0x00070000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9148, 0xffff0001, 0xff000000,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x9190, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x91ac, 0x0fff0fff, 0x00090008,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x3f94, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x914c, 0xffff0000, 0xff000000,
352 0x929c, 0x00000fff, 0x00000001,
353 0x929c, 0x00000fff, 0x00000001,
354 0x55e4, 0xff607fff, 0xfc000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8a18, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x8b28, 0xff000fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x9144, 0xfffc0fff, 0x00000100,
361 0x6ed8, 0x00010101, 0x00010000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9830, 0xffffffff, 0x00000000,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9834, 0xf00fffff, 0x00000400,
366 0x9838, 0xfffffffe, 0x00000000,
367 0x9838, 0xfffffffe, 0x00000000,
368 0xd0c0, 0xff000fff, 0x00000100,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd02c, 0xbfffff1f, 0x08421000,
371 0xd0b8, 0x73773777, 0x12010001,
372 0xd0b8, 0x73773777, 0x12010001,
373 0x5bb0, 0x000000f0, 0x00000070,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98f8, 0x73773777, 0x12010001,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x98fc, 0xffffffff, 0x00000010,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x9b7c, 0x00ff0000, 0x00fc0000,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x8030, 0x00001f0f, 0x0000100a,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2f48, 0x73773777, 0x12010001,
384 0x2408, 0x00030000, 0x000c007f,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8a14, 0xf000003f, 0x00000007,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b24, 0x3fff3fff, 0x00ff0fff,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x8b10, 0x0000ff0f, 0x00000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x28a4c, 0x07ffffff, 0x06000000,
393 0x4d8, 0x00000fff, 0x00000100,
394 0x4d8, 0x00000fff, 0x00000100,
395 0xa008, 0xffffffff, 0x00010000,
396 0xa008, 0xffffffff, 0x00010000,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x913c, 0xffff03ff, 0x01000100,
399 0x90e8, 0x001fffff, 0x010400c0,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c00, 0x000000ff, 0x00000003,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c04, 0xf8ff00ff, 0x40600060,
404 0x8c30, 0x0000000f, 0x00040005,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x8cf0, 0x1fff1fff, 0x08e00410,
407 0x900c, 0x00ffffff, 0x0017071f,
408 0x28350, 0x00000f01, 0x00000000,
409 0x28350, 0x00000f01, 0x00000000,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9508, 0xf700071f, 0x00000002,
412 0x9688, 0x00300000, 0x0017000f,
413 0x960c, 0xffffffff, 0x54763210,
414 0x960c, 0xffffffff, 0x54763210,
415 0x20ef8, 0x01ff01ff, 0x00000002,
416 0x20e98, 0xfffffbff, 0x00200000,
417 0x2015c, 0xffffffff, 0x00000f40,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x88c4, 0x001f3ae3, 0x00000082,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x8978, 0x3fffffff, 0x04050140,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x88d4, 0x0000001f, 0x00000010,
424 0x8974, 0xffffffff, 0x00000000,
425 0x8974, 0xffffffff, 0x00000000
426};
427
428static void ni_init_golden_registers(struct radeon_device *rdev)
429{
430 switch (rdev->family) {
431 case CHIP_CAYMAN:
432 radeon_program_register_sequence(rdev,
433 cayman_golden_registers,
434 (const u32)ARRAY_SIZE(cayman_golden_registers));
435 radeon_program_register_sequence(rdev,
436 cayman_golden_registers2,
437 (const u32)ARRAY_SIZE(cayman_golden_registers2));
438 break;
439 case CHIP_ARUBA:
440 if ((rdev->pdev->device == 0x9900) ||
441 (rdev->pdev->device == 0x9901) ||
442 (rdev->pdev->device == 0x9903) ||
443 (rdev->pdev->device == 0x9904) ||
444 (rdev->pdev->device == 0x9905) ||
445 (rdev->pdev->device == 0x9906) ||
446 (rdev->pdev->device == 0x9907) ||
447 (rdev->pdev->device == 0x9908) ||
448 (rdev->pdev->device == 0x9909) ||
449 (rdev->pdev->device == 0x990A) ||
450 (rdev->pdev->device == 0x990B) ||
451 (rdev->pdev->device == 0x990C) ||
452 (rdev->pdev->device == 0x990D) ||
453 (rdev->pdev->device == 0x990E) ||
454 (rdev->pdev->device == 0x990F) ||
455 (rdev->pdev->device == 0x9910) ||
456 (rdev->pdev->device == 0x9913) ||
457 (rdev->pdev->device == 0x9917) ||
458 (rdev->pdev->device == 0x9918)) {
459 radeon_program_register_sequence(rdev,
460 dvst_golden_registers,
461 (const u32)ARRAY_SIZE(dvst_golden_registers));
462 radeon_program_register_sequence(rdev,
463 dvst_golden_registers2,
464 (const u32)ARRAY_SIZE(dvst_golden_registers2));
465 } else {
466 radeon_program_register_sequence(rdev,
467 scrapper_golden_registers,
468 (const u32)ARRAY_SIZE(scrapper_golden_registers));
469 radeon_program_register_sequence(rdev,
470 dvst_golden_registers2,
471 (const u32)ARRAY_SIZE(dvst_golden_registers2));
472 }
473 break;
474 default:
475 break;
476 }
477}
478
0af62b01
AD		 479#define BTC_IO_MC_REGS_SIZE 29
480
481static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
482 {0x00000077, 0xff010100},
483 {0x00000078, 0x00000000},
484 {0x00000079, 0x00001434},
485 {0x0000007a, 0xcc08ec08},
486 {0x0000007b, 0x00040000},
487 {0x0000007c, 0x000080c0},
488 {0x0000007d, 0x09000000},
489 {0x0000007e, 0x00210404},
490 {0x00000081, 0x08a8e800},
491 {0x00000082, 0x00030444},
492 {0x00000083, 0x00000000},
493 {0x00000085, 0x00000001},
494 {0x00000086, 0x00000002},
495 {0x00000087, 0x48490000},
496 {0x00000088, 0x20244647},
497 {0x00000089, 0x00000005},
498 {0x0000008b, 0x66030000},
499 {0x0000008c, 0x00006603},
500 {0x0000008d, 0x00000100},
501 {0x0000008f, 0x00001c0a},
502 {0x00000090, 0xff000001},
503 {0x00000094, 0x00101101},
504 {0x00000095, 0x00000fff},
505 {0x00000096, 0x00116fff},
506 {0x00000097, 0x60010000},
507 {0x00000098, 0x10010000},
508 {0x00000099, 0x00006000},
509 {0x0000009a, 0x00001000},
510 {0x0000009f, 0x00946a00}
511};
512
513static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
514 {0x00000077, 0xff010100},
515 {0x00000078, 0x00000000},
516 {0x00000079, 0x00001434},
517 {0x0000007a, 0xcc08ec08},
518 {0x0000007b, 0x00040000},
519 {0x0000007c, 0x000080c0},
520 {0x0000007d, 0x09000000},
521 {0x0000007e, 0x00210404},
522 {0x00000081, 0x08a8e800},
523 {0x00000082, 0x00030444},
524 {0x00000083, 0x00000000},
525 {0x00000085, 0x00000001},
526 {0x00000086, 0x00000002},
527 {0x00000087, 0x48490000},
528 {0x00000088, 0x20244647},
529 {0x00000089, 0x00000005},
530 {0x0000008b, 0x66030000},
531 {0x0000008c, 0x00006603},
532 {0x0000008d, 0x00000100},
533 {0x0000008f, 0x00001c0a},
534 {0x00000090, 0xff000001},
535 {0x00000094, 0x00101101},
536 {0x00000095, 0x00000fff},
537 {0x00000096, 0x00116fff},
538 {0x00000097, 0x60010000},
539 {0x00000098, 0x10010000},
540 {0x00000099, 0x00006000},
541 {0x0000009a, 0x00001000},
542 {0x0000009f, 0x00936a00}
543};
544
545static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
546 {0x00000077, 0xff010100},
547 {0x00000078, 0x00000000},
548 {0x00000079, 0x00001434},
549 {0x0000007a, 0xcc08ec08},
550 {0x0000007b, 0x00040000},
551 {0x0000007c, 0x000080c0},
552 {0x0000007d, 0x09000000},
553 {0x0000007e, 0x00210404},
554 {0x00000081, 0x08a8e800},
555 {0x00000082, 0x00030444},
556 {0x00000083, 0x00000000},
557 {0x00000085, 0x00000001},
558 {0x00000086, 0x00000002},
559 {0x00000087, 0x48490000},
560 {0x00000088, 0x20244647},
561 {0x00000089, 0x00000005},
562 {0x0000008b, 0x66030000},
563 {0x0000008c, 0x00006603},
564 {0x0000008d, 0x00000100},
565 {0x0000008f, 0x00001c0a},
566 {0x00000090, 0xff000001},
567 {0x00000094, 0x00101101},
568 {0x00000095, 0x00000fff},
569 {0x00000096, 0x00116fff},
570 {0x00000097, 0x60010000},
571 {0x00000098, 0x10010000},
572 {0x00000099, 0x00006000},
573 {0x0000009a, 0x00001000},
574 {0x0000009f, 0x00916a00}
575};
576
9b8253ce
AD		 577static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
578 {0x00000077, 0xff010100},
579 {0x00000078, 0x00000000},
580 {0x00000079, 0x00001434},
581 {0x0000007a, 0xcc08ec08},
582 {0x0000007b, 0x00040000},
583 {0x0000007c, 0x000080c0},
584 {0x0000007d, 0x09000000},
585 {0x0000007e, 0x00210404},
586 {0x00000081, 0x08a8e800},
587 {0x00000082, 0x00030444},
588 {0x00000083, 0x00000000},
589 {0x00000085, 0x00000001},
590 {0x00000086, 0x00000002},
591 {0x00000087, 0x48490000},
592 {0x00000088, 0x20244647},
593 {0x00000089, 0x00000005},
594 {0x0000008b, 0x66030000},
595 {0x0000008c, 0x00006603},
596 {0x0000008d, 0x00000100},
597 {0x0000008f, 0x00001c0a},
598 {0x00000090, 0xff000001},
599 {0x00000094, 0x00101101},
600 {0x00000095, 0x00000fff},
601 {0x00000096, 0x00116fff},
602 {0x00000097, 0x60010000},
603 {0x00000098, 0x10010000},
604 {0x00000099, 0x00006000},
605 {0x0000009a, 0x00001000},
606 {0x0000009f, 0x00976b00}
607};
608
755d819e 609int ni_mc_load_microcode(struct radeon_device *rdev)
0af62b01
AD		 610{
611 const __be32 *fw_data;
612 u32 mem_type, running, blackout = 0;
613 u32 *io_mc_regs;
9b8253ce 614 int i, ucode_size, regs_size;
0af62b01
AD		 615
616 if (!rdev->mc_fw)
617 return -EINVAL;
618
619 switch (rdev->family) {
620 case CHIP_BARTS:
621 io_mc_regs = (u32 *)&barts_io_mc_regs;
9b8253ce
AD		 622 ucode_size = BTC_MC_UCODE_SIZE;
623 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 624 break;
625 case CHIP_TURKS:
626 io_mc_regs = (u32 *)&turks_io_mc_regs;
9b8253ce
AD		 627 ucode_size = BTC_MC_UCODE_SIZE;
628 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 629 break;
630 case CHIP_CAICOS:
631 default:
632 io_mc_regs = (u32 *)&caicos_io_mc_regs;
9b8253ce
AD		 633 ucode_size = BTC_MC_UCODE_SIZE;
634 regs_size = BTC_IO_MC_REGS_SIZE;
635 break;
636 case CHIP_CAYMAN:
637 io_mc_regs = (u32 *)&cayman_io_mc_regs;
638 ucode_size = CAYMAN_MC_UCODE_SIZE;
639 regs_size = BTC_IO_MC_REGS_SIZE;
0af62b01
AD		 640 break;
641 }
642
643 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
644 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
645
646 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
647 if (running) {
648 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
649 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
650 }
651
652 /* reset the engine and set to writable */
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
654 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
655
656 /* load mc io regs */
9b8253ce 657 for (i = 0; i < regs_size; i++) {
0af62b01
AD		 658 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
659 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
660 }
661 /* load the MC ucode */
662 fw_data = (const __be32 *)rdev->mc_fw->data;
9b8253ce 663 for (i = 0; i < ucode_size; i++)
0af62b01
AD		 664 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
665
666 /* put the engine back into the active state */
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
669 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
670
671 /* wait for training to complete */
0e2c978e
AD		 672 for (i = 0; i < rdev->usec_timeout; i++) {
673 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
674 break;
675 udelay(1);
676 }
0af62b01
AD		 677
678 if (running)
679 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
680 }
681
682 return 0;
683}
684
685int ni_init_microcode(struct radeon_device *rdev)
686{
0af62b01
AD		 687 const char *chip_name;
688 const char *rlc_chip_name;
689 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
6596afd4 690 size_t smc_req_size = 0;
0af62b01
AD		 691 char fw_name[30];
692 int err;
693
694 DRM_DEBUG("\n");
695
0af62b01
AD		 696 switch (rdev->family) {
697 case CHIP_BARTS:
698 chip_name = "BARTS";
699 rlc_chip_name = "BTC";
9b8253ce
AD		 700 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
701 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
702 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
703 mc_req_size = BTC_MC_UCODE_SIZE * 4;
6596afd4 704 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
0af62b01
AD		 705 break;
706 case CHIP_TURKS:
707 chip_name = "TURKS";
708 rlc_chip_name = "BTC";
9b8253ce
AD		 709 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
710 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
711 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
712 mc_req_size = BTC_MC_UCODE_SIZE * 4;
6596afd4 713 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
0af62b01
AD		 714 break;
715 case CHIP_CAICOS:
716 chip_name = "CAICOS";
717 rlc_chip_name = "BTC";
9b8253ce
AD		 718 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
719 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
720 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
721 mc_req_size = BTC_MC_UCODE_SIZE * 4;
6596afd4 722 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
9b8253ce
AD		 723 break;
724 case CHIP_CAYMAN:
725 chip_name = "CAYMAN";
726 rlc_chip_name = "CAYMAN";
727 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
728 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
729 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
730 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
69e0b57a 731 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
0af62b01 732 break;
c420c745
AD		 733 case CHIP_ARUBA:
734 chip_name = "ARUBA";
735 rlc_chip_name = "ARUBA";
736 /* pfp/me same size as CAYMAN */
737 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
738 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
739 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
740 mc_req_size = 0;
741 break;
0af62b01
AD		 742 default: BUG();
743 }
744
0af62b01
AD		 745 DRM_INFO("Loading %s Microcode\n", chip_name);
746
747 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
0a168933 748 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
0af62b01
AD		 749 if (err)
750 goto out;
751 if (rdev->pfp_fw->size != pfp_req_size) {
752 printk(KERN_ERR
753 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
754 rdev->pfp_fw->size, fw_name);
755 err = -EINVAL;
756 goto out;
757 }
758
759 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
0a168933 760 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
0af62b01
AD		 761 if (err)
762 goto out;
763 if (rdev->me_fw->size != me_req_size) {
764 printk(KERN_ERR
765 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
766 rdev->me_fw->size, fw_name);
767 err = -EINVAL;
768 }
769
770 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
0a168933 771 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
0af62b01
AD		 772 if (err)
773 goto out;
774 if (rdev->rlc_fw->size != rlc_req_size) {
775 printk(KERN_ERR
776 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
777 rdev->rlc_fw->size, fw_name);
778 err = -EINVAL;
779 }
780
c420c745
AD		 781 /* no MC ucode on TN */
782 if (!(rdev->flags & RADEON_IS_IGP)) {
783 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
0a168933 784 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
c420c745
AD		 785 if (err)
786 goto out;
787 if (rdev->mc_fw->size != mc_req_size) {
788 printk(KERN_ERR
789 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
790 rdev->mc_fw->size, fw_name);
791 err = -EINVAL;
792 }
0af62b01 793 }
6596afd4 794
69e0b57a 795 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
6596afd4 796 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
0a168933 797 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
8a53fa23
AD		 798 if (err) {
799 printk(KERN_ERR
800 "smc: error loading firmware \"%s\"\n",
801 fw_name);
802 release_firmware(rdev->smc_fw);
803 rdev->smc_fw = NULL;
d8367112 804 err = 0;
8a53fa23 805 } else if (rdev->smc_fw->size != smc_req_size) {
6596afd4
AD		 806 printk(KERN_ERR
807 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
808 rdev->mc_fw->size, fw_name);
809 err = -EINVAL;
810 }
811 }
812
0af62b01 813out:
0af62b01
AD		 814 if (err) {
815 if (err != -EINVAL)
816 printk(KERN_ERR
817 "ni_cp: Failed to load firmware \"%s\"\n",
818 fw_name);
819 release_firmware(rdev->pfp_fw);
820 rdev->pfp_fw = NULL;
821 release_firmware(rdev->me_fw);
822 rdev->me_fw = NULL;
823 release_firmware(rdev->rlc_fw);
824 rdev->rlc_fw = NULL;
825 release_firmware(rdev->mc_fw);
826 rdev->mc_fw = NULL;
827 }
828 return err;
829}
830
e66582f9
AD		 831/**
832 * cayman_get_allowed_info_register - fetch the register for the info ioctl
833 *
834 * @rdev: radeon_device pointer
835 * @reg: register offset in bytes
836 * @val: register value
837 *
838 * Returns 0 for success or -EINVAL for an invalid register
839 *
840 */
841int cayman_get_allowed_info_register(struct radeon_device *rdev,
842 u32 reg, u32 *val)
843{
844 switch (reg) {
845 case GRBM_STATUS:
846 case GRBM_STATUS_SE0:
847 case GRBM_STATUS_SE1:
848 case SRBM_STATUS:
849 case SRBM_STATUS2:
850 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
851 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
852 case UVD_STATUS:
853 *val = RREG32(reg);
854 return 0;
855 default:
856 return -EINVAL;
857 }
858}
859
29a15221
AD		 860int tn_get_temp(struct radeon_device *rdev)
861{
862 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
863 int actual_temp = (temp / 8) - 49;
864
865 return actual_temp * 1000;
866}
867
fecf1d07
AD		 868/*
869 * Core functions
870 */
fecf1d07
AD		 871static void cayman_gpu_init(struct radeon_device *rdev)
872{
fecf1d07
AD		 873 u32 gb_addr_config = 0;
874 u32 mc_shared_chmap, mc_arb_ramcfg;
fecf1d07
AD		 875 u32 cgts_tcc_disable;
876 u32 sx_debug_1;
877 u32 smx_dc_ctl0;
fecf1d07
AD		 878 u32 cgts_sm_ctrl_reg;
879 u32 hdp_host_path_cntl;
880 u32 tmp;
416a2bd2 881 u32 disabled_rb_mask;
fecf1d07
AD		 882 int i, j;
883
884 switch (rdev->family) {
885 case CHIP_CAYMAN:
fecf1d07
AD		 886 rdev->config.cayman.max_shader_engines = 2;
887 rdev->config.cayman.max_pipes_per_simd = 4;
888 rdev->config.cayman.max_tile_pipes = 8;
889 rdev->config.cayman.max_simds_per_se = 12;
890 rdev->config.cayman.max_backends_per_se = 4;
891 rdev->config.cayman.max_texture_channel_caches = 8;
892 rdev->config.cayman.max_gprs = 256;
893 rdev->config.cayman.max_threads = 256;
894 rdev->config.cayman.max_gs_threads = 32;
895 rdev->config.cayman.max_stack_entries = 512;
896 rdev->config.cayman.sx_num_of_sets = 8;
897 rdev->config.cayman.sx_max_export_size = 256;
898 rdev->config.cayman.sx_max_export_pos_size = 64;
899 rdev->config.cayman.sx_max_export_smx_size = 192;
900 rdev->config.cayman.max_hw_contexts = 8;
901 rdev->config.cayman.sq_num_cf_insts = 2;
902
903 rdev->config.cayman.sc_prim_fifo_size = 0x100;
904 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
905 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 906 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
fecf1d07 907 break;
7b76e479
AD		 908 case CHIP_ARUBA:
909 default:
910 rdev->config.cayman.max_shader_engines = 1;
911 rdev->config.cayman.max_pipes_per_simd = 4;
912 rdev->config.cayman.max_tile_pipes = 2;
913 if ((rdev->pdev->device == 0x9900) ||
d430f7db
AD		 914 (rdev->pdev->device == 0x9901) ||
915 (rdev->pdev->device == 0x9905) ||
916 (rdev->pdev->device == 0x9906) ||
917 (rdev->pdev->device == 0x9907) ||
918 (rdev->pdev->device == 0x9908) ||
919 (rdev->pdev->device == 0x9909) ||
e4d17063
AD		 920 (rdev->pdev->device == 0x990B) ||
921 (rdev->pdev->device == 0x990C) ||
922 (rdev->pdev->device == 0x990F) ||
d430f7db 923 (rdev->pdev->device == 0x9910) ||
e4d17063 924 (rdev->pdev->device == 0x9917) ||
62d1f92e
AD		 925 (rdev->pdev->device == 0x9999) ||
926 (rdev->pdev->device == 0x999C)) {
7b76e479
AD		 927 rdev->config.cayman.max_simds_per_se = 6;
928 rdev->config.cayman.max_backends_per_se = 2;
e2f6c88f
AD		 929 rdev->config.cayman.max_hw_contexts = 8;
930 rdev->config.cayman.sx_max_export_size = 256;
931 rdev->config.cayman.sx_max_export_pos_size = 64;
932 rdev->config.cayman.sx_max_export_smx_size = 192;
7b76e479 933 } else if ((rdev->pdev->device == 0x9903) ||
d430f7db
AD		 934 (rdev->pdev->device == 0x9904) ||
935 (rdev->pdev->device == 0x990A) ||
e4d17063
AD		 936 (rdev->pdev->device == 0x990D) ||
937 (rdev->pdev->device == 0x990E) ||
d430f7db 938 (rdev->pdev->device == 0x9913) ||
62d1f92e
AD		 939 (rdev->pdev->device == 0x9918) ||
940 (rdev->pdev->device == 0x999D)) {
7b76e479
AD		 941 rdev->config.cayman.max_simds_per_se = 4;
942 rdev->config.cayman.max_backends_per_se = 2;
e2f6c88f
AD		 943 rdev->config.cayman.max_hw_contexts = 8;
944 rdev->config.cayman.sx_max_export_size = 256;
945 rdev->config.cayman.sx_max_export_pos_size = 64;
946 rdev->config.cayman.sx_max_export_smx_size = 192;
d430f7db
AD		 947 } else if ((rdev->pdev->device == 0x9919) ||
948 (rdev->pdev->device == 0x9990) ||
949 (rdev->pdev->device == 0x9991) ||
950 (rdev->pdev->device == 0x9994) ||
e4d17063
AD		 951 (rdev->pdev->device == 0x9995) ||
952 (rdev->pdev->device == 0x9996) ||
953 (rdev->pdev->device == 0x999A) ||
d430f7db 954 (rdev->pdev->device == 0x99A0)) {
7b76e479
AD		 955 rdev->config.cayman.max_simds_per_se = 3;
956 rdev->config.cayman.max_backends_per_se = 1;
e2f6c88f
AD		 957 rdev->config.cayman.max_hw_contexts = 4;
958 rdev->config.cayman.sx_max_export_size = 128;
959 rdev->config.cayman.sx_max_export_pos_size = 32;
960 rdev->config.cayman.sx_max_export_smx_size = 96;
7b76e479
AD		 961 } else {
962 rdev->config.cayman.max_simds_per_se = 2;
963 rdev->config.cayman.max_backends_per_se = 1;
e2f6c88f
AD		 964 rdev->config.cayman.max_hw_contexts = 4;
965 rdev->config.cayman.sx_max_export_size = 128;
966 rdev->config.cayman.sx_max_export_pos_size = 32;
967 rdev->config.cayman.sx_max_export_smx_size = 96;
7b76e479
AD		 968 }
969 rdev->config.cayman.max_texture_channel_caches = 2;
970 rdev->config.cayman.max_gprs = 256;
971 rdev->config.cayman.max_threads = 256;
972 rdev->config.cayman.max_gs_threads = 32;
973 rdev->config.cayman.max_stack_entries = 512;
974 rdev->config.cayman.sx_num_of_sets = 8;
7b76e479
AD		 975 rdev->config.cayman.sq_num_cf_insts = 2;
976
977 rdev->config.cayman.sc_prim_fifo_size = 0x40;
978 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
979 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 980 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
7b76e479 981 break;
fecf1d07
AD		 982 }
983
984 /* Initialize HDP */
985 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
986 WREG32((0x2c14 + j), 0x00000000);
987 WREG32((0x2c18 + j), 0x00000000);
988 WREG32((0x2c1c + j), 0x00000000);
989 WREG32((0x2c20 + j), 0x00000000);
990 WREG32((0x2c24 + j), 0x00000000);
991 }
992
993 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
acc1522a
CK		 994 WREG32(SRBM_INT_CNTL, 0x1);
995 WREG32(SRBM_INT_ACK, 0x1);
fecf1d07 996
d054ac16
AD		 997 evergreen_fix_pci_max_read_req_size(rdev);
998
fecf1d07
AD		 999 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1000 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1001
fecf1d07
AD		 1002 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1003 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1004 if (rdev->config.cayman.mem_row_size_in_kb > 4)
1005 rdev->config.cayman.mem_row_size_in_kb = 4;
1006 /* XXX use MC settings? */
1007 rdev->config.cayman.shader_engine_tile_size = 32;
1008 rdev->config.cayman.num_gpus = 1;
1009 rdev->config.cayman.multi_gpu_tile_size = 64;
1010
fecf1d07
AD		 1011 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1012 rdev->config.cayman.num_tile_pipes = (1 << tmp);
1013 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1014 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
1015 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1016 rdev->config.cayman.num_shader_engines = tmp + 1;
1017 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1018 rdev->config.cayman.num_gpus = tmp + 1;
1019 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1020 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1021 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1022 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1023
416a2bd2 1024
fecf1d07
AD		 1025 /* setup tiling info dword. gb_addr_config is not adequate since it does
1026 * not have bank info, so create a custom tiling dword.
1027 * bits 3:0 num_pipes
1028 * bits 7:4 num_banks
1029 * bits 11:8 group_size
1030 * bits 15:12 row_size
1031 */
1032 rdev->config.cayman.tile_config = 0;
1033 switch (rdev->config.cayman.num_tile_pipes) {
1034 case 1:
1035 default:
1036 rdev->config.cayman.tile_config |= (0 << 0);
1037 break;
1038 case 2:
1039 rdev->config.cayman.tile_config |= (1 << 0);
1040 break;
1041 case 4:
1042 rdev->config.cayman.tile_config |= (2 << 0);
1043 break;
1044 case 8:
1045 rdev->config.cayman.tile_config |= (3 << 0);
1046 break;
1047 }
7b76e479
AD		 1048
1049 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1050 if (rdev->flags & RADEON_IS_IGP)
1f73cca7 1051 rdev->config.cayman.tile_config |= 1 << 4;
29d65406 1052 else {
5b23c904
AD		 1053 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1054 case 0: /* four banks */
29d65406 1055 rdev->config.cayman.tile_config |= 0 << 4;
5b23c904
AD		 1056 break;
1057 case 1: /* eight banks */
1058 rdev->config.cayman.tile_config |= 1 << 4;
1059 break;
1060 case 2: /* sixteen banks */
1061 default:
1062 rdev->config.cayman.tile_config |= 2 << 4;
1063 break;
1064 }
29d65406 1065 }
fecf1d07 1066 rdev->config.cayman.tile_config |=
cde5083b 1067 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
fecf1d07
AD		 1068 rdev->config.cayman.tile_config |=
1069 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1070
416a2bd2
AD		 1071 tmp = 0;
1072 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1073 u32 rb_disable_bitmap;
1074
1075 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1076 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1077 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1078 tmp <<= 4;
1079 tmp |= rb_disable_bitmap;
1080 }
1081 /* enabled rb are just the one not disabled :) */
1082 disabled_rb_mask = tmp;
cedb655a
AD		 1083 tmp = 0;
1084 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1085 tmp |= (1 << i);
1086 /* if all the backends are disabled, fix it up here */
1087 if ((disabled_rb_mask & tmp) == tmp) {
1088 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1089 disabled_rb_mask &= ~(1 << i);
1090 }
416a2bd2 1091
65fcf668
AD		 1092 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
1093 u32 simd_disable_bitmap;
1094
1095 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1096 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1097 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
1098 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
1099 tmp <<= 16;
1100 tmp |= simd_disable_bitmap;
1101 }
1102 rdev->config.cayman.active_simds = hweight32(~tmp);
1103
416a2bd2
AD		 1104 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1105 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1106
fecf1d07
AD		 1107 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1108 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
7c1c7c18
AD		 1109 if (ASIC_IS_DCE6(rdev))
1110 WREG32(DMIF_ADDR_CALC, gb_addr_config);
fecf1d07 1111 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
f60cbd11
AD		 1112 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1113 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
9a21059d
CK		 1114 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1115 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1116 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
fecf1d07 1117
8f612b23
AD		 1118 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1119 (rdev->flags & RADEON_IS_IGP)) {
dbfb00c3 1120 if ((disabled_rb_mask & 3) == 2) {
8f612b23
AD		 1121 /* RB1 disabled, RB0 enabled */
1122 tmp = 0x00000000;
dbfb00c3
AD		 1123 } else {
1124 /* RB0 disabled, RB1 enabled */
1125 tmp = 0x11111111;
8f612b23
AD		 1126 }
1127 } else {
1128 tmp = gb_addr_config & NUM_PIPES_MASK;
1129 tmp = r6xx_remap_render_backend(rdev, tmp,
1130 rdev->config.cayman.max_backends_per_se *
1131 rdev->config.cayman.max_shader_engines,
1132 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1133 }
416a2bd2 1134 WREG32(GB_BACKEND_MAP, tmp);
fecf1d07 1135
416a2bd2
AD		 1136 cgts_tcc_disable = 0xffff0000;
1137 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1138 cgts_tcc_disable &= ~(1 << (16 + i));
fecf1d07
AD		 1139 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1140 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
fecf1d07
AD		 1141 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1142 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1143
1144 /* reprogram the shader complex */
1145 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1146 for (i = 0; i < 16; i++)
1147 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1148 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1149
1150 /* set HW defaults for 3D engine */
1151 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1152
1153 sx_debug_1 = RREG32(SX_DEBUG_1);
1154 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1155 WREG32(SX_DEBUG_1, sx_debug_1);
1156
1157 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1158 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
285e042d 1159 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
fecf1d07
AD		 1160 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1161
1162 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1163
1164 /* need to be explicitly zero-ed */
1165 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1166 WREG32(SQ_LSTMP_RING_BASE, 0);
1167 WREG32(SQ_HSTMP_RING_BASE, 0);
1168 WREG32(SQ_ESTMP_RING_BASE, 0);
1169 WREG32(SQ_GSTMP_RING_BASE, 0);
1170 WREG32(SQ_VSTMP_RING_BASE, 0);
1171 WREG32(SQ_PSTMP_RING_BASE, 0);
1172
1173 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1174
285e042d
DA		 1175 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1176 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1177 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
fecf1d07 1178
285e042d
DA		 1179 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1180 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1181 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
fecf1d07
AD		 1182
1183
1184 WREG32(VGT_NUM_INSTANCES, 1);
1185
1186 WREG32(CP_PERFMON_CNTL, 0);
1187
285e042d 1188 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
fecf1d07
AD		 1189 FETCH_FIFO_HIWATER(0x4) |
1190 DONE_FIFO_HIWATER(0xe0) |
1191 ALU_UPDATE_FIFO_HIWATER(0x8)));
1192
1193 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1194 WREG32(SQ_CONFIG, (VC_ENABLE |
1195 EXPORT_SRC_C |
1196 GFX_PRIO(0) |
1197 CS1_PRIO(0) |
1198 CS2_PRIO(1)));
1199 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1200
1201 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1202 FORCE_EOV_MAX_REZ_CNT(255)));
1203
1204 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1205 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1206
1207 WREG32(VGT_GS_VERTEX_REUSE, 16);
1208 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1209
1210 WREG32(CB_PERF_CTR0_SEL_0, 0);
1211 WREG32(CB_PERF_CTR0_SEL_1, 0);
1212 WREG32(CB_PERF_CTR1_SEL_0, 0);
1213 WREG32(CB_PERF_CTR1_SEL_1, 0);
1214 WREG32(CB_PERF_CTR2_SEL_0, 0);
1215 WREG32(CB_PERF_CTR2_SEL_1, 0);
1216 WREG32(CB_PERF_CTR3_SEL_0, 0);
1217 WREG32(CB_PERF_CTR3_SEL_1, 0);
1218
0b65f83f
DA		 1219 tmp = RREG32(HDP_MISC_CNTL);
1220 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1221 WREG32(HDP_MISC_CNTL, tmp);
1222
fecf1d07
AD		 1223 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1224 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1225
1226 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1227
1228 udelay(50);
8ba10463
AD		 1229
1230 /* set clockgating golden values on TN */
1231 if (rdev->family == CHIP_ARUBA) {
1232 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1233 tmp &= ~0x00380000;
1234 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1235 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1236 tmp &= ~0x0e000000;
1237 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1238 }
fecf1d07
AD		 1239}
1240
fa8198ea
AD		 1241/*
1242 * GART
1243 */
1244void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1245{
1246 /* flush hdp cache */
1247 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1248
1249 /* bits 0-7 are the VM contexts0-7 */
1250 WREG32(VM_INVALIDATE_REQUEST, 1);
1251}
1252
1109ca09 1253static int cayman_pcie_gart_enable(struct radeon_device *rdev)
fa8198ea 1254{
721604a1 1255 int i, r;
fa8198ea 1256
c9a1be96 1257 if (rdev->gart.robj == NULL) {
fa8198ea
AD		 1258 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1259 return -EINVAL;
1260 }
1261 r = radeon_gart_table_vram_pin(rdev);
1262 if (r)
1263 return r;
fa8198ea 1264 /* Setup TLB control */
721604a1
JG		 1265 WREG32(MC_VM_MX_L1_TLB_CNTL,
1266 (0xA << 7) |
1267 ENABLE_L1_TLB |
fa8198ea
AD		 1268 ENABLE_L1_FRAGMENT_PROCESSING |
1269 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
721604a1 1270 ENABLE_ADVANCED_DRIVER_MODEL |
fa8198ea
AD		 1271 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1272 /* Setup L2 cache */
1273 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
ec3dbbcb 1274 ENABLE_L2_FRAGMENT_PROCESSING |
fa8198ea
AD		 1275 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1276 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1277 EFFECTIVE_L2_QUEUE_SIZE(7) |
1278 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1279 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1280 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
ec3dbbcb 1281 BANK_SELECT(6) |
fa8198ea
AD		 1282 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1283 /* setup context0 */
1284 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1285 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1286 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1287 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1288 (u32)(rdev->dummy_page.addr >> 12));
1289 WREG32(VM_CONTEXT0_CNTL2, 0);
1290 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1291 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
721604a1
JG		 1292
1293 WREG32(0x15D4, 0);
1294 WREG32(0x15D8, 0);
1295 WREG32(0x15DC, 0);
1296
1297 /* empty context1-7 */
23d4f1f2
AD		 1298 /* Assign the pt base to something valid for now; the pts used for
1299 * the VMs are determined by the application and setup and assigned
1300 * on the fly in the vm part of radeon_gart.c
1301 */
721604a1
JG		 1302 for (i = 1; i < 8; i++) {
1303 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
c1a7ca0d 1304 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
721604a1 1305 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
054e01d6 1306 rdev->vm_manager.saved_table_addr[i]);
721604a1
JG		 1307 }
1308
1309 /* enable context1-7 */
1310 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1311 (u32)(rdev->dummy_page.addr >> 12));
ae133a11 1312 WREG32(VM_CONTEXT1_CNTL2, 4);
fa87e62d 1313 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4510fb98 1314 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
ae133a11
CK		 1315 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1316 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1317 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1318 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1319 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1320 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1321 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1322 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1323 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1324 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1325 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1326 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
fa8198ea
AD		 1327
1328 cayman_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1329 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1330 (unsigned)(rdev->mc.gtt_size >> 20),
1331 (unsigned long long)rdev->gart.table_addr);
fa8198ea
AD		 1332 rdev->gart.ready = true;
1333 return 0;
1334}
1335
1109ca09 1336static void cayman_pcie_gart_disable(struct radeon_device *rdev)
fa8198ea 1337{
054e01d6
CK		 1338 unsigned i;
1339
1340 for (i = 1; i < 8; ++i) {
1341 rdev->vm_manager.saved_table_addr[i] = RREG32(
1342 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
1343 }
1344
fa8198ea
AD		 1345 /* Disable all tables */
1346 WREG32(VM_CONTEXT0_CNTL, 0);
1347 WREG32(VM_CONTEXT1_CNTL, 0);
1348 /* Setup TLB control */
1349 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1350 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1351 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1352 /* Setup L2 cache */
1353 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1354 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1355 EFFECTIVE_L2_QUEUE_SIZE(7) |
1356 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1357 WREG32(VM_L2_CNTL2, 0);
1358 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1359 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
c9a1be96 1360 radeon_gart_table_vram_unpin(rdev);
fa8198ea
AD		 1361}
1362
1109ca09 1363static void cayman_pcie_gart_fini(struct radeon_device *rdev)
fa8198ea
AD		 1364{
1365 cayman_pcie_gart_disable(rdev);
1366 radeon_gart_table_vram_free(rdev);
1367 radeon_gart_fini(rdev);
1368}
1369
1b37078b
AD		 1370void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1371 int ring, u32 cp_int_cntl)
1372{
1373 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1374
1375 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1376 WREG32(CP_INT_CNTL, cp_int_cntl);
1377}
1378
0c88a02e
AD		 1379/*
1380 * CP.
1381 */
b40e7e16
AD		 1382void cayman_fence_ring_emit(struct radeon_device *rdev,
1383 struct radeon_fence *fence)
1384{
1385 struct radeon_ring *ring = &rdev->ring[fence->ring];
1386 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
10e9ffae
AD		 1387 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1388 PACKET3_SH_ACTION_ENA;
b40e7e16 1389
721604a1 1390 /* flush read cache over gart for this vmid */
b40e7e16 1391 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
10e9ffae 1392 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
b40e7e16
AD		 1393 radeon_ring_write(ring, 0xFFFFFFFF);
1394 radeon_ring_write(ring, 0);
1395 radeon_ring_write(ring, 10); /* poll interval */
1396 /* EVENT_WRITE_EOP - flush caches, send int */
1397 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1398 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
5e167cdb 1399 radeon_ring_write(ring, lower_32_bits(addr));
b40e7e16
AD		 1400 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1401 radeon_ring_write(ring, fence->seq);
1402 radeon_ring_write(ring, 0);
1403}
1404
721604a1
JG		 1405void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1406{
876dc9f3 1407 struct radeon_ring *ring = &rdev->ring[ib->ring];
7c42bc1a 1408 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
10e9ffae
AD		 1409 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1410 PACKET3_SH_ACTION_ENA;
721604a1
JG		 1411
1412 /* set to DX10/11 mode */
1413 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1414 radeon_ring_write(ring, 1);
45df6803
CK		 1415
1416 if (ring->rptr_save_reg) {
1417 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1418 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1419 radeon_ring_write(ring, ((ring->rptr_save_reg -
1420 PACKET3_SET_CONFIG_REG_START) >> 2));
1421 radeon_ring_write(ring, next_rptr);
1422 }
1423
721604a1
JG		 1424 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1425 radeon_ring_write(ring,
1426#ifdef __BIG_ENDIAN
1427 (2 << 0) |
1428#endif
1429 (ib->gpu_addr & 0xFFFFFFFC));
1430 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
7c42bc1a 1431 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
721604a1
JG		 1432
1433 /* flush read cache over gart for this vmid */
721604a1 1434 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
10e9ffae 1435 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
721604a1
JG		 1436 radeon_ring_write(ring, 0xFFFFFFFF);
1437 radeon_ring_write(ring, 0);
7c42bc1a 1438 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */
721604a1
JG		 1439}
1440
0c88a02e
AD		 1441static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1442{
1443 if (enable)
1444 WREG32(CP_ME_CNTL, 0);
1445 else {
50efa51a
AD		 1446 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1447 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
0c88a02e
AD		 1448 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1449 WREG32(SCRATCH_UMSK, 0);
f60cbd11 1450 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c88a02e
AD		 1451 }
1452}
1453
ea31bf69
AD		 1454u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1455 struct radeon_ring *ring)
1456{
1457 u32 rptr;
1458
1459 if (rdev->wb.enabled)
1460 rptr = rdev->wb.wb[ring->rptr_offs/4];
1461 else {
1462 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1463 rptr = RREG32(CP_RB0_RPTR);
1464 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1465 rptr = RREG32(CP_RB1_RPTR);
1466 else
1467 rptr = RREG32(CP_RB2_RPTR);
1468 }
1469
1470 return rptr;
1471}
1472
1473u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1474 struct radeon_ring *ring)
1475{
1476 u32 wptr;
1477
1478 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1479 wptr = RREG32(CP_RB0_WPTR);
1480 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1481 wptr = RREG32(CP_RB1_WPTR);
1482 else
1483 wptr = RREG32(CP_RB2_WPTR);
1484
1485 return wptr;
1486}
1487
1488void cayman_gfx_set_wptr(struct radeon_device *rdev,
1489 struct radeon_ring *ring)
1490{
1491 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1492 WREG32(CP_RB0_WPTR, ring->wptr);
1493 (void)RREG32(CP_RB0_WPTR);
1494 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1495 WREG32(CP_RB1_WPTR, ring->wptr);
1496 (void)RREG32(CP_RB1_WPTR);
1497 } else {
1498 WREG32(CP_RB2_WPTR, ring->wptr);
1499 (void)RREG32(CP_RB2_WPTR);
1500 }
1501}
1502
0c88a02e
AD		 1503static int cayman_cp_load_microcode(struct radeon_device *rdev)
1504{
1505 const __be32 *fw_data;
1506 int i;
1507
1508 if (!rdev->me_fw || !rdev->pfp_fw)
1509 return -EINVAL;
1510
1511 cayman_cp_enable(rdev, false);
1512
1513 fw_data = (const __be32 *)rdev->pfp_fw->data;
1514 WREG32(CP_PFP_UCODE_ADDR, 0);
1515 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1516 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1517 WREG32(CP_PFP_UCODE_ADDR, 0);
1518
1519 fw_data = (const __be32 *)rdev->me_fw->data;
1520 WREG32(CP_ME_RAM_WADDR, 0);
1521 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1522 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1523
1524 WREG32(CP_PFP_UCODE_ADDR, 0);
1525 WREG32(CP_ME_RAM_WADDR, 0);
1526 WREG32(CP_ME_RAM_RADDR, 0);
1527 return 0;
1528}
1529
1530static int cayman_cp_start(struct radeon_device *rdev)
1531{
e32eb50d 1532 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
0c88a02e
AD		 1533 int r, i;
1534
e32eb50d 1535 r = radeon_ring_lock(rdev, ring, 7);
0c88a02e
AD		 1536 if (r) {
1537 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1538 return r;
1539 }
e32eb50d
CK		 1540 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1541 radeon_ring_write(ring, 0x1);
1542 radeon_ring_write(ring, 0x0);
1543 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1544 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1545 radeon_ring_write(ring, 0);
1546 radeon_ring_write(ring, 0);
1538a9e0 1547 radeon_ring_unlock_commit(rdev, ring, false);
0c88a02e
AD		 1548
1549 cayman_cp_enable(rdev, true);
1550
e32eb50d 1551 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
0c88a02e
AD		 1552 if (r) {
1553 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1554 return r;
1555 }
1556
1557 /* setup clear context state */
e32eb50d
CK		 1558 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1559 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
0c88a02e
AD		 1560
1561 for (i = 0; i < cayman_default_size; i++)
e32eb50d 1562 radeon_ring_write(ring, cayman_default_state[i]);
0c88a02e 1563
e32eb50d
CK		 1564 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1565 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
0c88a02e
AD		 1566
1567 /* set clear context state */
e32eb50d
CK		 1568 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1569 radeon_ring_write(ring, 0);
0c88a02e
AD		 1570
1571 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1572 radeon_ring_write(ring, 0xc0026f00);
1573 radeon_ring_write(ring, 0x00000000);
1574 radeon_ring_write(ring, 0x00000000);
1575 radeon_ring_write(ring, 0x00000000);
0c88a02e
AD		 1576
1577 /* Clear consts */
e32eb50d
CK		 1578 radeon_ring_write(ring, 0xc0036f00);
1579 radeon_ring_write(ring, 0x00000bc4);
1580 radeon_ring_write(ring, 0xffffffff);
1581 radeon_ring_write(ring, 0xffffffff);
1582 radeon_ring_write(ring, 0xffffffff);
0c88a02e 1583
e32eb50d
CK		 1584 radeon_ring_write(ring, 0xc0026900);
1585 radeon_ring_write(ring, 0x00000316);
1586 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1587 radeon_ring_write(ring, 0x00000010); /* */
9b91d18d 1588
1538a9e0 1589 radeon_ring_unlock_commit(rdev, ring, false);
0c88a02e
AD		 1590
1591 /* XXX init other rings */
1592
1593 return 0;
1594}
1595
755d819e
AD		 1596static void cayman_cp_fini(struct radeon_device *rdev)
1597{
45df6803 1598 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e 1599 cayman_cp_enable(rdev, false);
45df6803
CK		 1600 radeon_ring_fini(rdev, ring);
1601 radeon_scratch_free(rdev, ring->rptr_save_reg);
755d819e
AD		 1602}
1603
1109ca09 1604static int cayman_cp_resume(struct radeon_device *rdev)
0c88a02e 1605{
b90ca986
CK		 1606 static const int ridx[] = {
1607 RADEON_RING_TYPE_GFX_INDEX,
1608 CAYMAN_RING_TYPE_CP1_INDEX,
1609 CAYMAN_RING_TYPE_CP2_INDEX
1610 };
1611 static const unsigned cp_rb_cntl[] = {
1612 CP_RB0_CNTL,
1613 CP_RB1_CNTL,
1614 CP_RB2_CNTL,
1615 };
1616 static const unsigned cp_rb_rptr_addr[] = {
1617 CP_RB0_RPTR_ADDR,
1618 CP_RB1_RPTR_ADDR,
1619 CP_RB2_RPTR_ADDR
1620 };
1621 static const unsigned cp_rb_rptr_addr_hi[] = {
1622 CP_RB0_RPTR_ADDR_HI,
1623 CP_RB1_RPTR_ADDR_HI,
1624 CP_RB2_RPTR_ADDR_HI
1625 };
1626 static const unsigned cp_rb_base[] = {
1627 CP_RB0_BASE,
1628 CP_RB1_BASE,
1629 CP_RB2_BASE
1630 };
ea31bf69
AD		 1631 static const unsigned cp_rb_rptr[] = {
1632 CP_RB0_RPTR,
1633 CP_RB1_RPTR,
1634 CP_RB2_RPTR
1635 };
1636 static const unsigned cp_rb_wptr[] = {
1637 CP_RB0_WPTR,
1638 CP_RB1_WPTR,
1639 CP_RB2_WPTR
1640 };
e32eb50d 1641 struct radeon_ring *ring;
b90ca986 1642 int i, r;
0c88a02e
AD		 1643
1644 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1645 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1646 SOFT_RESET_PA |
1647 SOFT_RESET_SH |
1648 SOFT_RESET_VGT |
a49a50da 1649 SOFT_RESET_SPI |
0c88a02e
AD		 1650 SOFT_RESET_SX));
1651 RREG32(GRBM_SOFT_RESET);
1652 mdelay(15);
1653 WREG32(GRBM_SOFT_RESET, 0);
1654 RREG32(GRBM_SOFT_RESET);
1655
15d3332f 1656 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1657 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
0c88a02e
AD		 1658
1659 /* Set the write pointer delay */
1660 WREG32(CP_RB_WPTR_DELAY, 0);
1661
1662 WREG32(CP_DEBUG, (1 << 27));
1663
48fc7f7e 1664 /* set the wb address whether it's enabled or not */
0c88a02e 1665 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
b90ca986 1666 WREG32(SCRATCH_UMSK, 0xff);
0c88a02e 1667
b90ca986
CK		 1668 for (i = 0; i < 3; ++i) {
1669 uint32_t rb_cntl;
1670 uint64_t addr;
0c88a02e 1671
b90ca986
CK		 1672 /* Set ring buffer size */
1673 ring = &rdev->ring[ridx[i]];
b72a8925
DV		 1674 rb_cntl = order_base_2(ring->ring_size / 8);
1675 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
0c88a02e 1676#ifdef __BIG_ENDIAN
b90ca986 1677 rb_cntl |= BUF_SWAP_32BIT;
0c88a02e 1678#endif
b90ca986 1679 WREG32(cp_rb_cntl[i], rb_cntl);
0c88a02e 1680
48fc7f7e 1681 /* set the wb address whether it's enabled or not */
b90ca986
CK		 1682 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1683 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1684 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1685 }
0c88a02e 1686
b90ca986
CK		 1687 /* set the rb base addr, this causes an internal reset of ALL rings */
1688 for (i = 0; i < 3; ++i) {
1689 ring = &rdev->ring[ridx[i]];
1690 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1691 }
0c88a02e 1692
b90ca986
CK		 1693 for (i = 0; i < 3; ++i) {
1694 /* Initialize the ring buffer's read and write pointers */
1695 ring = &rdev->ring[ridx[i]];
1696 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
0c88a02e 1697
ff212f25
CK		 1698 ring->wptr = 0;
1699 WREG32(cp_rb_rptr[i], 0);
ea31bf69 1700 WREG32(cp_rb_wptr[i], ring->wptr);
0c88a02e 1701
b90ca986
CK		 1702 mdelay(1);
1703 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1704 }
0c88a02e
AD		 1705
1706 /* start the rings */
1707 cayman_cp_start(rdev);
e32eb50d
CK		 1708 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1709 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1710 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e 1711 /* this only test cp0 */
f712812e 1712 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
0c88a02e 1713 if (r) {
e32eb50d
CK		 1714 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1715 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1716 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
0c88a02e
AD		 1717 return r;
1718 }
1719
50efa51a
AD		 1720 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1721 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1722
0c88a02e
AD		 1723 return 0;
1724}
1725
2483b4ea 1726u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
271d6fed 1727{
168757ea 1728 u32 reset_mask = 0;
187e3593 1729 u32 tmp;
271d6fed 1730
168757ea
AD		 1731 /* GRBM_STATUS */
1732 tmp = RREG32(GRBM_STATUS);
1733 if (tmp & (PA_BUSY | SC_BUSY |
1734 SH_BUSY | SX_BUSY |
1735 TA_BUSY | VGT_BUSY |
1736 DB_BUSY | CB_BUSY |
1737 GDS_BUSY | SPI_BUSY |
1738 IA_BUSY | IA_BUSY_NO_DMA))
1739 reset_mask |= RADEON_RESET_GFX;
1740
1741 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1742 CP_BUSY | CP_COHERENCY_BUSY))
1743 reset_mask |= RADEON_RESET_CP;
1744
1745 if (tmp & GRBM_EE_BUSY)
1746 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1747
1748 /* DMA_STATUS_REG 0 */
1749 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1750 if (!(tmp & DMA_IDLE))
1751 reset_mask |= RADEON_RESET_DMA;
1752
1753 /* DMA_STATUS_REG 1 */
1754 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1755 if (!(tmp & DMA_IDLE))
1756 reset_mask |= RADEON_RESET_DMA1;
1757
1758 /* SRBM_STATUS2 */
1759 tmp = RREG32(SRBM_STATUS2);
1760 if (tmp & DMA_BUSY)
1761 reset_mask |= RADEON_RESET_DMA;
1762
1763 if (tmp & DMA1_BUSY)
1764 reset_mask |= RADEON_RESET_DMA1;
1765
1766 /* SRBM_STATUS */
1767 tmp = RREG32(SRBM_STATUS);
1768 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1769 reset_mask |= RADEON_RESET_RLC;
1770
1771 if (tmp & IH_BUSY)
1772 reset_mask |= RADEON_RESET_IH;
1773
1774 if (tmp & SEM_BUSY)
1775 reset_mask |= RADEON_RESET_SEM;
1776
1777 if (tmp & GRBM_RQ_PENDING)
1778 reset_mask |= RADEON_RESET_GRBM;
1779
1780 if (tmp & VMC_BUSY)
1781 reset_mask |= RADEON_RESET_VMC;
19fc42ed 1782
168757ea
AD		 1783 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1784 MCC_BUSY | MCD_BUSY))
1785 reset_mask |= RADEON_RESET_MC;
1786
1787 if (evergreen_is_display_hung(rdev))
1788 reset_mask |= RADEON_RESET_DISPLAY;
1789
1790 /* VM_L2_STATUS */
1791 tmp = RREG32(VM_L2_STATUS);
1792 if (tmp & L2_BUSY)
1793 reset_mask |= RADEON_RESET_VMC;
1794
d808fc88
AD		 1795 /* Skip MC reset as it's mostly likely not hung, just busy */
1796 if (reset_mask & RADEON_RESET_MC) {
1797 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1798 reset_mask &= ~RADEON_RESET_MC;
1799 }
1800
168757ea
AD		 1801 return reset_mask;
1802}
1803
1804static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1805{
1806 struct evergreen_mc_save save;
1807 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1808 u32 tmp;
19fc42ed 1809
271d6fed 1810 if (reset_mask == 0)
168757ea 1811 return;
271d6fed
AD		 1812
1813 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1814
187e3593 1815 evergreen_print_gpu_status_regs(rdev);
271d6fed
AD		 1816 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1817 RREG32(0x14F8));
1818 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1819 RREG32(0x14D8));
1820 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1821 RREG32(0x14FC));
1822 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1823 RREG32(0x14DC));
1824
187e3593
AD		 1825 /* Disable CP parsing/prefetching */
1826 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1827
1828 if (reset_mask & RADEON_RESET_DMA) {
1829 /* dma0 */
1830 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1831 tmp &= ~DMA_RB_ENABLE;
1832 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
168757ea 1833 }
187e3593 1834
168757ea 1835 if (reset_mask & RADEON_RESET_DMA1) {
187e3593
AD		 1836 /* dma1 */
1837 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1838 tmp &= ~DMA_RB_ENABLE;
1839 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1840 }
1841
90fb8779
AD		 1842 udelay(50);
1843
1844 evergreen_mc_stop(rdev, &save);
1845 if (evergreen_mc_wait_for_idle(rdev)) {
1846 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1847 }
1848
187e3593
AD		 1849 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1850 grbm_soft_reset = SOFT_RESET_CB |
1851 SOFT_RESET_DB |
1852 SOFT_RESET_GDS |
1853 SOFT_RESET_PA |
1854 SOFT_RESET_SC |
1855 SOFT_RESET_SPI |
1856 SOFT_RESET_SH |
1857 SOFT_RESET_SX |
1858 SOFT_RESET_TC |
1859 SOFT_RESET_TA |
1860 SOFT_RESET_VGT |
1861 SOFT_RESET_IA;
1862 }
1863
1864 if (reset_mask & RADEON_RESET_CP) {
1865 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1866
1867 srbm_soft_reset |= SOFT_RESET_GRBM;
1868 }
271d6fed
AD		 1869
1870 if (reset_mask & RADEON_RESET_DMA)
168757ea
AD		 1871 srbm_soft_reset |= SOFT_RESET_DMA;
1872
1873 if (reset_mask & RADEON_RESET_DMA1)
1874 srbm_soft_reset |= SOFT_RESET_DMA1;
1875
1876 if (reset_mask & RADEON_RESET_DISPLAY)
1877 srbm_soft_reset |= SOFT_RESET_DC;
1878
1879 if (reset_mask & RADEON_RESET_RLC)
1880 srbm_soft_reset |= SOFT_RESET_RLC;
1881
1882 if (reset_mask & RADEON_RESET_SEM)
1883 srbm_soft_reset |= SOFT_RESET_SEM;
1884
1885 if (reset_mask & RADEON_RESET_IH)
1886 srbm_soft_reset |= SOFT_RESET_IH;
1887
1888 if (reset_mask & RADEON_RESET_GRBM)
1889 srbm_soft_reset |= SOFT_RESET_GRBM;
1890
1891 if (reset_mask & RADEON_RESET_VMC)
1892 srbm_soft_reset |= SOFT_RESET_VMC;
1893
24178ec4
AD		 1894 if (!(rdev->flags & RADEON_IS_IGP)) {
1895 if (reset_mask & RADEON_RESET_MC)
1896 srbm_soft_reset |= SOFT_RESET_MC;
1897 }
187e3593
AD		 1898
1899 if (grbm_soft_reset) {
1900 tmp = RREG32(GRBM_SOFT_RESET);
1901 tmp |= grbm_soft_reset;
1902 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1903 WREG32(GRBM_SOFT_RESET, tmp);
1904 tmp = RREG32(GRBM_SOFT_RESET);
1905
1906 udelay(50);
1907
1908 tmp &= ~grbm_soft_reset;
1909 WREG32(GRBM_SOFT_RESET, tmp);
1910 tmp = RREG32(GRBM_SOFT_RESET);
1911 }
1912
1913 if (srbm_soft_reset) {
1914 tmp = RREG32(SRBM_SOFT_RESET);
1915 tmp |= srbm_soft_reset;
1916 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1917 WREG32(SRBM_SOFT_RESET, tmp);
1918 tmp = RREG32(SRBM_SOFT_RESET);
1919
1920 udelay(50);
1921
1922 tmp &= ~srbm_soft_reset;
1923 WREG32(SRBM_SOFT_RESET, tmp);
1924 tmp = RREG32(SRBM_SOFT_RESET);
1925 }
271d6fed
AD		 1926
1927 /* Wait a little for things to settle down */
1928 udelay(50);
1929
b9952a8a 1930 evergreen_mc_resume(rdev, &save);
187e3593
AD		 1931 udelay(50);
1932
187e3593 1933 evergreen_print_gpu_status_regs(rdev);
b9952a8a
AD		 1934}
1935
1936int cayman_asic_reset(struct radeon_device *rdev)
1937{
168757ea
AD		 1938 u32 reset_mask;
1939
1940 reset_mask = cayman_gpu_check_soft_reset(rdev);
1941
1942 if (reset_mask)
1943 r600_set_bios_scratch_engine_hung(rdev, true);
1944
1945 cayman_gpu_soft_reset(rdev, reset_mask);
1946
1947 reset_mask = cayman_gpu_check_soft_reset(rdev);
1948
b5470b03
AD		 1949 if (reset_mask)
1950 evergreen_gpu_pci_config_reset(rdev);
1951
1952 r600_set_bios_scratch_engine_hung(rdev, false);
168757ea
AD		 1953
1954 return 0;
b9952a8a
AD		 1955}
1956
123bc183
AD		 1957/**
1958 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1959 *
1960 * @rdev: radeon_device pointer
1961 * @ring: radeon_ring structure holding ring information
1962 *
1963 * Check if the GFX engine is locked up.
1964 * Returns true if the engine appears to be locked up, false if not.
1965 */
1966bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1967{
1968 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1969
1970 if (!(reset_mask & (RADEON_RESET_GFX |
1971 RADEON_RESET_COMPUTE |
1972 RADEON_RESET_CP))) {
ff212f25 1973 radeon_ring_lockup_update(rdev, ring);
123bc183
AD		 1974 return false;
1975 }
123bc183
AD		 1976 return radeon_ring_test_lockup(rdev, ring);
1977}
1978
755d819e
AD		 1979static int cayman_startup(struct radeon_device *rdev)
1980{
e32eb50d 1981 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 1982 int r;
1983
b07759bf
IH		 1984 /* enable pcie gen2 link */
1985 evergreen_pcie_gen2_enable(rdev);
f52382d7
AD		 1986 /* enable aspm */
1987 evergreen_program_aspm(rdev);
b07759bf 1988
e5903d39
AD		 1989 /* scratch needs to be initialized before MC */
1990 r = r600_vram_scratch_init(rdev);
1991 if (r)
1992 return r;
1993
6fab3feb
AD		 1994 evergreen_mc_program(rdev);
1995
6c7bccea 1996 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
c420c745 1997 r = ni_mc_load_microcode(rdev);
755d819e 1998 if (r) {
c420c745 1999 DRM_ERROR("Failed to load MC firmware!\n");
755d819e
AD		 2000 return r;
2001 }
2002 }
755d819e 2003
755d819e
AD		 2004 r = cayman_pcie_gart_enable(rdev);
2005 if (r)
2006 return r;
2007 cayman_gpu_init(rdev);
2008
c420c745
AD		 2009 /* allocate rlc buffers */
2010 if (rdev->flags & RADEON_IS_IGP) {
2948f5e6 2011 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1fd11777
AD		 2012 rdev->rlc.reg_list_size =
2013 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
2948f5e6
AD		 2014 rdev->rlc.cs_data = cayman_cs_data;
2015 r = sumo_rlc_init(rdev);
c420c745
AD		 2016 if (r) {
2017 DRM_ERROR("Failed to init rlc BOs!\n");
2018 return r;
2019 }
2020 }
2021
755d819e
AD		 2022 /* allocate wb buffer */
2023 r = radeon_wb_init(rdev);
2024 if (r)
2025 return r;
2026
30eb77f4
JG		 2027 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2028 if (r) {
2029 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2030 return r;
2031 }
2032
e409b128 2033 r = uvd_v2_2_resume(rdev);
f2ba57b5
CK		 2034 if (!r) {
2035 r = radeon_fence_driver_start_ring(rdev,
2036 R600_RING_TYPE_UVD_INDEX);
2037 if (r)
2038 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
2039 }
2040 if (r)
2041 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2042
30eb77f4
JG		 2043 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2044 if (r) {
2045 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2046 return r;
2047 }
2048
2049 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2050 if (r) {
2051 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2052 return r;
2053 }
2054
f60cbd11
AD		 2055 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2056 if (r) {
2057 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2058 return r;
2059 }
2060
2061 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2062 if (r) {
2063 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2064 return r;
2065 }
2066
755d819e 2067 /* Enable IRQ */
e49f3959
AH		 2068 if (!rdev->irq.installed) {
2069 r = radeon_irq_kms_init(rdev);
2070 if (r)
2071 return r;
2072 }
2073
755d819e
AD		 2074 r = r600_irq_init(rdev);
2075 if (r) {
2076 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2077 radeon_irq_kms_fini(rdev);
2078 return r;
2079 }
2080 evergreen_irq_set(rdev);
2081
e32eb50d 2082 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 2083 RADEON_CP_PACKET2);
755d819e
AD		 2084 if (r)
2085 return r;
f60cbd11
AD		 2086
2087 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2088 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2e1e6dad 2089 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
f60cbd11
AD		 2090 if (r)
2091 return r;
2092
2093 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2094 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2e1e6dad 2095 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
f60cbd11
AD		 2096 if (r)
2097 return r;
2098
755d819e
AD		 2099 r = cayman_cp_load_microcode(rdev);
2100 if (r)
2101 return r;
2102 r = cayman_cp_resume(rdev);
2103 if (r)
2104 return r;
2105
f60cbd11
AD		 2106 r = cayman_dma_resume(rdev);
2107 if (r)
2108 return r;
2109
f2ba57b5
CK		 2110 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2111 if (ring->ring_size) {
02c9f7fa 2112 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2e1e6dad 2113 RADEON_CP_PACKET2);
f2ba57b5 2114 if (!r)
e409b128 2115 r = uvd_v1_0_init(rdev);
f2ba57b5
CK		 2116 if (r)
2117 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2118 }
2119
2898c348
CK		 2120 r = radeon_ib_pool_init(rdev);
2121 if (r) {
2122 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 2123 return r;
2898c348 2124 }
b15ba512 2125
c6105f24
CK		 2126 r = radeon_vm_manager_init(rdev);
2127 if (r) {
2128 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
721604a1 2129 return r;
c6105f24 2130 }
721604a1 2131
bfc1f97d
SG		 2132 r = radeon_audio_init(rdev);
2133 if (r)
2134 return r;
6b53a050 2135
755d819e
AD		 2136 return 0;
2137}
2138
2139int cayman_resume(struct radeon_device *rdev)
2140{
2141 int r;
2142
2143 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2144 * posting will perform necessary task to bring back GPU into good
2145 * shape.
2146 */
2147 /* post card */
2148 atom_asic_init(rdev->mode_info.atom_context);
2149
a2c96a21
AD		 2150 /* init golden registers */
2151 ni_init_golden_registers(rdev);
2152
bc6a6295
AD		 2153 if (rdev->pm.pm_method == PM_METHOD_DPM)
2154 radeon_pm_resume(rdev);
6c7bccea 2155
b15ba512 2156 rdev->accel_working = true;
755d819e
AD		 2157 r = cayman_startup(rdev);
2158 if (r) {
2159 DRM_ERROR("cayman startup failed on resume\n");
6b7746e8 2160 rdev->accel_working = false;
755d819e
AD		 2161 return r;
2162 }
755d819e 2163 return r;
755d819e
AD		 2164}
2165
2166int cayman_suspend(struct radeon_device *rdev)
2167{
6c7bccea 2168 radeon_pm_suspend(rdev);
7991d665 2169 radeon_audio_fini(rdev);
fa3daf9a 2170 radeon_vm_manager_fini(rdev);
755d819e 2171 cayman_cp_enable(rdev, false);
f60cbd11 2172 cayman_dma_stop(rdev);
e409b128 2173 uvd_v1_0_fini(rdev);
f2ba57b5 2174 radeon_uvd_suspend(rdev);
755d819e
AD		 2175 evergreen_irq_suspend(rdev);
2176 radeon_wb_disable(rdev);
2177 cayman_pcie_gart_disable(rdev);
755d819e
AD		 2178 return 0;
2179}
2180
2181/* Plan is to move initialization in that function and use
2182 * helper function so that radeon_device_init pretty much
2183 * do nothing more than calling asic specific function. This
2184 * should also allow to remove a bunch of callback function
2185 * like vram_info.
2186 */
2187int cayman_init(struct radeon_device *rdev)
2188{
e32eb50d 2189 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
755d819e
AD		 2190 int r;
2191
755d819e
AD		 2192 /* Read BIOS */
2193 if (!radeon_get_bios(rdev)) {
2194 if (ASIC_IS_AVIVO(rdev))
2195 return -EINVAL;
2196 }
2197 /* Must be an ATOMBIOS */
2198 if (!rdev->is_atom_bios) {
2199 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2200 return -EINVAL;
2201 }
2202 r = radeon_atombios_init(rdev);
2203 if (r)
2204 return r;
2205
2206 /* Post card if necessary */
2207 if (!radeon_card_posted(rdev)) {
2208 if (!rdev->bios) {
2209 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2210 return -EINVAL;
2211 }
2212 DRM_INFO("GPU not posted. posting now...\n");
2213 atom_asic_init(rdev->mode_info.atom_context);
2214 }
a2c96a21
AD		 2215 /* init golden registers */
2216 ni_init_golden_registers(rdev);
755d819e
AD		 2217 /* Initialize scratch registers */
2218 r600_scratch_init(rdev);
2219 /* Initialize surface registers */
2220 radeon_surface_init(rdev);
2221 /* Initialize clocks */
2222 radeon_get_clock_info(rdev->ddev);
2223 /* Fence driver */
30eb77f4 2224 r = radeon_fence_driver_init(rdev);
755d819e
AD		 2225 if (r)
2226 return r;
2227 /* initialize memory controller */
2228 r = evergreen_mc_init(rdev);
2229 if (r)
2230 return r;
2231 /* Memory manager */
2232 r = radeon_bo_init(rdev);
2233 if (r)
2234 return r;
2235
01ac8794
AD		 2236 if (rdev->flags & RADEON_IS_IGP) {
2237 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2238 r = ni_init_microcode(rdev);
2239 if (r) {
2240 DRM_ERROR("Failed to load firmware!\n");
2241 return r;
2242 }
2243 }
2244 } else {
2245 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2246 r = ni_init_microcode(rdev);
2247 if (r) {
2248 DRM_ERROR("Failed to load firmware!\n");
2249 return r;
2250 }
2251 }
2252 }
2253
6c7bccea
AD		 2254 /* Initialize power management */
2255 radeon_pm_init(rdev);
2256
e32eb50d
CK		 2257 ring->ring_obj = NULL;
2258 r600_ring_init(rdev, ring, 1024 * 1024);
755d819e 2259
f60cbd11
AD		 2260 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2261 ring->ring_obj = NULL;
2262 r600_ring_init(rdev, ring, 64 * 1024);
2263
2264 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2265 ring->ring_obj = NULL;
2266 r600_ring_init(rdev, ring, 64 * 1024);
2267
f2ba57b5
CK		 2268 r = radeon_uvd_init(rdev);
2269 if (!r) {
2270 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2271 ring->ring_obj = NULL;
2272 r600_ring_init(rdev, ring, 4096);
2273 }
2274
755d819e
AD		 2275 rdev->ih.ring_obj = NULL;
2276 r600_ih_ring_init(rdev, 64 * 1024);
2277
2278 r = r600_pcie_gart_init(rdev);
2279 if (r)
2280 return r;
2281
2282 rdev->accel_working = true;
2283 r = cayman_startup(rdev);
2284 if (r) {
2285 dev_err(rdev->dev, "disabling GPU acceleration\n");
2286 cayman_cp_fini(rdev);
f60cbd11 2287 cayman_dma_fini(rdev);
755d819e 2288 r600_irq_fini(rdev);
c420c745 2289 if (rdev->flags & RADEON_IS_IGP)
2948f5e6 2290 sumo_rlc_fini(rdev);
755d819e 2291 radeon_wb_fini(rdev);
2898c348 2292 radeon_ib_pool_fini(rdev);
721604a1 2293 radeon_vm_manager_fini(rdev);
755d819e
AD		 2294 radeon_irq_kms_fini(rdev);
2295 cayman_pcie_gart_fini(rdev);
2296 rdev->accel_working = false;
2297 }
755d819e
AD		 2298
2299 /* Don't start up if the MC ucode is missing.
2300 * The default clocks and voltages before the MC ucode
2301 * is loaded are not suffient for advanced operations.
c420c745
AD		 2302 *
2303 * We can skip this check for TN, because there is no MC
2304 * ucode.
755d819e 2305 */
c420c745 2306 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
755d819e
AD		 2307 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2308 return -EINVAL;
2309 }
2310
2311 return 0;
2312}
2313
2314void cayman_fini(struct radeon_device *rdev)
2315{
6c7bccea 2316 radeon_pm_fini(rdev);
755d819e 2317 cayman_cp_fini(rdev);
f60cbd11 2318 cayman_dma_fini(rdev);
755d819e 2319 r600_irq_fini(rdev);
c420c745 2320 if (rdev->flags & RADEON_IS_IGP)
2948f5e6 2321 sumo_rlc_fini(rdev);
755d819e 2322 radeon_wb_fini(rdev);
721604a1 2323 radeon_vm_manager_fini(rdev);
2898c348 2324 radeon_ib_pool_fini(rdev);
755d819e 2325 radeon_irq_kms_fini(rdev);
e409b128 2326 uvd_v1_0_fini(rdev);
f2ba57b5 2327 radeon_uvd_fini(rdev);
755d819e 2328 cayman_pcie_gart_fini(rdev);
16cdf04d 2329 r600_vram_scratch_fini(rdev);
755d819e
AD		 2330 radeon_gem_fini(rdev);
2331 radeon_fence_driver_fini(rdev);
2332 radeon_bo_fini(rdev);
2333 radeon_atombios_fini(rdev);
2334 kfree(rdev->bios);
2335 rdev->bios = NULL;
2336}
2337
721604a1
JG		 2338/*
2339 * vm
2340 */
2341int cayman_vm_init(struct radeon_device *rdev)
2342{
2343 /* number of VMs */
2344 rdev->vm_manager.nvm = 8;
2345 /* base offset of vram pages */
e71270fd
AD		 2346 if (rdev->flags & RADEON_IS_IGP) {
2347 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2348 tmp <<= 22;
2349 rdev->vm_manager.vram_base_offset = tmp;
2350 } else
2351 rdev->vm_manager.vram_base_offset = 0;
721604a1
JG		 2352 return 0;
2353}
2354
2355void cayman_vm_fini(struct radeon_device *rdev)
2356{
2357}
2358
54e2e49c
AD		 2359/**
2360 * cayman_vm_decode_fault - print human readable fault info
2361 *
2362 * @rdev: radeon_device pointer
2363 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2364 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2365 *
2366 * Print human readable fault information (cayman/TN).
2367 */
2368void cayman_vm_decode_fault(struct radeon_device *rdev,
2369 u32 status, u32 addr)
2370{
2371 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2372 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2373 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2374 char *block;
2375
2376 switch (mc_id) {
2377 case 32:
2378 case 16:
2379 case 96:
2380 case 80:
2381 case 160:
2382 case 144:
2383 case 224:
2384 case 208:
2385 block = "CB";
2386 break;
2387 case 33:
2388 case 17:
2389 case 97:
2390 case 81:
2391 case 161:
2392 case 145:
2393 case 225:
2394 case 209:
2395 block = "CB_FMASK";
2396 break;
2397 case 34:
2398 case 18:
2399 case 98:
2400 case 82:
2401 case 162:
2402 case 146:
2403 case 226:
2404 case 210:
2405 block = "CB_CMASK";
2406 break;
2407 case 35:
2408 case 19:
2409 case 99:
2410 case 83:
2411 case 163:
2412 case 147:
2413 case 227:
2414 case 211:
2415 block = "CB_IMMED";
2416 break;
2417 case 36:
2418 case 20:
2419 case 100:
2420 case 84:
2421 case 164:
2422 case 148:
2423 case 228:
2424 case 212:
2425 block = "DB";
2426 break;
2427 case 37:
2428 case 21:
2429 case 101:
2430 case 85:
2431 case 165:
2432 case 149:
2433 case 229:
2434 case 213:
2435 block = "DB_HTILE";
2436 break;
2437 case 38:
2438 case 22:
2439 case 102:
2440 case 86:
2441 case 166:
2442 case 150:
2443 case 230:
2444 case 214:
2445 block = "SX";
2446 break;
2447 case 39:
2448 case 23:
2449 case 103:
2450 case 87:
2451 case 167:
2452 case 151:
2453 case 231:
2454 case 215:
2455 block = "DB_STEN";
2456 break;
2457 case 40:
2458 case 24:
2459 case 104:
2460 case 88:
2461 case 232:
2462 case 216:
2463 case 168:
2464 case 152:
2465 block = "TC_TFETCH";
2466 break;
2467 case 41:
2468 case 25:
2469 case 105:
2470 case 89:
2471 case 233:
2472 case 217:
2473 case 169:
2474 case 153:
2475 block = "TC_VFETCH";
2476 break;
2477 case 42:
2478 case 26:
2479 case 106:
2480 case 90:
2481 case 234:
2482 case 218:
2483 case 170:
2484 case 154:
2485 block = "VC";
2486 break;
2487 case 112:
2488 block = "CP";
2489 break;
2490 case 113:
2491 case 114:
2492 block = "SH";
2493 break;
2494 case 115:
2495 block = "VGT";
2496 break;
2497 case 178:
2498 block = "IH";
2499 break;
2500 case 51:
2501 block = "RLC";
2502 break;
2503 case 55:
2504 block = "DMA";
2505 break;
2506 case 56:
2507 block = "HDP";
2508 break;
2509 default:
2510 block = "unknown";
2511 break;
2512 }
2513
2514 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2515 protections, vmid, addr,
2516 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2517 block, mc_id);
2518}
2519
7a083293
AD		 2520/**
2521 * cayman_vm_flush - vm flush using the CP
2522 *
2523 * @rdev: radeon_device pointer
2524 *
2525 * Update the page table base and flush the VM TLB
2526 * using the CP (cayman-si).
2527 */
faffaf62
CK		 2528void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
2529 unsigned vm_id, uint64_t pd_addr)
721604a1 2530{
faffaf62
CK		 2531 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
2532 radeon_ring_write(ring, pd_addr >> 12);
ee60e29f 2533
9b40e5d8
CK		 2534 /* flush hdp cache */
2535 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2536 radeon_ring_write(ring, 0x1);
2537
2538 /* bits 0-7 are the VM contexts0-7 */
2539 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
faffaf62 2540 radeon_ring_write(ring, 1 << vm_id);
58f8cf56 2541
cbfc35b9
AD		 2542 /* wait for the invalidate to complete */
2543 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2544 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2545 WAIT_REG_MEM_ENGINE(0))); /* me */
2546 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2547 radeon_ring_write(ring, 0);
2548 radeon_ring_write(ring, 0); /* ref */
2549 radeon_ring_write(ring, 0); /* mask */
2550 radeon_ring_write(ring, 0x20); /* poll interval */
2551
58f8cf56
CK		 2552 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2553 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2554 radeon_ring_write(ring, 0x0);
721604a1 2555}
Linux 6.x block layer and io_uring tree(s)