projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 0fcdb61e AD |
1 | /* |
| 2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | * Authors: Alex Deucher | |
| 23 | */ | |
| 24 | #ifndef EVERGREEND_H | |
| 25 | #define EVERGREEND_H | |
| 26 | ||
| 32fcdbf4 AD |
27 | #define EVERGREEN_MAX_SH_GPRS 256 |
| 28 | #define EVERGREEN_MAX_TEMP_GPRS 16 | |
| 29 | #define EVERGREEN_MAX_SH_THREADS 256 | |
| 30 | #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 | |
| 31 | #define EVERGREEN_MAX_FRC_EOV_CNT 16384 | |
| 32 | #define EVERGREEN_MAX_BACKENDS 8 | |
| 33 | #define EVERGREEN_MAX_BACKENDS_MASK 0xFF | |
| 34 | #define EVERGREEN_MAX_SIMDS 16 | |
| 35 | #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF | |
| 36 | #define EVERGREEN_MAX_PIPES 8 | |
| 37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF | |
| 38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF | |
| 39 | ||
| 416a2bd2 AD |
40 | #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
| 41 | #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 | |
| 42 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 | |
| 43 | #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
| 44 | #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
| 45 | #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
| 46 | #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 | |
| 47 | #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 | |
| bd25f078 JG |
48 | #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
| 49 | #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
| 416a2bd2 | 50 | |
| dc50ba7f AD |
51 | /* pm registers */ |
| 52 | #define SMC_MSG 0x20c | |
| 53 | #define HOST_SMC_MSG(x) ((x) << 0) | |
| 54 | #define HOST_SMC_MSG_MASK (0xff << 0) | |
| 55 | #define HOST_SMC_MSG_SHIFT 0 | |
| 56 | #define HOST_SMC_RESP(x) ((x) << 8) | |
| 57 | #define HOST_SMC_RESP_MASK (0xff << 8) | |
| 58 | #define HOST_SMC_RESP_SHIFT 8 | |
| 59 | #define SMC_HOST_MSG(x) ((x) << 16) | |
| 60 | #define SMC_HOST_MSG_MASK (0xff << 16) | |
| 61 | #define SMC_HOST_MSG_SHIFT 16 | |
| 62 | #define SMC_HOST_RESP(x) ((x) << 24) | |
| 63 | #define SMC_HOST_RESP_MASK (0xff << 24) | |
| 64 | #define SMC_HOST_RESP_SHIFT 24 | |
| 65 | ||
| 66 | #define DCCG_DISP_SLOW_SELECT_REG 0x4fc | |
| 67 | #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) | |
| 68 | #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) | |
| 69 | #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 | |
| 70 | #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) | |
| 71 | #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) | |
| 72 | #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 | |
| 73 | ||
| 74 | #define CG_SPLL_FUNC_CNTL 0x600 | |
| 75 | #define SPLL_RESET (1 << 0) | |
| 76 | #define SPLL_SLEEP (1 << 1) | |
| 77 | #define SPLL_BYPASS_EN (1 << 3) | |
| 78 | #define SPLL_REF_DIV(x) ((x) << 4) | |
| 79 | #define SPLL_REF_DIV_MASK (0x3f << 4) | |
| 80 | #define SPLL_PDIV_A(x) ((x) << 20) | |
| 81 | #define SPLL_PDIV_A_MASK (0x7f << 20) | |
| 82 | #define CG_SPLL_FUNC_CNTL_2 0x604 | |
| 83 | #define SCLK_MUX_SEL(x) ((x) << 0) | |
| 84 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | |
| 85 | #define CG_SPLL_FUNC_CNTL_3 0x608 | |
| 86 | #define SPLL_FB_DIV(x) ((x) << 0) | |
| 87 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | |
| 88 | #define SPLL_DITHEN (1 << 28) | |
| 89 | ||
| 90 | #define MPLL_CNTL_MODE 0x61c | |
| 91 | # define SS_SSEN (1 << 24) | |
| 92 | # define SS_DSMODE_EN (1 << 25) | |
| 93 | ||
| 94 | #define MPLL_AD_FUNC_CNTL 0x624 | |
| 95 | #define CLKF(x) ((x) << 0) | |
| 96 | #define CLKF_MASK (0x7f << 0) | |
| 97 | #define CLKR(x) ((x) << 7) | |
| 98 | #define CLKR_MASK (0x1f << 7) | |
| 99 | #define CLKFRAC(x) ((x) << 12) | |
| 100 | #define CLKFRAC_MASK (0x1f << 12) | |
| 101 | #define YCLK_POST_DIV(x) ((x) << 17) | |
| 102 | #define YCLK_POST_DIV_MASK (3 << 17) | |
| 103 | #define IBIAS(x) ((x) << 20) | |
| 104 | #define IBIAS_MASK (0x3ff << 20) | |
| 105 | #define RESET (1 << 30) | |
| 106 | #define PDNB (1 << 31) | |
| 107 | #define MPLL_AD_FUNC_CNTL_2 0x628 | |
| 108 | #define BYPASS (1 << 19) | |
| 109 | #define BIAS_GEN_PDNB (1 << 24) | |
| 110 | #define RESET_EN (1 << 25) | |
| 111 | #define VCO_MODE (1 << 29) | |
| 112 | #define MPLL_DQ_FUNC_CNTL 0x62c | |
| 113 | #define MPLL_DQ_FUNC_CNTL_2 0x630 | |
| 114 | ||
| 115 | #define GENERAL_PWRMGT 0x63c | |
| 116 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
| 117 | # define STATIC_PM_EN (1 << 1) | |
| 118 | # define THERMAL_PROTECTION_DIS (1 << 2) | |
| 119 | # define THERMAL_PROTECTION_TYPE (1 << 3) | |
| 120 | # define ENABLE_GEN2PCIE (1 << 4) | |
| 121 | # define ENABLE_GEN2XSP (1 << 5) | |
| 122 | # define SW_SMIO_INDEX(x) ((x) << 6) | |
| 123 | # define SW_SMIO_INDEX_MASK (3 << 6) | |
| 124 | # define SW_SMIO_INDEX_SHIFT 6 | |
| 125 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
| 126 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
| 127 | # define VOLT_PWRMGT_EN (1 << 10) | |
| 128 | # define BACKBIAS_PAD_EN (1 << 18) | |
| 129 | # define BACKBIAS_VALUE (1 << 19) | |
| 130 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
| 131 | # define AC_DC_SW (1 << 24) | |
| 132 | ||
| 133 | #define SCLK_PWRMGT_CNTL 0x644 | |
| 134 | # define SCLK_PWRMGT_OFF (1 << 0) | |
| 135 | # define SCLK_LOW_D1 (1 << 1) | |
| 136 | # define FIR_RESET (1 << 4) | |
| 137 | # define FIR_FORCE_TREND_SEL (1 << 5) | |
| 138 | # define FIR_TREND_MODE (1 << 6) | |
| 139 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | |
| 140 | # define GFX_CLK_FORCE_ON (1 << 8) | |
| 141 | # define GFX_CLK_REQUEST_OFF (1 << 9) | |
| 142 | # define GFX_CLK_FORCE_OFF (1 << 10) | |
| 143 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) | |
| 144 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) | |
| 145 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) | |
| 146 | # define DYN_LIGHT_SLEEP_EN (1 << 14) | |
| 147 | #define MCLK_PWRMGT_CNTL 0x648 | |
| 148 | # define DLL_SPEED(x) ((x) << 0) | |
| 149 | # define DLL_SPEED_MASK (0x1f << 0) | |
| 150 | # define MPLL_PWRMGT_OFF (1 << 5) | |
| 151 | # define DLL_READY (1 << 6) | |
| 152 | # define MC_INT_CNTL (1 << 7) | |
| 153 | # define MRDCKA0_PDNB (1 << 8) | |
| 154 | # define MRDCKA1_PDNB (1 << 9) | |
| 155 | # define MRDCKB0_PDNB (1 << 10) | |
| 156 | # define MRDCKB1_PDNB (1 << 11) | |
| 157 | # define MRDCKC0_PDNB (1 << 12) | |
| 158 | # define MRDCKC1_PDNB (1 << 13) | |
| 159 | # define MRDCKD0_PDNB (1 << 14) | |
| 160 | # define MRDCKD1_PDNB (1 << 15) | |
| 161 | # define MRDCKA0_RESET (1 << 16) | |
| 162 | # define MRDCKA1_RESET (1 << 17) | |
| 163 | # define MRDCKB0_RESET (1 << 18) | |
| 164 | # define MRDCKB1_RESET (1 << 19) | |
| 165 | # define MRDCKC0_RESET (1 << 20) | |
| 166 | # define MRDCKC1_RESET (1 << 21) | |
| 167 | # define MRDCKD0_RESET (1 << 22) | |
| 168 | # define MRDCKD1_RESET (1 << 23) | |
| 169 | # define DLL_READY_READ (1 << 24) | |
| 170 | # define USE_DISPLAY_GAP (1 << 25) | |
| 171 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) | |
| 172 | # define MPLL_TURNOFF_D2 (1 << 28) | |
| 173 | #define DLL_CNTL 0x64c | |
| 174 | # define MRDCKA0_BYPASS (1 << 24) | |
| 175 | # define MRDCKA1_BYPASS (1 << 25) | |
| 176 | # define MRDCKB0_BYPASS (1 << 26) | |
| 177 | # define MRDCKB1_BYPASS (1 << 27) | |
| 178 | # define MRDCKC0_BYPASS (1 << 28) | |
| 179 | # define MRDCKC1_BYPASS (1 << 29) | |
| 180 | # define MRDCKD0_BYPASS (1 << 30) | |
| 181 | # define MRDCKD1_BYPASS (1 << 31) | |
| 182 | ||
| 183 | #define CG_AT 0x6d4 | |
| 184 | # define CG_R(x) ((x) << 0) | |
| 185 | # define CG_R_MASK (0xffff << 0) | |
| 186 | # define CG_L(x) ((x) << 16) | |
| 187 | # define CG_L_MASK (0xffff << 16) | |
| 188 | ||
| 189 | #define CG_DISPLAY_GAP_CNTL 0x714 | |
| 190 | # define DISP1_GAP(x) ((x) << 0) | |
| 191 | # define DISP1_GAP_MASK (3 << 0) | |
| 192 | # define DISP2_GAP(x) ((x) << 2) | |
| 193 | # define DISP2_GAP_MASK (3 << 2) | |
| 194 | # define VBI_TIMER_COUNT(x) ((x) << 4) | |
| 195 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) | |
| 196 | # define VBI_TIMER_UNIT(x) ((x) << 20) | |
| 197 | # define VBI_TIMER_UNIT_MASK (7 << 20) | |
| 198 | # define DISP1_GAP_MCHG(x) ((x) << 24) | |
| 199 | # define DISP1_GAP_MCHG_MASK (3 << 24) | |
| 200 | # define DISP2_GAP_MCHG(x) ((x) << 26) | |
| 201 | # define DISP2_GAP_MCHG_MASK (3 << 26) | |
| 202 | ||
| 203 | #define CG_BIF_REQ_AND_RSP 0x7f4 | |
| 204 | #define CG_CLIENT_REQ(x) ((x) << 0) | |
| 205 | #define CG_CLIENT_REQ_MASK (0xff << 0) | |
| 206 | #define CG_CLIENT_REQ_SHIFT 0 | |
| 207 | #define CG_CLIENT_RESP(x) ((x) << 8) | |
| 208 | #define CG_CLIENT_RESP_MASK (0xff << 8) | |
| 209 | #define CG_CLIENT_RESP_SHIFT 8 | |
| 210 | #define CLIENT_CG_REQ(x) ((x) << 16) | |
| 211 | #define CLIENT_CG_REQ_MASK (0xff << 16) | |
| 212 | #define CLIENT_CG_REQ_SHIFT 16 | |
| 213 | #define CLIENT_CG_RESP(x) ((x) << 24) | |
| 214 | #define CLIENT_CG_RESP_MASK (0xff << 24) | |
| 215 | #define CLIENT_CG_RESP_SHIFT 24 | |
| 216 | ||
| 217 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 | |
| 218 | #define SSEN (1 << 0) | |
| 219 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 | |
| 220 | ||
| 221 | #define MPLL_SS1 0x85c | |
| 222 | #define CLKV(x) ((x) << 0) | |
| 223 | #define CLKV_MASK (0x3ffffff << 0) | |
| 224 | #define MPLL_SS2 0x860 | |
| 225 | #define CLKS(x) ((x) << 0) | |
| 226 | #define CLKS_MASK (0xfff << 0) | |
| 227 | ||
| 228 | #define CG_IND_ADDR 0x8f8 | |
| 229 | #define CG_IND_DATA 0x8fc | |
| 230 | /* CGIND regs */ | |
| 231 | #define CG_CGTT_LOCAL_0 0x00 | |
| 232 | #define CG_CGTT_LOCAL_1 0x01 | |
| 233 | #define CG_CGTT_LOCAL_2 0x02 | |
| 234 | #define CG_CGTT_LOCAL_3 0x03 | |
| 235 | #define CG_CGLS_TILE_0 0x20 | |
| 236 | #define CG_CGLS_TILE_1 0x21 | |
| 237 | #define CG_CGLS_TILE_2 0x22 | |
| 238 | #define CG_CGLS_TILE_3 0x23 | |
| 239 | #define CG_CGLS_TILE_4 0x24 | |
| 240 | #define CG_CGLS_TILE_5 0x25 | |
| 241 | #define CG_CGLS_TILE_6 0x26 | |
| 242 | #define CG_CGLS_TILE_7 0x27 | |
| 243 | #define CG_CGLS_TILE_8 0x28 | |
| 244 | #define CG_CGLS_TILE_9 0x29 | |
| 245 | #define CG_CGLS_TILE_10 0x2a | |
| 246 | #define CG_CGLS_TILE_11 0x2b | |
| 247 | ||
| 248 | #define VM_L2_CG 0x15c0 | |
| 249 | ||
| 250 | #define MC_CONFIG 0x2000 | |
| 251 | ||
| 252 | #define MC_CONFIG_MCD 0x20a0 | |
| 253 | #define MC_CG_CONFIG_MCD 0x20a4 | |
| 254 | #define MC_RD_ENABLE_MCD(x) ((x) << 8) | |
| 255 | #define MC_RD_ENABLE_MCD_MASK (7 << 8) | |
| 256 | ||
| 257 | #define MC_HUB_MISC_HUB_CG 0x20b8 | |
| 258 | #define MC_HUB_MISC_VM_CG 0x20bc | |
| 259 | #define MC_HUB_MISC_SIP_CG 0x20c0 | |
| 260 | ||
| 261 | #define MC_XPB_CLK_GAT 0x2478 | |
| 262 | ||
| 263 | #define MC_CG_CONFIG 0x25bc | |
| 264 | #define MC_RD_ENABLE(x) ((x) << 4) | |
| 265 | #define MC_RD_ENABLE_MASK (3 << 4) | |
| 266 | ||
| 267 | #define MC_CITF_MISC_RD_CG 0x2648 | |
| 268 | #define MC_CITF_MISC_WR_CG 0x264c | |
| 269 | #define MC_CITF_MISC_VM_CG 0x2650 | |
| 270 | # define MEM_LS_ENABLE (1 << 19) | |
| 271 | ||
| 272 | #define MC_ARB_BURST_TIME 0x2808 | |
| 273 | #define STATE0(x) ((x) << 0) | |
| 274 | #define STATE0_MASK (0x1f << 0) | |
| 275 | #define STATE1(x) ((x) << 5) | |
| 276 | #define STATE1_MASK (0x1f << 5) | |
| 277 | #define STATE2(x) ((x) << 10) | |
| 278 | #define STATE2_MASK (0x1f << 10) | |
| 279 | #define STATE3(x) ((x) << 15) | |
| 280 | #define STATE3_MASK (0x1f << 15) | |
| 281 | ||
| 282 | #define MC_SEQ_RAS_TIMING 0x28a0 | |
| 283 | #define MC_SEQ_CAS_TIMING 0x28a4 | |
| 284 | #define MC_SEQ_MISC_TIMING 0x28a8 | |
| 285 | #define MC_SEQ_MISC_TIMING2 0x28ac | |
| 286 | ||
| 287 | #define MC_SEQ_RD_CTL_D0 0x28b4 | |
| 288 | #define MC_SEQ_RD_CTL_D1 0x28b8 | |
| 289 | #define MC_SEQ_WR_CTL_D0 0x28bc | |
| 290 | #define MC_SEQ_WR_CTL_D1 0x28c0 | |
| 291 | ||
| 292 | #define MC_SEQ_STATUS_M 0x29f4 | |
| 293 | # define PMG_PWRSTATE (1 << 16) | |
| 294 | ||
| 295 | #define MC_SEQ_MISC1 0x2a04 | |
| 296 | #define MC_SEQ_RESERVE_M 0x2a08 | |
| 297 | #define MC_PMG_CMD_EMRS 0x2a0c | |
| 298 | ||
| 299 | #define MC_SEQ_MISC3 0x2a2c | |
| 300 | ||
| 301 | #define MC_SEQ_MISC5 0x2a54 | |
| 302 | #define MC_SEQ_MISC6 0x2a58 | |
| 303 | ||
| 304 | #define MC_SEQ_MISC7 0x2a64 | |
| 305 | ||
| 306 | #define MC_SEQ_CG 0x2a68 | |
| 307 | #define CG_SEQ_REQ(x) ((x) << 0) | |
| 308 | #define CG_SEQ_REQ_MASK (0xff << 0) | |
| 309 | #define CG_SEQ_REQ_SHIFT 0 | |
| 310 | #define CG_SEQ_RESP(x) ((x) << 8) | |
| 311 | #define CG_SEQ_RESP_MASK (0xff << 8) | |
| 312 | #define CG_SEQ_RESP_SHIFT 8 | |
| 313 | #define SEQ_CG_REQ(x) ((x) << 16) | |
| 314 | #define SEQ_CG_REQ_MASK (0xff << 16) | |
| 315 | #define SEQ_CG_REQ_SHIFT 16 | |
| 316 | #define SEQ_CG_RESP(x) ((x) << 24) | |
| 317 | #define SEQ_CG_RESP_MASK (0xff << 24) | |
| 318 | #define SEQ_CG_RESP_SHIFT 24 | |
| 319 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c | |
| 320 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 | |
| 321 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 | |
| 322 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 | |
| 323 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c | |
| 324 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 | |
| 325 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 | |
| 326 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 | |
| 327 | ||
| 328 | #define MC_PMG_CMD_MRS 0x2aac | |
| 329 | ||
| 330 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c | |
| 331 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 | |
| 332 | ||
| 333 | #define MC_PMG_CMD_MRS1 0x2b44 | |
| 334 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 | |
| 335 | ||
| 336 | #define CGTS_SM_CTRL_REG 0x9150 | |
| 337 | ||
| 0fcdb61e AD |
338 | /* Registers */ |
| 339 | ||
| 32fcdbf4 AD |
340 | #define RCU_IND_INDEX 0x100 |
| 341 | #define RCU_IND_DATA 0x104 | |
| 342 | ||
| a8b4925c AD |
343 | /* discrete uvd clocks */ |
| 344 | #define CG_UPLL_FUNC_CNTL 0x718 | |
| 345 | # define UPLL_RESET_MASK 0x00000001 | |
| 346 | # define UPLL_SLEEP_MASK 0x00000002 | |
| 347 | # define UPLL_BYPASS_EN_MASK 0x00000004 | |
| 348 | # define UPLL_CTLREQ_MASK 0x00000008 | |
| 092fbc4c | 349 | # define UPLL_REF_DIV_MASK 0x003F0000 |
| a8b4925c AD |
350 | # define UPLL_VCO_MODE_MASK 0x00000200 |
| 351 | # define UPLL_CTLACK_MASK 0x40000000 | |
| 352 | # define UPLL_CTLACK2_MASK 0x80000000 | |
| 353 | #define CG_UPLL_FUNC_CNTL_2 0x71c | |
| 354 | # define UPLL_PDIV_A(x) ((x) << 0) | |
| 355 | # define UPLL_PDIV_A_MASK 0x0000007F | |
| 356 | # define UPLL_PDIV_B(x) ((x) << 8) | |
| 357 | # define UPLL_PDIV_B_MASK 0x00007F00 | |
| 358 | # define VCLK_SRC_SEL(x) ((x) << 20) | |
| 359 | # define VCLK_SRC_SEL_MASK 0x01F00000 | |
| 360 | # define DCLK_SRC_SEL(x) ((x) << 25) | |
| 361 | # define DCLK_SRC_SEL_MASK 0x3E000000 | |
| 362 | #define CG_UPLL_FUNC_CNTL_3 0x720 | |
| 363 | # define UPLL_FB_DIV(x) ((x) << 0) | |
| 364 | # define UPLL_FB_DIV_MASK 0x01FFFFFF | |
| 365 | #define CG_UPLL_FUNC_CNTL_4 0x854 | |
| 366 | # define UPLL_SPARE_ISPARE9 0x00020000 | |
| 367 | #define CG_UPLL_SPREAD_SPECTRUM 0x79c | |
| 368 | # define SSEN_MASK 0x00000001 | |
| 369 | ||
| 23d33ba3 AD |
370 | /* fusion uvd clocks */ |
| 371 | #define CG_DCLK_CNTL 0x610 | |
| 372 | # define DCLK_DIVIDER_MASK 0x7f | |
| 373 | # define DCLK_DIR_CNTL_EN (1 << 8) | |
| 374 | #define CG_DCLK_STATUS 0x614 | |
| 375 | # define DCLK_STATUS (1 << 0) | |
| 376 | #define CG_VCLK_CNTL 0x618 | |
| 377 | #define CG_VCLK_STATUS 0x61c | |
| 378 | #define CG_SCRATCH1 0x820 | |
| 379 | ||
| 2948f5e6 AD |
380 | #define RLC_CNTL 0x3f00 |
| 381 | # define RLC_ENABLE (1 << 0) | |
| 382 | # define GFX_POWER_GATING_ENABLE (1 << 7) | |
| 383 | # define GFX_POWER_GATING_SRC (1 << 8) | |
| 8ba10463 AD |
384 | # define DYN_PER_SIMD_PG_ENABLE (1 << 27) |
| 385 | # define LB_CNT_SPIM_ACTIVE (1 << 30) | |
| 386 | # define LOAD_BALANCE_ENABLE (1 << 31) | |
| 387 | ||
| 2948f5e6 AD |
388 | #define RLC_HB_BASE 0x3f10 |
| 389 | #define RLC_HB_CNTL 0x3f0c | |
| 390 | #define RLC_HB_RPTR 0x3f20 | |
| 391 | #define RLC_HB_WPTR 0x3f1c | |
| 392 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 | |
| 393 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 | |
| 394 | #define RLC_MC_CNTL 0x3f44 | |
| 395 | #define RLC_UCODE_CNTL 0x3f48 | |
| 396 | #define RLC_UCODE_ADDR 0x3f2c | |
| 397 | #define RLC_UCODE_DATA 0x3f30 | |
| 398 | ||
| 399 | /* new for TN */ | |
| 400 | #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 | |
| 8ba10463 AD |
401 | #define TN_RLC_LB_CNTR_MAX 0x3f14 |
| 402 | #define TN_RLC_LB_CNTR_INIT 0x3f18 | |
| 2948f5e6 | 403 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
| 8ba10463 AD |
404 | #define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4 |
| 405 | #define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8 | |
| 406 | #define TN_RLC_LB_PARAMS 0x3fec | |
| 2948f5e6 | 407 | |
| 32fcdbf4 AD |
408 | #define GRBM_GFX_INDEX 0x802C |
| 409 | #define INSTANCE_INDEX(x) ((x) << 0) | |
| 410 | #define SE_INDEX(x) ((x) << 16) | |
| 411 | #define INSTANCE_BROADCAST_WRITES (1 << 30) | |
| 412 | #define SE_BROADCAST_WRITES (1 << 31) | |
| 413 | #define RLC_GFX_INDEX 0x3fC4 | |
| 414 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 | |
| 415 | #define WRITE_DIS (1 << 0) | |
| 416 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
| 417 | #define BACKEND_DISABLE(x) ((x) << 16) | |
| 418 | #define GB_ADDR_CONFIG 0x98F8 | |
| 419 | #define NUM_PIPES(x) ((x) << 0) | |
| 416a2bd2 | 420 | #define NUM_PIPES_MASK 0x0000000f |
| 32fcdbf4 AD |
421 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
| 422 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) | |
| 423 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | |
| 424 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) | |
| 425 | #define NUM_GPUS(x) ((x) << 20) | |
| 426 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) | |
| 427 | #define ROW_SIZE(x) ((x) << 28) | |
| 428 | #define GB_BACKEND_MAP 0x98FC | |
| 429 | #define DMIF_ADDR_CONFIG 0xBD4 | |
| 430 | #define HDP_ADDR_CONFIG 0x2F48 | |
| f25a5c63 AD |
431 | #define HDP_MISC_CNTL 0x2F4C |
| 432 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | |
| 32fcdbf4 | 433 | |
| 0fcdb61e | 434 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
| 32fcdbf4 | 435 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
| 0fcdb61e AD |
436 | |
| 437 | #define CGTS_SYS_TCC_DISABLE 0x3F90 | |
| 438 | #define CGTS_TCC_DISABLE 0x9148 | |
| 439 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 | |
| 440 | #define CGTS_USER_TCC_DISABLE 0x914C | |
| 441 | ||
| 442 | #define CONFIG_MEMSIZE 0x5428 | |
| 443 | ||
| 62444b74 AD |
444 | #define BIF_FB_EN 0x5490 |
| 445 | #define FB_READ_EN (1 << 0) | |
| 446 | #define FB_WRITE_EN (1 << 1) | |
| 447 | ||
| 860fe2f0 AD |
448 | #define CP_STRMOUT_CNTL 0x84FC |
| 449 | ||
| 450 | #define CP_COHER_CNTL 0x85F0 | |
| 451 | #define CP_COHER_SIZE 0x85F4 | |
| dd220a00 | 452 | #define CP_COHER_BASE 0x85F8 |
| 440a7cd8 JG |
453 | #define CP_STALLED_STAT1 0x8674 |
| 454 | #define CP_STALLED_STAT2 0x8678 | |
| 455 | #define CP_BUSY_STAT 0x867C | |
| 456 | #define CP_STAT 0x8680 | |
| 32fcdbf4 AD |
457 | #define CP_ME_CNTL 0x86D8 |
| 458 | #define CP_ME_HALT (1 << 28) | |
| 459 | #define CP_PFP_HALT (1 << 26) | |
| 0fcdb61e AD |
460 | #define CP_ME_RAM_DATA 0xC160 |
| 461 | #define CP_ME_RAM_RADDR 0xC158 | |
| 462 | #define CP_ME_RAM_WADDR 0xC15C | |
| 463 | #define CP_MEQ_THRESHOLDS 0x8764 | |
| 464 | #define STQ_SPLIT(x) ((x) << 0) | |
| 465 | #define CP_PERFMON_CNTL 0x87FC | |
| 466 | #define CP_PFP_UCODE_ADDR 0xC150 | |
| 467 | #define CP_PFP_UCODE_DATA 0xC154 | |
| 468 | #define CP_QUEUE_THRESHOLDS 0x8760 | |
| 469 | #define ROQ_IB1_START(x) ((x) << 0) | |
| 470 | #define ROQ_IB2_START(x) ((x) << 8) | |
| fe251e2f | 471 | #define CP_RB_BASE 0xC100 |
| 0fcdb61e | 472 | #define CP_RB_CNTL 0xC104 |
| 32fcdbf4 AD |
473 | #define RB_BUFSZ(x) ((x) << 0) |
| 474 | #define RB_BLKSZ(x) ((x) << 8) | |
| 475 | #define RB_NO_UPDATE (1 << 27) | |
| 476 | #define RB_RPTR_WR_ENA (1 << 31) | |
| 0fcdb61e AD |
477 | #define BUF_SWAP_32BIT (2 << 16) |
| 478 | #define CP_RB_RPTR 0x8700 | |
| 479 | #define CP_RB_RPTR_ADDR 0xC10C | |
| 0f234f5f | 480 | #define RB_RPTR_SWAP(x) ((x) << 0) |
| 0fcdb61e AD |
481 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
| 482 | #define CP_RB_RPTR_WR 0xC108 | |
| 483 | #define CP_RB_WPTR 0xC114 | |
| 484 | #define CP_RB_WPTR_ADDR 0xC118 | |
| 485 | #define CP_RB_WPTR_ADDR_HI 0xC11C | |
| 486 | #define CP_RB_WPTR_DELAY 0x8704 | |
| 487 | #define CP_SEM_WAIT_TIMER 0x85BC | |
| 11ef3f1f | 488 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 |
| fe251e2f | 489 | #define CP_DEBUG 0xC1FC |
| 0fcdb61e | 490 | |
| 3a2a67aa AD |
491 | /* Audio clocks */ |
| 492 | #define DCCG_AUDIO_DTO_SOURCE 0x05ac | |
| 493 | # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ | |
| 494 | # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ | |
| 495 | ||
| 496 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 | |
| 497 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 | |
| 498 | #define DCCG_AUDIO_DTO0_LOAD 0x05b8 | |
| 499 | #define DCCG_AUDIO_DTO0_CNTL 0x05bc | |
| 1518dd8e AD |
500 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) |
| 501 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 | |
| 502 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 | |
| 3a2a67aa AD |
503 | |
| 504 | #define DCCG_AUDIO_DTO1_PHASE 0x05c0 | |
| 505 | #define DCCG_AUDIO_DTO1_MODULE 0x05c4 | |
| 506 | #define DCCG_AUDIO_DTO1_LOAD 0x05c8 | |
| 507 | #define DCCG_AUDIO_DTO1_CNTL 0x05cc | |
| 508 | ||
| 509 | /* DCE 4.0 AFMT */ | |
| 510 | #define HDMI_CONTROL 0x7030 | |
| 511 | # define HDMI_KEEPOUT_MODE (1 << 0) | |
| 512 | # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ | |
| 513 | # define HDMI_ERROR_ACK (1 << 8) | |
| 514 | # define HDMI_ERROR_MASK (1 << 9) | |
| 515 | # define HDMI_DEEP_COLOR_ENABLE (1 << 24) | |
| 516 | # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) | |
| 517 | # define HDMI_24BIT_DEEP_COLOR 0 | |
| 518 | # define HDMI_30BIT_DEEP_COLOR 1 | |
| 519 | # define HDMI_36BIT_DEEP_COLOR 2 | |
| 520 | #define HDMI_STATUS 0x7034 | |
| 521 | # define HDMI_ACTIVE_AVMUTE (1 << 0) | |
| 522 | # define HDMI_AUDIO_PACKET_ERROR (1 << 16) | |
| 523 | # define HDMI_VBI_PACKET_ERROR (1 << 20) | |
| 524 | #define HDMI_AUDIO_PACKET_CONTROL 0x7038 | |
| 525 | # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) | |
| 526 | # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) | |
| 527 | #define HDMI_ACR_PACKET_CONTROL 0x703c | |
| 528 | # define HDMI_ACR_SEND (1 << 0) | |
| 529 | # define HDMI_ACR_CONT (1 << 1) | |
| 530 | # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) | |
| 531 | # define HDMI_ACR_HW 0 | |
| 532 | # define HDMI_ACR_32 1 | |
| 533 | # define HDMI_ACR_44 2 | |
| 534 | # define HDMI_ACR_48 3 | |
| 535 | # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ | |
| 536 | # define HDMI_ACR_AUTO_SEND (1 << 12) | |
| 537 | # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) | |
| 538 | # define HDMI_ACR_X1 1 | |
| 539 | # define HDMI_ACR_X2 2 | |
| 540 | # define HDMI_ACR_X4 4 | |
| 541 | # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) | |
| 542 | #define HDMI_VBI_PACKET_CONTROL 0x7040 | |
| 543 | # define HDMI_NULL_SEND (1 << 0) | |
| 544 | # define HDMI_GC_SEND (1 << 4) | |
| 545 | # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ | |
| 546 | #define HDMI_INFOFRAME_CONTROL0 0x7044 | |
| 547 | # define HDMI_AVI_INFO_SEND (1 << 0) | |
| 548 | # define HDMI_AVI_INFO_CONT (1 << 1) | |
| 549 | # define HDMI_AUDIO_INFO_SEND (1 << 4) | |
| 550 | # define HDMI_AUDIO_INFO_CONT (1 << 5) | |
| 551 | # define HDMI_MPEG_INFO_SEND (1 << 8) | |
| 552 | # define HDMI_MPEG_INFO_CONT (1 << 9) | |
| 553 | #define HDMI_INFOFRAME_CONTROL1 0x7048 | |
| 554 | # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) | |
| d3418eac | 555 | # define HDMI_AVI_INFO_LINE_MASK (0x3f << 0) |
| 3a2a67aa AD |
556 | # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
| 557 | # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) | |
| 558 | #define HDMI_GENERIC_PACKET_CONTROL 0x704c | |
| 559 | # define HDMI_GENERIC0_SEND (1 << 0) | |
| 560 | # define HDMI_GENERIC0_CONT (1 << 1) | |
| 561 | # define HDMI_GENERIC1_SEND (1 << 4) | |
| 562 | # define HDMI_GENERIC1_CONT (1 << 5) | |
| 563 | # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) | |
| 564 | # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) | |
| 565 | #define HDMI_GC 0x7058 | |
| 566 | # define HDMI_GC_AVMUTE (1 << 0) | |
| 567 | # define HDMI_GC_AVMUTE_CONT (1 << 2) | |
| 568 | #define AFMT_AUDIO_PACKET_CONTROL2 0x705c | |
| 569 | # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) | |
| 570 | # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) | |
| 571 | # define AFMT_60958_CS_SOURCE (1 << 4) | |
| 572 | # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) | |
| 573 | # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) | |
| 574 | #define AFMT_AVI_INFO0 0x7084 | |
| 575 | # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
| 576 | # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) | |
| 577 | # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) | |
| 578 | # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) | |
| 579 | # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) | |
| 580 | # define AFMT_AVI_INFO_Y_RGB 0 | |
| 581 | # define AFMT_AVI_INFO_Y_YCBCR422 1 | |
| 582 | # define AFMT_AVI_INFO_Y_YCBCR444 2 | |
| 583 | # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) | |
| 584 | # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) | |
| 585 | # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) | |
| 586 | # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) | |
| 587 | # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) | |
| 588 | # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) | |
| 589 | # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) | |
| 590 | # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) | |
| 591 | # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) | |
| 592 | # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) | |
| 593 | #define AFMT_AVI_INFO1 0x7088 | |
| 594 | # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ | |
| 595 | # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ | |
| 596 | # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) | |
| 597 | # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) | |
| 598 | # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) | |
| 599 | #define AFMT_AVI_INFO2 0x708c | |
| 600 | # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) | |
| 601 | # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) | |
| 602 | #define AFMT_AVI_INFO3 0x7090 | |
| 603 | # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) | |
| 604 | # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) | |
| 605 | #define AFMT_MPEG_INFO0 0x7094 | |
| 606 | # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
| 607 | # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) | |
| 608 | # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) | |
| 609 | # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) | |
| 610 | #define AFMT_MPEG_INFO1 0x7098 | |
| 611 | # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) | |
| 612 | # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) | |
| 613 | # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) | |
| 614 | #define AFMT_GENERIC0_HDR 0x709c | |
| 615 | #define AFMT_GENERIC0_0 0x70a0 | |
| 616 | #define AFMT_GENERIC0_1 0x70a4 | |
| 617 | #define AFMT_GENERIC0_2 0x70a8 | |
| 618 | #define AFMT_GENERIC0_3 0x70ac | |
| 619 | #define AFMT_GENERIC0_4 0x70b0 | |
| 620 | #define AFMT_GENERIC0_5 0x70b4 | |
| 621 | #define AFMT_GENERIC0_6 0x70b8 | |
| 622 | #define AFMT_GENERIC1_HDR 0x70bc | |
| 623 | #define AFMT_GENERIC1_0 0x70c0 | |
| 624 | #define AFMT_GENERIC1_1 0x70c4 | |
| 625 | #define AFMT_GENERIC1_2 0x70c8 | |
| 626 | #define AFMT_GENERIC1_3 0x70cc | |
| 627 | #define AFMT_GENERIC1_4 0x70d0 | |
| 628 | #define AFMT_GENERIC1_5 0x70d4 | |
| 629 | #define AFMT_GENERIC1_6 0x70d8 | |
| 630 | #define HDMI_ACR_32_0 0x70dc | |
| 631 | # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) | |
| 632 | #define HDMI_ACR_32_1 0x70e0 | |
| 633 | # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) | |
| 634 | #define HDMI_ACR_44_0 0x70e4 | |
| 635 | # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) | |
| 636 | #define HDMI_ACR_44_1 0x70e8 | |
| 637 | # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) | |
| 638 | #define HDMI_ACR_48_0 0x70ec | |
| 639 | # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) | |
| 640 | #define HDMI_ACR_48_1 0x70f0 | |
| 641 | # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) | |
| 642 | #define HDMI_ACR_STATUS_0 0x70f4 | |
| 643 | #define HDMI_ACR_STATUS_1 0x70f8 | |
| 644 | #define AFMT_AUDIO_INFO0 0x70fc | |
| 645 | # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
| 646 | # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) | |
| 647 | # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) | |
| 648 | # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) | |
| 649 | # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) | |
| 650 | #define AFMT_AUDIO_INFO1 0x7100 | |
| 651 | # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) | |
| 652 | # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) | |
| 653 | # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) | |
| 654 | # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) | |
| 655 | # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) | |
| 656 | #define AFMT_60958_0 0x7104 | |
| 657 | # define AFMT_60958_CS_A(x) (((x) & 1) << 0) | |
| 658 | # define AFMT_60958_CS_B(x) (((x) & 1) << 1) | |
| 659 | # define AFMT_60958_CS_C(x) (((x) & 1) << 2) | |
| 660 | # define AFMT_60958_CS_D(x) (((x) & 3) << 3) | |
| 661 | # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) | |
| 662 | # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) | |
| 663 | # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) | |
| 664 | # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) | |
| 665 | # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) | |
| 666 | # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) | |
| 667 | #define AFMT_60958_1 0x7108 | |
| 668 | # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) | |
| 669 | # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) | |
| 670 | # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) | |
| 671 | # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) | |
| 672 | # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) | |
| 673 | #define AFMT_AUDIO_CRC_CONTROL 0x710c | |
| 674 | # define AFMT_AUDIO_CRC_EN (1 << 0) | |
| 675 | #define AFMT_RAMP_CONTROL0 0x7110 | |
| 676 | # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) | |
| 677 | # define AFMT_RAMP_DATA_SIGN (1 << 31) | |
| 678 | #define AFMT_RAMP_CONTROL1 0x7114 | |
| 679 | # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) | |
| 680 | # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) | |
| 681 | #define AFMT_RAMP_CONTROL2 0x7118 | |
| 682 | # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) | |
| 683 | #define AFMT_RAMP_CONTROL3 0x711c | |
| 684 | # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) | |
| 685 | #define AFMT_60958_2 0x7120 | |
| 686 | # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) | |
| 687 | # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) | |
| 688 | # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) | |
| 689 | # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) | |
| 690 | # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) | |
| 691 | # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) | |
| 692 | #define AFMT_STATUS 0x7128 | |
| 693 | # define AFMT_AUDIO_ENABLE (1 << 4) | |
| 694 | # define AFMT_AUDIO_HBR_ENABLE (1 << 8) | |
| 695 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) | |
| 696 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) | |
| 697 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) | |
| 698 | #define AFMT_AUDIO_PACKET_CONTROL 0x712c | |
| 699 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) | |
| 700 | # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ | |
| 701 | # define AFMT_AUDIO_TEST_EN (1 << 12) | |
| 702 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) | |
| 703 | # define AFMT_60958_CS_UPDATE (1 << 26) | |
| 704 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) | |
| 705 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) | |
| 706 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) | |
| 707 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) | |
| 708 | #define AFMT_VBI_PACKET_CONTROL 0x7130 | |
| 709 | # define AFMT_GENERIC0_UPDATE (1 << 2) | |
| 710 | #define AFMT_INFOFRAME_CONTROL0 0x7134 | |
| 711 | # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ | |
| 712 | # define AFMT_AUDIO_INFO_UPDATE (1 << 7) | |
| 713 | # define AFMT_MPEG_INFO_UPDATE (1 << 10) | |
| 714 | #define AFMT_GENERIC0_7 0x7138 | |
| 0fcdb61e | 715 | |
| 1c4c3a99 | 716 | /* DCE4/5 ELD audio interface */ |
| ba7def4f AD |
717 | #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78 |
| 718 | #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) | |
| 719 | #define SPEAKER_ALLOCATION_MASK (0x7f << 0) | |
| 720 | #define SPEAKER_ALLOCATION_SHIFT 0 | |
| 721 | #define HDMI_CONNECTION (1 << 16) | |
| 722 | #define DP_CONNECTION (1 << 17) | |
| 723 | ||
| 1c4c3a99 AD |
724 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ |
| 725 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ | |
| 726 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ | |
| 727 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ | |
| 728 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ | |
| 729 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ | |
| 730 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ | |
| 731 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ | |
| 732 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ | |
| 733 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ | |
| 734 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ | |
| 735 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ | |
| 736 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ | |
| 737 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ | |
| 738 | # define MAX_CHANNELS(x) (((x) & 0x7) << 0) | |
| 739 | /* max channels minus one. 7 = 8 channels */ | |
| 740 | # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) | |
| 741 | # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) | |
| 742 | # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ | |
| 743 | /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO | |
| 744 | * bit0 = 32 kHz | |
| 745 | * bit1 = 44.1 kHz | |
| 746 | * bit2 = 48 kHz | |
| 747 | * bit3 = 88.2 kHz | |
| 748 | * bit4 = 96 kHz | |
| 749 | * bit5 = 176.4 kHz | |
| 750 | * bit6 = 192 kHz | |
| 751 | */ | |
| 752 | ||
| 753 | #define AZ_HOT_PLUG_CONTROL 0x5e78 | |
| 754 | # define AZ_FORCE_CODEC_WAKE (1 << 0) | |
| 755 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) | |
| 756 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) | |
| 757 | # define PIN2_JACK_DETECTION_ENABLE (1 << 6) | |
| 758 | # define PIN3_JACK_DETECTION_ENABLE (1 << 7) | |
| 759 | # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) | |
| 760 | # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) | |
| 761 | # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) | |
| 762 | # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) | |
| 763 | # define CODEC_HOT_PLUG_ENABLE (1 << 12) | |
| 764 | # define PIN0_AUDIO_ENABLED (1 << 24) | |
| 765 | # define PIN1_AUDIO_ENABLED (1 << 25) | |
| 766 | # define PIN2_AUDIO_ENABLED (1 << 26) | |
| 767 | # define PIN3_AUDIO_ENABLED (1 << 27) | |
| 768 | # define AUDIO_ENABLED (1 << 31) | |
| 769 | ||
| 770 | ||
| 0fcdb61e AD |
771 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
| 772 | #define INACTIVE_QD_PIPES(x) ((x) << 8) | |
| 773 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 | |
| 774 | #define INACTIVE_SIMDS(x) ((x) << 16) | |
| 775 | #define INACTIVE_SIMDS_MASK 0x00FF0000 | |
| 776 | ||
| 777 | #define GRBM_CNTL 0x8000 | |
| 778 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
| 779 | #define GRBM_SOFT_RESET 0x8020 | |
| 747943ea AD |
780 | #define SOFT_RESET_CP (1 << 0) |
| 781 | #define SOFT_RESET_CB (1 << 1) | |
| 782 | #define SOFT_RESET_DB (1 << 3) | |
| 783 | #define SOFT_RESET_PA (1 << 5) | |
| 784 | #define SOFT_RESET_SC (1 << 6) | |
| 785 | #define SOFT_RESET_SPI (1 << 8) | |
| 786 | #define SOFT_RESET_SH (1 << 9) | |
| 787 | #define SOFT_RESET_SX (1 << 10) | |
| 788 | #define SOFT_RESET_TC (1 << 11) | |
| 789 | #define SOFT_RESET_TA (1 << 12) | |
| 790 | #define SOFT_RESET_VC (1 << 13) | |
| 791 | #define SOFT_RESET_VGT (1 << 14) | |
| 792 | ||
| 0fcdb61e AD |
793 | #define GRBM_STATUS 0x8010 |
| 794 | #define CMDFIFO_AVAIL_MASK 0x0000000F | |
| 747943ea AD |
795 | #define SRBM_RQ_PENDING (1 << 5) |
| 796 | #define CF_RQ_PENDING (1 << 7) | |
| 797 | #define PF_RQ_PENDING (1 << 8) | |
| 798 | #define GRBM_EE_BUSY (1 << 10) | |
| 799 | #define SX_CLEAN (1 << 11) | |
| 800 | #define DB_CLEAN (1 << 12) | |
| 801 | #define CB_CLEAN (1 << 13) | |
| 802 | #define TA_BUSY (1 << 14) | |
| 803 | #define VGT_BUSY_NO_DMA (1 << 16) | |
| 804 | #define VGT_BUSY (1 << 17) | |
| 805 | #define SX_BUSY (1 << 20) | |
| 806 | #define SH_BUSY (1 << 21) | |
| 807 | #define SPI_BUSY (1 << 22) | |
| 808 | #define SC_BUSY (1 << 24) | |
| 809 | #define PA_BUSY (1 << 25) | |
| 810 | #define DB_BUSY (1 << 26) | |
| 811 | #define CP_COHERENCY_BUSY (1 << 28) | |
| 812 | #define CP_BUSY (1 << 29) | |
| 813 | #define CB_BUSY (1 << 30) | |
| 814 | #define GUI_ACTIVE (1 << 31) | |
| 815 | #define GRBM_STATUS_SE0 0x8014 | |
| 816 | #define GRBM_STATUS_SE1 0x8018 | |
| 817 | #define SE_SX_CLEAN (1 << 0) | |
| 818 | #define SE_DB_CLEAN (1 << 1) | |
| 819 | #define SE_CB_CLEAN (1 << 2) | |
| 820 | #define SE_TA_BUSY (1 << 25) | |
| 821 | #define SE_SX_BUSY (1 << 26) | |
| 822 | #define SE_SPI_BUSY (1 << 27) | |
| 823 | #define SE_SH_BUSY (1 << 28) | |
| 824 | #define SE_SC_BUSY (1 << 29) | |
| 825 | #define SE_DB_BUSY (1 << 30) | |
| 826 | #define SE_CB_BUSY (1 << 31) | |
| e33df25f | 827 | /* evergreen */ |
| 67b3f823 AD |
828 | #define CG_THERMAL_CTRL 0x72c |
| 829 | #define TOFFSET_MASK 0x00003FE0 | |
| 830 | #define TOFFSET_SHIFT 5 | |
| dc50ba7f AD |
831 | #define DIG_THERM_DPM(x) ((x) << 14) |
| 832 | #define DIG_THERM_DPM_MASK 0x003FC000 | |
| 833 | #define DIG_THERM_DPM_SHIFT 14 | |
| 834 | ||
| 835 | #define CG_THERMAL_INT 0x734 | |
| 836 | #define DIG_THERM_INTH(x) ((x) << 8) | |
| 837 | #define DIG_THERM_INTH_MASK 0x0000FF00 | |
| 838 | #define DIG_THERM_INTH_SHIFT 8 | |
| 839 | #define DIG_THERM_INTL(x) ((x) << 16) | |
| 840 | #define DIG_THERM_INTL_MASK 0x00FF0000 | |
| 841 | #define DIG_THERM_INTL_SHIFT 16 | |
| 842 | #define THERM_INT_MASK_HIGH (1 << 24) | |
| 843 | #define THERM_INT_MASK_LOW (1 << 25) | |
| 844 | ||
| d70229f7 AD |
845 | #define TN_CG_THERMAL_INT_CTRL 0x738 |
| 846 | #define TN_DIG_THERM_INTH(x) ((x) << 0) | |
| 847 | #define TN_DIG_THERM_INTH_MASK 0x000000FF | |
| 848 | #define TN_DIG_THERM_INTH_SHIFT 0 | |
| 849 | #define TN_DIG_THERM_INTL(x) ((x) << 8) | |
| 850 | #define TN_DIG_THERM_INTL_MASK 0x0000FF00 | |
| 851 | #define TN_DIG_THERM_INTL_SHIFT 8 | |
| 852 | #define TN_THERM_INT_MASK_HIGH (1 << 24) | |
| 853 | #define TN_THERM_INT_MASK_LOW (1 << 25) | |
| 854 | ||
| 21a8122a AD |
855 | #define CG_MULT_THERMAL_STATUS 0x740 |
| 856 | #define ASIC_T(x) ((x) << 16) | |
| 67b3f823 | 857 | #define ASIC_T_MASK 0x07FF0000 |
| 21a8122a | 858 | #define ASIC_T_SHIFT 16 |
| 67b3f823 AD |
859 | #define CG_TS0_STATUS 0x760 |
| 860 | #define TS0_ADC_DOUT_MASK 0x000003FF | |
| 861 | #define TS0_ADC_DOUT_SHIFT 0 | |
| dc50ba7f | 862 | |
| e33df25f AD |
863 | /* APU */ |
| 864 | #define CG_THERMAL_STATUS 0x678 | |
| 21a8122a | 865 | |
| 0fcdb61e AD |
866 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 867 | #define HDP_NONSURFACE_BASE 0x2C04 | |
| 868 | #define HDP_NONSURFACE_INFO 0x2C08 | |
| 869 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
| 6f2f48a9 | 870 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
| 0fcdb61e AD |
871 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
| 872 | #define HDP_TILING_CONFIG 0x2F3C | |
| 873 | ||
| 874 | #define MC_SHARED_CHMAP 0x2004 | |
| 875 | #define NOOFCHAN_SHIFT 12 | |
| 876 | #define NOOFCHAN_MASK 0x00003000 | |
| 9535ab73 | 877 | #define MC_SHARED_CHREMAP 0x2008 |
| 0fcdb61e | 878 | |
| 62444b74 AD |
879 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
| 880 | #define BLACKOUT_MODE_MASK 0x00000007 | |
| 881 | ||
| 0fcdb61e AD |
882 | #define MC_ARB_RAMCFG 0x2760 |
| 883 | #define NOOFBANK_SHIFT 0 | |
| 884 | #define NOOFBANK_MASK 0x00000003 | |
| 885 | #define NOOFRANK_SHIFT 2 | |
| 886 | #define NOOFRANK_MASK 0x00000004 | |
| 887 | #define NOOFROWS_SHIFT 3 | |
| 888 | #define NOOFROWS_MASK 0x00000038 | |
| 889 | #define NOOFCOLS_SHIFT 6 | |
| 890 | #define NOOFCOLS_MASK 0x000000C0 | |
| 891 | #define CHANSIZE_SHIFT 8 | |
| 892 | #define CHANSIZE_MASK 0x00000100 | |
| 893 | #define BURSTLENGTH_SHIFT 9 | |
| 894 | #define BURSTLENGTH_MASK 0x00000200 | |
| 895 | #define CHANSIZE_OVERRIDE (1 << 11) | |
| d9282fca | 896 | #define FUS_MC_ARB_RAMCFG 0x2768 |
| 0fcdb61e AD |
897 | #define MC_VM_AGP_TOP 0x2028 |
| 898 | #define MC_VM_AGP_BOT 0x202C | |
| 899 | #define MC_VM_AGP_BASE 0x2030 | |
| 900 | #define MC_VM_FB_LOCATION 0x2024 | |
| b4183e30 | 901 | #define MC_FUS_VM_FB_OFFSET 0x2898 |
| 0fcdb61e AD |
902 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 |
| 903 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 | |
| 904 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C | |
| 905 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 | |
| 906 | #define ENABLE_L1_TLB (1 << 0) | |
| 907 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
| 908 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) | |
| 909 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) | |
| 910 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | |
| 911 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) | |
| 912 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
| 913 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) | |
| 914 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) | |
| 915 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 | |
| 916 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 | |
| 917 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C | |
| 0b8c30bc | 918 | #define MC_VM_MD_L1_TLB3_CNTL 0x2698 |
| 8aeb96f8 AD |
919 | |
| 920 | #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C | |
| 921 | #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 | |
| 922 | #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 | |
| 923 | ||
| 0fcdb61e AD |
924 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
| 925 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | |
| 926 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | |
| 927 | ||
| 928 | #define PA_CL_ENHANCE 0x8A14 | |
| 929 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
| 930 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
| 721604a1 | 931 | #define PA_SC_ENHANCE 0x8BF0 |
| 0fcdb61e | 932 | #define PA_SC_AA_CONFIG 0x28C04 |
| cb5fcbd5 AD |
933 | #define MSAA_NUM_SAMPLES_SHIFT 0 |
| 934 | #define MSAA_NUM_SAMPLES_MASK 0x3 | |
| 0fcdb61e AD |
935 | #define PA_SC_CLIPRECT_RULE 0x2820C |
| 936 | #define PA_SC_EDGERULE 0x28230 | |
| 937 | #define PA_SC_FIFO_SIZE 0x8BCC | |
| 938 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) | |
| 939 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) | |
| 32fcdbf4 | 940 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) |
| 0fcdb61e | 941 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
| 32fcdbf4 AD |
942 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
| 943 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | |
| 0fcdb61e | 944 | #define PA_SC_LINE_STIPPLE 0x28A0C |
| 12920591 | 945 | #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 |
| 0fcdb61e AD |
946 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
| 947 | ||
| 948 | #define SCRATCH_REG0 0x8500 | |
| 949 | #define SCRATCH_REG1 0x8504 | |
| 950 | #define SCRATCH_REG2 0x8508 | |
| 951 | #define SCRATCH_REG3 0x850C | |
| 952 | #define SCRATCH_REG4 0x8510 | |
| 953 | #define SCRATCH_REG5 0x8514 | |
| 954 | #define SCRATCH_REG6 0x8518 | |
| 955 | #define SCRATCH_REG7 0x851C | |
| 956 | #define SCRATCH_UMSK 0x8540 | |
| 957 | #define SCRATCH_ADDR 0x8544 | |
| 958 | ||
| b866d133 | 959 | #define SMX_SAR_CTL0 0xA008 |
| 0fcdb61e AD |
960 | #define SMX_DC_CTL0 0xA020 |
| 961 | #define USE_HASH_FUNCTION (1 << 0) | |
| 32fcdbf4 | 962 | #define NUMBER_OF_SETS(x) ((x) << 1) |
| 0fcdb61e AD |
963 | #define FLUSH_ALL_ON_EVENT (1 << 10) |
| 964 | #define STALL_ON_EVENT (1 << 11) | |
| 965 | #define SMX_EVENT_CTL 0xA02C | |
| 966 | #define ES_FLUSH_CTL(x) ((x) << 0) | |
| 967 | #define GS_FLUSH_CTL(x) ((x) << 3) | |
| 968 | #define ACK_FLUSH_CTL(x) ((x) << 6) | |
| 969 | #define SYNC_FLUSH_CTL (1 << 8) | |
| 970 | ||
| 971 | #define SPI_CONFIG_CNTL 0x9100 | |
| 972 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) | |
| 973 | #define SPI_CONFIG_CNTL_1 0x913C | |
| 974 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
| 975 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
| 976 | #define SPI_INPUT_Z 0x286D8 | |
| 977 | #define SPI_PS_IN_CONTROL_0 0x286CC | |
| 978 | #define NUM_INTERP(x) ((x)<<0) | |
| 979 | #define POSITION_ENA (1<<8) | |
| 980 | #define POSITION_CENTROID (1<<9) | |
| 981 | #define POSITION_ADDR(x) ((x)<<10) | |
| 982 | #define PARAM_GEN(x) ((x)<<15) | |
| 983 | #define PARAM_GEN_ADDR(x) ((x)<<19) | |
| 984 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) | |
| 985 | #define PERSP_GRADIENT_ENA (1<<28) | |
| 986 | #define LINEAR_GRADIENT_ENA (1<<29) | |
| 987 | #define POSITION_SAMPLE (1<<30) | |
| 988 | #define BARYC_AT_SAMPLE_ENA (1<<31) | |
| 989 | ||
| 990 | #define SQ_CONFIG 0x8C00 | |
| 991 | #define VC_ENABLE (1 << 0) | |
| 992 | #define EXPORT_SRC_C (1 << 1) | |
| 32fcdbf4 AD |
993 | #define CS_PRIO(x) ((x) << 18) |
| 994 | #define LS_PRIO(x) ((x) << 20) | |
| 995 | #define HS_PRIO(x) ((x) << 22) | |
| 996 | #define PS_PRIO(x) ((x) << 24) | |
| 997 | #define VS_PRIO(x) ((x) << 26) | |
| 998 | #define GS_PRIO(x) ((x) << 28) | |
| 999 | #define ES_PRIO(x) ((x) << 30) | |
| 0fcdb61e AD |
1000 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 |
| 1001 | #define NUM_PS_GPRS(x) ((x) << 0) | |
| 1002 | #define NUM_VS_GPRS(x) ((x) << 16) | |
| 1003 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | |
| 1004 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 | |
| 1005 | #define NUM_GS_GPRS(x) ((x) << 0) | |
| 1006 | #define NUM_ES_GPRS(x) ((x) << 16) | |
| 32fcdbf4 AD |
1007 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C |
| 1008 | #define NUM_HS_GPRS(x) ((x) << 0) | |
| 1009 | #define NUM_LS_GPRS(x) ((x) << 16) | |
| 721604a1 JG |
1010 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 |
| 1011 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 | |
| 32fcdbf4 AD |
1012 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 |
| 1013 | #define NUM_PS_THREADS(x) ((x) << 0) | |
| 1014 | #define NUM_VS_THREADS(x) ((x) << 8) | |
| 1015 | #define NUM_GS_THREADS(x) ((x) << 16) | |
| 1016 | #define NUM_ES_THREADS(x) ((x) << 24) | |
| 1017 | #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C | |
| 1018 | #define NUM_HS_THREADS(x) ((x) << 0) | |
| 1019 | #define NUM_LS_THREADS(x) ((x) << 8) | |
| 1020 | #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 | |
| 1021 | #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) | |
| 1022 | #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) | |
| 1023 | #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 | |
| 1024 | #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) | |
| 1025 | #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) | |
| 1026 | #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 | |
| 1027 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) | |
| 1028 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) | |
| 1029 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C | |
| 721604a1 JG |
1030 | #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 |
| 1031 | #define SQ_STATIC_THREAD_MGMT_1 0x8E20 | |
| 1032 | #define SQ_STATIC_THREAD_MGMT_2 0x8E24 | |
| 1033 | #define SQ_STATIC_THREAD_MGMT_3 0x8E28 | |
| 32fcdbf4 AD |
1034 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C |
| 1035 | ||
| 0fcdb61e AD |
1036 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
| 1037 | #define CACHE_FIFO_SIZE(x) ((x) << 0) | |
| 1038 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) | |
| 1039 | #define DONE_FIFO_HIWATER(x) ((x) << 16) | |
| 1040 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | |
| 1041 | ||
| 1042 | #define SX_DEBUG_1 0x9058 | |
| 1043 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | |
| 1044 | #define SX_EXPORT_BUFFER_SIZES 0x900C | |
| 1045 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) | |
| 1046 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) | |
| 1047 | #define SMX_BUFFER_SIZE(x) ((x) << 16) | |
| 033b5650 | 1048 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
| 0fcdb61e AD |
1049 | #define SX_MISC 0x28350 |
| 1050 | ||
| 32fcdbf4 AD |
1051 | #define CB_PERF_CTR0_SEL_0 0x9A20 |
| 1052 | #define CB_PERF_CTR0_SEL_1 0x9A24 | |
| 1053 | #define CB_PERF_CTR1_SEL_0 0x9A28 | |
| 1054 | #define CB_PERF_CTR1_SEL_1 0x9A2C | |
| 1055 | #define CB_PERF_CTR2_SEL_0 0x9A30 | |
| 1056 | #define CB_PERF_CTR2_SEL_1 0x9A34 | |
| 1057 | #define CB_PERF_CTR3_SEL_0 0x9A38 | |
| 1058 | #define CB_PERF_CTR3_SEL_1 0x9A3C | |
| 1059 | ||
| 0fcdb61e AD |
1060 | #define TA_CNTL_AUX 0x9508 |
| 1061 | #define DISABLE_CUBE_WRAP (1 << 0) | |
| 1062 | #define DISABLE_CUBE_ANISO (1 << 1) | |
| 1063 | #define SYNC_GRADIENT (1 << 24) | |
| 1064 | #define SYNC_WALKER (1 << 25) | |
| 1065 | #define SYNC_ALIGNER (1 << 26) | |
| 1066 | ||
| 9535ab73 AD |
1067 | #define TCP_CHAN_STEER_LO 0x960c |
| 1068 | #define TCP_CHAN_STEER_HI 0x9610 | |
| 1069 | ||
| 0fcdb61e | 1070 | #define VGT_CACHE_INVALIDATION 0x88C4 |
| 32fcdbf4 | 1071 | #define CACHE_INVALIDATION(x) ((x) << 0) |
| 0fcdb61e AD |
1072 | #define VC_ONLY 0 |
| 1073 | #define TC_ONLY 1 | |
| 1074 | #define VC_AND_TC 2 | |
| 1075 | #define AUTO_INVLD_EN(x) ((x) << 6) | |
| 1076 | #define NO_AUTO 0 | |
| 1077 | #define ES_AUTO 1 | |
| 1078 | #define GS_AUTO 2 | |
| 1079 | #define ES_AND_GS_AUTO 3 | |
| 1080 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
| 1081 | #define VGT_NUM_INSTANCES 0x8974 | |
| 1082 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C | |
| 1083 | #define DEALLOC_DIST_MASK 0x0000007F | |
| 1084 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 | |
| 1085 | #define VTX_REUSE_DEPTH_MASK 0x000000FF | |
| 1086 | ||
| 1087 | #define VM_CONTEXT0_CNTL 0x1410 | |
| 1088 | #define ENABLE_CONTEXT (1 << 0) | |
| 1089 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
| 1090 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) | |
| 1091 | #define VM_CONTEXT1_CNTL 0x1414 | |
| ae133a11 | 1092 | #define VM_CONTEXT1_CNTL2 0x1434 |
| 0fcdb61e AD |
1093 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
| 1094 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | |
| 1095 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C | |
| 1096 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 | |
| 1097 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 | |
| 1098 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) | |
| 1099 | #define RESPONSE_TYPE_MASK 0x000000F0 | |
| 1100 | #define RESPONSE_TYPE_SHIFT 4 | |
| 1101 | #define VM_L2_CNTL 0x1400 | |
| 1102 | #define ENABLE_L2_CACHE (1 << 0) | |
| 1103 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
| 1104 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
| 1105 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) | |
| 1106 | #define VM_L2_CNTL2 0x1404 | |
| 1107 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
| 1108 | #define INVALIDATE_L2_CACHE (1 << 1) | |
| 1109 | #define VM_L2_CNTL3 0x1408 | |
| 1110 | #define BANK_SELECT(x) ((x) << 0) | |
| 1111 | #define CACHE_UPDATE_MODE(x) ((x) << 6) | |
| 1112 | #define VM_L2_STATUS 0x140C | |
| 1113 | #define L2_BUSY (1 << 0) | |
| ae133a11 CK |
1114 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
| 1115 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC | |
| 0fcdb61e AD |
1116 | |
| 1117 | #define WAIT_UNTIL 0x8040 | |
| 1118 | ||
| 1119 | #define SRBM_STATUS 0x0E50 | |
| a65a4369 AD |
1120 | #define RLC_RQ_PENDING (1 << 3) |
| 1121 | #define GRBM_RQ_PENDING (1 << 5) | |
| 1122 | #define VMC_BUSY (1 << 8) | |
| 1123 | #define MCB_BUSY (1 << 9) | |
| 1124 | #define MCB_NON_DISPLAY_BUSY (1 << 10) | |
| 1125 | #define MCC_BUSY (1 << 11) | |
| 1126 | #define MCD_BUSY (1 << 12) | |
| 1127 | #define SEM_BUSY (1 << 14) | |
| 1128 | #define RLC_BUSY (1 << 15) | |
| 1129 | #define IH_BUSY (1 << 17) | |
| 1130 | #define SRBM_STATUS2 0x0EC4 | |
| 1131 | #define DMA_BUSY (1 << 5) | |
| 747943ea AD |
1132 | #define SRBM_SOFT_RESET 0x0E60 |
| 1133 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 | |
| 1134 | #define SOFT_RESET_BIF (1 << 1) | |
| 1135 | #define SOFT_RESET_CG (1 << 2) | |
| 1136 | #define SOFT_RESET_DC (1 << 5) | |
| 1137 | #define SOFT_RESET_GRBM (1 << 8) | |
| 1138 | #define SOFT_RESET_HDP (1 << 9) | |
| 1139 | #define SOFT_RESET_IH (1 << 10) | |
| 1140 | #define SOFT_RESET_MC (1 << 11) | |
| 1141 | #define SOFT_RESET_RLC (1 << 13) | |
| 1142 | #define SOFT_RESET_ROM (1 << 14) | |
| 1143 | #define SOFT_RESET_SEM (1 << 15) | |
| 1144 | #define SOFT_RESET_VMC (1 << 17) | |
| 64c56e8c | 1145 | #define SOFT_RESET_DMA (1 << 20) |
| 747943ea | 1146 | #define SOFT_RESET_TST (1 << 21) |
| 64c56e8c | 1147 | #define SOFT_RESET_REGBB (1 << 22) |
| 747943ea | 1148 | #define SOFT_RESET_ORB (1 << 23) |
| 0fcdb61e | 1149 | |
| f9d9c362 AD |
1150 | /* display watermarks */ |
| 1151 | #define DC_LB_MEMORY_SPLIT 0x6b0c | |
| 1152 | #define PRIORITY_A_CNT 0x6b18 | |
| 1153 | #define PRIORITY_MARK_MASK 0x7fff | |
| 1154 | #define PRIORITY_OFF (1 << 16) | |
| 1155 | #define PRIORITY_ALWAYS_ON (1 << 20) | |
| 1156 | #define PRIORITY_B_CNT 0x6b1c | |
| 1157 | #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 | |
| 1158 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) | |
| 1159 | #define PIPE0_LATENCY_CONTROL 0x0bf4 | |
| 1160 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) | |
| 1161 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) | |
| 1162 | ||
| 45f9a39b AD |
1163 | #define IH_RB_CNTL 0x3e00 |
| 1164 | # define IH_RB_ENABLE (1 << 0) | |
| 1165 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ | |
| 1166 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) | |
| 1167 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) | |
| 1168 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ | |
| 1169 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) | |
| 1170 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) | |
| 1171 | #define IH_RB_BASE 0x3e04 | |
| 1172 | #define IH_RB_RPTR 0x3e08 | |
| 1173 | #define IH_RB_WPTR 0x3e0c | |
| 1174 | # define RB_OVERFLOW (1 << 0) | |
| 1175 | # define WPTR_OFFSET_MASK 0x3fffc | |
| 1176 | #define IH_RB_WPTR_ADDR_HI 0x3e10 | |
| 1177 | #define IH_RB_WPTR_ADDR_LO 0x3e14 | |
| 1178 | #define IH_CNTL 0x3e18 | |
| 1179 | # define ENABLE_INTR (1 << 0) | |
| fcb857ab | 1180 | # define IH_MC_SWAP(x) ((x) << 1) |
| 45f9a39b AD |
1181 | # define IH_MC_SWAP_NONE 0 |
| 1182 | # define IH_MC_SWAP_16BIT 1 | |
| 1183 | # define IH_MC_SWAP_32BIT 2 | |
| 1184 | # define IH_MC_SWAP_64BIT 3 | |
| 1185 | # define RPTR_REARM (1 << 4) | |
| 1186 | # define MC_WRREQ_CREDIT(x) ((x) << 15) | |
| 1187 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) | |
| 1188 | ||
| 1189 | #define CP_INT_CNTL 0xc124 | |
| 1190 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | |
| 1191 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) | |
| 1192 | # define SCRATCH_INT_ENABLE (1 << 25) | |
| 1193 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
| 1194 | # define IB2_INT_ENABLE (1 << 29) | |
| 1195 | # define IB1_INT_ENABLE (1 << 30) | |
| 1196 | # define RB_INT_ENABLE (1 << 31) | |
| 1197 | #define CP_INT_STATUS 0xc128 | |
| 1198 | # define SCRATCH_INT_STAT (1 << 25) | |
| 1199 | # define TIME_STAMP_INT_STAT (1 << 26) | |
| 1200 | # define IB2_INT_STAT (1 << 29) | |
| 1201 | # define IB1_INT_STAT (1 << 30) | |
| 1202 | # define RB_INT_STAT (1 << 31) | |
| 1203 | ||
| 1204 | #define GRBM_INT_CNTL 0x8060 | |
| 1205 | # define RDERR_INT_ENABLE (1 << 0) | |
| 1206 | # define GUI_IDLE_INT_ENABLE (1 << 19) | |
| 1207 | ||
| 1208 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ | |
| 1209 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 | |
| 1210 | ||
| 1211 | /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ | |
| 1212 | #define VLINE_STATUS 0x6bb8 | |
| 1213 | # define VLINE_OCCURRED (1 << 0) | |
| 1214 | # define VLINE_ACK (1 << 4) | |
| 1215 | # define VLINE_STAT (1 << 12) | |
| 1216 | # define VLINE_INTERRUPT (1 << 16) | |
| 1217 | # define VLINE_INTERRUPT_TYPE (1 << 17) | |
| 1218 | /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ | |
| 1219 | #define VBLANK_STATUS 0x6bbc | |
| 1220 | # define VBLANK_OCCURRED (1 << 0) | |
| 1221 | # define VBLANK_ACK (1 << 4) | |
| 1222 | # define VBLANK_STAT (1 << 12) | |
| 1223 | # define VBLANK_INTERRUPT (1 << 16) | |
| 1224 | # define VBLANK_INTERRUPT_TYPE (1 << 17) | |
| 1225 | ||
| 1226 | /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ | |
| 1227 | #define INT_MASK 0x6b40 | |
| 1228 | # define VBLANK_INT_MASK (1 << 0) | |
| 1229 | # define VLINE_INT_MASK (1 << 4) | |
| 1230 | ||
| 1231 | #define DISP_INTERRUPT_STATUS 0x60f4 | |
| 1232 | # define LB_D1_VLINE_INTERRUPT (1 << 2) | |
| 1233 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) | |
| 1234 | # define DC_HPD1_INTERRUPT (1 << 17) | |
| 1235 | # define DC_HPD1_RX_INTERRUPT (1 << 18) | |
| 1236 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) | |
| 1237 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) | |
| 1238 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) | |
| 1239 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) | |
| 1240 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 | |
| 1241 | # define LB_D2_VLINE_INTERRUPT (1 << 2) | |
| 1242 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) | |
| 1243 | # define DC_HPD2_INTERRUPT (1 << 17) | |
| 1244 | # define DC_HPD2_RX_INTERRUPT (1 << 18) | |
| 1245 | # define DISP_TIMER_INTERRUPT (1 << 24) | |
| 1246 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc | |
| 1247 | # define LB_D3_VLINE_INTERRUPT (1 << 2) | |
| 1248 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) | |
| 1249 | # define DC_HPD3_INTERRUPT (1 << 17) | |
| 1250 | # define DC_HPD3_RX_INTERRUPT (1 << 18) | |
| 1251 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 | |
| 1252 | # define LB_D4_VLINE_INTERRUPT (1 << 2) | |
| 1253 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) | |
| 1254 | # define DC_HPD4_INTERRUPT (1 << 17) | |
| 1255 | # define DC_HPD4_RX_INTERRUPT (1 << 18) | |
| 1256 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c | |
| 1257 | # define LB_D5_VLINE_INTERRUPT (1 << 2) | |
| 1258 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) | |
| 1259 | # define DC_HPD5_INTERRUPT (1 << 17) | |
| 1260 | # define DC_HPD5_RX_INTERRUPT (1 << 18) | |
| 37cba6c6 | 1261 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
| 45f9a39b AD |
1262 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
| 1263 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) | |
| 1264 | # define DC_HPD6_INTERRUPT (1 << 17) | |
| 1265 | # define DC_HPD6_RX_INTERRUPT (1 << 18) | |
| 1266 | ||
| 1267 | /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ | |
| 1268 | #define GRPH_INT_STATUS 0x6858 | |
| 1269 | # define GRPH_PFLIP_INT_OCCURRED (1 << 0) | |
| 1270 | # define GRPH_PFLIP_INT_CLEAR (1 << 8) | |
| 1271 | /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ | |
| 1272 | #define GRPH_INT_CONTROL 0x685c | |
| 1273 | # define GRPH_PFLIP_INT_MASK (1 << 0) | |
| 1274 | # define GRPH_PFLIP_INT_TYPE (1 << 8) | |
| 1275 | ||
| 1276 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 | |
| 1277 | #define DACB_AUTODETECT_INT_CONTROL 0x67c8 | |
| 1278 | ||
| 1279 | #define DC_HPD1_INT_STATUS 0x601c | |
| 1280 | #define DC_HPD2_INT_STATUS 0x6028 | |
| 1281 | #define DC_HPD3_INT_STATUS 0x6034 | |
| 1282 | #define DC_HPD4_INT_STATUS 0x6040 | |
| 1283 | #define DC_HPD5_INT_STATUS 0x604c | |
| 1284 | #define DC_HPD6_INT_STATUS 0x6058 | |
| 1285 | # define DC_HPDx_INT_STATUS (1 << 0) | |
| 1286 | # define DC_HPDx_SENSE (1 << 1) | |
| 1287 | # define DC_HPDx_RX_INT_STATUS (1 << 8) | |
| 1288 | ||
| 1289 | #define DC_HPD1_INT_CONTROL 0x6020 | |
| 1290 | #define DC_HPD2_INT_CONTROL 0x602c | |
| 1291 | #define DC_HPD3_INT_CONTROL 0x6038 | |
| 1292 | #define DC_HPD4_INT_CONTROL 0x6044 | |
| 1293 | #define DC_HPD5_INT_CONTROL 0x6050 | |
| 1294 | #define DC_HPD6_INT_CONTROL 0x605c | |
| 1295 | # define DC_HPDx_INT_ACK (1 << 0) | |
| 1296 | # define DC_HPDx_INT_POLARITY (1 << 8) | |
| 1297 | # define DC_HPDx_INT_EN (1 << 16) | |
| 1298 | # define DC_HPDx_RX_INT_ACK (1 << 20) | |
| 1299 | # define DC_HPDx_RX_INT_EN (1 << 24) | |
| 1300 | ||
| 1301 | #define DC_HPD1_CONTROL 0x6024 | |
| 1302 | #define DC_HPD2_CONTROL 0x6030 | |
| 1303 | #define DC_HPD3_CONTROL 0x603c | |
| 1304 | #define DC_HPD4_CONTROL 0x6048 | |
| 1305 | #define DC_HPD5_CONTROL 0x6054 | |
| 1306 | #define DC_HPD6_CONTROL 0x6060 | |
| 1307 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) | |
| 1308 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | |
| 1309 | # define DC_HPDx_EN (1 << 28) | |
| 1310 | ||
| 233d1ad5 AD |
1311 | /* ASYNC DMA */ |
| 1312 | #define DMA_RB_RPTR 0xd008 | |
| 1313 | #define DMA_RB_WPTR 0xd00c | |
| 1314 | ||
| 1315 | #define DMA_CNTL 0xd02c | |
| 1316 | # define TRAP_ENABLE (1 << 0) | |
| 1317 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | |
| 1318 | # define SEM_WAIT_INT_ENABLE (1 << 2) | |
| 1319 | # define DATA_SWAP_ENABLE (1 << 3) | |
| 1320 | # define FENCE_SWAP_ENABLE (1 << 4) | |
| 1321 | # define CTXEMPTY_INT_ENABLE (1 << 28) | |
| 1322 | #define DMA_TILING_CONFIG 0xD0B8 | |
| 1323 | ||
| f60cbd11 AD |
1324 | #define CAYMAN_DMA1_CNTL 0xd82c |
| 1325 | ||
| 233d1ad5 | 1326 | /* async DMA packets */ |
| 0fcb6155 JG |
1327 | #define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ |
| 1328 | (((sub_cmd) & 0xFF) << 20) |\ | |
| 1329 | (((n) & 0xFFFFF) << 0)) | |
| 1330 | #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) | |
| 1331 | #define GET_DMA_COUNT(h) ((h) & 0x000fffff) | |
| 1332 | #define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20) | |
| 1333 | ||
| 233d1ad5 | 1334 | /* async DMA Packet types */ |
| 0fcb6155 JG |
1335 | #define DMA_PACKET_WRITE 0x2 |
| 1336 | #define DMA_PACKET_COPY 0x3 | |
| 1337 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | |
| 1338 | #define DMA_PACKET_SEMAPHORE 0x5 | |
| 1339 | #define DMA_PACKET_FENCE 0x6 | |
| 1340 | #define DMA_PACKET_TRAP 0x7 | |
| 1341 | #define DMA_PACKET_SRBM_WRITE 0x9 | |
| 1342 | #define DMA_PACKET_CONSTANT_FILL 0xd | |
| 1343 | #define DMA_PACKET_NOP 0xf | |
| 233d1ad5 | 1344 | |
| f52382d7 AD |
1345 | /* PIF PHY0 indirect regs */ |
| 1346 | #define PB0_PIF_CNTL 0x10 | |
| 1347 | # define LS2_EXIT_TIME(x) ((x) << 17) | |
| 1348 | # define LS2_EXIT_TIME_MASK (0x7 << 17) | |
| 1349 | # define LS2_EXIT_TIME_SHIFT 17 | |
| 1350 | #define PB0_PIF_PAIRING 0x11 | |
| 1351 | # define MULTI_PIF (1 << 25) | |
| 1352 | #define PB0_PIF_PWRDOWN_0 0x12 | |
| 1353 | # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) | |
| 1354 | # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) | |
| 1355 | # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 | |
| 1356 | # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) | |
| 1357 | # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) | |
| 1358 | # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 | |
| 1359 | # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) | |
| 1360 | # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) | |
| 1361 | # define PLL_RAMP_UP_TIME_0_SHIFT 24 | |
| 1362 | #define PB0_PIF_PWRDOWN_1 0x13 | |
| 1363 | # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) | |
| 1364 | # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) | |
| 1365 | # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 | |
| 1366 | # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) | |
| 1367 | # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) | |
| 1368 | # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 | |
| 1369 | # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) | |
| 1370 | # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) | |
| 1371 | # define PLL_RAMP_UP_TIME_1_SHIFT 24 | |
| 1372 | /* PIF PHY1 indirect regs */ | |
| 1373 | #define PB1_PIF_CNTL 0x10 | |
| 1374 | #define PB1_PIF_PAIRING 0x11 | |
| 1375 | #define PB1_PIF_PWRDOWN_0 0x12 | |
| 1376 | #define PB1_PIF_PWRDOWN_1 0x13 | |
| 1377 | /* PCIE PORT indirect regs */ | |
| 1378 | #define PCIE_LC_CNTL 0xa0 | |
| 1379 | # define LC_L0S_INACTIVITY(x) ((x) << 8) | |
| 1380 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) | |
| 1381 | # define LC_L0S_INACTIVITY_SHIFT 8 | |
| 1382 | # define LC_L1_INACTIVITY(x) ((x) << 12) | |
| 1383 | # define LC_L1_INACTIVITY_MASK (0xf << 12) | |
| 1384 | # define LC_L1_INACTIVITY_SHIFT 12 | |
| 1385 | # define LC_PMI_TO_L1_DIS (1 << 16) | |
| 1386 | # define LC_ASPM_TO_L1_DIS (1 << 24) | |
| 9e46a48d AD |
1387 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
| 1388 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ | |
| 1389 | # define LC_LINK_WIDTH_SHIFT 0 | |
| 1390 | # define LC_LINK_WIDTH_MASK 0x7 | |
| 1391 | # define LC_LINK_WIDTH_X0 0 | |
| 1392 | # define LC_LINK_WIDTH_X1 1 | |
| 1393 | # define LC_LINK_WIDTH_X2 2 | |
| 1394 | # define LC_LINK_WIDTH_X4 3 | |
| 1395 | # define LC_LINK_WIDTH_X8 4 | |
| 1396 | # define LC_LINK_WIDTH_X16 6 | |
| 1397 | # define LC_LINK_WIDTH_RD_SHIFT 4 | |
| 1398 | # define LC_LINK_WIDTH_RD_MASK 0x70 | |
| 1399 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | |
| 1400 | # define LC_RECONFIG_NOW (1 << 8) | |
| 1401 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | |
| 1402 | # define LC_RENEGOTIATE_EN (1 << 10) | |
| 1403 | # define LC_SHORT_RECONFIG_EN (1 << 11) | |
| 1404 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | |
| 1405 | # define LC_UPCONFIGURE_DIS (1 << 13) | |
| f52382d7 AD |
1406 | # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) |
| 1407 | # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) | |
| 1408 | # define LC_DYN_LANES_PWR_STATE_SHIFT 21 | |
| 9e46a48d AD |
1409 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
| 1410 | # define LC_GEN2_EN_STRAP (1 << 0) | |
| 1411 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | |
| 1412 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) | |
| 1413 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) | |
| 1414 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) | |
| 1415 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 | |
| 1416 | # define LC_CURRENT_DATA_RATE (1 << 11) | |
| dc50ba7f AD |
1417 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) |
| 1418 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) | |
| 1419 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 | |
| 9e46a48d AD |
1420 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
| 1421 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) | |
| 1422 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) | |
| 1423 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) | |
| 1424 | #define MM_CFGREGS_CNTL 0x544c | |
| 1425 | # define MM_WR_TO_CFG_EN (1 << 3) | |
| 1426 | #define LINK_CNTL2 0x88 /* F0 */ | |
| 1427 | # define TARGET_LINK_SPEED_MASK (0xf << 0) | |
| 1428 | # define SELECTABLE_DEEMPHASIS (1 << 6) | |
| 1429 | ||
| f2ba57b5 CK |
1430 | |
| 1431 | /* | |
| 1432 | * UVD | |
| 1433 | */ | |
| 9a21059d CK |
1434 | #define UVD_UDEC_ADDR_CONFIG 0xef4c |
| 1435 | #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 | |
| 1436 | #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 | |
| f2ba57b5 CK |
1437 | #define UVD_RBC_RB_RPTR 0xf690 |
| 1438 | #define UVD_RBC_RB_WPTR 0xf694 | |
| 1439 | ||
| cb5fcbd5 AD |
1440 | /* |
| 1441 | * PM4 | |
| 1442 | */ | |
| 4e872ae2 | 1443 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
| cb5fcbd5 AD |
1444 | (((reg) >> 2) & 0xFFFF) | \ |
| 1445 | ((n) & 0x3FFF) << 16) | |
| 1446 | #define CP_PACKET2 0x80000000 | |
| 1447 | #define PACKET2_PAD_SHIFT 0 | |
| 1448 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
| 1449 | ||
| 1450 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
| 1451 | ||
| 4e872ae2 | 1452 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
| cb5fcbd5 AD |
1453 | (((op) & 0xFF) << 8) | \ |
| 1454 | ((n) & 0x3FFF) << 16) | |
| 1455 | ||
| 1456 | /* Packet 3 types */ | |
| 1457 | #define PACKET3_NOP 0x10 | |
| 1458 | #define PACKET3_SET_BASE 0x11 | |
| 1459 | #define PACKET3_CLEAR_STATE 0x12 | |
| 32171d22 | 1460 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
| cb5fcbd5 AD |
1461 | #define PACKET3_DISPATCH_DIRECT 0x15 |
| 1462 | #define PACKET3_DISPATCH_INDIRECT 0x16 | |
| 1463 | #define PACKET3_INDIRECT_BUFFER_END 0x17 | |
| 12920591 | 1464 | #define PACKET3_MODE_CONTROL 0x18 |
| cb5fcbd5 AD |
1465 | #define PACKET3_SET_PREDICATION 0x20 |
| 1466 | #define PACKET3_REG_RMW 0x21 | |
| 1467 | #define PACKET3_COND_EXEC 0x22 | |
| 1468 | #define PACKET3_PRED_EXEC 0x23 | |
| 1469 | #define PACKET3_DRAW_INDIRECT 0x24 | |
| 1470 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | |
| 1471 | #define PACKET3_INDEX_BASE 0x26 | |
| 1472 | #define PACKET3_DRAW_INDEX_2 0x27 | |
| 1473 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
| 1474 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 | |
| 1475 | #define PACKET3_INDEX_TYPE 0x2A | |
| 1476 | #define PACKET3_DRAW_INDEX 0x2B | |
| 1477 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
| 1478 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | |
| 1479 | #define PACKET3_NUM_INSTANCES 0x2F | |
| 1480 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | |
| 1481 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
| 1482 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | |
| 1483 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 | |
| 1484 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
| 1485 | #define PACKET3_MPEG_INDEX 0x3A | |
| 721604a1 | 1486 | #define PACKET3_COPY_DW 0x3B |
| cb5fcbd5 AD |
1487 | #define PACKET3_WAIT_REG_MEM 0x3C |
| 1488 | #define PACKET3_MEM_WRITE 0x3D | |
| 1489 | #define PACKET3_INDIRECT_BUFFER 0x32 | |
| b997a8ba AD |
1490 | #define PACKET3_CP_DMA 0x41 |
| 1491 | /* 1. header | |
| 1492 | * 2. SRC_ADDR_LO or DATA [31:0] | |
| 1493 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | | |
| 1494 | * SRC_ADDR_HI [7:0] | |
| 1495 | * 4. DST_ADDR_LO [31:0] | |
| 1496 | * 5. DST_ADDR_HI [7:0] | |
| 1497 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] | |
| 1498 | */ | |
| 1499 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) | |
| 1500 | /* 0 - SRC_ADDR | |
| 1501 | * 1 - GDS | |
| 1502 | */ | |
| 1503 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) | |
| 1504 | /* 0 - ME | |
| 1505 | * 1 - PFP | |
| 1506 | */ | |
| 1507 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) | |
| 1508 | /* 0 - SRC_ADDR | |
| 1509 | * 1 - GDS | |
| 1510 | * 2 - DATA | |
| 1511 | */ | |
| 1512 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) | |
| 1513 | /* COMMAND */ | |
| 1514 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) | |
| 1515 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) | |
| 1516 | /* 0 - none | |
| 1517 | * 1 - 8 in 16 | |
| 1518 | * 2 - 8 in 32 | |
| 1519 | * 3 - 8 in 64 | |
| 1520 | */ | |
| 1521 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) | |
| 1522 | /* 0 - none | |
| 1523 | * 1 - 8 in 16 | |
| 1524 | * 2 - 8 in 32 | |
| 1525 | * 3 - 8 in 64 | |
| 1526 | */ | |
| 1527 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) | |
| 1528 | /* 0 - memory | |
| 1529 | * 1 - register | |
| 1530 | */ | |
| 1531 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) | |
| 1532 | /* 0 - memory | |
| 1533 | * 1 - register | |
| 1534 | */ | |
| 1535 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | |
| 1536 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | |
| cb5fcbd5 AD |
1537 | #define PACKET3_SURFACE_SYNC 0x43 |
| 1538 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
| 1539 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | |
| 1540 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | |
| 1541 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | |
| 1542 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | |
| 1543 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | |
| 1544 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | |
| 1545 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | |
| 1546 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | |
| 1547 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) | |
| 1548 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) | |
| 1549 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) | |
| 32171d22 | 1550 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) |
| cb5fcbd5 AD |
1551 | # define PACKET3_FULL_CACHE_ENA (1 << 20) |
| 1552 | # define PACKET3_TC_ACTION_ENA (1 << 23) | |
| 1553 | # define PACKET3_VC_ACTION_ENA (1 << 24) | |
| 1554 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
| 1555 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
| 1556 | # define PACKET3_SH_ACTION_ENA (1 << 27) | |
| 32171d22 | 1557 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
| cb5fcbd5 AD |
1558 | #define PACKET3_ME_INITIALIZE 0x44 |
| 1559 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | |
| 1560 | #define PACKET3_COND_WRITE 0x45 | |
| 1561 | #define PACKET3_EVENT_WRITE 0x46 | |
| 1562 | #define PACKET3_EVENT_WRITE_EOP 0x47 | |
| 1563 | #define PACKET3_EVENT_WRITE_EOS 0x48 | |
| 1564 | #define PACKET3_PREAMBLE_CNTL 0x4A | |
| 2281a378 AD |
1565 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
| 1566 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | |
| cb5fcbd5 AD |
1567 | #define PACKET3_RB_OFFSET 0x4B |
| 1568 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C | |
| 1569 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D | |
| 1570 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E | |
| 1571 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F | |
| 1572 | #define PACKET3_ONE_REG_WRITE 0x57 | |
| 1573 | #define PACKET3_SET_CONFIG_REG 0x68 | |
| 1574 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 | |
| 1575 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 | |
| 1576 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
| 1577 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 | |
| 1578 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
| 1579 | #define PACKET3_SET_ALU_CONST 0x6A | |
| 1580 | /* alu const buffers only; no reg file */ | |
| 1581 | #define PACKET3_SET_BOOL_CONST 0x6B | |
| 1582 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 | |
| 1583 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 | |
| 1584 | #define PACKET3_SET_LOOP_CONST 0x6C | |
| 1585 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 | |
| 1586 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 | |
| 1587 | #define PACKET3_SET_RESOURCE 0x6D | |
| 1588 | #define PACKET3_SET_RESOURCE_START 0x00030000 | |
| 1589 | #define PACKET3_SET_RESOURCE_END 0x00038000 | |
| 1590 | #define PACKET3_SET_SAMPLER 0x6E | |
| 1591 | #define PACKET3_SET_SAMPLER_START 0x0003c000 | |
| 1592 | #define PACKET3_SET_SAMPLER_END 0x0003c600 | |
| 1593 | #define PACKET3_SET_CTL_CONST 0x6F | |
| 1594 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 | |
| 1595 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c | |
| 1596 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 | |
| 1597 | #define PACKET3_SET_ALU_CONST_VS 0x71 | |
| 1598 | #define PACKET3_SET_ALU_CONST_DI 0x72 | |
| 1599 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | |
| 1600 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 | |
| 1601 | #define PACKET3_SET_APPEND_CNT 0x75 | |
| 1602 | ||
| 1603 | #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c | |
| 1604 | #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) | |
| 1605 | #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) | |
| 1606 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 | |
| 1607 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 | |
| 1608 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 | |
| 1609 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 | |
| 1610 | ||
| 721604a1 JG |
1611 | #define VGT_VTX_VECT_EJECT_REG 0x88b0 |
| 1612 | ||
| cb5fcbd5 AD |
1613 | #define SQ_CONST_MEM_BASE 0x8df8 |
| 1614 | ||
| 8aa75009 | 1615 | #define SQ_ESGS_RING_BASE 0x8c40 |
| cb5fcbd5 | 1616 | #define SQ_ESGS_RING_SIZE 0x8c44 |
| 8aa75009 | 1617 | #define SQ_GSVS_RING_BASE 0x8c48 |
| cb5fcbd5 | 1618 | #define SQ_GSVS_RING_SIZE 0x8c4c |
| 8aa75009 | 1619 | #define SQ_ESTMP_RING_BASE 0x8c50 |
| cb5fcbd5 | 1620 | #define SQ_ESTMP_RING_SIZE 0x8c54 |
| 8aa75009 | 1621 | #define SQ_GSTMP_RING_BASE 0x8c58 |
| cb5fcbd5 | 1622 | #define SQ_GSTMP_RING_SIZE 0x8c5c |
| 8aa75009 | 1623 | #define SQ_VSTMP_RING_BASE 0x8c60 |
| cb5fcbd5 | 1624 | #define SQ_VSTMP_RING_SIZE 0x8c64 |
| 8aa75009 | 1625 | #define SQ_PSTMP_RING_BASE 0x8c68 |
| cb5fcbd5 | 1626 | #define SQ_PSTMP_RING_SIZE 0x8c6c |
| 8aa75009 | 1627 | #define SQ_LSTMP_RING_BASE 0x8e10 |
| cb5fcbd5 | 1628 | #define SQ_LSTMP_RING_SIZE 0x8e14 |
| 8aa75009 | 1629 | #define SQ_HSTMP_RING_BASE 0x8e18 |
| cb5fcbd5 AD |
1630 | #define SQ_HSTMP_RING_SIZE 0x8e1c |
| 1631 | #define VGT_TF_RING_SIZE 0x8988 | |
| 1632 | ||
| 1633 | #define SQ_ESGS_RING_ITEMSIZE 0x28900 | |
| 1634 | #define SQ_GSVS_RING_ITEMSIZE 0x28904 | |
| 1635 | #define SQ_ESTMP_RING_ITEMSIZE 0x28908 | |
| 1636 | #define SQ_GSTMP_RING_ITEMSIZE 0x2890c | |
| 1637 | #define SQ_VSTMP_RING_ITEMSIZE 0x28910 | |
| 1638 | #define SQ_PSTMP_RING_ITEMSIZE 0x28914 | |
| 1639 | #define SQ_LSTMP_RING_ITEMSIZE 0x28830 | |
| 1640 | #define SQ_HSTMP_RING_ITEMSIZE 0x28834 | |
| 1641 | ||
| 1642 | #define SQ_GS_VERT_ITEMSIZE 0x2891c | |
| 1643 | #define SQ_GS_VERT_ITEMSIZE_1 0x28920 | |
| 1644 | #define SQ_GS_VERT_ITEMSIZE_2 0x28924 | |
| 1645 | #define SQ_GS_VERT_ITEMSIZE_3 0x28928 | |
| 1646 | #define SQ_GSVS_RING_OFFSET_1 0x2892c | |
| 1647 | #define SQ_GSVS_RING_OFFSET_2 0x28930 | |
| 1648 | #define SQ_GSVS_RING_OFFSET_3 0x28934 | |
| 1649 | ||
| 60a4a3e0 AD |
1650 | #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 |
| 1651 | #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 | |
| 1652 | ||
| cb5fcbd5 AD |
1653 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
| 1654 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 | |
| 1655 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 | |
| 1656 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c | |
| 1657 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 | |
| 1658 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 | |
| 1659 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 | |
| 1660 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c | |
| 1661 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 | |
| 1662 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 | |
| 1663 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 | |
| 1664 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c | |
| 1665 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 | |
| 1666 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 | |
| 1667 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 | |
| 1668 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c | |
| 1669 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 | |
| 1670 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 | |
| 1671 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 | |
| 1672 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c | |
| 1673 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 | |
| 1674 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 | |
| 1675 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 | |
| 1676 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c | |
| 1677 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 | |
| 1678 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 | |
| 1679 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 | |
| 1680 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac | |
| 1681 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 | |
| 1682 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 | |
| 1683 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 | |
| 1684 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc | |
| 1685 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 | |
| 1686 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 | |
| 1687 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 | |
| 1688 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc | |
| 1689 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 | |
| 1690 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 | |
| 1691 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 | |
| 1692 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc | |
| 1693 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 | |
| 1694 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 | |
| 1695 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 | |
| 1696 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec | |
| 1697 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 | |
| 1698 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 | |
| 1699 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 | |
| 1700 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc | |
| 1701 | #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 | |
| 1702 | #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 | |
| 1703 | #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 | |
| 1704 | #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c | |
| 1705 | #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 | |
| 1706 | #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 | |
| 1707 | #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 | |
| 1708 | #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c | |
| 1709 | #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 | |
| 1710 | #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 | |
| 1711 | #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 | |
| 1712 | #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c | |
| 1713 | #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 | |
| 1714 | #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 | |
| 1715 | #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 | |
| 1716 | #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c | |
| 1717 | #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 | |
| 1718 | #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 | |
| 1719 | #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 | |
| 1720 | #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c | |
| 1721 | #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 | |
| 1722 | #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 | |
| 1723 | #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 | |
| 1724 | #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c | |
| 1725 | #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 | |
| 1726 | #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 | |
| 1727 | #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 | |
| 1728 | #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c | |
| 1729 | #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 | |
| 1730 | #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 | |
| 1731 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 | |
| 1732 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c | |
| 1733 | ||
| d7ccd8fc AD |
1734 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
| 1735 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 | |
| 1736 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 | |
| d7ccd8fc | 1737 | |
| 721604a1 JG |
1738 | #define VGT_PRIMITIVE_TYPE 0x8958 |
| 1739 | #define VGT_INDEX_TYPE 0x895C | |
| 1740 | ||
| 1741 | #define VGT_NUM_INDICES 0x8970 | |
| 1742 | ||
| 1743 | #define VGT_COMPUTE_DIM_X 0x8990 | |
| 1744 | #define VGT_COMPUTE_DIM_Y 0x8994 | |
| 1745 | #define VGT_COMPUTE_DIM_Z 0x8998 | |
| 1746 | #define VGT_COMPUTE_START_X 0x899C | |
| 1747 | #define VGT_COMPUTE_START_Y 0x89A0 | |
| 1748 | #define VGT_COMPUTE_START_Z 0x89A4 | |
| 1749 | #define VGT_COMPUTE_INDEX 0x89A8 | |
| 1750 | #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC | |
| 1751 | #define VGT_HS_OFFCHIP_PARAM 0x89B0 | |
| 1752 | ||
| 1753 | #define DB_DEBUG 0x9830 | |
| 1754 | #define DB_DEBUG2 0x9834 | |
| 1755 | #define DB_DEBUG3 0x9838 | |
| 1756 | #define DB_DEBUG4 0x983C | |
| 1757 | #define DB_WATERMARKS 0x9854 | |
| cb5fcbd5 | 1758 | #define DB_DEPTH_CONTROL 0x28800 |
| 285484e2 JG |
1759 | #define R_028800_DB_DEPTH_CONTROL 0x028800 |
| 1760 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) | |
| 1761 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) | |
| 1762 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE | |
| 1763 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) | |
| 1764 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) | |
| 1765 | #define C_028800_Z_ENABLE 0xFFFFFFFD | |
| 1766 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) | |
| 1767 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) | |
| 1768 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB | |
| 1769 | #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) | |
| 1770 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) | |
| 1771 | #define C_028800_ZFUNC 0xFFFFFF8F | |
| 1772 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) | |
| 1773 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) | |
| 1774 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F | |
| 1775 | #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) | |
| 1776 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) | |
| 1777 | #define C_028800_STENCILFUNC 0xFFFFF8FF | |
| 1778 | #define V_028800_STENCILFUNC_NEVER 0x00000000 | |
| 1779 | #define V_028800_STENCILFUNC_LESS 0x00000001 | |
| 1780 | #define V_028800_STENCILFUNC_EQUAL 0x00000002 | |
| 1781 | #define V_028800_STENCILFUNC_LEQUAL 0x00000003 | |
| 1782 | #define V_028800_STENCILFUNC_GREATER 0x00000004 | |
| 1783 | #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 | |
| 1784 | #define V_028800_STENCILFUNC_GEQUAL 0x00000006 | |
| 1785 | #define V_028800_STENCILFUNC_ALWAYS 0x00000007 | |
| 1786 | #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) | |
| 1787 | #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) | |
| 1788 | #define C_028800_STENCILFAIL 0xFFFFC7FF | |
| 1789 | #define V_028800_STENCIL_KEEP 0x00000000 | |
| 1790 | #define V_028800_STENCIL_ZERO 0x00000001 | |
| 1791 | #define V_028800_STENCIL_REPLACE 0x00000002 | |
| 1792 | #define V_028800_STENCIL_INCR 0x00000003 | |
| 1793 | #define V_028800_STENCIL_DECR 0x00000004 | |
| 1794 | #define V_028800_STENCIL_INVERT 0x00000005 | |
| 1795 | #define V_028800_STENCIL_INCR_WRAP 0x00000006 | |
| 1796 | #define V_028800_STENCIL_DECR_WRAP 0x00000007 | |
| 1797 | #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) | |
| 1798 | #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) | |
| 1799 | #define C_028800_STENCILZPASS 0xFFFE3FFF | |
| 1800 | #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) | |
| 1801 | #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) | |
| 1802 | #define C_028800_STENCILZFAIL 0xFFF1FFFF | |
| 1803 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) | |
| 1804 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) | |
| 1805 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF | |
| 1806 | #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) | |
| 1807 | #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) | |
| 1808 | #define C_028800_STENCILFAIL_BF 0xFC7FFFFF | |
| 1809 | #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) | |
| 1810 | #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) | |
| 1811 | #define C_028800_STENCILZPASS_BF 0xE3FFFFFF | |
| 1812 | #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) | |
| 1813 | #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) | |
| 1814 | #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF | |
| cb5fcbd5 | 1815 | #define DB_DEPTH_VIEW 0x28008 |
| 285484e2 JG |
1816 | #define R_028008_DB_DEPTH_VIEW 0x00028008 |
| 1817 | #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) | |
| 1818 | #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) | |
| 1819 | #define C_028008_SLICE_START 0xFFFFF800 | |
| 1820 | #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) | |
| 1821 | #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) | |
| 1822 | #define C_028008_SLICE_MAX 0xFF001FFF | |
| cb5fcbd5 | 1823 | #define DB_HTILE_DATA_BASE 0x28014 |
| 88f50c80 JG |
1824 | #define DB_HTILE_SURFACE 0x28abc |
| 1825 | #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) | |
| 1826 | #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) | |
| 1827 | #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE | |
| 1828 | #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) | |
| 1829 | #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) | |
| 1830 | #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD | |
| 1831 | #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) | |
| cb5fcbd5 AD |
1832 | #define DB_Z_INFO 0x28040 |
| 1833 | # define Z_ARRAY_MODE(x) ((x) << 4) | |
| f3a71df0 AD |
1834 | # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) |
| 1835 | # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) | |
| 1836 | # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) | |
| 1837 | # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) | |
| 285484e2 JG |
1838 | # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) |
| 1839 | #define R_028040_DB_Z_INFO 0x028040 | |
| 1840 | #define S_028040_FORMAT(x) (((x) & 0x3) << 0) | |
| 1841 | #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) | |
| 1842 | #define C_028040_FORMAT 0xFFFFFFFC | |
| 1843 | #define V_028040_Z_INVALID 0x00000000 | |
| 1844 | #define V_028040_Z_16 0x00000001 | |
| 1845 | #define V_028040_Z_24 0x00000002 | |
| 1846 | #define V_028040_Z_32_FLOAT 0x00000003 | |
| 1847 | #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) | |
| 1848 | #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) | |
| 1849 | #define C_028040_ARRAY_MODE 0xFFFFFF0F | |
| 1850 | #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) | |
| 1851 | #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) | |
| 1852 | #define C_028040_READ_SIZE 0xEFFFFFFF | |
| 1853 | #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) | |
| 1854 | #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) | |
| 1855 | #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF | |
| 1856 | #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) | |
| 1857 | #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) | |
| 1858 | #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF | |
| 1859 | #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) | |
| 1860 | #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) | |
| 1861 | #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) | |
| 1862 | #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) | |
| 1863 | #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) | |
| 1864 | #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) | |
| 1865 | #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) | |
| 1866 | #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) | |
| 1867 | #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) | |
| 1868 | #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) | |
| cb5fcbd5 | 1869 | #define DB_STENCIL_INFO 0x28044 |
| 285484e2 JG |
1870 | #define R_028044_DB_STENCIL_INFO 0x028044 |
| 1871 | #define S_028044_FORMAT(x) (((x) & 0x1) << 0) | |
| 1872 | #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) | |
| 1873 | #define C_028044_FORMAT 0xFFFFFFFE | |
| 0f457e48 MO |
1874 | #define V_028044_STENCIL_INVALID 0 |
| 1875 | #define V_028044_STENCIL_8 1 | |
| 285484e2 | 1876 | #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) |
| cb5fcbd5 AD |
1877 | #define DB_Z_READ_BASE 0x28048 |
| 1878 | #define DB_STENCIL_READ_BASE 0x2804c | |
| 1879 | #define DB_Z_WRITE_BASE 0x28050 | |
| 1880 | #define DB_STENCIL_WRITE_BASE 0x28054 | |
| 1881 | #define DB_DEPTH_SIZE 0x28058 | |
| 285484e2 JG |
1882 | #define R_028058_DB_DEPTH_SIZE 0x028058 |
| 1883 | #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) | |
| 1884 | #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) | |
| 1885 | #define C_028058_PITCH_TILE_MAX 0xFFFFF800 | |
| 1886 | #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) | |
| 1887 | #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) | |
| 1888 | #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF | |
| 1889 | #define R_02805C_DB_DEPTH_SLICE 0x02805C | |
| 1890 | #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) | |
| 1891 | #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) | |
| 1892 | #define C_02805C_SLICE_TILE_MAX 0xFFC00000 | |
| cb5fcbd5 AD |
1893 | |
| 1894 | #define SQ_PGM_START_PS 0x28840 | |
| 1895 | #define SQ_PGM_START_VS 0x2885c | |
| 1896 | #define SQ_PGM_START_GS 0x28874 | |
| 1897 | #define SQ_PGM_START_ES 0x2888c | |
| 1898 | #define SQ_PGM_START_FS 0x288a4 | |
| 1899 | #define SQ_PGM_START_HS 0x288b8 | |
| 1900 | #define SQ_PGM_START_LS 0x288d0 | |
| 1901 | ||
| dd220a00 MO |
1902 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 |
| 1903 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 | |
| 1904 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 | |
| 1905 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 | |
| 1906 | #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 | |
| 1907 | #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 | |
| 1908 | #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 | |
| 1909 | #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 | |
| cb5fcbd5 AD |
1910 | #define VGT_STRMOUT_CONFIG 0x28b94 |
| 1911 | #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 | |
| 1912 | ||
| 1913 | #define CB_TARGET_MASK 0x28238 | |
| 1914 | #define CB_SHADER_MASK 0x2823c | |
| 1915 | ||
| 1916 | #define GDS_ADDR_BASE 0x28720 | |
| 1917 | ||
| 1918 | #define CB_IMMED0_BASE 0x28b9c | |
| 1919 | #define CB_IMMED1_BASE 0x28ba0 | |
| 1920 | #define CB_IMMED2_BASE 0x28ba4 | |
| 1921 | #define CB_IMMED3_BASE 0x28ba8 | |
| 1922 | #define CB_IMMED4_BASE 0x28bac | |
| 1923 | #define CB_IMMED5_BASE 0x28bb0 | |
| 1924 | #define CB_IMMED6_BASE 0x28bb4 | |
| 1925 | #define CB_IMMED7_BASE 0x28bb8 | |
| 1926 | #define CB_IMMED8_BASE 0x28bbc | |
| 1927 | #define CB_IMMED9_BASE 0x28bc0 | |
| 1928 | #define CB_IMMED10_BASE 0x28bc4 | |
| 1929 | #define CB_IMMED11_BASE 0x28bc8 | |
| 1930 | ||
| 1931 | /* all 12 CB blocks have these regs */ | |
| 1932 | #define CB_COLOR0_BASE 0x28c60 | |
| 1933 | #define CB_COLOR0_PITCH 0x28c64 | |
| 1934 | #define CB_COLOR0_SLICE 0x28c68 | |
| 1935 | #define CB_COLOR0_VIEW 0x28c6c | |
| 285484e2 JG |
1936 | #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C |
| 1937 | #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) | |
| 1938 | #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) | |
| 1939 | #define C_028C6C_SLICE_START 0xFFFFF800 | |
| 1940 | #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) | |
| 1941 | #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) | |
| 1942 | #define C_028C6C_SLICE_MAX 0xFF001FFF | |
| 1943 | #define R_028C70_CB_COLOR0_INFO 0x028C70 | |
| 1944 | #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) | |
| 1945 | #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) | |
| 1946 | #define C_028C70_ENDIAN 0xFFFFFFFC | |
| 1947 | #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) | |
| 1948 | #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) | |
| 1949 | #define C_028C70_FORMAT 0xFFFFFF03 | |
| 1950 | #define V_028C70_COLOR_INVALID 0x00000000 | |
| 1951 | #define V_028C70_COLOR_8 0x00000001 | |
| 1952 | #define V_028C70_COLOR_4_4 0x00000002 | |
| 1953 | #define V_028C70_COLOR_3_3_2 0x00000003 | |
| 1954 | #define V_028C70_COLOR_16 0x00000005 | |
| 1955 | #define V_028C70_COLOR_16_FLOAT 0x00000006 | |
| 1956 | #define V_028C70_COLOR_8_8 0x00000007 | |
| 1957 | #define V_028C70_COLOR_5_6_5 0x00000008 | |
| 1958 | #define V_028C70_COLOR_6_5_5 0x00000009 | |
| 1959 | #define V_028C70_COLOR_1_5_5_5 0x0000000A | |
| 1960 | #define V_028C70_COLOR_4_4_4_4 0x0000000B | |
| 1961 | #define V_028C70_COLOR_5_5_5_1 0x0000000C | |
| 1962 | #define V_028C70_COLOR_32 0x0000000D | |
| 1963 | #define V_028C70_COLOR_32_FLOAT 0x0000000E | |
| 1964 | #define V_028C70_COLOR_16_16 0x0000000F | |
| 1965 | #define V_028C70_COLOR_16_16_FLOAT 0x00000010 | |
| 1966 | #define V_028C70_COLOR_8_24 0x00000011 | |
| 1967 | #define V_028C70_COLOR_8_24_FLOAT 0x00000012 | |
| 1968 | #define V_028C70_COLOR_24_8 0x00000013 | |
| 1969 | #define V_028C70_COLOR_24_8_FLOAT 0x00000014 | |
| 1970 | #define V_028C70_COLOR_10_11_11 0x00000015 | |
| 1971 | #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 | |
| 1972 | #define V_028C70_COLOR_11_11_10 0x00000017 | |
| 1973 | #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 | |
| 1974 | #define V_028C70_COLOR_2_10_10_10 0x00000019 | |
| 1975 | #define V_028C70_COLOR_8_8_8_8 0x0000001A | |
| 1976 | #define V_028C70_COLOR_10_10_10_2 0x0000001B | |
| 1977 | #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C | |
| 1978 | #define V_028C70_COLOR_32_32 0x0000001D | |
| 1979 | #define V_028C70_COLOR_32_32_FLOAT 0x0000001E | |
| 1980 | #define V_028C70_COLOR_16_16_16_16 0x0000001F | |
| 1981 | #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 | |
| 1982 | #define V_028C70_COLOR_32_32_32_32 0x00000022 | |
| 1983 | #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 | |
| 1984 | #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 | |
| 1985 | #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) | |
| 1986 | #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) | |
| 1987 | #define C_028C70_ARRAY_MODE 0xFFFFF0FF | |
| 1988 | #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 | |
| 1989 | #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 | |
| 1990 | #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 | |
| 1991 | #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 | |
| 1992 | #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) | |
| 1993 | #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) | |
| 1994 | #define C_028C70_NUMBER_TYPE 0xFFFF8FFF | |
| 1995 | #define V_028C70_NUMBER_UNORM 0x00000000 | |
| 1996 | #define V_028C70_NUMBER_SNORM 0x00000001 | |
| 1997 | #define V_028C70_NUMBER_USCALED 0x00000002 | |
| 1998 | #define V_028C70_NUMBER_SSCALED 0x00000003 | |
| 1999 | #define V_028C70_NUMBER_UINT 0x00000004 | |
| 2000 | #define V_028C70_NUMBER_SINT 0x00000005 | |
| 2001 | #define V_028C70_NUMBER_SRGB 0x00000006 | |
| 2002 | #define V_028C70_NUMBER_FLOAT 0x00000007 | |
| 2003 | #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) | |
| 2004 | #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) | |
| 2005 | #define C_028C70_COMP_SWAP 0xFFFE7FFF | |
| 2006 | #define V_028C70_SWAP_STD 0x00000000 | |
| 2007 | #define V_028C70_SWAP_ALT 0x00000001 | |
| 2008 | #define V_028C70_SWAP_STD_REV 0x00000002 | |
| 2009 | #define V_028C70_SWAP_ALT_REV 0x00000003 | |
| 2010 | #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) | |
| 2011 | #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) | |
| 2012 | #define C_028C70_FAST_CLEAR 0xFFFDFFFF | |
| 2013 | #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) | |
| 2014 | #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) | |
| 2015 | #define C_028C70_COMPRESSION 0xFFF3FFFF | |
| 2016 | #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) | |
| 2017 | #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) | |
| 2018 | #define C_028C70_BLEND_CLAMP 0xFFF7FFFF | |
| 2019 | #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) | |
| 2020 | #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) | |
| 2021 | #define C_028C70_BLEND_BYPASS 0xFFEFFFFF | |
| 2022 | #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) | |
| 2023 | #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) | |
| 2024 | #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF | |
| 2025 | #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) | |
| 2026 | #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) | |
| 2027 | #define C_028C70_ROUND_MODE 0xFFBFFFFF | |
| 2028 | #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) | |
| 2029 | #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) | |
| 2030 | #define C_028C70_TILE_COMPACT 0xFF7FFFFF | |
| 2031 | #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) | |
| 2032 | #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) | |
| 2033 | #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF | |
| 2034 | #define V_028C70_EXPORT_4C_32BPC 0x0 | |
| 2035 | #define V_028C70_EXPORT_4C_16BPC 0x1 | |
| 2036 | #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ | |
| 2037 | #define S_028C70_RAT(x) (((x) & 0x1) << 26) | |
| 2038 | #define G_028C70_RAT(x) (((x) >> 26) & 0x1) | |
| 2039 | #define C_028C70_RAT 0xFBFFFFFF | |
| 2040 | #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) | |
| 2041 | #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) | |
| 2042 | #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF | |
| 2043 | ||
| cb5fcbd5 | 2044 | #define CB_COLOR0_INFO 0x28c70 |
| 6018faf5 | 2045 | # define CB_FORMAT(x) ((x) << 2) |
| cb5fcbd5 AD |
2046 | # define CB_ARRAY_MODE(x) ((x) << 8) |
| 2047 | # define ARRAY_LINEAR_GENERAL 0 | |
| 2048 | # define ARRAY_LINEAR_ALIGNED 1 | |
| 2049 | # define ARRAY_1D_TILED_THIN1 2 | |
| 2050 | # define ARRAY_2D_TILED_THIN1 4 | |
| 6018faf5 IH |
2051 | # define CB_SOURCE_FORMAT(x) ((x) << 24) |
| 2052 | # define CB_SF_EXPORT_FULL 0 | |
| 2053 | # define CB_SF_EXPORT_NORM 1 | |
| 285484e2 JG |
2054 | #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 |
| 2055 | #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) | |
| 2056 | #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) | |
| 2057 | #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF | |
| 2058 | #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) | |
| 2059 | #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) | |
| 2060 | #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) | |
| 2061 | #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) | |
| 2062 | #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) | |
| 2063 | #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) | |
| 2064 | #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) | |
| 2065 | #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) | |
| 2066 | #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) | |
| 2067 | #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) | |
| cb5fcbd5 | 2068 | #define CB_COLOR0_ATTRIB 0x28c74 |
| f3a71df0 AD |
2069 | # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) |
| 2070 | # define ADDR_SURF_TILE_SPLIT_64B 0 | |
| 2071 | # define ADDR_SURF_TILE_SPLIT_128B 1 | |
| 2072 | # define ADDR_SURF_TILE_SPLIT_256B 2 | |
| 2073 | # define ADDR_SURF_TILE_SPLIT_512B 3 | |
| 2074 | # define ADDR_SURF_TILE_SPLIT_1KB 4 | |
| 2075 | # define ADDR_SURF_TILE_SPLIT_2KB 5 | |
| 2076 | # define ADDR_SURF_TILE_SPLIT_4KB 6 | |
| 2077 | # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) | |
| 2078 | # define ADDR_SURF_2_BANK 0 | |
| 2079 | # define ADDR_SURF_4_BANK 1 | |
| 2080 | # define ADDR_SURF_8_BANK 2 | |
| 2081 | # define ADDR_SURF_16_BANK 3 | |
| 2082 | # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) | |
| 2083 | # define ADDR_SURF_BANK_WIDTH_1 0 | |
| 2084 | # define ADDR_SURF_BANK_WIDTH_2 1 | |
| 2085 | # define ADDR_SURF_BANK_WIDTH_4 2 | |
| 2086 | # define ADDR_SURF_BANK_WIDTH_8 3 | |
| 2087 | # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) | |
| 2088 | # define ADDR_SURF_BANK_HEIGHT_1 0 | |
| 2089 | # define ADDR_SURF_BANK_HEIGHT_2 1 | |
| 2090 | # define ADDR_SURF_BANK_HEIGHT_4 2 | |
| 2091 | # define ADDR_SURF_BANK_HEIGHT_8 3 | |
| 285484e2 | 2092 | # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) |
| cb5fcbd5 AD |
2093 | #define CB_COLOR0_DIM 0x28c78 |
| 2094 | /* only CB0-7 blocks have these regs */ | |
| 2095 | #define CB_COLOR0_CMASK 0x28c7c | |
| 2096 | #define CB_COLOR0_CMASK_SLICE 0x28c80 | |
| 2097 | #define CB_COLOR0_FMASK 0x28c84 | |
| 2098 | #define CB_COLOR0_FMASK_SLICE 0x28c88 | |
| 2099 | #define CB_COLOR0_CLEAR_WORD0 0x28c8c | |
| 2100 | #define CB_COLOR0_CLEAR_WORD1 0x28c90 | |
| 2101 | #define CB_COLOR0_CLEAR_WORD2 0x28c94 | |
| 2102 | #define CB_COLOR0_CLEAR_WORD3 0x28c98 | |
| 2103 | ||
| 2104 | #define CB_COLOR1_BASE 0x28c9c | |
| 2105 | #define CB_COLOR2_BASE 0x28cd8 | |
| 2106 | #define CB_COLOR3_BASE 0x28d14 | |
| 2107 | #define CB_COLOR4_BASE 0x28d50 | |
| 2108 | #define CB_COLOR5_BASE 0x28d8c | |
| 2109 | #define CB_COLOR6_BASE 0x28dc8 | |
| 2110 | #define CB_COLOR7_BASE 0x28e04 | |
| 2111 | #define CB_COLOR8_BASE 0x28e40 | |
| 2112 | #define CB_COLOR9_BASE 0x28e5c | |
| 2113 | #define CB_COLOR10_BASE 0x28e78 | |
| 2114 | #define CB_COLOR11_BASE 0x28e94 | |
| 2115 | ||
| 2116 | #define CB_COLOR1_PITCH 0x28ca0 | |
| 2117 | #define CB_COLOR2_PITCH 0x28cdc | |
| 2118 | #define CB_COLOR3_PITCH 0x28d18 | |
| 2119 | #define CB_COLOR4_PITCH 0x28d54 | |
| 2120 | #define CB_COLOR5_PITCH 0x28d90 | |
| 2121 | #define CB_COLOR6_PITCH 0x28dcc | |
| 2122 | #define CB_COLOR7_PITCH 0x28e08 | |
| 2123 | #define CB_COLOR8_PITCH 0x28e44 | |
| 2124 | #define CB_COLOR9_PITCH 0x28e60 | |
| 2125 | #define CB_COLOR10_PITCH 0x28e7c | |
| 2126 | #define CB_COLOR11_PITCH 0x28e98 | |
| 2127 | ||
| 2128 | #define CB_COLOR1_SLICE 0x28ca4 | |
| 2129 | #define CB_COLOR2_SLICE 0x28ce0 | |
| 2130 | #define CB_COLOR3_SLICE 0x28d1c | |
| 2131 | #define CB_COLOR4_SLICE 0x28d58 | |
| 2132 | #define CB_COLOR5_SLICE 0x28d94 | |
| 2133 | #define CB_COLOR6_SLICE 0x28dd0 | |
| 2134 | #define CB_COLOR7_SLICE 0x28e0c | |
| 2135 | #define CB_COLOR8_SLICE 0x28e48 | |
| 2136 | #define CB_COLOR9_SLICE 0x28e64 | |
| 2137 | #define CB_COLOR10_SLICE 0x28e80 | |
| 2138 | #define CB_COLOR11_SLICE 0x28e9c | |
| 2139 | ||
| 2140 | #define CB_COLOR1_VIEW 0x28ca8 | |
| 2141 | #define CB_COLOR2_VIEW 0x28ce4 | |
| 2142 | #define CB_COLOR3_VIEW 0x28d20 | |
| 2143 | #define CB_COLOR4_VIEW 0x28d5c | |
| 2144 | #define CB_COLOR5_VIEW 0x28d98 | |
| 2145 | #define CB_COLOR6_VIEW 0x28dd4 | |
| 2146 | #define CB_COLOR7_VIEW 0x28e10 | |
| 2147 | #define CB_COLOR8_VIEW 0x28e4c | |
| 2148 | #define CB_COLOR9_VIEW 0x28e68 | |
| 2149 | #define CB_COLOR10_VIEW 0x28e84 | |
| 2150 | #define CB_COLOR11_VIEW 0x28ea0 | |
| 2151 | ||
| 2152 | #define CB_COLOR1_INFO 0x28cac | |
| 2153 | #define CB_COLOR2_INFO 0x28ce8 | |
| 2154 | #define CB_COLOR3_INFO 0x28d24 | |
| 2155 | #define CB_COLOR4_INFO 0x28d60 | |
| 2156 | #define CB_COLOR5_INFO 0x28d9c | |
| 2157 | #define CB_COLOR6_INFO 0x28dd8 | |
| 2158 | #define CB_COLOR7_INFO 0x28e14 | |
| 2159 | #define CB_COLOR8_INFO 0x28e50 | |
| 2160 | #define CB_COLOR9_INFO 0x28e6c | |
| 2161 | #define CB_COLOR10_INFO 0x28e88 | |
| 2162 | #define CB_COLOR11_INFO 0x28ea4 | |
| 2163 | ||
| 2164 | #define CB_COLOR1_ATTRIB 0x28cb0 | |
| 2165 | #define CB_COLOR2_ATTRIB 0x28cec | |
| 2166 | #define CB_COLOR3_ATTRIB 0x28d28 | |
| 2167 | #define CB_COLOR4_ATTRIB 0x28d64 | |
| 2168 | #define CB_COLOR5_ATTRIB 0x28da0 | |
| 2169 | #define CB_COLOR6_ATTRIB 0x28ddc | |
| 2170 | #define CB_COLOR7_ATTRIB 0x28e18 | |
| 2171 | #define CB_COLOR8_ATTRIB 0x28e54 | |
| 2172 | #define CB_COLOR9_ATTRIB 0x28e70 | |
| 2173 | #define CB_COLOR10_ATTRIB 0x28e8c | |
| 2174 | #define CB_COLOR11_ATTRIB 0x28ea8 | |
| 2175 | ||
| 2176 | #define CB_COLOR1_DIM 0x28cb4 | |
| 2177 | #define CB_COLOR2_DIM 0x28cf0 | |
| 2178 | #define CB_COLOR3_DIM 0x28d2c | |
| 2179 | #define CB_COLOR4_DIM 0x28d68 | |
| 2180 | #define CB_COLOR5_DIM 0x28da4 | |
| 2181 | #define CB_COLOR6_DIM 0x28de0 | |
| 2182 | #define CB_COLOR7_DIM 0x28e1c | |
| 2183 | #define CB_COLOR8_DIM 0x28e58 | |
| 2184 | #define CB_COLOR9_DIM 0x28e74 | |
| 2185 | #define CB_COLOR10_DIM 0x28e90 | |
| 2186 | #define CB_COLOR11_DIM 0x28eac | |
| 2187 | ||
| 2188 | #define CB_COLOR1_CMASK 0x28cb8 | |
| 2189 | #define CB_COLOR2_CMASK 0x28cf4 | |
| 2190 | #define CB_COLOR3_CMASK 0x28d30 | |
| 2191 | #define CB_COLOR4_CMASK 0x28d6c | |
| 2192 | #define CB_COLOR5_CMASK 0x28da8 | |
| 2193 | #define CB_COLOR6_CMASK 0x28de4 | |
| 2194 | #define CB_COLOR7_CMASK 0x28e20 | |
| 2195 | ||
| 2196 | #define CB_COLOR1_CMASK_SLICE 0x28cbc | |
| 2197 | #define CB_COLOR2_CMASK_SLICE 0x28cf8 | |
| 2198 | #define CB_COLOR3_CMASK_SLICE 0x28d34 | |
| 2199 | #define CB_COLOR4_CMASK_SLICE 0x28d70 | |
| 2200 | #define CB_COLOR5_CMASK_SLICE 0x28dac | |
| 2201 | #define CB_COLOR6_CMASK_SLICE 0x28de8 | |
| 2202 | #define CB_COLOR7_CMASK_SLICE 0x28e24 | |
| 2203 | ||
| 2204 | #define CB_COLOR1_FMASK 0x28cc0 | |
| 2205 | #define CB_COLOR2_FMASK 0x28cfc | |
| 2206 | #define CB_COLOR3_FMASK 0x28d38 | |
| 2207 | #define CB_COLOR4_FMASK 0x28d74 | |
| 2208 | #define CB_COLOR5_FMASK 0x28db0 | |
| 2209 | #define CB_COLOR6_FMASK 0x28dec | |
| 2210 | #define CB_COLOR7_FMASK 0x28e28 | |
| 2211 | ||
| 2212 | #define CB_COLOR1_FMASK_SLICE 0x28cc4 | |
| 2213 | #define CB_COLOR2_FMASK_SLICE 0x28d00 | |
| 2214 | #define CB_COLOR3_FMASK_SLICE 0x28d3c | |
| 2215 | #define CB_COLOR4_FMASK_SLICE 0x28d78 | |
| 2216 | #define CB_COLOR5_FMASK_SLICE 0x28db4 | |
| 2217 | #define CB_COLOR6_FMASK_SLICE 0x28df0 | |
| 2218 | #define CB_COLOR7_FMASK_SLICE 0x28e2c | |
| 2219 | ||
| 2220 | #define CB_COLOR1_CLEAR_WORD0 0x28cc8 | |
| 2221 | #define CB_COLOR2_CLEAR_WORD0 0x28d04 | |
| 2222 | #define CB_COLOR3_CLEAR_WORD0 0x28d40 | |
| 2223 | #define CB_COLOR4_CLEAR_WORD0 0x28d7c | |
| 2224 | #define CB_COLOR5_CLEAR_WORD0 0x28db8 | |
| 2225 | #define CB_COLOR6_CLEAR_WORD0 0x28df4 | |
| 2226 | #define CB_COLOR7_CLEAR_WORD0 0x28e30 | |
| 2227 | ||
| 2228 | #define CB_COLOR1_CLEAR_WORD1 0x28ccc | |
| 2229 | #define CB_COLOR2_CLEAR_WORD1 0x28d08 | |
| 2230 | #define CB_COLOR3_CLEAR_WORD1 0x28d44 | |
| 2231 | #define CB_COLOR4_CLEAR_WORD1 0x28d80 | |
| 2232 | #define CB_COLOR5_CLEAR_WORD1 0x28dbc | |
| 2233 | #define CB_COLOR6_CLEAR_WORD1 0x28df8 | |
| 2234 | #define CB_COLOR7_CLEAR_WORD1 0x28e34 | |
| 2235 | ||
| 2236 | #define CB_COLOR1_CLEAR_WORD2 0x28cd0 | |
| 2237 | #define CB_COLOR2_CLEAR_WORD2 0x28d0c | |
| 2238 | #define CB_COLOR3_CLEAR_WORD2 0x28d48 | |
| 2239 | #define CB_COLOR4_CLEAR_WORD2 0x28d84 | |
| 2240 | #define CB_COLOR5_CLEAR_WORD2 0x28dc0 | |
| 2241 | #define CB_COLOR6_CLEAR_WORD2 0x28dfc | |
| 2242 | #define CB_COLOR7_CLEAR_WORD2 0x28e38 | |
| 2243 | ||
| 2244 | #define CB_COLOR1_CLEAR_WORD3 0x28cd4 | |
| 2245 | #define CB_COLOR2_CLEAR_WORD3 0x28d10 | |
| 2246 | #define CB_COLOR3_CLEAR_WORD3 0x28d4c | |
| 2247 | #define CB_COLOR4_CLEAR_WORD3 0x28d88 | |
| 2248 | #define CB_COLOR5_CLEAR_WORD3 0x28dc4 | |
| 2249 | #define CB_COLOR6_CLEAR_WORD3 0x28e00 | |
| 2250 | #define CB_COLOR7_CLEAR_WORD3 0x28e3c | |
| 2251 | ||
| 2252 | #define SQ_TEX_RESOURCE_WORD0_0 0x30000 | |
| 6018faf5 IH |
2253 | # define TEX_DIM(x) ((x) << 0) |
| 2254 | # define SQ_TEX_DIM_1D 0 | |
| 2255 | # define SQ_TEX_DIM_2D 1 | |
| 2256 | # define SQ_TEX_DIM_3D 2 | |
| 2257 | # define SQ_TEX_DIM_CUBEMAP 3 | |
| 2258 | # define SQ_TEX_DIM_1D_ARRAY 4 | |
| 2259 | # define SQ_TEX_DIM_2D_ARRAY 5 | |
| 2260 | # define SQ_TEX_DIM_2D_MSAA 6 | |
| 2261 | # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 | |
| cb5fcbd5 AD |
2262 | #define SQ_TEX_RESOURCE_WORD1_0 0x30004 |
| 2263 | # define TEX_ARRAY_MODE(x) ((x) << 28) | |
| 2264 | #define SQ_TEX_RESOURCE_WORD2_0 0x30008 | |
| 2265 | #define SQ_TEX_RESOURCE_WORD3_0 0x3000C | |
| 2266 | #define SQ_TEX_RESOURCE_WORD4_0 0x30010 | |
| 6018faf5 IH |
2267 | # define TEX_DST_SEL_X(x) ((x) << 16) |
| 2268 | # define TEX_DST_SEL_Y(x) ((x) << 19) | |
| 2269 | # define TEX_DST_SEL_Z(x) ((x) << 22) | |
| 2270 | # define TEX_DST_SEL_W(x) ((x) << 25) | |
| 2271 | # define SQ_SEL_X 0 | |
| 2272 | # define SQ_SEL_Y 1 | |
| 2273 | # define SQ_SEL_Z 2 | |
| 2274 | # define SQ_SEL_W 3 | |
| 2275 | # define SQ_SEL_0 4 | |
| 2276 | # define SQ_SEL_1 5 | |
| cb5fcbd5 AD |
2277 | #define SQ_TEX_RESOURCE_WORD5_0 0x30014 |
| 2278 | #define SQ_TEX_RESOURCE_WORD6_0 0x30018 | |
| f3a71df0 | 2279 | # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) |
| cb5fcbd5 | 2280 | #define SQ_TEX_RESOURCE_WORD7_0 0x3001c |
| 285484e2 | 2281 | # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) |
| f3a71df0 AD |
2282 | # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) |
| 2283 | # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) | |
| 2284 | # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) | |
| 285484e2 JG |
2285 | #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 |
| 2286 | #define S_030000_DIM(x) (((x) & 0x7) << 0) | |
| 2287 | #define G_030000_DIM(x) (((x) >> 0) & 0x7) | |
| 2288 | #define C_030000_DIM 0xFFFFFFF8 | |
| 2289 | #define V_030000_SQ_TEX_DIM_1D 0x00000000 | |
| 2290 | #define V_030000_SQ_TEX_DIM_2D 0x00000001 | |
| 2291 | #define V_030000_SQ_TEX_DIM_3D 0x00000002 | |
| 2292 | #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 | |
| 2293 | #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 | |
| 2294 | #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 | |
| 2295 | #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 | |
| 2296 | #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 | |
| 2297 | #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) | |
| 2298 | #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) | |
| 2299 | #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF | |
| 2300 | #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) | |
| 2301 | #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) | |
| 2302 | #define C_030000_PITCH 0xFFFC003F | |
| 2303 | #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) | |
| 2304 | #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) | |
| 2305 | #define C_030000_TEX_WIDTH 0x0003FFFF | |
| 2306 | #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 | |
| 2307 | #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) | |
| 2308 | #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) | |
| 2309 | #define C_030004_TEX_HEIGHT 0xFFFFC000 | |
| 2310 | #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) | |
| 2311 | #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) | |
| 2312 | #define C_030004_TEX_DEPTH 0xF8003FFF | |
| 2313 | #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) | |
| 2314 | #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) | |
| 2315 | #define C_030004_ARRAY_MODE 0x0FFFFFFF | |
| 2316 | #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 | |
| 2317 | #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | |
| 2318 | #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | |
| 2319 | #define C_030008_BASE_ADDRESS 0x00000000 | |
| 2320 | #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C | |
| 2321 | #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | |
| 2322 | #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | |
| 2323 | #define C_03000C_MIP_ADDRESS 0x00000000 | |
| 2324 | #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 | |
| 2325 | #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) | |
| 2326 | #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) | |
| 2327 | #define C_030010_FORMAT_COMP_X 0xFFFFFFFC | |
| 2328 | #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 | |
| 2329 | #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 | |
| 2330 | #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 | |
| 2331 | #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) | |
| 2332 | #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) | |
| 2333 | #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 | |
| 2334 | #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) | |
| 2335 | #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) | |
| 2336 | #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF | |
| 2337 | #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) | |
| 2338 | #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) | |
| 2339 | #define C_030010_FORMAT_COMP_W 0xFFFFFF3F | |
| 2340 | #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) | |
| 2341 | #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) | |
| 2342 | #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF | |
| 2343 | #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 | |
| 2344 | #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 | |
| 2345 | #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 | |
| 2346 | #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) | |
| 2347 | #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) | |
| 2348 | #define C_030010_SRF_MODE_ALL 0xFFFFFBFF | |
| 2349 | #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 | |
| 2350 | #define V_030010_SRF_MODE_NO_ZERO 0x00000001 | |
| 2351 | #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) | |
| 2352 | #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) | |
| 2353 | #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF | |
| 2354 | #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) | |
| 2355 | #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) | |
| 2356 | #define C_030010_ENDIAN_SWAP 0xFFFFCFFF | |
| 2357 | #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) | |
| 2358 | #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) | |
| 2359 | #define C_030010_DST_SEL_X 0xFFF8FFFF | |
| 2360 | #define V_030010_SQ_SEL_X 0x00000000 | |
| 2361 | #define V_030010_SQ_SEL_Y 0x00000001 | |
| 2362 | #define V_030010_SQ_SEL_Z 0x00000002 | |
| 2363 | #define V_030010_SQ_SEL_W 0x00000003 | |
| 2364 | #define V_030010_SQ_SEL_0 0x00000004 | |
| 2365 | #define V_030010_SQ_SEL_1 0x00000005 | |
| 2366 | #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) | |
| 2367 | #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) | |
| 2368 | #define C_030010_DST_SEL_Y 0xFFC7FFFF | |
| 2369 | #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) | |
| 2370 | #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) | |
| 2371 | #define C_030010_DST_SEL_Z 0xFE3FFFFF | |
| 2372 | #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) | |
| 2373 | #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) | |
| 2374 | #define C_030010_DST_SEL_W 0xF1FFFFFF | |
| 2375 | #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) | |
| 2376 | #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) | |
| 2377 | #define C_030010_BASE_LEVEL 0x0FFFFFFF | |
| 2378 | #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 | |
| 2379 | #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) | |
| 2380 | #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) | |
| 2381 | #define C_030014_LAST_LEVEL 0xFFFFFFF0 | |
| 2382 | #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) | |
| 2383 | #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) | |
| 2384 | #define C_030014_BASE_ARRAY 0xFFFE000F | |
| 2385 | #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) | |
| 2386 | #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) | |
| 2387 | #define C_030014_LAST_ARRAY 0xC001FFFF | |
| 2388 | #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 | |
| 2389 | #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) | |
| 2390 | #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) | |
| 2391 | #define C_030018_MAX_ANISO 0xFFFFFFF8 | |
| 2392 | #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) | |
| 2393 | #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) | |
| 2394 | #define C_030018_PERF_MODULATION 0xFFFFFFC7 | |
| 2395 | #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) | |
| 2396 | #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) | |
| 2397 | #define C_030018_INTERLACED 0xFFFFFFBF | |
| 2398 | #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) | |
| 2399 | #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) | |
| 2400 | #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C | |
| 2401 | #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) | |
| 2402 | #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) | |
| 2403 | #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) | |
| 2404 | #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) | |
| 2405 | #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) | |
| 2406 | #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) | |
| 2407 | #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) | |
| 2408 | #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) | |
| 2409 | #define S_03001C_TYPE(x) (((x) & 0x3) << 30) | |
| 2410 | #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) | |
| 2411 | #define C_03001C_TYPE 0x3FFFFFFF | |
| 2412 | #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 | |
| 2413 | #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 | |
| 2414 | #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 | |
| 2415 | #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 | |
| 2416 | #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) | |
| 2417 | #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) | |
| 2418 | #define C_03001C_DATA_FORMAT 0xFFFFFFC0 | |
| cb5fcbd5 | 2419 | |
| 6018faf5 IH |
2420 | #define SQ_VTX_CONSTANT_WORD0_0 0x30000 |
| 2421 | #define SQ_VTX_CONSTANT_WORD1_0 0x30004 | |
| 2422 | #define SQ_VTX_CONSTANT_WORD2_0 0x30008 | |
| 2423 | # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) | |
| 2424 | # define SQ_VTXC_STRIDE(x) ((x) << 8) | |
| 2425 | # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) | |
| 2426 | # define SQ_ENDIAN_NONE 0 | |
| 2427 | # define SQ_ENDIAN_8IN16 1 | |
| 2428 | # define SQ_ENDIAN_8IN32 2 | |
| 2429 | #define SQ_VTX_CONSTANT_WORD3_0 0x3000C | |
| 2430 | # define SQ_VTCX_SEL_X(x) ((x) << 3) | |
| 2431 | # define SQ_VTCX_SEL_Y(x) ((x) << 6) | |
| 2432 | # define SQ_VTCX_SEL_Z(x) ((x) << 9) | |
| 2433 | # define SQ_VTCX_SEL_W(x) ((x) << 12) | |
| 2434 | #define SQ_VTX_CONSTANT_WORD4_0 0x30010 | |
| 2435 | #define SQ_VTX_CONSTANT_WORD5_0 0x30014 | |
| 2436 | #define SQ_VTX_CONSTANT_WORD6_0 0x30018 | |
| 2437 | #define SQ_VTX_CONSTANT_WORD7_0 0x3001c | |
| 2438 | ||
| 721604a1 JG |
2439 | #define TD_PS_BORDER_COLOR_INDEX 0xA400 |
| 2440 | #define TD_PS_BORDER_COLOR_RED 0xA404 | |
| 2441 | #define TD_PS_BORDER_COLOR_GREEN 0xA408 | |
| 2442 | #define TD_PS_BORDER_COLOR_BLUE 0xA40C | |
| 2443 | #define TD_PS_BORDER_COLOR_ALPHA 0xA410 | |
| 2444 | #define TD_VS_BORDER_COLOR_INDEX 0xA414 | |
| 2445 | #define TD_VS_BORDER_COLOR_RED 0xA418 | |
| 2446 | #define TD_VS_BORDER_COLOR_GREEN 0xA41C | |
| 2447 | #define TD_VS_BORDER_COLOR_BLUE 0xA420 | |
| 2448 | #define TD_VS_BORDER_COLOR_ALPHA 0xA424 | |
| 2449 | #define TD_GS_BORDER_COLOR_INDEX 0xA428 | |
| 2450 | #define TD_GS_BORDER_COLOR_RED 0xA42C | |
| 2451 | #define TD_GS_BORDER_COLOR_GREEN 0xA430 | |
| 2452 | #define TD_GS_BORDER_COLOR_BLUE 0xA434 | |
| 2453 | #define TD_GS_BORDER_COLOR_ALPHA 0xA438 | |
| 2454 | #define TD_HS_BORDER_COLOR_INDEX 0xA43C | |
| 2455 | #define TD_HS_BORDER_COLOR_RED 0xA440 | |
| 2456 | #define TD_HS_BORDER_COLOR_GREEN 0xA444 | |
| 2457 | #define TD_HS_BORDER_COLOR_BLUE 0xA448 | |
| 2458 | #define TD_HS_BORDER_COLOR_ALPHA 0xA44C | |
| 2459 | #define TD_LS_BORDER_COLOR_INDEX 0xA450 | |
| 2460 | #define TD_LS_BORDER_COLOR_RED 0xA454 | |
| 2461 | #define TD_LS_BORDER_COLOR_GREEN 0xA458 | |
| 2462 | #define TD_LS_BORDER_COLOR_BLUE 0xA45C | |
| 2463 | #define TD_LS_BORDER_COLOR_ALPHA 0xA460 | |
| 2464 | #define TD_CS_BORDER_COLOR_INDEX 0xA464 | |
| 2465 | #define TD_CS_BORDER_COLOR_RED 0xA468 | |
| 2466 | #define TD_CS_BORDER_COLOR_GREEN 0xA46C | |
| 2467 | #define TD_CS_BORDER_COLOR_BLUE 0xA470 | |
| 2468 | #define TD_CS_BORDER_COLOR_ALPHA 0xA474 | |
| 2469 | ||
| c175ca9a | 2470 | /* cayman 3D regs */ |
| 721604a1 JG |
2471 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 |
| 2472 | #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 | |
| c175ca9a AD |
2473 | #define CAYMAN_DB_EQAA 0x28804 |
| 2474 | #define CAYMAN_DB_DEPTH_INFO 0x2803C | |
| 2475 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 | |
| 2476 | #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 | |
| 2477 | #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 | |
| 033b5650 | 2478 | #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 |
| c175ca9a AD |
2479 | /* cayman packet3 addition */ |
| 2480 | #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 | |
| cb5fcbd5 | 2481 | |
| eaaa6983 | 2482 | /* DMA regs common on r6xx/r7xx/evergreen/ni */ |
| 64c56e8c JG |
2483 | #define DMA_RB_CNTL 0xd000 |
| 2484 | # define DMA_RB_ENABLE (1 << 0) | |
| 2485 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ | |
| 2486 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | |
| 2487 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) | |
| 2488 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | |
| 2489 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | |
| eaaa6983 | 2490 | #define DMA_STATUS_REG 0xd034 |
| 0ecebb9e | 2491 | # define DMA_IDLE (1 << 0) |
| eaaa6983 | 2492 | |
| 0fcdb61e | 2493 | #endif |