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0fcdb61e AD |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #ifndef EVERGREEND_H | |
25 | #define EVERGREEND_H | |
26 | ||
32fcdbf4 AD |
27 | #define EVERGREEN_MAX_SH_GPRS 256 |
28 | #define EVERGREEN_MAX_TEMP_GPRS 16 | |
29 | #define EVERGREEN_MAX_SH_THREADS 256 | |
30 | #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 | |
31 | #define EVERGREEN_MAX_FRC_EOV_CNT 16384 | |
32 | #define EVERGREEN_MAX_BACKENDS 8 | |
33 | #define EVERGREEN_MAX_BACKENDS_MASK 0xFF | |
34 | #define EVERGREEN_MAX_SIMDS 16 | |
35 | #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF | |
36 | #define EVERGREEN_MAX_PIPES 8 | |
37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF | |
38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF | |
39 | ||
416a2bd2 AD |
40 | #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 |
41 | #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 | |
42 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 | |
43 | #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
44 | #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
45 | #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
46 | #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 | |
47 | #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 | |
bd25f078 JG |
48 | #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
49 | #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 | |
416a2bd2 | 50 | |
dc50ba7f AD |
51 | /* pm registers */ |
52 | #define SMC_MSG 0x20c | |
53 | #define HOST_SMC_MSG(x) ((x) << 0) | |
54 | #define HOST_SMC_MSG_MASK (0xff << 0) | |
55 | #define HOST_SMC_MSG_SHIFT 0 | |
56 | #define HOST_SMC_RESP(x) ((x) << 8) | |
57 | #define HOST_SMC_RESP_MASK (0xff << 8) | |
58 | #define HOST_SMC_RESP_SHIFT 8 | |
59 | #define SMC_HOST_MSG(x) ((x) << 16) | |
60 | #define SMC_HOST_MSG_MASK (0xff << 16) | |
61 | #define SMC_HOST_MSG_SHIFT 16 | |
62 | #define SMC_HOST_RESP(x) ((x) << 24) | |
63 | #define SMC_HOST_RESP_MASK (0xff << 24) | |
64 | #define SMC_HOST_RESP_SHIFT 24 | |
65 | ||
66 | #define DCCG_DISP_SLOW_SELECT_REG 0x4fc | |
67 | #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) | |
68 | #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) | |
69 | #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 | |
70 | #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) | |
71 | #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) | |
72 | #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 | |
73 | ||
74 | #define CG_SPLL_FUNC_CNTL 0x600 | |
75 | #define SPLL_RESET (1 << 0) | |
76 | #define SPLL_SLEEP (1 << 1) | |
77 | #define SPLL_BYPASS_EN (1 << 3) | |
78 | #define SPLL_REF_DIV(x) ((x) << 4) | |
79 | #define SPLL_REF_DIV_MASK (0x3f << 4) | |
80 | #define SPLL_PDIV_A(x) ((x) << 20) | |
81 | #define SPLL_PDIV_A_MASK (0x7f << 20) | |
82 | #define CG_SPLL_FUNC_CNTL_2 0x604 | |
83 | #define SCLK_MUX_SEL(x) ((x) << 0) | |
84 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | |
b5470b03 | 85 | #define SCLK_MUX_UPDATE (1 << 26) |
dc50ba7f AD |
86 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
87 | #define SPLL_FB_DIV(x) ((x) << 0) | |
88 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | |
89 | #define SPLL_DITHEN (1 << 28) | |
b5470b03 AD |
90 | #define CG_SPLL_STATUS 0x60c |
91 | #define SPLL_CHG_STATUS (1 << 1) | |
dc50ba7f AD |
92 | |
93 | #define MPLL_CNTL_MODE 0x61c | |
b5470b03 | 94 | # define MPLL_MCLK_SEL (1 << 11) |
dc50ba7f AD |
95 | # define SS_SSEN (1 << 24) |
96 | # define SS_DSMODE_EN (1 << 25) | |
97 | ||
98 | #define MPLL_AD_FUNC_CNTL 0x624 | |
99 | #define CLKF(x) ((x) << 0) | |
100 | #define CLKF_MASK (0x7f << 0) | |
101 | #define CLKR(x) ((x) << 7) | |
102 | #define CLKR_MASK (0x1f << 7) | |
103 | #define CLKFRAC(x) ((x) << 12) | |
104 | #define CLKFRAC_MASK (0x1f << 12) | |
105 | #define YCLK_POST_DIV(x) ((x) << 17) | |
106 | #define YCLK_POST_DIV_MASK (3 << 17) | |
107 | #define IBIAS(x) ((x) << 20) | |
108 | #define IBIAS_MASK (0x3ff << 20) | |
109 | #define RESET (1 << 30) | |
110 | #define PDNB (1 << 31) | |
111 | #define MPLL_AD_FUNC_CNTL_2 0x628 | |
112 | #define BYPASS (1 << 19) | |
113 | #define BIAS_GEN_PDNB (1 << 24) | |
114 | #define RESET_EN (1 << 25) | |
115 | #define VCO_MODE (1 << 29) | |
116 | #define MPLL_DQ_FUNC_CNTL 0x62c | |
117 | #define MPLL_DQ_FUNC_CNTL_2 0x630 | |
118 | ||
119 | #define GENERAL_PWRMGT 0x63c | |
120 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
121 | # define STATIC_PM_EN (1 << 1) | |
122 | # define THERMAL_PROTECTION_DIS (1 << 2) | |
123 | # define THERMAL_PROTECTION_TYPE (1 << 3) | |
124 | # define ENABLE_GEN2PCIE (1 << 4) | |
125 | # define ENABLE_GEN2XSP (1 << 5) | |
126 | # define SW_SMIO_INDEX(x) ((x) << 6) | |
127 | # define SW_SMIO_INDEX_MASK (3 << 6) | |
128 | # define SW_SMIO_INDEX_SHIFT 6 | |
129 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
130 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
131 | # define VOLT_PWRMGT_EN (1 << 10) | |
132 | # define BACKBIAS_PAD_EN (1 << 18) | |
133 | # define BACKBIAS_VALUE (1 << 19) | |
134 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
135 | # define AC_DC_SW (1 << 24) | |
136 | ||
137 | #define SCLK_PWRMGT_CNTL 0x644 | |
138 | # define SCLK_PWRMGT_OFF (1 << 0) | |
139 | # define SCLK_LOW_D1 (1 << 1) | |
140 | # define FIR_RESET (1 << 4) | |
141 | # define FIR_FORCE_TREND_SEL (1 << 5) | |
142 | # define FIR_TREND_MODE (1 << 6) | |
143 | # define DYN_GFX_CLK_OFF_EN (1 << 7) | |
144 | # define GFX_CLK_FORCE_ON (1 << 8) | |
145 | # define GFX_CLK_REQUEST_OFF (1 << 9) | |
146 | # define GFX_CLK_FORCE_OFF (1 << 10) | |
147 | # define GFX_CLK_OFF_ACPI_D1 (1 << 11) | |
148 | # define GFX_CLK_OFF_ACPI_D2 (1 << 12) | |
149 | # define GFX_CLK_OFF_ACPI_D3 (1 << 13) | |
150 | # define DYN_LIGHT_SLEEP_EN (1 << 14) | |
151 | #define MCLK_PWRMGT_CNTL 0x648 | |
152 | # define DLL_SPEED(x) ((x) << 0) | |
153 | # define DLL_SPEED_MASK (0x1f << 0) | |
154 | # define MPLL_PWRMGT_OFF (1 << 5) | |
155 | # define DLL_READY (1 << 6) | |
156 | # define MC_INT_CNTL (1 << 7) | |
157 | # define MRDCKA0_PDNB (1 << 8) | |
158 | # define MRDCKA1_PDNB (1 << 9) | |
159 | # define MRDCKB0_PDNB (1 << 10) | |
160 | # define MRDCKB1_PDNB (1 << 11) | |
161 | # define MRDCKC0_PDNB (1 << 12) | |
162 | # define MRDCKC1_PDNB (1 << 13) | |
163 | # define MRDCKD0_PDNB (1 << 14) | |
164 | # define MRDCKD1_PDNB (1 << 15) | |
165 | # define MRDCKA0_RESET (1 << 16) | |
166 | # define MRDCKA1_RESET (1 << 17) | |
167 | # define MRDCKB0_RESET (1 << 18) | |
168 | # define MRDCKB1_RESET (1 << 19) | |
169 | # define MRDCKC0_RESET (1 << 20) | |
170 | # define MRDCKC1_RESET (1 << 21) | |
171 | # define MRDCKD0_RESET (1 << 22) | |
172 | # define MRDCKD1_RESET (1 << 23) | |
173 | # define DLL_READY_READ (1 << 24) | |
174 | # define USE_DISPLAY_GAP (1 << 25) | |
175 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) | |
176 | # define MPLL_TURNOFF_D2 (1 << 28) | |
177 | #define DLL_CNTL 0x64c | |
178 | # define MRDCKA0_BYPASS (1 << 24) | |
179 | # define MRDCKA1_BYPASS (1 << 25) | |
180 | # define MRDCKB0_BYPASS (1 << 26) | |
181 | # define MRDCKB1_BYPASS (1 << 27) | |
182 | # define MRDCKC0_BYPASS (1 << 28) | |
183 | # define MRDCKC1_BYPASS (1 << 29) | |
184 | # define MRDCKD0_BYPASS (1 << 30) | |
185 | # define MRDCKD1_BYPASS (1 << 31) | |
186 | ||
187 | #define CG_AT 0x6d4 | |
188 | # define CG_R(x) ((x) << 0) | |
189 | # define CG_R_MASK (0xffff << 0) | |
190 | # define CG_L(x) ((x) << 16) | |
191 | # define CG_L_MASK (0xffff << 16) | |
192 | ||
193 | #define CG_DISPLAY_GAP_CNTL 0x714 | |
194 | # define DISP1_GAP(x) ((x) << 0) | |
195 | # define DISP1_GAP_MASK (3 << 0) | |
196 | # define DISP2_GAP(x) ((x) << 2) | |
197 | # define DISP2_GAP_MASK (3 << 2) | |
198 | # define VBI_TIMER_COUNT(x) ((x) << 4) | |
199 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) | |
200 | # define VBI_TIMER_UNIT(x) ((x) << 20) | |
201 | # define VBI_TIMER_UNIT_MASK (7 << 20) | |
202 | # define DISP1_GAP_MCHG(x) ((x) << 24) | |
203 | # define DISP1_GAP_MCHG_MASK (3 << 24) | |
204 | # define DISP2_GAP_MCHG(x) ((x) << 26) | |
205 | # define DISP2_GAP_MCHG_MASK (3 << 26) | |
206 | ||
207 | #define CG_BIF_REQ_AND_RSP 0x7f4 | |
208 | #define CG_CLIENT_REQ(x) ((x) << 0) | |
209 | #define CG_CLIENT_REQ_MASK (0xff << 0) | |
210 | #define CG_CLIENT_REQ_SHIFT 0 | |
211 | #define CG_CLIENT_RESP(x) ((x) << 8) | |
212 | #define CG_CLIENT_RESP_MASK (0xff << 8) | |
213 | #define CG_CLIENT_RESP_SHIFT 8 | |
214 | #define CLIENT_CG_REQ(x) ((x) << 16) | |
215 | #define CLIENT_CG_REQ_MASK (0xff << 16) | |
216 | #define CLIENT_CG_REQ_SHIFT 16 | |
217 | #define CLIENT_CG_RESP(x) ((x) << 24) | |
218 | #define CLIENT_CG_RESP_MASK (0xff << 24) | |
219 | #define CLIENT_CG_RESP_SHIFT 24 | |
220 | ||
221 | #define CG_SPLL_SPREAD_SPECTRUM 0x790 | |
222 | #define SSEN (1 << 0) | |
223 | #define CG_SPLL_SPREAD_SPECTRUM_2 0x794 | |
224 | ||
225 | #define MPLL_SS1 0x85c | |
226 | #define CLKV(x) ((x) << 0) | |
227 | #define CLKV_MASK (0x3ffffff << 0) | |
228 | #define MPLL_SS2 0x860 | |
229 | #define CLKS(x) ((x) << 0) | |
230 | #define CLKS_MASK (0xfff << 0) | |
231 | ||
232 | #define CG_IND_ADDR 0x8f8 | |
233 | #define CG_IND_DATA 0x8fc | |
234 | /* CGIND regs */ | |
235 | #define CG_CGTT_LOCAL_0 0x00 | |
236 | #define CG_CGTT_LOCAL_1 0x01 | |
237 | #define CG_CGTT_LOCAL_2 0x02 | |
238 | #define CG_CGTT_LOCAL_3 0x03 | |
239 | #define CG_CGLS_TILE_0 0x20 | |
240 | #define CG_CGLS_TILE_1 0x21 | |
241 | #define CG_CGLS_TILE_2 0x22 | |
242 | #define CG_CGLS_TILE_3 0x23 | |
243 | #define CG_CGLS_TILE_4 0x24 | |
244 | #define CG_CGLS_TILE_5 0x25 | |
245 | #define CG_CGLS_TILE_6 0x26 | |
246 | #define CG_CGLS_TILE_7 0x27 | |
247 | #define CG_CGLS_TILE_8 0x28 | |
248 | #define CG_CGLS_TILE_9 0x29 | |
249 | #define CG_CGLS_TILE_10 0x2a | |
250 | #define CG_CGLS_TILE_11 0x2b | |
251 | ||
252 | #define VM_L2_CG 0x15c0 | |
253 | ||
254 | #define MC_CONFIG 0x2000 | |
255 | ||
256 | #define MC_CONFIG_MCD 0x20a0 | |
257 | #define MC_CG_CONFIG_MCD 0x20a4 | |
258 | #define MC_RD_ENABLE_MCD(x) ((x) << 8) | |
259 | #define MC_RD_ENABLE_MCD_MASK (7 << 8) | |
260 | ||
261 | #define MC_HUB_MISC_HUB_CG 0x20b8 | |
262 | #define MC_HUB_MISC_VM_CG 0x20bc | |
263 | #define MC_HUB_MISC_SIP_CG 0x20c0 | |
264 | ||
265 | #define MC_XPB_CLK_GAT 0x2478 | |
266 | ||
267 | #define MC_CG_CONFIG 0x25bc | |
268 | #define MC_RD_ENABLE(x) ((x) << 4) | |
269 | #define MC_RD_ENABLE_MASK (3 << 4) | |
270 | ||
271 | #define MC_CITF_MISC_RD_CG 0x2648 | |
272 | #define MC_CITF_MISC_WR_CG 0x264c | |
273 | #define MC_CITF_MISC_VM_CG 0x2650 | |
274 | # define MEM_LS_ENABLE (1 << 19) | |
275 | ||
276 | #define MC_ARB_BURST_TIME 0x2808 | |
277 | #define STATE0(x) ((x) << 0) | |
278 | #define STATE0_MASK (0x1f << 0) | |
279 | #define STATE1(x) ((x) << 5) | |
280 | #define STATE1_MASK (0x1f << 5) | |
281 | #define STATE2(x) ((x) << 10) | |
282 | #define STATE2_MASK (0x1f << 10) | |
283 | #define STATE3(x) ((x) << 15) | |
284 | #define STATE3_MASK (0x1f << 15) | |
285 | ||
286 | #define MC_SEQ_RAS_TIMING 0x28a0 | |
287 | #define MC_SEQ_CAS_TIMING 0x28a4 | |
288 | #define MC_SEQ_MISC_TIMING 0x28a8 | |
289 | #define MC_SEQ_MISC_TIMING2 0x28ac | |
290 | ||
291 | #define MC_SEQ_RD_CTL_D0 0x28b4 | |
292 | #define MC_SEQ_RD_CTL_D1 0x28b8 | |
293 | #define MC_SEQ_WR_CTL_D0 0x28bc | |
294 | #define MC_SEQ_WR_CTL_D1 0x28c0 | |
295 | ||
296 | #define MC_SEQ_STATUS_M 0x29f4 | |
297 | # define PMG_PWRSTATE (1 << 16) | |
298 | ||
299 | #define MC_SEQ_MISC1 0x2a04 | |
300 | #define MC_SEQ_RESERVE_M 0x2a08 | |
301 | #define MC_PMG_CMD_EMRS 0x2a0c | |
302 | ||
303 | #define MC_SEQ_MISC3 0x2a2c | |
304 | ||
305 | #define MC_SEQ_MISC5 0x2a54 | |
306 | #define MC_SEQ_MISC6 0x2a58 | |
307 | ||
308 | #define MC_SEQ_MISC7 0x2a64 | |
309 | ||
310 | #define MC_SEQ_CG 0x2a68 | |
311 | #define CG_SEQ_REQ(x) ((x) << 0) | |
312 | #define CG_SEQ_REQ_MASK (0xff << 0) | |
313 | #define CG_SEQ_REQ_SHIFT 0 | |
314 | #define CG_SEQ_RESP(x) ((x) << 8) | |
315 | #define CG_SEQ_RESP_MASK (0xff << 8) | |
316 | #define CG_SEQ_RESP_SHIFT 8 | |
317 | #define SEQ_CG_REQ(x) ((x) << 16) | |
318 | #define SEQ_CG_REQ_MASK (0xff << 16) | |
319 | #define SEQ_CG_REQ_SHIFT 16 | |
320 | #define SEQ_CG_RESP(x) ((x) << 24) | |
321 | #define SEQ_CG_RESP_MASK (0xff << 24) | |
322 | #define SEQ_CG_RESP_SHIFT 24 | |
323 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c | |
324 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 | |
325 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 | |
326 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 | |
327 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c | |
328 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 | |
329 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 | |
330 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 | |
331 | ||
332 | #define MC_PMG_CMD_MRS 0x2aac | |
333 | ||
334 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c | |
335 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 | |
336 | ||
337 | #define MC_PMG_CMD_MRS1 0x2b44 | |
338 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 | |
339 | ||
340 | #define CGTS_SM_CTRL_REG 0x9150 | |
341 | ||
0fcdb61e AD |
342 | /* Registers */ |
343 | ||
32fcdbf4 AD |
344 | #define RCU_IND_INDEX 0x100 |
345 | #define RCU_IND_DATA 0x104 | |
346 | ||
a8b4925c AD |
347 | /* discrete uvd clocks */ |
348 | #define CG_UPLL_FUNC_CNTL 0x718 | |
349 | # define UPLL_RESET_MASK 0x00000001 | |
350 | # define UPLL_SLEEP_MASK 0x00000002 | |
351 | # define UPLL_BYPASS_EN_MASK 0x00000004 | |
352 | # define UPLL_CTLREQ_MASK 0x00000008 | |
092fbc4c | 353 | # define UPLL_REF_DIV_MASK 0x003F0000 |
a8b4925c AD |
354 | # define UPLL_VCO_MODE_MASK 0x00000200 |
355 | # define UPLL_CTLACK_MASK 0x40000000 | |
356 | # define UPLL_CTLACK2_MASK 0x80000000 | |
357 | #define CG_UPLL_FUNC_CNTL_2 0x71c | |
358 | # define UPLL_PDIV_A(x) ((x) << 0) | |
359 | # define UPLL_PDIV_A_MASK 0x0000007F | |
360 | # define UPLL_PDIV_B(x) ((x) << 8) | |
361 | # define UPLL_PDIV_B_MASK 0x00007F00 | |
362 | # define VCLK_SRC_SEL(x) ((x) << 20) | |
363 | # define VCLK_SRC_SEL_MASK 0x01F00000 | |
364 | # define DCLK_SRC_SEL(x) ((x) << 25) | |
365 | # define DCLK_SRC_SEL_MASK 0x3E000000 | |
366 | #define CG_UPLL_FUNC_CNTL_3 0x720 | |
367 | # define UPLL_FB_DIV(x) ((x) << 0) | |
368 | # define UPLL_FB_DIV_MASK 0x01FFFFFF | |
369 | #define CG_UPLL_FUNC_CNTL_4 0x854 | |
370 | # define UPLL_SPARE_ISPARE9 0x00020000 | |
371 | #define CG_UPLL_SPREAD_SPECTRUM 0x79c | |
372 | # define SSEN_MASK 0x00000001 | |
373 | ||
23d33ba3 AD |
374 | /* fusion uvd clocks */ |
375 | #define CG_DCLK_CNTL 0x610 | |
376 | # define DCLK_DIVIDER_MASK 0x7f | |
377 | # define DCLK_DIR_CNTL_EN (1 << 8) | |
378 | #define CG_DCLK_STATUS 0x614 | |
379 | # define DCLK_STATUS (1 << 0) | |
380 | #define CG_VCLK_CNTL 0x618 | |
381 | #define CG_VCLK_STATUS 0x61c | |
382 | #define CG_SCRATCH1 0x820 | |
383 | ||
2948f5e6 AD |
384 | #define RLC_CNTL 0x3f00 |
385 | # define RLC_ENABLE (1 << 0) | |
386 | # define GFX_POWER_GATING_ENABLE (1 << 7) | |
387 | # define GFX_POWER_GATING_SRC (1 << 8) | |
8ba10463 AD |
388 | # define DYN_PER_SIMD_PG_ENABLE (1 << 27) |
389 | # define LB_CNT_SPIM_ACTIVE (1 << 30) | |
390 | # define LOAD_BALANCE_ENABLE (1 << 31) | |
391 | ||
2948f5e6 AD |
392 | #define RLC_HB_BASE 0x3f10 |
393 | #define RLC_HB_CNTL 0x3f0c | |
394 | #define RLC_HB_RPTR 0x3f20 | |
395 | #define RLC_HB_WPTR 0x3f1c | |
396 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 | |
397 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 | |
398 | #define RLC_MC_CNTL 0x3f44 | |
399 | #define RLC_UCODE_CNTL 0x3f48 | |
400 | #define RLC_UCODE_ADDR 0x3f2c | |
401 | #define RLC_UCODE_DATA 0x3f30 | |
402 | ||
403 | /* new for TN */ | |
404 | #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 | |
8ba10463 AD |
405 | #define TN_RLC_LB_CNTR_MAX 0x3f14 |
406 | #define TN_RLC_LB_CNTR_INIT 0x3f18 | |
2948f5e6 | 407 | #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 |
8ba10463 AD |
408 | #define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4 |
409 | #define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8 | |
410 | #define TN_RLC_LB_PARAMS 0x3fec | |
2948f5e6 | 411 | |
32fcdbf4 AD |
412 | #define GRBM_GFX_INDEX 0x802C |
413 | #define INSTANCE_INDEX(x) ((x) << 0) | |
414 | #define SE_INDEX(x) ((x) << 16) | |
415 | #define INSTANCE_BROADCAST_WRITES (1 << 30) | |
416 | #define SE_BROADCAST_WRITES (1 << 31) | |
417 | #define RLC_GFX_INDEX 0x3fC4 | |
418 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 | |
419 | #define WRITE_DIS (1 << 0) | |
420 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
421 | #define BACKEND_DISABLE(x) ((x) << 16) | |
422 | #define GB_ADDR_CONFIG 0x98F8 | |
423 | #define NUM_PIPES(x) ((x) << 0) | |
416a2bd2 | 424 | #define NUM_PIPES_MASK 0x0000000f |
32fcdbf4 AD |
425 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
426 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) | |
427 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | |
428 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) | |
429 | #define NUM_GPUS(x) ((x) << 20) | |
430 | #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) | |
431 | #define ROW_SIZE(x) ((x) << 28) | |
432 | #define GB_BACKEND_MAP 0x98FC | |
433 | #define DMIF_ADDR_CONFIG 0xBD4 | |
434 | #define HDP_ADDR_CONFIG 0x2F48 | |
f25a5c63 AD |
435 | #define HDP_MISC_CNTL 0x2F4C |
436 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | |
32fcdbf4 | 437 | |
0fcdb61e | 438 | #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 |
32fcdbf4 | 439 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
0fcdb61e AD |
440 | |
441 | #define CGTS_SYS_TCC_DISABLE 0x3F90 | |
442 | #define CGTS_TCC_DISABLE 0x9148 | |
443 | #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 | |
444 | #define CGTS_USER_TCC_DISABLE 0x914C | |
445 | ||
446 | #define CONFIG_MEMSIZE 0x5428 | |
447 | ||
62444b74 AD |
448 | #define BIF_FB_EN 0x5490 |
449 | #define FB_READ_EN (1 << 0) | |
450 | #define FB_WRITE_EN (1 << 1) | |
451 | ||
860fe2f0 AD |
452 | #define CP_STRMOUT_CNTL 0x84FC |
453 | ||
454 | #define CP_COHER_CNTL 0x85F0 | |
455 | #define CP_COHER_SIZE 0x85F4 | |
dd220a00 | 456 | #define CP_COHER_BASE 0x85F8 |
440a7cd8 JG |
457 | #define CP_STALLED_STAT1 0x8674 |
458 | #define CP_STALLED_STAT2 0x8678 | |
459 | #define CP_BUSY_STAT 0x867C | |
460 | #define CP_STAT 0x8680 | |
32fcdbf4 AD |
461 | #define CP_ME_CNTL 0x86D8 |
462 | #define CP_ME_HALT (1 << 28) | |
463 | #define CP_PFP_HALT (1 << 26) | |
0fcdb61e AD |
464 | #define CP_ME_RAM_DATA 0xC160 |
465 | #define CP_ME_RAM_RADDR 0xC158 | |
466 | #define CP_ME_RAM_WADDR 0xC15C | |
467 | #define CP_MEQ_THRESHOLDS 0x8764 | |
468 | #define STQ_SPLIT(x) ((x) << 0) | |
469 | #define CP_PERFMON_CNTL 0x87FC | |
470 | #define CP_PFP_UCODE_ADDR 0xC150 | |
471 | #define CP_PFP_UCODE_DATA 0xC154 | |
472 | #define CP_QUEUE_THRESHOLDS 0x8760 | |
473 | #define ROQ_IB1_START(x) ((x) << 0) | |
474 | #define ROQ_IB2_START(x) ((x) << 8) | |
fe251e2f | 475 | #define CP_RB_BASE 0xC100 |
0fcdb61e | 476 | #define CP_RB_CNTL 0xC104 |
32fcdbf4 AD |
477 | #define RB_BUFSZ(x) ((x) << 0) |
478 | #define RB_BLKSZ(x) ((x) << 8) | |
479 | #define RB_NO_UPDATE (1 << 27) | |
480 | #define RB_RPTR_WR_ENA (1 << 31) | |
0fcdb61e AD |
481 | #define BUF_SWAP_32BIT (2 << 16) |
482 | #define CP_RB_RPTR 0x8700 | |
483 | #define CP_RB_RPTR_ADDR 0xC10C | |
0f234f5f | 484 | #define RB_RPTR_SWAP(x) ((x) << 0) |
0fcdb61e AD |
485 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
486 | #define CP_RB_RPTR_WR 0xC108 | |
487 | #define CP_RB_WPTR 0xC114 | |
488 | #define CP_RB_WPTR_ADDR 0xC118 | |
489 | #define CP_RB_WPTR_ADDR_HI 0xC11C | |
490 | #define CP_RB_WPTR_DELAY 0x8704 | |
491 | #define CP_SEM_WAIT_TIMER 0x85BC | |
11ef3f1f | 492 | #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 |
fe251e2f | 493 | #define CP_DEBUG 0xC1FC |
0fcdb61e | 494 | |
3a2a67aa AD |
495 | /* Audio clocks */ |
496 | #define DCCG_AUDIO_DTO_SOURCE 0x05ac | |
497 | # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ | |
498 | # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ | |
499 | ||
500 | #define DCCG_AUDIO_DTO0_PHASE 0x05b0 | |
501 | #define DCCG_AUDIO_DTO0_MODULE 0x05b4 | |
502 | #define DCCG_AUDIO_DTO0_LOAD 0x05b8 | |
503 | #define DCCG_AUDIO_DTO0_CNTL 0x05bc | |
1518dd8e AD |
504 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) |
505 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 | |
506 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 | |
3a2a67aa AD |
507 | |
508 | #define DCCG_AUDIO_DTO1_PHASE 0x05c0 | |
509 | #define DCCG_AUDIO_DTO1_MODULE 0x05c4 | |
510 | #define DCCG_AUDIO_DTO1_LOAD 0x05c8 | |
511 | #define DCCG_AUDIO_DTO1_CNTL 0x05cc | |
512 | ||
513 | /* DCE 4.0 AFMT */ | |
514 | #define HDMI_CONTROL 0x7030 | |
515 | # define HDMI_KEEPOUT_MODE (1 << 0) | |
516 | # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ | |
517 | # define HDMI_ERROR_ACK (1 << 8) | |
518 | # define HDMI_ERROR_MASK (1 << 9) | |
519 | # define HDMI_DEEP_COLOR_ENABLE (1 << 24) | |
7b555e06 | 520 | # define HDMI_DEEP_COLOR_DEPTH(x) (((x) & 3) << 28) |
3a2a67aa AD |
521 | # define HDMI_24BIT_DEEP_COLOR 0 |
522 | # define HDMI_30BIT_DEEP_COLOR 1 | |
523 | # define HDMI_36BIT_DEEP_COLOR 2 | |
7b555e06 | 524 | # define HDMI_DEEP_COLOR_DEPTH_MASK (3 << 28) |
3a2a67aa AD |
525 | #define HDMI_STATUS 0x7034 |
526 | # define HDMI_ACTIVE_AVMUTE (1 << 0) | |
527 | # define HDMI_AUDIO_PACKET_ERROR (1 << 16) | |
528 | # define HDMI_VBI_PACKET_ERROR (1 << 20) | |
529 | #define HDMI_AUDIO_PACKET_CONTROL 0x7038 | |
530 | # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) | |
531 | # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) | |
532 | #define HDMI_ACR_PACKET_CONTROL 0x703c | |
533 | # define HDMI_ACR_SEND (1 << 0) | |
534 | # define HDMI_ACR_CONT (1 << 1) | |
535 | # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) | |
536 | # define HDMI_ACR_HW 0 | |
537 | # define HDMI_ACR_32 1 | |
538 | # define HDMI_ACR_44 2 | |
539 | # define HDMI_ACR_48 3 | |
540 | # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ | |
541 | # define HDMI_ACR_AUTO_SEND (1 << 12) | |
542 | # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) | |
543 | # define HDMI_ACR_X1 1 | |
544 | # define HDMI_ACR_X2 2 | |
545 | # define HDMI_ACR_X4 4 | |
546 | # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) | |
547 | #define HDMI_VBI_PACKET_CONTROL 0x7040 | |
548 | # define HDMI_NULL_SEND (1 << 0) | |
549 | # define HDMI_GC_SEND (1 << 4) | |
550 | # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ | |
551 | #define HDMI_INFOFRAME_CONTROL0 0x7044 | |
552 | # define HDMI_AVI_INFO_SEND (1 << 0) | |
553 | # define HDMI_AVI_INFO_CONT (1 << 1) | |
554 | # define HDMI_AUDIO_INFO_SEND (1 << 4) | |
555 | # define HDMI_AUDIO_INFO_CONT (1 << 5) | |
556 | # define HDMI_MPEG_INFO_SEND (1 << 8) | |
557 | # define HDMI_MPEG_INFO_CONT (1 << 9) | |
558 | #define HDMI_INFOFRAME_CONTROL1 0x7048 | |
559 | # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) | |
d3418eac | 560 | # define HDMI_AVI_INFO_LINE_MASK (0x3f << 0) |
3a2a67aa AD |
561 | # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) |
562 | # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) | |
563 | #define HDMI_GENERIC_PACKET_CONTROL 0x704c | |
564 | # define HDMI_GENERIC0_SEND (1 << 0) | |
565 | # define HDMI_GENERIC0_CONT (1 << 1) | |
566 | # define HDMI_GENERIC1_SEND (1 << 4) | |
567 | # define HDMI_GENERIC1_CONT (1 << 5) | |
568 | # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) | |
569 | # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) | |
570 | #define HDMI_GC 0x7058 | |
571 | # define HDMI_GC_AVMUTE (1 << 0) | |
572 | # define HDMI_GC_AVMUTE_CONT (1 << 2) | |
573 | #define AFMT_AUDIO_PACKET_CONTROL2 0x705c | |
574 | # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) | |
575 | # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) | |
576 | # define AFMT_60958_CS_SOURCE (1 << 4) | |
577 | # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) | |
578 | # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) | |
579 | #define AFMT_AVI_INFO0 0x7084 | |
580 | # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
581 | # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) | |
582 | # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) | |
583 | # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) | |
584 | # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) | |
585 | # define AFMT_AVI_INFO_Y_RGB 0 | |
586 | # define AFMT_AVI_INFO_Y_YCBCR422 1 | |
587 | # define AFMT_AVI_INFO_Y_YCBCR444 2 | |
588 | # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) | |
589 | # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) | |
590 | # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) | |
591 | # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) | |
592 | # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) | |
593 | # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) | |
594 | # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) | |
595 | # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) | |
596 | # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) | |
597 | # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) | |
598 | #define AFMT_AVI_INFO1 0x7088 | |
599 | # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ | |
600 | # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ | |
601 | # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) | |
602 | # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) | |
603 | # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) | |
604 | #define AFMT_AVI_INFO2 0x708c | |
605 | # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) | |
606 | # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) | |
607 | #define AFMT_AVI_INFO3 0x7090 | |
608 | # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) | |
609 | # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) | |
610 | #define AFMT_MPEG_INFO0 0x7094 | |
611 | # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
612 | # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) | |
613 | # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) | |
614 | # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) | |
615 | #define AFMT_MPEG_INFO1 0x7098 | |
616 | # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) | |
617 | # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) | |
618 | # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) | |
619 | #define AFMT_GENERIC0_HDR 0x709c | |
620 | #define AFMT_GENERIC0_0 0x70a0 | |
621 | #define AFMT_GENERIC0_1 0x70a4 | |
622 | #define AFMT_GENERIC0_2 0x70a8 | |
623 | #define AFMT_GENERIC0_3 0x70ac | |
624 | #define AFMT_GENERIC0_4 0x70b0 | |
625 | #define AFMT_GENERIC0_5 0x70b4 | |
626 | #define AFMT_GENERIC0_6 0x70b8 | |
627 | #define AFMT_GENERIC1_HDR 0x70bc | |
628 | #define AFMT_GENERIC1_0 0x70c0 | |
629 | #define AFMT_GENERIC1_1 0x70c4 | |
630 | #define AFMT_GENERIC1_2 0x70c8 | |
631 | #define AFMT_GENERIC1_3 0x70cc | |
632 | #define AFMT_GENERIC1_4 0x70d0 | |
633 | #define AFMT_GENERIC1_5 0x70d4 | |
634 | #define AFMT_GENERIC1_6 0x70d8 | |
635 | #define HDMI_ACR_32_0 0x70dc | |
636 | # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) | |
637 | #define HDMI_ACR_32_1 0x70e0 | |
638 | # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) | |
639 | #define HDMI_ACR_44_0 0x70e4 | |
640 | # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) | |
641 | #define HDMI_ACR_44_1 0x70e8 | |
642 | # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) | |
643 | #define HDMI_ACR_48_0 0x70ec | |
644 | # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) | |
645 | #define HDMI_ACR_48_1 0x70f0 | |
646 | # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) | |
647 | #define HDMI_ACR_STATUS_0 0x70f4 | |
648 | #define HDMI_ACR_STATUS_1 0x70f8 | |
649 | #define AFMT_AUDIO_INFO0 0x70fc | |
650 | # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
651 | # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) | |
652 | # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) | |
653 | # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) | |
654 | # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) | |
655 | #define AFMT_AUDIO_INFO1 0x7100 | |
656 | # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) | |
657 | # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) | |
658 | # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) | |
659 | # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) | |
660 | # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) | |
661 | #define AFMT_60958_0 0x7104 | |
662 | # define AFMT_60958_CS_A(x) (((x) & 1) << 0) | |
663 | # define AFMT_60958_CS_B(x) (((x) & 1) << 1) | |
664 | # define AFMT_60958_CS_C(x) (((x) & 1) << 2) | |
665 | # define AFMT_60958_CS_D(x) (((x) & 3) << 3) | |
666 | # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) | |
667 | # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) | |
668 | # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) | |
669 | # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) | |
670 | # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) | |
671 | # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) | |
672 | #define AFMT_60958_1 0x7108 | |
673 | # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) | |
674 | # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) | |
675 | # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) | |
676 | # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) | |
677 | # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) | |
678 | #define AFMT_AUDIO_CRC_CONTROL 0x710c | |
679 | # define AFMT_AUDIO_CRC_EN (1 << 0) | |
680 | #define AFMT_RAMP_CONTROL0 0x7110 | |
681 | # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) | |
682 | # define AFMT_RAMP_DATA_SIGN (1 << 31) | |
683 | #define AFMT_RAMP_CONTROL1 0x7114 | |
684 | # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) | |
685 | # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) | |
686 | #define AFMT_RAMP_CONTROL2 0x7118 | |
687 | # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) | |
688 | #define AFMT_RAMP_CONTROL3 0x711c | |
689 | # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) | |
690 | #define AFMT_60958_2 0x7120 | |
691 | # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) | |
692 | # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) | |
693 | # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) | |
694 | # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) | |
695 | # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) | |
696 | # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) | |
697 | #define AFMT_STATUS 0x7128 | |
698 | # define AFMT_AUDIO_ENABLE (1 << 4) | |
699 | # define AFMT_AUDIO_HBR_ENABLE (1 << 8) | |
700 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) | |
701 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) | |
702 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) | |
703 | #define AFMT_AUDIO_PACKET_CONTROL 0x712c | |
704 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) | |
705 | # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ | |
706 | # define AFMT_AUDIO_TEST_EN (1 << 12) | |
707 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) | |
708 | # define AFMT_60958_CS_UPDATE (1 << 26) | |
709 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) | |
710 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) | |
711 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) | |
712 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) | |
713 | #define AFMT_VBI_PACKET_CONTROL 0x7130 | |
714 | # define AFMT_GENERIC0_UPDATE (1 << 2) | |
715 | #define AFMT_INFOFRAME_CONTROL0 0x7134 | |
716 | # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ | |
717 | # define AFMT_AUDIO_INFO_UPDATE (1 << 7) | |
718 | # define AFMT_MPEG_INFO_UPDATE (1 << 10) | |
719 | #define AFMT_GENERIC0_7 0x7138 | |
0fcdb61e | 720 | |
1c4c3a99 | 721 | /* DCE4/5 ELD audio interface */ |
ba7def4f AD |
722 | #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78 |
723 | #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) | |
724 | #define SPEAKER_ALLOCATION_MASK (0x7f << 0) | |
725 | #define SPEAKER_ALLOCATION_SHIFT 0 | |
726 | #define HDMI_CONNECTION (1 << 16) | |
727 | #define DP_CONNECTION (1 << 17) | |
728 | ||
1c4c3a99 AD |
729 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ |
730 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ | |
731 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ | |
732 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ | |
733 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ | |
734 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ | |
735 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ | |
736 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ | |
737 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ | |
738 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ | |
739 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ | |
740 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ | |
741 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ | |
742 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ | |
743 | # define MAX_CHANNELS(x) (((x) & 0x7) << 0) | |
744 | /* max channels minus one. 7 = 8 channels */ | |
745 | # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) | |
746 | # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) | |
747 | # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ | |
748 | /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO | |
749 | * bit0 = 32 kHz | |
750 | * bit1 = 44.1 kHz | |
751 | * bit2 = 48 kHz | |
752 | * bit3 = 88.2 kHz | |
753 | * bit4 = 96 kHz | |
754 | * bit5 = 176.4 kHz | |
755 | * bit6 = 192 kHz | |
756 | */ | |
757 | ||
712fd8a2 AD |
758 | #define AZ_CHANNEL_COUNT_CONTROL 0x5fe4 |
759 | # define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0) | |
760 | # define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4) | |
761 | /* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT | |
762 | * 0 = use stream header | |
763 | * 1-7 = channel count - 1 | |
764 | */ | |
765 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8 | |
766 | # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) | |
767 | # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) | |
768 | /* VIDEO_LIPSYNC, AUDIO_LIPSYNC | |
769 | * 0 = invalid | |
770 | * x = legal delay value | |
771 | * 255 = sync not supported | |
772 | */ | |
773 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec | |
774 | # define HBR_CAPABLE (1 << 0) /* enabled by default */ | |
775 | ||
776 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4 | |
777 | # define DISPLAY0_TYPE(x) (((x) & 0x3) << 0) | |
778 | # define DISPLAY_TYPE_NONE 0 | |
779 | # define DISPLAY_TYPE_HDMI 1 | |
780 | # define DISPLAY_TYPE_DP 2 | |
781 | # define DISPLAY0_ID(x) (((x) & 0x3f) << 2) | |
782 | # define DISPLAY1_TYPE(x) (((x) & 0x3) << 8) | |
783 | # define DISPLAY1_ID(x) (((x) & 0x3f) << 10) | |
784 | # define DISPLAY2_TYPE(x) (((x) & 0x3) << 16) | |
785 | # define DISPLAY2_ID(x) (((x) & 0x3f) << 18) | |
786 | # define DISPLAY3_TYPE(x) (((x) & 0x3) << 24) | |
787 | # define DISPLAY3_ID(x) (((x) & 0x3f) << 26) | |
788 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8 | |
789 | # define DISPLAY4_TYPE(x) (((x) & 0x3) << 0) | |
790 | # define DISPLAY4_ID(x) (((x) & 0x3f) << 2) | |
791 | # define DISPLAY5_TYPE(x) (((x) & 0x3) << 8) | |
792 | # define DISPLAY5_ID(x) (((x) & 0x3f) << 10) | |
793 | #define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc | |
794 | # define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0) | |
795 | ||
1c4c3a99 AD |
796 | #define AZ_HOT_PLUG_CONTROL 0x5e78 |
797 | # define AZ_FORCE_CODEC_WAKE (1 << 0) | |
798 | # define PIN0_JACK_DETECTION_ENABLE (1 << 4) | |
799 | # define PIN1_JACK_DETECTION_ENABLE (1 << 5) | |
800 | # define PIN2_JACK_DETECTION_ENABLE (1 << 6) | |
801 | # define PIN3_JACK_DETECTION_ENABLE (1 << 7) | |
802 | # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) | |
803 | # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) | |
804 | # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) | |
805 | # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) | |
806 | # define CODEC_HOT_PLUG_ENABLE (1 << 12) | |
807 | # define PIN0_AUDIO_ENABLED (1 << 24) | |
808 | # define PIN1_AUDIO_ENABLED (1 << 25) | |
809 | # define PIN2_AUDIO_ENABLED (1 << 26) | |
810 | # define PIN3_AUDIO_ENABLED (1 << 27) | |
811 | # define AUDIO_ENABLED (1 << 31) | |
812 | ||
813 | ||
0fcdb61e AD |
814 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
815 | #define INACTIVE_QD_PIPES(x) ((x) << 8) | |
816 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 | |
817 | #define INACTIVE_SIMDS(x) ((x) << 16) | |
818 | #define INACTIVE_SIMDS_MASK 0x00FF0000 | |
819 | ||
820 | #define GRBM_CNTL 0x8000 | |
821 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
822 | #define GRBM_SOFT_RESET 0x8020 | |
747943ea AD |
823 | #define SOFT_RESET_CP (1 << 0) |
824 | #define SOFT_RESET_CB (1 << 1) | |
825 | #define SOFT_RESET_DB (1 << 3) | |
826 | #define SOFT_RESET_PA (1 << 5) | |
827 | #define SOFT_RESET_SC (1 << 6) | |
828 | #define SOFT_RESET_SPI (1 << 8) | |
829 | #define SOFT_RESET_SH (1 << 9) | |
830 | #define SOFT_RESET_SX (1 << 10) | |
831 | #define SOFT_RESET_TC (1 << 11) | |
832 | #define SOFT_RESET_TA (1 << 12) | |
833 | #define SOFT_RESET_VC (1 << 13) | |
834 | #define SOFT_RESET_VGT (1 << 14) | |
835 | ||
0fcdb61e AD |
836 | #define GRBM_STATUS 0x8010 |
837 | #define CMDFIFO_AVAIL_MASK 0x0000000F | |
747943ea AD |
838 | #define SRBM_RQ_PENDING (1 << 5) |
839 | #define CF_RQ_PENDING (1 << 7) | |
840 | #define PF_RQ_PENDING (1 << 8) | |
841 | #define GRBM_EE_BUSY (1 << 10) | |
842 | #define SX_CLEAN (1 << 11) | |
843 | #define DB_CLEAN (1 << 12) | |
844 | #define CB_CLEAN (1 << 13) | |
845 | #define TA_BUSY (1 << 14) | |
846 | #define VGT_BUSY_NO_DMA (1 << 16) | |
847 | #define VGT_BUSY (1 << 17) | |
848 | #define SX_BUSY (1 << 20) | |
849 | #define SH_BUSY (1 << 21) | |
850 | #define SPI_BUSY (1 << 22) | |
851 | #define SC_BUSY (1 << 24) | |
852 | #define PA_BUSY (1 << 25) | |
853 | #define DB_BUSY (1 << 26) | |
854 | #define CP_COHERENCY_BUSY (1 << 28) | |
855 | #define CP_BUSY (1 << 29) | |
856 | #define CB_BUSY (1 << 30) | |
857 | #define GUI_ACTIVE (1 << 31) | |
858 | #define GRBM_STATUS_SE0 0x8014 | |
859 | #define GRBM_STATUS_SE1 0x8018 | |
860 | #define SE_SX_CLEAN (1 << 0) | |
861 | #define SE_DB_CLEAN (1 << 1) | |
862 | #define SE_CB_CLEAN (1 << 2) | |
863 | #define SE_TA_BUSY (1 << 25) | |
864 | #define SE_SX_BUSY (1 << 26) | |
865 | #define SE_SPI_BUSY (1 << 27) | |
866 | #define SE_SH_BUSY (1 << 28) | |
867 | #define SE_SC_BUSY (1 << 29) | |
868 | #define SE_DB_BUSY (1 << 30) | |
869 | #define SE_CB_BUSY (1 << 31) | |
e33df25f | 870 | /* evergreen */ |
67b3f823 AD |
871 | #define CG_THERMAL_CTRL 0x72c |
872 | #define TOFFSET_MASK 0x00003FE0 | |
873 | #define TOFFSET_SHIFT 5 | |
dc50ba7f AD |
874 | #define DIG_THERM_DPM(x) ((x) << 14) |
875 | #define DIG_THERM_DPM_MASK 0x003FC000 | |
876 | #define DIG_THERM_DPM_SHIFT 14 | |
877 | ||
878 | #define CG_THERMAL_INT 0x734 | |
879 | #define DIG_THERM_INTH(x) ((x) << 8) | |
880 | #define DIG_THERM_INTH_MASK 0x0000FF00 | |
881 | #define DIG_THERM_INTH_SHIFT 8 | |
882 | #define DIG_THERM_INTL(x) ((x) << 16) | |
883 | #define DIG_THERM_INTL_MASK 0x00FF0000 | |
884 | #define DIG_THERM_INTL_SHIFT 16 | |
885 | #define THERM_INT_MASK_HIGH (1 << 24) | |
886 | #define THERM_INT_MASK_LOW (1 << 25) | |
887 | ||
d70229f7 AD |
888 | #define TN_CG_THERMAL_INT_CTRL 0x738 |
889 | #define TN_DIG_THERM_INTH(x) ((x) << 0) | |
890 | #define TN_DIG_THERM_INTH_MASK 0x000000FF | |
891 | #define TN_DIG_THERM_INTH_SHIFT 0 | |
892 | #define TN_DIG_THERM_INTL(x) ((x) << 8) | |
893 | #define TN_DIG_THERM_INTL_MASK 0x0000FF00 | |
894 | #define TN_DIG_THERM_INTL_SHIFT 8 | |
895 | #define TN_THERM_INT_MASK_HIGH (1 << 24) | |
896 | #define TN_THERM_INT_MASK_LOW (1 << 25) | |
897 | ||
21a8122a AD |
898 | #define CG_MULT_THERMAL_STATUS 0x740 |
899 | #define ASIC_T(x) ((x) << 16) | |
67b3f823 | 900 | #define ASIC_T_MASK 0x07FF0000 |
21a8122a | 901 | #define ASIC_T_SHIFT 16 |
67b3f823 AD |
902 | #define CG_TS0_STATUS 0x760 |
903 | #define TS0_ADC_DOUT_MASK 0x000003FF | |
904 | #define TS0_ADC_DOUT_SHIFT 0 | |
dc50ba7f | 905 | |
e33df25f AD |
906 | /* APU */ |
907 | #define CG_THERMAL_STATUS 0x678 | |
21a8122a | 908 | |
0fcdb61e AD |
909 | #define HDP_HOST_PATH_CNTL 0x2C00 |
910 | #define HDP_NONSURFACE_BASE 0x2C04 | |
911 | #define HDP_NONSURFACE_INFO 0x2C08 | |
912 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
6f2f48a9 | 913 | #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
0fcdb61e AD |
914 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
915 | #define HDP_TILING_CONFIG 0x2F3C | |
916 | ||
917 | #define MC_SHARED_CHMAP 0x2004 | |
918 | #define NOOFCHAN_SHIFT 12 | |
919 | #define NOOFCHAN_MASK 0x00003000 | |
9535ab73 | 920 | #define MC_SHARED_CHREMAP 0x2008 |
0fcdb61e | 921 | |
62444b74 AD |
922 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
923 | #define BLACKOUT_MODE_MASK 0x00000007 | |
924 | ||
0fcdb61e AD |
925 | #define MC_ARB_RAMCFG 0x2760 |
926 | #define NOOFBANK_SHIFT 0 | |
927 | #define NOOFBANK_MASK 0x00000003 | |
928 | #define NOOFRANK_SHIFT 2 | |
929 | #define NOOFRANK_MASK 0x00000004 | |
930 | #define NOOFROWS_SHIFT 3 | |
931 | #define NOOFROWS_MASK 0x00000038 | |
932 | #define NOOFCOLS_SHIFT 6 | |
933 | #define NOOFCOLS_MASK 0x000000C0 | |
934 | #define CHANSIZE_SHIFT 8 | |
935 | #define CHANSIZE_MASK 0x00000100 | |
936 | #define BURSTLENGTH_SHIFT 9 | |
937 | #define BURSTLENGTH_MASK 0x00000200 | |
938 | #define CHANSIZE_OVERRIDE (1 << 11) | |
d9282fca | 939 | #define FUS_MC_ARB_RAMCFG 0x2768 |
0fcdb61e AD |
940 | #define MC_VM_AGP_TOP 0x2028 |
941 | #define MC_VM_AGP_BOT 0x202C | |
942 | #define MC_VM_AGP_BASE 0x2030 | |
943 | #define MC_VM_FB_LOCATION 0x2024 | |
b4183e30 | 944 | #define MC_FUS_VM_FB_OFFSET 0x2898 |
0fcdb61e AD |
945 | #define MC_VM_MB_L1_TLB0_CNTL 0x2234 |
946 | #define MC_VM_MB_L1_TLB1_CNTL 0x2238 | |
947 | #define MC_VM_MB_L1_TLB2_CNTL 0x223C | |
948 | #define MC_VM_MB_L1_TLB3_CNTL 0x2240 | |
949 | #define ENABLE_L1_TLB (1 << 0) | |
950 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
951 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) | |
952 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) | |
953 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | |
954 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) | |
955 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | |
956 | #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) | |
957 | #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) | |
958 | #define MC_VM_MD_L1_TLB0_CNTL 0x2654 | |
959 | #define MC_VM_MD_L1_TLB1_CNTL 0x2658 | |
960 | #define MC_VM_MD_L1_TLB2_CNTL 0x265C | |
0b8c30bc | 961 | #define MC_VM_MD_L1_TLB3_CNTL 0x2698 |
8aeb96f8 AD |
962 | |
963 | #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C | |
964 | #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 | |
965 | #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 | |
966 | ||
0fcdb61e AD |
967 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C |
968 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | |
969 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | |
970 | ||
971 | #define PA_CL_ENHANCE 0x8A14 | |
972 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
973 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
721604a1 | 974 | #define PA_SC_ENHANCE 0x8BF0 |
0fcdb61e | 975 | #define PA_SC_AA_CONFIG 0x28C04 |
cb5fcbd5 AD |
976 | #define MSAA_NUM_SAMPLES_SHIFT 0 |
977 | #define MSAA_NUM_SAMPLES_MASK 0x3 | |
0fcdb61e AD |
978 | #define PA_SC_CLIPRECT_RULE 0x2820C |
979 | #define PA_SC_EDGERULE 0x28230 | |
980 | #define PA_SC_FIFO_SIZE 0x8BCC | |
981 | #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) | |
982 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) | |
32fcdbf4 | 983 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) |
0fcdb61e | 984 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
32fcdbf4 AD |
985 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
986 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | |
0fcdb61e | 987 | #define PA_SC_LINE_STIPPLE 0x28A0C |
12920591 | 988 | #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 |
0fcdb61e AD |
989 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 |
990 | ||
991 | #define SCRATCH_REG0 0x8500 | |
992 | #define SCRATCH_REG1 0x8504 | |
993 | #define SCRATCH_REG2 0x8508 | |
994 | #define SCRATCH_REG3 0x850C | |
995 | #define SCRATCH_REG4 0x8510 | |
996 | #define SCRATCH_REG5 0x8514 | |
997 | #define SCRATCH_REG6 0x8518 | |
998 | #define SCRATCH_REG7 0x851C | |
999 | #define SCRATCH_UMSK 0x8540 | |
1000 | #define SCRATCH_ADDR 0x8544 | |
1001 | ||
b866d133 | 1002 | #define SMX_SAR_CTL0 0xA008 |
0fcdb61e AD |
1003 | #define SMX_DC_CTL0 0xA020 |
1004 | #define USE_HASH_FUNCTION (1 << 0) | |
32fcdbf4 | 1005 | #define NUMBER_OF_SETS(x) ((x) << 1) |
0fcdb61e AD |
1006 | #define FLUSH_ALL_ON_EVENT (1 << 10) |
1007 | #define STALL_ON_EVENT (1 << 11) | |
1008 | #define SMX_EVENT_CTL 0xA02C | |
1009 | #define ES_FLUSH_CTL(x) ((x) << 0) | |
1010 | #define GS_FLUSH_CTL(x) ((x) << 3) | |
1011 | #define ACK_FLUSH_CTL(x) ((x) << 6) | |
1012 | #define SYNC_FLUSH_CTL (1 << 8) | |
1013 | ||
1014 | #define SPI_CONFIG_CNTL 0x9100 | |
1015 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) | |
1016 | #define SPI_CONFIG_CNTL_1 0x913C | |
1017 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
1018 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
1019 | #define SPI_INPUT_Z 0x286D8 | |
1020 | #define SPI_PS_IN_CONTROL_0 0x286CC | |
1021 | #define NUM_INTERP(x) ((x)<<0) | |
1022 | #define POSITION_ENA (1<<8) | |
1023 | #define POSITION_CENTROID (1<<9) | |
1024 | #define POSITION_ADDR(x) ((x)<<10) | |
1025 | #define PARAM_GEN(x) ((x)<<15) | |
1026 | #define PARAM_GEN_ADDR(x) ((x)<<19) | |
1027 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) | |
1028 | #define PERSP_GRADIENT_ENA (1<<28) | |
1029 | #define LINEAR_GRADIENT_ENA (1<<29) | |
1030 | #define POSITION_SAMPLE (1<<30) | |
1031 | #define BARYC_AT_SAMPLE_ENA (1<<31) | |
1032 | ||
1033 | #define SQ_CONFIG 0x8C00 | |
1034 | #define VC_ENABLE (1 << 0) | |
1035 | #define EXPORT_SRC_C (1 << 1) | |
32fcdbf4 AD |
1036 | #define CS_PRIO(x) ((x) << 18) |
1037 | #define LS_PRIO(x) ((x) << 20) | |
1038 | #define HS_PRIO(x) ((x) << 22) | |
1039 | #define PS_PRIO(x) ((x) << 24) | |
1040 | #define VS_PRIO(x) ((x) << 26) | |
1041 | #define GS_PRIO(x) ((x) << 28) | |
1042 | #define ES_PRIO(x) ((x) << 30) | |
0fcdb61e AD |
1043 | #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 |
1044 | #define NUM_PS_GPRS(x) ((x) << 0) | |
1045 | #define NUM_VS_GPRS(x) ((x) << 16) | |
1046 | #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | |
1047 | #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 | |
1048 | #define NUM_GS_GPRS(x) ((x) << 0) | |
1049 | #define NUM_ES_GPRS(x) ((x) << 16) | |
32fcdbf4 AD |
1050 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C |
1051 | #define NUM_HS_GPRS(x) ((x) << 0) | |
1052 | #define NUM_LS_GPRS(x) ((x) << 16) | |
721604a1 JG |
1053 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 |
1054 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 | |
32fcdbf4 AD |
1055 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 |
1056 | #define NUM_PS_THREADS(x) ((x) << 0) | |
1057 | #define NUM_VS_THREADS(x) ((x) << 8) | |
1058 | #define NUM_GS_THREADS(x) ((x) << 16) | |
1059 | #define NUM_ES_THREADS(x) ((x) << 24) | |
1060 | #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C | |
1061 | #define NUM_HS_THREADS(x) ((x) << 0) | |
1062 | #define NUM_LS_THREADS(x) ((x) << 8) | |
1063 | #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 | |
1064 | #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) | |
1065 | #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) | |
1066 | #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 | |
1067 | #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) | |
1068 | #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) | |
1069 | #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 | |
1070 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) | |
1071 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) | |
1072 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C | |
721604a1 JG |
1073 | #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 |
1074 | #define SQ_STATIC_THREAD_MGMT_1 0x8E20 | |
1075 | #define SQ_STATIC_THREAD_MGMT_2 0x8E24 | |
1076 | #define SQ_STATIC_THREAD_MGMT_3 0x8E28 | |
32fcdbf4 AD |
1077 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C |
1078 | ||
0fcdb61e AD |
1079 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
1080 | #define CACHE_FIFO_SIZE(x) ((x) << 0) | |
1081 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) | |
1082 | #define DONE_FIFO_HIWATER(x) ((x) << 16) | |
1083 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | |
1084 | ||
1085 | #define SX_DEBUG_1 0x9058 | |
1086 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | |
1087 | #define SX_EXPORT_BUFFER_SIZES 0x900C | |
1088 | #define COLOR_BUFFER_SIZE(x) ((x) << 0) | |
1089 | #define POSITION_BUFFER_SIZE(x) ((x) << 8) | |
1090 | #define SMX_BUFFER_SIZE(x) ((x) << 16) | |
033b5650 | 1091 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
0fcdb61e AD |
1092 | #define SX_MISC 0x28350 |
1093 | ||
32fcdbf4 AD |
1094 | #define CB_PERF_CTR0_SEL_0 0x9A20 |
1095 | #define CB_PERF_CTR0_SEL_1 0x9A24 | |
1096 | #define CB_PERF_CTR1_SEL_0 0x9A28 | |
1097 | #define CB_PERF_CTR1_SEL_1 0x9A2C | |
1098 | #define CB_PERF_CTR2_SEL_0 0x9A30 | |
1099 | #define CB_PERF_CTR2_SEL_1 0x9A34 | |
1100 | #define CB_PERF_CTR3_SEL_0 0x9A38 | |
1101 | #define CB_PERF_CTR3_SEL_1 0x9A3C | |
1102 | ||
0fcdb61e AD |
1103 | #define TA_CNTL_AUX 0x9508 |
1104 | #define DISABLE_CUBE_WRAP (1 << 0) | |
1105 | #define DISABLE_CUBE_ANISO (1 << 1) | |
1106 | #define SYNC_GRADIENT (1 << 24) | |
1107 | #define SYNC_WALKER (1 << 25) | |
1108 | #define SYNC_ALIGNER (1 << 26) | |
1109 | ||
9535ab73 AD |
1110 | #define TCP_CHAN_STEER_LO 0x960c |
1111 | #define TCP_CHAN_STEER_HI 0x9610 | |
1112 | ||
0fcdb61e | 1113 | #define VGT_CACHE_INVALIDATION 0x88C4 |
32fcdbf4 | 1114 | #define CACHE_INVALIDATION(x) ((x) << 0) |
0fcdb61e AD |
1115 | #define VC_ONLY 0 |
1116 | #define TC_ONLY 1 | |
1117 | #define VC_AND_TC 2 | |
1118 | #define AUTO_INVLD_EN(x) ((x) << 6) | |
1119 | #define NO_AUTO 0 | |
1120 | #define ES_AUTO 1 | |
1121 | #define GS_AUTO 2 | |
1122 | #define ES_AND_GS_AUTO 3 | |
1123 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
1124 | #define VGT_NUM_INSTANCES 0x8974 | |
1125 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C | |
1126 | #define DEALLOC_DIST_MASK 0x0000007F | |
1127 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 | |
1128 | #define VTX_REUSE_DEPTH_MASK 0x000000FF | |
1129 | ||
1130 | #define VM_CONTEXT0_CNTL 0x1410 | |
1131 | #define ENABLE_CONTEXT (1 << 0) | |
1132 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
1133 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) | |
1134 | #define VM_CONTEXT1_CNTL 0x1414 | |
ae133a11 | 1135 | #define VM_CONTEXT1_CNTL2 0x1434 |
0fcdb61e AD |
1136 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
1137 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | |
1138 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C | |
1139 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 | |
1140 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 | |
1141 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) | |
1142 | #define RESPONSE_TYPE_MASK 0x000000F0 | |
1143 | #define RESPONSE_TYPE_SHIFT 4 | |
1144 | #define VM_L2_CNTL 0x1400 | |
1145 | #define ENABLE_L2_CACHE (1 << 0) | |
1146 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
1147 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
1148 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) | |
1149 | #define VM_L2_CNTL2 0x1404 | |
1150 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
1151 | #define INVALIDATE_L2_CACHE (1 << 1) | |
1152 | #define VM_L2_CNTL3 0x1408 | |
1153 | #define BANK_SELECT(x) ((x) << 0) | |
1154 | #define CACHE_UPDATE_MODE(x) ((x) << 6) | |
1155 | #define VM_L2_STATUS 0x140C | |
1156 | #define L2_BUSY (1 << 0) | |
ae133a11 CK |
1157 | #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
1158 | #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC | |
0fcdb61e AD |
1159 | |
1160 | #define WAIT_UNTIL 0x8040 | |
1161 | ||
1162 | #define SRBM_STATUS 0x0E50 | |
a65a4369 AD |
1163 | #define RLC_RQ_PENDING (1 << 3) |
1164 | #define GRBM_RQ_PENDING (1 << 5) | |
1165 | #define VMC_BUSY (1 << 8) | |
1166 | #define MCB_BUSY (1 << 9) | |
1167 | #define MCB_NON_DISPLAY_BUSY (1 << 10) | |
1168 | #define MCC_BUSY (1 << 11) | |
1169 | #define MCD_BUSY (1 << 12) | |
1170 | #define SEM_BUSY (1 << 14) | |
1171 | #define RLC_BUSY (1 << 15) | |
1172 | #define IH_BUSY (1 << 17) | |
1173 | #define SRBM_STATUS2 0x0EC4 | |
1174 | #define DMA_BUSY (1 << 5) | |
747943ea AD |
1175 | #define SRBM_SOFT_RESET 0x0E60 |
1176 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 | |
1177 | #define SOFT_RESET_BIF (1 << 1) | |
1178 | #define SOFT_RESET_CG (1 << 2) | |
1179 | #define SOFT_RESET_DC (1 << 5) | |
1180 | #define SOFT_RESET_GRBM (1 << 8) | |
1181 | #define SOFT_RESET_HDP (1 << 9) | |
1182 | #define SOFT_RESET_IH (1 << 10) | |
1183 | #define SOFT_RESET_MC (1 << 11) | |
1184 | #define SOFT_RESET_RLC (1 << 13) | |
1185 | #define SOFT_RESET_ROM (1 << 14) | |
1186 | #define SOFT_RESET_SEM (1 << 15) | |
1187 | #define SOFT_RESET_VMC (1 << 17) | |
64c56e8c | 1188 | #define SOFT_RESET_DMA (1 << 20) |
747943ea | 1189 | #define SOFT_RESET_TST (1 << 21) |
64c56e8c | 1190 | #define SOFT_RESET_REGBB (1 << 22) |
747943ea | 1191 | #define SOFT_RESET_ORB (1 << 23) |
0fcdb61e | 1192 | |
f9d9c362 AD |
1193 | /* display watermarks */ |
1194 | #define DC_LB_MEMORY_SPLIT 0x6b0c | |
1195 | #define PRIORITY_A_CNT 0x6b18 | |
1196 | #define PRIORITY_MARK_MASK 0x7fff | |
1197 | #define PRIORITY_OFF (1 << 16) | |
1198 | #define PRIORITY_ALWAYS_ON (1 << 20) | |
1199 | #define PRIORITY_B_CNT 0x6b1c | |
1200 | #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 | |
1201 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) | |
1202 | #define PIPE0_LATENCY_CONTROL 0x0bf4 | |
1203 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) | |
1204 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) | |
1205 | ||
0b31e023 AD |
1206 | #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 |
1207 | # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) | |
1208 | # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) | |
1209 | ||
45f9a39b AD |
1210 | #define IH_RB_CNTL 0x3e00 |
1211 | # define IH_RB_ENABLE (1 << 0) | |
1212 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ | |
1213 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) | |
1214 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) | |
1215 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ | |
1216 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) | |
1217 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) | |
1218 | #define IH_RB_BASE 0x3e04 | |
1219 | #define IH_RB_RPTR 0x3e08 | |
1220 | #define IH_RB_WPTR 0x3e0c | |
1221 | # define RB_OVERFLOW (1 << 0) | |
1222 | # define WPTR_OFFSET_MASK 0x3fffc | |
1223 | #define IH_RB_WPTR_ADDR_HI 0x3e10 | |
1224 | #define IH_RB_WPTR_ADDR_LO 0x3e14 | |
1225 | #define IH_CNTL 0x3e18 | |
1226 | # define ENABLE_INTR (1 << 0) | |
fcb857ab | 1227 | # define IH_MC_SWAP(x) ((x) << 1) |
45f9a39b AD |
1228 | # define IH_MC_SWAP_NONE 0 |
1229 | # define IH_MC_SWAP_16BIT 1 | |
1230 | # define IH_MC_SWAP_32BIT 2 | |
1231 | # define IH_MC_SWAP_64BIT 3 | |
1232 | # define RPTR_REARM (1 << 4) | |
1233 | # define MC_WRREQ_CREDIT(x) ((x) << 15) | |
1234 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) | |
1235 | ||
1236 | #define CP_INT_CNTL 0xc124 | |
1237 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | |
1238 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) | |
1239 | # define SCRATCH_INT_ENABLE (1 << 25) | |
1240 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
1241 | # define IB2_INT_ENABLE (1 << 29) | |
1242 | # define IB1_INT_ENABLE (1 << 30) | |
1243 | # define RB_INT_ENABLE (1 << 31) | |
1244 | #define CP_INT_STATUS 0xc128 | |
1245 | # define SCRATCH_INT_STAT (1 << 25) | |
1246 | # define TIME_STAMP_INT_STAT (1 << 26) | |
1247 | # define IB2_INT_STAT (1 << 29) | |
1248 | # define IB1_INT_STAT (1 << 30) | |
1249 | # define RB_INT_STAT (1 << 31) | |
1250 | ||
1251 | #define GRBM_INT_CNTL 0x8060 | |
1252 | # define RDERR_INT_ENABLE (1 << 0) | |
1253 | # define GUI_IDLE_INT_ENABLE (1 << 19) | |
1254 | ||
1255 | /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ | |
1256 | #define CRTC_STATUS_FRAME_COUNT 0x6e98 | |
1257 | ||
1258 | /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ | |
1259 | #define VLINE_STATUS 0x6bb8 | |
1260 | # define VLINE_OCCURRED (1 << 0) | |
1261 | # define VLINE_ACK (1 << 4) | |
1262 | # define VLINE_STAT (1 << 12) | |
1263 | # define VLINE_INTERRUPT (1 << 16) | |
1264 | # define VLINE_INTERRUPT_TYPE (1 << 17) | |
1265 | /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ | |
1266 | #define VBLANK_STATUS 0x6bbc | |
1267 | # define VBLANK_OCCURRED (1 << 0) | |
1268 | # define VBLANK_ACK (1 << 4) | |
1269 | # define VBLANK_STAT (1 << 12) | |
1270 | # define VBLANK_INTERRUPT (1 << 16) | |
1271 | # define VBLANK_INTERRUPT_TYPE (1 << 17) | |
1272 | ||
1273 | /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ | |
1274 | #define INT_MASK 0x6b40 | |
1275 | # define VBLANK_INT_MASK (1 << 0) | |
1276 | # define VLINE_INT_MASK (1 << 4) | |
1277 | ||
1278 | #define DISP_INTERRUPT_STATUS 0x60f4 | |
1279 | # define LB_D1_VLINE_INTERRUPT (1 << 2) | |
1280 | # define LB_D1_VBLANK_INTERRUPT (1 << 3) | |
1281 | # define DC_HPD1_INTERRUPT (1 << 17) | |
1282 | # define DC_HPD1_RX_INTERRUPT (1 << 18) | |
1283 | # define DACA_AUTODETECT_INTERRUPT (1 << 22) | |
1284 | # define DACB_AUTODETECT_INTERRUPT (1 << 23) | |
1285 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) | |
1286 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) | |
1287 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 | |
1288 | # define LB_D2_VLINE_INTERRUPT (1 << 2) | |
1289 | # define LB_D2_VBLANK_INTERRUPT (1 << 3) | |
1290 | # define DC_HPD2_INTERRUPT (1 << 17) | |
1291 | # define DC_HPD2_RX_INTERRUPT (1 << 18) | |
1292 | # define DISP_TIMER_INTERRUPT (1 << 24) | |
1293 | #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc | |
1294 | # define LB_D3_VLINE_INTERRUPT (1 << 2) | |
1295 | # define LB_D3_VBLANK_INTERRUPT (1 << 3) | |
1296 | # define DC_HPD3_INTERRUPT (1 << 17) | |
1297 | # define DC_HPD3_RX_INTERRUPT (1 << 18) | |
1298 | #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 | |
1299 | # define LB_D4_VLINE_INTERRUPT (1 << 2) | |
1300 | # define LB_D4_VBLANK_INTERRUPT (1 << 3) | |
1301 | # define DC_HPD4_INTERRUPT (1 << 17) | |
1302 | # define DC_HPD4_RX_INTERRUPT (1 << 18) | |
1303 | #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c | |
1304 | # define LB_D5_VLINE_INTERRUPT (1 << 2) | |
1305 | # define LB_D5_VBLANK_INTERRUPT (1 << 3) | |
1306 | # define DC_HPD5_INTERRUPT (1 << 17) | |
1307 | # define DC_HPD5_RX_INTERRUPT (1 << 18) | |
37cba6c6 | 1308 | #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
45f9a39b AD |
1309 | # define LB_D6_VLINE_INTERRUPT (1 << 2) |
1310 | # define LB_D6_VBLANK_INTERRUPT (1 << 3) | |
1311 | # define DC_HPD6_INTERRUPT (1 << 17) | |
1312 | # define DC_HPD6_RX_INTERRUPT (1 << 18) | |
1313 | ||
1314 | /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ | |
1315 | #define GRPH_INT_STATUS 0x6858 | |
1316 | # define GRPH_PFLIP_INT_OCCURRED (1 << 0) | |
1317 | # define GRPH_PFLIP_INT_CLEAR (1 << 8) | |
1318 | /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ | |
1319 | #define GRPH_INT_CONTROL 0x685c | |
1320 | # define GRPH_PFLIP_INT_MASK (1 << 0) | |
1321 | # define GRPH_PFLIP_INT_TYPE (1 << 8) | |
1322 | ||
1323 | #define DACA_AUTODETECT_INT_CONTROL 0x66c8 | |
1324 | #define DACB_AUTODETECT_INT_CONTROL 0x67c8 | |
1325 | ||
1326 | #define DC_HPD1_INT_STATUS 0x601c | |
1327 | #define DC_HPD2_INT_STATUS 0x6028 | |
1328 | #define DC_HPD3_INT_STATUS 0x6034 | |
1329 | #define DC_HPD4_INT_STATUS 0x6040 | |
1330 | #define DC_HPD5_INT_STATUS 0x604c | |
1331 | #define DC_HPD6_INT_STATUS 0x6058 | |
1332 | # define DC_HPDx_INT_STATUS (1 << 0) | |
1333 | # define DC_HPDx_SENSE (1 << 1) | |
1334 | # define DC_HPDx_RX_INT_STATUS (1 << 8) | |
1335 | ||
1336 | #define DC_HPD1_INT_CONTROL 0x6020 | |
1337 | #define DC_HPD2_INT_CONTROL 0x602c | |
1338 | #define DC_HPD3_INT_CONTROL 0x6038 | |
1339 | #define DC_HPD4_INT_CONTROL 0x6044 | |
1340 | #define DC_HPD5_INT_CONTROL 0x6050 | |
1341 | #define DC_HPD6_INT_CONTROL 0x605c | |
1342 | # define DC_HPDx_INT_ACK (1 << 0) | |
1343 | # define DC_HPDx_INT_POLARITY (1 << 8) | |
1344 | # define DC_HPDx_INT_EN (1 << 16) | |
1345 | # define DC_HPDx_RX_INT_ACK (1 << 20) | |
1346 | # define DC_HPDx_RX_INT_EN (1 << 24) | |
1347 | ||
1348 | #define DC_HPD1_CONTROL 0x6024 | |
1349 | #define DC_HPD2_CONTROL 0x6030 | |
1350 | #define DC_HPD3_CONTROL 0x603c | |
1351 | #define DC_HPD4_CONTROL 0x6048 | |
1352 | #define DC_HPD5_CONTROL 0x6054 | |
1353 | #define DC_HPD6_CONTROL 0x6060 | |
1354 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) | |
1355 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | |
1356 | # define DC_HPDx_EN (1 << 28) | |
1357 | ||
134b480f AD |
1358 | /* DCE4/5/6 FMT blocks */ |
1359 | #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 | |
1360 | # define FMT_DYNAMIC_EXP_EN (1 << 0) | |
1361 | # define FMT_DYNAMIC_EXP_MODE (1 << 4) | |
1362 | /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ | |
1363 | #define FMT_CONTROL 0x6fb8 | |
1364 | # define FMT_PIXEL_ENCODING (1 << 16) | |
1365 | /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ | |
1366 | #define FMT_BIT_DEPTH_CONTROL 0x6fc8 | |
1367 | # define FMT_TRUNCATE_EN (1 << 0) | |
1368 | # define FMT_TRUNCATE_DEPTH (1 << 4) | |
1369 | # define FMT_SPATIAL_DITHER_EN (1 << 8) | |
1370 | # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) | |
1371 | # define FMT_SPATIAL_DITHER_DEPTH (1 << 12) | |
1372 | # define FMT_FRAME_RANDOM_ENABLE (1 << 13) | |
1373 | # define FMT_RGB_RANDOM_ENABLE (1 << 14) | |
1374 | # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) | |
1375 | # define FMT_TEMPORAL_DITHER_EN (1 << 16) | |
1376 | # define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) | |
1377 | # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) | |
1378 | # define FMT_TEMPORAL_LEVEL (1 << 24) | |
1379 | # define FMT_TEMPORAL_DITHER_RESET (1 << 25) | |
1380 | # define FMT_25FRC_SEL(x) ((x) << 26) | |
1381 | # define FMT_50FRC_SEL(x) ((x) << 28) | |
1382 | # define FMT_75FRC_SEL(x) ((x) << 30) | |
1383 | #define FMT_CLAMP_CONTROL 0x6fe4 | |
1384 | # define FMT_CLAMP_DATA_EN (1 << 0) | |
1385 | # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) | |
1386 | # define FMT_CLAMP_6BPC 0 | |
1387 | # define FMT_CLAMP_8BPC 1 | |
1388 | # define FMT_CLAMP_10BPC 2 | |
1389 | ||
233d1ad5 AD |
1390 | /* ASYNC DMA */ |
1391 | #define DMA_RB_RPTR 0xd008 | |
1392 | #define DMA_RB_WPTR 0xd00c | |
1393 | ||
1394 | #define DMA_CNTL 0xd02c | |
1395 | # define TRAP_ENABLE (1 << 0) | |
1396 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | |
1397 | # define SEM_WAIT_INT_ENABLE (1 << 2) | |
1398 | # define DATA_SWAP_ENABLE (1 << 3) | |
1399 | # define FENCE_SWAP_ENABLE (1 << 4) | |
1400 | # define CTXEMPTY_INT_ENABLE (1 << 28) | |
1401 | #define DMA_TILING_CONFIG 0xD0B8 | |
1402 | ||
f60cbd11 AD |
1403 | #define CAYMAN_DMA1_CNTL 0xd82c |
1404 | ||
233d1ad5 | 1405 | /* async DMA packets */ |
0fcb6155 JG |
1406 | #define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \ |
1407 | (((sub_cmd) & 0xFF) << 20) |\ | |
1408 | (((n) & 0xFFFFF) << 0)) | |
1409 | #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) | |
1410 | #define GET_DMA_COUNT(h) ((h) & 0x000fffff) | |
1411 | #define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20) | |
1412 | ||
233d1ad5 | 1413 | /* async DMA Packet types */ |
0fcb6155 JG |
1414 | #define DMA_PACKET_WRITE 0x2 |
1415 | #define DMA_PACKET_COPY 0x3 | |
1416 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | |
1417 | #define DMA_PACKET_SEMAPHORE 0x5 | |
1418 | #define DMA_PACKET_FENCE 0x6 | |
1419 | #define DMA_PACKET_TRAP 0x7 | |
1420 | #define DMA_PACKET_SRBM_WRITE 0x9 | |
1421 | #define DMA_PACKET_CONSTANT_FILL 0xd | |
1422 | #define DMA_PACKET_NOP 0xf | |
233d1ad5 | 1423 | |
f52382d7 AD |
1424 | /* PIF PHY0 indirect regs */ |
1425 | #define PB0_PIF_CNTL 0x10 | |
1426 | # define LS2_EXIT_TIME(x) ((x) << 17) | |
1427 | # define LS2_EXIT_TIME_MASK (0x7 << 17) | |
1428 | # define LS2_EXIT_TIME_SHIFT 17 | |
1429 | #define PB0_PIF_PAIRING 0x11 | |
1430 | # define MULTI_PIF (1 << 25) | |
1431 | #define PB0_PIF_PWRDOWN_0 0x12 | |
1432 | # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) | |
1433 | # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) | |
1434 | # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 | |
1435 | # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) | |
1436 | # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) | |
1437 | # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 | |
1438 | # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) | |
1439 | # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) | |
1440 | # define PLL_RAMP_UP_TIME_0_SHIFT 24 | |
1441 | #define PB0_PIF_PWRDOWN_1 0x13 | |
1442 | # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) | |
1443 | # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) | |
1444 | # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 | |
1445 | # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) | |
1446 | # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) | |
1447 | # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 | |
1448 | # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) | |
1449 | # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) | |
1450 | # define PLL_RAMP_UP_TIME_1_SHIFT 24 | |
1451 | /* PIF PHY1 indirect regs */ | |
1452 | #define PB1_PIF_CNTL 0x10 | |
1453 | #define PB1_PIF_PAIRING 0x11 | |
1454 | #define PB1_PIF_PWRDOWN_0 0x12 | |
1455 | #define PB1_PIF_PWRDOWN_1 0x13 | |
1456 | /* PCIE PORT indirect regs */ | |
1457 | #define PCIE_LC_CNTL 0xa0 | |
1458 | # define LC_L0S_INACTIVITY(x) ((x) << 8) | |
1459 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) | |
1460 | # define LC_L0S_INACTIVITY_SHIFT 8 | |
1461 | # define LC_L1_INACTIVITY(x) ((x) << 12) | |
1462 | # define LC_L1_INACTIVITY_MASK (0xf << 12) | |
1463 | # define LC_L1_INACTIVITY_SHIFT 12 | |
1464 | # define LC_PMI_TO_L1_DIS (1 << 16) | |
1465 | # define LC_ASPM_TO_L1_DIS (1 << 24) | |
9e46a48d AD |
1466 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
1467 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ | |
1468 | # define LC_LINK_WIDTH_SHIFT 0 | |
1469 | # define LC_LINK_WIDTH_MASK 0x7 | |
1470 | # define LC_LINK_WIDTH_X0 0 | |
1471 | # define LC_LINK_WIDTH_X1 1 | |
1472 | # define LC_LINK_WIDTH_X2 2 | |
1473 | # define LC_LINK_WIDTH_X4 3 | |
1474 | # define LC_LINK_WIDTH_X8 4 | |
1475 | # define LC_LINK_WIDTH_X16 6 | |
1476 | # define LC_LINK_WIDTH_RD_SHIFT 4 | |
1477 | # define LC_LINK_WIDTH_RD_MASK 0x70 | |
1478 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | |
1479 | # define LC_RECONFIG_NOW (1 << 8) | |
1480 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | |
1481 | # define LC_RENEGOTIATE_EN (1 << 10) | |
1482 | # define LC_SHORT_RECONFIG_EN (1 << 11) | |
1483 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | |
1484 | # define LC_UPCONFIGURE_DIS (1 << 13) | |
f52382d7 AD |
1485 | # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) |
1486 | # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) | |
1487 | # define LC_DYN_LANES_PWR_STATE_SHIFT 21 | |
9e46a48d AD |
1488 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
1489 | # define LC_GEN2_EN_STRAP (1 << 0) | |
1490 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | |
1491 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) | |
1492 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) | |
1493 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) | |
1494 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 | |
1495 | # define LC_CURRENT_DATA_RATE (1 << 11) | |
dc50ba7f AD |
1496 | # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) |
1497 | # define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) | |
1498 | # define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 | |
9e46a48d AD |
1499 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) |
1500 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) | |
1501 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) | |
1502 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) | |
1503 | #define MM_CFGREGS_CNTL 0x544c | |
1504 | # define MM_WR_TO_CFG_EN (1 << 3) | |
1505 | #define LINK_CNTL2 0x88 /* F0 */ | |
1506 | # define TARGET_LINK_SPEED_MASK (0xf << 0) | |
1507 | # define SELECTABLE_DEEMPHASIS (1 << 6) | |
1508 | ||
f2ba57b5 CK |
1509 | |
1510 | /* | |
1511 | * UVD | |
1512 | */ | |
9a21059d CK |
1513 | #define UVD_UDEC_ADDR_CONFIG 0xef4c |
1514 | #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 | |
1515 | #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 | |
f2ba57b5 CK |
1516 | #define UVD_RBC_RB_RPTR 0xf690 |
1517 | #define UVD_RBC_RB_WPTR 0xf694 | |
1518 | ||
cb5fcbd5 AD |
1519 | /* |
1520 | * PM4 | |
1521 | */ | |
4e872ae2 | 1522 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
cb5fcbd5 AD |
1523 | (((reg) >> 2) & 0xFFFF) | \ |
1524 | ((n) & 0x3FFF) << 16) | |
1525 | #define CP_PACKET2 0x80000000 | |
1526 | #define PACKET2_PAD_SHIFT 0 | |
1527 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
1528 | ||
1529 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
1530 | ||
4e872ae2 | 1531 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
cb5fcbd5 AD |
1532 | (((op) & 0xFF) << 8) | \ |
1533 | ((n) & 0x3FFF) << 16) | |
1534 | ||
1535 | /* Packet 3 types */ | |
1536 | #define PACKET3_NOP 0x10 | |
1537 | #define PACKET3_SET_BASE 0x11 | |
1538 | #define PACKET3_CLEAR_STATE 0x12 | |
32171d22 | 1539 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
cb5fcbd5 AD |
1540 | #define PACKET3_DISPATCH_DIRECT 0x15 |
1541 | #define PACKET3_DISPATCH_INDIRECT 0x16 | |
1542 | #define PACKET3_INDIRECT_BUFFER_END 0x17 | |
12920591 | 1543 | #define PACKET3_MODE_CONTROL 0x18 |
cb5fcbd5 AD |
1544 | #define PACKET3_SET_PREDICATION 0x20 |
1545 | #define PACKET3_REG_RMW 0x21 | |
1546 | #define PACKET3_COND_EXEC 0x22 | |
1547 | #define PACKET3_PRED_EXEC 0x23 | |
1548 | #define PACKET3_DRAW_INDIRECT 0x24 | |
1549 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 | |
1550 | #define PACKET3_INDEX_BASE 0x26 | |
1551 | #define PACKET3_DRAW_INDEX_2 0x27 | |
1552 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
1553 | #define PACKET3_DRAW_INDEX_OFFSET 0x29 | |
1554 | #define PACKET3_INDEX_TYPE 0x2A | |
1555 | #define PACKET3_DRAW_INDEX 0x2B | |
1556 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
1557 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | |
1558 | #define PACKET3_NUM_INSTANCES 0x2F | |
1559 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 | |
1560 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
1561 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 | |
1562 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 | |
1563 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
1564 | #define PACKET3_MPEG_INDEX 0x3A | |
721604a1 | 1565 | #define PACKET3_COPY_DW 0x3B |
cb5fcbd5 AD |
1566 | #define PACKET3_WAIT_REG_MEM 0x3C |
1567 | #define PACKET3_MEM_WRITE 0x3D | |
1568 | #define PACKET3_INDIRECT_BUFFER 0x32 | |
b997a8ba AD |
1569 | #define PACKET3_CP_DMA 0x41 |
1570 | /* 1. header | |
1571 | * 2. SRC_ADDR_LO or DATA [31:0] | |
1572 | * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | | |
1573 | * SRC_ADDR_HI [7:0] | |
1574 | * 4. DST_ADDR_LO [31:0] | |
1575 | * 5. DST_ADDR_HI [7:0] | |
1576 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] | |
1577 | */ | |
1578 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) | |
aa3e146d | 1579 | /* 0 - DST_ADDR |
b997a8ba AD |
1580 | * 1 - GDS |
1581 | */ | |
1582 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) | |
1583 | /* 0 - ME | |
1584 | * 1 - PFP | |
1585 | */ | |
1586 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) | |
1587 | /* 0 - SRC_ADDR | |
1588 | * 1 - GDS | |
1589 | * 2 - DATA | |
1590 | */ | |
1591 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) | |
1592 | /* COMMAND */ | |
1593 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) | |
aa3e146d | 1594 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) |
b997a8ba AD |
1595 | /* 0 - none |
1596 | * 1 - 8 in 16 | |
1597 | * 2 - 8 in 32 | |
1598 | * 3 - 8 in 64 | |
1599 | */ | |
1600 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) | |
1601 | /* 0 - none | |
1602 | * 1 - 8 in 16 | |
1603 | * 2 - 8 in 32 | |
1604 | * 3 - 8 in 64 | |
1605 | */ | |
1606 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) | |
1607 | /* 0 - memory | |
1608 | * 1 - register | |
1609 | */ | |
1610 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) | |
1611 | /* 0 - memory | |
1612 | * 1 - register | |
1613 | */ | |
1614 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | |
1615 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | |
cb5fcbd5 AD |
1616 | #define PACKET3_SURFACE_SYNC 0x43 |
1617 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
1618 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) | |
1619 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) | |
1620 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) | |
1621 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) | |
1622 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) | |
1623 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) | |
1624 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) | |
1625 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) | |
1626 | # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) | |
1627 | # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) | |
1628 | # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) | |
32171d22 | 1629 | # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) |
cb5fcbd5 AD |
1630 | # define PACKET3_FULL_CACHE_ENA (1 << 20) |
1631 | # define PACKET3_TC_ACTION_ENA (1 << 23) | |
1632 | # define PACKET3_VC_ACTION_ENA (1 << 24) | |
1633 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
1634 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
1635 | # define PACKET3_SH_ACTION_ENA (1 << 27) | |
32171d22 | 1636 | # define PACKET3_SX_ACTION_ENA (1 << 28) |
cb5fcbd5 AD |
1637 | #define PACKET3_ME_INITIALIZE 0x44 |
1638 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | |
1639 | #define PACKET3_COND_WRITE 0x45 | |
1640 | #define PACKET3_EVENT_WRITE 0x46 | |
1641 | #define PACKET3_EVENT_WRITE_EOP 0x47 | |
1642 | #define PACKET3_EVENT_WRITE_EOS 0x48 | |
1643 | #define PACKET3_PREAMBLE_CNTL 0x4A | |
2281a378 AD |
1644 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
1645 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | |
cb5fcbd5 AD |
1646 | #define PACKET3_RB_OFFSET 0x4B |
1647 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C | |
1648 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D | |
1649 | #define PACKET3_ALU_PS_CONST_UPDATE 0x4E | |
1650 | #define PACKET3_ALU_VS_CONST_UPDATE 0x4F | |
1651 | #define PACKET3_ONE_REG_WRITE 0x57 | |
1652 | #define PACKET3_SET_CONFIG_REG 0x68 | |
1653 | #define PACKET3_SET_CONFIG_REG_START 0x00008000 | |
1654 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 | |
1655 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
1656 | #define PACKET3_SET_CONTEXT_REG_START 0x00028000 | |
1657 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
1658 | #define PACKET3_SET_ALU_CONST 0x6A | |
1659 | /* alu const buffers only; no reg file */ | |
1660 | #define PACKET3_SET_BOOL_CONST 0x6B | |
1661 | #define PACKET3_SET_BOOL_CONST_START 0x0003a500 | |
1662 | #define PACKET3_SET_BOOL_CONST_END 0x0003a518 | |
1663 | #define PACKET3_SET_LOOP_CONST 0x6C | |
1664 | #define PACKET3_SET_LOOP_CONST_START 0x0003a200 | |
1665 | #define PACKET3_SET_LOOP_CONST_END 0x0003a500 | |
1666 | #define PACKET3_SET_RESOURCE 0x6D | |
1667 | #define PACKET3_SET_RESOURCE_START 0x00030000 | |
1668 | #define PACKET3_SET_RESOURCE_END 0x00038000 | |
1669 | #define PACKET3_SET_SAMPLER 0x6E | |
1670 | #define PACKET3_SET_SAMPLER_START 0x0003c000 | |
1671 | #define PACKET3_SET_SAMPLER_END 0x0003c600 | |
1672 | #define PACKET3_SET_CTL_CONST 0x6F | |
1673 | #define PACKET3_SET_CTL_CONST_START 0x0003cff0 | |
1674 | #define PACKET3_SET_CTL_CONST_END 0x0003ff0c | |
1675 | #define PACKET3_SET_RESOURCE_OFFSET 0x70 | |
1676 | #define PACKET3_SET_ALU_CONST_VS 0x71 | |
1677 | #define PACKET3_SET_ALU_CONST_DI 0x72 | |
1678 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 | |
1679 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 | |
1680 | #define PACKET3_SET_APPEND_CNT 0x75 | |
1681 | ||
1682 | #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c | |
1683 | #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) | |
1684 | #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) | |
1685 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 | |
1686 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 | |
1687 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 | |
1688 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 | |
1689 | ||
721604a1 JG |
1690 | #define VGT_VTX_VECT_EJECT_REG 0x88b0 |
1691 | ||
cb5fcbd5 AD |
1692 | #define SQ_CONST_MEM_BASE 0x8df8 |
1693 | ||
8aa75009 | 1694 | #define SQ_ESGS_RING_BASE 0x8c40 |
cb5fcbd5 | 1695 | #define SQ_ESGS_RING_SIZE 0x8c44 |
8aa75009 | 1696 | #define SQ_GSVS_RING_BASE 0x8c48 |
cb5fcbd5 | 1697 | #define SQ_GSVS_RING_SIZE 0x8c4c |
8aa75009 | 1698 | #define SQ_ESTMP_RING_BASE 0x8c50 |
cb5fcbd5 | 1699 | #define SQ_ESTMP_RING_SIZE 0x8c54 |
8aa75009 | 1700 | #define SQ_GSTMP_RING_BASE 0x8c58 |
cb5fcbd5 | 1701 | #define SQ_GSTMP_RING_SIZE 0x8c5c |
8aa75009 | 1702 | #define SQ_VSTMP_RING_BASE 0x8c60 |
cb5fcbd5 | 1703 | #define SQ_VSTMP_RING_SIZE 0x8c64 |
8aa75009 | 1704 | #define SQ_PSTMP_RING_BASE 0x8c68 |
cb5fcbd5 | 1705 | #define SQ_PSTMP_RING_SIZE 0x8c6c |
8aa75009 | 1706 | #define SQ_LSTMP_RING_BASE 0x8e10 |
cb5fcbd5 | 1707 | #define SQ_LSTMP_RING_SIZE 0x8e14 |
8aa75009 | 1708 | #define SQ_HSTMP_RING_BASE 0x8e18 |
cb5fcbd5 AD |
1709 | #define SQ_HSTMP_RING_SIZE 0x8e1c |
1710 | #define VGT_TF_RING_SIZE 0x8988 | |
1711 | ||
1712 | #define SQ_ESGS_RING_ITEMSIZE 0x28900 | |
1713 | #define SQ_GSVS_RING_ITEMSIZE 0x28904 | |
1714 | #define SQ_ESTMP_RING_ITEMSIZE 0x28908 | |
1715 | #define SQ_GSTMP_RING_ITEMSIZE 0x2890c | |
1716 | #define SQ_VSTMP_RING_ITEMSIZE 0x28910 | |
1717 | #define SQ_PSTMP_RING_ITEMSIZE 0x28914 | |
1718 | #define SQ_LSTMP_RING_ITEMSIZE 0x28830 | |
1719 | #define SQ_HSTMP_RING_ITEMSIZE 0x28834 | |
1720 | ||
1721 | #define SQ_GS_VERT_ITEMSIZE 0x2891c | |
1722 | #define SQ_GS_VERT_ITEMSIZE_1 0x28920 | |
1723 | #define SQ_GS_VERT_ITEMSIZE_2 0x28924 | |
1724 | #define SQ_GS_VERT_ITEMSIZE_3 0x28928 | |
1725 | #define SQ_GSVS_RING_OFFSET_1 0x2892c | |
1726 | #define SQ_GSVS_RING_OFFSET_2 0x28930 | |
1727 | #define SQ_GSVS_RING_OFFSET_3 0x28934 | |
1728 | ||
60a4a3e0 AD |
1729 | #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 |
1730 | #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 | |
1731 | ||
cb5fcbd5 AD |
1732 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
1733 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 | |
1734 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 | |
1735 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c | |
1736 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 | |
1737 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 | |
1738 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 | |
1739 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c | |
1740 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 | |
1741 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 | |
1742 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 | |
1743 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c | |
1744 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 | |
1745 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 | |
1746 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 | |
1747 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c | |
1748 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 | |
1749 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 | |
1750 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 | |
1751 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c | |
1752 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 | |
1753 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 | |
1754 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 | |
1755 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c | |
1756 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 | |
1757 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 | |
1758 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 | |
1759 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac | |
1760 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 | |
1761 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 | |
1762 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 | |
1763 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc | |
1764 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 | |
1765 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 | |
1766 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 | |
1767 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc | |
1768 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 | |
1769 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 | |
1770 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 | |
1771 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc | |
1772 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 | |
1773 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 | |
1774 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 | |
1775 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec | |
1776 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 | |
1777 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 | |
1778 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 | |
1779 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc | |
1780 | #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 | |
1781 | #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 | |
1782 | #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 | |
1783 | #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c | |
1784 | #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 | |
1785 | #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 | |
1786 | #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 | |
1787 | #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c | |
1788 | #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 | |
1789 | #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 | |
1790 | #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 | |
1791 | #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c | |
1792 | #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 | |
1793 | #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 | |
1794 | #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 | |
1795 | #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c | |
1796 | #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 | |
1797 | #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 | |
1798 | #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 | |
1799 | #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c | |
1800 | #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 | |
1801 | #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 | |
1802 | #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 | |
1803 | #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c | |
1804 | #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 | |
1805 | #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 | |
1806 | #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 | |
1807 | #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c | |
1808 | #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 | |
1809 | #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 | |
1810 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 | |
1811 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c | |
1812 | ||
d7ccd8fc AD |
1813 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
1814 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 | |
1815 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 | |
d7ccd8fc | 1816 | |
721604a1 JG |
1817 | #define VGT_PRIMITIVE_TYPE 0x8958 |
1818 | #define VGT_INDEX_TYPE 0x895C | |
1819 | ||
1820 | #define VGT_NUM_INDICES 0x8970 | |
1821 | ||
1822 | #define VGT_COMPUTE_DIM_X 0x8990 | |
1823 | #define VGT_COMPUTE_DIM_Y 0x8994 | |
1824 | #define VGT_COMPUTE_DIM_Z 0x8998 | |
1825 | #define VGT_COMPUTE_START_X 0x899C | |
1826 | #define VGT_COMPUTE_START_Y 0x89A0 | |
1827 | #define VGT_COMPUTE_START_Z 0x89A4 | |
1828 | #define VGT_COMPUTE_INDEX 0x89A8 | |
1829 | #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC | |
1830 | #define VGT_HS_OFFCHIP_PARAM 0x89B0 | |
1831 | ||
1832 | #define DB_DEBUG 0x9830 | |
1833 | #define DB_DEBUG2 0x9834 | |
1834 | #define DB_DEBUG3 0x9838 | |
1835 | #define DB_DEBUG4 0x983C | |
1836 | #define DB_WATERMARKS 0x9854 | |
cb5fcbd5 | 1837 | #define DB_DEPTH_CONTROL 0x28800 |
285484e2 JG |
1838 | #define R_028800_DB_DEPTH_CONTROL 0x028800 |
1839 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) | |
1840 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) | |
1841 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE | |
1842 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) | |
1843 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) | |
1844 | #define C_028800_Z_ENABLE 0xFFFFFFFD | |
1845 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) | |
1846 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) | |
1847 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB | |
1848 | #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) | |
1849 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) | |
1850 | #define C_028800_ZFUNC 0xFFFFFF8F | |
1851 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) | |
1852 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) | |
1853 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F | |
1854 | #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) | |
1855 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) | |
1856 | #define C_028800_STENCILFUNC 0xFFFFF8FF | |
1857 | #define V_028800_STENCILFUNC_NEVER 0x00000000 | |
1858 | #define V_028800_STENCILFUNC_LESS 0x00000001 | |
1859 | #define V_028800_STENCILFUNC_EQUAL 0x00000002 | |
1860 | #define V_028800_STENCILFUNC_LEQUAL 0x00000003 | |
1861 | #define V_028800_STENCILFUNC_GREATER 0x00000004 | |
1862 | #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 | |
1863 | #define V_028800_STENCILFUNC_GEQUAL 0x00000006 | |
1864 | #define V_028800_STENCILFUNC_ALWAYS 0x00000007 | |
1865 | #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) | |
1866 | #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) | |
1867 | #define C_028800_STENCILFAIL 0xFFFFC7FF | |
1868 | #define V_028800_STENCIL_KEEP 0x00000000 | |
1869 | #define V_028800_STENCIL_ZERO 0x00000001 | |
1870 | #define V_028800_STENCIL_REPLACE 0x00000002 | |
1871 | #define V_028800_STENCIL_INCR 0x00000003 | |
1872 | #define V_028800_STENCIL_DECR 0x00000004 | |
1873 | #define V_028800_STENCIL_INVERT 0x00000005 | |
1874 | #define V_028800_STENCIL_INCR_WRAP 0x00000006 | |
1875 | #define V_028800_STENCIL_DECR_WRAP 0x00000007 | |
1876 | #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) | |
1877 | #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) | |
1878 | #define C_028800_STENCILZPASS 0xFFFE3FFF | |
1879 | #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) | |
1880 | #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) | |
1881 | #define C_028800_STENCILZFAIL 0xFFF1FFFF | |
1882 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) | |
1883 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) | |
1884 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF | |
1885 | #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) | |
1886 | #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) | |
1887 | #define C_028800_STENCILFAIL_BF 0xFC7FFFFF | |
1888 | #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) | |
1889 | #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) | |
1890 | #define C_028800_STENCILZPASS_BF 0xE3FFFFFF | |
1891 | #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) | |
1892 | #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) | |
1893 | #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF | |
cb5fcbd5 | 1894 | #define DB_DEPTH_VIEW 0x28008 |
285484e2 JG |
1895 | #define R_028008_DB_DEPTH_VIEW 0x00028008 |
1896 | #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) | |
1897 | #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) | |
1898 | #define C_028008_SLICE_START 0xFFFFF800 | |
1899 | #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) | |
1900 | #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) | |
1901 | #define C_028008_SLICE_MAX 0xFF001FFF | |
cb5fcbd5 | 1902 | #define DB_HTILE_DATA_BASE 0x28014 |
88f50c80 JG |
1903 | #define DB_HTILE_SURFACE 0x28abc |
1904 | #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) | |
1905 | #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) | |
1906 | #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE | |
1907 | #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) | |
1908 | #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) | |
1909 | #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD | |
1910 | #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) | |
cb5fcbd5 AD |
1911 | #define DB_Z_INFO 0x28040 |
1912 | # define Z_ARRAY_MODE(x) ((x) << 4) | |
f3a71df0 AD |
1913 | # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) |
1914 | # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) | |
1915 | # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) | |
1916 | # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) | |
285484e2 JG |
1917 | # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) |
1918 | #define R_028040_DB_Z_INFO 0x028040 | |
1919 | #define S_028040_FORMAT(x) (((x) & 0x3) << 0) | |
1920 | #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) | |
1921 | #define C_028040_FORMAT 0xFFFFFFFC | |
1922 | #define V_028040_Z_INVALID 0x00000000 | |
1923 | #define V_028040_Z_16 0x00000001 | |
1924 | #define V_028040_Z_24 0x00000002 | |
1925 | #define V_028040_Z_32_FLOAT 0x00000003 | |
1926 | #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) | |
1927 | #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) | |
1928 | #define C_028040_ARRAY_MODE 0xFFFFFF0F | |
1929 | #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) | |
1930 | #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) | |
1931 | #define C_028040_READ_SIZE 0xEFFFFFFF | |
1932 | #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) | |
1933 | #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) | |
1934 | #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF | |
1935 | #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) | |
1936 | #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) | |
1937 | #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF | |
1938 | #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) | |
1939 | #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) | |
1940 | #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) | |
1941 | #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) | |
1942 | #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) | |
1943 | #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) | |
1944 | #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) | |
1945 | #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) | |
1946 | #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) | |
1947 | #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) | |
cb5fcbd5 | 1948 | #define DB_STENCIL_INFO 0x28044 |
285484e2 JG |
1949 | #define R_028044_DB_STENCIL_INFO 0x028044 |
1950 | #define S_028044_FORMAT(x) (((x) & 0x1) << 0) | |
1951 | #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) | |
1952 | #define C_028044_FORMAT 0xFFFFFFFE | |
0f457e48 MO |
1953 | #define V_028044_STENCIL_INVALID 0 |
1954 | #define V_028044_STENCIL_8 1 | |
285484e2 | 1955 | #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) |
cb5fcbd5 AD |
1956 | #define DB_Z_READ_BASE 0x28048 |
1957 | #define DB_STENCIL_READ_BASE 0x2804c | |
1958 | #define DB_Z_WRITE_BASE 0x28050 | |
1959 | #define DB_STENCIL_WRITE_BASE 0x28054 | |
1960 | #define DB_DEPTH_SIZE 0x28058 | |
285484e2 JG |
1961 | #define R_028058_DB_DEPTH_SIZE 0x028058 |
1962 | #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) | |
1963 | #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) | |
1964 | #define C_028058_PITCH_TILE_MAX 0xFFFFF800 | |
1965 | #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) | |
1966 | #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) | |
1967 | #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF | |
1968 | #define R_02805C_DB_DEPTH_SLICE 0x02805C | |
1969 | #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) | |
1970 | #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) | |
1971 | #define C_02805C_SLICE_TILE_MAX 0xFFC00000 | |
cb5fcbd5 AD |
1972 | |
1973 | #define SQ_PGM_START_PS 0x28840 | |
1974 | #define SQ_PGM_START_VS 0x2885c | |
1975 | #define SQ_PGM_START_GS 0x28874 | |
1976 | #define SQ_PGM_START_ES 0x2888c | |
1977 | #define SQ_PGM_START_FS 0x288a4 | |
1978 | #define SQ_PGM_START_HS 0x288b8 | |
1979 | #define SQ_PGM_START_LS 0x288d0 | |
1980 | ||
dd220a00 MO |
1981 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 |
1982 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 | |
1983 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 | |
1984 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 | |
1985 | #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 | |
1986 | #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 | |
1987 | #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 | |
1988 | #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 | |
cb5fcbd5 AD |
1989 | #define VGT_STRMOUT_CONFIG 0x28b94 |
1990 | #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 | |
1991 | ||
1992 | #define CB_TARGET_MASK 0x28238 | |
1993 | #define CB_SHADER_MASK 0x2823c | |
1994 | ||
1995 | #define GDS_ADDR_BASE 0x28720 | |
1996 | ||
1997 | #define CB_IMMED0_BASE 0x28b9c | |
1998 | #define CB_IMMED1_BASE 0x28ba0 | |
1999 | #define CB_IMMED2_BASE 0x28ba4 | |
2000 | #define CB_IMMED3_BASE 0x28ba8 | |
2001 | #define CB_IMMED4_BASE 0x28bac | |
2002 | #define CB_IMMED5_BASE 0x28bb0 | |
2003 | #define CB_IMMED6_BASE 0x28bb4 | |
2004 | #define CB_IMMED7_BASE 0x28bb8 | |
2005 | #define CB_IMMED8_BASE 0x28bbc | |
2006 | #define CB_IMMED9_BASE 0x28bc0 | |
2007 | #define CB_IMMED10_BASE 0x28bc4 | |
2008 | #define CB_IMMED11_BASE 0x28bc8 | |
2009 | ||
2010 | /* all 12 CB blocks have these regs */ | |
2011 | #define CB_COLOR0_BASE 0x28c60 | |
2012 | #define CB_COLOR0_PITCH 0x28c64 | |
2013 | #define CB_COLOR0_SLICE 0x28c68 | |
2014 | #define CB_COLOR0_VIEW 0x28c6c | |
285484e2 JG |
2015 | #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C |
2016 | #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) | |
2017 | #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) | |
2018 | #define C_028C6C_SLICE_START 0xFFFFF800 | |
2019 | #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) | |
2020 | #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) | |
2021 | #define C_028C6C_SLICE_MAX 0xFF001FFF | |
2022 | #define R_028C70_CB_COLOR0_INFO 0x028C70 | |
2023 | #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) | |
2024 | #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) | |
2025 | #define C_028C70_ENDIAN 0xFFFFFFFC | |
2026 | #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) | |
2027 | #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) | |
2028 | #define C_028C70_FORMAT 0xFFFFFF03 | |
2029 | #define V_028C70_COLOR_INVALID 0x00000000 | |
2030 | #define V_028C70_COLOR_8 0x00000001 | |
2031 | #define V_028C70_COLOR_4_4 0x00000002 | |
2032 | #define V_028C70_COLOR_3_3_2 0x00000003 | |
2033 | #define V_028C70_COLOR_16 0x00000005 | |
2034 | #define V_028C70_COLOR_16_FLOAT 0x00000006 | |
2035 | #define V_028C70_COLOR_8_8 0x00000007 | |
2036 | #define V_028C70_COLOR_5_6_5 0x00000008 | |
2037 | #define V_028C70_COLOR_6_5_5 0x00000009 | |
2038 | #define V_028C70_COLOR_1_5_5_5 0x0000000A | |
2039 | #define V_028C70_COLOR_4_4_4_4 0x0000000B | |
2040 | #define V_028C70_COLOR_5_5_5_1 0x0000000C | |
2041 | #define V_028C70_COLOR_32 0x0000000D | |
2042 | #define V_028C70_COLOR_32_FLOAT 0x0000000E | |
2043 | #define V_028C70_COLOR_16_16 0x0000000F | |
2044 | #define V_028C70_COLOR_16_16_FLOAT 0x00000010 | |
2045 | #define V_028C70_COLOR_8_24 0x00000011 | |
2046 | #define V_028C70_COLOR_8_24_FLOAT 0x00000012 | |
2047 | #define V_028C70_COLOR_24_8 0x00000013 | |
2048 | #define V_028C70_COLOR_24_8_FLOAT 0x00000014 | |
2049 | #define V_028C70_COLOR_10_11_11 0x00000015 | |
2050 | #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 | |
2051 | #define V_028C70_COLOR_11_11_10 0x00000017 | |
2052 | #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 | |
2053 | #define V_028C70_COLOR_2_10_10_10 0x00000019 | |
2054 | #define V_028C70_COLOR_8_8_8_8 0x0000001A | |
2055 | #define V_028C70_COLOR_10_10_10_2 0x0000001B | |
2056 | #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C | |
2057 | #define V_028C70_COLOR_32_32 0x0000001D | |
2058 | #define V_028C70_COLOR_32_32_FLOAT 0x0000001E | |
2059 | #define V_028C70_COLOR_16_16_16_16 0x0000001F | |
2060 | #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 | |
2061 | #define V_028C70_COLOR_32_32_32_32 0x00000022 | |
2062 | #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 | |
2063 | #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 | |
2064 | #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) | |
2065 | #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) | |
2066 | #define C_028C70_ARRAY_MODE 0xFFFFF0FF | |
2067 | #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 | |
2068 | #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 | |
2069 | #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 | |
2070 | #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 | |
2071 | #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) | |
2072 | #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) | |
2073 | #define C_028C70_NUMBER_TYPE 0xFFFF8FFF | |
2074 | #define V_028C70_NUMBER_UNORM 0x00000000 | |
2075 | #define V_028C70_NUMBER_SNORM 0x00000001 | |
2076 | #define V_028C70_NUMBER_USCALED 0x00000002 | |
2077 | #define V_028C70_NUMBER_SSCALED 0x00000003 | |
2078 | #define V_028C70_NUMBER_UINT 0x00000004 | |
2079 | #define V_028C70_NUMBER_SINT 0x00000005 | |
2080 | #define V_028C70_NUMBER_SRGB 0x00000006 | |
2081 | #define V_028C70_NUMBER_FLOAT 0x00000007 | |
2082 | #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) | |
2083 | #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) | |
2084 | #define C_028C70_COMP_SWAP 0xFFFE7FFF | |
2085 | #define V_028C70_SWAP_STD 0x00000000 | |
2086 | #define V_028C70_SWAP_ALT 0x00000001 | |
2087 | #define V_028C70_SWAP_STD_REV 0x00000002 | |
2088 | #define V_028C70_SWAP_ALT_REV 0x00000003 | |
2089 | #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) | |
2090 | #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) | |
2091 | #define C_028C70_FAST_CLEAR 0xFFFDFFFF | |
2092 | #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) | |
2093 | #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) | |
2094 | #define C_028C70_COMPRESSION 0xFFF3FFFF | |
2095 | #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) | |
2096 | #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) | |
2097 | #define C_028C70_BLEND_CLAMP 0xFFF7FFFF | |
2098 | #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) | |
2099 | #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) | |
2100 | #define C_028C70_BLEND_BYPASS 0xFFEFFFFF | |
2101 | #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) | |
2102 | #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) | |
2103 | #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF | |
2104 | #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) | |
2105 | #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) | |
2106 | #define C_028C70_ROUND_MODE 0xFFBFFFFF | |
2107 | #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) | |
2108 | #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) | |
2109 | #define C_028C70_TILE_COMPACT 0xFF7FFFFF | |
2110 | #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) | |
2111 | #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) | |
2112 | #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF | |
2113 | #define V_028C70_EXPORT_4C_32BPC 0x0 | |
2114 | #define V_028C70_EXPORT_4C_16BPC 0x1 | |
2115 | #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ | |
2116 | #define S_028C70_RAT(x) (((x) & 0x1) << 26) | |
2117 | #define G_028C70_RAT(x) (((x) >> 26) & 0x1) | |
2118 | #define C_028C70_RAT 0xFBFFFFFF | |
2119 | #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) | |
2120 | #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) | |
2121 | #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF | |
2122 | ||
cb5fcbd5 | 2123 | #define CB_COLOR0_INFO 0x28c70 |
6018faf5 | 2124 | # define CB_FORMAT(x) ((x) << 2) |
cb5fcbd5 AD |
2125 | # define CB_ARRAY_MODE(x) ((x) << 8) |
2126 | # define ARRAY_LINEAR_GENERAL 0 | |
2127 | # define ARRAY_LINEAR_ALIGNED 1 | |
2128 | # define ARRAY_1D_TILED_THIN1 2 | |
2129 | # define ARRAY_2D_TILED_THIN1 4 | |
6018faf5 IH |
2130 | # define CB_SOURCE_FORMAT(x) ((x) << 24) |
2131 | # define CB_SF_EXPORT_FULL 0 | |
2132 | # define CB_SF_EXPORT_NORM 1 | |
285484e2 JG |
2133 | #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 |
2134 | #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) | |
2135 | #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) | |
2136 | #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF | |
2137 | #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) | |
2138 | #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) | |
2139 | #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) | |
2140 | #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) | |
2141 | #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) | |
2142 | #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) | |
2143 | #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) | |
2144 | #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) | |
2145 | #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) | |
2146 | #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) | |
cb5fcbd5 | 2147 | #define CB_COLOR0_ATTRIB 0x28c74 |
f3a71df0 AD |
2148 | # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) |
2149 | # define ADDR_SURF_TILE_SPLIT_64B 0 | |
2150 | # define ADDR_SURF_TILE_SPLIT_128B 1 | |
2151 | # define ADDR_SURF_TILE_SPLIT_256B 2 | |
2152 | # define ADDR_SURF_TILE_SPLIT_512B 3 | |
2153 | # define ADDR_SURF_TILE_SPLIT_1KB 4 | |
2154 | # define ADDR_SURF_TILE_SPLIT_2KB 5 | |
2155 | # define ADDR_SURF_TILE_SPLIT_4KB 6 | |
2156 | # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) | |
2157 | # define ADDR_SURF_2_BANK 0 | |
2158 | # define ADDR_SURF_4_BANK 1 | |
2159 | # define ADDR_SURF_8_BANK 2 | |
2160 | # define ADDR_SURF_16_BANK 3 | |
2161 | # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) | |
2162 | # define ADDR_SURF_BANK_WIDTH_1 0 | |
2163 | # define ADDR_SURF_BANK_WIDTH_2 1 | |
2164 | # define ADDR_SURF_BANK_WIDTH_4 2 | |
2165 | # define ADDR_SURF_BANK_WIDTH_8 3 | |
2166 | # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) | |
2167 | # define ADDR_SURF_BANK_HEIGHT_1 0 | |
2168 | # define ADDR_SURF_BANK_HEIGHT_2 1 | |
2169 | # define ADDR_SURF_BANK_HEIGHT_4 2 | |
2170 | # define ADDR_SURF_BANK_HEIGHT_8 3 | |
285484e2 | 2171 | # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) |
cb5fcbd5 AD |
2172 | #define CB_COLOR0_DIM 0x28c78 |
2173 | /* only CB0-7 blocks have these regs */ | |
2174 | #define CB_COLOR0_CMASK 0x28c7c | |
2175 | #define CB_COLOR0_CMASK_SLICE 0x28c80 | |
2176 | #define CB_COLOR0_FMASK 0x28c84 | |
2177 | #define CB_COLOR0_FMASK_SLICE 0x28c88 | |
2178 | #define CB_COLOR0_CLEAR_WORD0 0x28c8c | |
2179 | #define CB_COLOR0_CLEAR_WORD1 0x28c90 | |
2180 | #define CB_COLOR0_CLEAR_WORD2 0x28c94 | |
2181 | #define CB_COLOR0_CLEAR_WORD3 0x28c98 | |
2182 | ||
2183 | #define CB_COLOR1_BASE 0x28c9c | |
2184 | #define CB_COLOR2_BASE 0x28cd8 | |
2185 | #define CB_COLOR3_BASE 0x28d14 | |
2186 | #define CB_COLOR4_BASE 0x28d50 | |
2187 | #define CB_COLOR5_BASE 0x28d8c | |
2188 | #define CB_COLOR6_BASE 0x28dc8 | |
2189 | #define CB_COLOR7_BASE 0x28e04 | |
2190 | #define CB_COLOR8_BASE 0x28e40 | |
2191 | #define CB_COLOR9_BASE 0x28e5c | |
2192 | #define CB_COLOR10_BASE 0x28e78 | |
2193 | #define CB_COLOR11_BASE 0x28e94 | |
2194 | ||
2195 | #define CB_COLOR1_PITCH 0x28ca0 | |
2196 | #define CB_COLOR2_PITCH 0x28cdc | |
2197 | #define CB_COLOR3_PITCH 0x28d18 | |
2198 | #define CB_COLOR4_PITCH 0x28d54 | |
2199 | #define CB_COLOR5_PITCH 0x28d90 | |
2200 | #define CB_COLOR6_PITCH 0x28dcc | |
2201 | #define CB_COLOR7_PITCH 0x28e08 | |
2202 | #define CB_COLOR8_PITCH 0x28e44 | |
2203 | #define CB_COLOR9_PITCH 0x28e60 | |
2204 | #define CB_COLOR10_PITCH 0x28e7c | |
2205 | #define CB_COLOR11_PITCH 0x28e98 | |
2206 | ||
2207 | #define CB_COLOR1_SLICE 0x28ca4 | |
2208 | #define CB_COLOR2_SLICE 0x28ce0 | |
2209 | #define CB_COLOR3_SLICE 0x28d1c | |
2210 | #define CB_COLOR4_SLICE 0x28d58 | |
2211 | #define CB_COLOR5_SLICE 0x28d94 | |
2212 | #define CB_COLOR6_SLICE 0x28dd0 | |
2213 | #define CB_COLOR7_SLICE 0x28e0c | |
2214 | #define CB_COLOR8_SLICE 0x28e48 | |
2215 | #define CB_COLOR9_SLICE 0x28e64 | |
2216 | #define CB_COLOR10_SLICE 0x28e80 | |
2217 | #define CB_COLOR11_SLICE 0x28e9c | |
2218 | ||
2219 | #define CB_COLOR1_VIEW 0x28ca8 | |
2220 | #define CB_COLOR2_VIEW 0x28ce4 | |
2221 | #define CB_COLOR3_VIEW 0x28d20 | |
2222 | #define CB_COLOR4_VIEW 0x28d5c | |
2223 | #define CB_COLOR5_VIEW 0x28d98 | |
2224 | #define CB_COLOR6_VIEW 0x28dd4 | |
2225 | #define CB_COLOR7_VIEW 0x28e10 | |
2226 | #define CB_COLOR8_VIEW 0x28e4c | |
2227 | #define CB_COLOR9_VIEW 0x28e68 | |
2228 | #define CB_COLOR10_VIEW 0x28e84 | |
2229 | #define CB_COLOR11_VIEW 0x28ea0 | |
2230 | ||
2231 | #define CB_COLOR1_INFO 0x28cac | |
2232 | #define CB_COLOR2_INFO 0x28ce8 | |
2233 | #define CB_COLOR3_INFO 0x28d24 | |
2234 | #define CB_COLOR4_INFO 0x28d60 | |
2235 | #define CB_COLOR5_INFO 0x28d9c | |
2236 | #define CB_COLOR6_INFO 0x28dd8 | |
2237 | #define CB_COLOR7_INFO 0x28e14 | |
2238 | #define CB_COLOR8_INFO 0x28e50 | |
2239 | #define CB_COLOR9_INFO 0x28e6c | |
2240 | #define CB_COLOR10_INFO 0x28e88 | |
2241 | #define CB_COLOR11_INFO 0x28ea4 | |
2242 | ||
2243 | #define CB_COLOR1_ATTRIB 0x28cb0 | |
2244 | #define CB_COLOR2_ATTRIB 0x28cec | |
2245 | #define CB_COLOR3_ATTRIB 0x28d28 | |
2246 | #define CB_COLOR4_ATTRIB 0x28d64 | |
2247 | #define CB_COLOR5_ATTRIB 0x28da0 | |
2248 | #define CB_COLOR6_ATTRIB 0x28ddc | |
2249 | #define CB_COLOR7_ATTRIB 0x28e18 | |
2250 | #define CB_COLOR8_ATTRIB 0x28e54 | |
2251 | #define CB_COLOR9_ATTRIB 0x28e70 | |
2252 | #define CB_COLOR10_ATTRIB 0x28e8c | |
2253 | #define CB_COLOR11_ATTRIB 0x28ea8 | |
2254 | ||
2255 | #define CB_COLOR1_DIM 0x28cb4 | |
2256 | #define CB_COLOR2_DIM 0x28cf0 | |
2257 | #define CB_COLOR3_DIM 0x28d2c | |
2258 | #define CB_COLOR4_DIM 0x28d68 | |
2259 | #define CB_COLOR5_DIM 0x28da4 | |
2260 | #define CB_COLOR6_DIM 0x28de0 | |
2261 | #define CB_COLOR7_DIM 0x28e1c | |
2262 | #define CB_COLOR8_DIM 0x28e58 | |
2263 | #define CB_COLOR9_DIM 0x28e74 | |
2264 | #define CB_COLOR10_DIM 0x28e90 | |
2265 | #define CB_COLOR11_DIM 0x28eac | |
2266 | ||
2267 | #define CB_COLOR1_CMASK 0x28cb8 | |
2268 | #define CB_COLOR2_CMASK 0x28cf4 | |
2269 | #define CB_COLOR3_CMASK 0x28d30 | |
2270 | #define CB_COLOR4_CMASK 0x28d6c | |
2271 | #define CB_COLOR5_CMASK 0x28da8 | |
2272 | #define CB_COLOR6_CMASK 0x28de4 | |
2273 | #define CB_COLOR7_CMASK 0x28e20 | |
2274 | ||
2275 | #define CB_COLOR1_CMASK_SLICE 0x28cbc | |
2276 | #define CB_COLOR2_CMASK_SLICE 0x28cf8 | |
2277 | #define CB_COLOR3_CMASK_SLICE 0x28d34 | |
2278 | #define CB_COLOR4_CMASK_SLICE 0x28d70 | |
2279 | #define CB_COLOR5_CMASK_SLICE 0x28dac | |
2280 | #define CB_COLOR6_CMASK_SLICE 0x28de8 | |
2281 | #define CB_COLOR7_CMASK_SLICE 0x28e24 | |
2282 | ||
2283 | #define CB_COLOR1_FMASK 0x28cc0 | |
2284 | #define CB_COLOR2_FMASK 0x28cfc | |
2285 | #define CB_COLOR3_FMASK 0x28d38 | |
2286 | #define CB_COLOR4_FMASK 0x28d74 | |
2287 | #define CB_COLOR5_FMASK 0x28db0 | |
2288 | #define CB_COLOR6_FMASK 0x28dec | |
2289 | #define CB_COLOR7_FMASK 0x28e28 | |
2290 | ||
2291 | #define CB_COLOR1_FMASK_SLICE 0x28cc4 | |
2292 | #define CB_COLOR2_FMASK_SLICE 0x28d00 | |
2293 | #define CB_COLOR3_FMASK_SLICE 0x28d3c | |
2294 | #define CB_COLOR4_FMASK_SLICE 0x28d78 | |
2295 | #define CB_COLOR5_FMASK_SLICE 0x28db4 | |
2296 | #define CB_COLOR6_FMASK_SLICE 0x28df0 | |
2297 | #define CB_COLOR7_FMASK_SLICE 0x28e2c | |
2298 | ||
2299 | #define CB_COLOR1_CLEAR_WORD0 0x28cc8 | |
2300 | #define CB_COLOR2_CLEAR_WORD0 0x28d04 | |
2301 | #define CB_COLOR3_CLEAR_WORD0 0x28d40 | |
2302 | #define CB_COLOR4_CLEAR_WORD0 0x28d7c | |
2303 | #define CB_COLOR5_CLEAR_WORD0 0x28db8 | |
2304 | #define CB_COLOR6_CLEAR_WORD0 0x28df4 | |
2305 | #define CB_COLOR7_CLEAR_WORD0 0x28e30 | |
2306 | ||
2307 | #define CB_COLOR1_CLEAR_WORD1 0x28ccc | |
2308 | #define CB_COLOR2_CLEAR_WORD1 0x28d08 | |
2309 | #define CB_COLOR3_CLEAR_WORD1 0x28d44 | |
2310 | #define CB_COLOR4_CLEAR_WORD1 0x28d80 | |
2311 | #define CB_COLOR5_CLEAR_WORD1 0x28dbc | |
2312 | #define CB_COLOR6_CLEAR_WORD1 0x28df8 | |
2313 | #define CB_COLOR7_CLEAR_WORD1 0x28e34 | |
2314 | ||
2315 | #define CB_COLOR1_CLEAR_WORD2 0x28cd0 | |
2316 | #define CB_COLOR2_CLEAR_WORD2 0x28d0c | |
2317 | #define CB_COLOR3_CLEAR_WORD2 0x28d48 | |
2318 | #define CB_COLOR4_CLEAR_WORD2 0x28d84 | |
2319 | #define CB_COLOR5_CLEAR_WORD2 0x28dc0 | |
2320 | #define CB_COLOR6_CLEAR_WORD2 0x28dfc | |
2321 | #define CB_COLOR7_CLEAR_WORD2 0x28e38 | |
2322 | ||
2323 | #define CB_COLOR1_CLEAR_WORD3 0x28cd4 | |
2324 | #define CB_COLOR2_CLEAR_WORD3 0x28d10 | |
2325 | #define CB_COLOR3_CLEAR_WORD3 0x28d4c | |
2326 | #define CB_COLOR4_CLEAR_WORD3 0x28d88 | |
2327 | #define CB_COLOR5_CLEAR_WORD3 0x28dc4 | |
2328 | #define CB_COLOR6_CLEAR_WORD3 0x28e00 | |
2329 | #define CB_COLOR7_CLEAR_WORD3 0x28e3c | |
2330 | ||
2331 | #define SQ_TEX_RESOURCE_WORD0_0 0x30000 | |
6018faf5 IH |
2332 | # define TEX_DIM(x) ((x) << 0) |
2333 | # define SQ_TEX_DIM_1D 0 | |
2334 | # define SQ_TEX_DIM_2D 1 | |
2335 | # define SQ_TEX_DIM_3D 2 | |
2336 | # define SQ_TEX_DIM_CUBEMAP 3 | |
2337 | # define SQ_TEX_DIM_1D_ARRAY 4 | |
2338 | # define SQ_TEX_DIM_2D_ARRAY 5 | |
2339 | # define SQ_TEX_DIM_2D_MSAA 6 | |
2340 | # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 | |
cb5fcbd5 AD |
2341 | #define SQ_TEX_RESOURCE_WORD1_0 0x30004 |
2342 | # define TEX_ARRAY_MODE(x) ((x) << 28) | |
2343 | #define SQ_TEX_RESOURCE_WORD2_0 0x30008 | |
2344 | #define SQ_TEX_RESOURCE_WORD3_0 0x3000C | |
2345 | #define SQ_TEX_RESOURCE_WORD4_0 0x30010 | |
6018faf5 IH |
2346 | # define TEX_DST_SEL_X(x) ((x) << 16) |
2347 | # define TEX_DST_SEL_Y(x) ((x) << 19) | |
2348 | # define TEX_DST_SEL_Z(x) ((x) << 22) | |
2349 | # define TEX_DST_SEL_W(x) ((x) << 25) | |
2350 | # define SQ_SEL_X 0 | |
2351 | # define SQ_SEL_Y 1 | |
2352 | # define SQ_SEL_Z 2 | |
2353 | # define SQ_SEL_W 3 | |
2354 | # define SQ_SEL_0 4 | |
2355 | # define SQ_SEL_1 5 | |
cb5fcbd5 AD |
2356 | #define SQ_TEX_RESOURCE_WORD5_0 0x30014 |
2357 | #define SQ_TEX_RESOURCE_WORD6_0 0x30018 | |
f3a71df0 | 2358 | # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) |
cb5fcbd5 | 2359 | #define SQ_TEX_RESOURCE_WORD7_0 0x3001c |
285484e2 | 2360 | # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) |
f3a71df0 AD |
2361 | # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) |
2362 | # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) | |
2363 | # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) | |
285484e2 JG |
2364 | #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 |
2365 | #define S_030000_DIM(x) (((x) & 0x7) << 0) | |
2366 | #define G_030000_DIM(x) (((x) >> 0) & 0x7) | |
2367 | #define C_030000_DIM 0xFFFFFFF8 | |
2368 | #define V_030000_SQ_TEX_DIM_1D 0x00000000 | |
2369 | #define V_030000_SQ_TEX_DIM_2D 0x00000001 | |
2370 | #define V_030000_SQ_TEX_DIM_3D 0x00000002 | |
2371 | #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 | |
2372 | #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 | |
2373 | #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 | |
2374 | #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 | |
2375 | #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 | |
2376 | #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) | |
2377 | #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) | |
2378 | #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF | |
2379 | #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) | |
2380 | #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) | |
2381 | #define C_030000_PITCH 0xFFFC003F | |
2382 | #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) | |
2383 | #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) | |
2384 | #define C_030000_TEX_WIDTH 0x0003FFFF | |
2385 | #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 | |
2386 | #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) | |
2387 | #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) | |
2388 | #define C_030004_TEX_HEIGHT 0xFFFFC000 | |
2389 | #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) | |
2390 | #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) | |
2391 | #define C_030004_TEX_DEPTH 0xF8003FFF | |
2392 | #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) | |
2393 | #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) | |
2394 | #define C_030004_ARRAY_MODE 0x0FFFFFFF | |
2395 | #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 | |
2396 | #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | |
2397 | #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | |
2398 | #define C_030008_BASE_ADDRESS 0x00000000 | |
2399 | #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C | |
2400 | #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) | |
2401 | #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) | |
2402 | #define C_03000C_MIP_ADDRESS 0x00000000 | |
2403 | #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 | |
2404 | #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) | |
2405 | #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) | |
2406 | #define C_030010_FORMAT_COMP_X 0xFFFFFFFC | |
2407 | #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 | |
2408 | #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 | |
2409 | #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 | |
2410 | #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) | |
2411 | #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) | |
2412 | #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 | |
2413 | #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) | |
2414 | #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) | |
2415 | #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF | |
2416 | #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) | |
2417 | #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) | |
2418 | #define C_030010_FORMAT_COMP_W 0xFFFFFF3F | |
2419 | #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) | |
2420 | #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) | |
2421 | #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF | |
2422 | #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 | |
2423 | #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 | |
2424 | #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 | |
2425 | #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) | |
2426 | #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) | |
2427 | #define C_030010_SRF_MODE_ALL 0xFFFFFBFF | |
2428 | #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 | |
2429 | #define V_030010_SRF_MODE_NO_ZERO 0x00000001 | |
2430 | #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) | |
2431 | #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) | |
2432 | #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF | |
2433 | #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) | |
2434 | #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) | |
2435 | #define C_030010_ENDIAN_SWAP 0xFFFFCFFF | |
2436 | #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) | |
2437 | #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) | |
2438 | #define C_030010_DST_SEL_X 0xFFF8FFFF | |
2439 | #define V_030010_SQ_SEL_X 0x00000000 | |
2440 | #define V_030010_SQ_SEL_Y 0x00000001 | |
2441 | #define V_030010_SQ_SEL_Z 0x00000002 | |
2442 | #define V_030010_SQ_SEL_W 0x00000003 | |
2443 | #define V_030010_SQ_SEL_0 0x00000004 | |
2444 | #define V_030010_SQ_SEL_1 0x00000005 | |
2445 | #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) | |
2446 | #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) | |
2447 | #define C_030010_DST_SEL_Y 0xFFC7FFFF | |
2448 | #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) | |
2449 | #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) | |
2450 | #define C_030010_DST_SEL_Z 0xFE3FFFFF | |
2451 | #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) | |
2452 | #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) | |
2453 | #define C_030010_DST_SEL_W 0xF1FFFFFF | |
2454 | #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) | |
2455 | #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) | |
2456 | #define C_030010_BASE_LEVEL 0x0FFFFFFF | |
2457 | #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 | |
2458 | #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) | |
2459 | #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) | |
2460 | #define C_030014_LAST_LEVEL 0xFFFFFFF0 | |
2461 | #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) | |
2462 | #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) | |
2463 | #define C_030014_BASE_ARRAY 0xFFFE000F | |
2464 | #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) | |
2465 | #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) | |
2466 | #define C_030014_LAST_ARRAY 0xC001FFFF | |
2467 | #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 | |
2468 | #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) | |
2469 | #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) | |
2470 | #define C_030018_MAX_ANISO 0xFFFFFFF8 | |
2471 | #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) | |
2472 | #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) | |
2473 | #define C_030018_PERF_MODULATION 0xFFFFFFC7 | |
2474 | #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) | |
2475 | #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) | |
2476 | #define C_030018_INTERLACED 0xFFFFFFBF | |
2477 | #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) | |
2478 | #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) | |
2479 | #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C | |
2480 | #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) | |
2481 | #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) | |
2482 | #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) | |
2483 | #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) | |
2484 | #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) | |
2485 | #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) | |
2486 | #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) | |
2487 | #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) | |
2488 | #define S_03001C_TYPE(x) (((x) & 0x3) << 30) | |
2489 | #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) | |
2490 | #define C_03001C_TYPE 0x3FFFFFFF | |
2491 | #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 | |
2492 | #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 | |
2493 | #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 | |
2494 | #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 | |
2495 | #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) | |
2496 | #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) | |
2497 | #define C_03001C_DATA_FORMAT 0xFFFFFFC0 | |
cb5fcbd5 | 2498 | |
6018faf5 IH |
2499 | #define SQ_VTX_CONSTANT_WORD0_0 0x30000 |
2500 | #define SQ_VTX_CONSTANT_WORD1_0 0x30004 | |
2501 | #define SQ_VTX_CONSTANT_WORD2_0 0x30008 | |
2502 | # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) | |
2503 | # define SQ_VTXC_STRIDE(x) ((x) << 8) | |
2504 | # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) | |
2505 | # define SQ_ENDIAN_NONE 0 | |
2506 | # define SQ_ENDIAN_8IN16 1 | |
2507 | # define SQ_ENDIAN_8IN32 2 | |
2508 | #define SQ_VTX_CONSTANT_WORD3_0 0x3000C | |
2509 | # define SQ_VTCX_SEL_X(x) ((x) << 3) | |
2510 | # define SQ_VTCX_SEL_Y(x) ((x) << 6) | |
2511 | # define SQ_VTCX_SEL_Z(x) ((x) << 9) | |
2512 | # define SQ_VTCX_SEL_W(x) ((x) << 12) | |
2513 | #define SQ_VTX_CONSTANT_WORD4_0 0x30010 | |
2514 | #define SQ_VTX_CONSTANT_WORD5_0 0x30014 | |
2515 | #define SQ_VTX_CONSTANT_WORD6_0 0x30018 | |
2516 | #define SQ_VTX_CONSTANT_WORD7_0 0x3001c | |
2517 | ||
721604a1 JG |
2518 | #define TD_PS_BORDER_COLOR_INDEX 0xA400 |
2519 | #define TD_PS_BORDER_COLOR_RED 0xA404 | |
2520 | #define TD_PS_BORDER_COLOR_GREEN 0xA408 | |
2521 | #define TD_PS_BORDER_COLOR_BLUE 0xA40C | |
2522 | #define TD_PS_BORDER_COLOR_ALPHA 0xA410 | |
2523 | #define TD_VS_BORDER_COLOR_INDEX 0xA414 | |
2524 | #define TD_VS_BORDER_COLOR_RED 0xA418 | |
2525 | #define TD_VS_BORDER_COLOR_GREEN 0xA41C | |
2526 | #define TD_VS_BORDER_COLOR_BLUE 0xA420 | |
2527 | #define TD_VS_BORDER_COLOR_ALPHA 0xA424 | |
2528 | #define TD_GS_BORDER_COLOR_INDEX 0xA428 | |
2529 | #define TD_GS_BORDER_COLOR_RED 0xA42C | |
2530 | #define TD_GS_BORDER_COLOR_GREEN 0xA430 | |
2531 | #define TD_GS_BORDER_COLOR_BLUE 0xA434 | |
2532 | #define TD_GS_BORDER_COLOR_ALPHA 0xA438 | |
2533 | #define TD_HS_BORDER_COLOR_INDEX 0xA43C | |
2534 | #define TD_HS_BORDER_COLOR_RED 0xA440 | |
2535 | #define TD_HS_BORDER_COLOR_GREEN 0xA444 | |
2536 | #define TD_HS_BORDER_COLOR_BLUE 0xA448 | |
2537 | #define TD_HS_BORDER_COLOR_ALPHA 0xA44C | |
2538 | #define TD_LS_BORDER_COLOR_INDEX 0xA450 | |
2539 | #define TD_LS_BORDER_COLOR_RED 0xA454 | |
2540 | #define TD_LS_BORDER_COLOR_GREEN 0xA458 | |
2541 | #define TD_LS_BORDER_COLOR_BLUE 0xA45C | |
2542 | #define TD_LS_BORDER_COLOR_ALPHA 0xA460 | |
2543 | #define TD_CS_BORDER_COLOR_INDEX 0xA464 | |
2544 | #define TD_CS_BORDER_COLOR_RED 0xA468 | |
2545 | #define TD_CS_BORDER_COLOR_GREEN 0xA46C | |
2546 | #define TD_CS_BORDER_COLOR_BLUE 0xA470 | |
2547 | #define TD_CS_BORDER_COLOR_ALPHA 0xA474 | |
2548 | ||
c175ca9a | 2549 | /* cayman 3D regs */ |
721604a1 JG |
2550 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 |
2551 | #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 | |
c175ca9a AD |
2552 | #define CAYMAN_DB_EQAA 0x28804 |
2553 | #define CAYMAN_DB_DEPTH_INFO 0x2803C | |
2554 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 | |
2555 | #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 | |
2556 | #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 | |
033b5650 | 2557 | #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 |
c175ca9a AD |
2558 | /* cayman packet3 addition */ |
2559 | #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 | |
cb5fcbd5 | 2560 | |
eaaa6983 | 2561 | /* DMA regs common on r6xx/r7xx/evergreen/ni */ |
64c56e8c JG |
2562 | #define DMA_RB_CNTL 0xd000 |
2563 | # define DMA_RB_ENABLE (1 << 0) | |
2564 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ | |
2565 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | |
2566 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) | |
2567 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | |
2568 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | |
eaaa6983 | 2569 | #define DMA_STATUS_REG 0xd034 |
0ecebb9e | 2570 | # define DMA_IDLE (1 << 0) |
eaaa6983 | 2571 | |
0fcdb61e | 2572 | #endif |