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e55d3e6c RM |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | * Rafał Miłecki | |
26 | */ | |
e3b2e034 | 27 | #include <linux/hdmi.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
e55d3e6c RM |
30 | #include "radeon.h" |
31 | #include "radeon_asic.h" | |
32 | #include "evergreend.h" | |
33 | #include "atom.h" | |
34 | ||
35 | /* | |
36 | * update the N and CTS parameters for a given pixel clock rate | |
37 | */ | |
38 | static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
39 | { | |
40 | struct drm_device *dev = encoder->dev; | |
41 | struct radeon_device *rdev = dev->dev_private; | |
42 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); | |
cfcbd6d3 RM |
43 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
44 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
45 | uint32_t offset = dig->afmt->offset; | |
e55d3e6c RM |
46 | |
47 | WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); | |
48 | WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); | |
49 | ||
50 | WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); | |
51 | WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); | |
52 | ||
53 | WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); | |
54 | WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); | |
55 | } | |
56 | ||
46892caa RM |
57 | static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder) |
58 | { | |
59 | struct radeon_device *rdev = encoder->dev->dev_private; | |
60 | struct drm_connector *connector; | |
61 | struct radeon_connector *radeon_connector = NULL; | |
62 | struct cea_sad *sads; | |
63 | int i, sad_count; | |
64 | ||
65 | static const u16 eld_reg_to_type[][2] = { | |
66 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, | |
67 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, | |
68 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, | |
69 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, | |
70 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, | |
71 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, | |
72 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, | |
73 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, | |
74 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, | |
75 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, | |
76 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, | |
77 | { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, | |
78 | }; | |
79 | ||
80 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | |
81 | if (connector->encoder == encoder) | |
82 | radeon_connector = to_radeon_connector(connector); | |
83 | } | |
84 | ||
85 | if (!radeon_connector) { | |
86 | DRM_ERROR("Couldn't find encoder's connector\n"); | |
87 | return; | |
88 | } | |
89 | ||
90 | sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); | |
91 | if (sad_count < 0) { | |
92 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); | |
93 | return; | |
94 | } | |
95 | BUG_ON(!sads); | |
96 | ||
97 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { | |
98 | u32 value = 0; | |
99 | int j; | |
100 | ||
101 | for (j = 0; j < sad_count; j++) { | |
102 | struct cea_sad *sad = &sads[j]; | |
103 | ||
104 | if (sad->format == eld_reg_to_type[i][1]) { | |
105 | value = MAX_CHANNELS(sad->channels) | | |
106 | DESCRIPTOR_BYTE_2(sad->byte2) | | |
107 | SUPPORTED_FREQUENCIES(sad->freq); | |
108 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) | |
109 | value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq); | |
110 | break; | |
111 | } | |
112 | } | |
113 | WREG32(eld_reg_to_type[i][0], value); | |
114 | } | |
115 | ||
116 | kfree(sads); | |
117 | } | |
118 | ||
e55d3e6c RM |
119 | /* |
120 | * build a HDMI Video Info Frame | |
121 | */ | |
e3b2e034 TR |
122 | static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
123 | void *buffer, size_t size) | |
e55d3e6c RM |
124 | { |
125 | struct drm_device *dev = encoder->dev; | |
126 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
127 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
128 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
129 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 130 | uint8_t *frame = buffer + 3; |
e55d3e6c | 131 | |
e55d3e6c RM |
132 | /* Our header values (type, version, length) should be alright, Intel |
133 | * is using the same. Checksum function also seems to be OK, it works | |
134 | * fine for audio infoframe. However calculated value is always lower | |
135 | * by 2 in comparison to fglrx. It breaks displaying anything in case | |
136 | * of TVs that strictly check the checksum. Hack it manually here to | |
137 | * workaround this issue. */ | |
138 | frame[0x0] += 2; | |
139 | ||
140 | WREG32(AFMT_AVI_INFO0 + offset, | |
141 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); | |
142 | WREG32(AFMT_AVI_INFO1 + offset, | |
143 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); | |
144 | WREG32(AFMT_AVI_INFO2 + offset, | |
145 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); | |
146 | WREG32(AFMT_AVI_INFO3 + offset, | |
147 | frame[0xC] | (frame[0xD] << 8)); | |
148 | } | |
149 | ||
b1f6f47e AD |
150 | static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
151 | { | |
152 | struct drm_device *dev = encoder->dev; | |
153 | struct radeon_device *rdev = dev->dev_private; | |
154 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
155 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
156 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
157 | u32 base_rate = 48000; | |
158 | ||
159 | if (!dig || !dig->afmt) | |
160 | return; | |
161 | ||
162 | /* XXX: properly calculate this */ | |
163 | /* XXX two dtos; generally use dto0 for hdmi */ | |
164 | /* Express [24MHz / target pixel clock] as an exact rational | |
165 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
166 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
167 | */ | |
168 | WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff); | |
169 | WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff); | |
170 | WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); | |
171 | } | |
172 | ||
173 | ||
e55d3e6c RM |
174 | /* |
175 | * update the info frames with the data from the current display mode | |
176 | */ | |
177 | void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
178 | { | |
179 | struct drm_device *dev = encoder->dev; | |
180 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
181 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
182 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
e3b2e034 TR |
183 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
184 | struct hdmi_avi_infoframe frame; | |
cfcbd6d3 | 185 | uint32_t offset; |
e3b2e034 | 186 | ssize_t err; |
e55d3e6c | 187 | |
cfcbd6d3 RM |
188 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
189 | if (!dig->afmt->enabled) | |
e55d3e6c | 190 | return; |
cfcbd6d3 | 191 | offset = dig->afmt->offset; |
e55d3e6c | 192 | |
b1f6f47e | 193 | evergreen_audio_set_dto(encoder, mode->clock); |
e55d3e6c | 194 | |
1c3439f2 RM |
195 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
196 | HDMI_NULL_SEND); /* send null packets when required */ | |
197 | ||
e55d3e6c | 198 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
e55d3e6c | 199 | |
1c3439f2 RM |
200 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
201 | HDMI_NULL_SEND | /* send null packets when required */ | |
202 | HDMI_GC_SEND | /* send general control packets */ | |
203 | HDMI_GC_CONT); /* send general control packets every frame */ | |
204 | ||
205 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, | |
1c3439f2 RM |
206 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ |
207 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ | |
e55d3e6c | 208 | |
1c3439f2 RM |
209 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
210 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ | |
e55d3e6c | 211 | |
1c3439f2 | 212 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
1c3439f2 RM |
213 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ |
214 | ||
215 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ | |
e55d3e6c | 216 | |
91a44019 RM |
217 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
218 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ | |
219 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | |
220 | ||
221 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, | |
222 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | |
223 | ||
224 | /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ | |
225 | ||
226 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, | |
227 | HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ | |
228 | HDMI_ACR_SOURCE); /* select SW CTS value */ | |
229 | ||
230 | evergreen_hdmi_update_ACR(encoder, mode->clock); | |
231 | ||
f93e3fc3 RM |
232 | WREG32(AFMT_60958_0 + offset, |
233 | AFMT_60958_CS_CHANNEL_NUMBER_L(1)); | |
234 | ||
235 | WREG32(AFMT_60958_1 + offset, | |
236 | AFMT_60958_CS_CHANNEL_NUMBER_R(2)); | |
237 | ||
238 | WREG32(AFMT_60958_2 + offset, | |
239 | AFMT_60958_CS_CHANNEL_NUMBER_2(3) | | |
240 | AFMT_60958_CS_CHANNEL_NUMBER_3(4) | | |
241 | AFMT_60958_CS_CHANNEL_NUMBER_4(5) | | |
242 | AFMT_60958_CS_CHANNEL_NUMBER_5(6) | | |
243 | AFMT_60958_CS_CHANNEL_NUMBER_6(7) | | |
244 | AFMT_60958_CS_CHANNEL_NUMBER_7(8)); | |
245 | ||
246 | /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */ | |
247 | ||
248 | WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset, | |
249 | AFMT_AUDIO_CHANNEL_ENABLE(0xff)); | |
250 | ||
251 | /* fglrx sets 0x40 in 0x5f80 here */ | |
46892caa | 252 | evergreen_hdmi_write_sad_regs(encoder); |
f93e3fc3 | 253 | |
e3b2e034 TR |
254 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
255 | if (err < 0) { | |
256 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
257 | return; | |
258 | } | |
259 | ||
260 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
261 | if (err < 0) { | |
262 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
263 | return; | |
264 | } | |
e55d3e6c | 265 | |
e3b2e034 | 266 | evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
1c3439f2 | 267 | |
d3418eac RM |
268 | WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset, |
269 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | |
270 | HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */ | |
271 | ||
272 | WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, | |
273 | HDMI_AVI_INFO_LINE(2), /* anything other than 0 */ | |
274 | ~HDMI_AVI_INFO_LINE_MASK); | |
275 | ||
276 | WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset, | |
277 | AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */ | |
278 | ||
e55d3e6c RM |
279 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
280 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); | |
281 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); | |
282 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); | |
283 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); | |
e55d3e6c | 284 | } |
a973bea1 AD |
285 | |
286 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |
287 | { | |
288 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
289 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
290 | ||
291 | /* Silent, r600_hdmi_enable will raise WARN for us */ | |
292 | if (enable && dig->afmt->enabled) | |
293 | return; | |
294 | if (!enable && !dig->afmt->enabled) | |
295 | return; | |
296 | ||
297 | dig->afmt->enabled = enable; | |
298 | ||
299 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", | |
300 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | |
301 | } |