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Merge tag 'drm-intel-next-2012-02-16-merge-resolved' of git://people.freedesktop...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
b07759bf 42void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 43extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44 int ring, u32 cp_int_cntl);
bcc1c2a1 45
285484e2
JG		 46void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
47 unsigned *bankh, unsigned *mtaspect,
48 unsigned *tile_split)
49{
50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
54 switch (*bankw) {
55 default:
56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
60 }
61 switch (*bankh) {
62 default:
63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
67 }
68 switch (*mtaspect) {
69 default:
70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
74 }
75}
76
d054ac16
AD		 77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78{
79 u16 ctl, v;
80 int cap, err;
81
82 cap = pci_pcie_cap(rdev->pdev);
83 if (!cap)
84 return;
85
86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
87 if (err)
88 return;
89
90 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
91
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
94 */
95 if ((v == 0) || (v == 6) || (v == 7)) {
96 ctl &= ~PCI_EXP_DEVCTL_READRQ;
97 ctl |= (2 << 12);
98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
99 }
100}
101
6f34be50
AD		 102void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
103{
6f34be50
AD		 104 /* enable the pflip int */
105 radeon_irq_kms_pflip_irq_get(rdev, crtc);
106}
107
108void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
109{
110 /* disable the pflip int */
111 radeon_irq_kms_pflip_irq_put(rdev, crtc);
112}
113
114u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
115{
116 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
117 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 118 int i;
6f34be50
AD		 119
120 /* Lock the graphics update lock */
121 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
122 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
123
124 /* update the scanout addresses */
125 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
126 upper_32_bits(crtc_base));
127 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
128 (u32)crtc_base);
129
130 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
131 upper_32_bits(crtc_base));
132 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
133 (u32)crtc_base);
134
135 /* Wait for update_pending to go high. */
f6496479
AD		 136 for (i = 0; i < rdev->usec_timeout; i++) {
137 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
138 break;
139 udelay(1);
140 }
6f34be50
AD		 141 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
142
143 /* Unlock the lock, so double-buffering can take place inside vblank */
144 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
145 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
146
147 /* Return current update_pending status: */
148 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
149}
150
21a8122a 151/* get temperature in millidegrees */
20d391d7 152int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 153{
1c88d74f
AD		 154 u32 temp, toffset;
155 int actual_temp = 0;
67b3f823
AD		 156
157 if (rdev->family == CHIP_JUNIPER) {
158 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
159 TOFFSET_SHIFT;
160 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
161 TS0_ADC_DOUT_SHIFT;
162
163 if (toffset & 0x100)
164 actual_temp = temp / 2 - (0x200 - toffset);
165 else
166 actual_temp = temp / 2 + toffset;
167
168 actual_temp = actual_temp * 1000;
169
170 } else {
171 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
172 ASIC_T_SHIFT;
173
174 if (temp & 0x400)
175 actual_temp = -256;
176 else if (temp & 0x200)
177 actual_temp = 255;
178 else if (temp & 0x100) {
179 actual_temp = temp & 0x1ff;
180 actual_temp |= ~0x1ff;
181 } else
182 actual_temp = temp & 0xff;
183
184 actual_temp = (actual_temp * 1000) / 2;
185 }
21a8122a 186
67b3f823 187 return actual_temp;
21a8122a
AD		 188}
189
20d391d7 190int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 191{
192 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 193 int actual_temp = temp - 49;
e33df25f
AD		 194
195 return actual_temp * 1000;
196}
197
a4c9e2ee
AD		 198void sumo_pm_init_profile(struct radeon_device *rdev)
199{
200 int idx;
201
202 /* default */
203 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
204 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
205 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
206 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
207
208 /* low,mid sh/mh */
209 if (rdev->flags & RADEON_IS_MOBILITY)
210 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
211 else
212 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
213
214 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
215 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
216 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
217 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
218
219 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
220 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
221 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
222 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
223
224 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
225 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
226 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
227 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
228
229 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
230 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
231 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
232 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
233
234 /* high sh/mh */
235 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
236 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
237 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
238 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
239 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
240 rdev->pm.power_state[idx].num_clock_modes - 1;
241
242 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
243 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
244 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
245 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
246 rdev->pm.power_state[idx].num_clock_modes - 1;
247}
248
49e02b73
AD		 249void evergreen_pm_misc(struct radeon_device *rdev)
250{
a081a9d6
RM		 251 int req_ps_idx = rdev->pm.requested_power_state_index;
252 int req_cm_idx = rdev->pm.requested_clock_mode_index;
253 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
254 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 255
2feea49a 256 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 257 /* 0xff01 is a flag rather then an actual voltage */
258 if (voltage->voltage == 0xff01)
259 return;
2feea49a 260 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 261 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 262 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 263 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
264 }
a377e187
AD		 265 /* 0xff01 is a flag rather then an actual voltage */
266 if (voltage->vddci == 0xff01)
267 return;
2feea49a
AD		 268 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
269 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
270 rdev->pm.current_vddci = voltage->vddci;
271 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 272 }
273 }
49e02b73
AD		 274}
275
276void evergreen_pm_prepare(struct radeon_device *rdev)
277{
278 struct drm_device *ddev = rdev->ddev;
279 struct drm_crtc *crtc;
280 struct radeon_crtc *radeon_crtc;
281 u32 tmp;
282
283 /* disable any active CRTCs */
284 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
285 radeon_crtc = to_radeon_crtc(crtc);
286 if (radeon_crtc->enabled) {
287 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
288 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
289 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
290 }
291 }
292}
293
294void evergreen_pm_finish(struct radeon_device *rdev)
295{
296 struct drm_device *ddev = rdev->ddev;
297 struct drm_crtc *crtc;
298 struct radeon_crtc *radeon_crtc;
299 u32 tmp;
300
301 /* enable any active CRTCs */
302 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
303 radeon_crtc = to_radeon_crtc(crtc);
304 if (radeon_crtc->enabled) {
305 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
306 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
307 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
308 }
309 }
310}
311
bcc1c2a1
AD		 312bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
313{
314 bool connected = false;
0ca2ab52
AD		 315
316 switch (hpd) {
317 case RADEON_HPD_1:
318 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
319 connected = true;
320 break;
321 case RADEON_HPD_2:
322 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
323 connected = true;
324 break;
325 case RADEON_HPD_3:
326 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
327 connected = true;
328 break;
329 case RADEON_HPD_4:
330 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
331 connected = true;
332 break;
333 case RADEON_HPD_5:
334 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
335 connected = true;
336 break;
337 case RADEON_HPD_6:
338 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
339 connected = true;
340 break;
341 default:
342 break;
343 }
344
bcc1c2a1
AD		 345 return connected;
346}
347
348void evergreen_hpd_set_polarity(struct radeon_device *rdev,
349 enum radeon_hpd_id hpd)
350{
0ca2ab52
AD		 351 u32 tmp;
352 bool connected = evergreen_hpd_sense(rdev, hpd);
353
354 switch (hpd) {
355 case RADEON_HPD_1:
356 tmp = RREG32(DC_HPD1_INT_CONTROL);
357 if (connected)
358 tmp &= ~DC_HPDx_INT_POLARITY;
359 else
360 tmp |= DC_HPDx_INT_POLARITY;
361 WREG32(DC_HPD1_INT_CONTROL, tmp);
362 break;
363 case RADEON_HPD_2:
364 tmp = RREG32(DC_HPD2_INT_CONTROL);
365 if (connected)
366 tmp &= ~DC_HPDx_INT_POLARITY;
367 else
368 tmp |= DC_HPDx_INT_POLARITY;
369 WREG32(DC_HPD2_INT_CONTROL, tmp);
370 break;
371 case RADEON_HPD_3:
372 tmp = RREG32(DC_HPD3_INT_CONTROL);
373 if (connected)
374 tmp &= ~DC_HPDx_INT_POLARITY;
375 else
376 tmp |= DC_HPDx_INT_POLARITY;
377 WREG32(DC_HPD3_INT_CONTROL, tmp);
378 break;
379 case RADEON_HPD_4:
380 tmp = RREG32(DC_HPD4_INT_CONTROL);
381 if (connected)
382 tmp &= ~DC_HPDx_INT_POLARITY;
383 else
384 tmp |= DC_HPDx_INT_POLARITY;
385 WREG32(DC_HPD4_INT_CONTROL, tmp);
386 break;
387 case RADEON_HPD_5:
388 tmp = RREG32(DC_HPD5_INT_CONTROL);
389 if (connected)
390 tmp &= ~DC_HPDx_INT_POLARITY;
391 else
392 tmp |= DC_HPDx_INT_POLARITY;
393 WREG32(DC_HPD5_INT_CONTROL, tmp);
394 break;
395 case RADEON_HPD_6:
396 tmp = RREG32(DC_HPD6_INT_CONTROL);
397 if (connected)
398 tmp &= ~DC_HPDx_INT_POLARITY;
399 else
400 tmp |= DC_HPDx_INT_POLARITY;
401 WREG32(DC_HPD6_INT_CONTROL, tmp);
402 break;
403 default:
404 break;
405 }
bcc1c2a1
AD		 406}
407
408void evergreen_hpd_init(struct radeon_device *rdev)
409{
0ca2ab52
AD		 410 struct drm_device *dev = rdev->ddev;
411 struct drm_connector *connector;
412 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
413 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 414
0ca2ab52
AD		 415 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
416 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
417 switch (radeon_connector->hpd.hpd) {
418 case RADEON_HPD_1:
419 WREG32(DC_HPD1_CONTROL, tmp);
420 rdev->irq.hpd[0] = true;
421 break;
422 case RADEON_HPD_2:
423 WREG32(DC_HPD2_CONTROL, tmp);
424 rdev->irq.hpd[1] = true;
425 break;
426 case RADEON_HPD_3:
427 WREG32(DC_HPD3_CONTROL, tmp);
428 rdev->irq.hpd[2] = true;
429 break;
430 case RADEON_HPD_4:
431 WREG32(DC_HPD4_CONTROL, tmp);
432 rdev->irq.hpd[3] = true;
433 break;
434 case RADEON_HPD_5:
435 WREG32(DC_HPD5_CONTROL, tmp);
436 rdev->irq.hpd[4] = true;
437 break;
438 case RADEON_HPD_6:
439 WREG32(DC_HPD6_CONTROL, tmp);
440 rdev->irq.hpd[5] = true;
441 break;
442 default:
443 break;
444 }
64912e99 445 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
0ca2ab52
AD		 446 }
447 if (rdev->irq.installed)
448 evergreen_irq_set(rdev);
bcc1c2a1
AD		 449}
450
0ca2ab52 451void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 452{
0ca2ab52
AD		 453 struct drm_device *dev = rdev->ddev;
454 struct drm_connector *connector;
455
456 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
457 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
458 switch (radeon_connector->hpd.hpd) {
459 case RADEON_HPD_1:
460 WREG32(DC_HPD1_CONTROL, 0);
461 rdev->irq.hpd[0] = false;
462 break;
463 case RADEON_HPD_2:
464 WREG32(DC_HPD2_CONTROL, 0);
465 rdev->irq.hpd[1] = false;
466 break;
467 case RADEON_HPD_3:
468 WREG32(DC_HPD3_CONTROL, 0);
469 rdev->irq.hpd[2] = false;
470 break;
471 case RADEON_HPD_4:
472 WREG32(DC_HPD4_CONTROL, 0);
473 rdev->irq.hpd[3] = false;
474 break;
475 case RADEON_HPD_5:
476 WREG32(DC_HPD5_CONTROL, 0);
477 rdev->irq.hpd[4] = false;
478 break;
479 case RADEON_HPD_6:
480 WREG32(DC_HPD6_CONTROL, 0);
481 rdev->irq.hpd[5] = false;
482 break;
483 default:
484 break;
485 }
486 }
bcc1c2a1
AD		 487}
488
f9d9c362
AD		 489/* watermark setup */
490
491static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
492 struct radeon_crtc *radeon_crtc,
493 struct drm_display_mode *mode,
494 struct drm_display_mode *other_mode)
495{
12dfc843 496 u32 tmp;
f9d9c362
AD		 497 /*
498 * Line Buffer Setup
499 * There are 3 line buffers, each one shared by 2 display controllers.
500 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
501 * the display controllers. The paritioning is done via one of four
502 * preset allocations specified in bits 2:0:
503 * first display controller
504 * 0 - first half of lb (3840 * 2)
505 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 506 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 507 * 3 - first 1/4 of lb (1920 * 2)
508 * second display controller
509 * 4 - second half of lb (3840 * 2)
510 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 511 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 512 * 7 - last 1/4 of lb (1920 * 2)
513 */
12dfc843
AD		 514 /* this can get tricky if we have two large displays on a paired group
515 * of crtcs. Ideally for multiple large displays we'd assign them to
516 * non-linked crtcs for maximum line buffer allocation.
517 */
518 if (radeon_crtc->base.enabled && mode) {
519 if (other_mode)
f9d9c362 520 tmp = 0; /* 1/2 */
12dfc843
AD		 521 else
522 tmp = 2; /* whole */
523 } else
524 tmp = 0;
f9d9c362
AD		 525
526 /* second controller of the pair uses second half of the lb */
527 if (radeon_crtc->crtc_id % 2)
528 tmp += 4;
529 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
530
12dfc843
AD		 531 if (radeon_crtc->base.enabled && mode) {
532 switch (tmp) {
533 case 0:
534 case 4:
535 default:
536 if (ASIC_IS_DCE5(rdev))
537 return 4096 * 2;
538 else
539 return 3840 * 2;
540 case 1:
541 case 5:
542 if (ASIC_IS_DCE5(rdev))
543 return 6144 * 2;
544 else
545 return 5760 * 2;
546 case 2:
547 case 6:
548 if (ASIC_IS_DCE5(rdev))
549 return 8192 * 2;
550 else
551 return 7680 * 2;
552 case 3:
553 case 7:
554 if (ASIC_IS_DCE5(rdev))
555 return 2048 * 2;
556 else
557 return 1920 * 2;
558 }
f9d9c362 559 }
12dfc843
AD		 560
561 /* controller not enabled, so no lb used */
562 return 0;
f9d9c362
AD		 563}
564
565static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
566{
567 u32 tmp = RREG32(MC_SHARED_CHMAP);
568
569 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
570 case 0:
571 default:
572 return 1;
573 case 1:
574 return 2;
575 case 2:
576 return 4;
577 case 3:
578 return 8;
579 }
580}
581
582struct evergreen_wm_params {
583 u32 dram_channels; /* number of dram channels */
584 u32 yclk; /* bandwidth per dram data pin in kHz */
585 u32 sclk; /* engine clock in kHz */
586 u32 disp_clk; /* display clock in kHz */
587 u32 src_width; /* viewport width */
588 u32 active_time; /* active display time in ns */
589 u32 blank_time; /* blank time in ns */
590 bool interlaced; /* mode is interlaced */
591 fixed20_12 vsc; /* vertical scale ratio */
592 u32 num_heads; /* number of active crtcs */
593 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
594 u32 lb_size; /* line buffer allocated to pipe */
595 u32 vtaps; /* vertical scaler taps */
596};
597
598static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
599{
600 /* Calculate DRAM Bandwidth and the part allocated to display. */
601 fixed20_12 dram_efficiency; /* 0.7 */
602 fixed20_12 yclk, dram_channels, bandwidth;
603 fixed20_12 a;
604
605 a.full = dfixed_const(1000);
606 yclk.full = dfixed_const(wm->yclk);
607 yclk.full = dfixed_div(yclk, a);
608 dram_channels.full = dfixed_const(wm->dram_channels * 4);
609 a.full = dfixed_const(10);
610 dram_efficiency.full = dfixed_const(7);
611 dram_efficiency.full = dfixed_div(dram_efficiency, a);
612 bandwidth.full = dfixed_mul(dram_channels, yclk);
613 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
614
615 return dfixed_trunc(bandwidth);
616}
617
618static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
619{
620 /* Calculate DRAM Bandwidth and the part allocated to display. */
621 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
622 fixed20_12 yclk, dram_channels, bandwidth;
623 fixed20_12 a;
624
625 a.full = dfixed_const(1000);
626 yclk.full = dfixed_const(wm->yclk);
627 yclk.full = dfixed_div(yclk, a);
628 dram_channels.full = dfixed_const(wm->dram_channels * 4);
629 a.full = dfixed_const(10);
630 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
631 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
632 bandwidth.full = dfixed_mul(dram_channels, yclk);
633 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
634
635 return dfixed_trunc(bandwidth);
636}
637
638static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
639{
640 /* Calculate the display Data return Bandwidth */
641 fixed20_12 return_efficiency; /* 0.8 */
642 fixed20_12 sclk, bandwidth;
643 fixed20_12 a;
644
645 a.full = dfixed_const(1000);
646 sclk.full = dfixed_const(wm->sclk);
647 sclk.full = dfixed_div(sclk, a);
648 a.full = dfixed_const(10);
649 return_efficiency.full = dfixed_const(8);
650 return_efficiency.full = dfixed_div(return_efficiency, a);
651 a.full = dfixed_const(32);
652 bandwidth.full = dfixed_mul(a, sclk);
653 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
654
655 return dfixed_trunc(bandwidth);
656}
657
658static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
659{
660 /* Calculate the DMIF Request Bandwidth */
661 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
662 fixed20_12 disp_clk, bandwidth;
663 fixed20_12 a;
664
665 a.full = dfixed_const(1000);
666 disp_clk.full = dfixed_const(wm->disp_clk);
667 disp_clk.full = dfixed_div(disp_clk, a);
668 a.full = dfixed_const(10);
669 disp_clk_request_efficiency.full = dfixed_const(8);
670 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
671 a.full = dfixed_const(32);
672 bandwidth.full = dfixed_mul(a, disp_clk);
673 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
674
675 return dfixed_trunc(bandwidth);
676}
677
678static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
679{
680 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
681 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
682 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
683 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
684
685 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
686}
687
688static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
689{
690 /* Calculate the display mode Average Bandwidth
691 * DisplayMode should contain the source and destination dimensions,
692 * timing, etc.
693 */
694 fixed20_12 bpp;
695 fixed20_12 line_time;
696 fixed20_12 src_width;
697 fixed20_12 bandwidth;
698 fixed20_12 a;
699
700 a.full = dfixed_const(1000);
701 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
702 line_time.full = dfixed_div(line_time, a);
703 bpp.full = dfixed_const(wm->bytes_per_pixel);
704 src_width.full = dfixed_const(wm->src_width);
705 bandwidth.full = dfixed_mul(src_width, bpp);
706 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
707 bandwidth.full = dfixed_div(bandwidth, line_time);
708
709 return dfixed_trunc(bandwidth);
710}
711
712static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
713{
714 /* First calcualte the latency in ns */
715 u32 mc_latency = 2000; /* 2000 ns. */
716 u32 available_bandwidth = evergreen_available_bandwidth(wm);
717 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
718 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
719 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
720 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
721 (wm->num_heads * cursor_line_pair_return_time);
722 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
723 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
724 fixed20_12 a, b, c;
725
726 if (wm->num_heads == 0)
727 return 0;
728
729 a.full = dfixed_const(2);
730 b.full = dfixed_const(1);
731 if ((wm->vsc.full > a.full) ||
732 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
733 (wm->vtaps >= 5) ||
734 ((wm->vsc.full >= a.full) && wm->interlaced))
735 max_src_lines_per_dst_line = 4;
736 else
737 max_src_lines_per_dst_line = 2;
738
739 a.full = dfixed_const(available_bandwidth);
740 b.full = dfixed_const(wm->num_heads);
741 a.full = dfixed_div(a, b);
742
743 b.full = dfixed_const(1000);
744 c.full = dfixed_const(wm->disp_clk);
745 b.full = dfixed_div(c, b);
746 c.full = dfixed_const(wm->bytes_per_pixel);
747 b.full = dfixed_mul(b, c);
748
749 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
750
751 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
752 b.full = dfixed_const(1000);
753 c.full = dfixed_const(lb_fill_bw);
754 b.full = dfixed_div(c, b);
755 a.full = dfixed_div(a, b);
756 line_fill_time = dfixed_trunc(a);
757
758 if (line_fill_time < wm->active_time)
759 return latency;
760 else
761 return latency + (line_fill_time - wm->active_time);
762
763}
764
765static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
766{
767 if (evergreen_average_bandwidth(wm) <=
768 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
769 return true;
770 else
771 return false;
772};
773
774static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
775{
776 if (evergreen_average_bandwidth(wm) <=
777 (evergreen_available_bandwidth(wm) / wm->num_heads))
778 return true;
779 else
780 return false;
781};
782
783static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
784{
785 u32 lb_partitions = wm->lb_size / wm->src_width;
786 u32 line_time = wm->active_time + wm->blank_time;
787 u32 latency_tolerant_lines;
788 u32 latency_hiding;
789 fixed20_12 a;
790
791 a.full = dfixed_const(1);
792 if (wm->vsc.full > a.full)
793 latency_tolerant_lines = 1;
794 else {
795 if (lb_partitions <= (wm->vtaps + 1))
796 latency_tolerant_lines = 1;
797 else
798 latency_tolerant_lines = 2;
799 }
800
801 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
802
803 if (evergreen_latency_watermark(wm) <= latency_hiding)
804 return true;
805 else
806 return false;
807}
808
809static void evergreen_program_watermarks(struct radeon_device *rdev,
810 struct radeon_crtc *radeon_crtc,
811 u32 lb_size, u32 num_heads)
812{
813 struct drm_display_mode *mode = &radeon_crtc->base.mode;
814 struct evergreen_wm_params wm;
815 u32 pixel_period;
816 u32 line_time = 0;
817 u32 latency_watermark_a = 0, latency_watermark_b = 0;
818 u32 priority_a_mark = 0, priority_b_mark = 0;
819 u32 priority_a_cnt = PRIORITY_OFF;
820 u32 priority_b_cnt = PRIORITY_OFF;
821 u32 pipe_offset = radeon_crtc->crtc_id * 16;
822 u32 tmp, arb_control3;
823 fixed20_12 a, b, c;
824
825 if (radeon_crtc->base.enabled && num_heads && mode) {
826 pixel_period = 1000000 / (u32)mode->clock;
827 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
828 priority_a_cnt = 0;
829 priority_b_cnt = 0;
830
831 wm.yclk = rdev->pm.current_mclk * 10;
832 wm.sclk = rdev->pm.current_sclk * 10;
833 wm.disp_clk = mode->clock;
834 wm.src_width = mode->crtc_hdisplay;
835 wm.active_time = mode->crtc_hdisplay * pixel_period;
836 wm.blank_time = line_time - wm.active_time;
837 wm.interlaced = false;
838 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
839 wm.interlaced = true;
840 wm.vsc = radeon_crtc->vsc;
841 wm.vtaps = 1;
842 if (radeon_crtc->rmx_type != RMX_OFF)
843 wm.vtaps = 2;
844 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
845 wm.lb_size = lb_size;
846 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
847 wm.num_heads = num_heads;
848
849 /* set for high clocks */
850 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
851 /* set for low clocks */
852 /* wm.yclk = low clk; wm.sclk = low clk */
853 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
854
855 /* possibly force display priority to high */
856 /* should really do this at mode validation time... */
857 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
858 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
859 !evergreen_check_latency_hiding(&wm) ||
860 (rdev->disp_priority == 2)) {
92bdfd4a 861 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 862 priority_a_cnt |= PRIORITY_ALWAYS_ON;
863 priority_b_cnt |= PRIORITY_ALWAYS_ON;
864 }
865
866 a.full = dfixed_const(1000);
867 b.full = dfixed_const(mode->clock);
868 b.full = dfixed_div(b, a);
869 c.full = dfixed_const(latency_watermark_a);
870 c.full = dfixed_mul(c, b);
871 c.full = dfixed_mul(c, radeon_crtc->hsc);
872 c.full = dfixed_div(c, a);
873 a.full = dfixed_const(16);
874 c.full = dfixed_div(c, a);
875 priority_a_mark = dfixed_trunc(c);
876 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
877
878 a.full = dfixed_const(1000);
879 b.full = dfixed_const(mode->clock);
880 b.full = dfixed_div(b, a);
881 c.full = dfixed_const(latency_watermark_b);
882 c.full = dfixed_mul(c, b);
883 c.full = dfixed_mul(c, radeon_crtc->hsc);
884 c.full = dfixed_div(c, a);
885 a.full = dfixed_const(16);
886 c.full = dfixed_div(c, a);
887 priority_b_mark = dfixed_trunc(c);
888 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
889 }
890
891 /* select wm A */
892 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
893 tmp = arb_control3;
894 tmp &= ~LATENCY_WATERMARK_MASK(3);
895 tmp |= LATENCY_WATERMARK_MASK(1);
896 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
897 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
898 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
899 LATENCY_HIGH_WATERMARK(line_time)));
900 /* select wm B */
901 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
902 tmp &= ~LATENCY_WATERMARK_MASK(3);
903 tmp |= LATENCY_WATERMARK_MASK(2);
904 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
905 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
906 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
907 LATENCY_HIGH_WATERMARK(line_time)));
908 /* restore original selection */
909 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
910
911 /* write the priority marks */
912 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
913 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
914
915}
916
0ca2ab52 917void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 918{
f9d9c362
AD		 919 struct drm_display_mode *mode0 = NULL;
920 struct drm_display_mode *mode1 = NULL;
921 u32 num_heads = 0, lb_size;
922 int i;
923
924 radeon_update_display_priority(rdev);
925
926 for (i = 0; i < rdev->num_crtc; i++) {
927 if (rdev->mode_info.crtcs[i]->base.enabled)
928 num_heads++;
929 }
930 for (i = 0; i < rdev->num_crtc; i += 2) {
931 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
932 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
933 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
934 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
935 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
936 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
937 }
bcc1c2a1
AD		 938}
939
b9952a8a 940int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 941{
942 unsigned i;
943 u32 tmp;
944
945 for (i = 0; i < rdev->usec_timeout; i++) {
946 /* read MC_STATUS */
947 tmp = RREG32(SRBM_STATUS) & 0x1F00;
948 if (!tmp)
949 return 0;
950 udelay(1);
951 }
952 return -1;
953}
954
955/*
956 * GART
957 */
0fcdb61e
AD		 958void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
959{
960 unsigned i;
961 u32 tmp;
962
6f2f48a9
AD		 963 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
964
0fcdb61e
AD		 965 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
966 for (i = 0; i < rdev->usec_timeout; i++) {
967 /* read MC_STATUS */
968 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
969 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
970 if (tmp == 2) {
971 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
972 return;
973 }
974 if (tmp) {
975 return;
976 }
977 udelay(1);
978 }
979}
980
bcc1c2a1
AD		 981int evergreen_pcie_gart_enable(struct radeon_device *rdev)
982{
983 u32 tmp;
0fcdb61e 984 int r;
bcc1c2a1 985
c9a1be96 986 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 987 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
988 return -EINVAL;
989 }
990 r = radeon_gart_table_vram_pin(rdev);
991 if (r)
992 return r;
82568565 993 radeon_gart_restore(rdev);
bcc1c2a1
AD		 994 /* Setup L2 cache */
995 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
996 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
997 EFFECTIVE_L2_QUEUE_SIZE(7));
998 WREG32(VM_L2_CNTL2, 0);
999 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1000 /* Setup TLB control */
1001 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1002 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1003 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1004 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1005 if (rdev->flags & RADEON_IS_IGP) {
1006 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1007 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1008 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1009 } else {
1010 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1011 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1012 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1013 }
bcc1c2a1
AD		 1014 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1015 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1016 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1017 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1018 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1019 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1020 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1021 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1022 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1023 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1024 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1025 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1026
0fcdb61e 1027 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1028 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1029 (unsigned)(rdev->mc.gtt_size >> 20),
1030 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1031 rdev->gart.ready = true;
1032 return 0;
1033}
1034
1035void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1036{
1037 u32 tmp;
bcc1c2a1
AD		 1038
1039 /* Disable all tables */
0fcdb61e
AD		 1040 WREG32(VM_CONTEXT0_CNTL, 0);
1041 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1042
1043 /* Setup L2 cache */
1044 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1045 EFFECTIVE_L2_QUEUE_SIZE(7));
1046 WREG32(VM_L2_CNTL2, 0);
1047 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1048 /* Setup TLB control */
1049 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1050 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1051 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1052 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1053 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1054 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1055 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1056 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1057 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1058}
1059
1060void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1061{
1062 evergreen_pcie_gart_disable(rdev);
1063 radeon_gart_table_vram_free(rdev);
1064 radeon_gart_fini(rdev);
1065}
1066
1067
1068void evergreen_agp_enable(struct radeon_device *rdev)
1069{
1070 u32 tmp;
bcc1c2a1
AD		 1071
1072 /* Setup L2 cache */
1073 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1074 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1075 EFFECTIVE_L2_QUEUE_SIZE(7));
1076 WREG32(VM_L2_CNTL2, 0);
1077 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1078 /* Setup TLB control */
1079 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1080 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1081 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1082 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1083 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1084 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1085 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1086 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1087 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1088 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1089 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1090 WREG32(VM_CONTEXT0_CNTL, 0);
1091 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1092}
1093
b9952a8a 1094void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1095{
1096 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1097 save->vga_control[1] = RREG32(D2VGA_CONTROL);
bcc1c2a1
AD		 1098 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1099 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1100 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1101 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 1102 if (rdev->num_crtc >= 4) {
1103 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1104 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
18007401
AD		 1105 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1106 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
b7eff394
AD		 1107 }
1108 if (rdev->num_crtc >= 6) {
1109 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1110 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
18007401
AD		 1111 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1112 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1113 }
bcc1c2a1
AD		 1114
1115 /* Stop all video */
1116 WREG32(VGA_RENDER_CONTROL, 0);
1117 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1118 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1119 if (rdev->num_crtc >= 4) {
18007401
AD		 1120 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1121 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1122 }
1123 if (rdev->num_crtc >= 6) {
18007401
AD		 1124 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1126 }
bcc1c2a1
AD		 1127 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1128 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1129 if (rdev->num_crtc >= 4) {
18007401
AD		 1130 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1131 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1132 }
1133 if (rdev->num_crtc >= 6) {
18007401
AD		 1134 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1136 }
bcc1c2a1
AD		 1137 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1138 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1139 if (rdev->num_crtc >= 4) {
18007401
AD		 1140 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1141 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1142 }
1143 if (rdev->num_crtc >= 6) {
18007401
AD		 1144 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1146 }
bcc1c2a1
AD		 1147
1148 WREG32(D1VGA_CONTROL, 0);
1149 WREG32(D2VGA_CONTROL, 0);
b7eff394
AD		 1150 if (rdev->num_crtc >= 4) {
1151 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1152 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1153 }
1154 if (rdev->num_crtc >= 6) {
1155 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1156 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1157 }
bcc1c2a1
AD		 1158}
1159
b9952a8a 1160void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1161{
1162 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1163 upper_32_bits(rdev->mc.vram_start));
1164 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1165 upper_32_bits(rdev->mc.vram_start));
1166 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1167 (u32)rdev->mc.vram_start);
1168 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1169 (u32)rdev->mc.vram_start);
1170
1171 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1172 upper_32_bits(rdev->mc.vram_start));
1173 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1174 upper_32_bits(rdev->mc.vram_start));
1175 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1176 (u32)rdev->mc.vram_start);
1177 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1178 (u32)rdev->mc.vram_start);
1179
b7eff394 1180 if (rdev->num_crtc >= 4) {
18007401
AD		 1181 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1182 upper_32_bits(rdev->mc.vram_start));
1183 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1184 upper_32_bits(rdev->mc.vram_start));
1185 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1186 (u32)rdev->mc.vram_start);
1187 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1188 (u32)rdev->mc.vram_start);
1189
1190 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1191 upper_32_bits(rdev->mc.vram_start));
1192 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1193 upper_32_bits(rdev->mc.vram_start));
1194 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1195 (u32)rdev->mc.vram_start);
1196 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1197 (u32)rdev->mc.vram_start);
b7eff394
AD		 1198 }
1199 if (rdev->num_crtc >= 6) {
18007401
AD		 1200 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1201 upper_32_bits(rdev->mc.vram_start));
1202 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1203 upper_32_bits(rdev->mc.vram_start));
1204 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1205 (u32)rdev->mc.vram_start);
1206 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1207 (u32)rdev->mc.vram_start);
1208
1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1210 upper_32_bits(rdev->mc.vram_start));
1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1212 upper_32_bits(rdev->mc.vram_start));
1213 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1214 (u32)rdev->mc.vram_start);
1215 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1216 (u32)rdev->mc.vram_start);
1217 }
bcc1c2a1
AD		 1218
1219 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1220 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1221 /* Unlock host access */
1222 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1223 mdelay(1);
1224 /* Restore video state */
1225 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1226 WREG32(D2VGA_CONTROL, save->vga_control[1]);
b7eff394
AD		 1227 if (rdev->num_crtc >= 4) {
1228 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1229 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1230 }
1231 if (rdev->num_crtc >= 6) {
1232 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1233 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1234 }
bcc1c2a1
AD		 1235 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1236 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1237 if (rdev->num_crtc >= 4) {
18007401
AD		 1238 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1239 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1240 }
1241 if (rdev->num_crtc >= 6) {
18007401
AD		 1242 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1243 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1244 }
bcc1c2a1
AD		 1245 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1246 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
b7eff394 1247 if (rdev->num_crtc >= 4) {
18007401
AD		 1248 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1249 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
b7eff394
AD		 1250 }
1251 if (rdev->num_crtc >= 6) {
18007401
AD		 1252 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1253 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1254 }
bcc1c2a1
AD		 1255 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1256 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1257 if (rdev->num_crtc >= 4) {
18007401
AD		 1258 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1259 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1260 }
1261 if (rdev->num_crtc >= 6) {
18007401
AD		 1262 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1263 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1264 }
bcc1c2a1
AD		 1265 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1266}
1267
755d819e 1268void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1269{
1270 struct evergreen_mc_save save;
1271 u32 tmp;
1272 int i, j;
1273
1274 /* Initialize HDP */
1275 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1276 WREG32((0x2c14 + j), 0x00000000);
1277 WREG32((0x2c18 + j), 0x00000000);
1278 WREG32((0x2c1c + j), 0x00000000);
1279 WREG32((0x2c20 + j), 0x00000000);
1280 WREG32((0x2c24 + j), 0x00000000);
1281 }
1282 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1283
1284 evergreen_mc_stop(rdev, &save);
1285 if (evergreen_mc_wait_for_idle(rdev)) {
1286 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1287 }
1288 /* Lockout access through VGA aperture*/
1289 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1290 /* Update configuration */
1291 if (rdev->flags & RADEON_IS_AGP) {
1292 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1293 /* VRAM before AGP */
1294 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1295 rdev->mc.vram_start >> 12);
1296 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1297 rdev->mc.gtt_end >> 12);
1298 } else {
1299 /* VRAM after AGP */
1300 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1301 rdev->mc.gtt_start >> 12);
1302 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1303 rdev->mc.vram_end >> 12);
1304 }
1305 } else {
1306 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1307 rdev->mc.vram_start >> 12);
1308 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1309 rdev->mc.vram_end >> 12);
1310 }
3b9832f6 1311 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
b4183e30
AD		 1312 if (rdev->flags & RADEON_IS_IGP) {
1313 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1314 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1315 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1316 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1317 }
bcc1c2a1
AD		 1318 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1319 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1320 WREG32(MC_VM_FB_LOCATION, tmp);
1321 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1322 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1323 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1324 if (rdev->flags & RADEON_IS_AGP) {
1325 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1326 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1327 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1328 } else {
1329 WREG32(MC_VM_AGP_BASE, 0);
1330 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1331 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1332 }
1333 if (evergreen_mc_wait_for_idle(rdev)) {
1334 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1335 }
1336 evergreen_mc_resume(rdev, &save);
1337 /* we need to own VRAM, so turn off the VGA renderer here
1338 * to stop it overwriting our objects */
1339 rv515_vga_render_disable(rdev);
1340}
1341
bcc1c2a1
AD		 1342/*
1343 * CP.
1344 */
12920591
AD		 1345void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1346{
e32eb50d 1347 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
7b1f2485 1348
12920591 1349 /* set to DX10/11 mode */
e32eb50d
CK		 1350 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1351 radeon_ring_write(ring, 1);
12920591 1352 /* FIXME: implement */
e32eb50d
CK		 1353 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1354 radeon_ring_write(ring,
0f234f5f
AD		 1355#ifdef __BIG_ENDIAN
1356 (2 << 0) |
1357#endif
1358 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1359 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1360 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1361}
1362
bcc1c2a1
AD		 1363
1364static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1365{
fe251e2f
AD		 1366 const __be32 *fw_data;
1367 int i;
1368
1369 if (!rdev->me_fw || !rdev->pfp_fw)
1370 return -EINVAL;
bcc1c2a1 1371
fe251e2f 1372 r700_cp_stop(rdev);
0f234f5f
AD		 1373 WREG32(CP_RB_CNTL,
1374#ifdef __BIG_ENDIAN
1375 BUF_SWAP_32BIT |
1376#endif
1377 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1378
1379 fw_data = (const __be32 *)rdev->pfp_fw->data;
1380 WREG32(CP_PFP_UCODE_ADDR, 0);
1381 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1382 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1383 WREG32(CP_PFP_UCODE_ADDR, 0);
1384
1385 fw_data = (const __be32 *)rdev->me_fw->data;
1386 WREG32(CP_ME_RAM_WADDR, 0);
1387 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1388 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1389
1390 WREG32(CP_PFP_UCODE_ADDR, 0);
1391 WREG32(CP_ME_RAM_WADDR, 0);
1392 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1393 return 0;
1394}
1395
7e7b41d2
AD		 1396static int evergreen_cp_start(struct radeon_device *rdev)
1397{
e32eb50d 1398 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1399 int r, i;
7e7b41d2
AD		 1400 uint32_t cp_me;
1401
e32eb50d 1402 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1403 if (r) {
1404 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1405 return r;
1406 }
e32eb50d
CK		 1407 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1408 radeon_ring_write(ring, 0x1);
1409 radeon_ring_write(ring, 0x0);
1410 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1411 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1412 radeon_ring_write(ring, 0);
1413 radeon_ring_write(ring, 0);
1414 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1415
1416 cp_me = 0xff;
1417 WREG32(CP_ME_CNTL, cp_me);
1418
e32eb50d 1419 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1420 if (r) {
1421 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1422 return r;
1423 }
2281a378
AD		 1424
1425 /* setup clear context state */
e32eb50d
CK		 1426 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1427 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1428
1429 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1430 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1431
e32eb50d
CK		 1432 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1433 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1434
1435 /* set clear context state */
e32eb50d
CK		 1436 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1437 radeon_ring_write(ring, 0);
2281a378
AD		 1438
1439 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1440 radeon_ring_write(ring, 0xc0026f00);
1441 radeon_ring_write(ring, 0x00000000);
1442 radeon_ring_write(ring, 0x00000000);
1443 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1444
1445 /* Clear consts */
e32eb50d
CK		 1446 radeon_ring_write(ring, 0xc0036f00);
1447 radeon_ring_write(ring, 0x00000bc4);
1448 radeon_ring_write(ring, 0xffffffff);
1449 radeon_ring_write(ring, 0xffffffff);
1450 radeon_ring_write(ring, 0xffffffff);
2281a378 1451
e32eb50d
CK		 1452 radeon_ring_write(ring, 0xc0026900);
1453 radeon_ring_write(ring, 0x00000316);
1454 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1455 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1456
e32eb50d 1457 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1458
1459 return 0;
1460}
1461
fe251e2f
AD		 1462int evergreen_cp_resume(struct radeon_device *rdev)
1463{
e32eb50d 1464 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1465 u32 tmp;
1466 u32 rb_bufsz;
1467 int r;
1468
1469 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1470 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1471 SOFT_RESET_PA |
1472 SOFT_RESET_SH |
1473 SOFT_RESET_VGT |
a49a50da 1474 SOFT_RESET_SPI |
fe251e2f
AD		 1475 SOFT_RESET_SX));
1476 RREG32(GRBM_SOFT_RESET);
1477 mdelay(15);
1478 WREG32(GRBM_SOFT_RESET, 0);
1479 RREG32(GRBM_SOFT_RESET);
1480
1481 /* Set ring buffer size */
e32eb50d 1482 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1483 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1484#ifdef __BIG_ENDIAN
1485 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1486#endif
fe251e2f 1487 WREG32(CP_RB_CNTL, tmp);
15d3332f 1488 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1489 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1490
1491 /* Set the write pointer delay */
1492 WREG32(CP_RB_WPTR_DELAY, 0);
1493
1494 /* Initialize the ring buffer's read and write pointers */
1495 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1496 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1497 ring->wptr = 0;
1498 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1499
1500 /* set the wb address wether it's enabled or not */
0f234f5f 1501 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1502 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1503 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1504 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1505
1506 if (rdev->wb.enabled)
1507 WREG32(SCRATCH_UMSK, 0xff);
1508 else {
1509 tmp |= RB_NO_UPDATE;
1510 WREG32(SCRATCH_UMSK, 0);
1511 }
1512
fe251e2f
AD		 1513 mdelay(1);
1514 WREG32(CP_RB_CNTL, tmp);
1515
e32eb50d 1516 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1517 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1518
e32eb50d 1519 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1520
7e7b41d2 1521 evergreen_cp_start(rdev);
e32eb50d
CK		 1522 ring->ready = true;
1523 r = radeon_ring_test(rdev, ring);
fe251e2f 1524 if (r) {
e32eb50d 1525 ring->ready = false;
fe251e2f
AD		 1526 return r;
1527 }
1528 return 0;
1529}
bcc1c2a1
AD		 1530
1531/*
1532 * Core functions
1533 */
32fcdbf4
AD		 1534static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1535 u32 num_tile_pipes,
bcc1c2a1
AD		 1536 u32 num_backends,
1537 u32 backend_disable_mask)
1538{
1539 u32 backend_map = 0;
32fcdbf4
AD		 1540 u32 enabled_backends_mask = 0;
1541 u32 enabled_backends_count = 0;
1542 u32 cur_pipe;
1543 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1544 u32 cur_backend = 0;
1545 u32 i;
1546 bool force_no_swizzle;
1547
1548 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1549 num_tile_pipes = EVERGREEN_MAX_PIPES;
1550 if (num_tile_pipes < 1)
1551 num_tile_pipes = 1;
1552 if (num_backends > EVERGREEN_MAX_BACKENDS)
1553 num_backends = EVERGREEN_MAX_BACKENDS;
1554 if (num_backends < 1)
1555 num_backends = 1;
1556
1557 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1558 if (((backend_disable_mask >> i) & 1) == 0) {
1559 enabled_backends_mask |= (1 << i);
1560 ++enabled_backends_count;
1561 }
1562 if (enabled_backends_count == num_backends)
1563 break;
1564 }
1565
1566 if (enabled_backends_count == 0) {
1567 enabled_backends_mask = 1;
1568 enabled_backends_count = 1;
1569 }
1570
1571 if (enabled_backends_count != num_backends)
1572 num_backends = enabled_backends_count;
1573
1574 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1575 switch (rdev->family) {
1576 case CHIP_CEDAR:
1577 case CHIP_REDWOOD:
d5e455e4 1578 case CHIP_PALM:
d5c5a72f
AD		 1579 case CHIP_SUMO:
1580 case CHIP_SUMO2:
adb68fa2
AD		 1581 case CHIP_TURKS:
1582 case CHIP_CAICOS:
32fcdbf4
AD		 1583 force_no_swizzle = false;
1584 break;
1585 case CHIP_CYPRESS:
1586 case CHIP_HEMLOCK:
1587 case CHIP_JUNIPER:
adb68fa2 1588 case CHIP_BARTS:
32fcdbf4
AD		 1589 default:
1590 force_no_swizzle = true;
1591 break;
1592 }
1593 if (force_no_swizzle) {
1594 bool last_backend_enabled = false;
1595
1596 force_no_swizzle = false;
1597 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1598 if (((enabled_backends_mask >> i) & 1) == 1) {
1599 if (last_backend_enabled)
1600 force_no_swizzle = true;
1601 last_backend_enabled = true;
1602 } else
1603 last_backend_enabled = false;
1604 }
1605 }
1606
1607 switch (num_tile_pipes) {
1608 case 1:
1609 case 3:
1610 case 5:
1611 case 7:
1612 DRM_ERROR("odd number of pipes!\n");
1613 break;
1614 case 2:
1615 swizzle_pipe[0] = 0;
1616 swizzle_pipe[1] = 1;
1617 break;
1618 case 4:
1619 if (force_no_swizzle) {
1620 swizzle_pipe[0] = 0;
1621 swizzle_pipe[1] = 1;
1622 swizzle_pipe[2] = 2;
1623 swizzle_pipe[3] = 3;
1624 } else {
1625 swizzle_pipe[0] = 0;
1626 swizzle_pipe[1] = 2;
1627 swizzle_pipe[2] = 1;
1628 swizzle_pipe[3] = 3;
1629 }
1630 break;
1631 case 6:
1632 if (force_no_swizzle) {
1633 swizzle_pipe[0] = 0;
1634 swizzle_pipe[1] = 1;
1635 swizzle_pipe[2] = 2;
1636 swizzle_pipe[3] = 3;
1637 swizzle_pipe[4] = 4;
1638 swizzle_pipe[5] = 5;
1639 } else {
1640 swizzle_pipe[0] = 0;
1641 swizzle_pipe[1] = 2;
1642 swizzle_pipe[2] = 4;
1643 swizzle_pipe[3] = 1;
1644 swizzle_pipe[4] = 3;
1645 swizzle_pipe[5] = 5;
1646 }
1647 break;
1648 case 8:
1649 if (force_no_swizzle) {
1650 swizzle_pipe[0] = 0;
1651 swizzle_pipe[1] = 1;
1652 swizzle_pipe[2] = 2;
1653 swizzle_pipe[3] = 3;
1654 swizzle_pipe[4] = 4;
1655 swizzle_pipe[5] = 5;
1656 swizzle_pipe[6] = 6;
1657 swizzle_pipe[7] = 7;
1658 } else {
1659 swizzle_pipe[0] = 0;
1660 swizzle_pipe[1] = 2;
1661 swizzle_pipe[2] = 4;
1662 swizzle_pipe[3] = 6;
1663 swizzle_pipe[4] = 1;
1664 swizzle_pipe[5] = 3;
1665 swizzle_pipe[6] = 5;
1666 swizzle_pipe[7] = 7;
1667 }
1668 break;
1669 }
1670
1671 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1672 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1673 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1674
1675 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1676
1677 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1678 }
bcc1c2a1
AD		 1679
1680 return backend_map;
1681}
bcc1c2a1
AD		 1682
1683static void evergreen_gpu_init(struct radeon_device *rdev)
1684{
32fcdbf4
AD		 1685 u32 cc_rb_backend_disable = 0;
1686 u32 cc_gc_shader_pipe_config;
1687 u32 gb_addr_config = 0;
1688 u32 mc_shared_chmap, mc_arb_ramcfg;
1689 u32 gb_backend_map;
1690 u32 grbm_gfx_index;
1691 u32 sx_debug_1;
1692 u32 smx_dc_ctl0;
1693 u32 sq_config;
1694 u32 sq_lds_resource_mgmt;
1695 u32 sq_gpr_resource_mgmt_1;
1696 u32 sq_gpr_resource_mgmt_2;
1697 u32 sq_gpr_resource_mgmt_3;
1698 u32 sq_thread_resource_mgmt;
1699 u32 sq_thread_resource_mgmt_2;
1700 u32 sq_stack_resource_mgmt_1;
1701 u32 sq_stack_resource_mgmt_2;
1702 u32 sq_stack_resource_mgmt_3;
1703 u32 vgt_cache_invalidation;
f25a5c63 1704 u32 hdp_host_path_cntl, tmp;
32fcdbf4
AD		 1705 int i, j, num_shader_engines, ps_thread_count;
1706
1707 switch (rdev->family) {
1708 case CHIP_CYPRESS:
1709 case CHIP_HEMLOCK:
1710 rdev->config.evergreen.num_ses = 2;
1711 rdev->config.evergreen.max_pipes = 4;
1712 rdev->config.evergreen.max_tile_pipes = 8;
1713 rdev->config.evergreen.max_simds = 10;
1714 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1715 rdev->config.evergreen.max_gprs = 256;
1716 rdev->config.evergreen.max_threads = 248;
1717 rdev->config.evergreen.max_gs_threads = 32;
1718 rdev->config.evergreen.max_stack_entries = 512;
1719 rdev->config.evergreen.sx_num_of_sets = 4;
1720 rdev->config.evergreen.sx_max_export_size = 256;
1721 rdev->config.evergreen.sx_max_export_pos_size = 64;
1722 rdev->config.evergreen.sx_max_export_smx_size = 192;
1723 rdev->config.evergreen.max_hw_contexts = 8;
1724 rdev->config.evergreen.sq_num_cf_insts = 2;
1725
1726 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1727 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1728 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1729 break;
1730 case CHIP_JUNIPER:
1731 rdev->config.evergreen.num_ses = 1;
1732 rdev->config.evergreen.max_pipes = 4;
1733 rdev->config.evergreen.max_tile_pipes = 4;
1734 rdev->config.evergreen.max_simds = 10;
1735 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1736 rdev->config.evergreen.max_gprs = 256;
1737 rdev->config.evergreen.max_threads = 248;
1738 rdev->config.evergreen.max_gs_threads = 32;
1739 rdev->config.evergreen.max_stack_entries = 512;
1740 rdev->config.evergreen.sx_num_of_sets = 4;
1741 rdev->config.evergreen.sx_max_export_size = 256;
1742 rdev->config.evergreen.sx_max_export_pos_size = 64;
1743 rdev->config.evergreen.sx_max_export_smx_size = 192;
1744 rdev->config.evergreen.max_hw_contexts = 8;
1745 rdev->config.evergreen.sq_num_cf_insts = 2;
1746
1747 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1748 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1749 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1750 break;
1751 case CHIP_REDWOOD:
1752 rdev->config.evergreen.num_ses = 1;
1753 rdev->config.evergreen.max_pipes = 4;
1754 rdev->config.evergreen.max_tile_pipes = 4;
1755 rdev->config.evergreen.max_simds = 5;
1756 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1757 rdev->config.evergreen.max_gprs = 256;
1758 rdev->config.evergreen.max_threads = 248;
1759 rdev->config.evergreen.max_gs_threads = 32;
1760 rdev->config.evergreen.max_stack_entries = 256;
1761 rdev->config.evergreen.sx_num_of_sets = 4;
1762 rdev->config.evergreen.sx_max_export_size = 256;
1763 rdev->config.evergreen.sx_max_export_pos_size = 64;
1764 rdev->config.evergreen.sx_max_export_smx_size = 192;
1765 rdev->config.evergreen.max_hw_contexts = 8;
1766 rdev->config.evergreen.sq_num_cf_insts = 2;
1767
1768 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1769 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1770 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1771 break;
1772 case CHIP_CEDAR:
1773 default:
1774 rdev->config.evergreen.num_ses = 1;
1775 rdev->config.evergreen.max_pipes = 2;
1776 rdev->config.evergreen.max_tile_pipes = 2;
1777 rdev->config.evergreen.max_simds = 2;
1778 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1779 rdev->config.evergreen.max_gprs = 256;
1780 rdev->config.evergreen.max_threads = 192;
1781 rdev->config.evergreen.max_gs_threads = 16;
1782 rdev->config.evergreen.max_stack_entries = 256;
1783 rdev->config.evergreen.sx_num_of_sets = 4;
1784 rdev->config.evergreen.sx_max_export_size = 128;
1785 rdev->config.evergreen.sx_max_export_pos_size = 32;
1786 rdev->config.evergreen.sx_max_export_smx_size = 96;
1787 rdev->config.evergreen.max_hw_contexts = 4;
1788 rdev->config.evergreen.sq_num_cf_insts = 1;
1789
d5e455e4
AD		 1790 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1791 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1792 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1793 break;
1794 case CHIP_PALM:
1795 rdev->config.evergreen.num_ses = 1;
1796 rdev->config.evergreen.max_pipes = 2;
1797 rdev->config.evergreen.max_tile_pipes = 2;
1798 rdev->config.evergreen.max_simds = 2;
1799 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1800 rdev->config.evergreen.max_gprs = 256;
1801 rdev->config.evergreen.max_threads = 192;
1802 rdev->config.evergreen.max_gs_threads = 16;
1803 rdev->config.evergreen.max_stack_entries = 256;
1804 rdev->config.evergreen.sx_num_of_sets = 4;
1805 rdev->config.evergreen.sx_max_export_size = 128;
1806 rdev->config.evergreen.sx_max_export_pos_size = 32;
1807 rdev->config.evergreen.sx_max_export_smx_size = 96;
1808 rdev->config.evergreen.max_hw_contexts = 4;
1809 rdev->config.evergreen.sq_num_cf_insts = 1;
1810
d5c5a72f
AD		 1811 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1812 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1813 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1814 break;
1815 case CHIP_SUMO:
1816 rdev->config.evergreen.num_ses = 1;
1817 rdev->config.evergreen.max_pipes = 4;
1818 rdev->config.evergreen.max_tile_pipes = 2;
1819 if (rdev->pdev->device == 0x9648)
1820 rdev->config.evergreen.max_simds = 3;
1821 else if ((rdev->pdev->device == 0x9647) ||
1822 (rdev->pdev->device == 0x964a))
1823 rdev->config.evergreen.max_simds = 4;
1824 else
1825 rdev->config.evergreen.max_simds = 5;
1826 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1827 rdev->config.evergreen.max_gprs = 256;
1828 rdev->config.evergreen.max_threads = 248;
1829 rdev->config.evergreen.max_gs_threads = 32;
1830 rdev->config.evergreen.max_stack_entries = 256;
1831 rdev->config.evergreen.sx_num_of_sets = 4;
1832 rdev->config.evergreen.sx_max_export_size = 256;
1833 rdev->config.evergreen.sx_max_export_pos_size = 64;
1834 rdev->config.evergreen.sx_max_export_smx_size = 192;
1835 rdev->config.evergreen.max_hw_contexts = 8;
1836 rdev->config.evergreen.sq_num_cf_insts = 2;
1837
1838 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1839 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1840 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1841 break;
1842 case CHIP_SUMO2:
1843 rdev->config.evergreen.num_ses = 1;
1844 rdev->config.evergreen.max_pipes = 4;
1845 rdev->config.evergreen.max_tile_pipes = 4;
1846 rdev->config.evergreen.max_simds = 2;
1847 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1848 rdev->config.evergreen.max_gprs = 256;
1849 rdev->config.evergreen.max_threads = 248;
1850 rdev->config.evergreen.max_gs_threads = 32;
1851 rdev->config.evergreen.max_stack_entries = 512;
1852 rdev->config.evergreen.sx_num_of_sets = 4;
1853 rdev->config.evergreen.sx_max_export_size = 256;
1854 rdev->config.evergreen.sx_max_export_pos_size = 64;
1855 rdev->config.evergreen.sx_max_export_smx_size = 192;
1856 rdev->config.evergreen.max_hw_contexts = 8;
1857 rdev->config.evergreen.sq_num_cf_insts = 2;
1858
adb68fa2
AD		 1859 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1860 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1861 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1862 break;
1863 case CHIP_BARTS:
1864 rdev->config.evergreen.num_ses = 2;
1865 rdev->config.evergreen.max_pipes = 4;
1866 rdev->config.evergreen.max_tile_pipes = 8;
1867 rdev->config.evergreen.max_simds = 7;
1868 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1869 rdev->config.evergreen.max_gprs = 256;
1870 rdev->config.evergreen.max_threads = 248;
1871 rdev->config.evergreen.max_gs_threads = 32;
1872 rdev->config.evergreen.max_stack_entries = 512;
1873 rdev->config.evergreen.sx_num_of_sets = 4;
1874 rdev->config.evergreen.sx_max_export_size = 256;
1875 rdev->config.evergreen.sx_max_export_pos_size = 64;
1876 rdev->config.evergreen.sx_max_export_smx_size = 192;
1877 rdev->config.evergreen.max_hw_contexts = 8;
1878 rdev->config.evergreen.sq_num_cf_insts = 2;
1879
1880 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1881 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1882 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1883 break;
1884 case CHIP_TURKS:
1885 rdev->config.evergreen.num_ses = 1;
1886 rdev->config.evergreen.max_pipes = 4;
1887 rdev->config.evergreen.max_tile_pipes = 4;
1888 rdev->config.evergreen.max_simds = 6;
1889 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1890 rdev->config.evergreen.max_gprs = 256;
1891 rdev->config.evergreen.max_threads = 248;
1892 rdev->config.evergreen.max_gs_threads = 32;
1893 rdev->config.evergreen.max_stack_entries = 256;
1894 rdev->config.evergreen.sx_num_of_sets = 4;
1895 rdev->config.evergreen.sx_max_export_size = 256;
1896 rdev->config.evergreen.sx_max_export_pos_size = 64;
1897 rdev->config.evergreen.sx_max_export_smx_size = 192;
1898 rdev->config.evergreen.max_hw_contexts = 8;
1899 rdev->config.evergreen.sq_num_cf_insts = 2;
1900
1901 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1902 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1903 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1904 break;
1905 case CHIP_CAICOS:
1906 rdev->config.evergreen.num_ses = 1;
1907 rdev->config.evergreen.max_pipes = 4;
1908 rdev->config.evergreen.max_tile_pipes = 2;
1909 rdev->config.evergreen.max_simds = 2;
1910 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1911 rdev->config.evergreen.max_gprs = 256;
1912 rdev->config.evergreen.max_threads = 192;
1913 rdev->config.evergreen.max_gs_threads = 16;
1914 rdev->config.evergreen.max_stack_entries = 256;
1915 rdev->config.evergreen.sx_num_of_sets = 4;
1916 rdev->config.evergreen.sx_max_export_size = 128;
1917 rdev->config.evergreen.sx_max_export_pos_size = 32;
1918 rdev->config.evergreen.sx_max_export_smx_size = 96;
1919 rdev->config.evergreen.max_hw_contexts = 4;
1920 rdev->config.evergreen.sq_num_cf_insts = 1;
1921
32fcdbf4
AD		 1922 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1923 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1924 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1925 break;
1926 }
1927
1928 /* Initialize HDP */
1929 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1930 WREG32((0x2c14 + j), 0x00000000);
1931 WREG32((0x2c18 + j), 0x00000000);
1932 WREG32((0x2c1c + j), 0x00000000);
1933 WREG32((0x2c20 + j), 0x00000000);
1934 WREG32((0x2c24 + j), 0x00000000);
1935 }
1936
1937 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1938
d054ac16
AD		 1939 evergreen_fix_pci_max_read_req_size(rdev);
1940
32fcdbf4
AD		 1941 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1942
1943 cc_gc_shader_pipe_config |=
1944 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1945 & EVERGREEN_MAX_PIPES_MASK);
1946 cc_gc_shader_pipe_config |=
1947 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1948 & EVERGREEN_MAX_SIMDS_MASK);
1949
1950 cc_rb_backend_disable =
1951 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1952 & EVERGREEN_MAX_BACKENDS_MASK);
1953
1954
1955 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
d9282fca
AD		 1956 if (rdev->flags & RADEON_IS_IGP)
1957 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1958 else
1959 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4
AD		 1960
1961 switch (rdev->config.evergreen.max_tile_pipes) {
1962 case 1:
1963 default:
1964 gb_addr_config |= NUM_PIPES(0);
1965 break;
1966 case 2:
1967 gb_addr_config |= NUM_PIPES(1);
1968 break;
1969 case 4:
1970 gb_addr_config |= NUM_PIPES(2);
1971 break;
1972 case 8:
1973 gb_addr_config |= NUM_PIPES(3);
1974 break;
1975 }
1976
1977 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1978 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1979 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1980 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1981 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1982 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1983
1984 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1985 gb_addr_config |= ROW_SIZE(2);
1986 else
1987 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1988
1989 if (rdev->ddev->pdev->device == 0x689e) {
1990 u32 efuse_straps_4;
1991 u32 efuse_straps_3;
1992 u8 efuse_box_bit_131_124;
1993
1994 WREG32(RCU_IND_INDEX, 0x204);
1995 efuse_straps_4 = RREG32(RCU_IND_DATA);
1996 WREG32(RCU_IND_INDEX, 0x203);
1997 efuse_straps_3 = RREG32(RCU_IND_DATA);
1998 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1999
2000 switch(efuse_box_bit_131_124) {
2001 case 0x00:
2002 gb_backend_map = 0x76543210;
2003 break;
2004 case 0x55:
2005 gb_backend_map = 0x77553311;
2006 break;
2007 case 0x56:
2008 gb_backend_map = 0x77553300;
2009 break;
2010 case 0x59:
2011 gb_backend_map = 0x77552211;
2012 break;
2013 case 0x66:
2014 gb_backend_map = 0x77443300;
2015 break;
2016 case 0x99:
2017 gb_backend_map = 0x66552211;
2018 break;
2019 case 0x5a:
2020 gb_backend_map = 0x77552200;
2021 break;
2022 case 0xaa:
2023 gb_backend_map = 0x66442200;
2024 break;
2025 case 0x95:
2026 gb_backend_map = 0x66553311;
2027 break;
2028 default:
2029 DRM_ERROR("bad backend map, using default\n");
2030 gb_backend_map =
2031 evergreen_get_tile_pipe_to_backend_map(rdev,
2032 rdev->config.evergreen.max_tile_pipes,
2033 rdev->config.evergreen.max_backends,
2034 ((EVERGREEN_MAX_BACKENDS_MASK <<
2035 rdev->config.evergreen.max_backends) &
2036 EVERGREEN_MAX_BACKENDS_MASK));
2037 break;
2038 }
2039 } else if (rdev->ddev->pdev->device == 0x68b9) {
2040 u32 efuse_straps_3;
2041 u8 efuse_box_bit_127_124;
2042
2043 WREG32(RCU_IND_INDEX, 0x203);
2044 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 2045 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 2046
2047 switch(efuse_box_bit_127_124) {
2048 case 0x0:
2049 gb_backend_map = 0x00003210;
2050 break;
2051 case 0x5:
2052 case 0x6:
2053 case 0x9:
2054 case 0xa:
2055 gb_backend_map = 0x00003311;
2056 break;
2057 default:
2058 DRM_ERROR("bad backend map, using default\n");
2059 gb_backend_map =
2060 evergreen_get_tile_pipe_to_backend_map(rdev,
2061 rdev->config.evergreen.max_tile_pipes,
2062 rdev->config.evergreen.max_backends,
2063 ((EVERGREEN_MAX_BACKENDS_MASK <<
2064 rdev->config.evergreen.max_backends) &
2065 EVERGREEN_MAX_BACKENDS_MASK));
2066 break;
2067 }
b741be82
AD		 2068 } else {
2069 switch (rdev->family) {
2070 case CHIP_CYPRESS:
2071 case CHIP_HEMLOCK:
03f40090 2072 case CHIP_BARTS:
b741be82
AD		 2073 gb_backend_map = 0x66442200;
2074 break;
2075 case CHIP_JUNIPER:
9a4a0b9c 2076 gb_backend_map = 0x00002200;
b741be82
AD		 2077 break;
2078 default:
2079 gb_backend_map =
2080 evergreen_get_tile_pipe_to_backend_map(rdev,
2081 rdev->config.evergreen.max_tile_pipes,
2082 rdev->config.evergreen.max_backends,
2083 ((EVERGREEN_MAX_BACKENDS_MASK <<
2084 rdev->config.evergreen.max_backends) &
2085 EVERGREEN_MAX_BACKENDS_MASK));
2086 }
2087 }
32fcdbf4 2088
1aa52bd3
AD		 2089 /* setup tiling info dword. gb_addr_config is not adequate since it does
2090 * not have bank info, so create a custom tiling dword.
2091 * bits 3:0 num_pipes
2092 * bits 7:4 num_banks
2093 * bits 11:8 group_size
2094 * bits 15:12 row_size
2095 */
2096 rdev->config.evergreen.tile_config = 0;
2097 switch (rdev->config.evergreen.max_tile_pipes) {
2098 case 1:
2099 default:
2100 rdev->config.evergreen.tile_config |= (0 << 0);
2101 break;
2102 case 2:
2103 rdev->config.evergreen.tile_config |= (1 << 0);
2104 break;
2105 case 4:
2106 rdev->config.evergreen.tile_config |= (2 << 0);
2107 break;
2108 case 8:
2109 rdev->config.evergreen.tile_config |= (3 << 0);
2110 break;
2111 }
d698a34d 2112 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 2113 if (rdev->flags & RADEON_IS_IGP)
d698a34d 2114 rdev->config.evergreen.tile_config |= 1 << 4;
5bfa4879
AD		 2115 else
2116 rdev->config.evergreen.tile_config |=
2117 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1aa52bd3
AD		 2118 rdev->config.evergreen.tile_config |=
2119 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2120 rdev->config.evergreen.tile_config |=
2121 ((gb_addr_config & 0x30000000) >> 28) << 12;
2122
e55b9422 2123 rdev->config.evergreen.backend_map = gb_backend_map;
32fcdbf4
AD		 2124 WREG32(GB_BACKEND_MAP, gb_backend_map);
2125 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2126 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2127 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2128
2129 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2130 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2131
2132 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2133 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2134 u32 sp = cc_gc_shader_pipe_config;
2135 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2136
2137 if (i == num_shader_engines) {
2138 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2139 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2140 }
2141
2142 WREG32(GRBM_GFX_INDEX, gfx);
2143 WREG32(RLC_GFX_INDEX, gfx);
2144
2145 WREG32(CC_RB_BACKEND_DISABLE, rb);
2146 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2147 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2148 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2149 }
2150
2151 grbm_gfx_index |= SE_BROADCAST_WRITES;
2152 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2153 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2154
2155 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2156 WREG32(CGTS_TCC_DISABLE, 0);
2157 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2158 WREG32(CGTS_USER_TCC_DISABLE, 0);
2159
2160 /* set HW defaults for 3D engine */
2161 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2162 ROQ_IB2_START(0x2b)));
2163
2164 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2165
2166 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2167 SYNC_GRADIENT |
2168 SYNC_WALKER |
2169 SYNC_ALIGNER));
2170
2171 sx_debug_1 = RREG32(SX_DEBUG_1);
2172 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2173 WREG32(SX_DEBUG_1, sx_debug_1);
2174
2175
2176 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2177 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2178 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2179 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2180
2181 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2182 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2183 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2184
2185 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2186 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2187 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2188
2189 WREG32(VGT_NUM_INSTANCES, 1);
2190 WREG32(SPI_CONFIG_CNTL, 0);
2191 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2192 WREG32(CP_PERFMON_CNTL, 0);
2193
2194 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2195 FETCH_FIFO_HIWATER(0x4) |
2196 DONE_FIFO_HIWATER(0xe0) |
2197 ALU_UPDATE_FIFO_HIWATER(0x8)));
2198
2199 sq_config = RREG32(SQ_CONFIG);
2200 sq_config &= ~(PS_PRIO(3) |
2201 VS_PRIO(3) |
2202 GS_PRIO(3) |
2203 ES_PRIO(3));
2204 sq_config |= (VC_ENABLE |
2205 EXPORT_SRC_C |
2206 PS_PRIO(0) |
2207 VS_PRIO(1) |
2208 GS_PRIO(2) |
2209 ES_PRIO(3));
2210
d5e455e4
AD		 2211 switch (rdev->family) {
2212 case CHIP_CEDAR:
2213 case CHIP_PALM:
d5c5a72f
AD		 2214 case CHIP_SUMO:
2215 case CHIP_SUMO2:
adb68fa2 2216 case CHIP_CAICOS:
32fcdbf4
AD		 2217 /* no vertex cache */
2218 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2219 break;
2220 default:
2221 break;
2222 }
32fcdbf4
AD		 2223
2224 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2225
2226 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2227 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2228 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2229 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2230 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2231 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2232 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2233
d5e455e4
AD		 2234 switch (rdev->family) {
2235 case CHIP_CEDAR:
2236 case CHIP_PALM:
d5c5a72f
AD		 2237 case CHIP_SUMO:
2238 case CHIP_SUMO2:
32fcdbf4 2239 ps_thread_count = 96;
d5e455e4
AD		 2240 break;
2241 default:
32fcdbf4 2242 ps_thread_count = 128;
d5e455e4
AD		 2243 break;
2244 }
32fcdbf4
AD		 2245
2246 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2247 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2248 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2249 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2250 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2251 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2252
2253 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2254 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2255 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2256 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2257 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2258 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2259
2260 WREG32(SQ_CONFIG, sq_config);
2261 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2262 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2263 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2264 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2265 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2266 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2267 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2268 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2269 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2270 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2271
2272 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2273 FORCE_EOV_MAX_REZ_CNT(255)));
2274
d5e455e4
AD		 2275 switch (rdev->family) {
2276 case CHIP_CEDAR:
2277 case CHIP_PALM:
d5c5a72f
AD		 2278 case CHIP_SUMO:
2279 case CHIP_SUMO2:
adb68fa2 2280 case CHIP_CAICOS:
32fcdbf4 2281 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2282 break;
2283 default:
32fcdbf4 2284 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2285 break;
2286 }
32fcdbf4
AD		 2287 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2288 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2289
2290 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2291 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2292 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2293
60a4a3e0
AD		 2294 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2295 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2296
32fcdbf4
AD		 2297 WREG32(CB_PERF_CTR0_SEL_0, 0);
2298 WREG32(CB_PERF_CTR0_SEL_1, 0);
2299 WREG32(CB_PERF_CTR1_SEL_0, 0);
2300 WREG32(CB_PERF_CTR1_SEL_1, 0);
2301 WREG32(CB_PERF_CTR2_SEL_0, 0);
2302 WREG32(CB_PERF_CTR2_SEL_1, 0);
2303 WREG32(CB_PERF_CTR3_SEL_0, 0);
2304 WREG32(CB_PERF_CTR3_SEL_1, 0);
2305
60a4a3e0
AD		 2306 /* clear render buffer base addresses */
2307 WREG32(CB_COLOR0_BASE, 0);
2308 WREG32(CB_COLOR1_BASE, 0);
2309 WREG32(CB_COLOR2_BASE, 0);
2310 WREG32(CB_COLOR3_BASE, 0);
2311 WREG32(CB_COLOR4_BASE, 0);
2312 WREG32(CB_COLOR5_BASE, 0);
2313 WREG32(CB_COLOR6_BASE, 0);
2314 WREG32(CB_COLOR7_BASE, 0);
2315 WREG32(CB_COLOR8_BASE, 0);
2316 WREG32(CB_COLOR9_BASE, 0);
2317 WREG32(CB_COLOR10_BASE, 0);
2318 WREG32(CB_COLOR11_BASE, 0);
2319
2320 /* set the shader const cache sizes to 0 */
2321 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2322 WREG32(i, 0);
2323 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2324 WREG32(i, 0);
2325
f25a5c63
AD		 2326 tmp = RREG32(HDP_MISC_CNTL);
2327 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2328 WREG32(HDP_MISC_CNTL, tmp);
2329
32fcdbf4
AD		 2330 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2331 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2332
2333 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2334
2335 udelay(50);
2336
bcc1c2a1
AD		 2337}
2338
2339int evergreen_mc_init(struct radeon_device *rdev)
2340{
bcc1c2a1
AD		 2341 u32 tmp;
2342 int chansize, numchan;
bcc1c2a1
AD		 2343
2344 /* Get VRAM informations */
2345 rdev->mc.vram_is_ddr = true;
8208441b
AD		 2346 if (rdev->flags & RADEON_IS_IGP)
2347 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2348 else
2349 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2350 if (tmp & CHANSIZE_OVERRIDE) {
2351 chansize = 16;
2352 } else if (tmp & CHANSIZE_MASK) {
2353 chansize = 64;
2354 } else {
2355 chansize = 32;
2356 }
2357 tmp = RREG32(MC_SHARED_CHMAP);
2358 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2359 case 0:
2360 default:
2361 numchan = 1;
2362 break;
2363 case 1:
2364 numchan = 2;
2365 break;
2366 case 2:
2367 numchan = 4;
2368 break;
2369 case 3:
2370 numchan = 8;
2371 break;
2372 }
2373 rdev->mc.vram_width = numchan * chansize;
2374 /* Could aper size report 0 ? */
01d73a69
JC		 2375 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2376 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2377 /* Setup GPU memory space */
6eb18f8b
AD		 2378 if (rdev->flags & RADEON_IS_IGP) {
2379 /* size in bytes on fusion */
2380 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2381 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2382 } else {
2383 /* size in MB on evergreen */
2384 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2385 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2386 }
51e5fcd3 2387 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2388 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2389 radeon_update_bandwidth_info(rdev);
2390
bcc1c2a1
AD		 2391 return 0;
2392}
d594e46a 2393
e32eb50d 2394bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 2395{
17db7042
AD		 2396 u32 srbm_status;
2397 u32 grbm_status;
2398 u32 grbm_status_se0, grbm_status_se1;
2399 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2400 int r;
2401
2402 srbm_status = RREG32(SRBM_STATUS);
2403 grbm_status = RREG32(GRBM_STATUS);
2404 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2405 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2406 if (!(grbm_status & GUI_ACTIVE)) {
e32eb50d 2407 r100_gpu_lockup_update(lockup, ring);
17db7042
AD		 2408 return false;
2409 }
2410 /* force CP activities */
e32eb50d 2411 r = radeon_ring_lock(rdev, ring, 2);
17db7042
AD		 2412 if (!r) {
2413 /* PACKET2 NOP */
e32eb50d
CK		 2414 radeon_ring_write(ring, 0x80000000);
2415 radeon_ring_write(ring, 0x80000000);
2416 radeon_ring_unlock_commit(rdev, ring);
17db7042 2417 }
e32eb50d
CK		 2418 ring->rptr = RREG32(CP_RB_RPTR);
2419 return r100_gpu_cp_is_lockup(rdev, lockup, ring);
225758d8
JG		 2420}
2421
747943ea 2422static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2423{
747943ea 2424 struct evergreen_mc_save save;
747943ea
AD		 2425 u32 grbm_reset = 0;
2426
8d96fe93
AD		 2427 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2428 return 0;
2429
747943ea
AD		 2430 dev_info(rdev->dev, "GPU softreset \n");
2431 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2432 RREG32(GRBM_STATUS));
2433 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2434 RREG32(GRBM_STATUS_SE0));
2435 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2436 RREG32(GRBM_STATUS_SE1));
2437 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2438 RREG32(SRBM_STATUS));
2439 evergreen_mc_stop(rdev, &save);
2440 if (evergreen_mc_wait_for_idle(rdev)) {
2441 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2442 }
2443 /* Disable CP parsing/prefetching */
2444 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2445
2446 /* reset all the gfx blocks */
2447 grbm_reset = (SOFT_RESET_CP |
2448 SOFT_RESET_CB |
2449 SOFT_RESET_DB |
2450 SOFT_RESET_PA |
2451 SOFT_RESET_SC |
2452 SOFT_RESET_SPI |
2453 SOFT_RESET_SH |
2454 SOFT_RESET_SX |
2455 SOFT_RESET_TC |
2456 SOFT_RESET_TA |
2457 SOFT_RESET_VC |
2458 SOFT_RESET_VGT);
2459
2460 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2461 WREG32(GRBM_SOFT_RESET, grbm_reset);
2462 (void)RREG32(GRBM_SOFT_RESET);
2463 udelay(50);
2464 WREG32(GRBM_SOFT_RESET, 0);
2465 (void)RREG32(GRBM_SOFT_RESET);
747943ea
AD		 2466 /* Wait a little for things to settle down */
2467 udelay(50);
2468 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2469 RREG32(GRBM_STATUS));
2470 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2471 RREG32(GRBM_STATUS_SE0));
2472 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2473 RREG32(GRBM_STATUS_SE1));
2474 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2475 RREG32(SRBM_STATUS));
747943ea 2476 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2477 return 0;
2478}
2479
a2d07b74 2480int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2481{
747943ea
AD		 2482 return evergreen_gpu_soft_reset(rdev);
2483}
2484
45f9a39b
AD		 2485/* Interrupts */
2486
2487u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2488{
2489 switch (crtc) {
2490 case 0:
2491 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2492 case 1:
2493 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2494 case 2:
2495 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2496 case 3:
2497 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2498 case 4:
2499 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2500 case 5:
2501 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2502 default:
2503 return 0;
2504 }
2505}
2506
2507void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2508{
2509 u32 tmp;
2510
1b37078b
AD		 2511 if (rdev->family >= CHIP_CAYMAN) {
2512 cayman_cp_int_cntl_setup(rdev, 0,
2513 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2514 cayman_cp_int_cntl_setup(rdev, 1, 0);
2515 cayman_cp_int_cntl_setup(rdev, 2, 0);
2516 } else
2517 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2518 WREG32(GRBM_INT_CNTL, 0);
2519 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2520 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2521 if (rdev->num_crtc >= 4) {
18007401
AD		 2522 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2523 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2524 }
2525 if (rdev->num_crtc >= 6) {
18007401
AD		 2526 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2527 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2528 }
45f9a39b
AD		 2529
2530 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2531 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2532 if (rdev->num_crtc >= 4) {
18007401
AD		 2533 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2534 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2535 }
2536 if (rdev->num_crtc >= 6) {
18007401
AD		 2537 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2538 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2539 }
45f9a39b
AD		 2540
2541 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2542 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2543
2544 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2545 WREG32(DC_HPD1_INT_CONTROL, tmp);
2546 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2547 WREG32(DC_HPD2_INT_CONTROL, tmp);
2548 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2549 WREG32(DC_HPD3_INT_CONTROL, tmp);
2550 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2551 WREG32(DC_HPD4_INT_CONTROL, tmp);
2552 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2553 WREG32(DC_HPD5_INT_CONTROL, tmp);
2554 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2555 WREG32(DC_HPD6_INT_CONTROL, tmp);
2556
2557}
2558
2559int evergreen_irq_set(struct radeon_device *rdev)
2560{
2561 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2562 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2563 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2564 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2565 u32 grbm_int_cntl = 0;
6f34be50 2566 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
45f9a39b
AD		 2567
2568 if (!rdev->irq.installed) {
fce7d61b 2569 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2570 return -EINVAL;
2571 }
2572 /* don't enable anything if the ih is disabled */
2573 if (!rdev->ih.enabled) {
2574 r600_disable_interrupts(rdev);
2575 /* force the active interrupt state to all disabled */
2576 evergreen_disable_interrupt_state(rdev);
2577 return 0;
2578 }
2579
2580 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2581 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2582 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2583 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2584 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2585 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2586
1b37078b
AD		 2587 if (rdev->family >= CHIP_CAYMAN) {
2588 /* enable CP interrupts on all rings */
2589 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2590 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2591 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2592 }
2593 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2594 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2595 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2596 }
2597 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2598 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2599 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2600 }
2601 } else {
2602 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2603 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2604 cp_int_cntl |= RB_INT_ENABLE;
2605 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2606 }
45f9a39b 2607 }
1b37078b 2608
6f34be50
AD		 2609 if (rdev->irq.crtc_vblank_int[0] ||
2610 rdev->irq.pflip[0]) {
45f9a39b
AD		 2611 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2612 crtc1 |= VBLANK_INT_MASK;
2613 }
6f34be50
AD		 2614 if (rdev->irq.crtc_vblank_int[1] ||
2615 rdev->irq.pflip[1]) {
45f9a39b
AD		 2616 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2617 crtc2 |= VBLANK_INT_MASK;
2618 }
6f34be50
AD		 2619 if (rdev->irq.crtc_vblank_int[2] ||
2620 rdev->irq.pflip[2]) {
45f9a39b
AD		 2621 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2622 crtc3 |= VBLANK_INT_MASK;
2623 }
6f34be50
AD		 2624 if (rdev->irq.crtc_vblank_int[3] ||
2625 rdev->irq.pflip[3]) {
45f9a39b
AD		 2626 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2627 crtc4 |= VBLANK_INT_MASK;
2628 }
6f34be50
AD		 2629 if (rdev->irq.crtc_vblank_int[4] ||
2630 rdev->irq.pflip[4]) {
45f9a39b
AD		 2631 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2632 crtc5 |= VBLANK_INT_MASK;
2633 }
6f34be50
AD		 2634 if (rdev->irq.crtc_vblank_int[5] ||
2635 rdev->irq.pflip[5]) {
45f9a39b
AD		 2636 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2637 crtc6 |= VBLANK_INT_MASK;
2638 }
2639 if (rdev->irq.hpd[0]) {
2640 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2641 hpd1 |= DC_HPDx_INT_EN;
2642 }
2643 if (rdev->irq.hpd[1]) {
2644 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2645 hpd2 |= DC_HPDx_INT_EN;
2646 }
2647 if (rdev->irq.hpd[2]) {
2648 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2649 hpd3 |= DC_HPDx_INT_EN;
2650 }
2651 if (rdev->irq.hpd[3]) {
2652 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2653 hpd4 |= DC_HPDx_INT_EN;
2654 }
2655 if (rdev->irq.hpd[4]) {
2656 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2657 hpd5 |= DC_HPDx_INT_EN;
2658 }
2659 if (rdev->irq.hpd[5]) {
2660 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2661 hpd6 |= DC_HPDx_INT_EN;
2662 }
2031f77c
AD		 2663 if (rdev->irq.gui_idle) {
2664 DRM_DEBUG("gui idle\n");
2665 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2666 }
45f9a39b 2667
1b37078b
AD		 2668 if (rdev->family >= CHIP_CAYMAN) {
2669 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2670 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2671 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2672 } else
2673 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2674 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2675
2676 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2677 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2678 if (rdev->num_crtc >= 4) {
18007401
AD		 2679 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2680 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2681 }
2682 if (rdev->num_crtc >= 6) {
18007401
AD		 2683 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2684 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2685 }
45f9a39b 2686
6f34be50
AD		 2687 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2688 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2689 if (rdev->num_crtc >= 4) {
2690 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2691 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2692 }
2693 if (rdev->num_crtc >= 6) {
2694 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2695 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2696 }
6f34be50 2697
45f9a39b
AD		 2698 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2699 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2700 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2701 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2702 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2703 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2704
bcc1c2a1
AD		 2705 return 0;
2706}
2707
cbdd4501 2708static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2709{
2710 u32 tmp;
2711
6f34be50
AD		 2712 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2713 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2714 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2715 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2716 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2717 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2718 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2719 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2720 if (rdev->num_crtc >= 4) {
2721 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2722 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2723 }
2724 if (rdev->num_crtc >= 6) {
2725 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2726 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2727 }
6f34be50
AD		 2728
2729 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2730 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2731 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2732 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2733 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2734 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2735 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2736 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2737 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2738 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2739 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2740 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2741
b7eff394
AD		 2742 if (rdev->num_crtc >= 4) {
2743 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2744 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2745 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2746 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2747 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2748 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2749 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2750 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2751 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2752 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2753 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2754 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2755 }
2756
2757 if (rdev->num_crtc >= 6) {
2758 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2759 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2760 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2761 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2762 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2763 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2764 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2765 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2766 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2767 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2768 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2769 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2770 }
45f9a39b 2771
6f34be50 2772 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2773 tmp = RREG32(DC_HPD1_INT_CONTROL);
2774 tmp |= DC_HPDx_INT_ACK;
2775 WREG32(DC_HPD1_INT_CONTROL, tmp);
2776 }
6f34be50 2777 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2778 tmp = RREG32(DC_HPD2_INT_CONTROL);
2779 tmp |= DC_HPDx_INT_ACK;
2780 WREG32(DC_HPD2_INT_CONTROL, tmp);
2781 }
6f34be50 2782 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2783 tmp = RREG32(DC_HPD3_INT_CONTROL);
2784 tmp |= DC_HPDx_INT_ACK;
2785 WREG32(DC_HPD3_INT_CONTROL, tmp);
2786 }
6f34be50 2787 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2788 tmp = RREG32(DC_HPD4_INT_CONTROL);
2789 tmp |= DC_HPDx_INT_ACK;
2790 WREG32(DC_HPD4_INT_CONTROL, tmp);
2791 }
6f34be50 2792 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2793 tmp = RREG32(DC_HPD5_INT_CONTROL);
2794 tmp |= DC_HPDx_INT_ACK;
2795 WREG32(DC_HPD5_INT_CONTROL, tmp);
2796 }
6f34be50 2797 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2798 tmp = RREG32(DC_HPD5_INT_CONTROL);
2799 tmp |= DC_HPDx_INT_ACK;
2800 WREG32(DC_HPD6_INT_CONTROL, tmp);
2801 }
2802}
2803
2804void evergreen_irq_disable(struct radeon_device *rdev)
2805{
45f9a39b
AD		 2806 r600_disable_interrupts(rdev);
2807 /* Wait and acknowledge irq */
2808 mdelay(1);
6f34be50 2809 evergreen_irq_ack(rdev);
45f9a39b
AD		 2810 evergreen_disable_interrupt_state(rdev);
2811}
2812
755d819e 2813void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2814{
2815 evergreen_irq_disable(rdev);
2816 r600_rlc_stop(rdev);
2817}
2818
cbdd4501 2819static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 2820{
2821 u32 wptr, tmp;
2822
724c80e1 2823 if (rdev->wb.enabled)
204ae24d 2824 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 2825 else
2826 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2827
2828 if (wptr & RB_OVERFLOW) {
2829 /* When a ring buffer overflow happen start parsing interrupt
2830 * from the last not overwritten vector (wptr + 16). Hopefully
2831 * this should allow us to catchup.
2832 */
2833 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2834 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2835 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2836 tmp = RREG32(IH_RB_CNTL);
2837 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2838 WREG32(IH_RB_CNTL, tmp);
2839 }
2840 return (wptr & rdev->ih.ptr_mask);
2841}
2842
2843int evergreen_irq_process(struct radeon_device *rdev)
2844{
682f1a54
DA		 2845 u32 wptr;
2846 u32 rptr;
45f9a39b
AD		 2847 u32 src_id, src_data;
2848 u32 ring_index;
45f9a39b
AD		 2849 unsigned long flags;
2850 bool queue_hotplug = false;
2851
682f1a54 2852 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 2853 return IRQ_NONE;
2854
682f1a54
DA		 2855 wptr = evergreen_get_ih_wptr(rdev);
2856 rptr = rdev->ih.rptr;
2857 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 2858
682f1a54 2859 spin_lock_irqsave(&rdev->ih.lock, flags);
45f9a39b
AD		 2860 if (rptr == wptr) {
2861 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2862 return IRQ_NONE;
2863 }
45f9a39b 2864restart_ih:
964f6645
BH		 2865 /* Order reading of wptr vs. reading of IH ring data */
2866 rmb();
2867
45f9a39b 2868 /* display interrupts */
6f34be50 2869 evergreen_irq_ack(rdev);
45f9a39b
AD		 2870
2871 rdev->ih.wptr = wptr;
2872 while (rptr != wptr) {
2873 /* wptr/rptr are in bytes! */
2874 ring_index = rptr / 4;
0f234f5f
AD		 2875 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2876 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 2877
2878 switch (src_id) {
2879 case 1: /* D1 vblank/vline */
2880 switch (src_data) {
2881 case 0: /* D1 vblank */
6f34be50 2882 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2883 if (rdev->irq.crtc_vblank_int[0]) {
2884 drm_handle_vblank(rdev->ddev, 0);
2885 rdev->pm.vblank_sync = true;
2886 wake_up(&rdev->irq.vblank_queue);
2887 }
3e4ea742
MK		 2888 if (rdev->irq.pflip[0])
2889 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2890 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2891 DRM_DEBUG("IH: D1 vblank\n");
2892 }
2893 break;
2894 case 1: /* D1 vline */
6f34be50
AD		 2895 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2896 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2897 DRM_DEBUG("IH: D1 vline\n");
2898 }
2899 break;
2900 default:
2901 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2902 break;
2903 }
2904 break;
2905 case 2: /* D2 vblank/vline */
2906 switch (src_data) {
2907 case 0: /* D2 vblank */
6f34be50 2908 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2909 if (rdev->irq.crtc_vblank_int[1]) {
2910 drm_handle_vblank(rdev->ddev, 1);
2911 rdev->pm.vblank_sync = true;
2912 wake_up(&rdev->irq.vblank_queue);
2913 }
3e4ea742
MK		 2914 if (rdev->irq.pflip[1])
2915 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2916 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2917 DRM_DEBUG("IH: D2 vblank\n");
2918 }
2919 break;
2920 case 1: /* D2 vline */
6f34be50
AD		 2921 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2922 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2923 DRM_DEBUG("IH: D2 vline\n");
2924 }
2925 break;
2926 default:
2927 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2928 break;
2929 }
2930 break;
2931 case 3: /* D3 vblank/vline */
2932 switch (src_data) {
2933 case 0: /* D3 vblank */
6f34be50
AD		 2934 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2935 if (rdev->irq.crtc_vblank_int[2]) {
2936 drm_handle_vblank(rdev->ddev, 2);
2937 rdev->pm.vblank_sync = true;
2938 wake_up(&rdev->irq.vblank_queue);
2939 }
2940 if (rdev->irq.pflip[2])
2941 radeon_crtc_handle_flip(rdev, 2);
2942 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2943 DRM_DEBUG("IH: D3 vblank\n");
2944 }
2945 break;
2946 case 1: /* D3 vline */
6f34be50
AD		 2947 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2948 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2949 DRM_DEBUG("IH: D3 vline\n");
2950 }
2951 break;
2952 default:
2953 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2954 break;
2955 }
2956 break;
2957 case 4: /* D4 vblank/vline */
2958 switch (src_data) {
2959 case 0: /* D4 vblank */
6f34be50
AD		 2960 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2961 if (rdev->irq.crtc_vblank_int[3]) {
2962 drm_handle_vblank(rdev->ddev, 3);
2963 rdev->pm.vblank_sync = true;
2964 wake_up(&rdev->irq.vblank_queue);
2965 }
2966 if (rdev->irq.pflip[3])
2967 radeon_crtc_handle_flip(rdev, 3);
2968 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2969 DRM_DEBUG("IH: D4 vblank\n");
2970 }
2971 break;
2972 case 1: /* D4 vline */
6f34be50
AD		 2973 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2974 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2975 DRM_DEBUG("IH: D4 vline\n");
2976 }
2977 break;
2978 default:
2979 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2980 break;
2981 }
2982 break;
2983 case 5: /* D5 vblank/vline */
2984 switch (src_data) {
2985 case 0: /* D5 vblank */
6f34be50
AD		 2986 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2987 if (rdev->irq.crtc_vblank_int[4]) {
2988 drm_handle_vblank(rdev->ddev, 4);
2989 rdev->pm.vblank_sync = true;
2990 wake_up(&rdev->irq.vblank_queue);
2991 }
2992 if (rdev->irq.pflip[4])
2993 radeon_crtc_handle_flip(rdev, 4);
2994 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 2995 DRM_DEBUG("IH: D5 vblank\n");
2996 }
2997 break;
2998 case 1: /* D5 vline */
6f34be50
AD		 2999 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3000 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3001 DRM_DEBUG("IH: D5 vline\n");
3002 }
3003 break;
3004 default:
3005 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3006 break;
3007 }
3008 break;
3009 case 6: /* D6 vblank/vline */
3010 switch (src_data) {
3011 case 0: /* D6 vblank */
6f34be50
AD		 3012 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3013 if (rdev->irq.crtc_vblank_int[5]) {
3014 drm_handle_vblank(rdev->ddev, 5);
3015 rdev->pm.vblank_sync = true;
3016 wake_up(&rdev->irq.vblank_queue);
3017 }
3018 if (rdev->irq.pflip[5])
3019 radeon_crtc_handle_flip(rdev, 5);
3020 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3021 DRM_DEBUG("IH: D6 vblank\n");
3022 }
3023 break;
3024 case 1: /* D6 vline */
6f34be50
AD		 3025 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3026 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3027 DRM_DEBUG("IH: D6 vline\n");
3028 }
3029 break;
3030 default:
3031 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3032 break;
3033 }
3034 break;
3035 case 42: /* HPD hotplug */
3036 switch (src_data) {
3037 case 0:
6f34be50
AD		 3038 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3039 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3040 queue_hotplug = true;
3041 DRM_DEBUG("IH: HPD1\n");
3042 }
3043 break;
3044 case 1:
6f34be50
AD		 3045 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3046 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3047 queue_hotplug = true;
3048 DRM_DEBUG("IH: HPD2\n");
3049 }
3050 break;
3051 case 2:
6f34be50
AD		 3052 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3053 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3054 queue_hotplug = true;
3055 DRM_DEBUG("IH: HPD3\n");
3056 }
3057 break;
3058 case 3:
6f34be50
AD		 3059 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3060 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3061 queue_hotplug = true;
3062 DRM_DEBUG("IH: HPD4\n");
3063 }
3064 break;
3065 case 4:
6f34be50
AD		 3066 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3067 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3068 queue_hotplug = true;
3069 DRM_DEBUG("IH: HPD5\n");
3070 }
3071 break;
3072 case 5:
6f34be50
AD		 3073 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3074 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3075 queue_hotplug = true;
3076 DRM_DEBUG("IH: HPD6\n");
3077 }
3078 break;
3079 default:
3080 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3081 break;
3082 }
3083 break;
3084 case 176: /* CP_INT in ring buffer */
3085 case 177: /* CP_INT in IB1 */
3086 case 178: /* CP_INT in IB2 */
3087 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3088 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3089 break;
3090 case 181: /* CP EOP event */
3091 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3092 if (rdev->family >= CHIP_CAYMAN) {
3093 switch (src_data) {
3094 case 0:
3095 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3096 break;
3097 case 1:
3098 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3099 break;
3100 case 2:
3101 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3102 break;
3103 }
3104 } else
3105 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3106 break;
2031f77c 3107 case 233: /* GUI IDLE */
303c805c 3108 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 3109 rdev->pm.gui_idle = true;
3110 wake_up(&rdev->irq.idle_queue);
3111 break;
45f9a39b
AD		 3112 default:
3113 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3114 break;
3115 }
3116
3117 /* wptr/rptr are in bytes! */
3118 rptr += 16;
3119 rptr &= rdev->ih.ptr_mask;
3120 }
3121 /* make sure wptr hasn't changed while processing */
3122 wptr = evergreen_get_ih_wptr(rdev);
3123 if (wptr != rdev->ih.wptr)
3124 goto restart_ih;
3125 if (queue_hotplug)
32c87fca 3126 schedule_work(&rdev->hotplug_work);
45f9a39b
AD		 3127 rdev->ih.rptr = rptr;
3128 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3129 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3130 return IRQ_HANDLED;
3131}
3132
bcc1c2a1
AD		 3133static int evergreen_startup(struct radeon_device *rdev)
3134{
e32eb50d 3135 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
bcc1c2a1
AD		 3136 int r;
3137
9e46a48d 3138 /* enable pcie gen2 link */
cd54033a 3139 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3140
0af62b01
AD		 3141 if (ASIC_IS_DCE5(rdev)) {
3142 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3143 r = ni_init_microcode(rdev);
3144 if (r) {
3145 DRM_ERROR("Failed to load firmware!\n");
3146 return r;
3147 }
3148 }
755d819e 3149 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3150 if (r) {
0af62b01 3151 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3152 return r;
3153 }
0af62b01
AD		 3154 } else {
3155 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3156 r = r600_init_microcode(rdev);
3157 if (r) {
3158 DRM_ERROR("Failed to load firmware!\n");
3159 return r;
3160 }
3161 }
bcc1c2a1 3162 }
fe251e2f 3163
16cdf04d
AD		 3164 r = r600_vram_scratch_init(rdev);
3165 if (r)
3166 return r;
3167
bcc1c2a1 3168 evergreen_mc_program(rdev);
bcc1c2a1 3169 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3170 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3171 } else {
3172 r = evergreen_pcie_gart_enable(rdev);
3173 if (r)
3174 return r;
3175 }
bcc1c2a1 3176 evergreen_gpu_init(rdev);
bcc1c2a1 3177
d7ccd8fc 3178 r = evergreen_blit_init(rdev);
bcc1c2a1 3179 if (r) {
fb3d9e97 3180 r600_blit_fini(rdev);
d7ccd8fc
AD		 3181 rdev->asic->copy = NULL;
3182 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3183 }
3184
724c80e1
AD		 3185 /* allocate wb buffer */
3186 r = radeon_wb_init(rdev);
3187 if (r)
3188 return r;
3189
30eb77f4
JG		 3190 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3191 if (r) {
3192 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3193 return r;
3194 }
3195
bcc1c2a1
AD		 3196 /* Enable IRQ */
3197 r = r600_irq_init(rdev);
3198 if (r) {
3199 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3200 radeon_irq_kms_fini(rdev);
3201 return r;
3202 }
45f9a39b 3203 evergreen_irq_set(rdev);
bcc1c2a1 3204
e32eb50d 3205 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3206 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3207 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3208 if (r)
3209 return r;
3210 r = evergreen_cp_load_microcode(rdev);
3211 if (r)
3212 return r;
fe251e2f 3213 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 3214 if (r)
3215 return r;
fe251e2f 3216
b15ba512
JG		 3217 r = radeon_ib_pool_start(rdev);
3218 if (r)
3219 return r;
3220
3221 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
3222 if (r) {
3223 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3224 rdev->accel_working = false;
3fe89a0c 3225 return r;
7a7e8734
DA		 3226 }
3227
69d2ae57
RM		 3228 r = r600_audio_init(rdev);
3229 if (r) {
3230 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3231 return r;
3232 }
3233
bcc1c2a1
AD		 3234 return 0;
3235}
3236
3237int evergreen_resume(struct radeon_device *rdev)
3238{
3239 int r;
3240
86f5c9ed
AD		 3241 /* reset the asic, the gfx blocks are often in a bad state
3242 * after the driver is unloaded or after a resume
3243 */
3244 if (radeon_asic_reset(rdev))
3245 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3246 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3247 * posting will perform necessary task to bring back GPU into good
3248 * shape.
3249 */
3250 /* post card */
3251 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3252
b15ba512 3253 rdev->accel_working = true;
bcc1c2a1
AD		 3254 r = evergreen_startup(rdev);
3255 if (r) {
755d819e 3256 DRM_ERROR("evergreen startup failed on resume\n");
bcc1c2a1
AD		 3257 return r;
3258 }
fe251e2f 3259
bcc1c2a1
AD		 3260 return r;
3261
3262}
3263
3264int evergreen_suspend(struct radeon_device *rdev)
3265{
e32eb50d 3266 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3267
69d2ae57 3268 r600_audio_fini(rdev);
bcc1c2a1 3269 /* FIXME: we should wait for ring to be empty */
b15ba512
JG		 3270 radeon_ib_pool_suspend(rdev);
3271 r600_blit_suspend(rdev);
bcc1c2a1 3272 r700_cp_stop(rdev);
e32eb50d 3273 ring->ready = false;
45f9a39b 3274 evergreen_irq_suspend(rdev);
724c80e1 3275 radeon_wb_disable(rdev);
bcc1c2a1 3276 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3277
3278 return 0;
3279}
3280
bcc1c2a1
AD		 3281/* Plan is to move initialization in that function and use
3282 * helper function so that radeon_device_init pretty much
3283 * do nothing more than calling asic specific function. This
3284 * should also allow to remove a bunch of callback function
3285 * like vram_info.
3286 */
3287int evergreen_init(struct radeon_device *rdev)
3288{
3289 int r;
3290
bcc1c2a1
AD		 3291 /* This don't do much */
3292 r = radeon_gem_init(rdev);
3293 if (r)
3294 return r;
3295 /* Read BIOS */
3296 if (!radeon_get_bios(rdev)) {
3297 if (ASIC_IS_AVIVO(rdev))
3298 return -EINVAL;
3299 }
3300 /* Must be an ATOMBIOS */
3301 if (!rdev->is_atom_bios) {
755d819e 3302 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3303 return -EINVAL;
3304 }
3305 r = radeon_atombios_init(rdev);
3306 if (r)
3307 return r;
86f5c9ed
AD		 3308 /* reset the asic, the gfx blocks are often in a bad state
3309 * after the driver is unloaded or after a resume
3310 */
3311 if (radeon_asic_reset(rdev))
3312 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3313 /* Post card if necessary */
fd909c37 3314 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3315 if (!rdev->bios) {
3316 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3317 return -EINVAL;
3318 }
3319 DRM_INFO("GPU not posted. posting now...\n");
3320 atom_asic_init(rdev->mode_info.atom_context);
3321 }
3322 /* Initialize scratch registers */
3323 r600_scratch_init(rdev);
3324 /* Initialize surface registers */
3325 radeon_surface_init(rdev);
3326 /* Initialize clocks */
3327 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3328 /* Fence driver */
3329 r = radeon_fence_driver_init(rdev);
3330 if (r)
3331 return r;
d594e46a
JG		 3332 /* initialize AGP */
3333 if (rdev->flags & RADEON_IS_AGP) {
3334 r = radeon_agp_init(rdev);
3335 if (r)
3336 radeon_agp_disable(rdev);
3337 }
3338 /* initialize memory controller */
bcc1c2a1
AD		 3339 r = evergreen_mc_init(rdev);
3340 if (r)
3341 return r;
3342 /* Memory manager */
3343 r = radeon_bo_init(rdev);
3344 if (r)
3345 return r;
45f9a39b 3346
bcc1c2a1
AD		 3347 r = radeon_irq_kms_init(rdev);
3348 if (r)
3349 return r;
3350
e32eb50d
CK		 3351 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3352 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1
AD		 3353
3354 rdev->ih.ring_obj = NULL;
3355 r600_ih_ring_init(rdev, 64 * 1024);
3356
3357 r = r600_pcie_gart_init(rdev);
3358 if (r)
3359 return r;
0fcdb61e 3360
b15ba512 3361 r = radeon_ib_pool_init(rdev);
148a03bc 3362 rdev->accel_working = true;
b15ba512
JG		 3363 if (r) {
3364 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3365 rdev->accel_working = false;
3366 }
3367
bcc1c2a1
AD		 3368 r = evergreen_startup(rdev);
3369 if (r) {
fe251e2f
AD		 3370 dev_err(rdev->dev, "disabling GPU acceleration\n");
3371 r700_cp_fini(rdev);
fe251e2f 3372 r600_irq_fini(rdev);
724c80e1 3373 radeon_wb_fini(rdev);
b15ba512 3374 r100_ib_fini(rdev);
fe251e2f 3375 radeon_irq_kms_fini(rdev);
0fcdb61e 3376 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3377 rdev->accel_working = false;
3378 }
77e00f2e
AD		 3379
3380 /* Don't start up if the MC ucode is missing on BTC parts.
3381 * The default clocks and voltages before the MC ucode
3382 * is loaded are not suffient for advanced operations.
3383 */
3384 if (ASIC_IS_DCE5(rdev)) {
3385 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3386 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3387 return -EINVAL;
3388 }
3389 }
3390
bcc1c2a1
AD		 3391 return 0;
3392}
3393
3394void evergreen_fini(struct radeon_device *rdev)
3395{
69d2ae57 3396 r600_audio_fini(rdev);
fb3d9e97 3397 r600_blit_fini(rdev);
45f9a39b 3398 r700_cp_fini(rdev);
bcc1c2a1 3399 r600_irq_fini(rdev);
724c80e1 3400 radeon_wb_fini(rdev);
b15ba512 3401 r100_ib_fini(rdev);
bcc1c2a1 3402 radeon_irq_kms_fini(rdev);
bcc1c2a1 3403 evergreen_pcie_gart_fini(rdev);
16cdf04d 3404 r600_vram_scratch_fini(rdev);
bcc1c2a1 3405 radeon_gem_fini(rdev);
15d3332f 3406 radeon_semaphore_driver_fini(rdev);
bcc1c2a1 3407 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3408 radeon_agp_fini(rdev);
3409 radeon_bo_fini(rdev);
3410 radeon_atombios_fini(rdev);
3411 kfree(rdev->bios);
3412 rdev->bios = NULL;
bcc1c2a1 3413}
9e46a48d 3414
b07759bf 3415void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d
AD		 3416{
3417 u32 link_width_cntl, speed_cntl;
3418
d42dd579
AD		 3419 if (radeon_pcie_gen2 == 0)
3420 return;
3421
9e46a48d
AD		 3422 if (rdev->flags & RADEON_IS_IGP)
3423 return;
3424
3425 if (!(rdev->flags & RADEON_IS_PCIE))
3426 return;
3427
3428 /* x2 cards have a special sequence */
3429 if (ASIC_IS_X2(rdev))
3430 return;
3431
3432 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3433 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3434 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3435
3436 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3437 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3438 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3439
3440 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3441 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3442 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3443
3444 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3445 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3446 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3447
3448 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3449 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3450 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3451
3452 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3453 speed_cntl |= LC_GEN2_EN_STRAP;
3454 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3455
3456 } else {
3457 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3458 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3459 if (1)
3460 link_width_cntl |= LC_UPCONFIGURE_DIS;
3461 else
3462 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3463 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3464 }
3465}
Linux 6.x block layer and io_uring tree(s)