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drm/radeon: add support for ASPM on SI asics (v2)
[linux-2.6-block.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
760285e7 27#include <drm/drmP.h>
bcc1c2a1 28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
760285e7 30#include <drm/radeon_drm.h>
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
138e4e16 36#include "radeon_ucode.h"
fe251e2f 37
4a15903d
AD		 38static const u32 crtc_offsets[6] =
39{
40 EVERGREEN_CRTC0_REGISTER_OFFSET,
41 EVERGREEN_CRTC1_REGISTER_OFFSET,
42 EVERGREEN_CRTC2_REGISTER_OFFSET,
43 EVERGREEN_CRTC3_REGISTER_OFFSET,
44 EVERGREEN_CRTC4_REGISTER_OFFSET,
45 EVERGREEN_CRTC5_REGISTER_OFFSET
46};
47
2948f5e6
AD		 48#include "clearstate_evergreen.h"
49
50static u32 sumo_rlc_save_restore_register_list[] =
51{
52 0x98fc,
53 0x9830,
54 0x9834,
55 0x9838,
56 0x9870,
57 0x9874,
58 0x8a14,
59 0x8b24,
60 0x8bcc,
61 0x8b10,
62 0x8d00,
63 0x8d04,
64 0x8c00,
65 0x8c04,
66 0x8c08,
67 0x8c0c,
68 0x8d8c,
69 0x8c20,
70 0x8c24,
71 0x8c28,
72 0x8c18,
73 0x8c1c,
74 0x8cf0,
75 0x8e2c,
76 0x8e38,
77 0x8c30,
78 0x9508,
79 0x9688,
80 0x9608,
81 0x960c,
82 0x9610,
83 0x9614,
84 0x88c4,
85 0x88d4,
86 0xa008,
87 0x900c,
88 0x9100,
89 0x913c,
90 0x98f8,
91 0x98f4,
92 0x9b7c,
93 0x3f8c,
94 0x8950,
95 0x8954,
96 0x8a18,
97 0x8b28,
98 0x9144,
99 0x9148,
100 0x914c,
101 0x3f90,
102 0x3f94,
103 0x915c,
104 0x9160,
105 0x9178,
106 0x917c,
107 0x9180,
108 0x918c,
109 0x9190,
110 0x9194,
111 0x9198,
112 0x919c,
113 0x91a8,
114 0x91ac,
115 0x91b0,
116 0x91b4,
117 0x91b8,
118 0x91c4,
119 0x91c8,
120 0x91cc,
121 0x91d0,
122 0x91d4,
123 0x91e0,
124 0x91e4,
125 0x91ec,
126 0x91f0,
127 0x91f4,
128 0x9200,
129 0x9204,
130 0x929c,
131 0x9150,
132 0x802c,
133};
134static u32 sumo_rlc_save_restore_register_list_size = ARRAY_SIZE(sumo_rlc_save_restore_register_list);
135
bcc1c2a1
AD		 136static void evergreen_gpu_init(struct radeon_device *rdev);
137void evergreen_fini(struct radeon_device *rdev);
b07759bf 138void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
f52382d7 139void evergreen_program_aspm(struct radeon_device *rdev);
1b37078b
AD		 140extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
141 int ring, u32 cp_int_cntl);
bcc1c2a1 142
d4788db3
AD		 143static const u32 evergreen_golden_registers[] =
144{
145 0x3f90, 0xffff0000, 0xff000000,
146 0x9148, 0xffff0000, 0xff000000,
147 0x3f94, 0xffff0000, 0xff000000,
148 0x914c, 0xffff0000, 0xff000000,
149 0x9b7c, 0xffffffff, 0x00000000,
150 0x8a14, 0xffffffff, 0x00000007,
151 0x8b10, 0xffffffff, 0x00000000,
152 0x960c, 0xffffffff, 0x54763210,
153 0x88c4, 0xffffffff, 0x000000c2,
154 0x88d4, 0xffffffff, 0x00000010,
155 0x8974, 0xffffffff, 0x00000000,
156 0xc78, 0x00000080, 0x00000080,
157 0x5eb4, 0xffffffff, 0x00000002,
158 0x5e78, 0xffffffff, 0x001000f0,
159 0x6104, 0x01000300, 0x00000000,
160 0x5bc0, 0x00300000, 0x00000000,
161 0x7030, 0xffffffff, 0x00000011,
162 0x7c30, 0xffffffff, 0x00000011,
163 0x10830, 0xffffffff, 0x00000011,
164 0x11430, 0xffffffff, 0x00000011,
165 0x12030, 0xffffffff, 0x00000011,
166 0x12c30, 0xffffffff, 0x00000011,
167 0xd02c, 0xffffffff, 0x08421000,
168 0x240c, 0xffffffff, 0x00000380,
169 0x8b24, 0xffffffff, 0x00ff0fff,
170 0x28a4c, 0x06000000, 0x06000000,
171 0x10c, 0x00000001, 0x00000001,
172 0x8d00, 0xffffffff, 0x100e4848,
173 0x8d04, 0xffffffff, 0x00164745,
174 0x8c00, 0xffffffff, 0xe4000003,
175 0x8c04, 0xffffffff, 0x40600060,
176 0x8c08, 0xffffffff, 0x001c001c,
177 0x8cf0, 0xffffffff, 0x08e00620,
178 0x8c20, 0xffffffff, 0x00800080,
179 0x8c24, 0xffffffff, 0x00800080,
180 0x8c18, 0xffffffff, 0x20202078,
181 0x8c1c, 0xffffffff, 0x00001010,
182 0x28350, 0xffffffff, 0x00000000,
183 0xa008, 0xffffffff, 0x00010000,
184 0x5cc, 0xffffffff, 0x00000001,
185 0x9508, 0xffffffff, 0x00000002,
186 0x913c, 0x0000000f, 0x0000000a
187};
188
189static const u32 evergreen_golden_registers2[] =
190{
191 0x2f4c, 0xffffffff, 0x00000000,
192 0x54f4, 0xffffffff, 0x00000000,
193 0x54f0, 0xffffffff, 0x00000000,
194 0x5498, 0xffffffff, 0x00000000,
195 0x549c, 0xffffffff, 0x00000000,
196 0x5494, 0xffffffff, 0x00000000,
197 0x53cc, 0xffffffff, 0x00000000,
198 0x53c8, 0xffffffff, 0x00000000,
199 0x53c4, 0xffffffff, 0x00000000,
200 0x53c0, 0xffffffff, 0x00000000,
201 0x53bc, 0xffffffff, 0x00000000,
202 0x53b8, 0xffffffff, 0x00000000,
203 0x53b4, 0xffffffff, 0x00000000,
204 0x53b0, 0xffffffff, 0x00000000
205};
206
207static const u32 cypress_mgcg_init[] =
208{
209 0x802c, 0xffffffff, 0xc0000000,
210 0x5448, 0xffffffff, 0x00000100,
211 0x55e4, 0xffffffff, 0x00000100,
212 0x160c, 0xffffffff, 0x00000100,
213 0x5644, 0xffffffff, 0x00000100,
214 0xc164, 0xffffffff, 0x00000100,
215 0x8a18, 0xffffffff, 0x00000100,
216 0x897c, 0xffffffff, 0x06000100,
217 0x8b28, 0xffffffff, 0x00000100,
218 0x9144, 0xffffffff, 0x00000100,
219 0x9a60, 0xffffffff, 0x00000100,
220 0x9868, 0xffffffff, 0x00000100,
221 0x8d58, 0xffffffff, 0x00000100,
222 0x9510, 0xffffffff, 0x00000100,
223 0x949c, 0xffffffff, 0x00000100,
224 0x9654, 0xffffffff, 0x00000100,
225 0x9030, 0xffffffff, 0x00000100,
226 0x9034, 0xffffffff, 0x00000100,
227 0x9038, 0xffffffff, 0x00000100,
228 0x903c, 0xffffffff, 0x00000100,
229 0x9040, 0xffffffff, 0x00000100,
230 0xa200, 0xffffffff, 0x00000100,
231 0xa204, 0xffffffff, 0x00000100,
232 0xa208, 0xffffffff, 0x00000100,
233 0xa20c, 0xffffffff, 0x00000100,
234 0x971c, 0xffffffff, 0x00000100,
235 0x977c, 0xffffffff, 0x00000100,
236 0x3f80, 0xffffffff, 0x00000100,
237 0xa210, 0xffffffff, 0x00000100,
238 0xa214, 0xffffffff, 0x00000100,
239 0x4d8, 0xffffffff, 0x00000100,
240 0x9784, 0xffffffff, 0x00000100,
241 0x9698, 0xffffffff, 0x00000100,
242 0x4d4, 0xffffffff, 0x00000200,
243 0x30cc, 0xffffffff, 0x00000100,
244 0xd0c0, 0xffffffff, 0xff000100,
245 0x802c, 0xffffffff, 0x40000000,
246 0x915c, 0xffffffff, 0x00010000,
247 0x9160, 0xffffffff, 0x00030002,
248 0x9178, 0xffffffff, 0x00070000,
249 0x917c, 0xffffffff, 0x00030002,
250 0x9180, 0xffffffff, 0x00050004,
251 0x918c, 0xffffffff, 0x00010006,
252 0x9190, 0xffffffff, 0x00090008,
253 0x9194, 0xffffffff, 0x00070000,
254 0x9198, 0xffffffff, 0x00030002,
255 0x919c, 0xffffffff, 0x00050004,
256 0x91a8, 0xffffffff, 0x00010006,
257 0x91ac, 0xffffffff, 0x00090008,
258 0x91b0, 0xffffffff, 0x00070000,
259 0x91b4, 0xffffffff, 0x00030002,
260 0x91b8, 0xffffffff, 0x00050004,
261 0x91c4, 0xffffffff, 0x00010006,
262 0x91c8, 0xffffffff, 0x00090008,
263 0x91cc, 0xffffffff, 0x00070000,
264 0x91d0, 0xffffffff, 0x00030002,
265 0x91d4, 0xffffffff, 0x00050004,
266 0x91e0, 0xffffffff, 0x00010006,
267 0x91e4, 0xffffffff, 0x00090008,
268 0x91e8, 0xffffffff, 0x00000000,
269 0x91ec, 0xffffffff, 0x00070000,
270 0x91f0, 0xffffffff, 0x00030002,
271 0x91f4, 0xffffffff, 0x00050004,
272 0x9200, 0xffffffff, 0x00010006,
273 0x9204, 0xffffffff, 0x00090008,
274 0x9208, 0xffffffff, 0x00070000,
275 0x920c, 0xffffffff, 0x00030002,
276 0x9210, 0xffffffff, 0x00050004,
277 0x921c, 0xffffffff, 0x00010006,
278 0x9220, 0xffffffff, 0x00090008,
279 0x9224, 0xffffffff, 0x00070000,
280 0x9228, 0xffffffff, 0x00030002,
281 0x922c, 0xffffffff, 0x00050004,
282 0x9238, 0xffffffff, 0x00010006,
283 0x923c, 0xffffffff, 0x00090008,
284 0x9240, 0xffffffff, 0x00070000,
285 0x9244, 0xffffffff, 0x00030002,
286 0x9248, 0xffffffff, 0x00050004,
287 0x9254, 0xffffffff, 0x00010006,
288 0x9258, 0xffffffff, 0x00090008,
289 0x925c, 0xffffffff, 0x00070000,
290 0x9260, 0xffffffff, 0x00030002,
291 0x9264, 0xffffffff, 0x00050004,
292 0x9270, 0xffffffff, 0x00010006,
293 0x9274, 0xffffffff, 0x00090008,
294 0x9278, 0xffffffff, 0x00070000,
295 0x927c, 0xffffffff, 0x00030002,
296 0x9280, 0xffffffff, 0x00050004,
297 0x928c, 0xffffffff, 0x00010006,
298 0x9290, 0xffffffff, 0x00090008,
299 0x9294, 0xffffffff, 0x00000000,
300 0x929c, 0xffffffff, 0x00000001,
301 0x802c, 0xffffffff, 0x40010000,
302 0x915c, 0xffffffff, 0x00010000,
303 0x9160, 0xffffffff, 0x00030002,
304 0x9178, 0xffffffff, 0x00070000,
305 0x917c, 0xffffffff, 0x00030002,
306 0x9180, 0xffffffff, 0x00050004,
307 0x918c, 0xffffffff, 0x00010006,
308 0x9190, 0xffffffff, 0x00090008,
309 0x9194, 0xffffffff, 0x00070000,
310 0x9198, 0xffffffff, 0x00030002,
311 0x919c, 0xffffffff, 0x00050004,
312 0x91a8, 0xffffffff, 0x00010006,
313 0x91ac, 0xffffffff, 0x00090008,
314 0x91b0, 0xffffffff, 0x00070000,
315 0x91b4, 0xffffffff, 0x00030002,
316 0x91b8, 0xffffffff, 0x00050004,
317 0x91c4, 0xffffffff, 0x00010006,
318 0x91c8, 0xffffffff, 0x00090008,
319 0x91cc, 0xffffffff, 0x00070000,
320 0x91d0, 0xffffffff, 0x00030002,
321 0x91d4, 0xffffffff, 0x00050004,
322 0x91e0, 0xffffffff, 0x00010006,
323 0x91e4, 0xffffffff, 0x00090008,
324 0x91e8, 0xffffffff, 0x00000000,
325 0x91ec, 0xffffffff, 0x00070000,
326 0x91f0, 0xffffffff, 0x00030002,
327 0x91f4, 0xffffffff, 0x00050004,
328 0x9200, 0xffffffff, 0x00010006,
329 0x9204, 0xffffffff, 0x00090008,
330 0x9208, 0xffffffff, 0x00070000,
331 0x920c, 0xffffffff, 0x00030002,
332 0x9210, 0xffffffff, 0x00050004,
333 0x921c, 0xffffffff, 0x00010006,
334 0x9220, 0xffffffff, 0x00090008,
335 0x9224, 0xffffffff, 0x00070000,
336 0x9228, 0xffffffff, 0x00030002,
337 0x922c, 0xffffffff, 0x00050004,
338 0x9238, 0xffffffff, 0x00010006,
339 0x923c, 0xffffffff, 0x00090008,
340 0x9240, 0xffffffff, 0x00070000,
341 0x9244, 0xffffffff, 0x00030002,
342 0x9248, 0xffffffff, 0x00050004,
343 0x9254, 0xffffffff, 0x00010006,
344 0x9258, 0xffffffff, 0x00090008,
345 0x925c, 0xffffffff, 0x00070000,
346 0x9260, 0xffffffff, 0x00030002,
347 0x9264, 0xffffffff, 0x00050004,
348 0x9270, 0xffffffff, 0x00010006,
349 0x9274, 0xffffffff, 0x00090008,
350 0x9278, 0xffffffff, 0x00070000,
351 0x927c, 0xffffffff, 0x00030002,
352 0x9280, 0xffffffff, 0x00050004,
353 0x928c, 0xffffffff, 0x00010006,
354 0x9290, 0xffffffff, 0x00090008,
355 0x9294, 0xffffffff, 0x00000000,
356 0x929c, 0xffffffff, 0x00000001,
357 0x802c, 0xffffffff, 0xc0000000
358};
359
360static const u32 redwood_mgcg_init[] =
361{
362 0x802c, 0xffffffff, 0xc0000000,
363 0x5448, 0xffffffff, 0x00000100,
364 0x55e4, 0xffffffff, 0x00000100,
365 0x160c, 0xffffffff, 0x00000100,
366 0x5644, 0xffffffff, 0x00000100,
367 0xc164, 0xffffffff, 0x00000100,
368 0x8a18, 0xffffffff, 0x00000100,
369 0x897c, 0xffffffff, 0x06000100,
370 0x8b28, 0xffffffff, 0x00000100,
371 0x9144, 0xffffffff, 0x00000100,
372 0x9a60, 0xffffffff, 0x00000100,
373 0x9868, 0xffffffff, 0x00000100,
374 0x8d58, 0xffffffff, 0x00000100,
375 0x9510, 0xffffffff, 0x00000100,
376 0x949c, 0xffffffff, 0x00000100,
377 0x9654, 0xffffffff, 0x00000100,
378 0x9030, 0xffffffff, 0x00000100,
379 0x9034, 0xffffffff, 0x00000100,
380 0x9038, 0xffffffff, 0x00000100,
381 0x903c, 0xffffffff, 0x00000100,
382 0x9040, 0xffffffff, 0x00000100,
383 0xa200, 0xffffffff, 0x00000100,
384 0xa204, 0xffffffff, 0x00000100,
385 0xa208, 0xffffffff, 0x00000100,
386 0xa20c, 0xffffffff, 0x00000100,
387 0x971c, 0xffffffff, 0x00000100,
388 0x977c, 0xffffffff, 0x00000100,
389 0x3f80, 0xffffffff, 0x00000100,
390 0xa210, 0xffffffff, 0x00000100,
391 0xa214, 0xffffffff, 0x00000100,
392 0x4d8, 0xffffffff, 0x00000100,
393 0x9784, 0xffffffff, 0x00000100,
394 0x9698, 0xffffffff, 0x00000100,
395 0x4d4, 0xffffffff, 0x00000200,
396 0x30cc, 0xffffffff, 0x00000100,
397 0xd0c0, 0xffffffff, 0xff000100,
398 0x802c, 0xffffffff, 0x40000000,
399 0x915c, 0xffffffff, 0x00010000,
400 0x9160, 0xffffffff, 0x00030002,
401 0x9178, 0xffffffff, 0x00070000,
402 0x917c, 0xffffffff, 0x00030002,
403 0x9180, 0xffffffff, 0x00050004,
404 0x918c, 0xffffffff, 0x00010006,
405 0x9190, 0xffffffff, 0x00090008,
406 0x9194, 0xffffffff, 0x00070000,
407 0x9198, 0xffffffff, 0x00030002,
408 0x919c, 0xffffffff, 0x00050004,
409 0x91a8, 0xffffffff, 0x00010006,
410 0x91ac, 0xffffffff, 0x00090008,
411 0x91b0, 0xffffffff, 0x00070000,
412 0x91b4, 0xffffffff, 0x00030002,
413 0x91b8, 0xffffffff, 0x00050004,
414 0x91c4, 0xffffffff, 0x00010006,
415 0x91c8, 0xffffffff, 0x00090008,
416 0x91cc, 0xffffffff, 0x00070000,
417 0x91d0, 0xffffffff, 0x00030002,
418 0x91d4, 0xffffffff, 0x00050004,
419 0x91e0, 0xffffffff, 0x00010006,
420 0x91e4, 0xffffffff, 0x00090008,
421 0x91e8, 0xffffffff, 0x00000000,
422 0x91ec, 0xffffffff, 0x00070000,
423 0x91f0, 0xffffffff, 0x00030002,
424 0x91f4, 0xffffffff, 0x00050004,
425 0x9200, 0xffffffff, 0x00010006,
426 0x9204, 0xffffffff, 0x00090008,
427 0x9294, 0xffffffff, 0x00000000,
428 0x929c, 0xffffffff, 0x00000001,
429 0x802c, 0xffffffff, 0xc0000000
430};
431
432static const u32 cedar_golden_registers[] =
433{
434 0x3f90, 0xffff0000, 0xff000000,
435 0x9148, 0xffff0000, 0xff000000,
436 0x3f94, 0xffff0000, 0xff000000,
437 0x914c, 0xffff0000, 0xff000000,
438 0x9b7c, 0xffffffff, 0x00000000,
439 0x8a14, 0xffffffff, 0x00000007,
440 0x8b10, 0xffffffff, 0x00000000,
441 0x960c, 0xffffffff, 0x54763210,
442 0x88c4, 0xffffffff, 0x000000c2,
443 0x88d4, 0xffffffff, 0x00000000,
444 0x8974, 0xffffffff, 0x00000000,
445 0xc78, 0x00000080, 0x00000080,
446 0x5eb4, 0xffffffff, 0x00000002,
447 0x5e78, 0xffffffff, 0x001000f0,
448 0x6104, 0x01000300, 0x00000000,
449 0x5bc0, 0x00300000, 0x00000000,
450 0x7030, 0xffffffff, 0x00000011,
451 0x7c30, 0xffffffff, 0x00000011,
452 0x10830, 0xffffffff, 0x00000011,
453 0x11430, 0xffffffff, 0x00000011,
454 0xd02c, 0xffffffff, 0x08421000,
455 0x240c, 0xffffffff, 0x00000380,
456 0x8b24, 0xffffffff, 0x00ff0fff,
457 0x28a4c, 0x06000000, 0x06000000,
458 0x10c, 0x00000001, 0x00000001,
459 0x8d00, 0xffffffff, 0x100e4848,
460 0x8d04, 0xffffffff, 0x00164745,
461 0x8c00, 0xffffffff, 0xe4000003,
462 0x8c04, 0xffffffff, 0x40600060,
463 0x8c08, 0xffffffff, 0x001c001c,
464 0x8cf0, 0xffffffff, 0x08e00410,
465 0x8c20, 0xffffffff, 0x00800080,
466 0x8c24, 0xffffffff, 0x00800080,
467 0x8c18, 0xffffffff, 0x20202078,
468 0x8c1c, 0xffffffff, 0x00001010,
469 0x28350, 0xffffffff, 0x00000000,
470 0xa008, 0xffffffff, 0x00010000,
471 0x5cc, 0xffffffff, 0x00000001,
472 0x9508, 0xffffffff, 0x00000002
473};
474
475static const u32 cedar_mgcg_init[] =
476{
477 0x802c, 0xffffffff, 0xc0000000,
478 0x5448, 0xffffffff, 0x00000100,
479 0x55e4, 0xffffffff, 0x00000100,
480 0x160c, 0xffffffff, 0x00000100,
481 0x5644, 0xffffffff, 0x00000100,
482 0xc164, 0xffffffff, 0x00000100,
483 0x8a18, 0xffffffff, 0x00000100,
484 0x897c, 0xffffffff, 0x06000100,
485 0x8b28, 0xffffffff, 0x00000100,
486 0x9144, 0xffffffff, 0x00000100,
487 0x9a60, 0xffffffff, 0x00000100,
488 0x9868, 0xffffffff, 0x00000100,
489 0x8d58, 0xffffffff, 0x00000100,
490 0x9510, 0xffffffff, 0x00000100,
491 0x949c, 0xffffffff, 0x00000100,
492 0x9654, 0xffffffff, 0x00000100,
493 0x9030, 0xffffffff, 0x00000100,
494 0x9034, 0xffffffff, 0x00000100,
495 0x9038, 0xffffffff, 0x00000100,
496 0x903c, 0xffffffff, 0x00000100,
497 0x9040, 0xffffffff, 0x00000100,
498 0xa200, 0xffffffff, 0x00000100,
499 0xa204, 0xffffffff, 0x00000100,
500 0xa208, 0xffffffff, 0x00000100,
501 0xa20c, 0xffffffff, 0x00000100,
502 0x971c, 0xffffffff, 0x00000100,
503 0x977c, 0xffffffff, 0x00000100,
504 0x3f80, 0xffffffff, 0x00000100,
505 0xa210, 0xffffffff, 0x00000100,
506 0xa214, 0xffffffff, 0x00000100,
507 0x4d8, 0xffffffff, 0x00000100,
508 0x9784, 0xffffffff, 0x00000100,
509 0x9698, 0xffffffff, 0x00000100,
510 0x4d4, 0xffffffff, 0x00000200,
511 0x30cc, 0xffffffff, 0x00000100,
512 0xd0c0, 0xffffffff, 0xff000100,
513 0x802c, 0xffffffff, 0x40000000,
514 0x915c, 0xffffffff, 0x00010000,
515 0x9178, 0xffffffff, 0x00050000,
516 0x917c, 0xffffffff, 0x00030002,
517 0x918c, 0xffffffff, 0x00010004,
518 0x9190, 0xffffffff, 0x00070006,
519 0x9194, 0xffffffff, 0x00050000,
520 0x9198, 0xffffffff, 0x00030002,
521 0x91a8, 0xffffffff, 0x00010004,
522 0x91ac, 0xffffffff, 0x00070006,
523 0x91e8, 0xffffffff, 0x00000000,
524 0x9294, 0xffffffff, 0x00000000,
525 0x929c, 0xffffffff, 0x00000001,
526 0x802c, 0xffffffff, 0xc0000000
527};
528
529static const u32 juniper_mgcg_init[] =
530{
531 0x802c, 0xffffffff, 0xc0000000,
532 0x5448, 0xffffffff, 0x00000100,
533 0x55e4, 0xffffffff, 0x00000100,
534 0x160c, 0xffffffff, 0x00000100,
535 0x5644, 0xffffffff, 0x00000100,
536 0xc164, 0xffffffff, 0x00000100,
537 0x8a18, 0xffffffff, 0x00000100,
538 0x897c, 0xffffffff, 0x06000100,
539 0x8b28, 0xffffffff, 0x00000100,
540 0x9144, 0xffffffff, 0x00000100,
541 0x9a60, 0xffffffff, 0x00000100,
542 0x9868, 0xffffffff, 0x00000100,
543 0x8d58, 0xffffffff, 0x00000100,
544 0x9510, 0xffffffff, 0x00000100,
545 0x949c, 0xffffffff, 0x00000100,
546 0x9654, 0xffffffff, 0x00000100,
547 0x9030, 0xffffffff, 0x00000100,
548 0x9034, 0xffffffff, 0x00000100,
549 0x9038, 0xffffffff, 0x00000100,
550 0x903c, 0xffffffff, 0x00000100,
551 0x9040, 0xffffffff, 0x00000100,
552 0xa200, 0xffffffff, 0x00000100,
553 0xa204, 0xffffffff, 0x00000100,
554 0xa208, 0xffffffff, 0x00000100,
555 0xa20c, 0xffffffff, 0x00000100,
556 0x971c, 0xffffffff, 0x00000100,
557 0xd0c0, 0xffffffff, 0xff000100,
558 0x802c, 0xffffffff, 0x40000000,
559 0x915c, 0xffffffff, 0x00010000,
560 0x9160, 0xffffffff, 0x00030002,
561 0x9178, 0xffffffff, 0x00070000,
562 0x917c, 0xffffffff, 0x00030002,
563 0x9180, 0xffffffff, 0x00050004,
564 0x918c, 0xffffffff, 0x00010006,
565 0x9190, 0xffffffff, 0x00090008,
566 0x9194, 0xffffffff, 0x00070000,
567 0x9198, 0xffffffff, 0x00030002,
568 0x919c, 0xffffffff, 0x00050004,
569 0x91a8, 0xffffffff, 0x00010006,
570 0x91ac, 0xffffffff, 0x00090008,
571 0x91b0, 0xffffffff, 0x00070000,
572 0x91b4, 0xffffffff, 0x00030002,
573 0x91b8, 0xffffffff, 0x00050004,
574 0x91c4, 0xffffffff, 0x00010006,
575 0x91c8, 0xffffffff, 0x00090008,
576 0x91cc, 0xffffffff, 0x00070000,
577 0x91d0, 0xffffffff, 0x00030002,
578 0x91d4, 0xffffffff, 0x00050004,
579 0x91e0, 0xffffffff, 0x00010006,
580 0x91e4, 0xffffffff, 0x00090008,
581 0x91e8, 0xffffffff, 0x00000000,
582 0x91ec, 0xffffffff, 0x00070000,
583 0x91f0, 0xffffffff, 0x00030002,
584 0x91f4, 0xffffffff, 0x00050004,
585 0x9200, 0xffffffff, 0x00010006,
586 0x9204, 0xffffffff, 0x00090008,
587 0x9208, 0xffffffff, 0x00070000,
588 0x920c, 0xffffffff, 0x00030002,
589 0x9210, 0xffffffff, 0x00050004,
590 0x921c, 0xffffffff, 0x00010006,
591 0x9220, 0xffffffff, 0x00090008,
592 0x9224, 0xffffffff, 0x00070000,
593 0x9228, 0xffffffff, 0x00030002,
594 0x922c, 0xffffffff, 0x00050004,
595 0x9238, 0xffffffff, 0x00010006,
596 0x923c, 0xffffffff, 0x00090008,
597 0x9240, 0xffffffff, 0x00070000,
598 0x9244, 0xffffffff, 0x00030002,
599 0x9248, 0xffffffff, 0x00050004,
600 0x9254, 0xffffffff, 0x00010006,
601 0x9258, 0xffffffff, 0x00090008,
602 0x925c, 0xffffffff, 0x00070000,
603 0x9260, 0xffffffff, 0x00030002,
604 0x9264, 0xffffffff, 0x00050004,
605 0x9270, 0xffffffff, 0x00010006,
606 0x9274, 0xffffffff, 0x00090008,
607 0x9278, 0xffffffff, 0x00070000,
608 0x927c, 0xffffffff, 0x00030002,
609 0x9280, 0xffffffff, 0x00050004,
610 0x928c, 0xffffffff, 0x00010006,
611 0x9290, 0xffffffff, 0x00090008,
612 0x9294, 0xffffffff, 0x00000000,
613 0x929c, 0xffffffff, 0x00000001,
614 0x802c, 0xffffffff, 0xc0000000,
615 0x977c, 0xffffffff, 0x00000100,
616 0x3f80, 0xffffffff, 0x00000100,
617 0xa210, 0xffffffff, 0x00000100,
618 0xa214, 0xffffffff, 0x00000100,
619 0x4d8, 0xffffffff, 0x00000100,
620 0x9784, 0xffffffff, 0x00000100,
621 0x9698, 0xffffffff, 0x00000100,
622 0x4d4, 0xffffffff, 0x00000200,
623 0x30cc, 0xffffffff, 0x00000100,
624 0x802c, 0xffffffff, 0xc0000000
625};
626
627static const u32 supersumo_golden_registers[] =
628{
629 0x5eb4, 0xffffffff, 0x00000002,
630 0x5cc, 0xffffffff, 0x00000001,
631 0x7030, 0xffffffff, 0x00000011,
632 0x7c30, 0xffffffff, 0x00000011,
633 0x6104, 0x01000300, 0x00000000,
634 0x5bc0, 0x00300000, 0x00000000,
635 0x8c04, 0xffffffff, 0x40600060,
636 0x8c08, 0xffffffff, 0x001c001c,
637 0x8c20, 0xffffffff, 0x00800080,
638 0x8c24, 0xffffffff, 0x00800080,
639 0x8c18, 0xffffffff, 0x20202078,
640 0x8c1c, 0xffffffff, 0x00001010,
641 0x918c, 0xffffffff, 0x00010006,
642 0x91a8, 0xffffffff, 0x00010006,
643 0x91c4, 0xffffffff, 0x00010006,
644 0x91e0, 0xffffffff, 0x00010006,
645 0x9200, 0xffffffff, 0x00010006,
646 0x9150, 0xffffffff, 0x6e944040,
647 0x917c, 0xffffffff, 0x00030002,
648 0x9180, 0xffffffff, 0x00050004,
649 0x9198, 0xffffffff, 0x00030002,
650 0x919c, 0xffffffff, 0x00050004,
651 0x91b4, 0xffffffff, 0x00030002,
652 0x91b8, 0xffffffff, 0x00050004,
653 0x91d0, 0xffffffff, 0x00030002,
654 0x91d4, 0xffffffff, 0x00050004,
655 0x91f0, 0xffffffff, 0x00030002,
656 0x91f4, 0xffffffff, 0x00050004,
657 0x915c, 0xffffffff, 0x00010000,
658 0x9160, 0xffffffff, 0x00030002,
659 0x3f90, 0xffff0000, 0xff000000,
660 0x9178, 0xffffffff, 0x00070000,
661 0x9194, 0xffffffff, 0x00070000,
662 0x91b0, 0xffffffff, 0x00070000,
663 0x91cc, 0xffffffff, 0x00070000,
664 0x91ec, 0xffffffff, 0x00070000,
665 0x9148, 0xffff0000, 0xff000000,
666 0x9190, 0xffffffff, 0x00090008,
667 0x91ac, 0xffffffff, 0x00090008,
668 0x91c8, 0xffffffff, 0x00090008,
669 0x91e4, 0xffffffff, 0x00090008,
670 0x9204, 0xffffffff, 0x00090008,
671 0x3f94, 0xffff0000, 0xff000000,
672 0x914c, 0xffff0000, 0xff000000,
673 0x929c, 0xffffffff, 0x00000001,
674 0x8a18, 0xffffffff, 0x00000100,
675 0x8b28, 0xffffffff, 0x00000100,
676 0x9144, 0xffffffff, 0x00000100,
677 0x5644, 0xffffffff, 0x00000100,
678 0x9b7c, 0xffffffff, 0x00000000,
679 0x8030, 0xffffffff, 0x0000100a,
680 0x8a14, 0xffffffff, 0x00000007,
681 0x8b24, 0xffffffff, 0x00ff0fff,
682 0x8b10, 0xffffffff, 0x00000000,
683 0x28a4c, 0x06000000, 0x06000000,
684 0x4d8, 0xffffffff, 0x00000100,
685 0x913c, 0xffff000f, 0x0100000a,
686 0x960c, 0xffffffff, 0x54763210,
687 0x88c4, 0xffffffff, 0x000000c2,
688 0x88d4, 0xffffffff, 0x00000010,
689 0x8974, 0xffffffff, 0x00000000,
690 0xc78, 0x00000080, 0x00000080,
691 0x5e78, 0xffffffff, 0x001000f0,
692 0xd02c, 0xffffffff, 0x08421000,
693 0xa008, 0xffffffff, 0x00010000,
694 0x8d00, 0xffffffff, 0x100e4848,
695 0x8d04, 0xffffffff, 0x00164745,
696 0x8c00, 0xffffffff, 0xe4000003,
697 0x8cf0, 0x1fffffff, 0x08e00620,
698 0x28350, 0xffffffff, 0x00000000,
699 0x9508, 0xffffffff, 0x00000002
700};
701
702static const u32 sumo_golden_registers[] =
703{
704 0x900c, 0x00ffffff, 0x0017071f,
705 0x8c18, 0xffffffff, 0x10101060,
706 0x8c1c, 0xffffffff, 0x00001010,
707 0x8c30, 0x0000000f, 0x00000005,
708 0x9688, 0x0000000f, 0x00000007
709};
710
711static const u32 wrestler_golden_registers[] =
712{
713 0x5eb4, 0xffffffff, 0x00000002,
714 0x5cc, 0xffffffff, 0x00000001,
715 0x7030, 0xffffffff, 0x00000011,
716 0x7c30, 0xffffffff, 0x00000011,
717 0x6104, 0x01000300, 0x00000000,
718 0x5bc0, 0x00300000, 0x00000000,
719 0x918c, 0xffffffff, 0x00010006,
720 0x91a8, 0xffffffff, 0x00010006,
721 0x9150, 0xffffffff, 0x6e944040,
722 0x917c, 0xffffffff, 0x00030002,
723 0x9198, 0xffffffff, 0x00030002,
724 0x915c, 0xffffffff, 0x00010000,
725 0x3f90, 0xffff0000, 0xff000000,
726 0x9178, 0xffffffff, 0x00070000,
727 0x9194, 0xffffffff, 0x00070000,
728 0x9148, 0xffff0000, 0xff000000,
729 0x9190, 0xffffffff, 0x00090008,
730 0x91ac, 0xffffffff, 0x00090008,
731 0x3f94, 0xffff0000, 0xff000000,
732 0x914c, 0xffff0000, 0xff000000,
733 0x929c, 0xffffffff, 0x00000001,
734 0x8a18, 0xffffffff, 0x00000100,
735 0x8b28, 0xffffffff, 0x00000100,
736 0x9144, 0xffffffff, 0x00000100,
737 0x9b7c, 0xffffffff, 0x00000000,
738 0x8030, 0xffffffff, 0x0000100a,
739 0x8a14, 0xffffffff, 0x00000001,
740 0x8b24, 0xffffffff, 0x00ff0fff,
741 0x8b10, 0xffffffff, 0x00000000,
742 0x28a4c, 0x06000000, 0x06000000,
743 0x4d8, 0xffffffff, 0x00000100,
744 0x913c, 0xffff000f, 0x0100000a,
745 0x960c, 0xffffffff, 0x54763210,
746 0x88c4, 0xffffffff, 0x000000c2,
747 0x88d4, 0xffffffff, 0x00000010,
748 0x8974, 0xffffffff, 0x00000000,
749 0xc78, 0x00000080, 0x00000080,
750 0x5e78, 0xffffffff, 0x001000f0,
751 0xd02c, 0xffffffff, 0x08421000,
752 0xa008, 0xffffffff, 0x00010000,
753 0x8d00, 0xffffffff, 0x100e4848,
754 0x8d04, 0xffffffff, 0x00164745,
755 0x8c00, 0xffffffff, 0xe4000003,
756 0x8cf0, 0x1fffffff, 0x08e00410,
757 0x28350, 0xffffffff, 0x00000000,
758 0x9508, 0xffffffff, 0x00000002,
759 0x900c, 0xffffffff, 0x0017071f,
760 0x8c18, 0xffffffff, 0x10101060,
761 0x8c1c, 0xffffffff, 0x00001010
762};
763
764static const u32 barts_golden_registers[] =
765{
766 0x5eb4, 0xffffffff, 0x00000002,
767 0x5e78, 0x8f311ff1, 0x001000f0,
768 0x3f90, 0xffff0000, 0xff000000,
769 0x9148, 0xffff0000, 0xff000000,
770 0x3f94, 0xffff0000, 0xff000000,
771 0x914c, 0xffff0000, 0xff000000,
772 0xc78, 0x00000080, 0x00000080,
773 0xbd4, 0x70073777, 0x00010001,
774 0xd02c, 0xbfffff1f, 0x08421000,
775 0xd0b8, 0x03773777, 0x02011003,
776 0x5bc0, 0x00200000, 0x50100000,
777 0x98f8, 0x33773777, 0x02011003,
778 0x98fc, 0xffffffff, 0x76543210,
779 0x7030, 0x31000311, 0x00000011,
780 0x2f48, 0x00000007, 0x02011003,
781 0x6b28, 0x00000010, 0x00000012,
782 0x7728, 0x00000010, 0x00000012,
783 0x10328, 0x00000010, 0x00000012,
784 0x10f28, 0x00000010, 0x00000012,
785 0x11b28, 0x00000010, 0x00000012,
786 0x12728, 0x00000010, 0x00000012,
787 0x240c, 0x000007ff, 0x00000380,
788 0x8a14, 0xf000001f, 0x00000007,
789 0x8b24, 0x3fff3fff, 0x00ff0fff,
790 0x8b10, 0x0000ff0f, 0x00000000,
791 0x28a4c, 0x07ffffff, 0x06000000,
792 0x10c, 0x00000001, 0x00010003,
793 0xa02c, 0xffffffff, 0x0000009b,
794 0x913c, 0x0000000f, 0x0100000a,
795 0x8d00, 0xffff7f7f, 0x100e4848,
796 0x8d04, 0x00ffffff, 0x00164745,
797 0x8c00, 0xfffc0003, 0xe4000003,
798 0x8c04, 0xf8ff00ff, 0x40600060,
799 0x8c08, 0x00ff00ff, 0x001c001c,
800 0x8cf0, 0x1fff1fff, 0x08e00620,
801 0x8c20, 0x0fff0fff, 0x00800080,
802 0x8c24, 0x0fff0fff, 0x00800080,
803 0x8c18, 0xffffffff, 0x20202078,
804 0x8c1c, 0x0000ffff, 0x00001010,
805 0x28350, 0x00000f01, 0x00000000,
806 0x9508, 0x3700001f, 0x00000002,
807 0x960c, 0xffffffff, 0x54763210,
808 0x88c4, 0x001f3ae3, 0x000000c2,
809 0x88d4, 0x0000001f, 0x00000010,
810 0x8974, 0xffffffff, 0x00000000
811};
812
813static const u32 turks_golden_registers[] =
814{
815 0x5eb4, 0xffffffff, 0x00000002,
816 0x5e78, 0x8f311ff1, 0x001000f0,
817 0x8c8, 0x00003000, 0x00001070,
818 0x8cc, 0x000fffff, 0x00040035,
819 0x3f90, 0xffff0000, 0xfff00000,
820 0x9148, 0xffff0000, 0xfff00000,
821 0x3f94, 0xffff0000, 0xfff00000,
822 0x914c, 0xffff0000, 0xfff00000,
823 0xc78, 0x00000080, 0x00000080,
824 0xbd4, 0x00073007, 0x00010002,
825 0xd02c, 0xbfffff1f, 0x08421000,
826 0xd0b8, 0x03773777, 0x02010002,
827 0x5bc0, 0x00200000, 0x50100000,
828 0x98f8, 0x33773777, 0x00010002,
829 0x98fc, 0xffffffff, 0x33221100,
830 0x7030, 0x31000311, 0x00000011,
831 0x2f48, 0x33773777, 0x00010002,
832 0x6b28, 0x00000010, 0x00000012,
833 0x7728, 0x00000010, 0x00000012,
834 0x10328, 0x00000010, 0x00000012,
835 0x10f28, 0x00000010, 0x00000012,
836 0x11b28, 0x00000010, 0x00000012,
837 0x12728, 0x00000010, 0x00000012,
838 0x240c, 0x000007ff, 0x00000380,
839 0x8a14, 0xf000001f, 0x00000007,
840 0x8b24, 0x3fff3fff, 0x00ff0fff,
841 0x8b10, 0x0000ff0f, 0x00000000,
842 0x28a4c, 0x07ffffff, 0x06000000,
843 0x10c, 0x00000001, 0x00010003,
844 0xa02c, 0xffffffff, 0x0000009b,
845 0x913c, 0x0000000f, 0x0100000a,
846 0x8d00, 0xffff7f7f, 0x100e4848,
847 0x8d04, 0x00ffffff, 0x00164745,
848 0x8c00, 0xfffc0003, 0xe4000003,
849 0x8c04, 0xf8ff00ff, 0x40600060,
850 0x8c08, 0x00ff00ff, 0x001c001c,
851 0x8cf0, 0x1fff1fff, 0x08e00410,
852 0x8c20, 0x0fff0fff, 0x00800080,
853 0x8c24, 0x0fff0fff, 0x00800080,
854 0x8c18, 0xffffffff, 0x20202078,
855 0x8c1c, 0x0000ffff, 0x00001010,
856 0x28350, 0x00000f01, 0x00000000,
857 0x9508, 0x3700001f, 0x00000002,
858 0x960c, 0xffffffff, 0x54763210,
859 0x88c4, 0x001f3ae3, 0x000000c2,
860 0x88d4, 0x0000001f, 0x00000010,
861 0x8974, 0xffffffff, 0x00000000
862};
863
864static const u32 caicos_golden_registers[] =
865{
866 0x5eb4, 0xffffffff, 0x00000002,
867 0x5e78, 0x8f311ff1, 0x001000f0,
868 0x8c8, 0x00003420, 0x00001450,
869 0x8cc, 0x000fffff, 0x00040035,
870 0x3f90, 0xffff0000, 0xfffc0000,
871 0x9148, 0xffff0000, 0xfffc0000,
872 0x3f94, 0xffff0000, 0xfffc0000,
873 0x914c, 0xffff0000, 0xfffc0000,
874 0xc78, 0x00000080, 0x00000080,
875 0xbd4, 0x00073007, 0x00010001,
876 0xd02c, 0xbfffff1f, 0x08421000,
877 0xd0b8, 0x03773777, 0x02010001,
878 0x5bc0, 0x00200000, 0x50100000,
879 0x98f8, 0x33773777, 0x02010001,
880 0x98fc, 0xffffffff, 0x33221100,
881 0x7030, 0x31000311, 0x00000011,
882 0x2f48, 0x33773777, 0x02010001,
883 0x6b28, 0x00000010, 0x00000012,
884 0x7728, 0x00000010, 0x00000012,
885 0x10328, 0x00000010, 0x00000012,
886 0x10f28, 0x00000010, 0x00000012,
887 0x11b28, 0x00000010, 0x00000012,
888 0x12728, 0x00000010, 0x00000012,
889 0x240c, 0x000007ff, 0x00000380,
890 0x8a14, 0xf000001f, 0x00000001,
891 0x8b24, 0x3fff3fff, 0x00ff0fff,
892 0x8b10, 0x0000ff0f, 0x00000000,
893 0x28a4c, 0x07ffffff, 0x06000000,
894 0x10c, 0x00000001, 0x00010003,
895 0xa02c, 0xffffffff, 0x0000009b,
896 0x913c, 0x0000000f, 0x0100000a,
897 0x8d00, 0xffff7f7f, 0x100e4848,
898 0x8d04, 0x00ffffff, 0x00164745,
899 0x8c00, 0xfffc0003, 0xe4000003,
900 0x8c04, 0xf8ff00ff, 0x40600060,
901 0x8c08, 0x00ff00ff, 0x001c001c,
902 0x8cf0, 0x1fff1fff, 0x08e00410,
903 0x8c20, 0x0fff0fff, 0x00800080,
904 0x8c24, 0x0fff0fff, 0x00800080,
905 0x8c18, 0xffffffff, 0x20202078,
906 0x8c1c, 0x0000ffff, 0x00001010,
907 0x28350, 0x00000f01, 0x00000000,
908 0x9508, 0x3700001f, 0x00000002,
909 0x960c, 0xffffffff, 0x54763210,
910 0x88c4, 0x001f3ae3, 0x000000c2,
911 0x88d4, 0x0000001f, 0x00000010,
912 0x8974, 0xffffffff, 0x00000000
913};
914
915static void evergreen_init_golden_registers(struct radeon_device *rdev)
916{
917 switch (rdev->family) {
918 case CHIP_CYPRESS:
919 case CHIP_HEMLOCK:
920 radeon_program_register_sequence(rdev,
921 evergreen_golden_registers,
922 (const u32)ARRAY_SIZE(evergreen_golden_registers));
923 radeon_program_register_sequence(rdev,
924 evergreen_golden_registers2,
925 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
926 radeon_program_register_sequence(rdev,
927 cypress_mgcg_init,
928 (const u32)ARRAY_SIZE(cypress_mgcg_init));
929 break;
930 case CHIP_JUNIPER:
931 radeon_program_register_sequence(rdev,
932 evergreen_golden_registers,
933 (const u32)ARRAY_SIZE(evergreen_golden_registers));
934 radeon_program_register_sequence(rdev,
935 evergreen_golden_registers2,
936 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
937 radeon_program_register_sequence(rdev,
938 juniper_mgcg_init,
939 (const u32)ARRAY_SIZE(juniper_mgcg_init));
940 break;
941 case CHIP_REDWOOD:
942 radeon_program_register_sequence(rdev,
943 evergreen_golden_registers,
944 (const u32)ARRAY_SIZE(evergreen_golden_registers));
945 radeon_program_register_sequence(rdev,
946 evergreen_golden_registers2,
947 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
948 radeon_program_register_sequence(rdev,
949 redwood_mgcg_init,
950 (const u32)ARRAY_SIZE(redwood_mgcg_init));
951 break;
952 case CHIP_CEDAR:
953 radeon_program_register_sequence(rdev,
954 cedar_golden_registers,
955 (const u32)ARRAY_SIZE(cedar_golden_registers));
956 radeon_program_register_sequence(rdev,
957 evergreen_golden_registers2,
958 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
959 radeon_program_register_sequence(rdev,
960 cedar_mgcg_init,
961 (const u32)ARRAY_SIZE(cedar_mgcg_init));
962 break;
963 case CHIP_PALM:
964 radeon_program_register_sequence(rdev,
965 wrestler_golden_registers,
966 (const u32)ARRAY_SIZE(wrestler_golden_registers));
967 break;
968 case CHIP_SUMO:
969 radeon_program_register_sequence(rdev,
970 supersumo_golden_registers,
971 (const u32)ARRAY_SIZE(supersumo_golden_registers));
972 break;
973 case CHIP_SUMO2:
974 radeon_program_register_sequence(rdev,
975 supersumo_golden_registers,
976 (const u32)ARRAY_SIZE(supersumo_golden_registers));
977 radeon_program_register_sequence(rdev,
978 sumo_golden_registers,
979 (const u32)ARRAY_SIZE(sumo_golden_registers));
980 break;
981 case CHIP_BARTS:
982 radeon_program_register_sequence(rdev,
983 barts_golden_registers,
984 (const u32)ARRAY_SIZE(barts_golden_registers));
985 break;
986 case CHIP_TURKS:
987 radeon_program_register_sequence(rdev,
988 turks_golden_registers,
989 (const u32)ARRAY_SIZE(turks_golden_registers));
990 break;
991 case CHIP_CAICOS:
992 radeon_program_register_sequence(rdev,
993 caicos_golden_registers,
994 (const u32)ARRAY_SIZE(caicos_golden_registers));
995 break;
996 default:
997 break;
998 }
999}
1000
285484e2
JG		 1001void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
1002 unsigned *bankh, unsigned *mtaspect,
1003 unsigned *tile_split)
1004{
1005 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
1006 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
1007 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
1008 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
1009 switch (*bankw) {
1010 default:
1011 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
1012 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
1013 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
1014 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
1015 }
1016 switch (*bankh) {
1017 default:
1018 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
1019 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
1020 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
1021 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
1022 }
1023 switch (*mtaspect) {
1024 default:
1025 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
1026 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
1027 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
1028 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
1029 }
1030}
1031
23d33ba3
AD		 1032static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
1033 u32 cntl_reg, u32 status_reg)
1034{
1035 int r, i;
1036 struct atom_clock_dividers dividers;
1037
1038 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1039 clock, false, &dividers);
1040 if (r)
1041 return r;
1042
1043 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
1044
1045 for (i = 0; i < 100; i++) {
1046 if (RREG32(status_reg) & DCLK_STATUS)
1047 break;
1048 mdelay(10);
1049 }
1050 if (i == 100)
1051 return -ETIMEDOUT;
1052
1053 return 0;
1054}
1055
1056int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1057{
1058 int r = 0;
1059 u32 cg_scratch = RREG32(CG_SCRATCH1);
1060
1061 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
1062 if (r)
1063 goto done;
1064 cg_scratch &= 0xffff0000;
1065 cg_scratch |= vclk / 100; /* Mhz */
1066
1067 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
1068 if (r)
1069 goto done;
1070 cg_scratch &= 0x0000ffff;
1071 cg_scratch |= (dclk / 100) << 16; /* Mhz */
1072
1073done:
1074 WREG32(CG_SCRATCH1, cg_scratch);
1075
1076 return r;
1077}
1078
a8b4925c
AD		 1079int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1080{
1081 /* start off with something large */
facd112d 1082 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
a8b4925c
AD		 1083 int r;
1084
4ed10835
CK		 1085 /* bypass vclk and dclk with bclk */
1086 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1087 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
1088 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1089
1090 /* put PLL in bypass mode */
1091 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
1092
1093 if (!vclk || !dclk) {
1094 /* keep the Bypass mode, put PLL to sleep */
1095 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1096 return 0;
1097 }
1098
facd112d
CK		 1099 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
1100 16384, 0x03FFFFFF, 0, 128, 5,
1101 &fb_div, &vclk_div, &dclk_div);
1102 if (r)
1103 return r;
a8b4925c
AD		 1104
1105 /* set VCO_MODE to 1 */
1106 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
1107
1108 /* toggle UPLL_SLEEP to 1 then back to 0 */
1109 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1110 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
1111
1112 /* deassert UPLL_RESET */
1113 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
1114
1115 mdelay(1);
1116
facd112d 1117 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
a8b4925c
AD		 1118 if (r)
1119 return r;
1120
1121 /* assert UPLL_RESET again */
1122 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
1123
1124 /* disable spread spectrum. */
1125 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
1126
1127 /* set feedback divider */
facd112d 1128 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
a8b4925c
AD		 1129
1130 /* set ref divider to 0 */
1131 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
1132
facd112d 1133 if (fb_div < 307200)
a8b4925c
AD		 1134 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
1135 else
1136 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
1137
1138 /* set PDIV_A and PDIV_B */
1139 WREG32_P(CG_UPLL_FUNC_CNTL_2,
facd112d 1140 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
a8b4925c
AD		 1141 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
1142
1143 /* give the PLL some time to settle */
1144 mdelay(15);
1145
1146 /* deassert PLL_RESET */
1147 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
1148
1149 mdelay(15);
1150
1151 /* switch from bypass mode to normal mode */
1152 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
1153
facd112d 1154 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
a8b4925c
AD		 1155 if (r)
1156 return r;
1157
1158 /* switch VCLK and DCLK selection */
1159 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1160 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
1161 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1162
1163 mdelay(100);
1164
1165 return 0;
1166}
1167
d054ac16
AD		 1168void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
1169{
1170 u16 ctl, v;
32195aec 1171 int err;
d054ac16 1172
32195aec 1173 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
d054ac16
AD		 1174 if (err)
1175 return;
1176
1177 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
1178
1179 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
1180 * to avoid hangs or perfomance issues
1181 */
1182 if ((v == 0) || (v == 6) || (v == 7)) {
1183 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1184 ctl |= (2 << 12);
32195aec 1185 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
d054ac16
AD		 1186 }
1187}
1188
10257a6d
AD		 1189static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1190{
1191 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1192 return true;
1193 else
1194 return false;
1195}
1196
1197static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
1198{
1199 u32 pos1, pos2;
1200
1201 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1202 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1203
1204 if (pos1 != pos2)
1205 return true;
1206 else
1207 return false;
1208}
1209
377edc8b
AD		 1210/**
1211 * dce4_wait_for_vblank - vblank wait asic callback.
1212 *
1213 * @rdev: radeon_device pointer
1214 * @crtc: crtc to wait for vblank on
1215 *
1216 * Wait for vblank on the requested crtc (evergreen+).
1217 */
3ae19b75
AD		 1218void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
1219{
10257a6d 1220 unsigned i = 0;
3ae19b75 1221
4a15903d
AD		 1222 if (crtc >= rdev->num_crtc)
1223 return;
1224
10257a6d
AD		 1225 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
1226 return;
1227
1228 /* depending on when we hit vblank, we may be close to active; if so,
1229 * wait for another frame.
1230 */
1231 while (dce4_is_in_vblank(rdev, crtc)) {
1232 if (i++ % 100 == 0) {
1233 if (!dce4_is_counter_moving(rdev, crtc))
3ae19b75 1234 break;
3ae19b75 1235 }
10257a6d
AD		 1236 }
1237
1238 while (!dce4_is_in_vblank(rdev, crtc)) {
1239 if (i++ % 100 == 0) {
1240 if (!dce4_is_counter_moving(rdev, crtc))
3ae19b75 1241 break;
3ae19b75
AD		 1242 }
1243 }
1244}
1245
377edc8b
AD		 1246/**
1247 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
1248 *
1249 * @rdev: radeon_device pointer
1250 * @crtc: crtc to prepare for pageflip on
1251 *
1252 * Pre-pageflip callback (evergreen+).
1253 * Enables the pageflip irq (vblank irq).
1254 */
6f34be50
AD		 1255void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
1256{
6f34be50
AD		 1257 /* enable the pflip int */
1258 radeon_irq_kms_pflip_irq_get(rdev, crtc);
1259}
1260
377edc8b
AD		 1261/**
1262 * evergreen_post_page_flip - pos-pageflip callback.
1263 *
1264 * @rdev: radeon_device pointer
1265 * @crtc: crtc to cleanup pageflip on
1266 *
1267 * Post-pageflip callback (evergreen+).
1268 * Disables the pageflip irq (vblank irq).
1269 */
6f34be50
AD		 1270void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
1271{
1272 /* disable the pflip int */
1273 radeon_irq_kms_pflip_irq_put(rdev, crtc);
1274}
1275
377edc8b
AD		 1276/**
1277 * evergreen_page_flip - pageflip callback.
1278 *
1279 * @rdev: radeon_device pointer
1280 * @crtc_id: crtc to cleanup pageflip on
1281 * @crtc_base: new address of the crtc (GPU MC address)
1282 *
1283 * Does the actual pageflip (evergreen+).
1284 * During vblank we take the crtc lock and wait for the update_pending
1285 * bit to go high, when it does, we release the lock, and allow the
1286 * double buffered update to take place.
1287 * Returns the current update pending status.
1288 */
6f34be50
AD		 1289u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
1290{
1291 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
1292 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 1293 int i;
6f34be50
AD		 1294
1295 /* Lock the graphics update lock */
1296 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
1297 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
1298
1299 /* update the scanout addresses */
1300 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1301 upper_32_bits(crtc_base));
1302 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1303 (u32)crtc_base);
1304
1305 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1306 upper_32_bits(crtc_base));
1307 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1308 (u32)crtc_base);
1309
1310 /* Wait for update_pending to go high. */
f6496479
AD		 1311 for (i = 0; i < rdev->usec_timeout; i++) {
1312 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
1313 break;
1314 udelay(1);
1315 }
6f34be50
AD		 1316 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
1317
1318 /* Unlock the lock, so double-buffering can take place inside vblank */
1319 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
1320 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
1321
1322 /* Return current update_pending status: */
1323 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
1324}
1325
21a8122a 1326/* get temperature in millidegrees */
20d391d7 1327int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 1328{
1c88d74f
AD		 1329 u32 temp, toffset;
1330 int actual_temp = 0;
67b3f823
AD		 1331
1332 if (rdev->family == CHIP_JUNIPER) {
1333 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
1334 TOFFSET_SHIFT;
1335 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
1336 TS0_ADC_DOUT_SHIFT;
1337
1338 if (toffset & 0x100)
1339 actual_temp = temp / 2 - (0x200 - toffset);
1340 else
1341 actual_temp = temp / 2 + toffset;
1342
1343 actual_temp = actual_temp * 1000;
1344
1345 } else {
1346 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
1347 ASIC_T_SHIFT;
1348
1349 if (temp & 0x400)
1350 actual_temp = -256;
1351 else if (temp & 0x200)
1352 actual_temp = 255;
1353 else if (temp & 0x100) {
1354 actual_temp = temp & 0x1ff;
1355 actual_temp |= ~0x1ff;
1356 } else
1357 actual_temp = temp & 0xff;
1358
1359 actual_temp = (actual_temp * 1000) / 2;
1360 }
21a8122a 1361
67b3f823 1362 return actual_temp;
21a8122a
AD		 1363}
1364
20d391d7 1365int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 1366{
1367 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 1368 int actual_temp = temp - 49;
e33df25f
AD		 1369
1370 return actual_temp * 1000;
1371}
1372
377edc8b
AD		 1373/**
1374 * sumo_pm_init_profile - Initialize power profiles callback.
1375 *
1376 * @rdev: radeon_device pointer
1377 *
1378 * Initialize the power states used in profile mode
1379 * (sumo, trinity, SI).
1380 * Used for profile mode only.
1381 */
a4c9e2ee
AD		 1382void sumo_pm_init_profile(struct radeon_device *rdev)
1383{
1384 int idx;
1385
1386 /* default */
1387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
1388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
1389 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
1390 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
1391
1392 /* low,mid sh/mh */
1393 if (rdev->flags & RADEON_IS_MOBILITY)
1394 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
1395 else
1396 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1397
1398 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
1399 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
1400 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
1401 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
1402
1403 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
1404 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
1405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
1406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
1407
1408 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
1409 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
1410 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
1411 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
1412
1413 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
1414 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
1415 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
1416 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
1417
1418 /* high sh/mh */
1419 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1420 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
1421 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
1422 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
1423 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
1424 rdev->pm.power_state[idx].num_clock_modes - 1;
1425
1426 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
1427 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
1428 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
1429 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
1430 rdev->pm.power_state[idx].num_clock_modes - 1;
1431}
1432
27810fb2
AD		 1433/**
1434 * btc_pm_init_profile - Initialize power profiles callback.
1435 *
1436 * @rdev: radeon_device pointer
1437 *
1438 * Initialize the power states used in profile mode
1439 * (BTC, cayman).
1440 * Used for profile mode only.
1441 */
1442void btc_pm_init_profile(struct radeon_device *rdev)
1443{
1444 int idx;
1445
1446 /* default */
1447 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
1448 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
1449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
1450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
1451 /* starting with BTC, there is one state that is used for both
1452 * MH and SH. Difference is that we always use the high clock index for
1453 * mclk.
1454 */
1455 if (rdev->flags & RADEON_IS_MOBILITY)
1456 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
1457 else
1458 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
1459 /* low sh */
1460 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
1461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
1462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
1463 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
1464 /* mid sh */
1465 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
1466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
1467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
1468 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
1469 /* high sh */
1470 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
1471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
1472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
1473 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
1474 /* low mh */
1475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
1476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
1477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
1478 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
1479 /* mid mh */
1480 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
1481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
1482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
1483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
1484 /* high mh */
1485 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
1486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
1487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
1488 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
1489}
1490
377edc8b
AD		 1491/**
1492 * evergreen_pm_misc - set additional pm hw parameters callback.
1493 *
1494 * @rdev: radeon_device pointer
1495 *
1496 * Set non-clock parameters associated with a power state
1497 * (voltage, etc.) (evergreen+).
1498 */
49e02b73
AD		 1499void evergreen_pm_misc(struct radeon_device *rdev)
1500{
a081a9d6
RM		 1501 int req_ps_idx = rdev->pm.requested_power_state_index;
1502 int req_cm_idx = rdev->pm.requested_clock_mode_index;
1503 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
1504 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 1505
2feea49a 1506 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 1507 /* 0xff01 is a flag rather then an actual voltage */
1508 if (voltage->voltage == 0xff01)
1509 return;
2feea49a 1510 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 1511 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 1512 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 1513 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
1514 }
7ae764b1
AD		 1515
1516 /* starting with BTC, there is one state that is used for both
1517 * MH and SH. Difference is that we always use the high clock index for
1518 * mclk and vddci.
1519 */
1520 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
1521 (rdev->family >= CHIP_BARTS) &&
1522 rdev->pm.active_crtc_count &&
1523 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
1524 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
1525 voltage = &rdev->pm.power_state[req_ps_idx].
1526 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
1527
a377e187
AD		 1528 /* 0xff01 is a flag rather then an actual voltage */
1529 if (voltage->vddci == 0xff01)
1530 return;
2feea49a
AD		 1531 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
1532 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
1533 rdev->pm.current_vddci = voltage->vddci;
1534 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 1535 }
1536 }
49e02b73
AD		 1537}
1538
377edc8b
AD		 1539/**
1540 * evergreen_pm_prepare - pre-power state change callback.
1541 *
1542 * @rdev: radeon_device pointer
1543 *
1544 * Prepare for a power state change (evergreen+).
1545 */
49e02b73
AD		 1546void evergreen_pm_prepare(struct radeon_device *rdev)
1547{
1548 struct drm_device *ddev = rdev->ddev;
1549 struct drm_crtc *crtc;
1550 struct radeon_crtc *radeon_crtc;
1551 u32 tmp;
1552
1553 /* disable any active CRTCs */
1554 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
1555 radeon_crtc = to_radeon_crtc(crtc);
1556 if (radeon_crtc->enabled) {
1557 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
1558 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1559 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
1560 }
1561 }
1562}
1563
377edc8b
AD		 1564/**
1565 * evergreen_pm_finish - post-power state change callback.
1566 *
1567 * @rdev: radeon_device pointer
1568 *
1569 * Clean up after a power state change (evergreen+).
1570 */
49e02b73
AD		 1571void evergreen_pm_finish(struct radeon_device *rdev)
1572{
1573 struct drm_device *ddev = rdev->ddev;
1574 struct drm_crtc *crtc;
1575 struct radeon_crtc *radeon_crtc;
1576 u32 tmp;
1577
1578 /* enable any active CRTCs */
1579 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
1580 radeon_crtc = to_radeon_crtc(crtc);
1581 if (radeon_crtc->enabled) {
1582 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
1583 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1584 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
1585 }
1586 }
1587}
1588
377edc8b
AD		 1589/**
1590 * evergreen_hpd_sense - hpd sense callback.
1591 *
1592 * @rdev: radeon_device pointer
1593 * @hpd: hpd (hotplug detect) pin
1594 *
1595 * Checks if a digital monitor is connected (evergreen+).
1596 * Returns true if connected, false if not connected.
1597 */
bcc1c2a1
AD		 1598bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
1599{
1600 bool connected = false;
0ca2ab52
AD		 1601
1602 switch (hpd) {
1603 case RADEON_HPD_1:
1604 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
1605 connected = true;
1606 break;
1607 case RADEON_HPD_2:
1608 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
1609 connected = true;
1610 break;
1611 case RADEON_HPD_3:
1612 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
1613 connected = true;
1614 break;
1615 case RADEON_HPD_4:
1616 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
1617 connected = true;
1618 break;
1619 case RADEON_HPD_5:
1620 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
1621 connected = true;
1622 break;
1623 case RADEON_HPD_6:
1624 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
1625 connected = true;
1626 break;
1627 default:
1628 break;
1629 }
1630
bcc1c2a1
AD		 1631 return connected;
1632}
1633
377edc8b
AD		 1634/**
1635 * evergreen_hpd_set_polarity - hpd set polarity callback.
1636 *
1637 * @rdev: radeon_device pointer
1638 * @hpd: hpd (hotplug detect) pin
1639 *
1640 * Set the polarity of the hpd pin (evergreen+).
1641 */
bcc1c2a1
AD		 1642void evergreen_hpd_set_polarity(struct radeon_device *rdev,
1643 enum radeon_hpd_id hpd)
1644{
0ca2ab52
AD		 1645 u32 tmp;
1646 bool connected = evergreen_hpd_sense(rdev, hpd);
1647
1648 switch (hpd) {
1649 case RADEON_HPD_1:
1650 tmp = RREG32(DC_HPD1_INT_CONTROL);
1651 if (connected)
1652 tmp &= ~DC_HPDx_INT_POLARITY;
1653 else
1654 tmp |= DC_HPDx_INT_POLARITY;
1655 WREG32(DC_HPD1_INT_CONTROL, tmp);
1656 break;
1657 case RADEON_HPD_2:
1658 tmp = RREG32(DC_HPD2_INT_CONTROL);
1659 if (connected)
1660 tmp &= ~DC_HPDx_INT_POLARITY;
1661 else
1662 tmp |= DC_HPDx_INT_POLARITY;
1663 WREG32(DC_HPD2_INT_CONTROL, tmp);
1664 break;
1665 case RADEON_HPD_3:
1666 tmp = RREG32(DC_HPD3_INT_CONTROL);
1667 if (connected)
1668 tmp &= ~DC_HPDx_INT_POLARITY;
1669 else
1670 tmp |= DC_HPDx_INT_POLARITY;
1671 WREG32(DC_HPD3_INT_CONTROL, tmp);
1672 break;
1673 case RADEON_HPD_4:
1674 tmp = RREG32(DC_HPD4_INT_CONTROL);
1675 if (connected)
1676 tmp &= ~DC_HPDx_INT_POLARITY;
1677 else
1678 tmp |= DC_HPDx_INT_POLARITY;
1679 WREG32(DC_HPD4_INT_CONTROL, tmp);
1680 break;
1681 case RADEON_HPD_5:
1682 tmp = RREG32(DC_HPD5_INT_CONTROL);
1683 if (connected)
1684 tmp &= ~DC_HPDx_INT_POLARITY;
1685 else
1686 tmp |= DC_HPDx_INT_POLARITY;
1687 WREG32(DC_HPD5_INT_CONTROL, tmp);
1688 break;
1689 case RADEON_HPD_6:
1690 tmp = RREG32(DC_HPD6_INT_CONTROL);
1691 if (connected)
1692 tmp &= ~DC_HPDx_INT_POLARITY;
1693 else
1694 tmp |= DC_HPDx_INT_POLARITY;
1695 WREG32(DC_HPD6_INT_CONTROL, tmp);
1696 break;
1697 default:
1698 break;
1699 }
bcc1c2a1
AD		 1700}
1701
377edc8b
AD		 1702/**
1703 * evergreen_hpd_init - hpd setup callback.
1704 *
1705 * @rdev: radeon_device pointer
1706 *
1707 * Setup the hpd pins used by the card (evergreen+).
1708 * Enable the pin, set the polarity, and enable the hpd interrupts.
1709 */
bcc1c2a1
AD		 1710void evergreen_hpd_init(struct radeon_device *rdev)
1711{
0ca2ab52
AD		 1712 struct drm_device *dev = rdev->ddev;
1713 struct drm_connector *connector;
fb98257a 1714 unsigned enabled = 0;
0ca2ab52
AD		 1715 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
1716 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 1717
0ca2ab52
AD		 1718 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1719 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2e97be73
AD		 1720
1721 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
1722 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
1723 /* don't try to enable hpd on eDP or LVDS avoid breaking the
1724 * aux dp channel on imac and help (but not completely fix)
1725 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
1726 * also avoid interrupt storms during dpms.
1727 */
1728 continue;
1729 }
0ca2ab52
AD		 1730 switch (radeon_connector->hpd.hpd) {
1731 case RADEON_HPD_1:
1732 WREG32(DC_HPD1_CONTROL, tmp);
0ca2ab52
AD		 1733 break;
1734 case RADEON_HPD_2:
1735 WREG32(DC_HPD2_CONTROL, tmp);
0ca2ab52
AD		 1736 break;
1737 case RADEON_HPD_3:
1738 WREG32(DC_HPD3_CONTROL, tmp);
0ca2ab52
AD		 1739 break;
1740 case RADEON_HPD_4:
1741 WREG32(DC_HPD4_CONTROL, tmp);
0ca2ab52
AD		 1742 break;
1743 case RADEON_HPD_5:
1744 WREG32(DC_HPD5_CONTROL, tmp);
0ca2ab52
AD		 1745 break;
1746 case RADEON_HPD_6:
1747 WREG32(DC_HPD6_CONTROL, tmp);
0ca2ab52
AD		 1748 break;
1749 default:
1750 break;
1751 }
64912e99 1752 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
fb98257a 1753 enabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 1754 }
fb98257a 1755 radeon_irq_kms_enable_hpd(rdev, enabled);
bcc1c2a1
AD		 1756}
1757
377edc8b
AD		 1758/**
1759 * evergreen_hpd_fini - hpd tear down callback.
1760 *
1761 * @rdev: radeon_device pointer
1762 *
1763 * Tear down the hpd pins used by the card (evergreen+).
1764 * Disable the hpd interrupts.
1765 */
0ca2ab52 1766void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 1767{
0ca2ab52
AD		 1768 struct drm_device *dev = rdev->ddev;
1769 struct drm_connector *connector;
fb98257a 1770 unsigned disabled = 0;
0ca2ab52
AD		 1771
1772 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1773 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1774 switch (radeon_connector->hpd.hpd) {
1775 case RADEON_HPD_1:
1776 WREG32(DC_HPD1_CONTROL, 0);
0ca2ab52
AD		 1777 break;
1778 case RADEON_HPD_2:
1779 WREG32(DC_HPD2_CONTROL, 0);
0ca2ab52
AD		 1780 break;
1781 case RADEON_HPD_3:
1782 WREG32(DC_HPD3_CONTROL, 0);
0ca2ab52
AD		 1783 break;
1784 case RADEON_HPD_4:
1785 WREG32(DC_HPD4_CONTROL, 0);
0ca2ab52
AD		 1786 break;
1787 case RADEON_HPD_5:
1788 WREG32(DC_HPD5_CONTROL, 0);
0ca2ab52
AD		 1789 break;
1790 case RADEON_HPD_6:
1791 WREG32(DC_HPD6_CONTROL, 0);
0ca2ab52
AD		 1792 break;
1793 default:
1794 break;
1795 }
fb98257a 1796 disabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 1797 }
fb98257a 1798 radeon_irq_kms_disable_hpd(rdev, disabled);
bcc1c2a1
AD		 1799}
1800
f9d9c362
AD		 1801/* watermark setup */
1802
1803static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
1804 struct radeon_crtc *radeon_crtc,
1805 struct drm_display_mode *mode,
1806 struct drm_display_mode *other_mode)
1807{
12dfc843 1808 u32 tmp;
f9d9c362
AD		 1809 /*
1810 * Line Buffer Setup
1811 * There are 3 line buffers, each one shared by 2 display controllers.
1812 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1813 * the display controllers. The paritioning is done via one of four
1814 * preset allocations specified in bits 2:0:
1815 * first display controller
1816 * 0 - first half of lb (3840 * 2)
1817 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 1818 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 1819 * 3 - first 1/4 of lb (1920 * 2)
1820 * second display controller
1821 * 4 - second half of lb (3840 * 2)
1822 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 1823 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 1824 * 7 - last 1/4 of lb (1920 * 2)
1825 */
12dfc843
AD		 1826 /* this can get tricky if we have two large displays on a paired group
1827 * of crtcs. Ideally for multiple large displays we'd assign them to
1828 * non-linked crtcs for maximum line buffer allocation.
1829 */
1830 if (radeon_crtc->base.enabled && mode) {
1831 if (other_mode)
f9d9c362 1832 tmp = 0; /* 1/2 */
12dfc843
AD		 1833 else
1834 tmp = 2; /* whole */
1835 } else
1836 tmp = 0;
f9d9c362
AD		 1837
1838 /* second controller of the pair uses second half of the lb */
1839 if (radeon_crtc->crtc_id % 2)
1840 tmp += 4;
1841 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
1842
12dfc843
AD		 1843 if (radeon_crtc->base.enabled && mode) {
1844 switch (tmp) {
1845 case 0:
1846 case 4:
1847 default:
1848 if (ASIC_IS_DCE5(rdev))
1849 return 4096 * 2;
1850 else
1851 return 3840 * 2;
1852 case 1:
1853 case 5:
1854 if (ASIC_IS_DCE5(rdev))
1855 return 6144 * 2;
1856 else
1857 return 5760 * 2;
1858 case 2:
1859 case 6:
1860 if (ASIC_IS_DCE5(rdev))
1861 return 8192 * 2;
1862 else
1863 return 7680 * 2;
1864 case 3:
1865 case 7:
1866 if (ASIC_IS_DCE5(rdev))
1867 return 2048 * 2;
1868 else
1869 return 1920 * 2;
1870 }
f9d9c362 1871 }
12dfc843
AD		 1872
1873 /* controller not enabled, so no lb used */
1874 return 0;
f9d9c362
AD		 1875}
1876
ca7db22b 1877u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 1878{
1879 u32 tmp = RREG32(MC_SHARED_CHMAP);
1880
1881 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1882 case 0:
1883 default:
1884 return 1;
1885 case 1:
1886 return 2;
1887 case 2:
1888 return 4;
1889 case 3:
1890 return 8;
1891 }
1892}
1893
1894struct evergreen_wm_params {
1895 u32 dram_channels; /* number of dram channels */
1896 u32 yclk; /* bandwidth per dram data pin in kHz */
1897 u32 sclk; /* engine clock in kHz */
1898 u32 disp_clk; /* display clock in kHz */
1899 u32 src_width; /* viewport width */
1900 u32 active_time; /* active display time in ns */
1901 u32 blank_time; /* blank time in ns */
1902 bool interlaced; /* mode is interlaced */
1903 fixed20_12 vsc; /* vertical scale ratio */
1904 u32 num_heads; /* number of active crtcs */
1905 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
1906 u32 lb_size; /* line buffer allocated to pipe */
1907 u32 vtaps; /* vertical scaler taps */
1908};
1909
1910static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
1911{
1912 /* Calculate DRAM Bandwidth and the part allocated to display. */
1913 fixed20_12 dram_efficiency; /* 0.7 */
1914 fixed20_12 yclk, dram_channels, bandwidth;
1915 fixed20_12 a;
1916
1917 a.full = dfixed_const(1000);
1918 yclk.full = dfixed_const(wm->yclk);
1919 yclk.full = dfixed_div(yclk, a);
1920 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1921 a.full = dfixed_const(10);
1922 dram_efficiency.full = dfixed_const(7);
1923 dram_efficiency.full = dfixed_div(dram_efficiency, a);
1924 bandwidth.full = dfixed_mul(dram_channels, yclk);
1925 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
1926
1927 return dfixed_trunc(bandwidth);
1928}
1929
1930static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
1931{
1932 /* Calculate DRAM Bandwidth and the part allocated to display. */
1933 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1934 fixed20_12 yclk, dram_channels, bandwidth;
1935 fixed20_12 a;
1936
1937 a.full = dfixed_const(1000);
1938 yclk.full = dfixed_const(wm->yclk);
1939 yclk.full = dfixed_div(yclk, a);
1940 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1941 a.full = dfixed_const(10);
1942 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1943 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1944 bandwidth.full = dfixed_mul(dram_channels, yclk);
1945 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1946
1947 return dfixed_trunc(bandwidth);
1948}
1949
1950static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
1951{
1952 /* Calculate the display Data return Bandwidth */
1953 fixed20_12 return_efficiency; /* 0.8 */
1954 fixed20_12 sclk, bandwidth;
1955 fixed20_12 a;
1956
1957 a.full = dfixed_const(1000);
1958 sclk.full = dfixed_const(wm->sclk);
1959 sclk.full = dfixed_div(sclk, a);
1960 a.full = dfixed_const(10);
1961 return_efficiency.full = dfixed_const(8);
1962 return_efficiency.full = dfixed_div(return_efficiency, a);
1963 a.full = dfixed_const(32);
1964 bandwidth.full = dfixed_mul(a, sclk);
1965 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1966
1967 return dfixed_trunc(bandwidth);
1968}
1969
1970static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
1971{
1972 /* Calculate the DMIF Request Bandwidth */
1973 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1974 fixed20_12 disp_clk, bandwidth;
1975 fixed20_12 a;
1976
1977 a.full = dfixed_const(1000);
1978 disp_clk.full = dfixed_const(wm->disp_clk);
1979 disp_clk.full = dfixed_div(disp_clk, a);
1980 a.full = dfixed_const(10);
1981 disp_clk_request_efficiency.full = dfixed_const(8);
1982 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1983 a.full = dfixed_const(32);
1984 bandwidth.full = dfixed_mul(a, disp_clk);
1985 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
1986
1987 return dfixed_trunc(bandwidth);
1988}
1989
1990static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
1991{
1992 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1993 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
1994 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
1995 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
1996
1997 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1998}
1999
2000static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
2001{
2002 /* Calculate the display mode Average Bandwidth
2003 * DisplayMode should contain the source and destination dimensions,
2004 * timing, etc.
2005 */
2006 fixed20_12 bpp;
2007 fixed20_12 line_time;
2008 fixed20_12 src_width;
2009 fixed20_12 bandwidth;
2010 fixed20_12 a;
2011
2012 a.full = dfixed_const(1000);
2013 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2014 line_time.full = dfixed_div(line_time, a);
2015 bpp.full = dfixed_const(wm->bytes_per_pixel);
2016 src_width.full = dfixed_const(wm->src_width);
2017 bandwidth.full = dfixed_mul(src_width, bpp);
2018 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2019 bandwidth.full = dfixed_div(bandwidth, line_time);
2020
2021 return dfixed_trunc(bandwidth);
2022}
2023
2024static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
2025{
2026 /* First calcualte the latency in ns */
2027 u32 mc_latency = 2000; /* 2000 ns. */
2028 u32 available_bandwidth = evergreen_available_bandwidth(wm);
2029 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2030 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2031 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2032 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2033 (wm->num_heads * cursor_line_pair_return_time);
2034 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2035 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2036 fixed20_12 a, b, c;
2037
2038 if (wm->num_heads == 0)
2039 return 0;
2040
2041 a.full = dfixed_const(2);
2042 b.full = dfixed_const(1);
2043 if ((wm->vsc.full > a.full) ||
2044 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2045 (wm->vtaps >= 5) ||
2046 ((wm->vsc.full >= a.full) && wm->interlaced))
2047 max_src_lines_per_dst_line = 4;
2048 else
2049 max_src_lines_per_dst_line = 2;
2050
2051 a.full = dfixed_const(available_bandwidth);
2052 b.full = dfixed_const(wm->num_heads);
2053 a.full = dfixed_div(a, b);
2054
2055 b.full = dfixed_const(1000);
2056 c.full = dfixed_const(wm->disp_clk);
2057 b.full = dfixed_div(c, b);
2058 c.full = dfixed_const(wm->bytes_per_pixel);
2059 b.full = dfixed_mul(b, c);
2060
2061 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
2062
2063 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2064 b.full = dfixed_const(1000);
2065 c.full = dfixed_const(lb_fill_bw);
2066 b.full = dfixed_div(c, b);
2067 a.full = dfixed_div(a, b);
2068 line_fill_time = dfixed_trunc(a);
2069
2070 if (line_fill_time < wm->active_time)
2071 return latency;
2072 else
2073 return latency + (line_fill_time - wm->active_time);
2074
2075}
2076
2077static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
2078{
2079 if (evergreen_average_bandwidth(wm) <=
2080 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
2081 return true;
2082 else
2083 return false;
2084};
2085
2086static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
2087{
2088 if (evergreen_average_bandwidth(wm) <=
2089 (evergreen_available_bandwidth(wm) / wm->num_heads))
2090 return true;
2091 else
2092 return false;
2093};
2094
2095static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
2096{
2097 u32 lb_partitions = wm->lb_size / wm->src_width;
2098 u32 line_time = wm->active_time + wm->blank_time;
2099 u32 latency_tolerant_lines;
2100 u32 latency_hiding;
2101 fixed20_12 a;
2102
2103 a.full = dfixed_const(1);
2104 if (wm->vsc.full > a.full)
2105 latency_tolerant_lines = 1;
2106 else {
2107 if (lb_partitions <= (wm->vtaps + 1))
2108 latency_tolerant_lines = 1;
2109 else
2110 latency_tolerant_lines = 2;
2111 }
2112
2113 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2114
2115 if (evergreen_latency_watermark(wm) <= latency_hiding)
2116 return true;
2117 else
2118 return false;
2119}
2120
2121static void evergreen_program_watermarks(struct radeon_device *rdev,
2122 struct radeon_crtc *radeon_crtc,
2123 u32 lb_size, u32 num_heads)
2124{
2125 struct drm_display_mode *mode = &radeon_crtc->base.mode;
cf0cfdd7
AD		 2126 struct evergreen_wm_params wm_low, wm_high;
2127 u32 dram_channels;
f9d9c362
AD		 2128 u32 pixel_period;
2129 u32 line_time = 0;
2130 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2131 u32 priority_a_mark = 0, priority_b_mark = 0;
2132 u32 priority_a_cnt = PRIORITY_OFF;
2133 u32 priority_b_cnt = PRIORITY_OFF;
2134 u32 pipe_offset = radeon_crtc->crtc_id * 16;
2135 u32 tmp, arb_control3;
2136 fixed20_12 a, b, c;
2137
2138 if (radeon_crtc->base.enabled && num_heads && mode) {
2139 pixel_period = 1000000 / (u32)mode->clock;
2140 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
2141 priority_a_cnt = 0;
2142 priority_b_cnt = 0;
cf0cfdd7
AD		 2143 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2144
2145 /* watermark for high clocks */
2146 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2147 wm_high.yclk =
2148 radeon_dpm_get_mclk(rdev, false) * 10;
2149 wm_high.sclk =
2150 radeon_dpm_get_sclk(rdev, false) * 10;
2151 } else {
2152 wm_high.yclk = rdev->pm.current_mclk * 10;
2153 wm_high.sclk = rdev->pm.current_sclk * 10;
2154 }
f9d9c362 2155
cf0cfdd7
AD		 2156 wm_high.disp_clk = mode->clock;
2157 wm_high.src_width = mode->crtc_hdisplay;
2158 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
2159 wm_high.blank_time = line_time - wm_high.active_time;
2160 wm_high.interlaced = false;
f9d9c362 2161 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
cf0cfdd7
AD		 2162 wm_high.interlaced = true;
2163 wm_high.vsc = radeon_crtc->vsc;
2164 wm_high.vtaps = 1;
f9d9c362 2165 if (radeon_crtc->rmx_type != RMX_OFF)
cf0cfdd7
AD		 2166 wm_high.vtaps = 2;
2167 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2168 wm_high.lb_size = lb_size;
2169 wm_high.dram_channels = dram_channels;
2170 wm_high.num_heads = num_heads;
2171
2172 /* watermark for low clocks */
2173 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2174 wm_low.yclk =
2175 radeon_dpm_get_mclk(rdev, true) * 10;
2176 wm_low.sclk =
2177 radeon_dpm_get_sclk(rdev, true) * 10;
2178 } else {
2179 wm_low.yclk = rdev->pm.current_mclk * 10;
2180 wm_low.sclk = rdev->pm.current_sclk * 10;
2181 }
2182
2183 wm_low.disp_clk = mode->clock;
2184 wm_low.src_width = mode->crtc_hdisplay;
2185 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
2186 wm_low.blank_time = line_time - wm_low.active_time;
2187 wm_low.interlaced = false;
2188 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2189 wm_low.interlaced = true;
2190 wm_low.vsc = radeon_crtc->vsc;
2191 wm_low.vtaps = 1;
2192 if (radeon_crtc->rmx_type != RMX_OFF)
2193 wm_low.vtaps = 2;
2194 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2195 wm_low.lb_size = lb_size;
2196 wm_low.dram_channels = dram_channels;
2197 wm_low.num_heads = num_heads;
f9d9c362
AD		 2198
2199 /* set for high clocks */
cf0cfdd7 2200 latency_watermark_a = min(evergreen_latency_watermark(&wm_high), (u32)65535);
f9d9c362 2201 /* set for low clocks */
cf0cfdd7 2202 latency_watermark_b = min(evergreen_latency_watermark(&wm_low), (u32)65535);
f9d9c362
AD		 2203
2204 /* possibly force display priority to high */
2205 /* should really do this at mode validation time... */
cf0cfdd7
AD		 2206 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2207 !evergreen_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2208 !evergreen_check_latency_hiding(&wm_high) ||
f9d9c362 2209 (rdev->disp_priority == 2)) {
cf0cfdd7 2210 DRM_DEBUG_KMS("force priority a to high\n");
f9d9c362 2211 priority_a_cnt |= PRIORITY_ALWAYS_ON;
cf0cfdd7
AD		 2212 }
2213 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2214 !evergreen_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2215 !evergreen_check_latency_hiding(&wm_low) ||
2216 (rdev->disp_priority == 2)) {
2217 DRM_DEBUG_KMS("force priority b to high\n");
f9d9c362
AD		 2218 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2219 }
2220
2221 a.full = dfixed_const(1000);
2222 b.full = dfixed_const(mode->clock);
2223 b.full = dfixed_div(b, a);
2224 c.full = dfixed_const(latency_watermark_a);
2225 c.full = dfixed_mul(c, b);
2226 c.full = dfixed_mul(c, radeon_crtc->hsc);
2227 c.full = dfixed_div(c, a);
2228 a.full = dfixed_const(16);
2229 c.full = dfixed_div(c, a);
2230 priority_a_mark = dfixed_trunc(c);
2231 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2232
2233 a.full = dfixed_const(1000);
2234 b.full = dfixed_const(mode->clock);
2235 b.full = dfixed_div(b, a);
2236 c.full = dfixed_const(latency_watermark_b);
2237 c.full = dfixed_mul(c, b);
2238 c.full = dfixed_mul(c, radeon_crtc->hsc);
2239 c.full = dfixed_div(c, a);
2240 a.full = dfixed_const(16);
2241 c.full = dfixed_div(c, a);
2242 priority_b_mark = dfixed_trunc(c);
2243 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2244 }
2245
2246 /* select wm A */
2247 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2248 tmp = arb_control3;
2249 tmp &= ~LATENCY_WATERMARK_MASK(3);
2250 tmp |= LATENCY_WATERMARK_MASK(1);
2251 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2252 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2253 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2254 LATENCY_HIGH_WATERMARK(line_time)));
2255 /* select wm B */
2256 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2257 tmp &= ~LATENCY_WATERMARK_MASK(3);
2258 tmp |= LATENCY_WATERMARK_MASK(2);
2259 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2260 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2261 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2262 LATENCY_HIGH_WATERMARK(line_time)));
2263 /* restore original selection */
2264 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
2265
2266 /* write the priority marks */
2267 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2268 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2269
2270}
2271
377edc8b
AD		 2272/**
2273 * evergreen_bandwidth_update - update display watermarks callback.
2274 *
2275 * @rdev: radeon_device pointer
2276 *
2277 * Update the display watermarks based on the requested mode(s)
2278 * (evergreen+).
2279 */
0ca2ab52 2280void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 2281{
f9d9c362
AD		 2282 struct drm_display_mode *mode0 = NULL;
2283 struct drm_display_mode *mode1 = NULL;
2284 u32 num_heads = 0, lb_size;
2285 int i;
2286
2287 radeon_update_display_priority(rdev);
2288
2289 for (i = 0; i < rdev->num_crtc; i++) {
2290 if (rdev->mode_info.crtcs[i]->base.enabled)
2291 num_heads++;
2292 }
2293 for (i = 0; i < rdev->num_crtc; i += 2) {
2294 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2295 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2296 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2297 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2298 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2299 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2300 }
bcc1c2a1
AD		 2301}
2302
377edc8b
AD		 2303/**
2304 * evergreen_mc_wait_for_idle - wait for MC idle callback.
2305 *
2306 * @rdev: radeon_device pointer
2307 *
2308 * Wait for the MC (memory controller) to be idle.
2309 * (evergreen+).
2310 * Returns 0 if the MC is idle, -1 if not.
2311 */
b9952a8a 2312int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 2313{
2314 unsigned i;
2315 u32 tmp;
2316
2317 for (i = 0; i < rdev->usec_timeout; i++) {
2318 /* read MC_STATUS */
2319 tmp = RREG32(SRBM_STATUS) & 0x1F00;
2320 if (!tmp)
2321 return 0;
2322 udelay(1);
2323 }
2324 return -1;
2325}
2326
2327/*
2328 * GART
2329 */
0fcdb61e
AD		 2330void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
2331{
2332 unsigned i;
2333 u32 tmp;
2334
6f2f48a9
AD		 2335 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2336
0fcdb61e
AD		 2337 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
2338 for (i = 0; i < rdev->usec_timeout; i++) {
2339 /* read MC_STATUS */
2340 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
2341 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
2342 if (tmp == 2) {
2343 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
2344 return;
2345 }
2346 if (tmp) {
2347 return;
2348 }
2349 udelay(1);
2350 }
2351}
2352
1109ca09 2353static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 2354{
2355 u32 tmp;
0fcdb61e 2356 int r;
bcc1c2a1 2357
c9a1be96 2358 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 2359 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
2360 return -EINVAL;
2361 }
2362 r = radeon_gart_table_vram_pin(rdev);
2363 if (r)
2364 return r;
82568565 2365 radeon_gart_restore(rdev);
bcc1c2a1
AD		 2366 /* Setup L2 cache */
2367 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
2368 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2369 EFFECTIVE_L2_QUEUE_SIZE(7));
2370 WREG32(VM_L2_CNTL2, 0);
2371 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2372 /* Setup TLB control */
2373 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
2374 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2375 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
2376 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 2377 if (rdev->flags & RADEON_IS_IGP) {
2378 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
2379 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
2380 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
2381 } else {
2382 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
2383 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
2384 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 2385 if ((rdev->family == CHIP_JUNIPER) ||
2386 (rdev->family == CHIP_CYPRESS) ||
2387 (rdev->family == CHIP_HEMLOCK) ||
2388 (rdev->family == CHIP_BARTS))
2389 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 2390 }
bcc1c2a1
AD		 2391 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
2392 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
2393 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
2394 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
2395 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
2396 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
2397 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
2398 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
2399 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2400 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
2401 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 2402 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 2403
0fcdb61e 2404 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 2405 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
2406 (unsigned)(rdev->mc.gtt_size >> 20),
2407 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 2408 rdev->gart.ready = true;
2409 return 0;
2410}
2411
1109ca09 2412static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
bcc1c2a1
AD		 2413{
2414 u32 tmp;
bcc1c2a1
AD		 2415
2416 /* Disable all tables */
0fcdb61e
AD		 2417 WREG32(VM_CONTEXT0_CNTL, 0);
2418 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 2419
2420 /* Setup L2 cache */
2421 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
2422 EFFECTIVE_L2_QUEUE_SIZE(7));
2423 WREG32(VM_L2_CNTL2, 0);
2424 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2425 /* Setup TLB control */
2426 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
2427 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
2428 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
2429 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
2430 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
2431 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
2432 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
2433 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 2434 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 2435}
2436
1109ca09 2437static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
bcc1c2a1
AD		 2438{
2439 evergreen_pcie_gart_disable(rdev);
2440 radeon_gart_table_vram_free(rdev);
2441 radeon_gart_fini(rdev);
2442}
2443
2444
1109ca09 2445static void evergreen_agp_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 2446{
2447 u32 tmp;
bcc1c2a1
AD		 2448
2449 /* Setup L2 cache */
2450 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
2451 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
2452 EFFECTIVE_L2_QUEUE_SIZE(7));
2453 WREG32(VM_L2_CNTL2, 0);
2454 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2455 /* Setup TLB control */
2456 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
2457 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
2458 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
2459 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
2460 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
2461 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
2462 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
2463 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
2464 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
2465 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
2466 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 2467 WREG32(VM_CONTEXT0_CNTL, 0);
2468 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 2469}
2470
b9952a8a 2471void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 2472{
62444b74
AD		 2473 u32 crtc_enabled, tmp, frame_count, blackout;
2474 int i, j;
2475
5153550a
AD		 2476 if (!ASIC_IS_NODCE(rdev)) {
2477 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
2478 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
bcc1c2a1 2479
5153550a
AD		 2480 /* disable VGA render */
2481 WREG32(VGA_RENDER_CONTROL, 0);
2482 }
62444b74
AD		 2483 /* blank the display controllers */
2484 for (i = 0; i < rdev->num_crtc; i++) {
2485 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
2486 if (crtc_enabled) {
2487 save->crtc_enabled[i] = true;
2488 if (ASIC_IS_DCE6(rdev)) {
2489 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
2490 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
2491 radeon_wait_for_vblank(rdev, i);
abf1457b 2492 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74
AD		 2493 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
2494 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
2495 }
2496 } else {
2497 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2498 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
2499 radeon_wait_for_vblank(rdev, i);
abf1457b 2500 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74
AD		 2501 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
2502 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
abf1457b 2503 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 2504 }
2505 }
2506 /* wait for the next frame */
2507 frame_count = radeon_get_vblank_counter(rdev, i);
2508 for (j = 0; j < rdev->usec_timeout; j++) {
2509 if (radeon_get_vblank_counter(rdev, i) != frame_count)
2510 break;
2511 udelay(1);
2512 }
abf1457b
AD		 2513
2514 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
2515 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2516 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2517 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
2518 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2519 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2520 save->crtc_enabled[i] = false;
2521 /* ***** */
804cc4a0
AD		 2522 } else {
2523 save->crtc_enabled[i] = false;
62444b74 2524 }
18007401 2525 }
bcc1c2a1 2526
62444b74
AD		 2527 radeon_mc_wait_for_idle(rdev);
2528
2529 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
2530 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
2531 /* Block CPU access */
2532 WREG32(BIF_FB_EN, 0);
2533 /* blackout the MC */
2534 blackout &= ~BLACKOUT_MODE_MASK;
2535 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
b7eff394 2536 }
ed39fadd
AD		 2537 /* wait for the MC to settle */
2538 udelay(100);
968c0166
AD		 2539
2540 /* lock double buffered regs */
2541 for (i = 0; i < rdev->num_crtc; i++) {
2542 if (save->crtc_enabled[i]) {
2543 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2544 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
2545 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
2546 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2547 }
2548 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2549 if (!(tmp & 1)) {
2550 tmp |= 1;
2551 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2552 }
2553 }
2554 }
bcc1c2a1
AD		 2555}
2556
b9952a8a 2557void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 2558{
62444b74
AD		 2559 u32 tmp, frame_count;
2560 int i, j;
18007401 2561
62444b74
AD		 2562 /* update crtc base addresses */
2563 for (i = 0; i < rdev->num_crtc; i++) {
2564 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 2565 upper_32_bits(rdev->mc.vram_start));
62444b74 2566 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 2567 upper_32_bits(rdev->mc.vram_start));
62444b74 2568 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401 2569 (u32)rdev->mc.vram_start);
62444b74 2570 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401
AD		 2571 (u32)rdev->mc.vram_start);
2572 }
5153550a
AD		 2573
2574 if (!ASIC_IS_NODCE(rdev)) {
2575 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
2576 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
2577 }
62444b74 2578
968c0166
AD		 2579 /* unlock regs and wait for update */
2580 for (i = 0; i < rdev->num_crtc; i++) {
2581 if (save->crtc_enabled[i]) {
2582 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
2583 if ((tmp & 0x3) != 0) {
2584 tmp &= ~0x3;
2585 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
2586 }
2587 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2588 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
2589 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
2590 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2591 }
2592 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2593 if (tmp & 1) {
2594 tmp &= ~1;
2595 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2596 }
2597 for (j = 0; j < rdev->usec_timeout; j++) {
2598 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2599 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
2600 break;
2601 udelay(1);
2602 }
2603 }
2604 }
2605
62444b74
AD		 2606 /* unblackout the MC */
2607 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
2608 tmp &= ~BLACKOUT_MODE_MASK;
2609 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
2610 /* allow CPU access */
2611 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
2612
2613 for (i = 0; i < rdev->num_crtc; i++) {
695ddeb4 2614 if (save->crtc_enabled[i]) {
62444b74
AD		 2615 if (ASIC_IS_DCE6(rdev)) {
2616 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
2617 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 2618 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 2619 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 2620 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 2621 } else {
2622 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2623 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 2624 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 2625 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 2626 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 2627 }
2628 /* wait for the next frame */
2629 frame_count = radeon_get_vblank_counter(rdev, i);
2630 for (j = 0; j < rdev->usec_timeout; j++) {
2631 if (radeon_get_vblank_counter(rdev, i) != frame_count)
2632 break;
2633 udelay(1);
2634 }
2635 }
2636 }
5153550a
AD		 2637 if (!ASIC_IS_NODCE(rdev)) {
2638 /* Unlock vga access */
2639 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
2640 mdelay(1);
2641 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
2642 }
bcc1c2a1
AD		 2643}
2644
755d819e 2645void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 2646{
2647 struct evergreen_mc_save save;
2648 u32 tmp;
2649 int i, j;
2650
2651 /* Initialize HDP */
2652 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2653 WREG32((0x2c14 + j), 0x00000000);
2654 WREG32((0x2c18 + j), 0x00000000);
2655 WREG32((0x2c1c + j), 0x00000000);
2656 WREG32((0x2c20 + j), 0x00000000);
2657 WREG32((0x2c24 + j), 0x00000000);
2658 }
2659 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2660
2661 evergreen_mc_stop(rdev, &save);
2662 if (evergreen_mc_wait_for_idle(rdev)) {
2663 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2664 }
2665 /* Lockout access through VGA aperture*/
2666 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2667 /* Update configuration */
2668 if (rdev->flags & RADEON_IS_AGP) {
2669 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
2670 /* VRAM before AGP */
2671 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2672 rdev->mc.vram_start >> 12);
2673 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2674 rdev->mc.gtt_end >> 12);
2675 } else {
2676 /* VRAM after AGP */
2677 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2678 rdev->mc.gtt_start >> 12);
2679 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2680 rdev->mc.vram_end >> 12);
2681 }
2682 } else {
2683 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2684 rdev->mc.vram_start >> 12);
2685 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2686 rdev->mc.vram_end >> 12);
2687 }
3b9832f6 2688 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 2689 /* llano/ontario only */
2690 if ((rdev->family == CHIP_PALM) ||
2691 (rdev->family == CHIP_SUMO) ||
2692 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 2693 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
2694 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
2695 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
2696 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
2697 }
bcc1c2a1
AD		 2698 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2699 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2700 WREG32(MC_VM_FB_LOCATION, tmp);
2701 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 2702 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 2703 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 2704 if (rdev->flags & RADEON_IS_AGP) {
2705 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
2706 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
2707 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
2708 } else {
2709 WREG32(MC_VM_AGP_BASE, 0);
2710 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
2711 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
2712 }
2713 if (evergreen_mc_wait_for_idle(rdev)) {
2714 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2715 }
2716 evergreen_mc_resume(rdev, &save);
2717 /* we need to own VRAM, so turn off the VGA renderer here
2718 * to stop it overwriting our objects */
2719 rv515_vga_render_disable(rdev);
2720}
2721
bcc1c2a1
AD		 2722/*
2723 * CP.
2724 */
12920591
AD		 2725void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2726{
876dc9f3 2727 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 2728 u32 next_rptr;
7b1f2485 2729
12920591 2730 /* set to DX10/11 mode */
e32eb50d
CK		 2731 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
2732 radeon_ring_write(ring, 1);
45df6803
CK		 2733
2734 if (ring->rptr_save_reg) {
89d35807 2735 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 2736 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2737 radeon_ring_write(ring, ((ring->rptr_save_reg -
2738 PACKET3_SET_CONFIG_REG_START) >> 2));
2739 radeon_ring_write(ring, next_rptr);
89d35807
AD		 2740 } else if (rdev->wb.enabled) {
2741 next_rptr = ring->wptr + 5 + 4;
2742 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2743 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2744 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2745 radeon_ring_write(ring, next_rptr);
2746 radeon_ring_write(ring, 0);
45df6803
CK		 2747 }
2748
e32eb50d
CK		 2749 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2750 radeon_ring_write(ring,
0f234f5f
AD		 2751#ifdef __BIG_ENDIAN
2752 (2 << 0) |
2753#endif
2754 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 2755 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2756 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 2757}
2758
bcc1c2a1
AD		 2759
2760static int evergreen_cp_load_microcode(struct radeon_device *rdev)
2761{
fe251e2f
AD		 2762 const __be32 *fw_data;
2763 int i;
2764
2765 if (!rdev->me_fw || !rdev->pfp_fw)
2766 return -EINVAL;
bcc1c2a1 2767
fe251e2f 2768 r700_cp_stop(rdev);
0f234f5f
AD		 2769 WREG32(CP_RB_CNTL,
2770#ifdef __BIG_ENDIAN
2771 BUF_SWAP_32BIT |
2772#endif
2773 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 2774
2775 fw_data = (const __be32 *)rdev->pfp_fw->data;
2776 WREG32(CP_PFP_UCODE_ADDR, 0);
2777 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
2778 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
2779 WREG32(CP_PFP_UCODE_ADDR, 0);
2780
2781 fw_data = (const __be32 *)rdev->me_fw->data;
2782 WREG32(CP_ME_RAM_WADDR, 0);
2783 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
2784 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
2785
2786 WREG32(CP_PFP_UCODE_ADDR, 0);
2787 WREG32(CP_ME_RAM_WADDR, 0);
2788 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 2789 return 0;
2790}
2791
7e7b41d2
AD		 2792static int evergreen_cp_start(struct radeon_device *rdev)
2793{
e32eb50d 2794 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 2795 int r, i;
7e7b41d2
AD		 2796 uint32_t cp_me;
2797
e32eb50d 2798 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 2799 if (r) {
2800 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2801 return r;
2802 }
e32eb50d
CK		 2803 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2804 radeon_ring_write(ring, 0x1);
2805 radeon_ring_write(ring, 0x0);
2806 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
2807 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2808 radeon_ring_write(ring, 0);
2809 radeon_ring_write(ring, 0);
2810 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 2811
2812 cp_me = 0xff;
2813 WREG32(CP_ME_CNTL, cp_me);
2814
e32eb50d 2815 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 2816 if (r) {
2817 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2818 return r;
2819 }
2281a378
AD		 2820
2821 /* setup clear context state */
e32eb50d
CK		 2822 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2823 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 2824
2825 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 2826 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 2827
e32eb50d
CK		 2828 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2829 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 2830
2831 /* set clear context state */
e32eb50d
CK		 2832 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2833 radeon_ring_write(ring, 0);
2281a378
AD		 2834
2835 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 2836 radeon_ring_write(ring, 0xc0026f00);
2837 radeon_ring_write(ring, 0x00000000);
2838 radeon_ring_write(ring, 0x00000000);
2839 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 2840
2841 /* Clear consts */
e32eb50d
CK		 2842 radeon_ring_write(ring, 0xc0036f00);
2843 radeon_ring_write(ring, 0x00000bc4);
2844 radeon_ring_write(ring, 0xffffffff);
2845 radeon_ring_write(ring, 0xffffffff);
2846 radeon_ring_write(ring, 0xffffffff);
2281a378 2847
e32eb50d
CK		 2848 radeon_ring_write(ring, 0xc0026900);
2849 radeon_ring_write(ring, 0x00000316);
2850 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2851 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 2852
e32eb50d 2853 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 2854
2855 return 0;
2856}
2857
1109ca09 2858static int evergreen_cp_resume(struct radeon_device *rdev)
fe251e2f 2859{
e32eb50d 2860 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 2861 u32 tmp;
2862 u32 rb_bufsz;
2863 int r;
2864
2865 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
2866 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
2867 SOFT_RESET_PA |
2868 SOFT_RESET_SH |
2869 SOFT_RESET_VGT |
a49a50da 2870 SOFT_RESET_SPI |
fe251e2f
AD		 2871 SOFT_RESET_SX));
2872 RREG32(GRBM_SOFT_RESET);
2873 mdelay(15);
2874 WREG32(GRBM_SOFT_RESET, 0);
2875 RREG32(GRBM_SOFT_RESET);
2876
2877 /* Set ring buffer size */
e32eb50d 2878 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 2879 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 2880#ifdef __BIG_ENDIAN
2881 tmp |= BUF_SWAP_32BIT;
32fcdbf4 2882#endif
fe251e2f 2883 WREG32(CP_RB_CNTL, tmp);
15d3332f 2884 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 2885 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 2886
2887 /* Set the write pointer delay */
2888 WREG32(CP_RB_WPTR_DELAY, 0);
2889
2890 /* Initialize the ring buffer's read and write pointers */
2891 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2892 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2893 ring->wptr = 0;
2894 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1 2895
48fc7f7e 2896 /* set the wb address whether it's enabled or not */
0f234f5f 2897 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 2898 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2899 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2900 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2901
2902 if (rdev->wb.enabled)
2903 WREG32(SCRATCH_UMSK, 0xff);
2904 else {
2905 tmp |= RB_NO_UPDATE;
2906 WREG32(SCRATCH_UMSK, 0);
2907 }
2908
fe251e2f
AD		 2909 mdelay(1);
2910 WREG32(CP_RB_CNTL, tmp);
2911
e32eb50d 2912 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 2913 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2914
e32eb50d 2915 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 2916
7e7b41d2 2917 evergreen_cp_start(rdev);
e32eb50d 2918 ring->ready = true;
f712812e 2919 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 2920 if (r) {
e32eb50d 2921 ring->ready = false;
fe251e2f
AD		 2922 return r;
2923 }
2924 return 0;
2925}
bcc1c2a1
AD		 2926
2927/*
2928 * Core functions
2929 */
bcc1c2a1
AD		 2930static void evergreen_gpu_init(struct radeon_device *rdev)
2931{
416a2bd2 2932 u32 gb_addr_config;
32fcdbf4 2933 u32 mc_shared_chmap, mc_arb_ramcfg;
32fcdbf4
AD		 2934 u32 sx_debug_1;
2935 u32 smx_dc_ctl0;
2936 u32 sq_config;
2937 u32 sq_lds_resource_mgmt;
2938 u32 sq_gpr_resource_mgmt_1;
2939 u32 sq_gpr_resource_mgmt_2;
2940 u32 sq_gpr_resource_mgmt_3;
2941 u32 sq_thread_resource_mgmt;
2942 u32 sq_thread_resource_mgmt_2;
2943 u32 sq_stack_resource_mgmt_1;
2944 u32 sq_stack_resource_mgmt_2;
2945 u32 sq_stack_resource_mgmt_3;
2946 u32 vgt_cache_invalidation;
f25a5c63 2947 u32 hdp_host_path_cntl, tmp;
416a2bd2 2948 u32 disabled_rb_mask;
32fcdbf4
AD		 2949 int i, j, num_shader_engines, ps_thread_count;
2950
2951 switch (rdev->family) {
2952 case CHIP_CYPRESS:
2953 case CHIP_HEMLOCK:
2954 rdev->config.evergreen.num_ses = 2;
2955 rdev->config.evergreen.max_pipes = 4;
2956 rdev->config.evergreen.max_tile_pipes = 8;
2957 rdev->config.evergreen.max_simds = 10;
2958 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
2959 rdev->config.evergreen.max_gprs = 256;
2960 rdev->config.evergreen.max_threads = 248;
2961 rdev->config.evergreen.max_gs_threads = 32;
2962 rdev->config.evergreen.max_stack_entries = 512;
2963 rdev->config.evergreen.sx_num_of_sets = 4;
2964 rdev->config.evergreen.sx_max_export_size = 256;
2965 rdev->config.evergreen.sx_max_export_pos_size = 64;
2966 rdev->config.evergreen.sx_max_export_smx_size = 192;
2967 rdev->config.evergreen.max_hw_contexts = 8;
2968 rdev->config.evergreen.sq_num_cf_insts = 2;
2969
2970 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2971 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2972 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2973 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2974 break;
2975 case CHIP_JUNIPER:
2976 rdev->config.evergreen.num_ses = 1;
2977 rdev->config.evergreen.max_pipes = 4;
2978 rdev->config.evergreen.max_tile_pipes = 4;
2979 rdev->config.evergreen.max_simds = 10;
2980 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
2981 rdev->config.evergreen.max_gprs = 256;
2982 rdev->config.evergreen.max_threads = 248;
2983 rdev->config.evergreen.max_gs_threads = 32;
2984 rdev->config.evergreen.max_stack_entries = 512;
2985 rdev->config.evergreen.sx_num_of_sets = 4;
2986 rdev->config.evergreen.sx_max_export_size = 256;
2987 rdev->config.evergreen.sx_max_export_pos_size = 64;
2988 rdev->config.evergreen.sx_max_export_smx_size = 192;
2989 rdev->config.evergreen.max_hw_contexts = 8;
2990 rdev->config.evergreen.sq_num_cf_insts = 2;
2991
2992 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2993 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2994 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2995 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2996 break;
2997 case CHIP_REDWOOD:
2998 rdev->config.evergreen.num_ses = 1;
2999 rdev->config.evergreen.max_pipes = 4;
3000 rdev->config.evergreen.max_tile_pipes = 4;
3001 rdev->config.evergreen.max_simds = 5;
3002 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3003 rdev->config.evergreen.max_gprs = 256;
3004 rdev->config.evergreen.max_threads = 248;
3005 rdev->config.evergreen.max_gs_threads = 32;
3006 rdev->config.evergreen.max_stack_entries = 256;
3007 rdev->config.evergreen.sx_num_of_sets = 4;
3008 rdev->config.evergreen.sx_max_export_size = 256;
3009 rdev->config.evergreen.sx_max_export_pos_size = 64;
3010 rdev->config.evergreen.sx_max_export_smx_size = 192;
3011 rdev->config.evergreen.max_hw_contexts = 8;
3012 rdev->config.evergreen.sq_num_cf_insts = 2;
3013
3014 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3015 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3016 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 3017 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 3018 break;
3019 case CHIP_CEDAR:
3020 default:
3021 rdev->config.evergreen.num_ses = 1;
3022 rdev->config.evergreen.max_pipes = 2;
3023 rdev->config.evergreen.max_tile_pipes = 2;
3024 rdev->config.evergreen.max_simds = 2;
3025 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3026 rdev->config.evergreen.max_gprs = 256;
3027 rdev->config.evergreen.max_threads = 192;
3028 rdev->config.evergreen.max_gs_threads = 16;
3029 rdev->config.evergreen.max_stack_entries = 256;
3030 rdev->config.evergreen.sx_num_of_sets = 4;
3031 rdev->config.evergreen.sx_max_export_size = 128;
3032 rdev->config.evergreen.sx_max_export_pos_size = 32;
3033 rdev->config.evergreen.sx_max_export_smx_size = 96;
3034 rdev->config.evergreen.max_hw_contexts = 4;
3035 rdev->config.evergreen.sq_num_cf_insts = 1;
3036
d5e455e4
AD		 3037 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3038 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3039 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 3040 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5e455e4
AD		 3041 break;
3042 case CHIP_PALM:
3043 rdev->config.evergreen.num_ses = 1;
3044 rdev->config.evergreen.max_pipes = 2;
3045 rdev->config.evergreen.max_tile_pipes = 2;
3046 rdev->config.evergreen.max_simds = 2;
3047 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3048 rdev->config.evergreen.max_gprs = 256;
3049 rdev->config.evergreen.max_threads = 192;
3050 rdev->config.evergreen.max_gs_threads = 16;
3051 rdev->config.evergreen.max_stack_entries = 256;
3052 rdev->config.evergreen.sx_num_of_sets = 4;
3053 rdev->config.evergreen.sx_max_export_size = 128;
3054 rdev->config.evergreen.sx_max_export_pos_size = 32;
3055 rdev->config.evergreen.sx_max_export_smx_size = 96;
3056 rdev->config.evergreen.max_hw_contexts = 4;
3057 rdev->config.evergreen.sq_num_cf_insts = 1;
3058
d5c5a72f
AD		 3059 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3060 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3061 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 3062 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 3063 break;
3064 case CHIP_SUMO:
3065 rdev->config.evergreen.num_ses = 1;
3066 rdev->config.evergreen.max_pipes = 4;
bd25f078 3067 rdev->config.evergreen.max_tile_pipes = 4;
d5c5a72f
AD		 3068 if (rdev->pdev->device == 0x9648)
3069 rdev->config.evergreen.max_simds = 3;
3070 else if ((rdev->pdev->device == 0x9647) ||
3071 (rdev->pdev->device == 0x964a))
3072 rdev->config.evergreen.max_simds = 4;
3073 else
3074 rdev->config.evergreen.max_simds = 5;
3075 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3076 rdev->config.evergreen.max_gprs = 256;
3077 rdev->config.evergreen.max_threads = 248;
3078 rdev->config.evergreen.max_gs_threads = 32;
3079 rdev->config.evergreen.max_stack_entries = 256;
3080 rdev->config.evergreen.sx_num_of_sets = 4;
3081 rdev->config.evergreen.sx_max_export_size = 256;
3082 rdev->config.evergreen.sx_max_export_pos_size = 64;
3083 rdev->config.evergreen.sx_max_export_smx_size = 192;
3084 rdev->config.evergreen.max_hw_contexts = 8;
3085 rdev->config.evergreen.sq_num_cf_insts = 2;
3086
3087 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3088 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3089 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 3090 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 3091 break;
3092 case CHIP_SUMO2:
3093 rdev->config.evergreen.num_ses = 1;
3094 rdev->config.evergreen.max_pipes = 4;
3095 rdev->config.evergreen.max_tile_pipes = 4;
3096 rdev->config.evergreen.max_simds = 2;
3097 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3098 rdev->config.evergreen.max_gprs = 256;
3099 rdev->config.evergreen.max_threads = 248;
3100 rdev->config.evergreen.max_gs_threads = 32;
3101 rdev->config.evergreen.max_stack_entries = 512;
3102 rdev->config.evergreen.sx_num_of_sets = 4;
3103 rdev->config.evergreen.sx_max_export_size = 256;
3104 rdev->config.evergreen.sx_max_export_pos_size = 64;
3105 rdev->config.evergreen.sx_max_export_smx_size = 192;
3106 rdev->config.evergreen.max_hw_contexts = 8;
3107 rdev->config.evergreen.sq_num_cf_insts = 2;
3108
adb68fa2
AD		 3109 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3110 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3111 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 3112 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 3113 break;
3114 case CHIP_BARTS:
3115 rdev->config.evergreen.num_ses = 2;
3116 rdev->config.evergreen.max_pipes = 4;
3117 rdev->config.evergreen.max_tile_pipes = 8;
3118 rdev->config.evergreen.max_simds = 7;
3119 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
3120 rdev->config.evergreen.max_gprs = 256;
3121 rdev->config.evergreen.max_threads = 248;
3122 rdev->config.evergreen.max_gs_threads = 32;
3123 rdev->config.evergreen.max_stack_entries = 512;
3124 rdev->config.evergreen.sx_num_of_sets = 4;
3125 rdev->config.evergreen.sx_max_export_size = 256;
3126 rdev->config.evergreen.sx_max_export_pos_size = 64;
3127 rdev->config.evergreen.sx_max_export_smx_size = 192;
3128 rdev->config.evergreen.max_hw_contexts = 8;
3129 rdev->config.evergreen.sq_num_cf_insts = 2;
3130
3131 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3132 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3133 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 3134 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 3135 break;
3136 case CHIP_TURKS:
3137 rdev->config.evergreen.num_ses = 1;
3138 rdev->config.evergreen.max_pipes = 4;
3139 rdev->config.evergreen.max_tile_pipes = 4;
3140 rdev->config.evergreen.max_simds = 6;
3141 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
3142 rdev->config.evergreen.max_gprs = 256;
3143 rdev->config.evergreen.max_threads = 248;
3144 rdev->config.evergreen.max_gs_threads = 32;
3145 rdev->config.evergreen.max_stack_entries = 256;
3146 rdev->config.evergreen.sx_num_of_sets = 4;
3147 rdev->config.evergreen.sx_max_export_size = 256;
3148 rdev->config.evergreen.sx_max_export_pos_size = 64;
3149 rdev->config.evergreen.sx_max_export_smx_size = 192;
3150 rdev->config.evergreen.max_hw_contexts = 8;
3151 rdev->config.evergreen.sq_num_cf_insts = 2;
3152
3153 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
3154 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3155 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 3156 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 3157 break;
3158 case CHIP_CAICOS:
3159 rdev->config.evergreen.num_ses = 1;
bd25f078 3160 rdev->config.evergreen.max_pipes = 2;
adb68fa2
AD		 3161 rdev->config.evergreen.max_tile_pipes = 2;
3162 rdev->config.evergreen.max_simds = 2;
3163 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
3164 rdev->config.evergreen.max_gprs = 256;
3165 rdev->config.evergreen.max_threads = 192;
3166 rdev->config.evergreen.max_gs_threads = 16;
3167 rdev->config.evergreen.max_stack_entries = 256;
3168 rdev->config.evergreen.sx_num_of_sets = 4;
3169 rdev->config.evergreen.sx_max_export_size = 128;
3170 rdev->config.evergreen.sx_max_export_pos_size = 32;
3171 rdev->config.evergreen.sx_max_export_smx_size = 96;
3172 rdev->config.evergreen.max_hw_contexts = 4;
3173 rdev->config.evergreen.sq_num_cf_insts = 1;
3174
32fcdbf4
AD		 3175 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3176 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3177 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 3178 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 3179 break;
3180 }
3181
3182 /* Initialize HDP */
3183 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3184 WREG32((0x2c14 + j), 0x00000000);
3185 WREG32((0x2c18 + j), 0x00000000);
3186 WREG32((0x2c1c + j), 0x00000000);
3187 WREG32((0x2c20 + j), 0x00000000);
3188 WREG32((0x2c24 + j), 0x00000000);
3189 }
3190
3191 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3192
d054ac16
AD		 3193 evergreen_fix_pci_max_read_req_size(rdev);
3194
32fcdbf4 3195 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 3196 if ((rdev->family == CHIP_PALM) ||
3197 (rdev->family == CHIP_SUMO) ||
3198 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 3199 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
3200 else
3201 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4 3202
1aa52bd3
AD		 3203 /* setup tiling info dword. gb_addr_config is not adequate since it does
3204 * not have bank info, so create a custom tiling dword.
3205 * bits 3:0 num_pipes
3206 * bits 7:4 num_banks
3207 * bits 11:8 group_size
3208 * bits 15:12 row_size
3209 */
3210 rdev->config.evergreen.tile_config = 0;
3211 switch (rdev->config.evergreen.max_tile_pipes) {
3212 case 1:
3213 default:
3214 rdev->config.evergreen.tile_config |= (0 << 0);
3215 break;
3216 case 2:
3217 rdev->config.evergreen.tile_config |= (1 << 0);
3218 break;
3219 case 4:
3220 rdev->config.evergreen.tile_config |= (2 << 0);
3221 break;
3222 case 8:
3223 rdev->config.evergreen.tile_config |= (3 << 0);
3224 break;
3225 }
d698a34d 3226 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 3227 if (rdev->flags & RADEON_IS_IGP)
d698a34d 3228 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406 3229 else {
c8d15edc
AD		 3230 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3231 case 0: /* four banks */
29d65406 3232 rdev->config.evergreen.tile_config |= 0 << 4;
c8d15edc
AD		 3233 break;
3234 case 1: /* eight banks */
3235 rdev->config.evergreen.tile_config |= 1 << 4;
3236 break;
3237 case 2: /* sixteen banks */
3238 default:
3239 rdev->config.evergreen.tile_config |= 2 << 4;
3240 break;
3241 }
29d65406 3242 }
416a2bd2 3243 rdev->config.evergreen.tile_config |= 0 << 8;
1aa52bd3
AD		 3244 rdev->config.evergreen.tile_config |=
3245 ((gb_addr_config & 0x30000000) >> 28) << 12;
3246
416a2bd2 3247 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
32fcdbf4 3248
416a2bd2
AD		 3249 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
3250 u32 efuse_straps_4;
3251 u32 efuse_straps_3;
32fcdbf4 3252
ff82bbc4
AD		 3253 efuse_straps_4 = RREG32_RCU(0x204);
3254 efuse_straps_3 = RREG32_RCU(0x203);
416a2bd2
AD		 3255 tmp = (((efuse_straps_4 & 0xf) << 4) |
3256 ((efuse_straps_3 & 0xf0000000) >> 28));
3257 } else {
3258 tmp = 0;
3259 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
3260 u32 rb_disable_bitmap;
3261
3262 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3263 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
3264 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
3265 tmp <<= 4;
3266 tmp |= rb_disable_bitmap;
32fcdbf4 3267 }
416a2bd2
AD		 3268 }
3269 /* enabled rb are just the one not disabled :) */
3270 disabled_rb_mask = tmp;
cedb655a
AD		 3271 tmp = 0;
3272 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3273 tmp |= (1 << i);
3274 /* if all the backends are disabled, fix it up here */
3275 if ((disabled_rb_mask & tmp) == tmp) {
3276 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
3277 disabled_rb_mask &= ~(1 << i);
3278 }
32fcdbf4 3279
416a2bd2
AD		 3280 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
3281 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
32fcdbf4 3282
416a2bd2
AD		 3283 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3284 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3285 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
233d1ad5 3286 WREG32(DMA_TILING_CONFIG, gb_addr_config);
9a21059d
CK		 3287 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3288 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3289 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
32fcdbf4 3290
f7eb9730
AD		 3291 if ((rdev->config.evergreen.max_backends == 1) &&
3292 (rdev->flags & RADEON_IS_IGP)) {
3293 if ((disabled_rb_mask & 3) == 1) {
3294 /* RB0 disabled, RB1 enabled */
3295 tmp = 0x11111111;
3296 } else {
3297 /* RB1 disabled, RB0 enabled */
3298 tmp = 0x00000000;
3299 }
3300 } else {
3301 tmp = gb_addr_config & NUM_PIPES_MASK;
3302 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
3303 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
3304 }
416a2bd2 3305 WREG32(GB_BACKEND_MAP, tmp);
32fcdbf4
AD		 3306
3307 WREG32(CGTS_SYS_TCC_DISABLE, 0);
3308 WREG32(CGTS_TCC_DISABLE, 0);
3309 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
3310 WREG32(CGTS_USER_TCC_DISABLE, 0);
3311
3312 /* set HW defaults for 3D engine */
3313 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3314 ROQ_IB2_START(0x2b)));
3315
3316 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
3317
3318 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
3319 SYNC_GRADIENT |
3320 SYNC_WALKER |
3321 SYNC_ALIGNER));
3322
3323 sx_debug_1 = RREG32(SX_DEBUG_1);
3324 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
3325 WREG32(SX_DEBUG_1, sx_debug_1);
3326
3327
3328 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
3329 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
3330 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
3331 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
3332
b866d133
AD		 3333 if (rdev->family <= CHIP_SUMO2)
3334 WREG32(SMX_SAR_CTL0, 0x00010000);
3335
32fcdbf4
AD		 3336 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
3337 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
3338 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
3339
3340 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
3341 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
3342 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
3343
3344 WREG32(VGT_NUM_INSTANCES, 1);
3345 WREG32(SPI_CONFIG_CNTL, 0);
3346 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3347 WREG32(CP_PERFMON_CNTL, 0);
3348
3349 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
3350 FETCH_FIFO_HIWATER(0x4) |
3351 DONE_FIFO_HIWATER(0xe0) |
3352 ALU_UPDATE_FIFO_HIWATER(0x8)));
3353
3354 sq_config = RREG32(SQ_CONFIG);
3355 sq_config &= ~(PS_PRIO(3) |
3356 VS_PRIO(3) |
3357 GS_PRIO(3) |
3358 ES_PRIO(3));
3359 sq_config |= (VC_ENABLE |
3360 EXPORT_SRC_C |
3361 PS_PRIO(0) |
3362 VS_PRIO(1) |
3363 GS_PRIO(2) |
3364 ES_PRIO(3));
3365
d5e455e4
AD		 3366 switch (rdev->family) {
3367 case CHIP_CEDAR:
3368 case CHIP_PALM:
d5c5a72f
AD		 3369 case CHIP_SUMO:
3370 case CHIP_SUMO2:
adb68fa2 3371 case CHIP_CAICOS:
32fcdbf4
AD		 3372 /* no vertex cache */
3373 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 3374 break;
3375 default:
3376 break;
3377 }
32fcdbf4
AD		 3378
3379 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
3380
3381 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
3382 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
3383 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
3384 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
3385 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
3386 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
3387 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
3388
d5e455e4
AD		 3389 switch (rdev->family) {
3390 case CHIP_CEDAR:
3391 case CHIP_PALM:
d5c5a72f
AD		 3392 case CHIP_SUMO:
3393 case CHIP_SUMO2:
32fcdbf4 3394 ps_thread_count = 96;
d5e455e4
AD		 3395 break;
3396 default:
32fcdbf4 3397 ps_thread_count = 128;
d5e455e4
AD		 3398 break;
3399 }
32fcdbf4
AD		 3400
3401 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 3402 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3403 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3404 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3405 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
3406 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 3407
3408 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3409 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3410 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3411 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3412 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3413 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
3414
3415 WREG32(SQ_CONFIG, sq_config);
3416 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
3417 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
3418 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
3419 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
3420 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
3421 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
3422 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
3423 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
3424 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
3425 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
3426
3427 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3428 FORCE_EOV_MAX_REZ_CNT(255)));
3429
d5e455e4
AD		 3430 switch (rdev->family) {
3431 case CHIP_CEDAR:
3432 case CHIP_PALM:
d5c5a72f
AD		 3433 case CHIP_SUMO:
3434 case CHIP_SUMO2:
adb68fa2 3435 case CHIP_CAICOS:
32fcdbf4 3436 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 3437 break;
3438 default:
32fcdbf4 3439 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 3440 break;
3441 }
32fcdbf4
AD		 3442 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
3443 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
3444
3445 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 3446 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 3447 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3448
60a4a3e0
AD		 3449 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3450 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
3451
32fcdbf4
AD		 3452 WREG32(CB_PERF_CTR0_SEL_0, 0);
3453 WREG32(CB_PERF_CTR0_SEL_1, 0);
3454 WREG32(CB_PERF_CTR1_SEL_0, 0);
3455 WREG32(CB_PERF_CTR1_SEL_1, 0);
3456 WREG32(CB_PERF_CTR2_SEL_0, 0);
3457 WREG32(CB_PERF_CTR2_SEL_1, 0);
3458 WREG32(CB_PERF_CTR3_SEL_0, 0);
3459 WREG32(CB_PERF_CTR3_SEL_1, 0);
3460
60a4a3e0
AD		 3461 /* clear render buffer base addresses */
3462 WREG32(CB_COLOR0_BASE, 0);
3463 WREG32(CB_COLOR1_BASE, 0);
3464 WREG32(CB_COLOR2_BASE, 0);
3465 WREG32(CB_COLOR3_BASE, 0);
3466 WREG32(CB_COLOR4_BASE, 0);
3467 WREG32(CB_COLOR5_BASE, 0);
3468 WREG32(CB_COLOR6_BASE, 0);
3469 WREG32(CB_COLOR7_BASE, 0);
3470 WREG32(CB_COLOR8_BASE, 0);
3471 WREG32(CB_COLOR9_BASE, 0);
3472 WREG32(CB_COLOR10_BASE, 0);
3473 WREG32(CB_COLOR11_BASE, 0);
3474
3475 /* set the shader const cache sizes to 0 */
3476 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
3477 WREG32(i, 0);
3478 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
3479 WREG32(i, 0);
3480
f25a5c63
AD		 3481 tmp = RREG32(HDP_MISC_CNTL);
3482 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3483 WREG32(HDP_MISC_CNTL, tmp);
3484
32fcdbf4
AD		 3485 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3486 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3487
3488 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3489
3490 udelay(50);
3491
bcc1c2a1
AD		 3492}
3493
3494int evergreen_mc_init(struct radeon_device *rdev)
3495{
bcc1c2a1
AD		 3496 u32 tmp;
3497 int chansize, numchan;
bcc1c2a1
AD		 3498
3499 /* Get VRAM informations */
3500 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 3501 if ((rdev->family == CHIP_PALM) ||
3502 (rdev->family == CHIP_SUMO) ||
3503 (rdev->family == CHIP_SUMO2))
8208441b
AD		 3504 tmp = RREG32(FUS_MC_ARB_RAMCFG);
3505 else
3506 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 3507 if (tmp & CHANSIZE_OVERRIDE) {
3508 chansize = 16;
3509 } else if (tmp & CHANSIZE_MASK) {
3510 chansize = 64;
3511 } else {
3512 chansize = 32;
3513 }
3514 tmp = RREG32(MC_SHARED_CHMAP);
3515 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
3516 case 0:
3517 default:
3518 numchan = 1;
3519 break;
3520 case 1:
3521 numchan = 2;
3522 break;
3523 case 2:
3524 numchan = 4;
3525 break;
3526 case 3:
3527 numchan = 8;
3528 break;
3529 }
3530 rdev->mc.vram_width = numchan * chansize;
3531 /* Could aper size report 0 ? */
01d73a69
JC		 3532 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3533 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 3534 /* Setup GPU memory space */
05b3ef69
AD		 3535 if ((rdev->family == CHIP_PALM) ||
3536 (rdev->family == CHIP_SUMO) ||
3537 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 3538 /* size in bytes on fusion */
3539 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
3540 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
3541 } else {
05b3ef69 3542 /* size in MB on evergreen/cayman/tn */
fc986034
NOS		 3543 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3544 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
6eb18f8b 3545 }
51e5fcd3 3546 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 3547 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 3548 radeon_update_bandwidth_info(rdev);
3549
bcc1c2a1
AD		 3550 return 0;
3551}
d594e46a 3552
187e3593 3553void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
bcc1c2a1 3554{
64c56e8c 3555 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
747943ea 3556 RREG32(GRBM_STATUS));
64c56e8c 3557 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
747943ea 3558 RREG32(GRBM_STATUS_SE0));
64c56e8c 3559 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
747943ea 3560 RREG32(GRBM_STATUS_SE1));
64c56e8c 3561 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
747943ea 3562 RREG32(SRBM_STATUS));
a65a4369
AD		 3563 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
3564 RREG32(SRBM_STATUS2));
440a7cd8
JG		 3565 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
3566 RREG32(CP_STALLED_STAT1));
3567 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
3568 RREG32(CP_STALLED_STAT2));
3569 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
3570 RREG32(CP_BUSY_STAT));
3571 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
3572 RREG32(CP_STAT));
eaaa6983
JG		 3573 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
3574 RREG32(DMA_STATUS_REG));
168757ea
AD		 3575 if (rdev->family >= CHIP_CAYMAN) {
3576 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
3577 RREG32(DMA_STATUS_REG + 0x800));
3578 }
0ecebb9e
AD		 3579}
3580
168757ea 3581bool evergreen_is_display_hung(struct radeon_device *rdev)
0ecebb9e 3582{
a65a4369
AD		 3583 u32 crtc_hung = 0;
3584 u32 crtc_status[6];
3585 u32 i, j, tmp;
3586
3587 for (i = 0; i < rdev->num_crtc; i++) {
3588 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
3589 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
3590 crtc_hung |= (1 << i);
3591 }
3592 }
3593
3594 for (j = 0; j < 10; j++) {
3595 for (i = 0; i < rdev->num_crtc; i++) {
3596 if (crtc_hung & (1 << i)) {
3597 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
3598 if (tmp != crtc_status[i])
3599 crtc_hung &= ~(1 << i);
3600 }
3601 }
3602 if (crtc_hung == 0)
3603 return false;
3604 udelay(100);
3605 }
3606
3607 return true;
3608}
3609
3610static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
3611{
3612 u32 reset_mask = 0;
b7630473 3613 u32 tmp;
0ecebb9e 3614
a65a4369
AD		 3615 /* GRBM_STATUS */
3616 tmp = RREG32(GRBM_STATUS);
3617 if (tmp & (PA_BUSY | SC_BUSY |
3618 SH_BUSY | SX_BUSY |
3619 TA_BUSY | VGT_BUSY |
3620 DB_BUSY | CB_BUSY |
3621 SPI_BUSY | VGT_BUSY_NO_DMA))
3622 reset_mask |= RADEON_RESET_GFX;
3623
3624 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3625 CP_BUSY | CP_COHERENCY_BUSY))
3626 reset_mask |= RADEON_RESET_CP;
3627
3628 if (tmp & GRBM_EE_BUSY)
3629 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
19fc42ed 3630
a65a4369
AD		 3631 /* DMA_STATUS_REG */
3632 tmp = RREG32(DMA_STATUS_REG);
3633 if (!(tmp & DMA_IDLE))
3634 reset_mask |= RADEON_RESET_DMA;
3635
3636 /* SRBM_STATUS2 */
3637 tmp = RREG32(SRBM_STATUS2);
3638 if (tmp & DMA_BUSY)
3639 reset_mask |= RADEON_RESET_DMA;
3640
3641 /* SRBM_STATUS */
3642 tmp = RREG32(SRBM_STATUS);
3643 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3644 reset_mask |= RADEON_RESET_RLC;
3645
3646 if (tmp & IH_BUSY)
3647 reset_mask |= RADEON_RESET_IH;
3648
3649 if (tmp & SEM_BUSY)
3650 reset_mask |= RADEON_RESET_SEM;
3651
3652 if (tmp & GRBM_RQ_PENDING)
3653 reset_mask |= RADEON_RESET_GRBM;
3654
3655 if (tmp & VMC_BUSY)
3656 reset_mask |= RADEON_RESET_VMC;
3657
3658 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3659 MCC_BUSY | MCD_BUSY))
3660 reset_mask |= RADEON_RESET_MC;
3661
3662 if (evergreen_is_display_hung(rdev))
3663 reset_mask |= RADEON_RESET_DISPLAY;
3664
3665 /* VM_L2_STATUS */
3666 tmp = RREG32(VM_L2_STATUS);
3667 if (tmp & L2_BUSY)
3668 reset_mask |= RADEON_RESET_VMC;
3669
d808fc88
AD		 3670 /* Skip MC reset as it's mostly likely not hung, just busy */
3671 if (reset_mask & RADEON_RESET_MC) {
3672 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3673 reset_mask &= ~RADEON_RESET_MC;
3674 }
3675
a65a4369
AD		 3676 return reset_mask;
3677}
3678
3679static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3680{
3681 struct evergreen_mc_save save;
3682 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3683 u32 tmp;
19fc42ed 3684
0ecebb9e 3685 if (reset_mask == 0)
a65a4369 3686 return;
0ecebb9e
AD		 3687
3688 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3689
b7630473
AD		 3690 evergreen_print_gpu_status_regs(rdev);
3691
b7630473
AD		 3692 /* Disable CP parsing/prefetching */
3693 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
3694
3695 if (reset_mask & RADEON_RESET_DMA) {
3696 /* Disable DMA */
3697 tmp = RREG32(DMA_RB_CNTL);
3698 tmp &= ~DMA_RB_ENABLE;
3699 WREG32(DMA_RB_CNTL, tmp);
3700 }
3701
b21b6e7a
AD		 3702 udelay(50);
3703
3704 evergreen_mc_stop(rdev, &save);
3705 if (evergreen_mc_wait_for_idle(rdev)) {
3706 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3707 }
3708
b7630473
AD		 3709 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
3710 grbm_soft_reset |= SOFT_RESET_DB |
3711 SOFT_RESET_CB |
3712 SOFT_RESET_PA |
3713 SOFT_RESET_SC |
3714 SOFT_RESET_SPI |
3715 SOFT_RESET_SX |
3716 SOFT_RESET_SH |
3717 SOFT_RESET_TC |
3718 SOFT_RESET_TA |
3719 SOFT_RESET_VC |
3720 SOFT_RESET_VGT;
3721 }
3722
3723 if (reset_mask & RADEON_RESET_CP) {
3724 grbm_soft_reset |= SOFT_RESET_CP |
3725 SOFT_RESET_VGT;
3726
3727 srbm_soft_reset |= SOFT_RESET_GRBM;
3728 }
0ecebb9e
AD		 3729
3730 if (reset_mask & RADEON_RESET_DMA)
b7630473
AD		 3731 srbm_soft_reset |= SOFT_RESET_DMA;
3732
a65a4369
AD		 3733 if (reset_mask & RADEON_RESET_DISPLAY)
3734 srbm_soft_reset |= SOFT_RESET_DC;
3735
3736 if (reset_mask & RADEON_RESET_RLC)
3737 srbm_soft_reset |= SOFT_RESET_RLC;
3738
3739 if (reset_mask & RADEON_RESET_SEM)
3740 srbm_soft_reset |= SOFT_RESET_SEM;
3741
3742 if (reset_mask & RADEON_RESET_IH)
3743 srbm_soft_reset |= SOFT_RESET_IH;
3744
3745 if (reset_mask & RADEON_RESET_GRBM)
3746 srbm_soft_reset |= SOFT_RESET_GRBM;
3747
3748 if (reset_mask & RADEON_RESET_VMC)
3749 srbm_soft_reset |= SOFT_RESET_VMC;
3750
24178ec4
AD		 3751 if (!(rdev->flags & RADEON_IS_IGP)) {
3752 if (reset_mask & RADEON_RESET_MC)
3753 srbm_soft_reset |= SOFT_RESET_MC;
3754 }
a65a4369 3755
b7630473
AD		 3756 if (grbm_soft_reset) {
3757 tmp = RREG32(GRBM_SOFT_RESET);
3758 tmp |= grbm_soft_reset;
3759 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3760 WREG32(GRBM_SOFT_RESET, tmp);
3761 tmp = RREG32(GRBM_SOFT_RESET);
3762
3763 udelay(50);
3764
3765 tmp &= ~grbm_soft_reset;
3766 WREG32(GRBM_SOFT_RESET, tmp);
3767 tmp = RREG32(GRBM_SOFT_RESET);
3768 }
3769
3770 if (srbm_soft_reset) {
3771 tmp = RREG32(SRBM_SOFT_RESET);
3772 tmp |= srbm_soft_reset;
3773 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3774 WREG32(SRBM_SOFT_RESET, tmp);
3775 tmp = RREG32(SRBM_SOFT_RESET);
3776
3777 udelay(50);
3778
3779 tmp &= ~srbm_soft_reset;
3780 WREG32(SRBM_SOFT_RESET, tmp);
3781 tmp = RREG32(SRBM_SOFT_RESET);
3782 }
0ecebb9e
AD		 3783
3784 /* Wait a little for things to settle down */
3785 udelay(50);
3786
747943ea 3787 evergreen_mc_resume(rdev, &save);
b7630473
AD		 3788 udelay(50);
3789
b7630473 3790 evergreen_print_gpu_status_regs(rdev);
bcc1c2a1
AD		 3791}
3792
a2d07b74 3793int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 3794{
a65a4369
AD		 3795 u32 reset_mask;
3796
3797 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3798
3799 if (reset_mask)
3800 r600_set_bios_scratch_engine_hung(rdev, true);
3801
3802 evergreen_gpu_soft_reset(rdev, reset_mask);
3803
3804 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3805
3806 if (!reset_mask)
3807 r600_set_bios_scratch_engine_hung(rdev, false);
3808
3809 return 0;
747943ea
AD		 3810}
3811
123bc183
AD		 3812/**
3813 * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
3814 *
3815 * @rdev: radeon_device pointer
3816 * @ring: radeon_ring structure holding ring information
3817 *
3818 * Check if the GFX engine is locked up.
3819 * Returns true if the engine appears to be locked up, false if not.
3820 */
3821bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3822{
3823 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3824
3825 if (!(reset_mask & (RADEON_RESET_GFX |
3826 RADEON_RESET_COMPUTE |
3827 RADEON_RESET_CP))) {
3828 radeon_ring_lockup_update(ring);
3829 return false;
3830 }
3831 /* force CP activities */
3832 radeon_ring_force_activity(rdev, ring);
3833 return radeon_ring_test_lockup(rdev, ring);
3834}
3835
3836/**
3837 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
3838 *
3839 * @rdev: radeon_device pointer
3840 * @ring: radeon_ring structure holding ring information
3841 *
3842 * Check if the async DMA engine is locked up.
3843 * Returns true if the engine appears to be locked up, false if not.
3844 */
3845bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3846{
3847 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3848
3849 if (!(reset_mask & RADEON_RESET_DMA)) {
3850 radeon_ring_lockup_update(ring);
3851 return false;
3852 }
3853 /* force ring activities */
3854 radeon_ring_force_activity(rdev, ring);
3855 return radeon_ring_test_lockup(rdev, ring);
3856}
3857
2948f5e6
AD		 3858/*
3859 * RLC
3860 */
3861#define RLC_SAVE_RESTORE_LIST_END_MARKER 0x00000000
3862#define RLC_CLEAR_STATE_END_MARKER 0x00000001
3863
3864void sumo_rlc_fini(struct radeon_device *rdev)
3865{
3866 int r;
3867
3868 /* save restore block */
3869 if (rdev->rlc.save_restore_obj) {
3870 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3871 if (unlikely(r != 0))
3872 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);
3873 radeon_bo_unpin(rdev->rlc.save_restore_obj);
3874 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3875
3876 radeon_bo_unref(&rdev->rlc.save_restore_obj);
3877 rdev->rlc.save_restore_obj = NULL;
3878 }
3879
3880 /* clear state block */
3881 if (rdev->rlc.clear_state_obj) {
3882 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3883 if (unlikely(r != 0))
3884 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);
3885 radeon_bo_unpin(rdev->rlc.clear_state_obj);
3886 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3887
3888 radeon_bo_unref(&rdev->rlc.clear_state_obj);
3889 rdev->rlc.clear_state_obj = NULL;
3890 }
3891}
3892
3893int sumo_rlc_init(struct radeon_device *rdev)
3894{
3895 u32 *src_ptr;
3896 volatile u32 *dst_ptr;
3897 u32 dws, data, i, j, k, reg_num;
3898 u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index;
3899 u64 reg_list_mc_addr;
3900 struct cs_section_def *cs_data;
3901 int r;
3902
3903 src_ptr = rdev->rlc.reg_list;
3904 dws = rdev->rlc.reg_list_size;
3905 cs_data = rdev->rlc.cs_data;
3906
3907 /* save restore block */
3908 if (rdev->rlc.save_restore_obj == NULL) {
3909 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
3910 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.save_restore_obj);
3911 if (r) {
3912 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);
3913 return r;
3914 }
3915 }
3916
3917 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
3918 if (unlikely(r != 0)) {
3919 sumo_rlc_fini(rdev);
3920 return r;
3921 }
3922 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
3923 &rdev->rlc.save_restore_gpu_addr);
3924 if (r) {
3925 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3926 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
3927 sumo_rlc_fini(rdev);
3928 return r;
3929 }
3930 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
3931 if (r) {
3932 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);
3933 sumo_rlc_fini(rdev);
3934 return r;
3935 }
3936 /* write the sr buffer */
3937 dst_ptr = rdev->rlc.sr_ptr;
3938 /* format:
3939 * dw0: (reg2 << 16) | reg1
3940 * dw1: reg1 save space
3941 * dw2: reg2 save space
3942 */
3943 for (i = 0; i < dws; i++) {
3944 data = src_ptr[i] >> 2;
3945 i++;
3946 if (i < dws)
3947 data |= (src_ptr[i] >> 2) << 16;
3948 j = (((i - 1) * 3) / 2);
3949 dst_ptr[j] = data;
3950 }
3951 j = ((i * 3) / 2);
3952 dst_ptr[j] = RLC_SAVE_RESTORE_LIST_END_MARKER;
3953
3954 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
3955 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
3956
3957 /* clear state block */
3958 reg_list_num = 0;
3959 dws = 0;
3960 for (i = 0; cs_data[i].section != NULL; i++) {
3961 for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
3962 reg_list_num++;
3963 dws += cs_data[i].section[j].reg_count;
3964 }
3965 }
3966 reg_list_blk_index = (3 * reg_list_num + 2);
3967 dws += reg_list_blk_index;
3968
3969 if (rdev->rlc.clear_state_obj == NULL) {
3970 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
3971 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->rlc.clear_state_obj);
3972 if (r) {
3973 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
3974 sumo_rlc_fini(rdev);
3975 return r;
3976 }
3977 }
3978 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
3979 if (unlikely(r != 0)) {
3980 sumo_rlc_fini(rdev);
3981 return r;
3982 }
3983 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
3984 &rdev->rlc.clear_state_gpu_addr);
3985 if (r) {
3986
3987 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
3988 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
3989 sumo_rlc_fini(rdev);
3990 return r;
3991 }
3992 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
3993 if (r) {
3994 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);
3995 sumo_rlc_fini(rdev);
3996 return r;
3997 }
3998 /* set up the cs buffer */
3999 dst_ptr = rdev->rlc.cs_ptr;
4000 reg_list_hdr_blk_index = 0;
4001 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
4002 data = upper_32_bits(reg_list_mc_addr);
4003 dst_ptr[reg_list_hdr_blk_index] = data;
4004 reg_list_hdr_blk_index++;
4005 for (i = 0; cs_data[i].section != NULL; i++) {
4006 for (j = 0; cs_data[i].section[j].extent != NULL; j++) {
4007 reg_num = cs_data[i].section[j].reg_count;
4008 data = reg_list_mc_addr & 0xffffffff;
4009 dst_ptr[reg_list_hdr_blk_index] = data;
4010 reg_list_hdr_blk_index++;
4011
4012 data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;
4013 dst_ptr[reg_list_hdr_blk_index] = data;
4014 reg_list_hdr_blk_index++;
4015
4016 data = 0x08000000 | (reg_num * 4);
4017 dst_ptr[reg_list_hdr_blk_index] = data;
4018 reg_list_hdr_blk_index++;
4019
4020 for (k = 0; k < reg_num; k++) {
4021 data = cs_data[i].section[j].extent[k];
4022 dst_ptr[reg_list_blk_index + k] = data;
4023 }
4024 reg_list_mc_addr += reg_num * 4;
4025 reg_list_blk_index += reg_num;
4026 }
4027 }
4028 dst_ptr[reg_list_hdr_blk_index] = RLC_CLEAR_STATE_END_MARKER;
4029
4030 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
4031 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4032
4033 return 0;
4034}
4035
4036static void evergreen_rlc_start(struct radeon_device *rdev)
4037{
4038 if (rdev->flags & RADEON_IS_IGP)
4039 WREG32(RLC_CNTL, RLC_ENABLE | GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC);
4040 else
4041 WREG32(RLC_CNTL, RLC_ENABLE);
4042}
4043
4044int evergreen_rlc_resume(struct radeon_device *rdev)
4045{
4046 u32 i;
4047 const __be32 *fw_data;
4048
4049 if (!rdev->rlc_fw)
4050 return -EINVAL;
4051
4052 r600_rlc_stop(rdev);
4053
4054 WREG32(RLC_HB_CNTL, 0);
4055
4056 if (rdev->flags & RADEON_IS_IGP) {
4057 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4058 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
4059 } else {
4060 WREG32(RLC_HB_BASE, 0);
4061 WREG32(RLC_HB_RPTR, 0);
4062 WREG32(RLC_HB_WPTR, 0);
4063 }
4064 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
4065 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
4066 WREG32(RLC_MC_CNTL, 0);
4067 WREG32(RLC_UCODE_CNTL, 0);
4068
4069 fw_data = (const __be32 *)rdev->rlc_fw->data;
4070 if (rdev->family >= CHIP_ARUBA) {
4071 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
4072 WREG32(RLC_UCODE_ADDR, i);
4073 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4074 }
4075 } else if (rdev->family >= CHIP_CAYMAN) {
4076 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
4077 WREG32(RLC_UCODE_ADDR, i);
4078 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4079 }
4080 } else {
4081 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
4082 WREG32(RLC_UCODE_ADDR, i);
4083 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
4084 }
4085 }
4086 WREG32(RLC_UCODE_ADDR, 0);
4087
4088 evergreen_rlc_start(rdev);
4089
4090 return 0;
4091}
4092
45f9a39b
AD		 4093/* Interrupts */
4094
4095u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
4096{
46437057 4097 if (crtc >= rdev->num_crtc)
45f9a39b 4098 return 0;
46437057
AD		 4099 else
4100 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
45f9a39b
AD		 4101}
4102
4103void evergreen_disable_interrupt_state(struct radeon_device *rdev)
4104{
4105 u32 tmp;
4106
1b37078b
AD		 4107 if (rdev->family >= CHIP_CAYMAN) {
4108 cayman_cp_int_cntl_setup(rdev, 0,
4109 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4110 cayman_cp_int_cntl_setup(rdev, 1, 0);
4111 cayman_cp_int_cntl_setup(rdev, 2, 0);
f60cbd11
AD		 4112 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
4113 WREG32(CAYMAN_DMA1_CNTL, tmp);
1b37078b
AD		 4114 } else
4115 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
233d1ad5
AD		 4116 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4117 WREG32(DMA_CNTL, tmp);
45f9a39b
AD		 4118 WREG32(GRBM_INT_CNTL, 0);
4119 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4120 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 4121 if (rdev->num_crtc >= 4) {
18007401
AD		 4122 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
4123 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 4124 }
4125 if (rdev->num_crtc >= 6) {
18007401
AD		 4126 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
4127 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4128 }
45f9a39b
AD		 4129
4130 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4131 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 4132 if (rdev->num_crtc >= 4) {
18007401
AD		 4133 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
4134 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 4135 }
4136 if (rdev->num_crtc >= 6) {
18007401
AD		 4137 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
4138 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4139 }
45f9a39b 4140
05b3ef69
AD		 4141 /* only one DAC on DCE6 */
4142 if (!ASIC_IS_DCE6(rdev))
4143 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 4144 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
4145
4146 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4147 WREG32(DC_HPD1_INT_CONTROL, tmp);
4148 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4149 WREG32(DC_HPD2_INT_CONTROL, tmp);
4150 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4151 WREG32(DC_HPD3_INT_CONTROL, tmp);
4152 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4153 WREG32(DC_HPD4_INT_CONTROL, tmp);
4154 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4155 WREG32(DC_HPD5_INT_CONTROL, tmp);
4156 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4157 WREG32(DC_HPD6_INT_CONTROL, tmp);
4158
4159}
4160
4161int evergreen_irq_set(struct radeon_device *rdev)
4162{
4163 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 4164 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 4165 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
4166 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 4167 u32 grbm_int_cntl = 0;
6f34be50 4168 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 4169 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
f60cbd11 4170 u32 dma_cntl, dma_cntl1 = 0;
dc50ba7f 4171 u32 thermal_int = 0;
45f9a39b
AD		 4172
4173 if (!rdev->irq.installed) {
fce7d61b 4174 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 4175 return -EINVAL;
4176 }
4177 /* don't enable anything if the ih is disabled */
4178 if (!rdev->ih.enabled) {
4179 r600_disable_interrupts(rdev);
4180 /* force the active interrupt state to all disabled */
4181 evergreen_disable_interrupt_state(rdev);
4182 return 0;
4183 }
4184
4185 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4186 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4187 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4188 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
4189 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
4190 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
d70229f7
AD		 4191 if (rdev->family == CHIP_ARUBA)
4192 thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) &
4193 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
4194 else
4195 thermal_int = RREG32(CG_THERMAL_INT) &
4196 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
45f9a39b 4197
f122c610
AD		 4198 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4199 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4200 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4201 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4202 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4203 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
4204
233d1ad5
AD		 4205 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4206
1b37078b
AD		 4207 if (rdev->family >= CHIP_CAYMAN) {
4208 /* enable CP interrupts on all rings */
736fc37f 4209 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 4210 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
4211 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4212 }
736fc37f 4213 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
1b37078b
AD		 4214 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
4215 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
4216 }
736fc37f 4217 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
1b37078b
AD		 4218 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
4219 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
4220 }
4221 } else {
736fc37f 4222 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 4223 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
4224 cp_int_cntl |= RB_INT_ENABLE;
4225 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
4226 }
45f9a39b 4227 }
1b37078b 4228
233d1ad5
AD		 4229 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
4230 DRM_DEBUG("r600_irq_set: sw int dma\n");
4231 dma_cntl |= TRAP_ENABLE;
4232 }
4233
f60cbd11
AD		 4234 if (rdev->family >= CHIP_CAYMAN) {
4235 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
4236 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
4237 DRM_DEBUG("r600_irq_set: sw int dma1\n");
4238 dma_cntl1 |= TRAP_ENABLE;
4239 }
4240 }
4241
dc50ba7f
AD		 4242 if (rdev->irq.dpm_thermal) {
4243 DRM_DEBUG("dpm thermal\n");
4244 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
4245 }
4246
6f34be50 4247 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 4248 atomic_read(&rdev->irq.pflip[0])) {
45f9a39b
AD		 4249 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
4250 crtc1 |= VBLANK_INT_MASK;
4251 }
6f34be50 4252 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 4253 atomic_read(&rdev->irq.pflip[1])) {
45f9a39b
AD		 4254 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
4255 crtc2 |= VBLANK_INT_MASK;
4256 }
6f34be50 4257 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 4258 atomic_read(&rdev->irq.pflip[2])) {
45f9a39b
AD		 4259 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
4260 crtc3 |= VBLANK_INT_MASK;
4261 }
6f34be50 4262 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 4263 atomic_read(&rdev->irq.pflip[3])) {
45f9a39b
AD		 4264 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
4265 crtc4 |= VBLANK_INT_MASK;
4266 }
6f34be50 4267 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 4268 atomic_read(&rdev->irq.pflip[4])) {
45f9a39b
AD		 4269 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
4270 crtc5 |= VBLANK_INT_MASK;
4271 }
6f34be50 4272 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 4273 atomic_read(&rdev->irq.pflip[5])) {
45f9a39b
AD		 4274 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
4275 crtc6 |= VBLANK_INT_MASK;
4276 }
4277 if (rdev->irq.hpd[0]) {
4278 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
4279 hpd1 |= DC_HPDx_INT_EN;
4280 }
4281 if (rdev->irq.hpd[1]) {
4282 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
4283 hpd2 |= DC_HPDx_INT_EN;
4284 }
4285 if (rdev->irq.hpd[2]) {
4286 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
4287 hpd3 |= DC_HPDx_INT_EN;
4288 }
4289 if (rdev->irq.hpd[3]) {
4290 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
4291 hpd4 |= DC_HPDx_INT_EN;
4292 }
4293 if (rdev->irq.hpd[4]) {
4294 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
4295 hpd5 |= DC_HPDx_INT_EN;
4296 }
4297 if (rdev->irq.hpd[5]) {
4298 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
4299 hpd6 |= DC_HPDx_INT_EN;
4300 }
f122c610
AD		 4301 if (rdev->irq.afmt[0]) {
4302 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
4303 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
4304 }
4305 if (rdev->irq.afmt[1]) {
4306 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
4307 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
4308 }
4309 if (rdev->irq.afmt[2]) {
4310 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
4311 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
4312 }
4313 if (rdev->irq.afmt[3]) {
4314 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
4315 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
4316 }
4317 if (rdev->irq.afmt[4]) {
4318 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
4319 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
4320 }
4321 if (rdev->irq.afmt[5]) {
4322 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
4323 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
4324 }
45f9a39b 4325
1b37078b
AD		 4326 if (rdev->family >= CHIP_CAYMAN) {
4327 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
4328 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
4329 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
4330 } else
4331 WREG32(CP_INT_CNTL, cp_int_cntl);
233d1ad5
AD		 4332
4333 WREG32(DMA_CNTL, dma_cntl);
4334
f60cbd11
AD		 4335 if (rdev->family >= CHIP_CAYMAN)
4336 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
4337
2031f77c 4338 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 4339
4340 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
4341 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 4342 if (rdev->num_crtc >= 4) {
18007401
AD		 4343 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
4344 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 4345 }
4346 if (rdev->num_crtc >= 6) {
18007401
AD		 4347 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
4348 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
4349 }
45f9a39b 4350
6f34be50
AD		 4351 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
4352 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 4353 if (rdev->num_crtc >= 4) {
4354 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
4355 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
4356 }
4357 if (rdev->num_crtc >= 6) {
4358 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
4359 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
4360 }
6f34be50 4361
45f9a39b
AD		 4362 WREG32(DC_HPD1_INT_CONTROL, hpd1);
4363 WREG32(DC_HPD2_INT_CONTROL, hpd2);
4364 WREG32(DC_HPD3_INT_CONTROL, hpd3);
4365 WREG32(DC_HPD4_INT_CONTROL, hpd4);
4366 WREG32(DC_HPD5_INT_CONTROL, hpd5);
4367 WREG32(DC_HPD6_INT_CONTROL, hpd6);
d70229f7
AD		 4368 if (rdev->family == CHIP_ARUBA)
4369 WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int);
4370 else
4371 WREG32(CG_THERMAL_INT, thermal_int);
45f9a39b 4372
f122c610
AD		 4373 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
4374 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
4375 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
4376 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
4377 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
4378 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
4379
bcc1c2a1
AD		 4380 return 0;
4381}
4382
cbdd4501 4383static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 4384{
4385 u32 tmp;
4386
6f34be50
AD		 4387 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
4388 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
4389 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
4390 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
4391 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
4392 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
4393 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
4394 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 4395 if (rdev->num_crtc >= 4) {
4396 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
4397 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
4398 }
4399 if (rdev->num_crtc >= 6) {
4400 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
4401 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
4402 }
6f34be50 4403
f122c610
AD		 4404 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
4405 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
4406 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
4407 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
4408 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
4409 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
4410
6f34be50
AD		 4411 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
4412 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
4413 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
4414 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 4415 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 4416 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 4417 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 4418 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 4419 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 4420 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 4421 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 4422 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
4423
b7eff394
AD		 4424 if (rdev->num_crtc >= 4) {
4425 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
4426 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
4427 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
4428 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
4429 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
4430 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
4431 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
4432 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
4433 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
4434 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
4435 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
4436 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
4437 }
4438
4439 if (rdev->num_crtc >= 6) {
4440 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
4441 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
4442 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
4443 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
4444 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
4445 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
4446 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
4447 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
4448 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
4449 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
4450 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
4451 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
4452 }
45f9a39b 4453
6f34be50 4454 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 4455 tmp = RREG32(DC_HPD1_INT_CONTROL);
4456 tmp |= DC_HPDx_INT_ACK;
4457 WREG32(DC_HPD1_INT_CONTROL, tmp);
4458 }
6f34be50 4459 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 4460 tmp = RREG32(DC_HPD2_INT_CONTROL);
4461 tmp |= DC_HPDx_INT_ACK;
4462 WREG32(DC_HPD2_INT_CONTROL, tmp);
4463 }
6f34be50 4464 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 4465 tmp = RREG32(DC_HPD3_INT_CONTROL);
4466 tmp |= DC_HPDx_INT_ACK;
4467 WREG32(DC_HPD3_INT_CONTROL, tmp);
4468 }
6f34be50 4469 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 4470 tmp = RREG32(DC_HPD4_INT_CONTROL);
4471 tmp |= DC_HPDx_INT_ACK;
4472 WREG32(DC_HPD4_INT_CONTROL, tmp);
4473 }
6f34be50 4474 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 4475 tmp = RREG32(DC_HPD5_INT_CONTROL);
4476 tmp |= DC_HPDx_INT_ACK;
4477 WREG32(DC_HPD5_INT_CONTROL, tmp);
4478 }
6f34be50 4479 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 4480 tmp = RREG32(DC_HPD5_INT_CONTROL);
4481 tmp |= DC_HPDx_INT_ACK;
4482 WREG32(DC_HPD6_INT_CONTROL, tmp);
4483 }
f122c610
AD		 4484 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
4485 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
4486 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4487 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
4488 }
4489 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
4490 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
4491 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4492 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
4493 }
4494 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
4495 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
4496 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4497 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
4498 }
4499 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
4500 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
4501 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4502 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
4503 }
4504 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
4505 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
4506 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4507 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
4508 }
4509 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
4510 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
4511 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
4512 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
4513 }
45f9a39b
AD		 4514}
4515
1109ca09 4516static void evergreen_irq_disable(struct radeon_device *rdev)
45f9a39b 4517{
45f9a39b
AD		 4518 r600_disable_interrupts(rdev);
4519 /* Wait and acknowledge irq */
4520 mdelay(1);
6f34be50 4521 evergreen_irq_ack(rdev);
45f9a39b
AD		 4522 evergreen_disable_interrupt_state(rdev);
4523}
4524
755d819e 4525void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 4526{
4527 evergreen_irq_disable(rdev);
4528 r600_rlc_stop(rdev);
4529}
4530
cbdd4501 4531static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 4532{
4533 u32 wptr, tmp;
4534
724c80e1 4535 if (rdev->wb.enabled)
204ae24d 4536 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 4537 else
4538 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 4539
4540 if (wptr & RB_OVERFLOW) {
4541 /* When a ring buffer overflow happen start parsing interrupt
4542 * from the last not overwritten vector (wptr + 16). Hopefully
4543 * this should allow us to catchup.
4544 */
4545 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4546 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
4547 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4548 tmp = RREG32(IH_RB_CNTL);
4549 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4550 WREG32(IH_RB_CNTL, tmp);
4551 }
4552 return (wptr & rdev->ih.ptr_mask);
4553}
4554
4555int evergreen_irq_process(struct radeon_device *rdev)
4556{
682f1a54
DA		 4557 u32 wptr;
4558 u32 rptr;
45f9a39b
AD		 4559 u32 src_id, src_data;
4560 u32 ring_index;
45f9a39b 4561 bool queue_hotplug = false;
f122c610 4562 bool queue_hdmi = false;
dc50ba7f 4563 bool queue_thermal = false;
45f9a39b 4564
682f1a54 4565 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 4566 return IRQ_NONE;
4567
682f1a54 4568 wptr = evergreen_get_ih_wptr(rdev);
c20dc369
CK		 4569
4570restart_ih:
4571 /* is somebody else already processing irqs? */
4572 if (atomic_xchg(&rdev->ih.lock, 1))
4573 return IRQ_NONE;
4574
682f1a54
DA		 4575 rptr = rdev->ih.rptr;
4576 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 4577
964f6645
BH		 4578 /* Order reading of wptr vs. reading of IH ring data */
4579 rmb();
4580
45f9a39b 4581 /* display interrupts */
6f34be50 4582 evergreen_irq_ack(rdev);
45f9a39b 4583
45f9a39b
AD		 4584 while (rptr != wptr) {
4585 /* wptr/rptr are in bytes! */
4586 ring_index = rptr / 4;
0f234f5f
AD		 4587 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4588 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 4589
4590 switch (src_id) {
4591 case 1: /* D1 vblank/vline */
4592 switch (src_data) {
4593 case 0: /* D1 vblank */
6f34be50 4594 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 4595 if (rdev->irq.crtc_vblank_int[0]) {
4596 drm_handle_vblank(rdev->ddev, 0);
4597 rdev->pm.vblank_sync = true;
4598 wake_up(&rdev->irq.vblank_queue);
4599 }
736fc37f 4600 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 4601 radeon_crtc_handle_flip(rdev, 0);
6f34be50 4602 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 4603 DRM_DEBUG("IH: D1 vblank\n");
4604 }
4605 break;
4606 case 1: /* D1 vline */
6f34be50
AD		 4607 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
4608 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 4609 DRM_DEBUG("IH: D1 vline\n");
4610 }
4611 break;
4612 default:
4613 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4614 break;
4615 }
4616 break;
4617 case 2: /* D2 vblank/vline */
4618 switch (src_data) {
4619 case 0: /* D2 vblank */
6f34be50 4620 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 4621 if (rdev->irq.crtc_vblank_int[1]) {
4622 drm_handle_vblank(rdev->ddev, 1);
4623 rdev->pm.vblank_sync = true;
4624 wake_up(&rdev->irq.vblank_queue);
4625 }
736fc37f 4626 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 4627 radeon_crtc_handle_flip(rdev, 1);
6f34be50 4628 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 4629 DRM_DEBUG("IH: D2 vblank\n");
4630 }
4631 break;
4632 case 1: /* D2 vline */
6f34be50
AD		 4633 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
4634 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 4635 DRM_DEBUG("IH: D2 vline\n");
4636 }
4637 break;
4638 default:
4639 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4640 break;
4641 }
4642 break;
4643 case 3: /* D3 vblank/vline */
4644 switch (src_data) {
4645 case 0: /* D3 vblank */
6f34be50
AD		 4646 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
4647 if (rdev->irq.crtc_vblank_int[2]) {
4648 drm_handle_vblank(rdev->ddev, 2);
4649 rdev->pm.vblank_sync = true;
4650 wake_up(&rdev->irq.vblank_queue);
4651 }
736fc37f 4652 if (atomic_read(&rdev->irq.pflip[2]))
6f34be50
AD		 4653 radeon_crtc_handle_flip(rdev, 2);
4654 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 4655 DRM_DEBUG("IH: D3 vblank\n");
4656 }
4657 break;
4658 case 1: /* D3 vline */
6f34be50
AD		 4659 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
4660 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 4661 DRM_DEBUG("IH: D3 vline\n");
4662 }
4663 break;
4664 default:
4665 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4666 break;
4667 }
4668 break;
4669 case 4: /* D4 vblank/vline */
4670 switch (src_data) {
4671 case 0: /* D4 vblank */
6f34be50
AD		 4672 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
4673 if (rdev->irq.crtc_vblank_int[3]) {
4674 drm_handle_vblank(rdev->ddev, 3);
4675 rdev->pm.vblank_sync = true;
4676 wake_up(&rdev->irq.vblank_queue);
4677 }
736fc37f 4678 if (atomic_read(&rdev->irq.pflip[3]))
6f34be50
AD		 4679 radeon_crtc_handle_flip(rdev, 3);
4680 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 4681 DRM_DEBUG("IH: D4 vblank\n");
4682 }
4683 break;
4684 case 1: /* D4 vline */
6f34be50
AD		 4685 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
4686 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 4687 DRM_DEBUG("IH: D4 vline\n");
4688 }
4689 break;
4690 default:
4691 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4692 break;
4693 }
4694 break;
4695 case 5: /* D5 vblank/vline */
4696 switch (src_data) {
4697 case 0: /* D5 vblank */
6f34be50
AD		 4698 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
4699 if (rdev->irq.crtc_vblank_int[4]) {
4700 drm_handle_vblank(rdev->ddev, 4);
4701 rdev->pm.vblank_sync = true;
4702 wake_up(&rdev->irq.vblank_queue);
4703 }
736fc37f 4704 if (atomic_read(&rdev->irq.pflip[4]))
6f34be50
AD		 4705 radeon_crtc_handle_flip(rdev, 4);
4706 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 4707 DRM_DEBUG("IH: D5 vblank\n");
4708 }
4709 break;
4710 case 1: /* D5 vline */
6f34be50
AD		 4711 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
4712 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 4713 DRM_DEBUG("IH: D5 vline\n");
4714 }
4715 break;
4716 default:
4717 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4718 break;
4719 }
4720 break;
4721 case 6: /* D6 vblank/vline */
4722 switch (src_data) {
4723 case 0: /* D6 vblank */
6f34be50
AD		 4724 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
4725 if (rdev->irq.crtc_vblank_int[5]) {
4726 drm_handle_vblank(rdev->ddev, 5);
4727 rdev->pm.vblank_sync = true;
4728 wake_up(&rdev->irq.vblank_queue);
4729 }
736fc37f 4730 if (atomic_read(&rdev->irq.pflip[5]))
6f34be50
AD		 4731 radeon_crtc_handle_flip(rdev, 5);
4732 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 4733 DRM_DEBUG("IH: D6 vblank\n");
4734 }
4735 break;
4736 case 1: /* D6 vline */
6f34be50
AD		 4737 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
4738 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 4739 DRM_DEBUG("IH: D6 vline\n");
4740 }
4741 break;
4742 default:
4743 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4744 break;
4745 }
4746 break;
4747 case 42: /* HPD hotplug */
4748 switch (src_data) {
4749 case 0:
6f34be50
AD		 4750 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
4751 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 4752 queue_hotplug = true;
4753 DRM_DEBUG("IH: HPD1\n");
4754 }
4755 break;
4756 case 1:
6f34be50
AD		 4757 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
4758 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 4759 queue_hotplug = true;
4760 DRM_DEBUG("IH: HPD2\n");
4761 }
4762 break;
4763 case 2:
6f34be50
AD		 4764 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
4765 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 4766 queue_hotplug = true;
4767 DRM_DEBUG("IH: HPD3\n");
4768 }
4769 break;
4770 case 3:
6f34be50
AD		 4771 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
4772 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 4773 queue_hotplug = true;
4774 DRM_DEBUG("IH: HPD4\n");
4775 }
4776 break;
4777 case 4:
6f34be50
AD		 4778 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
4779 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 4780 queue_hotplug = true;
4781 DRM_DEBUG("IH: HPD5\n");
4782 }
4783 break;
4784 case 5:
6f34be50
AD		 4785 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4786 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 4787 queue_hotplug = true;
4788 DRM_DEBUG("IH: HPD6\n");
4789 }
4790 break;
4791 default:
4792 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4793 break;
4794 }
4795 break;
f122c610
AD		 4796 case 44: /* hdmi */
4797 switch (src_data) {
4798 case 0:
4799 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
4800 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
4801 queue_hdmi = true;
4802 DRM_DEBUG("IH: HDMI0\n");
4803 }
4804 break;
4805 case 1:
4806 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
4807 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
4808 queue_hdmi = true;
4809 DRM_DEBUG("IH: HDMI1\n");
4810 }
4811 break;
4812 case 2:
4813 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
4814 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
4815 queue_hdmi = true;
4816 DRM_DEBUG("IH: HDMI2\n");
4817 }
4818 break;
4819 case 3:
4820 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
4821 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
4822 queue_hdmi = true;
4823 DRM_DEBUG("IH: HDMI3\n");
4824 }
4825 break;
4826 case 4:
4827 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
4828 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
4829 queue_hdmi = true;
4830 DRM_DEBUG("IH: HDMI4\n");
4831 }
4832 break;
4833 case 5:
4834 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
4835 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
4836 queue_hdmi = true;
4837 DRM_DEBUG("IH: HDMI5\n");
4838 }
4839 break;
4840 default:
4841 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4842 break;
4843 }
f2ba57b5
CK		 4844 case 124: /* UVD */
4845 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4846 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
f122c610 4847 break;
ae133a11
CK		 4848 case 146:
4849 case 147:
4850 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4851 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
4852 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4853 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4854 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4855 /* reset addr and status */
4856 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4857 break;
45f9a39b
AD		 4858 case 176: /* CP_INT in ring buffer */
4859 case 177: /* CP_INT in IB1 */
4860 case 178: /* CP_INT in IB2 */
4861 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 4862 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 4863 break;
4864 case 181: /* CP EOP event */
4865 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 4866 if (rdev->family >= CHIP_CAYMAN) {
4867 switch (src_data) {
4868 case 0:
4869 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4870 break;
4871 case 1:
4872 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
4873 break;
4874 case 2:
4875 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
4876 break;
4877 }
4878 } else
4879 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 4880 break;
233d1ad5
AD		 4881 case 224: /* DMA trap event */
4882 DRM_DEBUG("IH: DMA trap\n");
4883 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4884 break;
dc50ba7f
AD		 4885 case 230: /* thermal low to high */
4886 DRM_DEBUG("IH: thermal low to high\n");
4887 rdev->pm.dpm.thermal.high_to_low = false;
4888 queue_thermal = true;
4889 break;
4890 case 231: /* thermal high to low */
4891 DRM_DEBUG("IH: thermal high to low\n");
4892 rdev->pm.dpm.thermal.high_to_low = true;
4893 queue_thermal = true;
4894 break;
2031f77c 4895 case 233: /* GUI IDLE */
303c805c 4896 DRM_DEBUG("IH: GUI idle\n");
2031f77c 4897 break;
f60cbd11
AD		 4898 case 244: /* DMA trap event */
4899 if (rdev->family >= CHIP_CAYMAN) {
4900 DRM_DEBUG("IH: DMA1 trap\n");
4901 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4902 }
4903 break;
45f9a39b
AD		 4904 default:
4905 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4906 break;
4907 }
4908
4909 /* wptr/rptr are in bytes! */
4910 rptr += 16;
4911 rptr &= rdev->ih.ptr_mask;
4912 }
45f9a39b 4913 if (queue_hotplug)
32c87fca 4914 schedule_work(&rdev->hotplug_work);
f122c610
AD		 4915 if (queue_hdmi)
4916 schedule_work(&rdev->audio_work);
dc50ba7f
AD		 4917 if (queue_thermal && rdev->pm.dpm_enabled)
4918 schedule_work(&rdev->pm.dpm.thermal.work);
45f9a39b
AD		 4919 rdev->ih.rptr = rptr;
4920 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 4921 atomic_set(&rdev->ih.lock, 0);
4922
4923 /* make sure wptr hasn't changed while processing */
4924 wptr = evergreen_get_ih_wptr(rdev);
4925 if (wptr != rptr)
4926 goto restart_ih;
4927
45f9a39b
AD		 4928 return IRQ_HANDLED;
4929}
4930
233d1ad5
AD		 4931/**
4932 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
4933 *
4934 * @rdev: radeon_device pointer
4935 * @fence: radeon fence object
4936 *
4937 * Add a DMA fence packet to the ring to write
4938 * the fence seq number and DMA trap packet to generate
4939 * an interrupt if needed (evergreen-SI).
4940 */
4941void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
4942 struct radeon_fence *fence)
4943{
4944 struct radeon_ring *ring = &rdev->ring[fence->ring];
4945 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
4946 /* write the fence */
0fcb6155 4947 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
233d1ad5
AD		 4948 radeon_ring_write(ring, addr & 0xfffffffc);
4949 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
4950 radeon_ring_write(ring, fence->seq);
4951 /* generate an interrupt */
0fcb6155 4952 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
233d1ad5 4953 /* flush HDP */
0fcb6155 4954 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
4b681c28 4955 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
233d1ad5
AD		 4956 radeon_ring_write(ring, 1);
4957}
4958
4959/**
4960 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
4961 *
4962 * @rdev: radeon_device pointer
4963 * @ib: IB object to schedule
4964 *
4965 * Schedule an IB in the DMA ring (evergreen).
4966 */
4967void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
4968 struct radeon_ib *ib)
4969{
4970 struct radeon_ring *ring = &rdev->ring[ib->ring];
4971
4972 if (rdev->wb.enabled) {
4973 u32 next_rptr = ring->wptr + 4;
4974 while ((next_rptr & 7) != 5)
4975 next_rptr++;
4976 next_rptr += 3;
0fcb6155 4977 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
233d1ad5
AD		 4978 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4979 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
4980 radeon_ring_write(ring, next_rptr);
4981 }
4982
4983 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
4984 * Pad as necessary with NOPs.
4985 */
4986 while ((ring->wptr & 7) != 5)
0fcb6155
JG		 4987 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
4988 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
233d1ad5
AD		 4989 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
4990 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
4991
4992}
4993
4994/**
4995 * evergreen_copy_dma - copy pages using the DMA engine
4996 *
4997 * @rdev: radeon_device pointer
4998 * @src_offset: src GPU address
4999 * @dst_offset: dst GPU address
5000 * @num_gpu_pages: number of GPU pages to xfer
5001 * @fence: radeon fence object
5002 *
5003 * Copy GPU paging using the DMA engine (evergreen-cayman).
5004 * Used by the radeon ttm implementation to move pages if
5005 * registered as the asic copy callback.
5006 */
5007int evergreen_copy_dma(struct radeon_device *rdev,
5008 uint64_t src_offset, uint64_t dst_offset,
5009 unsigned num_gpu_pages,
5010 struct radeon_fence **fence)
5011{
5012 struct radeon_semaphore *sem = NULL;
5013 int ring_index = rdev->asic->copy.dma_ring_index;
5014 struct radeon_ring *ring = &rdev->ring[ring_index];
5015 u32 size_in_dw, cur_size_in_dw;
5016 int i, num_loops;
5017 int r = 0;
5018
5019 r = radeon_semaphore_create(rdev, &sem);
5020 if (r) {
5021 DRM_ERROR("radeon: moving bo (%d).\n", r);
5022 return r;
5023 }
5024
5025 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
5026 num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
5027 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
5028 if (r) {
5029 DRM_ERROR("radeon: moving bo (%d).\n", r);
5030 radeon_semaphore_free(rdev, &sem, NULL);
5031 return r;
5032 }
5033
5034 if (radeon_fence_need_sync(*fence, ring->idx)) {
5035 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
5036 ring->idx);
5037 radeon_fence_note_sync(*fence, ring->idx);
5038 } else {
5039 radeon_semaphore_free(rdev, &sem, NULL);
5040 }
5041
5042 for (i = 0; i < num_loops; i++) {
5043 cur_size_in_dw = size_in_dw;
5044 if (cur_size_in_dw > 0xFFFFF)
5045 cur_size_in_dw = 0xFFFFF;
5046 size_in_dw -= cur_size_in_dw;
0fcb6155 5047 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
233d1ad5
AD		 5048 radeon_ring_write(ring, dst_offset & 0xfffffffc);
5049 radeon_ring_write(ring, src_offset & 0xfffffffc);
5050 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
5051 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
5052 src_offset += cur_size_in_dw * 4;
5053 dst_offset += cur_size_in_dw * 4;
5054 }
5055
5056 r = radeon_fence_emit(rdev, fence, ring->idx);
5057 if (r) {
5058 radeon_ring_unlock_undo(rdev, ring);
5059 return r;
5060 }
5061
5062 radeon_ring_unlock_commit(rdev, ring);
5063 radeon_semaphore_free(rdev, &sem, *fence);
5064
5065 return r;
5066}
5067
bcc1c2a1
AD		 5068static int evergreen_startup(struct radeon_device *rdev)
5069{
f2ba57b5 5070 struct radeon_ring *ring;
bcc1c2a1
AD		 5071 int r;
5072
9e46a48d 5073 /* enable pcie gen2 link */
cd54033a 5074 evergreen_pcie_gen2_enable(rdev);
f52382d7
AD		 5075 /* enable aspm */
5076 evergreen_program_aspm(rdev);
9e46a48d 5077
0af62b01
AD		 5078 if (ASIC_IS_DCE5(rdev)) {
5079 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
5080 r = ni_init_microcode(rdev);
5081 if (r) {
5082 DRM_ERROR("Failed to load firmware!\n");
5083 return r;
5084 }
5085 }
755d819e 5086 r = ni_mc_load_microcode(rdev);
bcc1c2a1 5087 if (r) {
0af62b01 5088 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 5089 return r;
5090 }
0af62b01
AD		 5091 } else {
5092 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
5093 r = r600_init_microcode(rdev);
5094 if (r) {
5095 DRM_ERROR("Failed to load firmware!\n");
5096 return r;
5097 }
5098 }
bcc1c2a1 5099 }
fe251e2f 5100
16cdf04d
AD		 5101 r = r600_vram_scratch_init(rdev);
5102 if (r)
5103 return r;
5104
bcc1c2a1 5105 evergreen_mc_program(rdev);
bcc1c2a1 5106 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 5107 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 5108 } else {
5109 r = evergreen_pcie_gart_enable(rdev);
5110 if (r)
5111 return r;
5112 }
bcc1c2a1 5113 evergreen_gpu_init(rdev);
bcc1c2a1 5114
d7ccd8fc 5115 r = evergreen_blit_init(rdev);
bcc1c2a1 5116 if (r) {
fb3d9e97 5117 r600_blit_fini(rdev);
27cd7769 5118 rdev->asic->copy.copy = NULL;
d7ccd8fc 5119 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 5120 }
5121
2948f5e6
AD		 5122 /* allocate rlc buffers */
5123 if (rdev->flags & RADEON_IS_IGP) {
5124 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5125 rdev->rlc.reg_list_size = sumo_rlc_save_restore_register_list_size;
5126 rdev->rlc.cs_data = evergreen_cs_data;
5127 r = sumo_rlc_init(rdev);
5128 if (r) {
5129 DRM_ERROR("Failed to init rlc BOs!\n");
5130 return r;
5131 }
5132 }
5133
724c80e1
AD		 5134 /* allocate wb buffer */
5135 r = radeon_wb_init(rdev);
5136 if (r)
5137 return r;
5138
30eb77f4
JG		 5139 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
5140 if (r) {
5141 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
5142 return r;
5143 }
5144
233d1ad5
AD		 5145 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
5146 if (r) {
5147 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
5148 return r;
5149 }
5150
f2ba57b5
CK		 5151 r = rv770_uvd_resume(rdev);
5152 if (!r) {
5153 r = radeon_fence_driver_start_ring(rdev,
5154 R600_RING_TYPE_UVD_INDEX);
5155 if (r)
5156 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
5157 }
5158
5159 if (r)
5160 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
5161
bcc1c2a1 5162 /* Enable IRQ */
e49f3959
AH		 5163 if (!rdev->irq.installed) {
5164 r = radeon_irq_kms_init(rdev);
5165 if (r)
5166 return r;
5167 }
5168
bcc1c2a1
AD		 5169 r = r600_irq_init(rdev);
5170 if (r) {
5171 DRM_ERROR("radeon: IH init failed (%d).\n", r);
5172 radeon_irq_kms_fini(rdev);
5173 return r;
5174 }
45f9a39b 5175 evergreen_irq_set(rdev);
bcc1c2a1 5176
f2ba57b5 5177 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 5178 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 5179 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
5180 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 5181 if (r)
5182 return r;
233d1ad5
AD		 5183
5184 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
5185 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
5186 DMA_RB_RPTR, DMA_RB_WPTR,
0fcb6155 5187 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
233d1ad5
AD		 5188 if (r)
5189 return r;
5190
bcc1c2a1
AD		 5191 r = evergreen_cp_load_microcode(rdev);
5192 if (r)
5193 return r;
fe251e2f 5194 r = evergreen_cp_resume(rdev);
233d1ad5
AD		 5195 if (r)
5196 return r;
5197 r = r600_dma_resume(rdev);
bcc1c2a1
AD		 5198 if (r)
5199 return r;
fe251e2f 5200
f2ba57b5
CK		 5201 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
5202 if (ring->ring_size) {
5203 r = radeon_ring_init(rdev, ring, ring->ring_size,
5204 R600_WB_UVD_RPTR_OFFSET,
5205 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
5206 0, 0xfffff, RADEON_CP_PACKET2);
5207 if (!r)
5208 r = r600_uvd_init(rdev);
5209
5210 if (r)
5211 DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
5212 }
5213
2898c348
CK		 5214 r = radeon_ib_pool_init(rdev);
5215 if (r) {
5216 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 5217 return r;
2898c348 5218 }
b15ba512 5219
69d2ae57
RM		 5220 r = r600_audio_init(rdev);
5221 if (r) {
5222 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 5223 return r;
5224 }
5225
bcc1c2a1
AD		 5226 return 0;
5227}
5228
5229int evergreen_resume(struct radeon_device *rdev)
5230{
5231 int r;
5232
86f5c9ed
AD		 5233 /* reset the asic, the gfx blocks are often in a bad state
5234 * after the driver is unloaded or after a resume
5235 */
5236 if (radeon_asic_reset(rdev))
5237 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 5238 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
5239 * posting will perform necessary task to bring back GPU into good
5240 * shape.
5241 */
5242 /* post card */
5243 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 5244
d4788db3
AD		 5245 /* init golden registers */
5246 evergreen_init_golden_registers(rdev);
5247
b15ba512 5248 rdev->accel_working = true;
bcc1c2a1
AD		 5249 r = evergreen_startup(rdev);
5250 if (r) {
755d819e 5251 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 5252 rdev->accel_working = false;
bcc1c2a1
AD		 5253 return r;
5254 }
fe251e2f 5255
bcc1c2a1
AD		 5256 return r;
5257
5258}
5259
5260int evergreen_suspend(struct radeon_device *rdev)
5261{
69d2ae57 5262 r600_audio_fini(rdev);
f2ba57b5 5263 radeon_uvd_suspend(rdev);
bcc1c2a1 5264 r700_cp_stop(rdev);
233d1ad5 5265 r600_dma_stop(rdev);
f2ba57b5 5266 r600_uvd_rbc_stop(rdev);
45f9a39b 5267 evergreen_irq_suspend(rdev);
724c80e1 5268 radeon_wb_disable(rdev);
bcc1c2a1 5269 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 5270
5271 return 0;
5272}
5273
bcc1c2a1
AD		 5274/* Plan is to move initialization in that function and use
5275 * helper function so that radeon_device_init pretty much
5276 * do nothing more than calling asic specific function. This
5277 * should also allow to remove a bunch of callback function
5278 * like vram_info.
5279 */
5280int evergreen_init(struct radeon_device *rdev)
5281{
5282 int r;
5283
bcc1c2a1
AD		 5284 /* Read BIOS */
5285 if (!radeon_get_bios(rdev)) {
5286 if (ASIC_IS_AVIVO(rdev))
5287 return -EINVAL;
5288 }
5289 /* Must be an ATOMBIOS */
5290 if (!rdev->is_atom_bios) {
755d819e 5291 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 5292 return -EINVAL;
5293 }
5294 r = radeon_atombios_init(rdev);
5295 if (r)
5296 return r;
86f5c9ed
AD		 5297 /* reset the asic, the gfx blocks are often in a bad state
5298 * after the driver is unloaded or after a resume
5299 */
5300 if (radeon_asic_reset(rdev))
5301 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 5302 /* Post card if necessary */
fd909c37 5303 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 5304 if (!rdev->bios) {
5305 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
5306 return -EINVAL;
5307 }
5308 DRM_INFO("GPU not posted. posting now...\n");
5309 atom_asic_init(rdev->mode_info.atom_context);
5310 }
d4788db3
AD		 5311 /* init golden registers */
5312 evergreen_init_golden_registers(rdev);
bcc1c2a1
AD		 5313 /* Initialize scratch registers */
5314 r600_scratch_init(rdev);
5315 /* Initialize surface registers */
5316 radeon_surface_init(rdev);
5317 /* Initialize clocks */
5318 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 5319 /* Fence driver */
5320 r = radeon_fence_driver_init(rdev);
5321 if (r)
5322 return r;
d594e46a
JG		 5323 /* initialize AGP */
5324 if (rdev->flags & RADEON_IS_AGP) {
5325 r = radeon_agp_init(rdev);
5326 if (r)
5327 radeon_agp_disable(rdev);
5328 }
5329 /* initialize memory controller */
bcc1c2a1
AD		 5330 r = evergreen_mc_init(rdev);
5331 if (r)
5332 return r;
5333 /* Memory manager */
5334 r = radeon_bo_init(rdev);
5335 if (r)
5336 return r;
45f9a39b 5337
e32eb50d
CK		 5338 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
5339 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1 5340
233d1ad5
AD		 5341 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
5342 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
5343
f2ba57b5
CK		 5344 r = radeon_uvd_init(rdev);
5345 if (!r) {
5346 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
5347 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
5348 4096);
5349 }
5350
bcc1c2a1
AD		 5351 rdev->ih.ring_obj = NULL;
5352 r600_ih_ring_init(rdev, 64 * 1024);
5353
5354 r = r600_pcie_gart_init(rdev);
5355 if (r)
5356 return r;
0fcdb61e 5357
148a03bc 5358 rdev->accel_working = true;
bcc1c2a1
AD		 5359 r = evergreen_startup(rdev);
5360 if (r) {
fe251e2f
AD		 5361 dev_err(rdev->dev, "disabling GPU acceleration\n");
5362 r700_cp_fini(rdev);
233d1ad5 5363 r600_dma_fini(rdev);
fe251e2f 5364 r600_irq_fini(rdev);
2948f5e6
AD		 5365 if (rdev->flags & RADEON_IS_IGP)
5366 sumo_rlc_fini(rdev);
724c80e1 5367 radeon_wb_fini(rdev);
2898c348 5368 radeon_ib_pool_fini(rdev);
fe251e2f 5369 radeon_irq_kms_fini(rdev);
0fcdb61e 5370 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 5371 rdev->accel_working = false;
5372 }
77e00f2e
AD		 5373
5374 /* Don't start up if the MC ucode is missing on BTC parts.
5375 * The default clocks and voltages before the MC ucode
5376 * is loaded are not suffient for advanced operations.
5377 */
5378 if (ASIC_IS_DCE5(rdev)) {
5379 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
5380 DRM_ERROR("radeon: MC ucode required for NI+.\n");
5381 return -EINVAL;
5382 }
5383 }
5384
bcc1c2a1
AD		 5385 return 0;
5386}
5387
5388void evergreen_fini(struct radeon_device *rdev)
5389{
69d2ae57 5390 r600_audio_fini(rdev);
fb3d9e97 5391 r600_blit_fini(rdev);
45f9a39b 5392 r700_cp_fini(rdev);
233d1ad5 5393 r600_dma_fini(rdev);
bcc1c2a1 5394 r600_irq_fini(rdev);
2948f5e6
AD		 5395 if (rdev->flags & RADEON_IS_IGP)
5396 sumo_rlc_fini(rdev);
724c80e1 5397 radeon_wb_fini(rdev);
2898c348 5398 radeon_ib_pool_fini(rdev);
bcc1c2a1 5399 radeon_irq_kms_fini(rdev);
bcc1c2a1 5400 evergreen_pcie_gart_fini(rdev);
f2ba57b5 5401 radeon_uvd_fini(rdev);
16cdf04d 5402 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 5403 radeon_gem_fini(rdev);
5404 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 5405 radeon_agp_fini(rdev);
5406 radeon_bo_fini(rdev);
5407 radeon_atombios_fini(rdev);
5408 kfree(rdev->bios);
5409 rdev->bios = NULL;
bcc1c2a1 5410}
9e46a48d 5411
b07759bf 5412void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d 5413{
7e0e4196 5414 u32 link_width_cntl, speed_cntl;
9e46a48d 5415
d42dd579
AD		 5416 if (radeon_pcie_gen2 == 0)
5417 return;
5418
9e46a48d
AD		 5419 if (rdev->flags & RADEON_IS_IGP)
5420 return;
5421
5422 if (!(rdev->flags & RADEON_IS_PCIE))
5423 return;
5424
5425 /* x2 cards have a special sequence */
5426 if (ASIC_IS_X2(rdev))
5427 return;
5428
7e0e4196
KSS		 5429 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
5430 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
197bbb3d
DA		 5431 return;
5432
492d2b61 5433 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3691feea
AD		 5434 if (speed_cntl & LC_CURRENT_DATA_RATE) {
5435 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
5436 return;
5437 }
5438
197bbb3d
DA		 5439 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
5440
9e46a48d
AD		 5441 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
5442 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
5443
492d2b61 5444 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d 5445 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 5446 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d 5447
492d2b61 5448 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 5449 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
492d2b61 5450 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d 5451
492d2b61 5452 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 5453 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
492d2b61 5454 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d 5455
492d2b61 5456 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 5457 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
492d2b61 5458 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d 5459
492d2b61 5460 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 5461 speed_cntl |= LC_GEN2_EN_STRAP;
492d2b61 5462 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 5463
5464 } else {
492d2b61 5465 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 5466 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
5467 if (1)
5468 link_width_cntl |= LC_UPCONFIGURE_DIS;
5469 else
5470 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 5471 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 5472 }
5473}
f52382d7
AD		 5474
5475void evergreen_program_aspm(struct radeon_device *rdev)
5476{
5477 u32 data, orig;
5478 u32 pcie_lc_cntl, pcie_lc_cntl_old;
5479 bool disable_l0s, disable_l1 = false, disable_plloff_in_l1 = false;
5480 /* fusion_platform = true
5481 * if the system is a fusion system
5482 * (APU or DGPU in a fusion system).
5483 * todo: check if the system is a fusion platform.
5484 */
5485 bool fusion_platform = false;
5486
5487 if (!(rdev->flags & RADEON_IS_PCIE))
5488 return;
5489
5490 switch (rdev->family) {
5491 case CHIP_CYPRESS:
5492 case CHIP_HEMLOCK:
5493 case CHIP_JUNIPER:
5494 case CHIP_REDWOOD:
5495 case CHIP_CEDAR:
5496 case CHIP_SUMO:
5497 case CHIP_SUMO2:
5498 case CHIP_PALM:
5499 case CHIP_ARUBA:
5500 disable_l0s = true;
5501 break;
5502 default:
5503 disable_l0s = false;
5504 break;
5505 }
5506
5507 if (rdev->flags & RADEON_IS_IGP)
5508 fusion_platform = true; /* XXX also dGPUs in a fusion system */
5509
5510 data = orig = RREG32_PIF_PHY0(PB0_PIF_PAIRING);
5511 if (fusion_platform)
5512 data &= ~MULTI_PIF;
5513 else
5514 data |= MULTI_PIF;
5515 if (data != orig)
5516 WREG32_PIF_PHY0(PB0_PIF_PAIRING, data);
5517
5518 data = orig = RREG32_PIF_PHY1(PB1_PIF_PAIRING);
5519 if (fusion_platform)
5520 data &= ~MULTI_PIF;
5521 else
5522 data |= MULTI_PIF;
5523 if (data != orig)
5524 WREG32_PIF_PHY1(PB1_PIF_PAIRING, data);
5525
5526 pcie_lc_cntl = pcie_lc_cntl_old = RREG32_PCIE_PORT(PCIE_LC_CNTL);
5527 pcie_lc_cntl &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
5528 if (!disable_l0s) {
5529 if (rdev->family >= CHIP_BARTS)
5530 pcie_lc_cntl |= LC_L0S_INACTIVITY(7);
5531 else
5532 pcie_lc_cntl |= LC_L0S_INACTIVITY(3);
5533 }
5534
5535 if (!disable_l1) {
5536 if (rdev->family >= CHIP_BARTS)
5537 pcie_lc_cntl |= LC_L1_INACTIVITY(7);
5538 else
5539 pcie_lc_cntl |= LC_L1_INACTIVITY(8);
5540
5541 if (!disable_plloff_in_l1) {
5542 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
5543 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
5544 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
5545 if (data != orig)
5546 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
5547
5548 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
5549 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
5550 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
5551 if (data != orig)
5552 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
5553
5554 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
5555 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
5556 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
5557 if (data != orig)
5558 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
5559
5560 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
5561 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
5562 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
5563 if (data != orig)
5564 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
5565
5566 if (rdev->family >= CHIP_BARTS) {
5567 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
5568 data &= ~PLL_RAMP_UP_TIME_0_MASK;
5569 data |= PLL_RAMP_UP_TIME_0(4);
5570 if (data != orig)
5571 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
5572
5573 data = orig = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
5574 data &= ~PLL_RAMP_UP_TIME_1_MASK;
5575 data |= PLL_RAMP_UP_TIME_1(4);
5576 if (data != orig)
5577 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
5578
5579 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
5580 data &= ~PLL_RAMP_UP_TIME_0_MASK;
5581 data |= PLL_RAMP_UP_TIME_0(4);
5582 if (data != orig)
5583 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
5584
5585 data = orig = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
5586 data &= ~PLL_RAMP_UP_TIME_1_MASK;
5587 data |= PLL_RAMP_UP_TIME_1(4);
5588 if (data != orig)
5589 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
5590 }
5591
5592 data = orig = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
5593 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
5594 data |= LC_DYN_LANES_PWR_STATE(3);
5595 if (data != orig)
5596 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
5597
5598 if (rdev->family >= CHIP_BARTS) {
5599 data = orig = RREG32_PIF_PHY0(PB0_PIF_CNTL);
5600 data &= ~LS2_EXIT_TIME_MASK;
5601 data |= LS2_EXIT_TIME(1);
5602 if (data != orig)
5603 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
5604
5605 data = orig = RREG32_PIF_PHY1(PB1_PIF_CNTL);
5606 data &= ~LS2_EXIT_TIME_MASK;
5607 data |= LS2_EXIT_TIME(1);
5608 if (data != orig)
5609 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
5610 }
5611 }
5612 }
5613
5614 /* evergreen parts only */
5615 if (rdev->family < CHIP_BARTS)
5616 pcie_lc_cntl |= LC_PMI_TO_L1_DIS;
5617
5618 if (pcie_lc_cntl != pcie_lc_cntl_old)
5619 WREG32_PCIE_PORT(PCIE_LC_CNTL, pcie_lc_cntl);
5620}
Linux 6.x block layer and io_uring tree(s)