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bcc1c2a1 AD |
1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/platform_device.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
760285e7 | 27 | #include <drm/drmP.h> |
bcc1c2a1 | 28 | #include "radeon.h" |
e6990375 | 29 | #include "radeon_asic.h" |
760285e7 | 30 | #include <drm/radeon_drm.h> |
0fcdb61e | 31 | #include "evergreend.h" |
bcc1c2a1 AD |
32 | #include "atom.h" |
33 | #include "avivod.h" | |
34 | #include "evergreen_reg.h" | |
2281a378 | 35 | #include "evergreen_blit_shaders.h" |
bcc1c2a1 | 36 | |
fe251e2f AD |
37 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
38 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | |
39 | ||
4a15903d AD |
40 | static const u32 crtc_offsets[6] = |
41 | { | |
42 | EVERGREEN_CRTC0_REGISTER_OFFSET, | |
43 | EVERGREEN_CRTC1_REGISTER_OFFSET, | |
44 | EVERGREEN_CRTC2_REGISTER_OFFSET, | |
45 | EVERGREEN_CRTC3_REGISTER_OFFSET, | |
46 | EVERGREEN_CRTC4_REGISTER_OFFSET, | |
47 | EVERGREEN_CRTC5_REGISTER_OFFSET | |
48 | }; | |
49 | ||
bcc1c2a1 AD |
50 | static void evergreen_gpu_init(struct radeon_device *rdev); |
51 | void evergreen_fini(struct radeon_device *rdev); | |
b07759bf | 52 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
1b37078b AD |
53 | extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, |
54 | int ring, u32 cp_int_cntl); | |
bcc1c2a1 | 55 | |
285484e2 JG |
56 | void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
57 | unsigned *bankh, unsigned *mtaspect, | |
58 | unsigned *tile_split) | |
59 | { | |
60 | *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; | |
61 | *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; | |
62 | *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; | |
63 | *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; | |
64 | switch (*bankw) { | |
65 | default: | |
66 | case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; | |
67 | case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; | |
68 | case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; | |
69 | case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; | |
70 | } | |
71 | switch (*bankh) { | |
72 | default: | |
73 | case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break; | |
74 | case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break; | |
75 | case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break; | |
76 | case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break; | |
77 | } | |
78 | switch (*mtaspect) { | |
79 | default: | |
80 | case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; | |
81 | case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; | |
82 | case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; | |
83 | case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; | |
84 | } | |
85 | } | |
86 | ||
d054ac16 AD |
87 | void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) |
88 | { | |
89 | u16 ctl, v; | |
32195aec | 90 | int err; |
d054ac16 | 91 | |
32195aec | 92 | err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl); |
d054ac16 AD |
93 | if (err) |
94 | return; | |
95 | ||
96 | v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12; | |
97 | ||
98 | /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it | |
99 | * to avoid hangs or perfomance issues | |
100 | */ | |
101 | if ((v == 0) || (v == 6) || (v == 7)) { | |
102 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
103 | ctl |= (2 << 12); | |
32195aec | 104 | pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl); |
d054ac16 AD |
105 | } |
106 | } | |
107 | ||
377edc8b AD |
108 | /** |
109 | * dce4_wait_for_vblank - vblank wait asic callback. | |
110 | * | |
111 | * @rdev: radeon_device pointer | |
112 | * @crtc: crtc to wait for vblank on | |
113 | * | |
114 | * Wait for vblank on the requested crtc (evergreen+). | |
115 | */ | |
3ae19b75 AD |
116 | void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) |
117 | { | |
3ae19b75 AD |
118 | int i; |
119 | ||
4a15903d AD |
120 | if (crtc >= rdev->num_crtc) |
121 | return; | |
122 | ||
123 | if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) { | |
3ae19b75 | 124 | for (i = 0; i < rdev->usec_timeout; i++) { |
4a15903d | 125 | if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)) |
3ae19b75 AD |
126 | break; |
127 | udelay(1); | |
128 | } | |
129 | for (i = 0; i < rdev->usec_timeout; i++) { | |
4a15903d | 130 | if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) |
3ae19b75 AD |
131 | break; |
132 | udelay(1); | |
133 | } | |
134 | } | |
135 | } | |
136 | ||
377edc8b AD |
137 | /** |
138 | * radeon_irq_kms_pflip_irq_get - pre-pageflip callback. | |
139 | * | |
140 | * @rdev: radeon_device pointer | |
141 | * @crtc: crtc to prepare for pageflip on | |
142 | * | |
143 | * Pre-pageflip callback (evergreen+). | |
144 | * Enables the pageflip irq (vblank irq). | |
145 | */ | |
6f34be50 AD |
146 | void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) |
147 | { | |
6f34be50 AD |
148 | /* enable the pflip int */ |
149 | radeon_irq_kms_pflip_irq_get(rdev, crtc); | |
150 | } | |
151 | ||
377edc8b AD |
152 | /** |
153 | * evergreen_post_page_flip - pos-pageflip callback. | |
154 | * | |
155 | * @rdev: radeon_device pointer | |
156 | * @crtc: crtc to cleanup pageflip on | |
157 | * | |
158 | * Post-pageflip callback (evergreen+). | |
159 | * Disables the pageflip irq (vblank irq). | |
160 | */ | |
6f34be50 AD |
161 | void evergreen_post_page_flip(struct radeon_device *rdev, int crtc) |
162 | { | |
163 | /* disable the pflip int */ | |
164 | radeon_irq_kms_pflip_irq_put(rdev, crtc); | |
165 | } | |
166 | ||
377edc8b AD |
167 | /** |
168 | * evergreen_page_flip - pageflip callback. | |
169 | * | |
170 | * @rdev: radeon_device pointer | |
171 | * @crtc_id: crtc to cleanup pageflip on | |
172 | * @crtc_base: new address of the crtc (GPU MC address) | |
173 | * | |
174 | * Does the actual pageflip (evergreen+). | |
175 | * During vblank we take the crtc lock and wait for the update_pending | |
176 | * bit to go high, when it does, we release the lock, and allow the | |
177 | * double buffered update to take place. | |
178 | * Returns the current update pending status. | |
179 | */ | |
6f34be50 AD |
180 | u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
181 | { | |
182 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | |
183 | u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); | |
f6496479 | 184 | int i; |
6f34be50 AD |
185 | |
186 | /* Lock the graphics update lock */ | |
187 | tmp |= EVERGREEN_GRPH_UPDATE_LOCK; | |
188 | WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
189 | ||
190 | /* update the scanout addresses */ | |
191 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
192 | upper_32_bits(crtc_base)); | |
193 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
194 | (u32)crtc_base); | |
195 | ||
196 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
197 | upper_32_bits(crtc_base)); | |
198 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
199 | (u32)crtc_base); | |
200 | ||
201 | /* Wait for update_pending to go high. */ | |
f6496479 AD |
202 | for (i = 0; i < rdev->usec_timeout; i++) { |
203 | if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) | |
204 | break; | |
205 | udelay(1); | |
206 | } | |
6f34be50 AD |
207 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
208 | ||
209 | /* Unlock the lock, so double-buffering can take place inside vblank */ | |
210 | tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; | |
211 | WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); | |
212 | ||
213 | /* Return current update_pending status: */ | |
214 | return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; | |
215 | } | |
216 | ||
21a8122a | 217 | /* get temperature in millidegrees */ |
20d391d7 | 218 | int evergreen_get_temp(struct radeon_device *rdev) |
21a8122a | 219 | { |
1c88d74f AD |
220 | u32 temp, toffset; |
221 | int actual_temp = 0; | |
67b3f823 AD |
222 | |
223 | if (rdev->family == CHIP_JUNIPER) { | |
224 | toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> | |
225 | TOFFSET_SHIFT; | |
226 | temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> | |
227 | TS0_ADC_DOUT_SHIFT; | |
228 | ||
229 | if (toffset & 0x100) | |
230 | actual_temp = temp / 2 - (0x200 - toffset); | |
231 | else | |
232 | actual_temp = temp / 2 + toffset; | |
233 | ||
234 | actual_temp = actual_temp * 1000; | |
235 | ||
236 | } else { | |
237 | temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> | |
238 | ASIC_T_SHIFT; | |
239 | ||
240 | if (temp & 0x400) | |
241 | actual_temp = -256; | |
242 | else if (temp & 0x200) | |
243 | actual_temp = 255; | |
244 | else if (temp & 0x100) { | |
245 | actual_temp = temp & 0x1ff; | |
246 | actual_temp |= ~0x1ff; | |
247 | } else | |
248 | actual_temp = temp & 0xff; | |
249 | ||
250 | actual_temp = (actual_temp * 1000) / 2; | |
251 | } | |
21a8122a | 252 | |
67b3f823 | 253 | return actual_temp; |
21a8122a AD |
254 | } |
255 | ||
20d391d7 | 256 | int sumo_get_temp(struct radeon_device *rdev) |
e33df25f AD |
257 | { |
258 | u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; | |
20d391d7 | 259 | int actual_temp = temp - 49; |
e33df25f AD |
260 | |
261 | return actual_temp * 1000; | |
262 | } | |
263 | ||
377edc8b AD |
264 | /** |
265 | * sumo_pm_init_profile - Initialize power profiles callback. | |
266 | * | |
267 | * @rdev: radeon_device pointer | |
268 | * | |
269 | * Initialize the power states used in profile mode | |
270 | * (sumo, trinity, SI). | |
271 | * Used for profile mode only. | |
272 | */ | |
a4c9e2ee AD |
273 | void sumo_pm_init_profile(struct radeon_device *rdev) |
274 | { | |
275 | int idx; | |
276 | ||
277 | /* default */ | |
278 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
279 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
280 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
281 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
282 | ||
283 | /* low,mid sh/mh */ | |
284 | if (rdev->flags & RADEON_IS_MOBILITY) | |
285 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
286 | else | |
287 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
288 | ||
289 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; | |
290 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; | |
291 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
292 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
293 | ||
294 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; | |
295 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; | |
296 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
297 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
298 | ||
299 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; | |
300 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; | |
301 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
302 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
303 | ||
304 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; | |
305 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; | |
306 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
307 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
308 | ||
309 | /* high sh/mh */ | |
310 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
311 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; | |
312 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; | |
313 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
314 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = | |
315 | rdev->pm.power_state[idx].num_clock_modes - 1; | |
316 | ||
317 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; | |
318 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; | |
319 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
320 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = | |
321 | rdev->pm.power_state[idx].num_clock_modes - 1; | |
322 | } | |
323 | ||
27810fb2 AD |
324 | /** |
325 | * btc_pm_init_profile - Initialize power profiles callback. | |
326 | * | |
327 | * @rdev: radeon_device pointer | |
328 | * | |
329 | * Initialize the power states used in profile mode | |
330 | * (BTC, cayman). | |
331 | * Used for profile mode only. | |
332 | */ | |
333 | void btc_pm_init_profile(struct radeon_device *rdev) | |
334 | { | |
335 | int idx; | |
336 | ||
337 | /* default */ | |
338 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
339 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
340 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
341 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
342 | /* starting with BTC, there is one state that is used for both | |
343 | * MH and SH. Difference is that we always use the high clock index for | |
344 | * mclk. | |
345 | */ | |
346 | if (rdev->flags & RADEON_IS_MOBILITY) | |
347 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
348 | else | |
349 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
350 | /* low sh */ | |
351 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; | |
352 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; | |
353 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
354 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
355 | /* mid sh */ | |
356 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; | |
357 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; | |
358 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
359 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
360 | /* high sh */ | |
361 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; | |
362 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; | |
363 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
364 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
365 | /* low mh */ | |
366 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; | |
367 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; | |
368 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
369 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
370 | /* mid mh */ | |
371 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; | |
372 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; | |
373 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
374 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
375 | /* high mh */ | |
376 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; | |
377 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; | |
378 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
379 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
380 | } | |
381 | ||
377edc8b AD |
382 | /** |
383 | * evergreen_pm_misc - set additional pm hw parameters callback. | |
384 | * | |
385 | * @rdev: radeon_device pointer | |
386 | * | |
387 | * Set non-clock parameters associated with a power state | |
388 | * (voltage, etc.) (evergreen+). | |
389 | */ | |
49e02b73 AD |
390 | void evergreen_pm_misc(struct radeon_device *rdev) |
391 | { | |
a081a9d6 RM |
392 | int req_ps_idx = rdev->pm.requested_power_state_index; |
393 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
394 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
395 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
49e02b73 | 396 | |
2feea49a | 397 | if (voltage->type == VOLTAGE_SW) { |
a377e187 AD |
398 | /* 0xff01 is a flag rather then an actual voltage */ |
399 | if (voltage->voltage == 0xff01) | |
400 | return; | |
2feea49a | 401 | if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { |
8a83ec5e | 402 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
4d60173f | 403 | rdev->pm.current_vddc = voltage->voltage; |
2feea49a AD |
404 | DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); |
405 | } | |
7ae764b1 AD |
406 | |
407 | /* starting with BTC, there is one state that is used for both | |
408 | * MH and SH. Difference is that we always use the high clock index for | |
409 | * mclk and vddci. | |
410 | */ | |
411 | if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && | |
412 | (rdev->family >= CHIP_BARTS) && | |
413 | rdev->pm.active_crtc_count && | |
414 | ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || | |
415 | (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) | |
416 | voltage = &rdev->pm.power_state[req_ps_idx]. | |
417 | clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage; | |
418 | ||
a377e187 AD |
419 | /* 0xff01 is a flag rather then an actual voltage */ |
420 | if (voltage->vddci == 0xff01) | |
421 | return; | |
2feea49a AD |
422 | if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { |
423 | radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); | |
424 | rdev->pm.current_vddci = voltage->vddci; | |
425 | DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); | |
4d60173f AD |
426 | } |
427 | } | |
49e02b73 AD |
428 | } |
429 | ||
377edc8b AD |
430 | /** |
431 | * evergreen_pm_prepare - pre-power state change callback. | |
432 | * | |
433 | * @rdev: radeon_device pointer | |
434 | * | |
435 | * Prepare for a power state change (evergreen+). | |
436 | */ | |
49e02b73 AD |
437 | void evergreen_pm_prepare(struct radeon_device *rdev) |
438 | { | |
439 | struct drm_device *ddev = rdev->ddev; | |
440 | struct drm_crtc *crtc; | |
441 | struct radeon_crtc *radeon_crtc; | |
442 | u32 tmp; | |
443 | ||
444 | /* disable any active CRTCs */ | |
445 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
446 | radeon_crtc = to_radeon_crtc(crtc); | |
447 | if (radeon_crtc->enabled) { | |
448 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); | |
449 | tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
450 | WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
451 | } | |
452 | } | |
453 | } | |
454 | ||
377edc8b AD |
455 | /** |
456 | * evergreen_pm_finish - post-power state change callback. | |
457 | * | |
458 | * @rdev: radeon_device pointer | |
459 | * | |
460 | * Clean up after a power state change (evergreen+). | |
461 | */ | |
49e02b73 AD |
462 | void evergreen_pm_finish(struct radeon_device *rdev) |
463 | { | |
464 | struct drm_device *ddev = rdev->ddev; | |
465 | struct drm_crtc *crtc; | |
466 | struct radeon_crtc *radeon_crtc; | |
467 | u32 tmp; | |
468 | ||
469 | /* enable any active CRTCs */ | |
470 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
471 | radeon_crtc = to_radeon_crtc(crtc); | |
472 | if (radeon_crtc->enabled) { | |
473 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); | |
474 | tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
475 | WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); | |
476 | } | |
477 | } | |
478 | } | |
479 | ||
377edc8b AD |
480 | /** |
481 | * evergreen_hpd_sense - hpd sense callback. | |
482 | * | |
483 | * @rdev: radeon_device pointer | |
484 | * @hpd: hpd (hotplug detect) pin | |
485 | * | |
486 | * Checks if a digital monitor is connected (evergreen+). | |
487 | * Returns true if connected, false if not connected. | |
488 | */ | |
bcc1c2a1 AD |
489 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
490 | { | |
491 | bool connected = false; | |
0ca2ab52 AD |
492 | |
493 | switch (hpd) { | |
494 | case RADEON_HPD_1: | |
495 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
496 | connected = true; | |
497 | break; | |
498 | case RADEON_HPD_2: | |
499 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
500 | connected = true; | |
501 | break; | |
502 | case RADEON_HPD_3: | |
503 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
504 | connected = true; | |
505 | break; | |
506 | case RADEON_HPD_4: | |
507 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
508 | connected = true; | |
509 | break; | |
510 | case RADEON_HPD_5: | |
511 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
512 | connected = true; | |
513 | break; | |
514 | case RADEON_HPD_6: | |
515 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
516 | connected = true; | |
517 | break; | |
518 | default: | |
519 | break; | |
520 | } | |
521 | ||
bcc1c2a1 AD |
522 | return connected; |
523 | } | |
524 | ||
377edc8b AD |
525 | /** |
526 | * evergreen_hpd_set_polarity - hpd set polarity callback. | |
527 | * | |
528 | * @rdev: radeon_device pointer | |
529 | * @hpd: hpd (hotplug detect) pin | |
530 | * | |
531 | * Set the polarity of the hpd pin (evergreen+). | |
532 | */ | |
bcc1c2a1 AD |
533 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, |
534 | enum radeon_hpd_id hpd) | |
535 | { | |
0ca2ab52 AD |
536 | u32 tmp; |
537 | bool connected = evergreen_hpd_sense(rdev, hpd); | |
538 | ||
539 | switch (hpd) { | |
540 | case RADEON_HPD_1: | |
541 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
542 | if (connected) | |
543 | tmp &= ~DC_HPDx_INT_POLARITY; | |
544 | else | |
545 | tmp |= DC_HPDx_INT_POLARITY; | |
546 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
547 | break; | |
548 | case RADEON_HPD_2: | |
549 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
550 | if (connected) | |
551 | tmp &= ~DC_HPDx_INT_POLARITY; | |
552 | else | |
553 | tmp |= DC_HPDx_INT_POLARITY; | |
554 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
555 | break; | |
556 | case RADEON_HPD_3: | |
557 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
558 | if (connected) | |
559 | tmp &= ~DC_HPDx_INT_POLARITY; | |
560 | else | |
561 | tmp |= DC_HPDx_INT_POLARITY; | |
562 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
563 | break; | |
564 | case RADEON_HPD_4: | |
565 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
566 | if (connected) | |
567 | tmp &= ~DC_HPDx_INT_POLARITY; | |
568 | else | |
569 | tmp |= DC_HPDx_INT_POLARITY; | |
570 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
571 | break; | |
572 | case RADEON_HPD_5: | |
573 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
574 | if (connected) | |
575 | tmp &= ~DC_HPDx_INT_POLARITY; | |
576 | else | |
577 | tmp |= DC_HPDx_INT_POLARITY; | |
578 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
579 | break; | |
580 | case RADEON_HPD_6: | |
581 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
582 | if (connected) | |
583 | tmp &= ~DC_HPDx_INT_POLARITY; | |
584 | else | |
585 | tmp |= DC_HPDx_INT_POLARITY; | |
586 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
587 | break; | |
588 | default: | |
589 | break; | |
590 | } | |
bcc1c2a1 AD |
591 | } |
592 | ||
377edc8b AD |
593 | /** |
594 | * evergreen_hpd_init - hpd setup callback. | |
595 | * | |
596 | * @rdev: radeon_device pointer | |
597 | * | |
598 | * Setup the hpd pins used by the card (evergreen+). | |
599 | * Enable the pin, set the polarity, and enable the hpd interrupts. | |
600 | */ | |
bcc1c2a1 AD |
601 | void evergreen_hpd_init(struct radeon_device *rdev) |
602 | { | |
0ca2ab52 AD |
603 | struct drm_device *dev = rdev->ddev; |
604 | struct drm_connector *connector; | |
fb98257a | 605 | unsigned enabled = 0; |
0ca2ab52 AD |
606 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | |
607 | DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; | |
bcc1c2a1 | 608 | |
0ca2ab52 AD |
609 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
610 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
611 | switch (radeon_connector->hpd.hpd) { | |
612 | case RADEON_HPD_1: | |
613 | WREG32(DC_HPD1_CONTROL, tmp); | |
0ca2ab52 AD |
614 | break; |
615 | case RADEON_HPD_2: | |
616 | WREG32(DC_HPD2_CONTROL, tmp); | |
0ca2ab52 AD |
617 | break; |
618 | case RADEON_HPD_3: | |
619 | WREG32(DC_HPD3_CONTROL, tmp); | |
0ca2ab52 AD |
620 | break; |
621 | case RADEON_HPD_4: | |
622 | WREG32(DC_HPD4_CONTROL, tmp); | |
0ca2ab52 AD |
623 | break; |
624 | case RADEON_HPD_5: | |
625 | WREG32(DC_HPD5_CONTROL, tmp); | |
0ca2ab52 AD |
626 | break; |
627 | case RADEON_HPD_6: | |
628 | WREG32(DC_HPD6_CONTROL, tmp); | |
0ca2ab52 AD |
629 | break; |
630 | default: | |
631 | break; | |
632 | } | |
64912e99 | 633 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
fb98257a | 634 | enabled |= 1 << radeon_connector->hpd.hpd; |
0ca2ab52 | 635 | } |
fb98257a | 636 | radeon_irq_kms_enable_hpd(rdev, enabled); |
bcc1c2a1 AD |
637 | } |
638 | ||
377edc8b AD |
639 | /** |
640 | * evergreen_hpd_fini - hpd tear down callback. | |
641 | * | |
642 | * @rdev: radeon_device pointer | |
643 | * | |
644 | * Tear down the hpd pins used by the card (evergreen+). | |
645 | * Disable the hpd interrupts. | |
646 | */ | |
0ca2ab52 | 647 | void evergreen_hpd_fini(struct radeon_device *rdev) |
bcc1c2a1 | 648 | { |
0ca2ab52 AD |
649 | struct drm_device *dev = rdev->ddev; |
650 | struct drm_connector *connector; | |
fb98257a | 651 | unsigned disabled = 0; |
0ca2ab52 AD |
652 | |
653 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
654 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
655 | switch (radeon_connector->hpd.hpd) { | |
656 | case RADEON_HPD_1: | |
657 | WREG32(DC_HPD1_CONTROL, 0); | |
0ca2ab52 AD |
658 | break; |
659 | case RADEON_HPD_2: | |
660 | WREG32(DC_HPD2_CONTROL, 0); | |
0ca2ab52 AD |
661 | break; |
662 | case RADEON_HPD_3: | |
663 | WREG32(DC_HPD3_CONTROL, 0); | |
0ca2ab52 AD |
664 | break; |
665 | case RADEON_HPD_4: | |
666 | WREG32(DC_HPD4_CONTROL, 0); | |
0ca2ab52 AD |
667 | break; |
668 | case RADEON_HPD_5: | |
669 | WREG32(DC_HPD5_CONTROL, 0); | |
0ca2ab52 AD |
670 | break; |
671 | case RADEON_HPD_6: | |
672 | WREG32(DC_HPD6_CONTROL, 0); | |
0ca2ab52 AD |
673 | break; |
674 | default: | |
675 | break; | |
676 | } | |
fb98257a | 677 | disabled |= 1 << radeon_connector->hpd.hpd; |
0ca2ab52 | 678 | } |
fb98257a | 679 | radeon_irq_kms_disable_hpd(rdev, disabled); |
bcc1c2a1 AD |
680 | } |
681 | ||
f9d9c362 AD |
682 | /* watermark setup */ |
683 | ||
684 | static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, | |
685 | struct radeon_crtc *radeon_crtc, | |
686 | struct drm_display_mode *mode, | |
687 | struct drm_display_mode *other_mode) | |
688 | { | |
12dfc843 | 689 | u32 tmp; |
f9d9c362 AD |
690 | /* |
691 | * Line Buffer Setup | |
692 | * There are 3 line buffers, each one shared by 2 display controllers. | |
693 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between | |
694 | * the display controllers. The paritioning is done via one of four | |
695 | * preset allocations specified in bits 2:0: | |
696 | * first display controller | |
697 | * 0 - first half of lb (3840 * 2) | |
698 | * 1 - first 3/4 of lb (5760 * 2) | |
12dfc843 | 699 | * 2 - whole lb (7680 * 2), other crtc must be disabled |
f9d9c362 AD |
700 | * 3 - first 1/4 of lb (1920 * 2) |
701 | * second display controller | |
702 | * 4 - second half of lb (3840 * 2) | |
703 | * 5 - second 3/4 of lb (5760 * 2) | |
12dfc843 | 704 | * 6 - whole lb (7680 * 2), other crtc must be disabled |
f9d9c362 AD |
705 | * 7 - last 1/4 of lb (1920 * 2) |
706 | */ | |
12dfc843 AD |
707 | /* this can get tricky if we have two large displays on a paired group |
708 | * of crtcs. Ideally for multiple large displays we'd assign them to | |
709 | * non-linked crtcs for maximum line buffer allocation. | |
710 | */ | |
711 | if (radeon_crtc->base.enabled && mode) { | |
712 | if (other_mode) | |
f9d9c362 | 713 | tmp = 0; /* 1/2 */ |
12dfc843 AD |
714 | else |
715 | tmp = 2; /* whole */ | |
716 | } else | |
717 | tmp = 0; | |
f9d9c362 AD |
718 | |
719 | /* second controller of the pair uses second half of the lb */ | |
720 | if (radeon_crtc->crtc_id % 2) | |
721 | tmp += 4; | |
722 | WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); | |
723 | ||
12dfc843 AD |
724 | if (radeon_crtc->base.enabled && mode) { |
725 | switch (tmp) { | |
726 | case 0: | |
727 | case 4: | |
728 | default: | |
729 | if (ASIC_IS_DCE5(rdev)) | |
730 | return 4096 * 2; | |
731 | else | |
732 | return 3840 * 2; | |
733 | case 1: | |
734 | case 5: | |
735 | if (ASIC_IS_DCE5(rdev)) | |
736 | return 6144 * 2; | |
737 | else | |
738 | return 5760 * 2; | |
739 | case 2: | |
740 | case 6: | |
741 | if (ASIC_IS_DCE5(rdev)) | |
742 | return 8192 * 2; | |
743 | else | |
744 | return 7680 * 2; | |
745 | case 3: | |
746 | case 7: | |
747 | if (ASIC_IS_DCE5(rdev)) | |
748 | return 2048 * 2; | |
749 | else | |
750 | return 1920 * 2; | |
751 | } | |
f9d9c362 | 752 | } |
12dfc843 AD |
753 | |
754 | /* controller not enabled, so no lb used */ | |
755 | return 0; | |
f9d9c362 AD |
756 | } |
757 | ||
ca7db22b | 758 | u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) |
f9d9c362 AD |
759 | { |
760 | u32 tmp = RREG32(MC_SHARED_CHMAP); | |
761 | ||
762 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
763 | case 0: | |
764 | default: | |
765 | return 1; | |
766 | case 1: | |
767 | return 2; | |
768 | case 2: | |
769 | return 4; | |
770 | case 3: | |
771 | return 8; | |
772 | } | |
773 | } | |
774 | ||
775 | struct evergreen_wm_params { | |
776 | u32 dram_channels; /* number of dram channels */ | |
777 | u32 yclk; /* bandwidth per dram data pin in kHz */ | |
778 | u32 sclk; /* engine clock in kHz */ | |
779 | u32 disp_clk; /* display clock in kHz */ | |
780 | u32 src_width; /* viewport width */ | |
781 | u32 active_time; /* active display time in ns */ | |
782 | u32 blank_time; /* blank time in ns */ | |
783 | bool interlaced; /* mode is interlaced */ | |
784 | fixed20_12 vsc; /* vertical scale ratio */ | |
785 | u32 num_heads; /* number of active crtcs */ | |
786 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ | |
787 | u32 lb_size; /* line buffer allocated to pipe */ | |
788 | u32 vtaps; /* vertical scaler taps */ | |
789 | }; | |
790 | ||
791 | static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) | |
792 | { | |
793 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
794 | fixed20_12 dram_efficiency; /* 0.7 */ | |
795 | fixed20_12 yclk, dram_channels, bandwidth; | |
796 | fixed20_12 a; | |
797 | ||
798 | a.full = dfixed_const(1000); | |
799 | yclk.full = dfixed_const(wm->yclk); | |
800 | yclk.full = dfixed_div(yclk, a); | |
801 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
802 | a.full = dfixed_const(10); | |
803 | dram_efficiency.full = dfixed_const(7); | |
804 | dram_efficiency.full = dfixed_div(dram_efficiency, a); | |
805 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
806 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); | |
807 | ||
808 | return dfixed_trunc(bandwidth); | |
809 | } | |
810 | ||
811 | static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) | |
812 | { | |
813 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
814 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ | |
815 | fixed20_12 yclk, dram_channels, bandwidth; | |
816 | fixed20_12 a; | |
817 | ||
818 | a.full = dfixed_const(1000); | |
819 | yclk.full = dfixed_const(wm->yclk); | |
820 | yclk.full = dfixed_div(yclk, a); | |
821 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
822 | a.full = dfixed_const(10); | |
823 | disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ | |
824 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); | |
825 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
826 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); | |
827 | ||
828 | return dfixed_trunc(bandwidth); | |
829 | } | |
830 | ||
831 | static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) | |
832 | { | |
833 | /* Calculate the display Data return Bandwidth */ | |
834 | fixed20_12 return_efficiency; /* 0.8 */ | |
835 | fixed20_12 sclk, bandwidth; | |
836 | fixed20_12 a; | |
837 | ||
838 | a.full = dfixed_const(1000); | |
839 | sclk.full = dfixed_const(wm->sclk); | |
840 | sclk.full = dfixed_div(sclk, a); | |
841 | a.full = dfixed_const(10); | |
842 | return_efficiency.full = dfixed_const(8); | |
843 | return_efficiency.full = dfixed_div(return_efficiency, a); | |
844 | a.full = dfixed_const(32); | |
845 | bandwidth.full = dfixed_mul(a, sclk); | |
846 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency); | |
847 | ||
848 | return dfixed_trunc(bandwidth); | |
849 | } | |
850 | ||
851 | static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) | |
852 | { | |
853 | /* Calculate the DMIF Request Bandwidth */ | |
854 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ | |
855 | fixed20_12 disp_clk, bandwidth; | |
856 | fixed20_12 a; | |
857 | ||
858 | a.full = dfixed_const(1000); | |
859 | disp_clk.full = dfixed_const(wm->disp_clk); | |
860 | disp_clk.full = dfixed_div(disp_clk, a); | |
861 | a.full = dfixed_const(10); | |
862 | disp_clk_request_efficiency.full = dfixed_const(8); | |
863 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); | |
864 | a.full = dfixed_const(32); | |
865 | bandwidth.full = dfixed_mul(a, disp_clk); | |
866 | bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); | |
867 | ||
868 | return dfixed_trunc(bandwidth); | |
869 | } | |
870 | ||
871 | static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) | |
872 | { | |
873 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ | |
874 | u32 dram_bandwidth = evergreen_dram_bandwidth(wm); | |
875 | u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); | |
876 | u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); | |
877 | ||
878 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); | |
879 | } | |
880 | ||
881 | static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) | |
882 | { | |
883 | /* Calculate the display mode Average Bandwidth | |
884 | * DisplayMode should contain the source and destination dimensions, | |
885 | * timing, etc. | |
886 | */ | |
887 | fixed20_12 bpp; | |
888 | fixed20_12 line_time; | |
889 | fixed20_12 src_width; | |
890 | fixed20_12 bandwidth; | |
891 | fixed20_12 a; | |
892 | ||
893 | a.full = dfixed_const(1000); | |
894 | line_time.full = dfixed_const(wm->active_time + wm->blank_time); | |
895 | line_time.full = dfixed_div(line_time, a); | |
896 | bpp.full = dfixed_const(wm->bytes_per_pixel); | |
897 | src_width.full = dfixed_const(wm->src_width); | |
898 | bandwidth.full = dfixed_mul(src_width, bpp); | |
899 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc); | |
900 | bandwidth.full = dfixed_div(bandwidth, line_time); | |
901 | ||
902 | return dfixed_trunc(bandwidth); | |
903 | } | |
904 | ||
905 | static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) | |
906 | { | |
907 | /* First calcualte the latency in ns */ | |
908 | u32 mc_latency = 2000; /* 2000 ns. */ | |
909 | u32 available_bandwidth = evergreen_available_bandwidth(wm); | |
910 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; | |
911 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; | |
912 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ | |
913 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + | |
914 | (wm->num_heads * cursor_line_pair_return_time); | |
915 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; | |
916 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; | |
917 | fixed20_12 a, b, c; | |
918 | ||
919 | if (wm->num_heads == 0) | |
920 | return 0; | |
921 | ||
922 | a.full = dfixed_const(2); | |
923 | b.full = dfixed_const(1); | |
924 | if ((wm->vsc.full > a.full) || | |
925 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || | |
926 | (wm->vtaps >= 5) || | |
927 | ((wm->vsc.full >= a.full) && wm->interlaced)) | |
928 | max_src_lines_per_dst_line = 4; | |
929 | else | |
930 | max_src_lines_per_dst_line = 2; | |
931 | ||
932 | a.full = dfixed_const(available_bandwidth); | |
933 | b.full = dfixed_const(wm->num_heads); | |
934 | a.full = dfixed_div(a, b); | |
935 | ||
936 | b.full = dfixed_const(1000); | |
937 | c.full = dfixed_const(wm->disp_clk); | |
938 | b.full = dfixed_div(c, b); | |
939 | c.full = dfixed_const(wm->bytes_per_pixel); | |
940 | b.full = dfixed_mul(b, c); | |
941 | ||
942 | lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); | |
943 | ||
944 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | |
945 | b.full = dfixed_const(1000); | |
946 | c.full = dfixed_const(lb_fill_bw); | |
947 | b.full = dfixed_div(c, b); | |
948 | a.full = dfixed_div(a, b); | |
949 | line_fill_time = dfixed_trunc(a); | |
950 | ||
951 | if (line_fill_time < wm->active_time) | |
952 | return latency; | |
953 | else | |
954 | return latency + (line_fill_time - wm->active_time); | |
955 | ||
956 | } | |
957 | ||
958 | static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) | |
959 | { | |
960 | if (evergreen_average_bandwidth(wm) <= | |
961 | (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) | |
962 | return true; | |
963 | else | |
964 | return false; | |
965 | }; | |
966 | ||
967 | static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) | |
968 | { | |
969 | if (evergreen_average_bandwidth(wm) <= | |
970 | (evergreen_available_bandwidth(wm) / wm->num_heads)) | |
971 | return true; | |
972 | else | |
973 | return false; | |
974 | }; | |
975 | ||
976 | static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) | |
977 | { | |
978 | u32 lb_partitions = wm->lb_size / wm->src_width; | |
979 | u32 line_time = wm->active_time + wm->blank_time; | |
980 | u32 latency_tolerant_lines; | |
981 | u32 latency_hiding; | |
982 | fixed20_12 a; | |
983 | ||
984 | a.full = dfixed_const(1); | |
985 | if (wm->vsc.full > a.full) | |
986 | latency_tolerant_lines = 1; | |
987 | else { | |
988 | if (lb_partitions <= (wm->vtaps + 1)) | |
989 | latency_tolerant_lines = 1; | |
990 | else | |
991 | latency_tolerant_lines = 2; | |
992 | } | |
993 | ||
994 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); | |
995 | ||
996 | if (evergreen_latency_watermark(wm) <= latency_hiding) | |
997 | return true; | |
998 | else | |
999 | return false; | |
1000 | } | |
1001 | ||
1002 | static void evergreen_program_watermarks(struct radeon_device *rdev, | |
1003 | struct radeon_crtc *radeon_crtc, | |
1004 | u32 lb_size, u32 num_heads) | |
1005 | { | |
1006 | struct drm_display_mode *mode = &radeon_crtc->base.mode; | |
1007 | struct evergreen_wm_params wm; | |
1008 | u32 pixel_period; | |
1009 | u32 line_time = 0; | |
1010 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | |
1011 | u32 priority_a_mark = 0, priority_b_mark = 0; | |
1012 | u32 priority_a_cnt = PRIORITY_OFF; | |
1013 | u32 priority_b_cnt = PRIORITY_OFF; | |
1014 | u32 pipe_offset = radeon_crtc->crtc_id * 16; | |
1015 | u32 tmp, arb_control3; | |
1016 | fixed20_12 a, b, c; | |
1017 | ||
1018 | if (radeon_crtc->base.enabled && num_heads && mode) { | |
1019 | pixel_period = 1000000 / (u32)mode->clock; | |
1020 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | |
1021 | priority_a_cnt = 0; | |
1022 | priority_b_cnt = 0; | |
1023 | ||
1024 | wm.yclk = rdev->pm.current_mclk * 10; | |
1025 | wm.sclk = rdev->pm.current_sclk * 10; | |
1026 | wm.disp_clk = mode->clock; | |
1027 | wm.src_width = mode->crtc_hdisplay; | |
1028 | wm.active_time = mode->crtc_hdisplay * pixel_period; | |
1029 | wm.blank_time = line_time - wm.active_time; | |
1030 | wm.interlaced = false; | |
1031 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1032 | wm.interlaced = true; | |
1033 | wm.vsc = radeon_crtc->vsc; | |
1034 | wm.vtaps = 1; | |
1035 | if (radeon_crtc->rmx_type != RMX_OFF) | |
1036 | wm.vtaps = 2; | |
1037 | wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
1038 | wm.lb_size = lb_size; | |
1039 | wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); | |
1040 | wm.num_heads = num_heads; | |
1041 | ||
1042 | /* set for high clocks */ | |
1043 | latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); | |
1044 | /* set for low clocks */ | |
1045 | /* wm.yclk = low clk; wm.sclk = low clk */ | |
1046 | latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); | |
1047 | ||
1048 | /* possibly force display priority to high */ | |
1049 | /* should really do this at mode validation time... */ | |
1050 | if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || | |
1051 | !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || | |
1052 | !evergreen_check_latency_hiding(&wm) || | |
1053 | (rdev->disp_priority == 2)) { | |
92bdfd4a | 1054 | DRM_DEBUG_KMS("force priority to high\n"); |
f9d9c362 AD |
1055 | priority_a_cnt |= PRIORITY_ALWAYS_ON; |
1056 | priority_b_cnt |= PRIORITY_ALWAYS_ON; | |
1057 | } | |
1058 | ||
1059 | a.full = dfixed_const(1000); | |
1060 | b.full = dfixed_const(mode->clock); | |
1061 | b.full = dfixed_div(b, a); | |
1062 | c.full = dfixed_const(latency_watermark_a); | |
1063 | c.full = dfixed_mul(c, b); | |
1064 | c.full = dfixed_mul(c, radeon_crtc->hsc); | |
1065 | c.full = dfixed_div(c, a); | |
1066 | a.full = dfixed_const(16); | |
1067 | c.full = dfixed_div(c, a); | |
1068 | priority_a_mark = dfixed_trunc(c); | |
1069 | priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; | |
1070 | ||
1071 | a.full = dfixed_const(1000); | |
1072 | b.full = dfixed_const(mode->clock); | |
1073 | b.full = dfixed_div(b, a); | |
1074 | c.full = dfixed_const(latency_watermark_b); | |
1075 | c.full = dfixed_mul(c, b); | |
1076 | c.full = dfixed_mul(c, radeon_crtc->hsc); | |
1077 | c.full = dfixed_div(c, a); | |
1078 | a.full = dfixed_const(16); | |
1079 | c.full = dfixed_div(c, a); | |
1080 | priority_b_mark = dfixed_trunc(c); | |
1081 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; | |
1082 | } | |
1083 | ||
1084 | /* select wm A */ | |
1085 | arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); | |
1086 | tmp = arb_control3; | |
1087 | tmp &= ~LATENCY_WATERMARK_MASK(3); | |
1088 | tmp |= LATENCY_WATERMARK_MASK(1); | |
1089 | WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); | |
1090 | WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, | |
1091 | (LATENCY_LOW_WATERMARK(latency_watermark_a) | | |
1092 | LATENCY_HIGH_WATERMARK(line_time))); | |
1093 | /* select wm B */ | |
1094 | tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); | |
1095 | tmp &= ~LATENCY_WATERMARK_MASK(3); | |
1096 | tmp |= LATENCY_WATERMARK_MASK(2); | |
1097 | WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); | |
1098 | WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, | |
1099 | (LATENCY_LOW_WATERMARK(latency_watermark_b) | | |
1100 | LATENCY_HIGH_WATERMARK(line_time))); | |
1101 | /* restore original selection */ | |
1102 | WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); | |
1103 | ||
1104 | /* write the priority marks */ | |
1105 | WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); | |
1106 | WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); | |
1107 | ||
1108 | } | |
1109 | ||
377edc8b AD |
1110 | /** |
1111 | * evergreen_bandwidth_update - update display watermarks callback. | |
1112 | * | |
1113 | * @rdev: radeon_device pointer | |
1114 | * | |
1115 | * Update the display watermarks based on the requested mode(s) | |
1116 | * (evergreen+). | |
1117 | */ | |
0ca2ab52 | 1118 | void evergreen_bandwidth_update(struct radeon_device *rdev) |
bcc1c2a1 | 1119 | { |
f9d9c362 AD |
1120 | struct drm_display_mode *mode0 = NULL; |
1121 | struct drm_display_mode *mode1 = NULL; | |
1122 | u32 num_heads = 0, lb_size; | |
1123 | int i; | |
1124 | ||
1125 | radeon_update_display_priority(rdev); | |
1126 | ||
1127 | for (i = 0; i < rdev->num_crtc; i++) { | |
1128 | if (rdev->mode_info.crtcs[i]->base.enabled) | |
1129 | num_heads++; | |
1130 | } | |
1131 | for (i = 0; i < rdev->num_crtc; i += 2) { | |
1132 | mode0 = &rdev->mode_info.crtcs[i]->base.mode; | |
1133 | mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; | |
1134 | lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); | |
1135 | evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); | |
1136 | lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); | |
1137 | evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); | |
1138 | } | |
bcc1c2a1 AD |
1139 | } |
1140 | ||
377edc8b AD |
1141 | /** |
1142 | * evergreen_mc_wait_for_idle - wait for MC idle callback. | |
1143 | * | |
1144 | * @rdev: radeon_device pointer | |
1145 | * | |
1146 | * Wait for the MC (memory controller) to be idle. | |
1147 | * (evergreen+). | |
1148 | * Returns 0 if the MC is idle, -1 if not. | |
1149 | */ | |
b9952a8a | 1150 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev) |
bcc1c2a1 AD |
1151 | { |
1152 | unsigned i; | |
1153 | u32 tmp; | |
1154 | ||
1155 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1156 | /* read MC_STATUS */ | |
1157 | tmp = RREG32(SRBM_STATUS) & 0x1F00; | |
1158 | if (!tmp) | |
1159 | return 0; | |
1160 | udelay(1); | |
1161 | } | |
1162 | return -1; | |
1163 | } | |
1164 | ||
1165 | /* | |
1166 | * GART | |
1167 | */ | |
0fcdb61e AD |
1168 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) |
1169 | { | |
1170 | unsigned i; | |
1171 | u32 tmp; | |
1172 | ||
6f2f48a9 AD |
1173 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); |
1174 | ||
0fcdb61e AD |
1175 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); |
1176 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1177 | /* read MC_STATUS */ | |
1178 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
1179 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
1180 | if (tmp == 2) { | |
1181 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
1182 | return; | |
1183 | } | |
1184 | if (tmp) { | |
1185 | return; | |
1186 | } | |
1187 | udelay(1); | |
1188 | } | |
1189 | } | |
1190 | ||
1109ca09 | 1191 | static int evergreen_pcie_gart_enable(struct radeon_device *rdev) |
bcc1c2a1 AD |
1192 | { |
1193 | u32 tmp; | |
0fcdb61e | 1194 | int r; |
bcc1c2a1 | 1195 | |
c9a1be96 | 1196 | if (rdev->gart.robj == NULL) { |
bcc1c2a1 AD |
1197 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
1198 | return -EINVAL; | |
1199 | } | |
1200 | r = radeon_gart_table_vram_pin(rdev); | |
1201 | if (r) | |
1202 | return r; | |
82568565 | 1203 | radeon_gart_restore(rdev); |
bcc1c2a1 AD |
1204 | /* Setup L2 cache */ |
1205 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1206 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1207 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1208 | WREG32(VM_L2_CNTL2, 0); | |
1209 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
1210 | /* Setup TLB control */ | |
1211 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1212 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1213 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
1214 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
8aeb96f8 AD |
1215 | if (rdev->flags & RADEON_IS_IGP) { |
1216 | WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); | |
1217 | WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); | |
1218 | WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); | |
1219 | } else { | |
1220 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
1221 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
1222 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
0b8c30bc AD |
1223 | if ((rdev->family == CHIP_JUNIPER) || |
1224 | (rdev->family == CHIP_CYPRESS) || | |
1225 | (rdev->family == CHIP_HEMLOCK) || | |
1226 | (rdev->family == CHIP_BARTS)) | |
1227 | WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); | |
8aeb96f8 | 1228 | } |
bcc1c2a1 AD |
1229 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
1230 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
1231 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
1232 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
1233 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1234 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); | |
1235 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); | |
1236 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
1237 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
1238 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
1239 | (u32)(rdev->dummy_page.addr >> 12)); | |
0fcdb61e | 1240 | WREG32(VM_CONTEXT1_CNTL, 0); |
bcc1c2a1 | 1241 | |
0fcdb61e | 1242 | evergreen_pcie_gart_tlb_flush(rdev); |
fcf4de5a TV |
1243 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
1244 | (unsigned)(rdev->mc.gtt_size >> 20), | |
1245 | (unsigned long long)rdev->gart.table_addr); | |
bcc1c2a1 AD |
1246 | rdev->gart.ready = true; |
1247 | return 0; | |
1248 | } | |
1249 | ||
1109ca09 | 1250 | static void evergreen_pcie_gart_disable(struct radeon_device *rdev) |
bcc1c2a1 AD |
1251 | { |
1252 | u32 tmp; | |
bcc1c2a1 AD |
1253 | |
1254 | /* Disable all tables */ | |
0fcdb61e AD |
1255 | WREG32(VM_CONTEXT0_CNTL, 0); |
1256 | WREG32(VM_CONTEXT1_CNTL, 0); | |
bcc1c2a1 AD |
1257 | |
1258 | /* Setup L2 cache */ | |
1259 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
1260 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1261 | WREG32(VM_L2_CNTL2, 0); | |
1262 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
1263 | /* Setup TLB control */ | |
1264 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
1265 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
1266 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
1267 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
1268 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
1269 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
1270 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
1271 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
c9a1be96 | 1272 | radeon_gart_table_vram_unpin(rdev); |
bcc1c2a1 AD |
1273 | } |
1274 | ||
1109ca09 | 1275 | static void evergreen_pcie_gart_fini(struct radeon_device *rdev) |
bcc1c2a1 AD |
1276 | { |
1277 | evergreen_pcie_gart_disable(rdev); | |
1278 | radeon_gart_table_vram_free(rdev); | |
1279 | radeon_gart_fini(rdev); | |
1280 | } | |
1281 | ||
1282 | ||
1109ca09 | 1283 | static void evergreen_agp_enable(struct radeon_device *rdev) |
bcc1c2a1 AD |
1284 | { |
1285 | u32 tmp; | |
bcc1c2a1 AD |
1286 | |
1287 | /* Setup L2 cache */ | |
1288 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1289 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1290 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1291 | WREG32(VM_L2_CNTL2, 0); | |
1292 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); | |
1293 | /* Setup TLB control */ | |
1294 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1295 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1296 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
1297 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); | |
1298 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); | |
1299 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); | |
1300 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); | |
1301 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); | |
1302 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); | |
1303 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); | |
1304 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); | |
0fcdb61e AD |
1305 | WREG32(VM_CONTEXT0_CNTL, 0); |
1306 | WREG32(VM_CONTEXT1_CNTL, 0); | |
bcc1c2a1 AD |
1307 | } |
1308 | ||
b9952a8a | 1309 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) |
bcc1c2a1 | 1310 | { |
62444b74 AD |
1311 | u32 crtc_enabled, tmp, frame_count, blackout; |
1312 | int i, j; | |
1313 | ||
bcc1c2a1 AD |
1314 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); |
1315 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); | |
bcc1c2a1 | 1316 | |
62444b74 | 1317 | /* disable VGA render */ |
bcc1c2a1 | 1318 | WREG32(VGA_RENDER_CONTROL, 0); |
62444b74 AD |
1319 | /* blank the display controllers */ |
1320 | for (i = 0; i < rdev->num_crtc; i++) { | |
1321 | crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; | |
1322 | if (crtc_enabled) { | |
1323 | save->crtc_enabled[i] = true; | |
1324 | if (ASIC_IS_DCE6(rdev)) { | |
1325 | tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); | |
1326 | if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { | |
1327 | radeon_wait_for_vblank(rdev, i); | |
1328 | tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; | |
bb588820 | 1329 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
62444b74 | 1330 | WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); |
bb588820 | 1331 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
62444b74 AD |
1332 | } |
1333 | } else { | |
1334 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); | |
1335 | if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { | |
1336 | radeon_wait_for_vblank(rdev, i); | |
1337 | tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
bb588820 | 1338 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
62444b74 | 1339 | WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); |
bb588820 | 1340 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
62444b74 AD |
1341 | } |
1342 | } | |
1343 | /* wait for the next frame */ | |
1344 | frame_count = radeon_get_vblank_counter(rdev, i); | |
1345 | for (j = 0; j < rdev->usec_timeout; j++) { | |
1346 | if (radeon_get_vblank_counter(rdev, i) != frame_count) | |
1347 | break; | |
1348 | udelay(1); | |
1349 | } | |
804cc4a0 AD |
1350 | } else { |
1351 | save->crtc_enabled[i] = false; | |
62444b74 | 1352 | } |
18007401 | 1353 | } |
bcc1c2a1 | 1354 | |
62444b74 AD |
1355 | radeon_mc_wait_for_idle(rdev); |
1356 | ||
1357 | blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); | |
1358 | if ((blackout & BLACKOUT_MODE_MASK) != 1) { | |
1359 | /* Block CPU access */ | |
1360 | WREG32(BIF_FB_EN, 0); | |
1361 | /* blackout the MC */ | |
1362 | blackout &= ~BLACKOUT_MODE_MASK; | |
1363 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); | |
b7eff394 | 1364 | } |
ed39fadd AD |
1365 | /* wait for the MC to settle */ |
1366 | udelay(100); | |
bcc1c2a1 AD |
1367 | } |
1368 | ||
b9952a8a | 1369 | void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) |
bcc1c2a1 | 1370 | { |
62444b74 AD |
1371 | u32 tmp, frame_count; |
1372 | int i, j; | |
18007401 | 1373 | |
62444b74 AD |
1374 | /* update crtc base addresses */ |
1375 | for (i = 0; i < rdev->num_crtc; i++) { | |
1376 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], | |
18007401 | 1377 | upper_32_bits(rdev->mc.vram_start)); |
62444b74 | 1378 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], |
18007401 | 1379 | upper_32_bits(rdev->mc.vram_start)); |
62444b74 | 1380 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
18007401 | 1381 | (u32)rdev->mc.vram_start); |
62444b74 | 1382 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
18007401 AD |
1383 | (u32)rdev->mc.vram_start); |
1384 | } | |
bcc1c2a1 AD |
1385 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); |
1386 | WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); | |
62444b74 AD |
1387 | |
1388 | /* unblackout the MC */ | |
1389 | tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); | |
1390 | tmp &= ~BLACKOUT_MODE_MASK; | |
1391 | WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); | |
1392 | /* allow CPU access */ | |
1393 | WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); | |
1394 | ||
1395 | for (i = 0; i < rdev->num_crtc; i++) { | |
695ddeb4 | 1396 | if (save->crtc_enabled[i]) { |
62444b74 AD |
1397 | if (ASIC_IS_DCE6(rdev)) { |
1398 | tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); | |
1399 | tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; | |
bb588820 | 1400 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
62444b74 | 1401 | WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); |
bb588820 | 1402 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
62444b74 AD |
1403 | } else { |
1404 | tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); | |
1405 | tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; | |
bb588820 | 1406 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
62444b74 | 1407 | WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); |
bb588820 | 1408 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
62444b74 AD |
1409 | } |
1410 | /* wait for the next frame */ | |
1411 | frame_count = radeon_get_vblank_counter(rdev, i); | |
1412 | for (j = 0; j < rdev->usec_timeout; j++) { | |
1413 | if (radeon_get_vblank_counter(rdev, i) != frame_count) | |
1414 | break; | |
1415 | udelay(1); | |
1416 | } | |
1417 | } | |
1418 | } | |
1419 | /* Unlock vga access */ | |
bcc1c2a1 AD |
1420 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); |
1421 | mdelay(1); | |
bcc1c2a1 AD |
1422 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); |
1423 | } | |
1424 | ||
755d819e | 1425 | void evergreen_mc_program(struct radeon_device *rdev) |
bcc1c2a1 AD |
1426 | { |
1427 | struct evergreen_mc_save save; | |
1428 | u32 tmp; | |
1429 | int i, j; | |
1430 | ||
1431 | /* Initialize HDP */ | |
1432 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1433 | WREG32((0x2c14 + j), 0x00000000); | |
1434 | WREG32((0x2c18 + j), 0x00000000); | |
1435 | WREG32((0x2c1c + j), 0x00000000); | |
1436 | WREG32((0x2c20 + j), 0x00000000); | |
1437 | WREG32((0x2c24 + j), 0x00000000); | |
1438 | } | |
1439 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
1440 | ||
1441 | evergreen_mc_stop(rdev, &save); | |
1442 | if (evergreen_mc_wait_for_idle(rdev)) { | |
1443 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1444 | } | |
1445 | /* Lockout access through VGA aperture*/ | |
1446 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | |
1447 | /* Update configuration */ | |
1448 | if (rdev->flags & RADEON_IS_AGP) { | |
1449 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
1450 | /* VRAM before AGP */ | |
1451 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1452 | rdev->mc.vram_start >> 12); | |
1453 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1454 | rdev->mc.gtt_end >> 12); | |
1455 | } else { | |
1456 | /* VRAM after AGP */ | |
1457 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1458 | rdev->mc.gtt_start >> 12); | |
1459 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1460 | rdev->mc.vram_end >> 12); | |
1461 | } | |
1462 | } else { | |
1463 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1464 | rdev->mc.vram_start >> 12); | |
1465 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1466 | rdev->mc.vram_end >> 12); | |
1467 | } | |
3b9832f6 | 1468 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
05b3ef69 AD |
1469 | /* llano/ontario only */ |
1470 | if ((rdev->family == CHIP_PALM) || | |
1471 | (rdev->family == CHIP_SUMO) || | |
1472 | (rdev->family == CHIP_SUMO2)) { | |
b4183e30 AD |
1473 | tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; |
1474 | tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; | |
1475 | tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; | |
1476 | WREG32(MC_FUS_VM_FB_OFFSET, tmp); | |
1477 | } | |
bcc1c2a1 AD |
1478 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
1479 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); | |
1480 | WREG32(MC_VM_FB_LOCATION, tmp); | |
1481 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
c46cb4da | 1482 | WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); |
46fcd2b3 | 1483 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
bcc1c2a1 AD |
1484 | if (rdev->flags & RADEON_IS_AGP) { |
1485 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); | |
1486 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); | |
1487 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); | |
1488 | } else { | |
1489 | WREG32(MC_VM_AGP_BASE, 0); | |
1490 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
1491 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
1492 | } | |
1493 | if (evergreen_mc_wait_for_idle(rdev)) { | |
1494 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1495 | } | |
1496 | evergreen_mc_resume(rdev, &save); | |
1497 | /* we need to own VRAM, so turn off the VGA renderer here | |
1498 | * to stop it overwriting our objects */ | |
1499 | rv515_vga_render_disable(rdev); | |
1500 | } | |
1501 | ||
bcc1c2a1 AD |
1502 | /* |
1503 | * CP. | |
1504 | */ | |
12920591 AD |
1505 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
1506 | { | |
876dc9f3 | 1507 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
89d35807 | 1508 | u32 next_rptr; |
7b1f2485 | 1509 | |
12920591 | 1510 | /* set to DX10/11 mode */ |
e32eb50d CK |
1511 | radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); |
1512 | radeon_ring_write(ring, 1); | |
45df6803 CK |
1513 | |
1514 | if (ring->rptr_save_reg) { | |
89d35807 | 1515 | next_rptr = ring->wptr + 3 + 4; |
45df6803 CK |
1516 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
1517 | radeon_ring_write(ring, ((ring->rptr_save_reg - | |
1518 | PACKET3_SET_CONFIG_REG_START) >> 2)); | |
1519 | radeon_ring_write(ring, next_rptr); | |
89d35807 AD |
1520 | } else if (rdev->wb.enabled) { |
1521 | next_rptr = ring->wptr + 5 + 4; | |
1522 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); | |
1523 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
1524 | radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); | |
1525 | radeon_ring_write(ring, next_rptr); | |
1526 | radeon_ring_write(ring, 0); | |
45df6803 CK |
1527 | } |
1528 | ||
e32eb50d CK |
1529 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
1530 | radeon_ring_write(ring, | |
0f234f5f AD |
1531 | #ifdef __BIG_ENDIAN |
1532 | (2 << 0) | | |
1533 | #endif | |
1534 | (ib->gpu_addr & 0xFFFFFFFC)); | |
e32eb50d CK |
1535 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
1536 | radeon_ring_write(ring, ib->length_dw); | |
12920591 AD |
1537 | } |
1538 | ||
bcc1c2a1 AD |
1539 | |
1540 | static int evergreen_cp_load_microcode(struct radeon_device *rdev) | |
1541 | { | |
fe251e2f AD |
1542 | const __be32 *fw_data; |
1543 | int i; | |
1544 | ||
1545 | if (!rdev->me_fw || !rdev->pfp_fw) | |
1546 | return -EINVAL; | |
bcc1c2a1 | 1547 | |
fe251e2f | 1548 | r700_cp_stop(rdev); |
0f234f5f AD |
1549 | WREG32(CP_RB_CNTL, |
1550 | #ifdef __BIG_ENDIAN | |
1551 | BUF_SWAP_32BIT | | |
1552 | #endif | |
1553 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
fe251e2f AD |
1554 | |
1555 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
1556 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1557 | for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) | |
1558 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | |
1559 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1560 | ||
1561 | fw_data = (const __be32 *)rdev->me_fw->data; | |
1562 | WREG32(CP_ME_RAM_WADDR, 0); | |
1563 | for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) | |
1564 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | |
1565 | ||
1566 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1567 | WREG32(CP_ME_RAM_WADDR, 0); | |
1568 | WREG32(CP_ME_RAM_RADDR, 0); | |
bcc1c2a1 AD |
1569 | return 0; |
1570 | } | |
1571 | ||
7e7b41d2 AD |
1572 | static int evergreen_cp_start(struct radeon_device *rdev) |
1573 | { | |
e32eb50d | 1574 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
2281a378 | 1575 | int r, i; |
7e7b41d2 AD |
1576 | uint32_t cp_me; |
1577 | ||
e32eb50d | 1578 | r = radeon_ring_lock(rdev, ring, 7); |
7e7b41d2 AD |
1579 | if (r) { |
1580 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1581 | return r; | |
1582 | } | |
e32eb50d CK |
1583 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
1584 | radeon_ring_write(ring, 0x1); | |
1585 | radeon_ring_write(ring, 0x0); | |
1586 | radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); | |
1587 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
1588 | radeon_ring_write(ring, 0); | |
1589 | radeon_ring_write(ring, 0); | |
1590 | radeon_ring_unlock_commit(rdev, ring); | |
7e7b41d2 AD |
1591 | |
1592 | cp_me = 0xff; | |
1593 | WREG32(CP_ME_CNTL, cp_me); | |
1594 | ||
e32eb50d | 1595 | r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); |
7e7b41d2 AD |
1596 | if (r) { |
1597 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1598 | return r; | |
1599 | } | |
2281a378 AD |
1600 | |
1601 | /* setup clear context state */ | |
e32eb50d CK |
1602 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1603 | radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
2281a378 AD |
1604 | |
1605 | for (i = 0; i < evergreen_default_size; i++) | |
e32eb50d | 1606 | radeon_ring_write(ring, evergreen_default_state[i]); |
2281a378 | 1607 | |
e32eb50d CK |
1608 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); |
1609 | radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); | |
2281a378 AD |
1610 | |
1611 | /* set clear context state */ | |
e32eb50d CK |
1612 | radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
1613 | radeon_ring_write(ring, 0); | |
2281a378 AD |
1614 | |
1615 | /* SQ_VTX_BASE_VTX_LOC */ | |
e32eb50d CK |
1616 | radeon_ring_write(ring, 0xc0026f00); |
1617 | radeon_ring_write(ring, 0x00000000); | |
1618 | radeon_ring_write(ring, 0x00000000); | |
1619 | radeon_ring_write(ring, 0x00000000); | |
2281a378 AD |
1620 | |
1621 | /* Clear consts */ | |
e32eb50d CK |
1622 | radeon_ring_write(ring, 0xc0036f00); |
1623 | radeon_ring_write(ring, 0x00000bc4); | |
1624 | radeon_ring_write(ring, 0xffffffff); | |
1625 | radeon_ring_write(ring, 0xffffffff); | |
1626 | radeon_ring_write(ring, 0xffffffff); | |
2281a378 | 1627 | |
e32eb50d CK |
1628 | radeon_ring_write(ring, 0xc0026900); |
1629 | radeon_ring_write(ring, 0x00000316); | |
1630 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | |
1631 | radeon_ring_write(ring, 0x00000010); /* */ | |
18ff84da | 1632 | |
e32eb50d | 1633 | radeon_ring_unlock_commit(rdev, ring); |
7e7b41d2 AD |
1634 | |
1635 | return 0; | |
1636 | } | |
1637 | ||
1109ca09 | 1638 | static int evergreen_cp_resume(struct radeon_device *rdev) |
fe251e2f | 1639 | { |
e32eb50d | 1640 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
fe251e2f AD |
1641 | u32 tmp; |
1642 | u32 rb_bufsz; | |
1643 | int r; | |
1644 | ||
1645 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ | |
1646 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | | |
1647 | SOFT_RESET_PA | | |
1648 | SOFT_RESET_SH | | |
1649 | SOFT_RESET_VGT | | |
a49a50da | 1650 | SOFT_RESET_SPI | |
fe251e2f AD |
1651 | SOFT_RESET_SX)); |
1652 | RREG32(GRBM_SOFT_RESET); | |
1653 | mdelay(15); | |
1654 | WREG32(GRBM_SOFT_RESET, 0); | |
1655 | RREG32(GRBM_SOFT_RESET); | |
1656 | ||
1657 | /* Set ring buffer size */ | |
e32eb50d | 1658 | rb_bufsz = drm_order(ring->ring_size / 8); |
724c80e1 | 1659 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
fe251e2f AD |
1660 | #ifdef __BIG_ENDIAN |
1661 | tmp |= BUF_SWAP_32BIT; | |
32fcdbf4 | 1662 | #endif |
fe251e2f | 1663 | WREG32(CP_RB_CNTL, tmp); |
15d3332f | 1664 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
11ef3f1f | 1665 | WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); |
fe251e2f AD |
1666 | |
1667 | /* Set the write pointer delay */ | |
1668 | WREG32(CP_RB_WPTR_DELAY, 0); | |
1669 | ||
1670 | /* Initialize the ring buffer's read and write pointers */ | |
1671 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); | |
1672 | WREG32(CP_RB_RPTR_WR, 0); | |
e32eb50d CK |
1673 | ring->wptr = 0; |
1674 | WREG32(CP_RB_WPTR, ring->wptr); | |
724c80e1 | 1675 | |
48fc7f7e | 1676 | /* set the wb address whether it's enabled or not */ |
0f234f5f | 1677 | WREG32(CP_RB_RPTR_ADDR, |
0f234f5f | 1678 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
724c80e1 AD |
1679 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
1680 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | |
1681 | ||
1682 | if (rdev->wb.enabled) | |
1683 | WREG32(SCRATCH_UMSK, 0xff); | |
1684 | else { | |
1685 | tmp |= RB_NO_UPDATE; | |
1686 | WREG32(SCRATCH_UMSK, 0); | |
1687 | } | |
1688 | ||
fe251e2f AD |
1689 | mdelay(1); |
1690 | WREG32(CP_RB_CNTL, tmp); | |
1691 | ||
e32eb50d | 1692 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
fe251e2f AD |
1693 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
1694 | ||
e32eb50d | 1695 | ring->rptr = RREG32(CP_RB_RPTR); |
fe251e2f | 1696 | |
7e7b41d2 | 1697 | evergreen_cp_start(rdev); |
e32eb50d | 1698 | ring->ready = true; |
f712812e | 1699 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
fe251e2f | 1700 | if (r) { |
e32eb50d | 1701 | ring->ready = false; |
fe251e2f AD |
1702 | return r; |
1703 | } | |
1704 | return 0; | |
1705 | } | |
bcc1c2a1 AD |
1706 | |
1707 | /* | |
1708 | * Core functions | |
1709 | */ | |
bcc1c2a1 AD |
1710 | static void evergreen_gpu_init(struct radeon_device *rdev) |
1711 | { | |
416a2bd2 | 1712 | u32 gb_addr_config; |
32fcdbf4 | 1713 | u32 mc_shared_chmap, mc_arb_ramcfg; |
32fcdbf4 AD |
1714 | u32 sx_debug_1; |
1715 | u32 smx_dc_ctl0; | |
1716 | u32 sq_config; | |
1717 | u32 sq_lds_resource_mgmt; | |
1718 | u32 sq_gpr_resource_mgmt_1; | |
1719 | u32 sq_gpr_resource_mgmt_2; | |
1720 | u32 sq_gpr_resource_mgmt_3; | |
1721 | u32 sq_thread_resource_mgmt; | |
1722 | u32 sq_thread_resource_mgmt_2; | |
1723 | u32 sq_stack_resource_mgmt_1; | |
1724 | u32 sq_stack_resource_mgmt_2; | |
1725 | u32 sq_stack_resource_mgmt_3; | |
1726 | u32 vgt_cache_invalidation; | |
f25a5c63 | 1727 | u32 hdp_host_path_cntl, tmp; |
416a2bd2 | 1728 | u32 disabled_rb_mask; |
32fcdbf4 AD |
1729 | int i, j, num_shader_engines, ps_thread_count; |
1730 | ||
1731 | switch (rdev->family) { | |
1732 | case CHIP_CYPRESS: | |
1733 | case CHIP_HEMLOCK: | |
1734 | rdev->config.evergreen.num_ses = 2; | |
1735 | rdev->config.evergreen.max_pipes = 4; | |
1736 | rdev->config.evergreen.max_tile_pipes = 8; | |
1737 | rdev->config.evergreen.max_simds = 10; | |
1738 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
1739 | rdev->config.evergreen.max_gprs = 256; | |
1740 | rdev->config.evergreen.max_threads = 248; | |
1741 | rdev->config.evergreen.max_gs_threads = 32; | |
1742 | rdev->config.evergreen.max_stack_entries = 512; | |
1743 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1744 | rdev->config.evergreen.sx_max_export_size = 256; | |
1745 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1746 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1747 | rdev->config.evergreen.max_hw_contexts = 8; | |
1748 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1749 | ||
1750 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1751 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1752 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1753 | gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN; |
32fcdbf4 AD |
1754 | break; |
1755 | case CHIP_JUNIPER: | |
1756 | rdev->config.evergreen.num_ses = 1; | |
1757 | rdev->config.evergreen.max_pipes = 4; | |
1758 | rdev->config.evergreen.max_tile_pipes = 4; | |
1759 | rdev->config.evergreen.max_simds = 10; | |
1760 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
1761 | rdev->config.evergreen.max_gprs = 256; | |
1762 | rdev->config.evergreen.max_threads = 248; | |
1763 | rdev->config.evergreen.max_gs_threads = 32; | |
1764 | rdev->config.evergreen.max_stack_entries = 512; | |
1765 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1766 | rdev->config.evergreen.sx_max_export_size = 256; | |
1767 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1768 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1769 | rdev->config.evergreen.max_hw_contexts = 8; | |
1770 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1771 | ||
1772 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1773 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1774 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1775 | gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN; |
32fcdbf4 AD |
1776 | break; |
1777 | case CHIP_REDWOOD: | |
1778 | rdev->config.evergreen.num_ses = 1; | |
1779 | rdev->config.evergreen.max_pipes = 4; | |
1780 | rdev->config.evergreen.max_tile_pipes = 4; | |
1781 | rdev->config.evergreen.max_simds = 5; | |
1782 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
1783 | rdev->config.evergreen.max_gprs = 256; | |
1784 | rdev->config.evergreen.max_threads = 248; | |
1785 | rdev->config.evergreen.max_gs_threads = 32; | |
1786 | rdev->config.evergreen.max_stack_entries = 256; | |
1787 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1788 | rdev->config.evergreen.sx_max_export_size = 256; | |
1789 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1790 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1791 | rdev->config.evergreen.max_hw_contexts = 8; | |
1792 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1793 | ||
1794 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1795 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1796 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1797 | gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; |
32fcdbf4 AD |
1798 | break; |
1799 | case CHIP_CEDAR: | |
1800 | default: | |
1801 | rdev->config.evergreen.num_ses = 1; | |
1802 | rdev->config.evergreen.max_pipes = 2; | |
1803 | rdev->config.evergreen.max_tile_pipes = 2; | |
1804 | rdev->config.evergreen.max_simds = 2; | |
1805 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1806 | rdev->config.evergreen.max_gprs = 256; | |
1807 | rdev->config.evergreen.max_threads = 192; | |
1808 | rdev->config.evergreen.max_gs_threads = 16; | |
1809 | rdev->config.evergreen.max_stack_entries = 256; | |
1810 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1811 | rdev->config.evergreen.sx_max_export_size = 128; | |
1812 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1813 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1814 | rdev->config.evergreen.max_hw_contexts = 4; | |
1815 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1816 | ||
d5e455e4 AD |
1817 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1818 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1819 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1820 | gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; |
d5e455e4 AD |
1821 | break; |
1822 | case CHIP_PALM: | |
1823 | rdev->config.evergreen.num_ses = 1; | |
1824 | rdev->config.evergreen.max_pipes = 2; | |
1825 | rdev->config.evergreen.max_tile_pipes = 2; | |
1826 | rdev->config.evergreen.max_simds = 2; | |
1827 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1828 | rdev->config.evergreen.max_gprs = 256; | |
1829 | rdev->config.evergreen.max_threads = 192; | |
1830 | rdev->config.evergreen.max_gs_threads = 16; | |
1831 | rdev->config.evergreen.max_stack_entries = 256; | |
1832 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1833 | rdev->config.evergreen.sx_max_export_size = 128; | |
1834 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1835 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1836 | rdev->config.evergreen.max_hw_contexts = 4; | |
1837 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1838 | ||
d5c5a72f AD |
1839 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1840 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1841 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1842 | gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; |
d5c5a72f AD |
1843 | break; |
1844 | case CHIP_SUMO: | |
1845 | rdev->config.evergreen.num_ses = 1; | |
1846 | rdev->config.evergreen.max_pipes = 4; | |
bd25f078 | 1847 | rdev->config.evergreen.max_tile_pipes = 4; |
d5c5a72f AD |
1848 | if (rdev->pdev->device == 0x9648) |
1849 | rdev->config.evergreen.max_simds = 3; | |
1850 | else if ((rdev->pdev->device == 0x9647) || | |
1851 | (rdev->pdev->device == 0x964a)) | |
1852 | rdev->config.evergreen.max_simds = 4; | |
1853 | else | |
1854 | rdev->config.evergreen.max_simds = 5; | |
1855 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
1856 | rdev->config.evergreen.max_gprs = 256; | |
1857 | rdev->config.evergreen.max_threads = 248; | |
1858 | rdev->config.evergreen.max_gs_threads = 32; | |
1859 | rdev->config.evergreen.max_stack_entries = 256; | |
1860 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1861 | rdev->config.evergreen.sx_max_export_size = 256; | |
1862 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1863 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1864 | rdev->config.evergreen.max_hw_contexts = 8; | |
1865 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1866 | ||
1867 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; | |
1868 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1869 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
bd25f078 | 1870 | gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; |
d5c5a72f AD |
1871 | break; |
1872 | case CHIP_SUMO2: | |
1873 | rdev->config.evergreen.num_ses = 1; | |
1874 | rdev->config.evergreen.max_pipes = 4; | |
1875 | rdev->config.evergreen.max_tile_pipes = 4; | |
1876 | rdev->config.evergreen.max_simds = 2; | |
1877 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1878 | rdev->config.evergreen.max_gprs = 256; | |
1879 | rdev->config.evergreen.max_threads = 248; | |
1880 | rdev->config.evergreen.max_gs_threads = 32; | |
1881 | rdev->config.evergreen.max_stack_entries = 512; | |
1882 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1883 | rdev->config.evergreen.sx_max_export_size = 256; | |
1884 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1885 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1886 | rdev->config.evergreen.max_hw_contexts = 8; | |
1887 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1888 | ||
adb68fa2 AD |
1889 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1890 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1891 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
bd25f078 | 1892 | gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN; |
adb68fa2 AD |
1893 | break; |
1894 | case CHIP_BARTS: | |
1895 | rdev->config.evergreen.num_ses = 2; | |
1896 | rdev->config.evergreen.max_pipes = 4; | |
1897 | rdev->config.evergreen.max_tile_pipes = 8; | |
1898 | rdev->config.evergreen.max_simds = 7; | |
1899 | rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; | |
1900 | rdev->config.evergreen.max_gprs = 256; | |
1901 | rdev->config.evergreen.max_threads = 248; | |
1902 | rdev->config.evergreen.max_gs_threads = 32; | |
1903 | rdev->config.evergreen.max_stack_entries = 512; | |
1904 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1905 | rdev->config.evergreen.sx_max_export_size = 256; | |
1906 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1907 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1908 | rdev->config.evergreen.max_hw_contexts = 8; | |
1909 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1910 | ||
1911 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1912 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1913 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1914 | gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN; |
adb68fa2 AD |
1915 | break; |
1916 | case CHIP_TURKS: | |
1917 | rdev->config.evergreen.num_ses = 1; | |
1918 | rdev->config.evergreen.max_pipes = 4; | |
1919 | rdev->config.evergreen.max_tile_pipes = 4; | |
1920 | rdev->config.evergreen.max_simds = 6; | |
1921 | rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; | |
1922 | rdev->config.evergreen.max_gprs = 256; | |
1923 | rdev->config.evergreen.max_threads = 248; | |
1924 | rdev->config.evergreen.max_gs_threads = 32; | |
1925 | rdev->config.evergreen.max_stack_entries = 256; | |
1926 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1927 | rdev->config.evergreen.sx_max_export_size = 256; | |
1928 | rdev->config.evergreen.sx_max_export_pos_size = 64; | |
1929 | rdev->config.evergreen.sx_max_export_smx_size = 192; | |
1930 | rdev->config.evergreen.max_hw_contexts = 8; | |
1931 | rdev->config.evergreen.sq_num_cf_insts = 2; | |
1932 | ||
1933 | rdev->config.evergreen.sc_prim_fifo_size = 0x100; | |
1934 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1935 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1936 | gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; |
adb68fa2 AD |
1937 | break; |
1938 | case CHIP_CAICOS: | |
1939 | rdev->config.evergreen.num_ses = 1; | |
bd25f078 | 1940 | rdev->config.evergreen.max_pipes = 2; |
adb68fa2 AD |
1941 | rdev->config.evergreen.max_tile_pipes = 2; |
1942 | rdev->config.evergreen.max_simds = 2; | |
1943 | rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; | |
1944 | rdev->config.evergreen.max_gprs = 256; | |
1945 | rdev->config.evergreen.max_threads = 192; | |
1946 | rdev->config.evergreen.max_gs_threads = 16; | |
1947 | rdev->config.evergreen.max_stack_entries = 256; | |
1948 | rdev->config.evergreen.sx_num_of_sets = 4; | |
1949 | rdev->config.evergreen.sx_max_export_size = 128; | |
1950 | rdev->config.evergreen.sx_max_export_pos_size = 32; | |
1951 | rdev->config.evergreen.sx_max_export_smx_size = 96; | |
1952 | rdev->config.evergreen.max_hw_contexts = 4; | |
1953 | rdev->config.evergreen.sq_num_cf_insts = 1; | |
1954 | ||
32fcdbf4 AD |
1955 | rdev->config.evergreen.sc_prim_fifo_size = 0x40; |
1956 | rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; | |
1957 | rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; | |
416a2bd2 | 1958 | gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN; |
32fcdbf4 AD |
1959 | break; |
1960 | } | |
1961 | ||
1962 | /* Initialize HDP */ | |
1963 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1964 | WREG32((0x2c14 + j), 0x00000000); | |
1965 | WREG32((0x2c18 + j), 0x00000000); | |
1966 | WREG32((0x2c1c + j), 0x00000000); | |
1967 | WREG32((0x2c20 + j), 0x00000000); | |
1968 | WREG32((0x2c24 + j), 0x00000000); | |
1969 | } | |
1970 | ||
1971 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1972 | ||
d054ac16 AD |
1973 | evergreen_fix_pci_max_read_req_size(rdev); |
1974 | ||
32fcdbf4 | 1975 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); |
05b3ef69 AD |
1976 | if ((rdev->family == CHIP_PALM) || |
1977 | (rdev->family == CHIP_SUMO) || | |
1978 | (rdev->family == CHIP_SUMO2)) | |
d9282fca AD |
1979 | mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); |
1980 | else | |
1981 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); | |
32fcdbf4 | 1982 | |
1aa52bd3 AD |
1983 | /* setup tiling info dword. gb_addr_config is not adequate since it does |
1984 | * not have bank info, so create a custom tiling dword. | |
1985 | * bits 3:0 num_pipes | |
1986 | * bits 7:4 num_banks | |
1987 | * bits 11:8 group_size | |
1988 | * bits 15:12 row_size | |
1989 | */ | |
1990 | rdev->config.evergreen.tile_config = 0; | |
1991 | switch (rdev->config.evergreen.max_tile_pipes) { | |
1992 | case 1: | |
1993 | default: | |
1994 | rdev->config.evergreen.tile_config |= (0 << 0); | |
1995 | break; | |
1996 | case 2: | |
1997 | rdev->config.evergreen.tile_config |= (1 << 0); | |
1998 | break; | |
1999 | case 4: | |
2000 | rdev->config.evergreen.tile_config |= (2 << 0); | |
2001 | break; | |
2002 | case 8: | |
2003 | rdev->config.evergreen.tile_config |= (3 << 0); | |
2004 | break; | |
2005 | } | |
d698a34d | 2006 | /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ |
5bfa4879 | 2007 | if (rdev->flags & RADEON_IS_IGP) |
d698a34d | 2008 | rdev->config.evergreen.tile_config |= 1 << 4; |
29d65406 | 2009 | else { |
c8d15edc AD |
2010 | switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { |
2011 | case 0: /* four banks */ | |
29d65406 | 2012 | rdev->config.evergreen.tile_config |= 0 << 4; |
c8d15edc AD |
2013 | break; |
2014 | case 1: /* eight banks */ | |
2015 | rdev->config.evergreen.tile_config |= 1 << 4; | |
2016 | break; | |
2017 | case 2: /* sixteen banks */ | |
2018 | default: | |
2019 | rdev->config.evergreen.tile_config |= 2 << 4; | |
2020 | break; | |
2021 | } | |
29d65406 | 2022 | } |
416a2bd2 | 2023 | rdev->config.evergreen.tile_config |= 0 << 8; |
1aa52bd3 AD |
2024 | rdev->config.evergreen.tile_config |= |
2025 | ((gb_addr_config & 0x30000000) >> 28) << 12; | |
2026 | ||
416a2bd2 | 2027 | num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1; |
32fcdbf4 | 2028 | |
416a2bd2 AD |
2029 | if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { |
2030 | u32 efuse_straps_4; | |
2031 | u32 efuse_straps_3; | |
32fcdbf4 | 2032 | |
416a2bd2 AD |
2033 | WREG32(RCU_IND_INDEX, 0x204); |
2034 | efuse_straps_4 = RREG32(RCU_IND_DATA); | |
2035 | WREG32(RCU_IND_INDEX, 0x203); | |
2036 | efuse_straps_3 = RREG32(RCU_IND_DATA); | |
2037 | tmp = (((efuse_straps_4 & 0xf) << 4) | | |
2038 | ((efuse_straps_3 & 0xf0000000) >> 28)); | |
2039 | } else { | |
2040 | tmp = 0; | |
2041 | for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { | |
2042 | u32 rb_disable_bitmap; | |
2043 | ||
2044 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); | |
2045 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); | |
2046 | rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; | |
2047 | tmp <<= 4; | |
2048 | tmp |= rb_disable_bitmap; | |
32fcdbf4 | 2049 | } |
416a2bd2 AD |
2050 | } |
2051 | /* enabled rb are just the one not disabled :) */ | |
2052 | disabled_rb_mask = tmp; | |
32fcdbf4 | 2053 | |
416a2bd2 AD |
2054 | WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); |
2055 | WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); | |
32fcdbf4 | 2056 | |
416a2bd2 AD |
2057 | WREG32(GB_ADDR_CONFIG, gb_addr_config); |
2058 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); | |
2059 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); | |
233d1ad5 | 2060 | WREG32(DMA_TILING_CONFIG, gb_addr_config); |
32fcdbf4 | 2061 | |
f7eb9730 AD |
2062 | if ((rdev->config.evergreen.max_backends == 1) && |
2063 | (rdev->flags & RADEON_IS_IGP)) { | |
2064 | if ((disabled_rb_mask & 3) == 1) { | |
2065 | /* RB0 disabled, RB1 enabled */ | |
2066 | tmp = 0x11111111; | |
2067 | } else { | |
2068 | /* RB1 disabled, RB0 enabled */ | |
2069 | tmp = 0x00000000; | |
2070 | } | |
2071 | } else { | |
2072 | tmp = gb_addr_config & NUM_PIPES_MASK; | |
2073 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, | |
2074 | EVERGREEN_MAX_BACKENDS, disabled_rb_mask); | |
2075 | } | |
416a2bd2 | 2076 | WREG32(GB_BACKEND_MAP, tmp); |
32fcdbf4 AD |
2077 | |
2078 | WREG32(CGTS_SYS_TCC_DISABLE, 0); | |
2079 | WREG32(CGTS_TCC_DISABLE, 0); | |
2080 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); | |
2081 | WREG32(CGTS_USER_TCC_DISABLE, 0); | |
2082 | ||
2083 | /* set HW defaults for 3D engine */ | |
2084 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | | |
2085 | ROQ_IB2_START(0x2b))); | |
2086 | ||
2087 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); | |
2088 | ||
2089 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | | |
2090 | SYNC_GRADIENT | | |
2091 | SYNC_WALKER | | |
2092 | SYNC_ALIGNER)); | |
2093 | ||
2094 | sx_debug_1 = RREG32(SX_DEBUG_1); | |
2095 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; | |
2096 | WREG32(SX_DEBUG_1, sx_debug_1); | |
2097 | ||
2098 | ||
2099 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); | |
2100 | smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); | |
2101 | smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); | |
2102 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); | |
2103 | ||
b866d133 AD |
2104 | if (rdev->family <= CHIP_SUMO2) |
2105 | WREG32(SMX_SAR_CTL0, 0x00010000); | |
2106 | ||
32fcdbf4 AD |
2107 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | |
2108 | POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | | |
2109 | SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); | |
2110 | ||
2111 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | | |
2112 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | | |
2113 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); | |
2114 | ||
2115 | WREG32(VGT_NUM_INSTANCES, 1); | |
2116 | WREG32(SPI_CONFIG_CNTL, 0); | |
2117 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); | |
2118 | WREG32(CP_PERFMON_CNTL, 0); | |
2119 | ||
2120 | WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | | |
2121 | FETCH_FIFO_HIWATER(0x4) | | |
2122 | DONE_FIFO_HIWATER(0xe0) | | |
2123 | ALU_UPDATE_FIFO_HIWATER(0x8))); | |
2124 | ||
2125 | sq_config = RREG32(SQ_CONFIG); | |
2126 | sq_config &= ~(PS_PRIO(3) | | |
2127 | VS_PRIO(3) | | |
2128 | GS_PRIO(3) | | |
2129 | ES_PRIO(3)); | |
2130 | sq_config |= (VC_ENABLE | | |
2131 | EXPORT_SRC_C | | |
2132 | PS_PRIO(0) | | |
2133 | VS_PRIO(1) | | |
2134 | GS_PRIO(2) | | |
2135 | ES_PRIO(3)); | |
2136 | ||
d5e455e4 AD |
2137 | switch (rdev->family) { |
2138 | case CHIP_CEDAR: | |
2139 | case CHIP_PALM: | |
d5c5a72f AD |
2140 | case CHIP_SUMO: |
2141 | case CHIP_SUMO2: | |
adb68fa2 | 2142 | case CHIP_CAICOS: |
32fcdbf4 AD |
2143 | /* no vertex cache */ |
2144 | sq_config &= ~VC_ENABLE; | |
d5e455e4 AD |
2145 | break; |
2146 | default: | |
2147 | break; | |
2148 | } | |
32fcdbf4 AD |
2149 | |
2150 | sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); | |
2151 | ||
2152 | sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); | |
2153 | sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); | |
2154 | sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); | |
2155 | sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); | |
2156 | sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); | |
2157 | sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); | |
2158 | sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); | |
2159 | ||
d5e455e4 AD |
2160 | switch (rdev->family) { |
2161 | case CHIP_CEDAR: | |
2162 | case CHIP_PALM: | |
d5c5a72f AD |
2163 | case CHIP_SUMO: |
2164 | case CHIP_SUMO2: | |
32fcdbf4 | 2165 | ps_thread_count = 96; |
d5e455e4 AD |
2166 | break; |
2167 | default: | |
32fcdbf4 | 2168 | ps_thread_count = 128; |
d5e455e4 AD |
2169 | break; |
2170 | } | |
32fcdbf4 AD |
2171 | |
2172 | sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); | |
f96b35cd AD |
2173 | sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); |
2174 | sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
2175 | sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
2176 | sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
2177 | sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); | |
32fcdbf4 AD |
2178 | |
2179 | sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2180 | sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2181 | sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2182 | sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2183 | sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2184 | sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); | |
2185 | ||
2186 | WREG32(SQ_CONFIG, sq_config); | |
2187 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
2188 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
2189 | WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); | |
2190 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
2191 | WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); | |
2192 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
2193 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
2194 | WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); | |
2195 | WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); | |
2196 | WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); | |
2197 | ||
2198 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | | |
2199 | FORCE_EOV_MAX_REZ_CNT(255))); | |
2200 | ||
d5e455e4 AD |
2201 | switch (rdev->family) { |
2202 | case CHIP_CEDAR: | |
2203 | case CHIP_PALM: | |
d5c5a72f AD |
2204 | case CHIP_SUMO: |
2205 | case CHIP_SUMO2: | |
adb68fa2 | 2206 | case CHIP_CAICOS: |
32fcdbf4 | 2207 | vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); |
d5e455e4 AD |
2208 | break; |
2209 | default: | |
32fcdbf4 | 2210 | vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); |
d5e455e4 AD |
2211 | break; |
2212 | } | |
32fcdbf4 AD |
2213 | vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); |
2214 | WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); | |
2215 | ||
2216 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
12920591 | 2217 | WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); |
32fcdbf4 AD |
2218 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
2219 | ||
60a4a3e0 AD |
2220 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); |
2221 | WREG32(VGT_OUT_DEALLOC_CNTL, 16); | |
2222 | ||
32fcdbf4 AD |
2223 | WREG32(CB_PERF_CTR0_SEL_0, 0); |
2224 | WREG32(CB_PERF_CTR0_SEL_1, 0); | |
2225 | WREG32(CB_PERF_CTR1_SEL_0, 0); | |
2226 | WREG32(CB_PERF_CTR1_SEL_1, 0); | |
2227 | WREG32(CB_PERF_CTR2_SEL_0, 0); | |
2228 | WREG32(CB_PERF_CTR2_SEL_1, 0); | |
2229 | WREG32(CB_PERF_CTR3_SEL_0, 0); | |
2230 | WREG32(CB_PERF_CTR3_SEL_1, 0); | |
2231 | ||
60a4a3e0 AD |
2232 | /* clear render buffer base addresses */ |
2233 | WREG32(CB_COLOR0_BASE, 0); | |
2234 | WREG32(CB_COLOR1_BASE, 0); | |
2235 | WREG32(CB_COLOR2_BASE, 0); | |
2236 | WREG32(CB_COLOR3_BASE, 0); | |
2237 | WREG32(CB_COLOR4_BASE, 0); | |
2238 | WREG32(CB_COLOR5_BASE, 0); | |
2239 | WREG32(CB_COLOR6_BASE, 0); | |
2240 | WREG32(CB_COLOR7_BASE, 0); | |
2241 | WREG32(CB_COLOR8_BASE, 0); | |
2242 | WREG32(CB_COLOR9_BASE, 0); | |
2243 | WREG32(CB_COLOR10_BASE, 0); | |
2244 | WREG32(CB_COLOR11_BASE, 0); | |
2245 | ||
2246 | /* set the shader const cache sizes to 0 */ | |
2247 | for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) | |
2248 | WREG32(i, 0); | |
2249 | for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) | |
2250 | WREG32(i, 0); | |
2251 | ||
f25a5c63 AD |
2252 | tmp = RREG32(HDP_MISC_CNTL); |
2253 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; | |
2254 | WREG32(HDP_MISC_CNTL, tmp); | |
2255 | ||
32fcdbf4 AD |
2256 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
2257 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
2258 | ||
2259 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); | |
2260 | ||
2261 | udelay(50); | |
2262 | ||
bcc1c2a1 AD |
2263 | } |
2264 | ||
2265 | int evergreen_mc_init(struct radeon_device *rdev) | |
2266 | { | |
bcc1c2a1 AD |
2267 | u32 tmp; |
2268 | int chansize, numchan; | |
bcc1c2a1 AD |
2269 | |
2270 | /* Get VRAM informations */ | |
2271 | rdev->mc.vram_is_ddr = true; | |
05b3ef69 AD |
2272 | if ((rdev->family == CHIP_PALM) || |
2273 | (rdev->family == CHIP_SUMO) || | |
2274 | (rdev->family == CHIP_SUMO2)) | |
8208441b AD |
2275 | tmp = RREG32(FUS_MC_ARB_RAMCFG); |
2276 | else | |
2277 | tmp = RREG32(MC_ARB_RAMCFG); | |
bcc1c2a1 AD |
2278 | if (tmp & CHANSIZE_OVERRIDE) { |
2279 | chansize = 16; | |
2280 | } else if (tmp & CHANSIZE_MASK) { | |
2281 | chansize = 64; | |
2282 | } else { | |
2283 | chansize = 32; | |
2284 | } | |
2285 | tmp = RREG32(MC_SHARED_CHMAP); | |
2286 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
2287 | case 0: | |
2288 | default: | |
2289 | numchan = 1; | |
2290 | break; | |
2291 | case 1: | |
2292 | numchan = 2; | |
2293 | break; | |
2294 | case 2: | |
2295 | numchan = 4; | |
2296 | break; | |
2297 | case 3: | |
2298 | numchan = 8; | |
2299 | break; | |
2300 | } | |
2301 | rdev->mc.vram_width = numchan * chansize; | |
2302 | /* Could aper size report 0 ? */ | |
01d73a69 JC |
2303 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
2304 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
bcc1c2a1 | 2305 | /* Setup GPU memory space */ |
05b3ef69 AD |
2306 | if ((rdev->family == CHIP_PALM) || |
2307 | (rdev->family == CHIP_SUMO) || | |
2308 | (rdev->family == CHIP_SUMO2)) { | |
6eb18f8b AD |
2309 | /* size in bytes on fusion */ |
2310 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
2311 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
2312 | } else { | |
05b3ef69 | 2313 | /* size in MB on evergreen/cayman/tn */ |
6eb18f8b AD |
2314 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; |
2315 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
2316 | } | |
51e5fcd3 | 2317 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
0ef0c1f7 | 2318 | r700_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 AD |
2319 | radeon_update_bandwidth_info(rdev); |
2320 | ||
bcc1c2a1 AD |
2321 | return 0; |
2322 | } | |
d594e46a | 2323 | |
187e3593 | 2324 | void evergreen_print_gpu_status_regs(struct radeon_device *rdev) |
bcc1c2a1 | 2325 | { |
64c56e8c | 2326 | dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", |
747943ea | 2327 | RREG32(GRBM_STATUS)); |
64c56e8c | 2328 | dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", |
747943ea | 2329 | RREG32(GRBM_STATUS_SE0)); |
64c56e8c | 2330 | dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", |
747943ea | 2331 | RREG32(GRBM_STATUS_SE1)); |
64c56e8c | 2332 | dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", |
747943ea | 2333 | RREG32(SRBM_STATUS)); |
a65a4369 AD |
2334 | dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n", |
2335 | RREG32(SRBM_STATUS2)); | |
440a7cd8 JG |
2336 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
2337 | RREG32(CP_STALLED_STAT1)); | |
2338 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", | |
2339 | RREG32(CP_STALLED_STAT2)); | |
2340 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", | |
2341 | RREG32(CP_BUSY_STAT)); | |
2342 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", | |
2343 | RREG32(CP_STAT)); | |
eaaa6983 JG |
2344 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
2345 | RREG32(DMA_STATUS_REG)); | |
168757ea AD |
2346 | if (rdev->family >= CHIP_CAYMAN) { |
2347 | dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n", | |
2348 | RREG32(DMA_STATUS_REG + 0x800)); | |
2349 | } | |
0ecebb9e AD |
2350 | } |
2351 | ||
168757ea | 2352 | bool evergreen_is_display_hung(struct radeon_device *rdev) |
0ecebb9e | 2353 | { |
a65a4369 AD |
2354 | u32 crtc_hung = 0; |
2355 | u32 crtc_status[6]; | |
2356 | u32 i, j, tmp; | |
2357 | ||
2358 | for (i = 0; i < rdev->num_crtc; i++) { | |
2359 | if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) { | |
2360 | crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
2361 | crtc_hung |= (1 << i); | |
2362 | } | |
2363 | } | |
2364 | ||
2365 | for (j = 0; j < 10; j++) { | |
2366 | for (i = 0; i < rdev->num_crtc; i++) { | |
2367 | if (crtc_hung & (1 << i)) { | |
2368 | tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
2369 | if (tmp != crtc_status[i]) | |
2370 | crtc_hung &= ~(1 << i); | |
2371 | } | |
2372 | } | |
2373 | if (crtc_hung == 0) | |
2374 | return false; | |
2375 | udelay(100); | |
2376 | } | |
2377 | ||
2378 | return true; | |
2379 | } | |
2380 | ||
2381 | static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev) | |
2382 | { | |
2383 | u32 reset_mask = 0; | |
b7630473 | 2384 | u32 tmp; |
0ecebb9e | 2385 | |
a65a4369 AD |
2386 | /* GRBM_STATUS */ |
2387 | tmp = RREG32(GRBM_STATUS); | |
2388 | if (tmp & (PA_BUSY | SC_BUSY | | |
2389 | SH_BUSY | SX_BUSY | | |
2390 | TA_BUSY | VGT_BUSY | | |
2391 | DB_BUSY | CB_BUSY | | |
2392 | SPI_BUSY | VGT_BUSY_NO_DMA)) | |
2393 | reset_mask |= RADEON_RESET_GFX; | |
2394 | ||
2395 | if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | | |
2396 | CP_BUSY | CP_COHERENCY_BUSY)) | |
2397 | reset_mask |= RADEON_RESET_CP; | |
2398 | ||
2399 | if (tmp & GRBM_EE_BUSY) | |
2400 | reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; | |
19fc42ed | 2401 | |
a65a4369 AD |
2402 | /* DMA_STATUS_REG */ |
2403 | tmp = RREG32(DMA_STATUS_REG); | |
2404 | if (!(tmp & DMA_IDLE)) | |
2405 | reset_mask |= RADEON_RESET_DMA; | |
2406 | ||
2407 | /* SRBM_STATUS2 */ | |
2408 | tmp = RREG32(SRBM_STATUS2); | |
2409 | if (tmp & DMA_BUSY) | |
2410 | reset_mask |= RADEON_RESET_DMA; | |
2411 | ||
2412 | /* SRBM_STATUS */ | |
2413 | tmp = RREG32(SRBM_STATUS); | |
2414 | if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) | |
2415 | reset_mask |= RADEON_RESET_RLC; | |
2416 | ||
2417 | if (tmp & IH_BUSY) | |
2418 | reset_mask |= RADEON_RESET_IH; | |
2419 | ||
2420 | if (tmp & SEM_BUSY) | |
2421 | reset_mask |= RADEON_RESET_SEM; | |
2422 | ||
2423 | if (tmp & GRBM_RQ_PENDING) | |
2424 | reset_mask |= RADEON_RESET_GRBM; | |
2425 | ||
2426 | if (tmp & VMC_BUSY) | |
2427 | reset_mask |= RADEON_RESET_VMC; | |
2428 | ||
2429 | if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | | |
2430 | MCC_BUSY | MCD_BUSY)) | |
2431 | reset_mask |= RADEON_RESET_MC; | |
2432 | ||
2433 | if (evergreen_is_display_hung(rdev)) | |
2434 | reset_mask |= RADEON_RESET_DISPLAY; | |
2435 | ||
2436 | /* VM_L2_STATUS */ | |
2437 | tmp = RREG32(VM_L2_STATUS); | |
2438 | if (tmp & L2_BUSY) | |
2439 | reset_mask |= RADEON_RESET_VMC; | |
2440 | ||
d808fc88 AD |
2441 | /* Skip MC reset as it's mostly likely not hung, just busy */ |
2442 | if (reset_mask & RADEON_RESET_MC) { | |
2443 | DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); | |
2444 | reset_mask &= ~RADEON_RESET_MC; | |
2445 | } | |
2446 | ||
a65a4369 AD |
2447 | return reset_mask; |
2448 | } | |
2449 | ||
2450 | static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) | |
2451 | { | |
2452 | struct evergreen_mc_save save; | |
2453 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; | |
2454 | u32 tmp; | |
19fc42ed | 2455 | |
0ecebb9e | 2456 | if (reset_mask == 0) |
a65a4369 | 2457 | return; |
0ecebb9e AD |
2458 | |
2459 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); | |
2460 | ||
b7630473 AD |
2461 | evergreen_print_gpu_status_regs(rdev); |
2462 | ||
b7630473 AD |
2463 | /* Disable CP parsing/prefetching */ |
2464 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); | |
2465 | ||
2466 | if (reset_mask & RADEON_RESET_DMA) { | |
2467 | /* Disable DMA */ | |
2468 | tmp = RREG32(DMA_RB_CNTL); | |
2469 | tmp &= ~DMA_RB_ENABLE; | |
2470 | WREG32(DMA_RB_CNTL, tmp); | |
2471 | } | |
2472 | ||
b21b6e7a AD |
2473 | udelay(50); |
2474 | ||
2475 | evergreen_mc_stop(rdev, &save); | |
2476 | if (evergreen_mc_wait_for_idle(rdev)) { | |
2477 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
2478 | } | |
2479 | ||
b7630473 AD |
2480 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { |
2481 | grbm_soft_reset |= SOFT_RESET_DB | | |
2482 | SOFT_RESET_CB | | |
2483 | SOFT_RESET_PA | | |
2484 | SOFT_RESET_SC | | |
2485 | SOFT_RESET_SPI | | |
2486 | SOFT_RESET_SX | | |
2487 | SOFT_RESET_SH | | |
2488 | SOFT_RESET_TC | | |
2489 | SOFT_RESET_TA | | |
2490 | SOFT_RESET_VC | | |
2491 | SOFT_RESET_VGT; | |
2492 | } | |
2493 | ||
2494 | if (reset_mask & RADEON_RESET_CP) { | |
2495 | grbm_soft_reset |= SOFT_RESET_CP | | |
2496 | SOFT_RESET_VGT; | |
2497 | ||
2498 | srbm_soft_reset |= SOFT_RESET_GRBM; | |
2499 | } | |
0ecebb9e AD |
2500 | |
2501 | if (reset_mask & RADEON_RESET_DMA) | |
b7630473 AD |
2502 | srbm_soft_reset |= SOFT_RESET_DMA; |
2503 | ||
a65a4369 AD |
2504 | if (reset_mask & RADEON_RESET_DISPLAY) |
2505 | srbm_soft_reset |= SOFT_RESET_DC; | |
2506 | ||
2507 | if (reset_mask & RADEON_RESET_RLC) | |
2508 | srbm_soft_reset |= SOFT_RESET_RLC; | |
2509 | ||
2510 | if (reset_mask & RADEON_RESET_SEM) | |
2511 | srbm_soft_reset |= SOFT_RESET_SEM; | |
2512 | ||
2513 | if (reset_mask & RADEON_RESET_IH) | |
2514 | srbm_soft_reset |= SOFT_RESET_IH; | |
2515 | ||
2516 | if (reset_mask & RADEON_RESET_GRBM) | |
2517 | srbm_soft_reset |= SOFT_RESET_GRBM; | |
2518 | ||
2519 | if (reset_mask & RADEON_RESET_VMC) | |
2520 | srbm_soft_reset |= SOFT_RESET_VMC; | |
2521 | ||
24178ec4 AD |
2522 | if (!(rdev->flags & RADEON_IS_IGP)) { |
2523 | if (reset_mask & RADEON_RESET_MC) | |
2524 | srbm_soft_reset |= SOFT_RESET_MC; | |
2525 | } | |
a65a4369 | 2526 | |
b7630473 AD |
2527 | if (grbm_soft_reset) { |
2528 | tmp = RREG32(GRBM_SOFT_RESET); | |
2529 | tmp |= grbm_soft_reset; | |
2530 | dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); | |
2531 | WREG32(GRBM_SOFT_RESET, tmp); | |
2532 | tmp = RREG32(GRBM_SOFT_RESET); | |
2533 | ||
2534 | udelay(50); | |
2535 | ||
2536 | tmp &= ~grbm_soft_reset; | |
2537 | WREG32(GRBM_SOFT_RESET, tmp); | |
2538 | tmp = RREG32(GRBM_SOFT_RESET); | |
2539 | } | |
2540 | ||
2541 | if (srbm_soft_reset) { | |
2542 | tmp = RREG32(SRBM_SOFT_RESET); | |
2543 | tmp |= srbm_soft_reset; | |
2544 | dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
2545 | WREG32(SRBM_SOFT_RESET, tmp); | |
2546 | tmp = RREG32(SRBM_SOFT_RESET); | |
2547 | ||
2548 | udelay(50); | |
2549 | ||
2550 | tmp &= ~srbm_soft_reset; | |
2551 | WREG32(SRBM_SOFT_RESET, tmp); | |
2552 | tmp = RREG32(SRBM_SOFT_RESET); | |
2553 | } | |
0ecebb9e AD |
2554 | |
2555 | /* Wait a little for things to settle down */ | |
2556 | udelay(50); | |
2557 | ||
747943ea | 2558 | evergreen_mc_resume(rdev, &save); |
b7630473 AD |
2559 | udelay(50); |
2560 | ||
b7630473 | 2561 | evergreen_print_gpu_status_regs(rdev); |
bcc1c2a1 AD |
2562 | } |
2563 | ||
a2d07b74 | 2564 | int evergreen_asic_reset(struct radeon_device *rdev) |
bcc1c2a1 | 2565 | { |
a65a4369 AD |
2566 | u32 reset_mask; |
2567 | ||
2568 | reset_mask = evergreen_gpu_check_soft_reset(rdev); | |
2569 | ||
2570 | if (reset_mask) | |
2571 | r600_set_bios_scratch_engine_hung(rdev, true); | |
2572 | ||
2573 | evergreen_gpu_soft_reset(rdev, reset_mask); | |
2574 | ||
2575 | reset_mask = evergreen_gpu_check_soft_reset(rdev); | |
2576 | ||
2577 | if (!reset_mask) | |
2578 | r600_set_bios_scratch_engine_hung(rdev, false); | |
2579 | ||
2580 | return 0; | |
747943ea AD |
2581 | } |
2582 | ||
123bc183 AD |
2583 | /** |
2584 | * evergreen_gfx_is_lockup - Check if the GFX engine is locked up | |
2585 | * | |
2586 | * @rdev: radeon_device pointer | |
2587 | * @ring: radeon_ring structure holding ring information | |
2588 | * | |
2589 | * Check if the GFX engine is locked up. | |
2590 | * Returns true if the engine appears to be locked up, false if not. | |
2591 | */ | |
2592 | bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
2593 | { | |
2594 | u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); | |
2595 | ||
2596 | if (!(reset_mask & (RADEON_RESET_GFX | | |
2597 | RADEON_RESET_COMPUTE | | |
2598 | RADEON_RESET_CP))) { | |
2599 | radeon_ring_lockup_update(ring); | |
2600 | return false; | |
2601 | } | |
2602 | /* force CP activities */ | |
2603 | radeon_ring_force_activity(rdev, ring); | |
2604 | return radeon_ring_test_lockup(rdev, ring); | |
2605 | } | |
2606 | ||
2607 | /** | |
2608 | * evergreen_dma_is_lockup - Check if the DMA engine is locked up | |
2609 | * | |
2610 | * @rdev: radeon_device pointer | |
2611 | * @ring: radeon_ring structure holding ring information | |
2612 | * | |
2613 | * Check if the async DMA engine is locked up. | |
2614 | * Returns true if the engine appears to be locked up, false if not. | |
2615 | */ | |
2616 | bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
2617 | { | |
2618 | u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); | |
2619 | ||
2620 | if (!(reset_mask & RADEON_RESET_DMA)) { | |
2621 | radeon_ring_lockup_update(ring); | |
2622 | return false; | |
2623 | } | |
2624 | /* force ring activities */ | |
2625 | radeon_ring_force_activity(rdev, ring); | |
2626 | return radeon_ring_test_lockup(rdev, ring); | |
2627 | } | |
2628 | ||
45f9a39b AD |
2629 | /* Interrupts */ |
2630 | ||
2631 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
2632 | { | |
46437057 | 2633 | if (crtc >= rdev->num_crtc) |
45f9a39b | 2634 | return 0; |
46437057 AD |
2635 | else |
2636 | return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); | |
45f9a39b AD |
2637 | } |
2638 | ||
2639 | void evergreen_disable_interrupt_state(struct radeon_device *rdev) | |
2640 | { | |
2641 | u32 tmp; | |
2642 | ||
1b37078b AD |
2643 | if (rdev->family >= CHIP_CAYMAN) { |
2644 | cayman_cp_int_cntl_setup(rdev, 0, | |
2645 | CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); | |
2646 | cayman_cp_int_cntl_setup(rdev, 1, 0); | |
2647 | cayman_cp_int_cntl_setup(rdev, 2, 0); | |
f60cbd11 AD |
2648 | tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; |
2649 | WREG32(CAYMAN_DMA1_CNTL, tmp); | |
1b37078b AD |
2650 | } else |
2651 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); | |
233d1ad5 AD |
2652 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
2653 | WREG32(DMA_CNTL, tmp); | |
45f9a39b AD |
2654 | WREG32(GRBM_INT_CNTL, 0); |
2655 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
2656 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 2657 | if (rdev->num_crtc >= 4) { |
18007401 AD |
2658 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
2659 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
2660 | } |
2661 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
2662 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
2663 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
2664 | } | |
45f9a39b AD |
2665 | |
2666 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
2667 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
b7eff394 | 2668 | if (rdev->num_crtc >= 4) { |
18007401 AD |
2669 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
2670 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
b7eff394 AD |
2671 | } |
2672 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
2673 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
2674 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
2675 | } | |
45f9a39b | 2676 | |
05b3ef69 AD |
2677 | /* only one DAC on DCE6 */ |
2678 | if (!ASIC_IS_DCE6(rdev)) | |
2679 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
45f9a39b AD |
2680 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); |
2681 | ||
2682 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2683 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2684 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2685 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2686 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2687 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2688 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2689 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2690 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2691 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2692 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2693 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
2694 | ||
2695 | } | |
2696 | ||
2697 | int evergreen_irq_set(struct radeon_device *rdev) | |
2698 | { | |
2699 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; | |
1b37078b | 2700 | u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; |
45f9a39b AD |
2701 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
2702 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | |
2031f77c | 2703 | u32 grbm_int_cntl = 0; |
6f34be50 | 2704 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
f122c610 | 2705 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; |
f60cbd11 | 2706 | u32 dma_cntl, dma_cntl1 = 0; |
45f9a39b AD |
2707 | |
2708 | if (!rdev->irq.installed) { | |
fce7d61b | 2709 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
45f9a39b AD |
2710 | return -EINVAL; |
2711 | } | |
2712 | /* don't enable anything if the ih is disabled */ | |
2713 | if (!rdev->ih.enabled) { | |
2714 | r600_disable_interrupts(rdev); | |
2715 | /* force the active interrupt state to all disabled */ | |
2716 | evergreen_disable_interrupt_state(rdev); | |
2717 | return 0; | |
2718 | } | |
2719 | ||
2720 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2721 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2722 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2723 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2724 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2725 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2726 | ||
f122c610 AD |
2727 | afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
2728 | afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
2729 | afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
2730 | afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
2731 | afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
2732 | afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
2733 | ||
233d1ad5 AD |
2734 | dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
2735 | ||
1b37078b AD |
2736 | if (rdev->family >= CHIP_CAYMAN) { |
2737 | /* enable CP interrupts on all rings */ | |
736fc37f | 2738 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
1b37078b AD |
2739 | DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); |
2740 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; | |
2741 | } | |
736fc37f | 2742 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { |
1b37078b AD |
2743 | DRM_DEBUG("evergreen_irq_set: sw int cp1\n"); |
2744 | cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; | |
2745 | } | |
736fc37f | 2746 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { |
1b37078b AD |
2747 | DRM_DEBUG("evergreen_irq_set: sw int cp2\n"); |
2748 | cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; | |
2749 | } | |
2750 | } else { | |
736fc37f | 2751 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
1b37078b AD |
2752 | DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); |
2753 | cp_int_cntl |= RB_INT_ENABLE; | |
2754 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; | |
2755 | } | |
45f9a39b | 2756 | } |
1b37078b | 2757 | |
233d1ad5 AD |
2758 | if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { |
2759 | DRM_DEBUG("r600_irq_set: sw int dma\n"); | |
2760 | dma_cntl |= TRAP_ENABLE; | |
2761 | } | |
2762 | ||
f60cbd11 AD |
2763 | if (rdev->family >= CHIP_CAYMAN) { |
2764 | dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; | |
2765 | if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { | |
2766 | DRM_DEBUG("r600_irq_set: sw int dma1\n"); | |
2767 | dma_cntl1 |= TRAP_ENABLE; | |
2768 | } | |
2769 | } | |
2770 | ||
6f34be50 | 2771 | if (rdev->irq.crtc_vblank_int[0] || |
736fc37f | 2772 | atomic_read(&rdev->irq.pflip[0])) { |
45f9a39b AD |
2773 | DRM_DEBUG("evergreen_irq_set: vblank 0\n"); |
2774 | crtc1 |= VBLANK_INT_MASK; | |
2775 | } | |
6f34be50 | 2776 | if (rdev->irq.crtc_vblank_int[1] || |
736fc37f | 2777 | atomic_read(&rdev->irq.pflip[1])) { |
45f9a39b AD |
2778 | DRM_DEBUG("evergreen_irq_set: vblank 1\n"); |
2779 | crtc2 |= VBLANK_INT_MASK; | |
2780 | } | |
6f34be50 | 2781 | if (rdev->irq.crtc_vblank_int[2] || |
736fc37f | 2782 | atomic_read(&rdev->irq.pflip[2])) { |
45f9a39b AD |
2783 | DRM_DEBUG("evergreen_irq_set: vblank 2\n"); |
2784 | crtc3 |= VBLANK_INT_MASK; | |
2785 | } | |
6f34be50 | 2786 | if (rdev->irq.crtc_vblank_int[3] || |
736fc37f | 2787 | atomic_read(&rdev->irq.pflip[3])) { |
45f9a39b AD |
2788 | DRM_DEBUG("evergreen_irq_set: vblank 3\n"); |
2789 | crtc4 |= VBLANK_INT_MASK; | |
2790 | } | |
6f34be50 | 2791 | if (rdev->irq.crtc_vblank_int[4] || |
736fc37f | 2792 | atomic_read(&rdev->irq.pflip[4])) { |
45f9a39b AD |
2793 | DRM_DEBUG("evergreen_irq_set: vblank 4\n"); |
2794 | crtc5 |= VBLANK_INT_MASK; | |
2795 | } | |
6f34be50 | 2796 | if (rdev->irq.crtc_vblank_int[5] || |
736fc37f | 2797 | atomic_read(&rdev->irq.pflip[5])) { |
45f9a39b AD |
2798 | DRM_DEBUG("evergreen_irq_set: vblank 5\n"); |
2799 | crtc6 |= VBLANK_INT_MASK; | |
2800 | } | |
2801 | if (rdev->irq.hpd[0]) { | |
2802 | DRM_DEBUG("evergreen_irq_set: hpd 1\n"); | |
2803 | hpd1 |= DC_HPDx_INT_EN; | |
2804 | } | |
2805 | if (rdev->irq.hpd[1]) { | |
2806 | DRM_DEBUG("evergreen_irq_set: hpd 2\n"); | |
2807 | hpd2 |= DC_HPDx_INT_EN; | |
2808 | } | |
2809 | if (rdev->irq.hpd[2]) { | |
2810 | DRM_DEBUG("evergreen_irq_set: hpd 3\n"); | |
2811 | hpd3 |= DC_HPDx_INT_EN; | |
2812 | } | |
2813 | if (rdev->irq.hpd[3]) { | |
2814 | DRM_DEBUG("evergreen_irq_set: hpd 4\n"); | |
2815 | hpd4 |= DC_HPDx_INT_EN; | |
2816 | } | |
2817 | if (rdev->irq.hpd[4]) { | |
2818 | DRM_DEBUG("evergreen_irq_set: hpd 5\n"); | |
2819 | hpd5 |= DC_HPDx_INT_EN; | |
2820 | } | |
2821 | if (rdev->irq.hpd[5]) { | |
2822 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); | |
2823 | hpd6 |= DC_HPDx_INT_EN; | |
2824 | } | |
f122c610 AD |
2825 | if (rdev->irq.afmt[0]) { |
2826 | DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); | |
2827 | afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; | |
2828 | } | |
2829 | if (rdev->irq.afmt[1]) { | |
2830 | DRM_DEBUG("evergreen_irq_set: hdmi 1\n"); | |
2831 | afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK; | |
2832 | } | |
2833 | if (rdev->irq.afmt[2]) { | |
2834 | DRM_DEBUG("evergreen_irq_set: hdmi 2\n"); | |
2835 | afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK; | |
2836 | } | |
2837 | if (rdev->irq.afmt[3]) { | |
2838 | DRM_DEBUG("evergreen_irq_set: hdmi 3\n"); | |
2839 | afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK; | |
2840 | } | |
2841 | if (rdev->irq.afmt[4]) { | |
2842 | DRM_DEBUG("evergreen_irq_set: hdmi 4\n"); | |
2843 | afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK; | |
2844 | } | |
2845 | if (rdev->irq.afmt[5]) { | |
2846 | DRM_DEBUG("evergreen_irq_set: hdmi 5\n"); | |
2847 | afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK; | |
2848 | } | |
45f9a39b | 2849 | |
1b37078b AD |
2850 | if (rdev->family >= CHIP_CAYMAN) { |
2851 | cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); | |
2852 | cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); | |
2853 | cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); | |
2854 | } else | |
2855 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
233d1ad5 AD |
2856 | |
2857 | WREG32(DMA_CNTL, dma_cntl); | |
2858 | ||
f60cbd11 AD |
2859 | if (rdev->family >= CHIP_CAYMAN) |
2860 | WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); | |
2861 | ||
2031f77c | 2862 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
45f9a39b AD |
2863 | |
2864 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); | |
2865 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); | |
b7eff394 | 2866 | if (rdev->num_crtc >= 4) { |
18007401 AD |
2867 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); |
2868 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); | |
b7eff394 AD |
2869 | } |
2870 | if (rdev->num_crtc >= 6) { | |
18007401 AD |
2871 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); |
2872 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | |
2873 | } | |
45f9a39b | 2874 | |
6f34be50 AD |
2875 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); |
2876 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | |
b7eff394 AD |
2877 | if (rdev->num_crtc >= 4) { |
2878 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | |
2879 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | |
2880 | } | |
2881 | if (rdev->num_crtc >= 6) { | |
2882 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | |
2883 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | |
2884 | } | |
6f34be50 | 2885 | |
45f9a39b AD |
2886 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
2887 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
2888 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
2889 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
2890 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
2891 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
2892 | ||
f122c610 AD |
2893 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); |
2894 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); | |
2895 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); | |
2896 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); | |
2897 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); | |
2898 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); | |
2899 | ||
bcc1c2a1 AD |
2900 | return 0; |
2901 | } | |
2902 | ||
cbdd4501 | 2903 | static void evergreen_irq_ack(struct radeon_device *rdev) |
45f9a39b AD |
2904 | { |
2905 | u32 tmp; | |
2906 | ||
6f34be50 AD |
2907 | rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
2908 | rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
2909 | rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); | |
2910 | rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); | |
2911 | rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); | |
2912 | rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); | |
2913 | rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
2914 | rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
b7eff394 AD |
2915 | if (rdev->num_crtc >= 4) { |
2916 | rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
2917 | rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
2918 | } | |
2919 | if (rdev->num_crtc >= 6) { | |
2920 | rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
2921 | rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
2922 | } | |
6f34be50 | 2923 | |
f122c610 AD |
2924 | rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); |
2925 | rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
2926 | rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
2927 | rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
2928 | rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
2929 | rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
2930 | ||
6f34be50 AD |
2931 | if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) |
2932 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2933 | if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2934 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
6f34be50 | 2935 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) |
45f9a39b | 2936 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); |
6f34be50 | 2937 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) |
45f9a39b | 2938 | WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); |
6f34be50 | 2939 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) |
45f9a39b | 2940 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); |
6f34be50 | 2941 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) |
45f9a39b AD |
2942 | WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); |
2943 | ||
b7eff394 AD |
2944 | if (rdev->num_crtc >= 4) { |
2945 | if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2946 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2947 | if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2948 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2949 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) | |
2950 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); | |
2951 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) | |
2952 | WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); | |
2953 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) | |
2954 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); | |
2955 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) | |
2956 | WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); | |
2957 | } | |
2958 | ||
2959 | if (rdev->num_crtc >= 6) { | |
2960 | if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2961 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2962 | if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) | |
2963 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
2964 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) | |
2965 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); | |
2966 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) | |
2967 | WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); | |
2968 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) | |
2969 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); | |
2970 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) | |
2971 | WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); | |
2972 | } | |
45f9a39b | 2973 | |
6f34be50 | 2974 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
45f9a39b AD |
2975 | tmp = RREG32(DC_HPD1_INT_CONTROL); |
2976 | tmp |= DC_HPDx_INT_ACK; | |
2977 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2978 | } | |
6f34be50 | 2979 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
45f9a39b AD |
2980 | tmp = RREG32(DC_HPD2_INT_CONTROL); |
2981 | tmp |= DC_HPDx_INT_ACK; | |
2982 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2983 | } | |
6f34be50 | 2984 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
45f9a39b AD |
2985 | tmp = RREG32(DC_HPD3_INT_CONTROL); |
2986 | tmp |= DC_HPDx_INT_ACK; | |
2987 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2988 | } | |
6f34be50 | 2989 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
45f9a39b AD |
2990 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
2991 | tmp |= DC_HPDx_INT_ACK; | |
2992 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2993 | } | |
6f34be50 | 2994 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
45f9a39b AD |
2995 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
2996 | tmp |= DC_HPDx_INT_ACK; | |
2997 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2998 | } | |
6f34be50 | 2999 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
45f9a39b AD |
3000 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
3001 | tmp |= DC_HPDx_INT_ACK; | |
3002 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
3003 | } | |
f122c610 AD |
3004 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { |
3005 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
3006 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | |
3007 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); | |
3008 | } | |
3009 | if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { | |
3010 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
3011 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | |
3012 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); | |
3013 | } | |
3014 | if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { | |
3015 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
3016 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | |
3017 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); | |
3018 | } | |
3019 | if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { | |
3020 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
3021 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | |
3022 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); | |
3023 | } | |
3024 | if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { | |
3025 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
3026 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | |
3027 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); | |
3028 | } | |
3029 | if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { | |
3030 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
3031 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | |
3032 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); | |
3033 | } | |
45f9a39b AD |
3034 | } |
3035 | ||
1109ca09 | 3036 | static void evergreen_irq_disable(struct radeon_device *rdev) |
45f9a39b | 3037 | { |
45f9a39b AD |
3038 | r600_disable_interrupts(rdev); |
3039 | /* Wait and acknowledge irq */ | |
3040 | mdelay(1); | |
6f34be50 | 3041 | evergreen_irq_ack(rdev); |
45f9a39b AD |
3042 | evergreen_disable_interrupt_state(rdev); |
3043 | } | |
3044 | ||
755d819e | 3045 | void evergreen_irq_suspend(struct radeon_device *rdev) |
45f9a39b AD |
3046 | { |
3047 | evergreen_irq_disable(rdev); | |
3048 | r600_rlc_stop(rdev); | |
3049 | } | |
3050 | ||
cbdd4501 | 3051 | static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) |
45f9a39b AD |
3052 | { |
3053 | u32 wptr, tmp; | |
3054 | ||
724c80e1 | 3055 | if (rdev->wb.enabled) |
204ae24d | 3056 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
724c80e1 AD |
3057 | else |
3058 | wptr = RREG32(IH_RB_WPTR); | |
45f9a39b AD |
3059 | |
3060 | if (wptr & RB_OVERFLOW) { | |
3061 | /* When a ring buffer overflow happen start parsing interrupt | |
3062 | * from the last not overwritten vector (wptr + 16). Hopefully | |
3063 | * this should allow us to catchup. | |
3064 | */ | |
3065 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
3066 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
3067 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
3068 | tmp = RREG32(IH_RB_CNTL); | |
3069 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
3070 | WREG32(IH_RB_CNTL, tmp); | |
3071 | } | |
3072 | return (wptr & rdev->ih.ptr_mask); | |
3073 | } | |
3074 | ||
3075 | int evergreen_irq_process(struct radeon_device *rdev) | |
3076 | { | |
682f1a54 DA |
3077 | u32 wptr; |
3078 | u32 rptr; | |
45f9a39b AD |
3079 | u32 src_id, src_data; |
3080 | u32 ring_index; | |
45f9a39b | 3081 | bool queue_hotplug = false; |
f122c610 | 3082 | bool queue_hdmi = false; |
45f9a39b | 3083 | |
682f1a54 | 3084 | if (!rdev->ih.enabled || rdev->shutdown) |
45f9a39b AD |
3085 | return IRQ_NONE; |
3086 | ||
682f1a54 | 3087 | wptr = evergreen_get_ih_wptr(rdev); |
c20dc369 CK |
3088 | |
3089 | restart_ih: | |
3090 | /* is somebody else already processing irqs? */ | |
3091 | if (atomic_xchg(&rdev->ih.lock, 1)) | |
3092 | return IRQ_NONE; | |
3093 | ||
682f1a54 DA |
3094 | rptr = rdev->ih.rptr; |
3095 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
45f9a39b | 3096 | |
964f6645 BH |
3097 | /* Order reading of wptr vs. reading of IH ring data */ |
3098 | rmb(); | |
3099 | ||
45f9a39b | 3100 | /* display interrupts */ |
6f34be50 | 3101 | evergreen_irq_ack(rdev); |
45f9a39b | 3102 | |
45f9a39b AD |
3103 | while (rptr != wptr) { |
3104 | /* wptr/rptr are in bytes! */ | |
3105 | ring_index = rptr / 4; | |
0f234f5f AD |
3106 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
3107 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; | |
45f9a39b AD |
3108 | |
3109 | switch (src_id) { | |
3110 | case 1: /* D1 vblank/vline */ | |
3111 | switch (src_data) { | |
3112 | case 0: /* D1 vblank */ | |
6f34be50 | 3113 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { |
6f34be50 AD |
3114 | if (rdev->irq.crtc_vblank_int[0]) { |
3115 | drm_handle_vblank(rdev->ddev, 0); | |
3116 | rdev->pm.vblank_sync = true; | |
3117 | wake_up(&rdev->irq.vblank_queue); | |
3118 | } | |
736fc37f | 3119 | if (atomic_read(&rdev->irq.pflip[0])) |
3e4ea742 | 3120 | radeon_crtc_handle_flip(rdev, 0); |
6f34be50 | 3121 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
45f9a39b AD |
3122 | DRM_DEBUG("IH: D1 vblank\n"); |
3123 | } | |
3124 | break; | |
3125 | case 1: /* D1 vline */ | |
6f34be50 AD |
3126 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { |
3127 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
45f9a39b AD |
3128 | DRM_DEBUG("IH: D1 vline\n"); |
3129 | } | |
3130 | break; | |
3131 | default: | |
3132 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3133 | break; | |
3134 | } | |
3135 | break; | |
3136 | case 2: /* D2 vblank/vline */ | |
3137 | switch (src_data) { | |
3138 | case 0: /* D2 vblank */ | |
6f34be50 | 3139 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { |
6f34be50 AD |
3140 | if (rdev->irq.crtc_vblank_int[1]) { |
3141 | drm_handle_vblank(rdev->ddev, 1); | |
3142 | rdev->pm.vblank_sync = true; | |
3143 | wake_up(&rdev->irq.vblank_queue); | |
3144 | } | |
736fc37f | 3145 | if (atomic_read(&rdev->irq.pflip[1])) |
3e4ea742 | 3146 | radeon_crtc_handle_flip(rdev, 1); |
6f34be50 | 3147 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
45f9a39b AD |
3148 | DRM_DEBUG("IH: D2 vblank\n"); |
3149 | } | |
3150 | break; | |
3151 | case 1: /* D2 vline */ | |
6f34be50 AD |
3152 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { |
3153 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; | |
45f9a39b AD |
3154 | DRM_DEBUG("IH: D2 vline\n"); |
3155 | } | |
3156 | break; | |
3157 | default: | |
3158 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3159 | break; | |
3160 | } | |
3161 | break; | |
3162 | case 3: /* D3 vblank/vline */ | |
3163 | switch (src_data) { | |
3164 | case 0: /* D3 vblank */ | |
6f34be50 AD |
3165 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { |
3166 | if (rdev->irq.crtc_vblank_int[2]) { | |
3167 | drm_handle_vblank(rdev->ddev, 2); | |
3168 | rdev->pm.vblank_sync = true; | |
3169 | wake_up(&rdev->irq.vblank_queue); | |
3170 | } | |
736fc37f | 3171 | if (atomic_read(&rdev->irq.pflip[2])) |
6f34be50 AD |
3172 | radeon_crtc_handle_flip(rdev, 2); |
3173 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; | |
45f9a39b AD |
3174 | DRM_DEBUG("IH: D3 vblank\n"); |
3175 | } | |
3176 | break; | |
3177 | case 1: /* D3 vline */ | |
6f34be50 AD |
3178 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { |
3179 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; | |
45f9a39b AD |
3180 | DRM_DEBUG("IH: D3 vline\n"); |
3181 | } | |
3182 | break; | |
3183 | default: | |
3184 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3185 | break; | |
3186 | } | |
3187 | break; | |
3188 | case 4: /* D4 vblank/vline */ | |
3189 | switch (src_data) { | |
3190 | case 0: /* D4 vblank */ | |
6f34be50 AD |
3191 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { |
3192 | if (rdev->irq.crtc_vblank_int[3]) { | |
3193 | drm_handle_vblank(rdev->ddev, 3); | |
3194 | rdev->pm.vblank_sync = true; | |
3195 | wake_up(&rdev->irq.vblank_queue); | |
3196 | } | |
736fc37f | 3197 | if (atomic_read(&rdev->irq.pflip[3])) |
6f34be50 AD |
3198 | radeon_crtc_handle_flip(rdev, 3); |
3199 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; | |
45f9a39b AD |
3200 | DRM_DEBUG("IH: D4 vblank\n"); |
3201 | } | |
3202 | break; | |
3203 | case 1: /* D4 vline */ | |
6f34be50 AD |
3204 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { |
3205 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; | |
45f9a39b AD |
3206 | DRM_DEBUG("IH: D4 vline\n"); |
3207 | } | |
3208 | break; | |
3209 | default: | |
3210 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3211 | break; | |
3212 | } | |
3213 | break; | |
3214 | case 5: /* D5 vblank/vline */ | |
3215 | switch (src_data) { | |
3216 | case 0: /* D5 vblank */ | |
6f34be50 AD |
3217 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { |
3218 | if (rdev->irq.crtc_vblank_int[4]) { | |
3219 | drm_handle_vblank(rdev->ddev, 4); | |
3220 | rdev->pm.vblank_sync = true; | |
3221 | wake_up(&rdev->irq.vblank_queue); | |
3222 | } | |
736fc37f | 3223 | if (atomic_read(&rdev->irq.pflip[4])) |
6f34be50 AD |
3224 | radeon_crtc_handle_flip(rdev, 4); |
3225 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; | |
45f9a39b AD |
3226 | DRM_DEBUG("IH: D5 vblank\n"); |
3227 | } | |
3228 | break; | |
3229 | case 1: /* D5 vline */ | |
6f34be50 AD |
3230 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { |
3231 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; | |
45f9a39b AD |
3232 | DRM_DEBUG("IH: D5 vline\n"); |
3233 | } | |
3234 | break; | |
3235 | default: | |
3236 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3237 | break; | |
3238 | } | |
3239 | break; | |
3240 | case 6: /* D6 vblank/vline */ | |
3241 | switch (src_data) { | |
3242 | case 0: /* D6 vblank */ | |
6f34be50 AD |
3243 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { |
3244 | if (rdev->irq.crtc_vblank_int[5]) { | |
3245 | drm_handle_vblank(rdev->ddev, 5); | |
3246 | rdev->pm.vblank_sync = true; | |
3247 | wake_up(&rdev->irq.vblank_queue); | |
3248 | } | |
736fc37f | 3249 | if (atomic_read(&rdev->irq.pflip[5])) |
6f34be50 AD |
3250 | radeon_crtc_handle_flip(rdev, 5); |
3251 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; | |
45f9a39b AD |
3252 | DRM_DEBUG("IH: D6 vblank\n"); |
3253 | } | |
3254 | break; | |
3255 | case 1: /* D6 vline */ | |
6f34be50 AD |
3256 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { |
3257 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; | |
45f9a39b AD |
3258 | DRM_DEBUG("IH: D6 vline\n"); |
3259 | } | |
3260 | break; | |
3261 | default: | |
3262 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3263 | break; | |
3264 | } | |
3265 | break; | |
3266 | case 42: /* HPD hotplug */ | |
3267 | switch (src_data) { | |
3268 | case 0: | |
6f34be50 AD |
3269 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
3270 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; | |
45f9a39b AD |
3271 | queue_hotplug = true; |
3272 | DRM_DEBUG("IH: HPD1\n"); | |
3273 | } | |
3274 | break; | |
3275 | case 1: | |
6f34be50 AD |
3276 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
3277 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; | |
45f9a39b AD |
3278 | queue_hotplug = true; |
3279 | DRM_DEBUG("IH: HPD2\n"); | |
3280 | } | |
3281 | break; | |
3282 | case 2: | |
6f34be50 AD |
3283 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
3284 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; | |
45f9a39b AD |
3285 | queue_hotplug = true; |
3286 | DRM_DEBUG("IH: HPD3\n"); | |
3287 | } | |
3288 | break; | |
3289 | case 3: | |
6f34be50 AD |
3290 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
3291 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; | |
45f9a39b AD |
3292 | queue_hotplug = true; |
3293 | DRM_DEBUG("IH: HPD4\n"); | |
3294 | } | |
3295 | break; | |
3296 | case 4: | |
6f34be50 AD |
3297 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
3298 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; | |
45f9a39b AD |
3299 | queue_hotplug = true; |
3300 | DRM_DEBUG("IH: HPD5\n"); | |
3301 | } | |
3302 | break; | |
3303 | case 5: | |
6f34be50 AD |
3304 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
3305 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; | |
45f9a39b AD |
3306 | queue_hotplug = true; |
3307 | DRM_DEBUG("IH: HPD6\n"); | |
3308 | } | |
3309 | break; | |
3310 | default: | |
3311 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3312 | break; | |
3313 | } | |
3314 | break; | |
f122c610 AD |
3315 | case 44: /* hdmi */ |
3316 | switch (src_data) { | |
3317 | case 0: | |
3318 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { | |
3319 | rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; | |
3320 | queue_hdmi = true; | |
3321 | DRM_DEBUG("IH: HDMI0\n"); | |
3322 | } | |
3323 | break; | |
3324 | case 1: | |
3325 | if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { | |
3326 | rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; | |
3327 | queue_hdmi = true; | |
3328 | DRM_DEBUG("IH: HDMI1\n"); | |
3329 | } | |
3330 | break; | |
3331 | case 2: | |
3332 | if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { | |
3333 | rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; | |
3334 | queue_hdmi = true; | |
3335 | DRM_DEBUG("IH: HDMI2\n"); | |
3336 | } | |
3337 | break; | |
3338 | case 3: | |
3339 | if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { | |
3340 | rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; | |
3341 | queue_hdmi = true; | |
3342 | DRM_DEBUG("IH: HDMI3\n"); | |
3343 | } | |
3344 | break; | |
3345 | case 4: | |
3346 | if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { | |
3347 | rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; | |
3348 | queue_hdmi = true; | |
3349 | DRM_DEBUG("IH: HDMI4\n"); | |
3350 | } | |
3351 | break; | |
3352 | case 5: | |
3353 | if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { | |
3354 | rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; | |
3355 | queue_hdmi = true; | |
3356 | DRM_DEBUG("IH: HDMI5\n"); | |
3357 | } | |
3358 | break; | |
3359 | default: | |
3360 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3361 | break; | |
3362 | } | |
3363 | break; | |
ae133a11 CK |
3364 | case 146: |
3365 | case 147: | |
3366 | dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); | |
3367 | dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", | |
3368 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); | |
3369 | dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", | |
3370 | RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); | |
3371 | /* reset addr and status */ | |
3372 | WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); | |
3373 | break; | |
45f9a39b AD |
3374 | case 176: /* CP_INT in ring buffer */ |
3375 | case 177: /* CP_INT in IB1 */ | |
3376 | case 178: /* CP_INT in IB2 */ | |
3377 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
7465280c | 3378 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
45f9a39b AD |
3379 | break; |
3380 | case 181: /* CP EOP event */ | |
3381 | DRM_DEBUG("IH: CP EOP\n"); | |
1b37078b AD |
3382 | if (rdev->family >= CHIP_CAYMAN) { |
3383 | switch (src_data) { | |
3384 | case 0: | |
3385 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); | |
3386 | break; | |
3387 | case 1: | |
3388 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); | |
3389 | break; | |
3390 | case 2: | |
3391 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); | |
3392 | break; | |
3393 | } | |
3394 | } else | |
3395 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); | |
45f9a39b | 3396 | break; |
233d1ad5 AD |
3397 | case 224: /* DMA trap event */ |
3398 | DRM_DEBUG("IH: DMA trap\n"); | |
3399 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); | |
3400 | break; | |
2031f77c | 3401 | case 233: /* GUI IDLE */ |
303c805c | 3402 | DRM_DEBUG("IH: GUI idle\n"); |
2031f77c | 3403 | break; |
f60cbd11 AD |
3404 | case 244: /* DMA trap event */ |
3405 | if (rdev->family >= CHIP_CAYMAN) { | |
3406 | DRM_DEBUG("IH: DMA1 trap\n"); | |
3407 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); | |
3408 | } | |
3409 | break; | |
45f9a39b AD |
3410 | default: |
3411 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3412 | break; | |
3413 | } | |
3414 | ||
3415 | /* wptr/rptr are in bytes! */ | |
3416 | rptr += 16; | |
3417 | rptr &= rdev->ih.ptr_mask; | |
3418 | } | |
45f9a39b | 3419 | if (queue_hotplug) |
32c87fca | 3420 | schedule_work(&rdev->hotplug_work); |
f122c610 AD |
3421 | if (queue_hdmi) |
3422 | schedule_work(&rdev->audio_work); | |
45f9a39b AD |
3423 | rdev->ih.rptr = rptr; |
3424 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
c20dc369 CK |
3425 | atomic_set(&rdev->ih.lock, 0); |
3426 | ||
3427 | /* make sure wptr hasn't changed while processing */ | |
3428 | wptr = evergreen_get_ih_wptr(rdev); | |
3429 | if (wptr != rptr) | |
3430 | goto restart_ih; | |
3431 | ||
45f9a39b AD |
3432 | return IRQ_HANDLED; |
3433 | } | |
3434 | ||
233d1ad5 AD |
3435 | /** |
3436 | * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring | |
3437 | * | |
3438 | * @rdev: radeon_device pointer | |
3439 | * @fence: radeon fence object | |
3440 | * | |
3441 | * Add a DMA fence packet to the ring to write | |
3442 | * the fence seq number and DMA trap packet to generate | |
3443 | * an interrupt if needed (evergreen-SI). | |
3444 | */ | |
3445 | void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, | |
3446 | struct radeon_fence *fence) | |
3447 | { | |
3448 | struct radeon_ring *ring = &rdev->ring[fence->ring]; | |
3449 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; | |
3450 | /* write the fence */ | |
0fcb6155 | 3451 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); |
233d1ad5 AD |
3452 | radeon_ring_write(ring, addr & 0xfffffffc); |
3453 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); | |
3454 | radeon_ring_write(ring, fence->seq); | |
3455 | /* generate an interrupt */ | |
0fcb6155 | 3456 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); |
233d1ad5 | 3457 | /* flush HDP */ |
0fcb6155 | 3458 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0)); |
4b681c28 | 3459 | radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); |
233d1ad5 AD |
3460 | radeon_ring_write(ring, 1); |
3461 | } | |
3462 | ||
3463 | /** | |
3464 | * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine | |
3465 | * | |
3466 | * @rdev: radeon_device pointer | |
3467 | * @ib: IB object to schedule | |
3468 | * | |
3469 | * Schedule an IB in the DMA ring (evergreen). | |
3470 | */ | |
3471 | void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, | |
3472 | struct radeon_ib *ib) | |
3473 | { | |
3474 | struct radeon_ring *ring = &rdev->ring[ib->ring]; | |
3475 | ||
3476 | if (rdev->wb.enabled) { | |
3477 | u32 next_rptr = ring->wptr + 4; | |
3478 | while ((next_rptr & 7) != 5) | |
3479 | next_rptr++; | |
3480 | next_rptr += 3; | |
0fcb6155 | 3481 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1)); |
233d1ad5 AD |
3482 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
3483 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); | |
3484 | radeon_ring_write(ring, next_rptr); | |
3485 | } | |
3486 | ||
3487 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. | |
3488 | * Pad as necessary with NOPs. | |
3489 | */ | |
3490 | while ((ring->wptr & 7) != 5) | |
0fcb6155 JG |
3491 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); |
3492 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0)); | |
233d1ad5 AD |
3493 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
3494 | radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); | |
3495 | ||
3496 | } | |
3497 | ||
3498 | /** | |
3499 | * evergreen_copy_dma - copy pages using the DMA engine | |
3500 | * | |
3501 | * @rdev: radeon_device pointer | |
3502 | * @src_offset: src GPU address | |
3503 | * @dst_offset: dst GPU address | |
3504 | * @num_gpu_pages: number of GPU pages to xfer | |
3505 | * @fence: radeon fence object | |
3506 | * | |
3507 | * Copy GPU paging using the DMA engine (evergreen-cayman). | |
3508 | * Used by the radeon ttm implementation to move pages if | |
3509 | * registered as the asic copy callback. | |
3510 | */ | |
3511 | int evergreen_copy_dma(struct radeon_device *rdev, | |
3512 | uint64_t src_offset, uint64_t dst_offset, | |
3513 | unsigned num_gpu_pages, | |
3514 | struct radeon_fence **fence) | |
3515 | { | |
3516 | struct radeon_semaphore *sem = NULL; | |
3517 | int ring_index = rdev->asic->copy.dma_ring_index; | |
3518 | struct radeon_ring *ring = &rdev->ring[ring_index]; | |
3519 | u32 size_in_dw, cur_size_in_dw; | |
3520 | int i, num_loops; | |
3521 | int r = 0; | |
3522 | ||
3523 | r = radeon_semaphore_create(rdev, &sem); | |
3524 | if (r) { | |
3525 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
3526 | return r; | |
3527 | } | |
3528 | ||
3529 | size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; | |
3530 | num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff); | |
3531 | r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); | |
3532 | if (r) { | |
3533 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
3534 | radeon_semaphore_free(rdev, &sem, NULL); | |
3535 | return r; | |
3536 | } | |
3537 | ||
3538 | if (radeon_fence_need_sync(*fence, ring->idx)) { | |
3539 | radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, | |
3540 | ring->idx); | |
3541 | radeon_fence_note_sync(*fence, ring->idx); | |
3542 | } else { | |
3543 | radeon_semaphore_free(rdev, &sem, NULL); | |
3544 | } | |
3545 | ||
3546 | for (i = 0; i < num_loops; i++) { | |
3547 | cur_size_in_dw = size_in_dw; | |
3548 | if (cur_size_in_dw > 0xFFFFF) | |
3549 | cur_size_in_dw = 0xFFFFF; | |
3550 | size_in_dw -= cur_size_in_dw; | |
0fcb6155 | 3551 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw)); |
233d1ad5 AD |
3552 | radeon_ring_write(ring, dst_offset & 0xfffffffc); |
3553 | radeon_ring_write(ring, src_offset & 0xfffffffc); | |
3554 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); | |
3555 | radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); | |
3556 | src_offset += cur_size_in_dw * 4; | |
3557 | dst_offset += cur_size_in_dw * 4; | |
3558 | } | |
3559 | ||
3560 | r = radeon_fence_emit(rdev, fence, ring->idx); | |
3561 | if (r) { | |
3562 | radeon_ring_unlock_undo(rdev, ring); | |
3563 | return r; | |
3564 | } | |
3565 | ||
3566 | radeon_ring_unlock_commit(rdev, ring); | |
3567 | radeon_semaphore_free(rdev, &sem, *fence); | |
3568 | ||
3569 | return r; | |
3570 | } | |
3571 | ||
bcc1c2a1 AD |
3572 | static int evergreen_startup(struct radeon_device *rdev) |
3573 | { | |
e32eb50d | 3574 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
bcc1c2a1 AD |
3575 | int r; |
3576 | ||
9e46a48d | 3577 | /* enable pcie gen2 link */ |
cd54033a | 3578 | evergreen_pcie_gen2_enable(rdev); |
9e46a48d | 3579 | |
0af62b01 AD |
3580 | if (ASIC_IS_DCE5(rdev)) { |
3581 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { | |
3582 | r = ni_init_microcode(rdev); | |
3583 | if (r) { | |
3584 | DRM_ERROR("Failed to load firmware!\n"); | |
3585 | return r; | |
3586 | } | |
3587 | } | |
755d819e | 3588 | r = ni_mc_load_microcode(rdev); |
bcc1c2a1 | 3589 | if (r) { |
0af62b01 | 3590 | DRM_ERROR("Failed to load MC firmware!\n"); |
bcc1c2a1 AD |
3591 | return r; |
3592 | } | |
0af62b01 AD |
3593 | } else { |
3594 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { | |
3595 | r = r600_init_microcode(rdev); | |
3596 | if (r) { | |
3597 | DRM_ERROR("Failed to load firmware!\n"); | |
3598 | return r; | |
3599 | } | |
3600 | } | |
bcc1c2a1 | 3601 | } |
fe251e2f | 3602 | |
16cdf04d AD |
3603 | r = r600_vram_scratch_init(rdev); |
3604 | if (r) | |
3605 | return r; | |
3606 | ||
bcc1c2a1 | 3607 | evergreen_mc_program(rdev); |
bcc1c2a1 | 3608 | if (rdev->flags & RADEON_IS_AGP) { |
0fcdb61e | 3609 | evergreen_agp_enable(rdev); |
bcc1c2a1 AD |
3610 | } else { |
3611 | r = evergreen_pcie_gart_enable(rdev); | |
3612 | if (r) | |
3613 | return r; | |
3614 | } | |
bcc1c2a1 | 3615 | evergreen_gpu_init(rdev); |
bcc1c2a1 | 3616 | |
d7ccd8fc | 3617 | r = evergreen_blit_init(rdev); |
bcc1c2a1 | 3618 | if (r) { |
fb3d9e97 | 3619 | r600_blit_fini(rdev); |
27cd7769 | 3620 | rdev->asic->copy.copy = NULL; |
d7ccd8fc | 3621 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
bcc1c2a1 AD |
3622 | } |
3623 | ||
724c80e1 AD |
3624 | /* allocate wb buffer */ |
3625 | r = radeon_wb_init(rdev); | |
3626 | if (r) | |
3627 | return r; | |
3628 | ||
30eb77f4 JG |
3629 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3630 | if (r) { | |
3631 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3632 | return r; | |
3633 | } | |
3634 | ||
233d1ad5 AD |
3635 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); |
3636 | if (r) { | |
3637 | dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); | |
3638 | return r; | |
3639 | } | |
3640 | ||
bcc1c2a1 AD |
3641 | /* Enable IRQ */ |
3642 | r = r600_irq_init(rdev); | |
3643 | if (r) { | |
3644 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
3645 | radeon_irq_kms_fini(rdev); | |
3646 | return r; | |
3647 | } | |
45f9a39b | 3648 | evergreen_irq_set(rdev); |
bcc1c2a1 | 3649 | |
e32eb50d | 3650 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
78c5560a AD |
3651 | R600_CP_RB_RPTR, R600_CP_RB_WPTR, |
3652 | 0, 0xfffff, RADEON_CP_PACKET2); | |
bcc1c2a1 AD |
3653 | if (r) |
3654 | return r; | |
233d1ad5 AD |
3655 | |
3656 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; | |
3657 | r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, | |
3658 | DMA_RB_RPTR, DMA_RB_WPTR, | |
0fcb6155 | 3659 | 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); |
233d1ad5 AD |
3660 | if (r) |
3661 | return r; | |
3662 | ||
bcc1c2a1 AD |
3663 | r = evergreen_cp_load_microcode(rdev); |
3664 | if (r) | |
3665 | return r; | |
fe251e2f | 3666 | r = evergreen_cp_resume(rdev); |
233d1ad5 AD |
3667 | if (r) |
3668 | return r; | |
3669 | r = r600_dma_resume(rdev); | |
bcc1c2a1 AD |
3670 | if (r) |
3671 | return r; | |
fe251e2f | 3672 | |
2898c348 CK |
3673 | r = radeon_ib_pool_init(rdev); |
3674 | if (r) { | |
3675 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 3676 | return r; |
2898c348 | 3677 | } |
b15ba512 | 3678 | |
69d2ae57 RM |
3679 | r = r600_audio_init(rdev); |
3680 | if (r) { | |
3681 | DRM_ERROR("radeon: audio init failed\n"); | |
b15ba512 JG |
3682 | return r; |
3683 | } | |
3684 | ||
bcc1c2a1 AD |
3685 | return 0; |
3686 | } | |
3687 | ||
3688 | int evergreen_resume(struct radeon_device *rdev) | |
3689 | { | |
3690 | int r; | |
3691 | ||
86f5c9ed AD |
3692 | /* reset the asic, the gfx blocks are often in a bad state |
3693 | * after the driver is unloaded or after a resume | |
3694 | */ | |
3695 | if (radeon_asic_reset(rdev)) | |
3696 | dev_warn(rdev->dev, "GPU reset failed !\n"); | |
bcc1c2a1 AD |
3697 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
3698 | * posting will perform necessary task to bring back GPU into good | |
3699 | * shape. | |
3700 | */ | |
3701 | /* post card */ | |
3702 | atom_asic_init(rdev->mode_info.atom_context); | |
bcc1c2a1 | 3703 | |
b15ba512 | 3704 | rdev->accel_working = true; |
bcc1c2a1 AD |
3705 | r = evergreen_startup(rdev); |
3706 | if (r) { | |
755d819e | 3707 | DRM_ERROR("evergreen startup failed on resume\n"); |
6b7746e8 | 3708 | rdev->accel_working = false; |
bcc1c2a1 AD |
3709 | return r; |
3710 | } | |
fe251e2f | 3711 | |
bcc1c2a1 AD |
3712 | return r; |
3713 | ||
3714 | } | |
3715 | ||
3716 | int evergreen_suspend(struct radeon_device *rdev) | |
3717 | { | |
69d2ae57 | 3718 | r600_audio_fini(rdev); |
bcc1c2a1 | 3719 | r700_cp_stop(rdev); |
233d1ad5 | 3720 | r600_dma_stop(rdev); |
45f9a39b | 3721 | evergreen_irq_suspend(rdev); |
724c80e1 | 3722 | radeon_wb_disable(rdev); |
bcc1c2a1 | 3723 | evergreen_pcie_gart_disable(rdev); |
d7ccd8fc AD |
3724 | |
3725 | return 0; | |
3726 | } | |
3727 | ||
bcc1c2a1 AD |
3728 | /* Plan is to move initialization in that function and use |
3729 | * helper function so that radeon_device_init pretty much | |
3730 | * do nothing more than calling asic specific function. This | |
3731 | * should also allow to remove a bunch of callback function | |
3732 | * like vram_info. | |
3733 | */ | |
3734 | int evergreen_init(struct radeon_device *rdev) | |
3735 | { | |
3736 | int r; | |
3737 | ||
bcc1c2a1 AD |
3738 | /* Read BIOS */ |
3739 | if (!radeon_get_bios(rdev)) { | |
3740 | if (ASIC_IS_AVIVO(rdev)) | |
3741 | return -EINVAL; | |
3742 | } | |
3743 | /* Must be an ATOMBIOS */ | |
3744 | if (!rdev->is_atom_bios) { | |
755d819e | 3745 | dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); |
bcc1c2a1 AD |
3746 | return -EINVAL; |
3747 | } | |
3748 | r = radeon_atombios_init(rdev); | |
3749 | if (r) | |
3750 | return r; | |
86f5c9ed AD |
3751 | /* reset the asic, the gfx blocks are often in a bad state |
3752 | * after the driver is unloaded or after a resume | |
3753 | */ | |
3754 | if (radeon_asic_reset(rdev)) | |
3755 | dev_warn(rdev->dev, "GPU reset failed !\n"); | |
bcc1c2a1 | 3756 | /* Post card if necessary */ |
fd909c37 | 3757 | if (!radeon_card_posted(rdev)) { |
bcc1c2a1 AD |
3758 | if (!rdev->bios) { |
3759 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
3760 | return -EINVAL; | |
3761 | } | |
3762 | DRM_INFO("GPU not posted. posting now...\n"); | |
3763 | atom_asic_init(rdev->mode_info.atom_context); | |
3764 | } | |
3765 | /* Initialize scratch registers */ | |
3766 | r600_scratch_init(rdev); | |
3767 | /* Initialize surface registers */ | |
3768 | radeon_surface_init(rdev); | |
3769 | /* Initialize clocks */ | |
3770 | radeon_get_clock_info(rdev->ddev); | |
bcc1c2a1 AD |
3771 | /* Fence driver */ |
3772 | r = radeon_fence_driver_init(rdev); | |
3773 | if (r) | |
3774 | return r; | |
d594e46a JG |
3775 | /* initialize AGP */ |
3776 | if (rdev->flags & RADEON_IS_AGP) { | |
3777 | r = radeon_agp_init(rdev); | |
3778 | if (r) | |
3779 | radeon_agp_disable(rdev); | |
3780 | } | |
3781 | /* initialize memory controller */ | |
bcc1c2a1 AD |
3782 | r = evergreen_mc_init(rdev); |
3783 | if (r) | |
3784 | return r; | |
3785 | /* Memory manager */ | |
3786 | r = radeon_bo_init(rdev); | |
3787 | if (r) | |
3788 | return r; | |
45f9a39b | 3789 | |
bcc1c2a1 AD |
3790 | r = radeon_irq_kms_init(rdev); |
3791 | if (r) | |
3792 | return r; | |
3793 | ||
e32eb50d CK |
3794 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
3795 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | |
bcc1c2a1 | 3796 | |
233d1ad5 AD |
3797 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
3798 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); | |
3799 | ||
bcc1c2a1 AD |
3800 | rdev->ih.ring_obj = NULL; |
3801 | r600_ih_ring_init(rdev, 64 * 1024); | |
3802 | ||
3803 | r = r600_pcie_gart_init(rdev); | |
3804 | if (r) | |
3805 | return r; | |
0fcdb61e | 3806 | |
148a03bc | 3807 | rdev->accel_working = true; |
bcc1c2a1 AD |
3808 | r = evergreen_startup(rdev); |
3809 | if (r) { | |
fe251e2f AD |
3810 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
3811 | r700_cp_fini(rdev); | |
233d1ad5 | 3812 | r600_dma_fini(rdev); |
fe251e2f | 3813 | r600_irq_fini(rdev); |
724c80e1 | 3814 | radeon_wb_fini(rdev); |
2898c348 | 3815 | radeon_ib_pool_fini(rdev); |
fe251e2f | 3816 | radeon_irq_kms_fini(rdev); |
0fcdb61e | 3817 | evergreen_pcie_gart_fini(rdev); |
bcc1c2a1 AD |
3818 | rdev->accel_working = false; |
3819 | } | |
77e00f2e AD |
3820 | |
3821 | /* Don't start up if the MC ucode is missing on BTC parts. | |
3822 | * The default clocks and voltages before the MC ucode | |
3823 | * is loaded are not suffient for advanced operations. | |
3824 | */ | |
3825 | if (ASIC_IS_DCE5(rdev)) { | |
3826 | if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { | |
3827 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); | |
3828 | return -EINVAL; | |
3829 | } | |
3830 | } | |
3831 | ||
bcc1c2a1 AD |
3832 | return 0; |
3833 | } | |
3834 | ||
3835 | void evergreen_fini(struct radeon_device *rdev) | |
3836 | { | |
69d2ae57 | 3837 | r600_audio_fini(rdev); |
fb3d9e97 | 3838 | r600_blit_fini(rdev); |
45f9a39b | 3839 | r700_cp_fini(rdev); |
233d1ad5 | 3840 | r600_dma_fini(rdev); |
bcc1c2a1 | 3841 | r600_irq_fini(rdev); |
724c80e1 | 3842 | radeon_wb_fini(rdev); |
2898c348 | 3843 | radeon_ib_pool_fini(rdev); |
bcc1c2a1 | 3844 | radeon_irq_kms_fini(rdev); |
bcc1c2a1 | 3845 | evergreen_pcie_gart_fini(rdev); |
16cdf04d | 3846 | r600_vram_scratch_fini(rdev); |
bcc1c2a1 AD |
3847 | radeon_gem_fini(rdev); |
3848 | radeon_fence_driver_fini(rdev); | |
bcc1c2a1 AD |
3849 | radeon_agp_fini(rdev); |
3850 | radeon_bo_fini(rdev); | |
3851 | radeon_atombios_fini(rdev); | |
3852 | kfree(rdev->bios); | |
3853 | rdev->bios = NULL; | |
bcc1c2a1 | 3854 | } |
9e46a48d | 3855 | |
b07759bf | 3856 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev) |
9e46a48d | 3857 | { |
197bbb3d DA |
3858 | u32 link_width_cntl, speed_cntl, mask; |
3859 | int ret; | |
9e46a48d | 3860 | |
d42dd579 AD |
3861 | if (radeon_pcie_gen2 == 0) |
3862 | return; | |
3863 | ||
9e46a48d AD |
3864 | if (rdev->flags & RADEON_IS_IGP) |
3865 | return; | |
3866 | ||
3867 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
3868 | return; | |
3869 | ||
3870 | /* x2 cards have a special sequence */ | |
3871 | if (ASIC_IS_X2(rdev)) | |
3872 | return; | |
3873 | ||
197bbb3d DA |
3874 | ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
3875 | if (ret != 0) | |
3876 | return; | |
3877 | ||
3878 | if (!(mask & DRM_PCIE_SPEED_50)) | |
3879 | return; | |
3880 | ||
3691feea AD |
3881 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
3882 | if (speed_cntl & LC_CURRENT_DATA_RATE) { | |
3883 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); | |
3884 | return; | |
3885 | } | |
3886 | ||
197bbb3d DA |
3887 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
3888 | ||
9e46a48d AD |
3889 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || |
3890 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
3891 | ||
3892 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3893 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
3894 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3895 | ||
3896 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3897 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; | |
3898 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3899 | ||
3900 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3901 | speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; | |
3902 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3903 | ||
3904 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3905 | speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; | |
3906 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3907 | ||
3908 | speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); | |
3909 | speed_cntl |= LC_GEN2_EN_STRAP; | |
3910 | WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); | |
3911 | ||
3912 | } else { | |
3913 | link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); | |
3914 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ | |
3915 | if (1) | |
3916 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
3917 | else | |
3918 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
3919 | WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
3920 | } | |
3921 | } |