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drm/radeon: fix HD6790, HD6570 backend programming
[linux-2.6-block.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
b07759bf 42void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 43extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44 int ring, u32 cp_int_cntl);
bcc1c2a1 45
285484e2
JG		 46void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
47 unsigned *bankh, unsigned *mtaspect,
48 unsigned *tile_split)
49{
50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
54 switch (*bankw) {
55 default:
56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
60 }
61 switch (*bankh) {
62 default:
63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
67 }
68 switch (*mtaspect) {
69 default:
70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
74 }
75}
76
d054ac16
AD		 77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78{
79 u16 ctl, v;
80 int cap, err;
81
82 cap = pci_pcie_cap(rdev->pdev);
83 if (!cap)
84 return;
85
86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
87 if (err)
88 return;
89
90 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
91
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
94 */
95 if ((v == 0) || (v == 6) || (v == 7)) {
96 ctl &= ~PCI_EXP_DEVCTL_READRQ;
97 ctl |= (2 << 12);
98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
99 }
100}
101
3ae19b75
AD		 102void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
103{
104 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
105 int i;
106
107 if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
108 for (i = 0; i < rdev->usec_timeout; i++) {
109 if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
110 break;
111 udelay(1);
112 }
113 for (i = 0; i < rdev->usec_timeout; i++) {
114 if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
115 break;
116 udelay(1);
117 }
118 }
119}
120
6f34be50
AD		 121void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
122{
6f34be50
AD		 123 /* enable the pflip int */
124 radeon_irq_kms_pflip_irq_get(rdev, crtc);
125}
126
127void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
128{
129 /* disable the pflip int */
130 radeon_irq_kms_pflip_irq_put(rdev, crtc);
131}
132
133u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
134{
135 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
136 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 137 int i;
6f34be50
AD		 138
139 /* Lock the graphics update lock */
140 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
141 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
142
143 /* update the scanout addresses */
144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
145 upper_32_bits(crtc_base));
146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
147 (u32)crtc_base);
148
149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
150 upper_32_bits(crtc_base));
151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
152 (u32)crtc_base);
153
154 /* Wait for update_pending to go high. */
f6496479
AD		 155 for (i = 0; i < rdev->usec_timeout; i++) {
156 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
157 break;
158 udelay(1);
159 }
6f34be50
AD		 160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
161
162 /* Unlock the lock, so double-buffering can take place inside vblank */
163 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
164 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
165
166 /* Return current update_pending status: */
167 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
168}
169
21a8122a 170/* get temperature in millidegrees */
20d391d7 171int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 172{
1c88d74f
AD		 173 u32 temp, toffset;
174 int actual_temp = 0;
67b3f823
AD		 175
176 if (rdev->family == CHIP_JUNIPER) {
177 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
178 TOFFSET_SHIFT;
179 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
180 TS0_ADC_DOUT_SHIFT;
181
182 if (toffset & 0x100)
183 actual_temp = temp / 2 - (0x200 - toffset);
184 else
185 actual_temp = temp / 2 + toffset;
186
187 actual_temp = actual_temp * 1000;
188
189 } else {
190 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
191 ASIC_T_SHIFT;
192
193 if (temp & 0x400)
194 actual_temp = -256;
195 else if (temp & 0x200)
196 actual_temp = 255;
197 else if (temp & 0x100) {
198 actual_temp = temp & 0x1ff;
199 actual_temp |= ~0x1ff;
200 } else
201 actual_temp = temp & 0xff;
202
203 actual_temp = (actual_temp * 1000) / 2;
204 }
21a8122a 205
67b3f823 206 return actual_temp;
21a8122a
AD		 207}
208
20d391d7 209int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 210{
211 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 212 int actual_temp = temp - 49;
e33df25f
AD		 213
214 return actual_temp * 1000;
215}
216
a4c9e2ee
AD		 217void sumo_pm_init_profile(struct radeon_device *rdev)
218{
219 int idx;
220
221 /* default */
222 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
223 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
224 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
225 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
226
227 /* low,mid sh/mh */
228 if (rdev->flags & RADEON_IS_MOBILITY)
229 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
230 else
231 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
232
233 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
234 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
235 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
236 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
237
238 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
239 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
240 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
241 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
242
243 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
244 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
245 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
246 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
247
248 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
249 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
250 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
251 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
252
253 /* high sh/mh */
254 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
255 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
256 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
257 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
258 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
259 rdev->pm.power_state[idx].num_clock_modes - 1;
260
261 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
262 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
263 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
264 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
265 rdev->pm.power_state[idx].num_clock_modes - 1;
266}
267
49e02b73
AD		 268void evergreen_pm_misc(struct radeon_device *rdev)
269{
a081a9d6
RM		 270 int req_ps_idx = rdev->pm.requested_power_state_index;
271 int req_cm_idx = rdev->pm.requested_clock_mode_index;
272 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
273 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 274
2feea49a 275 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 276 /* 0xff01 is a flag rather then an actual voltage */
277 if (voltage->voltage == 0xff01)
278 return;
2feea49a 279 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 280 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 281 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 282 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
283 }
a377e187
AD		 284 /* 0xff01 is a flag rather then an actual voltage */
285 if (voltage->vddci == 0xff01)
286 return;
2feea49a
AD		 287 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
288 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
289 rdev->pm.current_vddci = voltage->vddci;
290 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 291 }
292 }
49e02b73
AD		 293}
294
295void evergreen_pm_prepare(struct radeon_device *rdev)
296{
297 struct drm_device *ddev = rdev->ddev;
298 struct drm_crtc *crtc;
299 struct radeon_crtc *radeon_crtc;
300 u32 tmp;
301
302 /* disable any active CRTCs */
303 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
304 radeon_crtc = to_radeon_crtc(crtc);
305 if (radeon_crtc->enabled) {
306 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
307 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
308 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
309 }
310 }
311}
312
313void evergreen_pm_finish(struct radeon_device *rdev)
314{
315 struct drm_device *ddev = rdev->ddev;
316 struct drm_crtc *crtc;
317 struct radeon_crtc *radeon_crtc;
318 u32 tmp;
319
320 /* enable any active CRTCs */
321 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
322 radeon_crtc = to_radeon_crtc(crtc);
323 if (radeon_crtc->enabled) {
324 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
325 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
326 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
327 }
328 }
329}
330
bcc1c2a1
AD		 331bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
332{
333 bool connected = false;
0ca2ab52
AD		 334
335 switch (hpd) {
336 case RADEON_HPD_1:
337 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
338 connected = true;
339 break;
340 case RADEON_HPD_2:
341 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
342 connected = true;
343 break;
344 case RADEON_HPD_3:
345 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
346 connected = true;
347 break;
348 case RADEON_HPD_4:
349 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
350 connected = true;
351 break;
352 case RADEON_HPD_5:
353 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
354 connected = true;
355 break;
356 case RADEON_HPD_6:
357 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
358 connected = true;
359 break;
360 default:
361 break;
362 }
363
bcc1c2a1
AD		 364 return connected;
365}
366
367void evergreen_hpd_set_polarity(struct radeon_device *rdev,
368 enum radeon_hpd_id hpd)
369{
0ca2ab52
AD		 370 u32 tmp;
371 bool connected = evergreen_hpd_sense(rdev, hpd);
372
373 switch (hpd) {
374 case RADEON_HPD_1:
375 tmp = RREG32(DC_HPD1_INT_CONTROL);
376 if (connected)
377 tmp &= ~DC_HPDx_INT_POLARITY;
378 else
379 tmp |= DC_HPDx_INT_POLARITY;
380 WREG32(DC_HPD1_INT_CONTROL, tmp);
381 break;
382 case RADEON_HPD_2:
383 tmp = RREG32(DC_HPD2_INT_CONTROL);
384 if (connected)
385 tmp &= ~DC_HPDx_INT_POLARITY;
386 else
387 tmp |= DC_HPDx_INT_POLARITY;
388 WREG32(DC_HPD2_INT_CONTROL, tmp);
389 break;
390 case RADEON_HPD_3:
391 tmp = RREG32(DC_HPD3_INT_CONTROL);
392 if (connected)
393 tmp &= ~DC_HPDx_INT_POLARITY;
394 else
395 tmp |= DC_HPDx_INT_POLARITY;
396 WREG32(DC_HPD3_INT_CONTROL, tmp);
397 break;
398 case RADEON_HPD_4:
399 tmp = RREG32(DC_HPD4_INT_CONTROL);
400 if (connected)
401 tmp &= ~DC_HPDx_INT_POLARITY;
402 else
403 tmp |= DC_HPDx_INT_POLARITY;
404 WREG32(DC_HPD4_INT_CONTROL, tmp);
405 break;
406 case RADEON_HPD_5:
407 tmp = RREG32(DC_HPD5_INT_CONTROL);
408 if (connected)
409 tmp &= ~DC_HPDx_INT_POLARITY;
410 else
411 tmp |= DC_HPDx_INT_POLARITY;
412 WREG32(DC_HPD5_INT_CONTROL, tmp);
413 break;
414 case RADEON_HPD_6:
415 tmp = RREG32(DC_HPD6_INT_CONTROL);
416 if (connected)
417 tmp &= ~DC_HPDx_INT_POLARITY;
418 else
419 tmp |= DC_HPDx_INT_POLARITY;
420 WREG32(DC_HPD6_INT_CONTROL, tmp);
421 break;
422 default:
423 break;
424 }
bcc1c2a1
AD		 425}
426
427void evergreen_hpd_init(struct radeon_device *rdev)
428{
0ca2ab52
AD		 429 struct drm_device *dev = rdev->ddev;
430 struct drm_connector *connector;
431 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
432 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 433
0ca2ab52
AD		 434 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
435 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
436 switch (radeon_connector->hpd.hpd) {
437 case RADEON_HPD_1:
438 WREG32(DC_HPD1_CONTROL, tmp);
439 rdev->irq.hpd[0] = true;
440 break;
441 case RADEON_HPD_2:
442 WREG32(DC_HPD2_CONTROL, tmp);
443 rdev->irq.hpd[1] = true;
444 break;
445 case RADEON_HPD_3:
446 WREG32(DC_HPD3_CONTROL, tmp);
447 rdev->irq.hpd[2] = true;
448 break;
449 case RADEON_HPD_4:
450 WREG32(DC_HPD4_CONTROL, tmp);
451 rdev->irq.hpd[3] = true;
452 break;
453 case RADEON_HPD_5:
454 WREG32(DC_HPD5_CONTROL, tmp);
455 rdev->irq.hpd[4] = true;
456 break;
457 case RADEON_HPD_6:
458 WREG32(DC_HPD6_CONTROL, tmp);
459 rdev->irq.hpd[5] = true;
460 break;
461 default:
462 break;
463 }
64912e99 464 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
0ca2ab52
AD		 465 }
466 if (rdev->irq.installed)
467 evergreen_irq_set(rdev);
bcc1c2a1
AD		 468}
469
0ca2ab52 470void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 471{
0ca2ab52
AD		 472 struct drm_device *dev = rdev->ddev;
473 struct drm_connector *connector;
474
475 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
477 switch (radeon_connector->hpd.hpd) {
478 case RADEON_HPD_1:
479 WREG32(DC_HPD1_CONTROL, 0);
480 rdev->irq.hpd[0] = false;
481 break;
482 case RADEON_HPD_2:
483 WREG32(DC_HPD2_CONTROL, 0);
484 rdev->irq.hpd[1] = false;
485 break;
486 case RADEON_HPD_3:
487 WREG32(DC_HPD3_CONTROL, 0);
488 rdev->irq.hpd[2] = false;
489 break;
490 case RADEON_HPD_4:
491 WREG32(DC_HPD4_CONTROL, 0);
492 rdev->irq.hpd[3] = false;
493 break;
494 case RADEON_HPD_5:
495 WREG32(DC_HPD5_CONTROL, 0);
496 rdev->irq.hpd[4] = false;
497 break;
498 case RADEON_HPD_6:
499 WREG32(DC_HPD6_CONTROL, 0);
500 rdev->irq.hpd[5] = false;
501 break;
502 default:
503 break;
504 }
505 }
bcc1c2a1
AD		 506}
507
f9d9c362
AD		 508/* watermark setup */
509
510static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
511 struct radeon_crtc *radeon_crtc,
512 struct drm_display_mode *mode,
513 struct drm_display_mode *other_mode)
514{
12dfc843 515 u32 tmp;
f9d9c362
AD		 516 /*
517 * Line Buffer Setup
518 * There are 3 line buffers, each one shared by 2 display controllers.
519 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
520 * the display controllers. The paritioning is done via one of four
521 * preset allocations specified in bits 2:0:
522 * first display controller
523 * 0 - first half of lb (3840 * 2)
524 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 525 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 526 * 3 - first 1/4 of lb (1920 * 2)
527 * second display controller
528 * 4 - second half of lb (3840 * 2)
529 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 530 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 531 * 7 - last 1/4 of lb (1920 * 2)
532 */
12dfc843
AD		 533 /* this can get tricky if we have two large displays on a paired group
534 * of crtcs. Ideally for multiple large displays we'd assign them to
535 * non-linked crtcs for maximum line buffer allocation.
536 */
537 if (radeon_crtc->base.enabled && mode) {
538 if (other_mode)
f9d9c362 539 tmp = 0; /* 1/2 */
12dfc843
AD		 540 else
541 tmp = 2; /* whole */
542 } else
543 tmp = 0;
f9d9c362
AD		 544
545 /* second controller of the pair uses second half of the lb */
546 if (radeon_crtc->crtc_id % 2)
547 tmp += 4;
548 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
549
12dfc843
AD		 550 if (radeon_crtc->base.enabled && mode) {
551 switch (tmp) {
552 case 0:
553 case 4:
554 default:
555 if (ASIC_IS_DCE5(rdev))
556 return 4096 * 2;
557 else
558 return 3840 * 2;
559 case 1:
560 case 5:
561 if (ASIC_IS_DCE5(rdev))
562 return 6144 * 2;
563 else
564 return 5760 * 2;
565 case 2:
566 case 6:
567 if (ASIC_IS_DCE5(rdev))
568 return 8192 * 2;
569 else
570 return 7680 * 2;
571 case 3:
572 case 7:
573 if (ASIC_IS_DCE5(rdev))
574 return 2048 * 2;
575 else
576 return 1920 * 2;
577 }
f9d9c362 578 }
12dfc843
AD		 579
580 /* controller not enabled, so no lb used */
581 return 0;
f9d9c362
AD		 582}
583
ca7db22b 584u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 585{
586 u32 tmp = RREG32(MC_SHARED_CHMAP);
587
588 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
589 case 0:
590 default:
591 return 1;
592 case 1:
593 return 2;
594 case 2:
595 return 4;
596 case 3:
597 return 8;
598 }
599}
600
601struct evergreen_wm_params {
602 u32 dram_channels; /* number of dram channels */
603 u32 yclk; /* bandwidth per dram data pin in kHz */
604 u32 sclk; /* engine clock in kHz */
605 u32 disp_clk; /* display clock in kHz */
606 u32 src_width; /* viewport width */
607 u32 active_time; /* active display time in ns */
608 u32 blank_time; /* blank time in ns */
609 bool interlaced; /* mode is interlaced */
610 fixed20_12 vsc; /* vertical scale ratio */
611 u32 num_heads; /* number of active crtcs */
612 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
613 u32 lb_size; /* line buffer allocated to pipe */
614 u32 vtaps; /* vertical scaler taps */
615};
616
617static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
618{
619 /* Calculate DRAM Bandwidth and the part allocated to display. */
620 fixed20_12 dram_efficiency; /* 0.7 */
621 fixed20_12 yclk, dram_channels, bandwidth;
622 fixed20_12 a;
623
624 a.full = dfixed_const(1000);
625 yclk.full = dfixed_const(wm->yclk);
626 yclk.full = dfixed_div(yclk, a);
627 dram_channels.full = dfixed_const(wm->dram_channels * 4);
628 a.full = dfixed_const(10);
629 dram_efficiency.full = dfixed_const(7);
630 dram_efficiency.full = dfixed_div(dram_efficiency, a);
631 bandwidth.full = dfixed_mul(dram_channels, yclk);
632 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
633
634 return dfixed_trunc(bandwidth);
635}
636
637static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
638{
639 /* Calculate DRAM Bandwidth and the part allocated to display. */
640 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
641 fixed20_12 yclk, dram_channels, bandwidth;
642 fixed20_12 a;
643
644 a.full = dfixed_const(1000);
645 yclk.full = dfixed_const(wm->yclk);
646 yclk.full = dfixed_div(yclk, a);
647 dram_channels.full = dfixed_const(wm->dram_channels * 4);
648 a.full = dfixed_const(10);
649 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
650 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
651 bandwidth.full = dfixed_mul(dram_channels, yclk);
652 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
653
654 return dfixed_trunc(bandwidth);
655}
656
657static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
658{
659 /* Calculate the display Data return Bandwidth */
660 fixed20_12 return_efficiency; /* 0.8 */
661 fixed20_12 sclk, bandwidth;
662 fixed20_12 a;
663
664 a.full = dfixed_const(1000);
665 sclk.full = dfixed_const(wm->sclk);
666 sclk.full = dfixed_div(sclk, a);
667 a.full = dfixed_const(10);
668 return_efficiency.full = dfixed_const(8);
669 return_efficiency.full = dfixed_div(return_efficiency, a);
670 a.full = dfixed_const(32);
671 bandwidth.full = dfixed_mul(a, sclk);
672 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
673
674 return dfixed_trunc(bandwidth);
675}
676
677static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
678{
679 /* Calculate the DMIF Request Bandwidth */
680 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
681 fixed20_12 disp_clk, bandwidth;
682 fixed20_12 a;
683
684 a.full = dfixed_const(1000);
685 disp_clk.full = dfixed_const(wm->disp_clk);
686 disp_clk.full = dfixed_div(disp_clk, a);
687 a.full = dfixed_const(10);
688 disp_clk_request_efficiency.full = dfixed_const(8);
689 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
690 a.full = dfixed_const(32);
691 bandwidth.full = dfixed_mul(a, disp_clk);
692 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
693
694 return dfixed_trunc(bandwidth);
695}
696
697static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
698{
699 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
700 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
701 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
702 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
703
704 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
705}
706
707static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
708{
709 /* Calculate the display mode Average Bandwidth
710 * DisplayMode should contain the source and destination dimensions,
711 * timing, etc.
712 */
713 fixed20_12 bpp;
714 fixed20_12 line_time;
715 fixed20_12 src_width;
716 fixed20_12 bandwidth;
717 fixed20_12 a;
718
719 a.full = dfixed_const(1000);
720 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
721 line_time.full = dfixed_div(line_time, a);
722 bpp.full = dfixed_const(wm->bytes_per_pixel);
723 src_width.full = dfixed_const(wm->src_width);
724 bandwidth.full = dfixed_mul(src_width, bpp);
725 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
726 bandwidth.full = dfixed_div(bandwidth, line_time);
727
728 return dfixed_trunc(bandwidth);
729}
730
731static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
732{
733 /* First calcualte the latency in ns */
734 u32 mc_latency = 2000; /* 2000 ns. */
735 u32 available_bandwidth = evergreen_available_bandwidth(wm);
736 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
737 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
738 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
739 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
740 (wm->num_heads * cursor_line_pair_return_time);
741 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
742 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
743 fixed20_12 a, b, c;
744
745 if (wm->num_heads == 0)
746 return 0;
747
748 a.full = dfixed_const(2);
749 b.full = dfixed_const(1);
750 if ((wm->vsc.full > a.full) ||
751 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
752 (wm->vtaps >= 5) ||
753 ((wm->vsc.full >= a.full) && wm->interlaced))
754 max_src_lines_per_dst_line = 4;
755 else
756 max_src_lines_per_dst_line = 2;
757
758 a.full = dfixed_const(available_bandwidth);
759 b.full = dfixed_const(wm->num_heads);
760 a.full = dfixed_div(a, b);
761
762 b.full = dfixed_const(1000);
763 c.full = dfixed_const(wm->disp_clk);
764 b.full = dfixed_div(c, b);
765 c.full = dfixed_const(wm->bytes_per_pixel);
766 b.full = dfixed_mul(b, c);
767
768 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
769
770 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
771 b.full = dfixed_const(1000);
772 c.full = dfixed_const(lb_fill_bw);
773 b.full = dfixed_div(c, b);
774 a.full = dfixed_div(a, b);
775 line_fill_time = dfixed_trunc(a);
776
777 if (line_fill_time < wm->active_time)
778 return latency;
779 else
780 return latency + (line_fill_time - wm->active_time);
781
782}
783
784static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
785{
786 if (evergreen_average_bandwidth(wm) <=
787 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
788 return true;
789 else
790 return false;
791};
792
793static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
794{
795 if (evergreen_average_bandwidth(wm) <=
796 (evergreen_available_bandwidth(wm) / wm->num_heads))
797 return true;
798 else
799 return false;
800};
801
802static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
803{
804 u32 lb_partitions = wm->lb_size / wm->src_width;
805 u32 line_time = wm->active_time + wm->blank_time;
806 u32 latency_tolerant_lines;
807 u32 latency_hiding;
808 fixed20_12 a;
809
810 a.full = dfixed_const(1);
811 if (wm->vsc.full > a.full)
812 latency_tolerant_lines = 1;
813 else {
814 if (lb_partitions <= (wm->vtaps + 1))
815 latency_tolerant_lines = 1;
816 else
817 latency_tolerant_lines = 2;
818 }
819
820 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
821
822 if (evergreen_latency_watermark(wm) <= latency_hiding)
823 return true;
824 else
825 return false;
826}
827
828static void evergreen_program_watermarks(struct radeon_device *rdev,
829 struct radeon_crtc *radeon_crtc,
830 u32 lb_size, u32 num_heads)
831{
832 struct drm_display_mode *mode = &radeon_crtc->base.mode;
833 struct evergreen_wm_params wm;
834 u32 pixel_period;
835 u32 line_time = 0;
836 u32 latency_watermark_a = 0, latency_watermark_b = 0;
837 u32 priority_a_mark = 0, priority_b_mark = 0;
838 u32 priority_a_cnt = PRIORITY_OFF;
839 u32 priority_b_cnt = PRIORITY_OFF;
840 u32 pipe_offset = radeon_crtc->crtc_id * 16;
841 u32 tmp, arb_control3;
842 fixed20_12 a, b, c;
843
844 if (radeon_crtc->base.enabled && num_heads && mode) {
845 pixel_period = 1000000 / (u32)mode->clock;
846 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
847 priority_a_cnt = 0;
848 priority_b_cnt = 0;
849
850 wm.yclk = rdev->pm.current_mclk * 10;
851 wm.sclk = rdev->pm.current_sclk * 10;
852 wm.disp_clk = mode->clock;
853 wm.src_width = mode->crtc_hdisplay;
854 wm.active_time = mode->crtc_hdisplay * pixel_period;
855 wm.blank_time = line_time - wm.active_time;
856 wm.interlaced = false;
857 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
858 wm.interlaced = true;
859 wm.vsc = radeon_crtc->vsc;
860 wm.vtaps = 1;
861 if (radeon_crtc->rmx_type != RMX_OFF)
862 wm.vtaps = 2;
863 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
864 wm.lb_size = lb_size;
865 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
866 wm.num_heads = num_heads;
867
868 /* set for high clocks */
869 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
870 /* set for low clocks */
871 /* wm.yclk = low clk; wm.sclk = low clk */
872 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
873
874 /* possibly force display priority to high */
875 /* should really do this at mode validation time... */
876 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
877 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
878 !evergreen_check_latency_hiding(&wm) ||
879 (rdev->disp_priority == 2)) {
92bdfd4a 880 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 881 priority_a_cnt |= PRIORITY_ALWAYS_ON;
882 priority_b_cnt |= PRIORITY_ALWAYS_ON;
883 }
884
885 a.full = dfixed_const(1000);
886 b.full = dfixed_const(mode->clock);
887 b.full = dfixed_div(b, a);
888 c.full = dfixed_const(latency_watermark_a);
889 c.full = dfixed_mul(c, b);
890 c.full = dfixed_mul(c, radeon_crtc->hsc);
891 c.full = dfixed_div(c, a);
892 a.full = dfixed_const(16);
893 c.full = dfixed_div(c, a);
894 priority_a_mark = dfixed_trunc(c);
895 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
896
897 a.full = dfixed_const(1000);
898 b.full = dfixed_const(mode->clock);
899 b.full = dfixed_div(b, a);
900 c.full = dfixed_const(latency_watermark_b);
901 c.full = dfixed_mul(c, b);
902 c.full = dfixed_mul(c, radeon_crtc->hsc);
903 c.full = dfixed_div(c, a);
904 a.full = dfixed_const(16);
905 c.full = dfixed_div(c, a);
906 priority_b_mark = dfixed_trunc(c);
907 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
908 }
909
910 /* select wm A */
911 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
912 tmp = arb_control3;
913 tmp &= ~LATENCY_WATERMARK_MASK(3);
914 tmp |= LATENCY_WATERMARK_MASK(1);
915 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
916 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
917 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
918 LATENCY_HIGH_WATERMARK(line_time)));
919 /* select wm B */
920 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
921 tmp &= ~LATENCY_WATERMARK_MASK(3);
922 tmp |= LATENCY_WATERMARK_MASK(2);
923 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
924 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
925 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
926 LATENCY_HIGH_WATERMARK(line_time)));
927 /* restore original selection */
928 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
929
930 /* write the priority marks */
931 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
932 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
933
934}
935
0ca2ab52 936void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 937{
f9d9c362
AD		 938 struct drm_display_mode *mode0 = NULL;
939 struct drm_display_mode *mode1 = NULL;
940 u32 num_heads = 0, lb_size;
941 int i;
942
943 radeon_update_display_priority(rdev);
944
945 for (i = 0; i < rdev->num_crtc; i++) {
946 if (rdev->mode_info.crtcs[i]->base.enabled)
947 num_heads++;
948 }
949 for (i = 0; i < rdev->num_crtc; i += 2) {
950 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
951 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
952 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
953 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
954 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
955 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
956 }
bcc1c2a1
AD		 957}
958
b9952a8a 959int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 960{
961 unsigned i;
962 u32 tmp;
963
964 for (i = 0; i < rdev->usec_timeout; i++) {
965 /* read MC_STATUS */
966 tmp = RREG32(SRBM_STATUS) & 0x1F00;
967 if (!tmp)
968 return 0;
969 udelay(1);
970 }
971 return -1;
972}
973
974/*
975 * GART
976 */
0fcdb61e
AD		 977void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
978{
979 unsigned i;
980 u32 tmp;
981
6f2f48a9
AD		 982 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
983
0fcdb61e
AD		 984 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
985 for (i = 0; i < rdev->usec_timeout; i++) {
986 /* read MC_STATUS */
987 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
988 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
989 if (tmp == 2) {
990 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
991 return;
992 }
993 if (tmp) {
994 return;
995 }
996 udelay(1);
997 }
998}
999
bcc1c2a1
AD		 1000int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1001{
1002 u32 tmp;
0fcdb61e 1003 int r;
bcc1c2a1 1004
c9a1be96 1005 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 1006 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1007 return -EINVAL;
1008 }
1009 r = radeon_gart_table_vram_pin(rdev);
1010 if (r)
1011 return r;
82568565 1012 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1013 /* Setup L2 cache */
1014 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1015 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1016 EFFECTIVE_L2_QUEUE_SIZE(7));
1017 WREG32(VM_L2_CNTL2, 0);
1018 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1019 /* Setup TLB control */
1020 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1021 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1022 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1023 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1024 if (rdev->flags & RADEON_IS_IGP) {
1025 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1026 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1027 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1028 } else {
1029 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1030 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1031 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 1032 if ((rdev->family == CHIP_JUNIPER) ||
1033 (rdev->family == CHIP_CYPRESS) ||
1034 (rdev->family == CHIP_HEMLOCK) ||
1035 (rdev->family == CHIP_BARTS))
1036 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 1037 }
bcc1c2a1
AD		 1038 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1039 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1040 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1041 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1042 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1043 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1044 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1045 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1046 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1047 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1048 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1049 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1050
0fcdb61e 1051 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1052 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1053 (unsigned)(rdev->mc.gtt_size >> 20),
1054 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1055 rdev->gart.ready = true;
1056 return 0;
1057}
1058
1059void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1060{
1061 u32 tmp;
bcc1c2a1
AD		 1062
1063 /* Disable all tables */
0fcdb61e
AD		 1064 WREG32(VM_CONTEXT0_CNTL, 0);
1065 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1066
1067 /* Setup L2 cache */
1068 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1069 EFFECTIVE_L2_QUEUE_SIZE(7));
1070 WREG32(VM_L2_CNTL2, 0);
1071 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1072 /* Setup TLB control */
1073 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1074 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1075 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1076 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1077 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1078 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1079 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1080 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1081 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1082}
1083
1084void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1085{
1086 evergreen_pcie_gart_disable(rdev);
1087 radeon_gart_table_vram_free(rdev);
1088 radeon_gart_fini(rdev);
1089}
1090
1091
1092void evergreen_agp_enable(struct radeon_device *rdev)
1093{
1094 u32 tmp;
bcc1c2a1
AD		 1095
1096 /* Setup L2 cache */
1097 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1098 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1099 EFFECTIVE_L2_QUEUE_SIZE(7));
1100 WREG32(VM_L2_CNTL2, 0);
1101 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1102 /* Setup TLB control */
1103 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1104 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1105 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1106 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1107 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1108 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1109 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1110 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1111 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1112 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1113 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1114 WREG32(VM_CONTEXT0_CNTL, 0);
1115 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1116}
1117
b9952a8a 1118void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1119{
1120 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1121 save->vga_control[1] = RREG32(D2VGA_CONTROL);
bcc1c2a1
AD		 1122 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1123 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1124 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1125 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 1126 if (rdev->num_crtc >= 4) {
1127 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1128 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
18007401
AD		 1129 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1130 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
b7eff394
AD		 1131 }
1132 if (rdev->num_crtc >= 6) {
1133 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1134 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
18007401
AD		 1135 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1136 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1137 }
bcc1c2a1
AD		 1138
1139 /* Stop all video */
1140 WREG32(VGA_RENDER_CONTROL, 0);
1141 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1142 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1143 if (rdev->num_crtc >= 4) {
18007401
AD		 1144 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1146 }
1147 if (rdev->num_crtc >= 6) {
18007401
AD		 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1150 }
bcc1c2a1
AD		 1151 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1152 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1153 if (rdev->num_crtc >= 4) {
18007401
AD		 1154 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1155 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1156 }
1157 if (rdev->num_crtc >= 6) {
18007401
AD		 1158 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1159 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1160 }
bcc1c2a1
AD		 1161 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1162 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1163 if (rdev->num_crtc >= 4) {
18007401
AD		 1164 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1165 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1166 }
1167 if (rdev->num_crtc >= 6) {
18007401
AD		 1168 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1169 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1170 }
bcc1c2a1
AD		 1171
1172 WREG32(D1VGA_CONTROL, 0);
1173 WREG32(D2VGA_CONTROL, 0);
b7eff394
AD		 1174 if (rdev->num_crtc >= 4) {
1175 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1176 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1177 }
1178 if (rdev->num_crtc >= 6) {
1179 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1180 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1181 }
bcc1c2a1
AD		 1182}
1183
b9952a8a 1184void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1185{
1186 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1187 upper_32_bits(rdev->mc.vram_start));
1188 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1189 upper_32_bits(rdev->mc.vram_start));
1190 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1191 (u32)rdev->mc.vram_start);
1192 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1193 (u32)rdev->mc.vram_start);
1194
1195 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1196 upper_32_bits(rdev->mc.vram_start));
1197 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1198 upper_32_bits(rdev->mc.vram_start));
1199 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1200 (u32)rdev->mc.vram_start);
1201 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1202 (u32)rdev->mc.vram_start);
1203
b7eff394 1204 if (rdev->num_crtc >= 4) {
18007401
AD		 1205 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1206 upper_32_bits(rdev->mc.vram_start));
1207 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1208 upper_32_bits(rdev->mc.vram_start));
1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1210 (u32)rdev->mc.vram_start);
1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1212 (u32)rdev->mc.vram_start);
1213
1214 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1215 upper_32_bits(rdev->mc.vram_start));
1216 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1217 upper_32_bits(rdev->mc.vram_start));
1218 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1219 (u32)rdev->mc.vram_start);
1220 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1221 (u32)rdev->mc.vram_start);
b7eff394
AD		 1222 }
1223 if (rdev->num_crtc >= 6) {
18007401
AD		 1224 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1225 upper_32_bits(rdev->mc.vram_start));
1226 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1227 upper_32_bits(rdev->mc.vram_start));
1228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1229 (u32)rdev->mc.vram_start);
1230 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1231 (u32)rdev->mc.vram_start);
1232
1233 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1234 upper_32_bits(rdev->mc.vram_start));
1235 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1236 upper_32_bits(rdev->mc.vram_start));
1237 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1238 (u32)rdev->mc.vram_start);
1239 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1240 (u32)rdev->mc.vram_start);
1241 }
bcc1c2a1
AD		 1242
1243 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1244 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1245 /* Unlock host access */
1246 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1247 mdelay(1);
1248 /* Restore video state */
1249 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1250 WREG32(D2VGA_CONTROL, save->vga_control[1]);
b7eff394
AD		 1251 if (rdev->num_crtc >= 4) {
1252 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1253 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1254 }
1255 if (rdev->num_crtc >= 6) {
1256 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1257 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1258 }
bcc1c2a1
AD		 1259 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1260 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1261 if (rdev->num_crtc >= 4) {
18007401
AD		 1262 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1263 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1264 }
1265 if (rdev->num_crtc >= 6) {
18007401
AD		 1266 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1267 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1268 }
bcc1c2a1
AD		 1269 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1270 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
b7eff394 1271 if (rdev->num_crtc >= 4) {
18007401
AD		 1272 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1273 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
b7eff394
AD		 1274 }
1275 if (rdev->num_crtc >= 6) {
18007401
AD		 1276 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1277 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1278 }
bcc1c2a1
AD		 1279 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1280 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1281 if (rdev->num_crtc >= 4) {
18007401
AD		 1282 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1283 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1284 }
1285 if (rdev->num_crtc >= 6) {
18007401
AD		 1286 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1287 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1288 }
bcc1c2a1
AD		 1289 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1290}
1291
755d819e 1292void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1293{
1294 struct evergreen_mc_save save;
1295 u32 tmp;
1296 int i, j;
1297
1298 /* Initialize HDP */
1299 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1300 WREG32((0x2c14 + j), 0x00000000);
1301 WREG32((0x2c18 + j), 0x00000000);
1302 WREG32((0x2c1c + j), 0x00000000);
1303 WREG32((0x2c20 + j), 0x00000000);
1304 WREG32((0x2c24 + j), 0x00000000);
1305 }
1306 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1307
1308 evergreen_mc_stop(rdev, &save);
1309 if (evergreen_mc_wait_for_idle(rdev)) {
1310 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1311 }
1312 /* Lockout access through VGA aperture*/
1313 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1314 /* Update configuration */
1315 if (rdev->flags & RADEON_IS_AGP) {
1316 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1317 /* VRAM before AGP */
1318 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1319 rdev->mc.vram_start >> 12);
1320 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1321 rdev->mc.gtt_end >> 12);
1322 } else {
1323 /* VRAM after AGP */
1324 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1325 rdev->mc.gtt_start >> 12);
1326 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1327 rdev->mc.vram_end >> 12);
1328 }
1329 } else {
1330 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1331 rdev->mc.vram_start >> 12);
1332 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1333 rdev->mc.vram_end >> 12);
1334 }
3b9832f6 1335 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 1336 /* llano/ontario only */
1337 if ((rdev->family == CHIP_PALM) ||
1338 (rdev->family == CHIP_SUMO) ||
1339 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 1340 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1341 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1342 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1343 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1344 }
bcc1c2a1
AD		 1345 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1346 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1347 WREG32(MC_VM_FB_LOCATION, tmp);
1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1349 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1350 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1351 if (rdev->flags & RADEON_IS_AGP) {
1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1355 } else {
1356 WREG32(MC_VM_AGP_BASE, 0);
1357 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1358 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1359 }
1360 if (evergreen_mc_wait_for_idle(rdev)) {
1361 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1362 }
1363 evergreen_mc_resume(rdev, &save);
1364 /* we need to own VRAM, so turn off the VGA renderer here
1365 * to stop it overwriting our objects */
1366 rv515_vga_render_disable(rdev);
1367}
1368
bcc1c2a1
AD		 1369/*
1370 * CP.
1371 */
12920591
AD		 1372void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1373{
e32eb50d 1374 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
7b1f2485 1375
12920591 1376 /* set to DX10/11 mode */
e32eb50d
CK		 1377 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1378 radeon_ring_write(ring, 1);
12920591 1379 /* FIXME: implement */
e32eb50d
CK		 1380 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1381 radeon_ring_write(ring,
0f234f5f
AD		 1382#ifdef __BIG_ENDIAN
1383 (2 << 0) |
1384#endif
1385 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1386 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1387 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1388}
1389
bcc1c2a1
AD		 1390
1391static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1392{
fe251e2f
AD		 1393 const __be32 *fw_data;
1394 int i;
1395
1396 if (!rdev->me_fw || !rdev->pfp_fw)
1397 return -EINVAL;
bcc1c2a1 1398
fe251e2f 1399 r700_cp_stop(rdev);
0f234f5f
AD		 1400 WREG32(CP_RB_CNTL,
1401#ifdef __BIG_ENDIAN
1402 BUF_SWAP_32BIT |
1403#endif
1404 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1405
1406 fw_data = (const __be32 *)rdev->pfp_fw->data;
1407 WREG32(CP_PFP_UCODE_ADDR, 0);
1408 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1409 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1410 WREG32(CP_PFP_UCODE_ADDR, 0);
1411
1412 fw_data = (const __be32 *)rdev->me_fw->data;
1413 WREG32(CP_ME_RAM_WADDR, 0);
1414 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1415 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1416
1417 WREG32(CP_PFP_UCODE_ADDR, 0);
1418 WREG32(CP_ME_RAM_WADDR, 0);
1419 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1420 return 0;
1421}
1422
7e7b41d2
AD		 1423static int evergreen_cp_start(struct radeon_device *rdev)
1424{
e32eb50d 1425 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1426 int r, i;
7e7b41d2
AD		 1427 uint32_t cp_me;
1428
e32eb50d 1429 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1430 if (r) {
1431 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1432 return r;
1433 }
e32eb50d
CK		 1434 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1435 radeon_ring_write(ring, 0x1);
1436 radeon_ring_write(ring, 0x0);
1437 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1438 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1439 radeon_ring_write(ring, 0);
1440 radeon_ring_write(ring, 0);
1441 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1442
1443 cp_me = 0xff;
1444 WREG32(CP_ME_CNTL, cp_me);
1445
e32eb50d 1446 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1447 if (r) {
1448 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1449 return r;
1450 }
2281a378
AD		 1451
1452 /* setup clear context state */
e32eb50d
CK		 1453 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1454 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1455
1456 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1457 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1458
e32eb50d
CK		 1459 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1460 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1461
1462 /* set clear context state */
e32eb50d
CK		 1463 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1464 radeon_ring_write(ring, 0);
2281a378
AD		 1465
1466 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1467 radeon_ring_write(ring, 0xc0026f00);
1468 radeon_ring_write(ring, 0x00000000);
1469 radeon_ring_write(ring, 0x00000000);
1470 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1471
1472 /* Clear consts */
e32eb50d
CK		 1473 radeon_ring_write(ring, 0xc0036f00);
1474 radeon_ring_write(ring, 0x00000bc4);
1475 radeon_ring_write(ring, 0xffffffff);
1476 radeon_ring_write(ring, 0xffffffff);
1477 radeon_ring_write(ring, 0xffffffff);
2281a378 1478
e32eb50d
CK		 1479 radeon_ring_write(ring, 0xc0026900);
1480 radeon_ring_write(ring, 0x00000316);
1481 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1482 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1483
e32eb50d 1484 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1485
1486 return 0;
1487}
1488
fe251e2f
AD		 1489int evergreen_cp_resume(struct radeon_device *rdev)
1490{
e32eb50d 1491 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1492 u32 tmp;
1493 u32 rb_bufsz;
1494 int r;
1495
1496 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1497 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1498 SOFT_RESET_PA |
1499 SOFT_RESET_SH |
1500 SOFT_RESET_VGT |
a49a50da 1501 SOFT_RESET_SPI |
fe251e2f
AD		 1502 SOFT_RESET_SX));
1503 RREG32(GRBM_SOFT_RESET);
1504 mdelay(15);
1505 WREG32(GRBM_SOFT_RESET, 0);
1506 RREG32(GRBM_SOFT_RESET);
1507
1508 /* Set ring buffer size */
e32eb50d 1509 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1510 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1511#ifdef __BIG_ENDIAN
1512 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1513#endif
fe251e2f 1514 WREG32(CP_RB_CNTL, tmp);
15d3332f 1515 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1516 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1517
1518 /* Set the write pointer delay */
1519 WREG32(CP_RB_WPTR_DELAY, 0);
1520
1521 /* Initialize the ring buffer's read and write pointers */
1522 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1523 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1524 ring->wptr = 0;
1525 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1526
1527 /* set the wb address wether it's enabled or not */
0f234f5f 1528 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1529 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1530 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1531 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1532
1533 if (rdev->wb.enabled)
1534 WREG32(SCRATCH_UMSK, 0xff);
1535 else {
1536 tmp |= RB_NO_UPDATE;
1537 WREG32(SCRATCH_UMSK, 0);
1538 }
1539
fe251e2f
AD		 1540 mdelay(1);
1541 WREG32(CP_RB_CNTL, tmp);
1542
e32eb50d 1543 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1544 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1545
e32eb50d 1546 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1547
7e7b41d2 1548 evergreen_cp_start(rdev);
e32eb50d 1549 ring->ready = true;
f712812e 1550 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 1551 if (r) {
e32eb50d 1552 ring->ready = false;
fe251e2f
AD		 1553 return r;
1554 }
1555 return 0;
1556}
bcc1c2a1
AD		 1557
1558/*
1559 * Core functions
1560 */
32fcdbf4
AD		 1561static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1562 u32 num_tile_pipes,
bcc1c2a1
AD		 1563 u32 num_backends,
1564 u32 backend_disable_mask)
1565{
1566 u32 backend_map = 0;
32fcdbf4
AD		 1567 u32 enabled_backends_mask = 0;
1568 u32 enabled_backends_count = 0;
1569 u32 cur_pipe;
1570 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1571 u32 cur_backend = 0;
1572 u32 i;
1573 bool force_no_swizzle;
1574
1575 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1576 num_tile_pipes = EVERGREEN_MAX_PIPES;
1577 if (num_tile_pipes < 1)
1578 num_tile_pipes = 1;
1579 if (num_backends > EVERGREEN_MAX_BACKENDS)
1580 num_backends = EVERGREEN_MAX_BACKENDS;
1581 if (num_backends < 1)
1582 num_backends = 1;
1583
1584 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1585 if (((backend_disable_mask >> i) & 1) == 0) {
1586 enabled_backends_mask |= (1 << i);
1587 ++enabled_backends_count;
1588 }
1589 if (enabled_backends_count == num_backends)
1590 break;
1591 }
1592
1593 if (enabled_backends_count == 0) {
1594 enabled_backends_mask = 1;
1595 enabled_backends_count = 1;
1596 }
1597
1598 if (enabled_backends_count != num_backends)
1599 num_backends = enabled_backends_count;
1600
1601 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1602 switch (rdev->family) {
1603 case CHIP_CEDAR:
1604 case CHIP_REDWOOD:
d5e455e4 1605 case CHIP_PALM:
d5c5a72f
AD		 1606 case CHIP_SUMO:
1607 case CHIP_SUMO2:
adb68fa2
AD		 1608 case CHIP_TURKS:
1609 case CHIP_CAICOS:
32fcdbf4
AD		 1610 force_no_swizzle = false;
1611 break;
1612 case CHIP_CYPRESS:
1613 case CHIP_HEMLOCK:
1614 case CHIP_JUNIPER:
adb68fa2 1615 case CHIP_BARTS:
32fcdbf4
AD		 1616 default:
1617 force_no_swizzle = true;
1618 break;
1619 }
1620 if (force_no_swizzle) {
1621 bool last_backend_enabled = false;
1622
1623 force_no_swizzle = false;
1624 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1625 if (((enabled_backends_mask >> i) & 1) == 1) {
1626 if (last_backend_enabled)
1627 force_no_swizzle = true;
1628 last_backend_enabled = true;
1629 } else
1630 last_backend_enabled = false;
1631 }
1632 }
1633
1634 switch (num_tile_pipes) {
1635 case 1:
1636 case 3:
1637 case 5:
1638 case 7:
1639 DRM_ERROR("odd number of pipes!\n");
1640 break;
1641 case 2:
1642 swizzle_pipe[0] = 0;
1643 swizzle_pipe[1] = 1;
1644 break;
1645 case 4:
1646 if (force_no_swizzle) {
1647 swizzle_pipe[0] = 0;
1648 swizzle_pipe[1] = 1;
1649 swizzle_pipe[2] = 2;
1650 swizzle_pipe[3] = 3;
1651 } else {
1652 swizzle_pipe[0] = 0;
1653 swizzle_pipe[1] = 2;
1654 swizzle_pipe[2] = 1;
1655 swizzle_pipe[3] = 3;
1656 }
1657 break;
1658 case 6:
1659 if (force_no_swizzle) {
1660 swizzle_pipe[0] = 0;
1661 swizzle_pipe[1] = 1;
1662 swizzle_pipe[2] = 2;
1663 swizzle_pipe[3] = 3;
1664 swizzle_pipe[4] = 4;
1665 swizzle_pipe[5] = 5;
1666 } else {
1667 swizzle_pipe[0] = 0;
1668 swizzle_pipe[1] = 2;
1669 swizzle_pipe[2] = 4;
1670 swizzle_pipe[3] = 1;
1671 swizzle_pipe[4] = 3;
1672 swizzle_pipe[5] = 5;
1673 }
1674 break;
1675 case 8:
1676 if (force_no_swizzle) {
1677 swizzle_pipe[0] = 0;
1678 swizzle_pipe[1] = 1;
1679 swizzle_pipe[2] = 2;
1680 swizzle_pipe[3] = 3;
1681 swizzle_pipe[4] = 4;
1682 swizzle_pipe[5] = 5;
1683 swizzle_pipe[6] = 6;
1684 swizzle_pipe[7] = 7;
1685 } else {
1686 swizzle_pipe[0] = 0;
1687 swizzle_pipe[1] = 2;
1688 swizzle_pipe[2] = 4;
1689 swizzle_pipe[3] = 6;
1690 swizzle_pipe[4] = 1;
1691 swizzle_pipe[5] = 3;
1692 swizzle_pipe[6] = 5;
1693 swizzle_pipe[7] = 7;
1694 }
1695 break;
1696 }
1697
1698 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1699 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1700 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1701
1702 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1703
1704 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1705 }
bcc1c2a1
AD		 1706
1707 return backend_map;
1708}
bcc1c2a1
AD		 1709
1710static void evergreen_gpu_init(struct radeon_device *rdev)
1711{
32fcdbf4
AD		 1712 u32 cc_rb_backend_disable = 0;
1713 u32 cc_gc_shader_pipe_config;
1714 u32 gb_addr_config = 0;
1715 u32 mc_shared_chmap, mc_arb_ramcfg;
1716 u32 gb_backend_map;
1717 u32 grbm_gfx_index;
1718 u32 sx_debug_1;
1719 u32 smx_dc_ctl0;
1720 u32 sq_config;
1721 u32 sq_lds_resource_mgmt;
1722 u32 sq_gpr_resource_mgmt_1;
1723 u32 sq_gpr_resource_mgmt_2;
1724 u32 sq_gpr_resource_mgmt_3;
1725 u32 sq_thread_resource_mgmt;
1726 u32 sq_thread_resource_mgmt_2;
1727 u32 sq_stack_resource_mgmt_1;
1728 u32 sq_stack_resource_mgmt_2;
1729 u32 sq_stack_resource_mgmt_3;
1730 u32 vgt_cache_invalidation;
f25a5c63 1731 u32 hdp_host_path_cntl, tmp;
32fcdbf4
AD		 1732 int i, j, num_shader_engines, ps_thread_count;
1733
1734 switch (rdev->family) {
1735 case CHIP_CYPRESS:
1736 case CHIP_HEMLOCK:
1737 rdev->config.evergreen.num_ses = 2;
1738 rdev->config.evergreen.max_pipes = 4;
1739 rdev->config.evergreen.max_tile_pipes = 8;
1740 rdev->config.evergreen.max_simds = 10;
1741 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1742 rdev->config.evergreen.max_gprs = 256;
1743 rdev->config.evergreen.max_threads = 248;
1744 rdev->config.evergreen.max_gs_threads = 32;
1745 rdev->config.evergreen.max_stack_entries = 512;
1746 rdev->config.evergreen.sx_num_of_sets = 4;
1747 rdev->config.evergreen.sx_max_export_size = 256;
1748 rdev->config.evergreen.sx_max_export_pos_size = 64;
1749 rdev->config.evergreen.sx_max_export_smx_size = 192;
1750 rdev->config.evergreen.max_hw_contexts = 8;
1751 rdev->config.evergreen.sq_num_cf_insts = 2;
1752
1753 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1754 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1755 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1756 break;
1757 case CHIP_JUNIPER:
1758 rdev->config.evergreen.num_ses = 1;
1759 rdev->config.evergreen.max_pipes = 4;
1760 rdev->config.evergreen.max_tile_pipes = 4;
1761 rdev->config.evergreen.max_simds = 10;
1762 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1763 rdev->config.evergreen.max_gprs = 256;
1764 rdev->config.evergreen.max_threads = 248;
1765 rdev->config.evergreen.max_gs_threads = 32;
1766 rdev->config.evergreen.max_stack_entries = 512;
1767 rdev->config.evergreen.sx_num_of_sets = 4;
1768 rdev->config.evergreen.sx_max_export_size = 256;
1769 rdev->config.evergreen.sx_max_export_pos_size = 64;
1770 rdev->config.evergreen.sx_max_export_smx_size = 192;
1771 rdev->config.evergreen.max_hw_contexts = 8;
1772 rdev->config.evergreen.sq_num_cf_insts = 2;
1773
1774 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1775 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1776 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1777 break;
1778 case CHIP_REDWOOD:
1779 rdev->config.evergreen.num_ses = 1;
1780 rdev->config.evergreen.max_pipes = 4;
1781 rdev->config.evergreen.max_tile_pipes = 4;
1782 rdev->config.evergreen.max_simds = 5;
1783 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1784 rdev->config.evergreen.max_gprs = 256;
1785 rdev->config.evergreen.max_threads = 248;
1786 rdev->config.evergreen.max_gs_threads = 32;
1787 rdev->config.evergreen.max_stack_entries = 256;
1788 rdev->config.evergreen.sx_num_of_sets = 4;
1789 rdev->config.evergreen.sx_max_export_size = 256;
1790 rdev->config.evergreen.sx_max_export_pos_size = 64;
1791 rdev->config.evergreen.sx_max_export_smx_size = 192;
1792 rdev->config.evergreen.max_hw_contexts = 8;
1793 rdev->config.evergreen.sq_num_cf_insts = 2;
1794
1795 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1796 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1797 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1798 break;
1799 case CHIP_CEDAR:
1800 default:
1801 rdev->config.evergreen.num_ses = 1;
1802 rdev->config.evergreen.max_pipes = 2;
1803 rdev->config.evergreen.max_tile_pipes = 2;
1804 rdev->config.evergreen.max_simds = 2;
1805 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1806 rdev->config.evergreen.max_gprs = 256;
1807 rdev->config.evergreen.max_threads = 192;
1808 rdev->config.evergreen.max_gs_threads = 16;
1809 rdev->config.evergreen.max_stack_entries = 256;
1810 rdev->config.evergreen.sx_num_of_sets = 4;
1811 rdev->config.evergreen.sx_max_export_size = 128;
1812 rdev->config.evergreen.sx_max_export_pos_size = 32;
1813 rdev->config.evergreen.sx_max_export_smx_size = 96;
1814 rdev->config.evergreen.max_hw_contexts = 4;
1815 rdev->config.evergreen.sq_num_cf_insts = 1;
1816
d5e455e4
AD		 1817 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1818 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1819 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1820 break;
1821 case CHIP_PALM:
1822 rdev->config.evergreen.num_ses = 1;
1823 rdev->config.evergreen.max_pipes = 2;
1824 rdev->config.evergreen.max_tile_pipes = 2;
1825 rdev->config.evergreen.max_simds = 2;
1826 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1827 rdev->config.evergreen.max_gprs = 256;
1828 rdev->config.evergreen.max_threads = 192;
1829 rdev->config.evergreen.max_gs_threads = 16;
1830 rdev->config.evergreen.max_stack_entries = 256;
1831 rdev->config.evergreen.sx_num_of_sets = 4;
1832 rdev->config.evergreen.sx_max_export_size = 128;
1833 rdev->config.evergreen.sx_max_export_pos_size = 32;
1834 rdev->config.evergreen.sx_max_export_smx_size = 96;
1835 rdev->config.evergreen.max_hw_contexts = 4;
1836 rdev->config.evergreen.sq_num_cf_insts = 1;
1837
d5c5a72f
AD		 1838 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1839 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1840 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1841 break;
1842 case CHIP_SUMO:
1843 rdev->config.evergreen.num_ses = 1;
1844 rdev->config.evergreen.max_pipes = 4;
1845 rdev->config.evergreen.max_tile_pipes = 2;
1846 if (rdev->pdev->device == 0x9648)
1847 rdev->config.evergreen.max_simds = 3;
1848 else if ((rdev->pdev->device == 0x9647) ||
1849 (rdev->pdev->device == 0x964a))
1850 rdev->config.evergreen.max_simds = 4;
1851 else
1852 rdev->config.evergreen.max_simds = 5;
1853 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1854 rdev->config.evergreen.max_gprs = 256;
1855 rdev->config.evergreen.max_threads = 248;
1856 rdev->config.evergreen.max_gs_threads = 32;
1857 rdev->config.evergreen.max_stack_entries = 256;
1858 rdev->config.evergreen.sx_num_of_sets = 4;
1859 rdev->config.evergreen.sx_max_export_size = 256;
1860 rdev->config.evergreen.sx_max_export_pos_size = 64;
1861 rdev->config.evergreen.sx_max_export_smx_size = 192;
1862 rdev->config.evergreen.max_hw_contexts = 8;
1863 rdev->config.evergreen.sq_num_cf_insts = 2;
1864
1865 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1866 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1867 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1868 break;
1869 case CHIP_SUMO2:
1870 rdev->config.evergreen.num_ses = 1;
1871 rdev->config.evergreen.max_pipes = 4;
1872 rdev->config.evergreen.max_tile_pipes = 4;
1873 rdev->config.evergreen.max_simds = 2;
1874 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1875 rdev->config.evergreen.max_gprs = 256;
1876 rdev->config.evergreen.max_threads = 248;
1877 rdev->config.evergreen.max_gs_threads = 32;
1878 rdev->config.evergreen.max_stack_entries = 512;
1879 rdev->config.evergreen.sx_num_of_sets = 4;
1880 rdev->config.evergreen.sx_max_export_size = 256;
1881 rdev->config.evergreen.sx_max_export_pos_size = 64;
1882 rdev->config.evergreen.sx_max_export_smx_size = 192;
1883 rdev->config.evergreen.max_hw_contexts = 8;
1884 rdev->config.evergreen.sq_num_cf_insts = 2;
1885
adb68fa2
AD		 1886 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1887 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1888 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1889 break;
1890 case CHIP_BARTS:
1891 rdev->config.evergreen.num_ses = 2;
1892 rdev->config.evergreen.max_pipes = 4;
1893 rdev->config.evergreen.max_tile_pipes = 8;
1894 rdev->config.evergreen.max_simds = 7;
1895 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1896 rdev->config.evergreen.max_gprs = 256;
1897 rdev->config.evergreen.max_threads = 248;
1898 rdev->config.evergreen.max_gs_threads = 32;
1899 rdev->config.evergreen.max_stack_entries = 512;
1900 rdev->config.evergreen.sx_num_of_sets = 4;
1901 rdev->config.evergreen.sx_max_export_size = 256;
1902 rdev->config.evergreen.sx_max_export_pos_size = 64;
1903 rdev->config.evergreen.sx_max_export_smx_size = 192;
1904 rdev->config.evergreen.max_hw_contexts = 8;
1905 rdev->config.evergreen.sq_num_cf_insts = 2;
1906
1907 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1908 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1909 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1910 break;
1911 case CHIP_TURKS:
1912 rdev->config.evergreen.num_ses = 1;
1913 rdev->config.evergreen.max_pipes = 4;
1914 rdev->config.evergreen.max_tile_pipes = 4;
1915 rdev->config.evergreen.max_simds = 6;
1916 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1917 rdev->config.evergreen.max_gprs = 256;
1918 rdev->config.evergreen.max_threads = 248;
1919 rdev->config.evergreen.max_gs_threads = 32;
1920 rdev->config.evergreen.max_stack_entries = 256;
1921 rdev->config.evergreen.sx_num_of_sets = 4;
1922 rdev->config.evergreen.sx_max_export_size = 256;
1923 rdev->config.evergreen.sx_max_export_pos_size = 64;
1924 rdev->config.evergreen.sx_max_export_smx_size = 192;
1925 rdev->config.evergreen.max_hw_contexts = 8;
1926 rdev->config.evergreen.sq_num_cf_insts = 2;
1927
1928 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1929 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1930 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1931 break;
1932 case CHIP_CAICOS:
1933 rdev->config.evergreen.num_ses = 1;
1934 rdev->config.evergreen.max_pipes = 4;
1935 rdev->config.evergreen.max_tile_pipes = 2;
1936 rdev->config.evergreen.max_simds = 2;
1937 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1938 rdev->config.evergreen.max_gprs = 256;
1939 rdev->config.evergreen.max_threads = 192;
1940 rdev->config.evergreen.max_gs_threads = 16;
1941 rdev->config.evergreen.max_stack_entries = 256;
1942 rdev->config.evergreen.sx_num_of_sets = 4;
1943 rdev->config.evergreen.sx_max_export_size = 128;
1944 rdev->config.evergreen.sx_max_export_pos_size = 32;
1945 rdev->config.evergreen.sx_max_export_smx_size = 96;
1946 rdev->config.evergreen.max_hw_contexts = 4;
1947 rdev->config.evergreen.sq_num_cf_insts = 1;
1948
32fcdbf4
AD		 1949 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1950 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1951 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1952 break;
1953 }
1954
1955 /* Initialize HDP */
1956 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1957 WREG32((0x2c14 + j), 0x00000000);
1958 WREG32((0x2c18 + j), 0x00000000);
1959 WREG32((0x2c1c + j), 0x00000000);
1960 WREG32((0x2c20 + j), 0x00000000);
1961 WREG32((0x2c24 + j), 0x00000000);
1962 }
1963
1964 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1965
d054ac16
AD		 1966 evergreen_fix_pci_max_read_req_size(rdev);
1967
32fcdbf4
AD		 1968 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1969
1970 cc_gc_shader_pipe_config |=
1971 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1972 & EVERGREEN_MAX_PIPES_MASK);
1973 cc_gc_shader_pipe_config |=
1974 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1975 & EVERGREEN_MAX_SIMDS_MASK);
1976
1977 cc_rb_backend_disable =
1978 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1979 & EVERGREEN_MAX_BACKENDS_MASK);
1980
1981
1982 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 1983 if ((rdev->family == CHIP_PALM) ||
1984 (rdev->family == CHIP_SUMO) ||
1985 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 1986 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1987 else
1988 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4
AD		 1989
1990 switch (rdev->config.evergreen.max_tile_pipes) {
1991 case 1:
1992 default:
1993 gb_addr_config |= NUM_PIPES(0);
1994 break;
1995 case 2:
1996 gb_addr_config |= NUM_PIPES(1);
1997 break;
1998 case 4:
1999 gb_addr_config |= NUM_PIPES(2);
2000 break;
2001 case 8:
2002 gb_addr_config |= NUM_PIPES(3);
2003 break;
2004 }
2005
2006 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
2007 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
2008 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
2009 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
2010 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
2011 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
2012
2013 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
2014 gb_addr_config |= ROW_SIZE(2);
2015 else
2016 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
2017
2018 if (rdev->ddev->pdev->device == 0x689e) {
2019 u32 efuse_straps_4;
2020 u32 efuse_straps_3;
2021 u8 efuse_box_bit_131_124;
2022
2023 WREG32(RCU_IND_INDEX, 0x204);
2024 efuse_straps_4 = RREG32(RCU_IND_DATA);
2025 WREG32(RCU_IND_INDEX, 0x203);
2026 efuse_straps_3 = RREG32(RCU_IND_DATA);
2027 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
2028
2029 switch(efuse_box_bit_131_124) {
2030 case 0x00:
2031 gb_backend_map = 0x76543210;
2032 break;
2033 case 0x55:
2034 gb_backend_map = 0x77553311;
2035 break;
2036 case 0x56:
2037 gb_backend_map = 0x77553300;
2038 break;
2039 case 0x59:
2040 gb_backend_map = 0x77552211;
2041 break;
2042 case 0x66:
2043 gb_backend_map = 0x77443300;
2044 break;
2045 case 0x99:
2046 gb_backend_map = 0x66552211;
2047 break;
2048 case 0x5a:
2049 gb_backend_map = 0x77552200;
2050 break;
2051 case 0xaa:
2052 gb_backend_map = 0x66442200;
2053 break;
2054 case 0x95:
2055 gb_backend_map = 0x66553311;
2056 break;
2057 default:
2058 DRM_ERROR("bad backend map, using default\n");
2059 gb_backend_map =
2060 evergreen_get_tile_pipe_to_backend_map(rdev,
2061 rdev->config.evergreen.max_tile_pipes,
2062 rdev->config.evergreen.max_backends,
2063 ((EVERGREEN_MAX_BACKENDS_MASK <<
2064 rdev->config.evergreen.max_backends) &
2065 EVERGREEN_MAX_BACKENDS_MASK));
2066 break;
2067 }
2068 } else if (rdev->ddev->pdev->device == 0x68b9) {
2069 u32 efuse_straps_3;
2070 u8 efuse_box_bit_127_124;
2071
2072 WREG32(RCU_IND_INDEX, 0x203);
2073 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 2074 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 2075
2076 switch(efuse_box_bit_127_124) {
2077 case 0x0:
2078 gb_backend_map = 0x00003210;
2079 break;
2080 case 0x5:
2081 case 0x6:
2082 case 0x9:
2083 case 0xa:
2084 gb_backend_map = 0x00003311;
2085 break;
2086 default:
2087 DRM_ERROR("bad backend map, using default\n");
2088 gb_backend_map =
2089 evergreen_get_tile_pipe_to_backend_map(rdev,
2090 rdev->config.evergreen.max_tile_pipes,
2091 rdev->config.evergreen.max_backends,
2092 ((EVERGREEN_MAX_BACKENDS_MASK <<
2093 rdev->config.evergreen.max_backends) &
2094 EVERGREEN_MAX_BACKENDS_MASK));
2095 break;
2096 }
b741be82
AD		 2097 } else {
2098 switch (rdev->family) {
2099 case CHIP_CYPRESS:
2100 case CHIP_HEMLOCK:
03f40090 2101 case CHIP_BARTS:
b741be82
AD		 2102 gb_backend_map = 0x66442200;
2103 break;
2104 case CHIP_JUNIPER:
9a4a0b9c 2105 gb_backend_map = 0x00002200;
b741be82
AD		 2106 break;
2107 default:
2108 gb_backend_map =
2109 evergreen_get_tile_pipe_to_backend_map(rdev,
2110 rdev->config.evergreen.max_tile_pipes,
2111 rdev->config.evergreen.max_backends,
2112 ((EVERGREEN_MAX_BACKENDS_MASK <<
2113 rdev->config.evergreen.max_backends) &
2114 EVERGREEN_MAX_BACKENDS_MASK));
2115 }
2116 }
32fcdbf4 2117
1aa52bd3
AD		 2118 /* setup tiling info dword. gb_addr_config is not adequate since it does
2119 * not have bank info, so create a custom tiling dword.
2120 * bits 3:0 num_pipes
2121 * bits 7:4 num_banks
2122 * bits 11:8 group_size
2123 * bits 15:12 row_size
2124 */
2125 rdev->config.evergreen.tile_config = 0;
2126 switch (rdev->config.evergreen.max_tile_pipes) {
2127 case 1:
2128 default:
2129 rdev->config.evergreen.tile_config |= (0 << 0);
2130 break;
2131 case 2:
2132 rdev->config.evergreen.tile_config |= (1 << 0);
2133 break;
2134 case 4:
2135 rdev->config.evergreen.tile_config |= (2 << 0);
2136 break;
2137 case 8:
2138 rdev->config.evergreen.tile_config |= (3 << 0);
2139 break;
2140 }
d698a34d 2141 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 2142 if (rdev->flags & RADEON_IS_IGP)
d698a34d 2143 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406
AD		 2144 else {
2145 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
2146 rdev->config.evergreen.tile_config |= 1 << 4;
2147 else
2148 rdev->config.evergreen.tile_config |= 0 << 4;
2149 }
1aa52bd3
AD		 2150 rdev->config.evergreen.tile_config |=
2151 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2152 rdev->config.evergreen.tile_config |=
2153 ((gb_addr_config & 0x30000000) >> 28) << 12;
2154
e55b9422 2155 rdev->config.evergreen.backend_map = gb_backend_map;
32fcdbf4
AD		 2156 WREG32(GB_BACKEND_MAP, gb_backend_map);
2157 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2158 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2159 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2160
2161 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2162 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2163
2164 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2165 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2166 u32 sp = cc_gc_shader_pipe_config;
2167 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2168
2169 if (i == num_shader_engines) {
2170 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2171 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2172 }
2173
2174 WREG32(GRBM_GFX_INDEX, gfx);
2175 WREG32(RLC_GFX_INDEX, gfx);
2176
2177 WREG32(CC_RB_BACKEND_DISABLE, rb);
2178 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2179 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2180 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
95c4b23e 2181 }
32fcdbf4 2182
95c4b23e 2183 grbm_gfx_index = INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES;
32fcdbf4
AD		 2184 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2185 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2186
2187 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2188 WREG32(CGTS_TCC_DISABLE, 0);
2189 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2190 WREG32(CGTS_USER_TCC_DISABLE, 0);
2191
2192 /* set HW defaults for 3D engine */
2193 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2194 ROQ_IB2_START(0x2b)));
2195
2196 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2197
2198 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2199 SYNC_GRADIENT |
2200 SYNC_WALKER |
2201 SYNC_ALIGNER));
2202
2203 sx_debug_1 = RREG32(SX_DEBUG_1);
2204 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2205 WREG32(SX_DEBUG_1, sx_debug_1);
2206
2207
2208 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2209 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2210 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2211 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2212
2213 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2214 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2215 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2216
2217 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2218 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2219 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2220
2221 WREG32(VGT_NUM_INSTANCES, 1);
2222 WREG32(SPI_CONFIG_CNTL, 0);
2223 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2224 WREG32(CP_PERFMON_CNTL, 0);
2225
2226 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2227 FETCH_FIFO_HIWATER(0x4) |
2228 DONE_FIFO_HIWATER(0xe0) |
2229 ALU_UPDATE_FIFO_HIWATER(0x8)));
2230
2231 sq_config = RREG32(SQ_CONFIG);
2232 sq_config &= ~(PS_PRIO(3) |
2233 VS_PRIO(3) |
2234 GS_PRIO(3) |
2235 ES_PRIO(3));
2236 sq_config |= (VC_ENABLE |
2237 EXPORT_SRC_C |
2238 PS_PRIO(0) |
2239 VS_PRIO(1) |
2240 GS_PRIO(2) |
2241 ES_PRIO(3));
2242
d5e455e4
AD		 2243 switch (rdev->family) {
2244 case CHIP_CEDAR:
2245 case CHIP_PALM:
d5c5a72f
AD		 2246 case CHIP_SUMO:
2247 case CHIP_SUMO2:
adb68fa2 2248 case CHIP_CAICOS:
32fcdbf4
AD		 2249 /* no vertex cache */
2250 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2251 break;
2252 default:
2253 break;
2254 }
32fcdbf4
AD		 2255
2256 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2257
2258 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2259 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2260 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2261 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2262 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2263 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2264 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2265
d5e455e4
AD		 2266 switch (rdev->family) {
2267 case CHIP_CEDAR:
2268 case CHIP_PALM:
d5c5a72f
AD		 2269 case CHIP_SUMO:
2270 case CHIP_SUMO2:
32fcdbf4 2271 ps_thread_count = 96;
d5e455e4
AD		 2272 break;
2273 default:
32fcdbf4 2274 ps_thread_count = 128;
d5e455e4
AD		 2275 break;
2276 }
32fcdbf4
AD		 2277
2278 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2279 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2280 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2281 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2282 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2283 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2284
2285 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2286 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2287 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2288 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2289 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2290 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2291
2292 WREG32(SQ_CONFIG, sq_config);
2293 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2294 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2295 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2296 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2297 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2298 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2299 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2300 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2301 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2302 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2303
2304 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2305 FORCE_EOV_MAX_REZ_CNT(255)));
2306
d5e455e4
AD		 2307 switch (rdev->family) {
2308 case CHIP_CEDAR:
2309 case CHIP_PALM:
d5c5a72f
AD		 2310 case CHIP_SUMO:
2311 case CHIP_SUMO2:
adb68fa2 2312 case CHIP_CAICOS:
32fcdbf4 2313 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2314 break;
2315 default:
32fcdbf4 2316 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2317 break;
2318 }
32fcdbf4
AD		 2319 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2320 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2321
2322 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2323 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2324 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2325
60a4a3e0
AD		 2326 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2327 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2328
32fcdbf4
AD		 2329 WREG32(CB_PERF_CTR0_SEL_0, 0);
2330 WREG32(CB_PERF_CTR0_SEL_1, 0);
2331 WREG32(CB_PERF_CTR1_SEL_0, 0);
2332 WREG32(CB_PERF_CTR1_SEL_1, 0);
2333 WREG32(CB_PERF_CTR2_SEL_0, 0);
2334 WREG32(CB_PERF_CTR2_SEL_1, 0);
2335 WREG32(CB_PERF_CTR3_SEL_0, 0);
2336 WREG32(CB_PERF_CTR3_SEL_1, 0);
2337
60a4a3e0
AD		 2338 /* clear render buffer base addresses */
2339 WREG32(CB_COLOR0_BASE, 0);
2340 WREG32(CB_COLOR1_BASE, 0);
2341 WREG32(CB_COLOR2_BASE, 0);
2342 WREG32(CB_COLOR3_BASE, 0);
2343 WREG32(CB_COLOR4_BASE, 0);
2344 WREG32(CB_COLOR5_BASE, 0);
2345 WREG32(CB_COLOR6_BASE, 0);
2346 WREG32(CB_COLOR7_BASE, 0);
2347 WREG32(CB_COLOR8_BASE, 0);
2348 WREG32(CB_COLOR9_BASE, 0);
2349 WREG32(CB_COLOR10_BASE, 0);
2350 WREG32(CB_COLOR11_BASE, 0);
2351
2352 /* set the shader const cache sizes to 0 */
2353 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2354 WREG32(i, 0);
2355 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2356 WREG32(i, 0);
2357
f25a5c63
AD		 2358 tmp = RREG32(HDP_MISC_CNTL);
2359 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2360 WREG32(HDP_MISC_CNTL, tmp);
2361
32fcdbf4
AD		 2362 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2363 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2364
2365 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2366
2367 udelay(50);
2368
bcc1c2a1
AD		 2369}
2370
2371int evergreen_mc_init(struct radeon_device *rdev)
2372{
bcc1c2a1
AD		 2373 u32 tmp;
2374 int chansize, numchan;
bcc1c2a1
AD		 2375
2376 /* Get VRAM informations */
2377 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 2378 if ((rdev->family == CHIP_PALM) ||
2379 (rdev->family == CHIP_SUMO) ||
2380 (rdev->family == CHIP_SUMO2))
8208441b
AD		 2381 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2382 else
2383 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2384 if (tmp & CHANSIZE_OVERRIDE) {
2385 chansize = 16;
2386 } else if (tmp & CHANSIZE_MASK) {
2387 chansize = 64;
2388 } else {
2389 chansize = 32;
2390 }
2391 tmp = RREG32(MC_SHARED_CHMAP);
2392 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2393 case 0:
2394 default:
2395 numchan = 1;
2396 break;
2397 case 1:
2398 numchan = 2;
2399 break;
2400 case 2:
2401 numchan = 4;
2402 break;
2403 case 3:
2404 numchan = 8;
2405 break;
2406 }
2407 rdev->mc.vram_width = numchan * chansize;
2408 /* Could aper size report 0 ? */
01d73a69
JC		 2409 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2410 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2411 /* Setup GPU memory space */
05b3ef69
AD		 2412 if ((rdev->family == CHIP_PALM) ||
2413 (rdev->family == CHIP_SUMO) ||
2414 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 2415 /* size in bytes on fusion */
2416 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2417 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2418 } else {
05b3ef69 2419 /* size in MB on evergreen/cayman/tn */
6eb18f8b
AD		 2420 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2421 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2422 }
51e5fcd3 2423 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2424 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2425 radeon_update_bandwidth_info(rdev);
2426
bcc1c2a1
AD		 2427 return 0;
2428}
d594e46a 2429
e32eb50d 2430bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 2431{
17db7042
AD		 2432 u32 srbm_status;
2433 u32 grbm_status;
2434 u32 grbm_status_se0, grbm_status_se1;
17db7042
AD		 2435
2436 srbm_status = RREG32(SRBM_STATUS);
2437 grbm_status = RREG32(GRBM_STATUS);
2438 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2439 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2440 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2441 radeon_ring_lockup_update(ring);
17db7042
AD		 2442 return false;
2443 }
2444 /* force CP activities */
7b9ef16b 2445 radeon_ring_force_activity(rdev, ring);
069211e5 2446 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 2447}
2448
747943ea 2449static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2450{
747943ea 2451 struct evergreen_mc_save save;
747943ea
AD		 2452 u32 grbm_reset = 0;
2453
8d96fe93
AD		 2454 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2455 return 0;
2456
747943ea
AD		 2457 dev_info(rdev->dev, "GPU softreset \n");
2458 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2459 RREG32(GRBM_STATUS));
2460 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2461 RREG32(GRBM_STATUS_SE0));
2462 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2463 RREG32(GRBM_STATUS_SE1));
2464 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2465 RREG32(SRBM_STATUS));
2466 evergreen_mc_stop(rdev, &save);
2467 if (evergreen_mc_wait_for_idle(rdev)) {
2468 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2469 }
2470 /* Disable CP parsing/prefetching */
2471 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2472
2473 /* reset all the gfx blocks */
2474 grbm_reset = (SOFT_RESET_CP |
2475 SOFT_RESET_CB |
2476 SOFT_RESET_DB |
2477 SOFT_RESET_PA |
2478 SOFT_RESET_SC |
2479 SOFT_RESET_SPI |
2480 SOFT_RESET_SH |
2481 SOFT_RESET_SX |
2482 SOFT_RESET_TC |
2483 SOFT_RESET_TA |
2484 SOFT_RESET_VC |
2485 SOFT_RESET_VGT);
2486
2487 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2488 WREG32(GRBM_SOFT_RESET, grbm_reset);
2489 (void)RREG32(GRBM_SOFT_RESET);
2490 udelay(50);
2491 WREG32(GRBM_SOFT_RESET, 0);
2492 (void)RREG32(GRBM_SOFT_RESET);
747943ea
AD		 2493 /* Wait a little for things to settle down */
2494 udelay(50);
2495 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2496 RREG32(GRBM_STATUS));
2497 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2498 RREG32(GRBM_STATUS_SE0));
2499 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2500 RREG32(GRBM_STATUS_SE1));
2501 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2502 RREG32(SRBM_STATUS));
747943ea 2503 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2504 return 0;
2505}
2506
a2d07b74 2507int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2508{
747943ea
AD		 2509 return evergreen_gpu_soft_reset(rdev);
2510}
2511
45f9a39b
AD		 2512/* Interrupts */
2513
2514u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2515{
2516 switch (crtc) {
2517 case 0:
2518 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2519 case 1:
2520 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2521 case 2:
2522 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2523 case 3:
2524 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2525 case 4:
2526 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2527 case 5:
2528 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2529 default:
2530 return 0;
2531 }
2532}
2533
2534void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2535{
2536 u32 tmp;
2537
1b37078b
AD		 2538 if (rdev->family >= CHIP_CAYMAN) {
2539 cayman_cp_int_cntl_setup(rdev, 0,
2540 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2541 cayman_cp_int_cntl_setup(rdev, 1, 0);
2542 cayman_cp_int_cntl_setup(rdev, 2, 0);
2543 } else
2544 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2545 WREG32(GRBM_INT_CNTL, 0);
2546 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2547 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2548 if (rdev->num_crtc >= 4) {
18007401
AD		 2549 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2550 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2551 }
2552 if (rdev->num_crtc >= 6) {
18007401
AD		 2553 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2554 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2555 }
45f9a39b
AD		 2556
2557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2558 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2559 if (rdev->num_crtc >= 4) {
18007401
AD		 2560 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2561 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2562 }
2563 if (rdev->num_crtc >= 6) {
18007401
AD		 2564 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2565 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2566 }
45f9a39b 2567
05b3ef69
AD		 2568 /* only one DAC on DCE6 */
2569 if (!ASIC_IS_DCE6(rdev))
2570 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 2571 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2572
2573 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2574 WREG32(DC_HPD1_INT_CONTROL, tmp);
2575 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2576 WREG32(DC_HPD2_INT_CONTROL, tmp);
2577 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2578 WREG32(DC_HPD3_INT_CONTROL, tmp);
2579 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2580 WREG32(DC_HPD4_INT_CONTROL, tmp);
2581 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2582 WREG32(DC_HPD5_INT_CONTROL, tmp);
2583 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2584 WREG32(DC_HPD6_INT_CONTROL, tmp);
2585
2586}
2587
2588int evergreen_irq_set(struct radeon_device *rdev)
2589{
2590 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2591 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2592 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2593 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2594 u32 grbm_int_cntl = 0;
6f34be50 2595 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 2596 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
45f9a39b
AD		 2597
2598 if (!rdev->irq.installed) {
fce7d61b 2599 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2600 return -EINVAL;
2601 }
2602 /* don't enable anything if the ih is disabled */
2603 if (!rdev->ih.enabled) {
2604 r600_disable_interrupts(rdev);
2605 /* force the active interrupt state to all disabled */
2606 evergreen_disable_interrupt_state(rdev);
2607 return 0;
2608 }
2609
2610 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2611 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2612 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2613 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2614 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2615 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2616
f122c610
AD		 2617 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2618 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2619 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2620 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2621 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2622 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2623
1b37078b
AD		 2624 if (rdev->family >= CHIP_CAYMAN) {
2625 /* enable CP interrupts on all rings */
2626 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2627 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2628 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2629 }
2630 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2631 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2632 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2633 }
2634 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2635 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2636 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2637 }
2638 } else {
2639 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2640 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2641 cp_int_cntl |= RB_INT_ENABLE;
2642 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2643 }
45f9a39b 2644 }
1b37078b 2645
6f34be50
AD		 2646 if (rdev->irq.crtc_vblank_int[0] ||
2647 rdev->irq.pflip[0]) {
45f9a39b
AD		 2648 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2649 crtc1 |= VBLANK_INT_MASK;
2650 }
6f34be50
AD		 2651 if (rdev->irq.crtc_vblank_int[1] ||
2652 rdev->irq.pflip[1]) {
45f9a39b
AD		 2653 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2654 crtc2 |= VBLANK_INT_MASK;
2655 }
6f34be50
AD		 2656 if (rdev->irq.crtc_vblank_int[2] ||
2657 rdev->irq.pflip[2]) {
45f9a39b
AD		 2658 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2659 crtc3 |= VBLANK_INT_MASK;
2660 }
6f34be50
AD		 2661 if (rdev->irq.crtc_vblank_int[3] ||
2662 rdev->irq.pflip[3]) {
45f9a39b
AD		 2663 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2664 crtc4 |= VBLANK_INT_MASK;
2665 }
6f34be50
AD		 2666 if (rdev->irq.crtc_vblank_int[4] ||
2667 rdev->irq.pflip[4]) {
45f9a39b
AD		 2668 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2669 crtc5 |= VBLANK_INT_MASK;
2670 }
6f34be50
AD		 2671 if (rdev->irq.crtc_vblank_int[5] ||
2672 rdev->irq.pflip[5]) {
45f9a39b
AD		 2673 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2674 crtc6 |= VBLANK_INT_MASK;
2675 }
2676 if (rdev->irq.hpd[0]) {
2677 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2678 hpd1 |= DC_HPDx_INT_EN;
2679 }
2680 if (rdev->irq.hpd[1]) {
2681 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2682 hpd2 |= DC_HPDx_INT_EN;
2683 }
2684 if (rdev->irq.hpd[2]) {
2685 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2686 hpd3 |= DC_HPDx_INT_EN;
2687 }
2688 if (rdev->irq.hpd[3]) {
2689 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2690 hpd4 |= DC_HPDx_INT_EN;
2691 }
2692 if (rdev->irq.hpd[4]) {
2693 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2694 hpd5 |= DC_HPDx_INT_EN;
2695 }
2696 if (rdev->irq.hpd[5]) {
2697 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2698 hpd6 |= DC_HPDx_INT_EN;
2699 }
f122c610
AD		 2700 if (rdev->irq.afmt[0]) {
2701 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2702 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2703 }
2704 if (rdev->irq.afmt[1]) {
2705 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2706 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2707 }
2708 if (rdev->irq.afmt[2]) {
2709 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2710 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2711 }
2712 if (rdev->irq.afmt[3]) {
2713 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2714 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2715 }
2716 if (rdev->irq.afmt[4]) {
2717 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2718 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2719 }
2720 if (rdev->irq.afmt[5]) {
2721 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2722 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2723 }
2031f77c
AD		 2724 if (rdev->irq.gui_idle) {
2725 DRM_DEBUG("gui idle\n");
2726 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2727 }
45f9a39b 2728
1b37078b
AD		 2729 if (rdev->family >= CHIP_CAYMAN) {
2730 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2731 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2732 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2733 } else
2734 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2735 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2736
2737 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2738 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2739 if (rdev->num_crtc >= 4) {
18007401
AD		 2740 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2741 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2742 }
2743 if (rdev->num_crtc >= 6) {
18007401
AD		 2744 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2745 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2746 }
45f9a39b 2747
6f34be50
AD		 2748 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2749 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2750 if (rdev->num_crtc >= 4) {
2751 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2752 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2753 }
2754 if (rdev->num_crtc >= 6) {
2755 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2756 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2757 }
6f34be50 2758
45f9a39b
AD		 2759 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2760 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2761 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2762 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2763 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2764 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2765
f122c610
AD		 2766 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2767 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2768 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2769 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2770 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2771 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2772
bcc1c2a1
AD		 2773 return 0;
2774}
2775
cbdd4501 2776static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2777{
2778 u32 tmp;
2779
6f34be50
AD		 2780 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2781 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2782 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2783 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2784 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2785 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2786 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2787 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2788 if (rdev->num_crtc >= 4) {
2789 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2790 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2791 }
2792 if (rdev->num_crtc >= 6) {
2793 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2794 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2795 }
6f34be50 2796
f122c610
AD		 2797 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2798 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2799 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2800 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2801 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2802 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2803
6f34be50
AD		 2804 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2805 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2806 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2807 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2808 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2809 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2810 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2811 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2812 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2813 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2814 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2815 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2816
b7eff394
AD		 2817 if (rdev->num_crtc >= 4) {
2818 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2819 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2820 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2821 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2822 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2823 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2824 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2825 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2826 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2827 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2828 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2829 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2830 }
2831
2832 if (rdev->num_crtc >= 6) {
2833 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2834 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2835 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2836 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2837 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2838 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2839 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2840 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2841 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2842 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2843 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2844 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2845 }
45f9a39b 2846
6f34be50 2847 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2848 tmp = RREG32(DC_HPD1_INT_CONTROL);
2849 tmp |= DC_HPDx_INT_ACK;
2850 WREG32(DC_HPD1_INT_CONTROL, tmp);
2851 }
6f34be50 2852 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2853 tmp = RREG32(DC_HPD2_INT_CONTROL);
2854 tmp |= DC_HPDx_INT_ACK;
2855 WREG32(DC_HPD2_INT_CONTROL, tmp);
2856 }
6f34be50 2857 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2858 tmp = RREG32(DC_HPD3_INT_CONTROL);
2859 tmp |= DC_HPDx_INT_ACK;
2860 WREG32(DC_HPD3_INT_CONTROL, tmp);
2861 }
6f34be50 2862 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2863 tmp = RREG32(DC_HPD4_INT_CONTROL);
2864 tmp |= DC_HPDx_INT_ACK;
2865 WREG32(DC_HPD4_INT_CONTROL, tmp);
2866 }
6f34be50 2867 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2868 tmp = RREG32(DC_HPD5_INT_CONTROL);
2869 tmp |= DC_HPDx_INT_ACK;
2870 WREG32(DC_HPD5_INT_CONTROL, tmp);
2871 }
6f34be50 2872 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2873 tmp = RREG32(DC_HPD5_INT_CONTROL);
2874 tmp |= DC_HPDx_INT_ACK;
2875 WREG32(DC_HPD6_INT_CONTROL, tmp);
2876 }
f122c610
AD		 2877 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2878 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2879 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2880 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2881 }
2882 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2883 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2884 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2885 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2886 }
2887 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2888 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2889 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2890 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2891 }
2892 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2893 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2894 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2895 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2896 }
2897 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2898 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2899 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2900 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2901 }
2902 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2903 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2904 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2905 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2906 }
45f9a39b
AD		 2907}
2908
2909void evergreen_irq_disable(struct radeon_device *rdev)
2910{
45f9a39b
AD		 2911 r600_disable_interrupts(rdev);
2912 /* Wait and acknowledge irq */
2913 mdelay(1);
6f34be50 2914 evergreen_irq_ack(rdev);
45f9a39b
AD		 2915 evergreen_disable_interrupt_state(rdev);
2916}
2917
755d819e 2918void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2919{
2920 evergreen_irq_disable(rdev);
2921 r600_rlc_stop(rdev);
2922}
2923
cbdd4501 2924static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 2925{
2926 u32 wptr, tmp;
2927
724c80e1 2928 if (rdev->wb.enabled)
204ae24d 2929 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 2930 else
2931 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2932
2933 if (wptr & RB_OVERFLOW) {
2934 /* When a ring buffer overflow happen start parsing interrupt
2935 * from the last not overwritten vector (wptr + 16). Hopefully
2936 * this should allow us to catchup.
2937 */
2938 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2939 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2940 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2941 tmp = RREG32(IH_RB_CNTL);
2942 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2943 WREG32(IH_RB_CNTL, tmp);
2944 }
2945 return (wptr & rdev->ih.ptr_mask);
2946}
2947
2948int evergreen_irq_process(struct radeon_device *rdev)
2949{
682f1a54
DA		 2950 u32 wptr;
2951 u32 rptr;
45f9a39b
AD		 2952 u32 src_id, src_data;
2953 u32 ring_index;
45f9a39b
AD		 2954 unsigned long flags;
2955 bool queue_hotplug = false;
f122c610 2956 bool queue_hdmi = false;
45f9a39b 2957
682f1a54 2958 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 2959 return IRQ_NONE;
2960
682f1a54
DA		 2961 wptr = evergreen_get_ih_wptr(rdev);
2962 rptr = rdev->ih.rptr;
2963 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 2964
682f1a54 2965 spin_lock_irqsave(&rdev->ih.lock, flags);
45f9a39b
AD		 2966 if (rptr == wptr) {
2967 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2968 return IRQ_NONE;
2969 }
45f9a39b 2970restart_ih:
964f6645
BH		 2971 /* Order reading of wptr vs. reading of IH ring data */
2972 rmb();
2973
45f9a39b 2974 /* display interrupts */
6f34be50 2975 evergreen_irq_ack(rdev);
45f9a39b
AD		 2976
2977 rdev->ih.wptr = wptr;
2978 while (rptr != wptr) {
2979 /* wptr/rptr are in bytes! */
2980 ring_index = rptr / 4;
0f234f5f
AD		 2981 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2982 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 2983
2984 switch (src_id) {
2985 case 1: /* D1 vblank/vline */
2986 switch (src_data) {
2987 case 0: /* D1 vblank */
6f34be50 2988 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2989 if (rdev->irq.crtc_vblank_int[0]) {
2990 drm_handle_vblank(rdev->ddev, 0);
2991 rdev->pm.vblank_sync = true;
2992 wake_up(&rdev->irq.vblank_queue);
2993 }
3e4ea742
MK		 2994 if (rdev->irq.pflip[0])
2995 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2996 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2997 DRM_DEBUG("IH: D1 vblank\n");
2998 }
2999 break;
3000 case 1: /* D1 vline */
6f34be50
AD		 3001 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3002 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 3003 DRM_DEBUG("IH: D1 vline\n");
3004 }
3005 break;
3006 default:
3007 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3008 break;
3009 }
3010 break;
3011 case 2: /* D2 vblank/vline */
3012 switch (src_data) {
3013 case 0: /* D2 vblank */
6f34be50 3014 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3015 if (rdev->irq.crtc_vblank_int[1]) {
3016 drm_handle_vblank(rdev->ddev, 1);
3017 rdev->pm.vblank_sync = true;
3018 wake_up(&rdev->irq.vblank_queue);
3019 }
3e4ea742
MK		 3020 if (rdev->irq.pflip[1])
3021 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3022 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 3023 DRM_DEBUG("IH: D2 vblank\n");
3024 }
3025 break;
3026 case 1: /* D2 vline */
6f34be50
AD		 3027 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3028 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 3029 DRM_DEBUG("IH: D2 vline\n");
3030 }
3031 break;
3032 default:
3033 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3034 break;
3035 }
3036 break;
3037 case 3: /* D3 vblank/vline */
3038 switch (src_data) {
3039 case 0: /* D3 vblank */
6f34be50
AD		 3040 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3041 if (rdev->irq.crtc_vblank_int[2]) {
3042 drm_handle_vblank(rdev->ddev, 2);
3043 rdev->pm.vblank_sync = true;
3044 wake_up(&rdev->irq.vblank_queue);
3045 }
3046 if (rdev->irq.pflip[2])
3047 radeon_crtc_handle_flip(rdev, 2);
3048 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 3049 DRM_DEBUG("IH: D3 vblank\n");
3050 }
3051 break;
3052 case 1: /* D3 vline */
6f34be50
AD		 3053 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3054 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 3055 DRM_DEBUG("IH: D3 vline\n");
3056 }
3057 break;
3058 default:
3059 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3060 break;
3061 }
3062 break;
3063 case 4: /* D4 vblank/vline */
3064 switch (src_data) {
3065 case 0: /* D4 vblank */
6f34be50
AD		 3066 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3067 if (rdev->irq.crtc_vblank_int[3]) {
3068 drm_handle_vblank(rdev->ddev, 3);
3069 rdev->pm.vblank_sync = true;
3070 wake_up(&rdev->irq.vblank_queue);
3071 }
3072 if (rdev->irq.pflip[3])
3073 radeon_crtc_handle_flip(rdev, 3);
3074 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 3075 DRM_DEBUG("IH: D4 vblank\n");
3076 }
3077 break;
3078 case 1: /* D4 vline */
6f34be50
AD		 3079 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3080 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 3081 DRM_DEBUG("IH: D4 vline\n");
3082 }
3083 break;
3084 default:
3085 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3086 break;
3087 }
3088 break;
3089 case 5: /* D5 vblank/vline */
3090 switch (src_data) {
3091 case 0: /* D5 vblank */
6f34be50
AD		 3092 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3093 if (rdev->irq.crtc_vblank_int[4]) {
3094 drm_handle_vblank(rdev->ddev, 4);
3095 rdev->pm.vblank_sync = true;
3096 wake_up(&rdev->irq.vblank_queue);
3097 }
3098 if (rdev->irq.pflip[4])
3099 radeon_crtc_handle_flip(rdev, 4);
3100 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 3101 DRM_DEBUG("IH: D5 vblank\n");
3102 }
3103 break;
3104 case 1: /* D5 vline */
6f34be50
AD		 3105 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3106 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3107 DRM_DEBUG("IH: D5 vline\n");
3108 }
3109 break;
3110 default:
3111 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3112 break;
3113 }
3114 break;
3115 case 6: /* D6 vblank/vline */
3116 switch (src_data) {
3117 case 0: /* D6 vblank */
6f34be50
AD		 3118 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3119 if (rdev->irq.crtc_vblank_int[5]) {
3120 drm_handle_vblank(rdev->ddev, 5);
3121 rdev->pm.vblank_sync = true;
3122 wake_up(&rdev->irq.vblank_queue);
3123 }
3124 if (rdev->irq.pflip[5])
3125 radeon_crtc_handle_flip(rdev, 5);
3126 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3127 DRM_DEBUG("IH: D6 vblank\n");
3128 }
3129 break;
3130 case 1: /* D6 vline */
6f34be50
AD		 3131 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3132 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3133 DRM_DEBUG("IH: D6 vline\n");
3134 }
3135 break;
3136 default:
3137 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3138 break;
3139 }
3140 break;
3141 case 42: /* HPD hotplug */
3142 switch (src_data) {
3143 case 0:
6f34be50
AD		 3144 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3145 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3146 queue_hotplug = true;
3147 DRM_DEBUG("IH: HPD1\n");
3148 }
3149 break;
3150 case 1:
6f34be50
AD		 3151 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3152 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3153 queue_hotplug = true;
3154 DRM_DEBUG("IH: HPD2\n");
3155 }
3156 break;
3157 case 2:
6f34be50
AD		 3158 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3159 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3160 queue_hotplug = true;
3161 DRM_DEBUG("IH: HPD3\n");
3162 }
3163 break;
3164 case 3:
6f34be50
AD		 3165 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3166 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3167 queue_hotplug = true;
3168 DRM_DEBUG("IH: HPD4\n");
3169 }
3170 break;
3171 case 4:
6f34be50
AD		 3172 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3173 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3174 queue_hotplug = true;
3175 DRM_DEBUG("IH: HPD5\n");
3176 }
3177 break;
3178 case 5:
6f34be50
AD		 3179 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3180 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3181 queue_hotplug = true;
3182 DRM_DEBUG("IH: HPD6\n");
3183 }
3184 break;
3185 default:
3186 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3187 break;
3188 }
3189 break;
f122c610
AD		 3190 case 44: /* hdmi */
3191 switch (src_data) {
3192 case 0:
3193 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3194 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3195 queue_hdmi = true;
3196 DRM_DEBUG("IH: HDMI0\n");
3197 }
3198 break;
3199 case 1:
3200 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3201 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3202 queue_hdmi = true;
3203 DRM_DEBUG("IH: HDMI1\n");
3204 }
3205 break;
3206 case 2:
3207 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3208 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3209 queue_hdmi = true;
3210 DRM_DEBUG("IH: HDMI2\n");
3211 }
3212 break;
3213 case 3:
3214 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3215 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3216 queue_hdmi = true;
3217 DRM_DEBUG("IH: HDMI3\n");
3218 }
3219 break;
3220 case 4:
3221 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3222 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3223 queue_hdmi = true;
3224 DRM_DEBUG("IH: HDMI4\n");
3225 }
3226 break;
3227 case 5:
3228 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3229 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3230 queue_hdmi = true;
3231 DRM_DEBUG("IH: HDMI5\n");
3232 }
3233 break;
3234 default:
3235 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3236 break;
3237 }
3238 break;
45f9a39b
AD		 3239 case 176: /* CP_INT in ring buffer */
3240 case 177: /* CP_INT in IB1 */
3241 case 178: /* CP_INT in IB2 */
3242 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3243 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3244 break;
3245 case 181: /* CP EOP event */
3246 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3247 if (rdev->family >= CHIP_CAYMAN) {
3248 switch (src_data) {
3249 case 0:
3250 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3251 break;
3252 case 1:
3253 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3254 break;
3255 case 2:
3256 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3257 break;
3258 }
3259 } else
3260 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3261 break;
2031f77c 3262 case 233: /* GUI IDLE */
303c805c 3263 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 3264 rdev->pm.gui_idle = true;
3265 wake_up(&rdev->irq.idle_queue);
3266 break;
45f9a39b
AD		 3267 default:
3268 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3269 break;
3270 }
3271
3272 /* wptr/rptr are in bytes! */
3273 rptr += 16;
3274 rptr &= rdev->ih.ptr_mask;
3275 }
3276 /* make sure wptr hasn't changed while processing */
3277 wptr = evergreen_get_ih_wptr(rdev);
3278 if (wptr != rdev->ih.wptr)
3279 goto restart_ih;
3280 if (queue_hotplug)
32c87fca 3281 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3282 if (queue_hdmi)
3283 schedule_work(&rdev->audio_work);
45f9a39b
AD		 3284 rdev->ih.rptr = rptr;
3285 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3286 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3287 return IRQ_HANDLED;
3288}
3289
bcc1c2a1
AD		 3290static int evergreen_startup(struct radeon_device *rdev)
3291{
e32eb50d 3292 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
bcc1c2a1
AD		 3293 int r;
3294
9e46a48d 3295 /* enable pcie gen2 link */
cd54033a 3296 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3297
0af62b01
AD		 3298 if (ASIC_IS_DCE5(rdev)) {
3299 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3300 r = ni_init_microcode(rdev);
3301 if (r) {
3302 DRM_ERROR("Failed to load firmware!\n");
3303 return r;
3304 }
3305 }
755d819e 3306 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3307 if (r) {
0af62b01 3308 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3309 return r;
3310 }
0af62b01
AD		 3311 } else {
3312 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3313 r = r600_init_microcode(rdev);
3314 if (r) {
3315 DRM_ERROR("Failed to load firmware!\n");
3316 return r;
3317 }
3318 }
bcc1c2a1 3319 }
fe251e2f 3320
16cdf04d
AD		 3321 r = r600_vram_scratch_init(rdev);
3322 if (r)
3323 return r;
3324
bcc1c2a1 3325 evergreen_mc_program(rdev);
bcc1c2a1 3326 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3327 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3328 } else {
3329 r = evergreen_pcie_gart_enable(rdev);
3330 if (r)
3331 return r;
3332 }
bcc1c2a1 3333 evergreen_gpu_init(rdev);
bcc1c2a1 3334
d7ccd8fc 3335 r = evergreen_blit_init(rdev);
bcc1c2a1 3336 if (r) {
fb3d9e97 3337 r600_blit_fini(rdev);
27cd7769 3338 rdev->asic->copy.copy = NULL;
d7ccd8fc 3339 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3340 }
3341
724c80e1
AD		 3342 /* allocate wb buffer */
3343 r = radeon_wb_init(rdev);
3344 if (r)
3345 return r;
3346
30eb77f4
JG		 3347 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3348 if (r) {
3349 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3350 return r;
3351 }
3352
bcc1c2a1
AD		 3353 /* Enable IRQ */
3354 r = r600_irq_init(rdev);
3355 if (r) {
3356 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3357 radeon_irq_kms_fini(rdev);
3358 return r;
3359 }
45f9a39b 3360 evergreen_irq_set(rdev);
bcc1c2a1 3361
e32eb50d 3362 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3363 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3364 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3365 if (r)
3366 return r;
3367 r = evergreen_cp_load_microcode(rdev);
3368 if (r)
3369 return r;
fe251e2f 3370 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 3371 if (r)
3372 return r;
fe251e2f 3373
b15ba512
JG		 3374 r = radeon_ib_pool_start(rdev);
3375 if (r)
3376 return r;
3377
7bd560e8
CK		 3378 r = radeon_ib_ring_tests(rdev);
3379 if (r)
3fe89a0c 3380 return r;
7a7e8734 3381
69d2ae57
RM		 3382 r = r600_audio_init(rdev);
3383 if (r) {
3384 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3385 return r;
3386 }
3387
bcc1c2a1
AD		 3388 return 0;
3389}
3390
3391int evergreen_resume(struct radeon_device *rdev)
3392{
3393 int r;
3394
86f5c9ed
AD		 3395 /* reset the asic, the gfx blocks are often in a bad state
3396 * after the driver is unloaded or after a resume
3397 */
3398 if (radeon_asic_reset(rdev))
3399 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3400 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3401 * posting will perform necessary task to bring back GPU into good
3402 * shape.
3403 */
3404 /* post card */
3405 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3406
b15ba512 3407 rdev->accel_working = true;
bcc1c2a1
AD		 3408 r = evergreen_startup(rdev);
3409 if (r) {
755d819e 3410 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 3411 rdev->accel_working = false;
bcc1c2a1
AD		 3412 return r;
3413 }
fe251e2f 3414
bcc1c2a1
AD		 3415 return r;
3416
3417}
3418
3419int evergreen_suspend(struct radeon_device *rdev)
3420{
e32eb50d 3421 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3422
69d2ae57 3423 r600_audio_fini(rdev);
bcc1c2a1 3424 /* FIXME: we should wait for ring to be empty */
b15ba512
JG		 3425 radeon_ib_pool_suspend(rdev);
3426 r600_blit_suspend(rdev);
bcc1c2a1 3427 r700_cp_stop(rdev);
e32eb50d 3428 ring->ready = false;
45f9a39b 3429 evergreen_irq_suspend(rdev);
724c80e1 3430 radeon_wb_disable(rdev);
bcc1c2a1 3431 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3432
3433 return 0;
3434}
3435
bcc1c2a1
AD		 3436/* Plan is to move initialization in that function and use
3437 * helper function so that radeon_device_init pretty much
3438 * do nothing more than calling asic specific function. This
3439 * should also allow to remove a bunch of callback function
3440 * like vram_info.
3441 */
3442int evergreen_init(struct radeon_device *rdev)
3443{
3444 int r;
3445
bcc1c2a1
AD		 3446 /* Read BIOS */
3447 if (!radeon_get_bios(rdev)) {
3448 if (ASIC_IS_AVIVO(rdev))
3449 return -EINVAL;
3450 }
3451 /* Must be an ATOMBIOS */
3452 if (!rdev->is_atom_bios) {
755d819e 3453 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3454 return -EINVAL;
3455 }
3456 r = radeon_atombios_init(rdev);
3457 if (r)
3458 return r;
86f5c9ed
AD		 3459 /* reset the asic, the gfx blocks are often in a bad state
3460 * after the driver is unloaded or after a resume
3461 */
3462 if (radeon_asic_reset(rdev))
3463 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3464 /* Post card if necessary */
fd909c37 3465 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3466 if (!rdev->bios) {
3467 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3468 return -EINVAL;
3469 }
3470 DRM_INFO("GPU not posted. posting now...\n");
3471 atom_asic_init(rdev->mode_info.atom_context);
3472 }
3473 /* Initialize scratch registers */
3474 r600_scratch_init(rdev);
3475 /* Initialize surface registers */
3476 radeon_surface_init(rdev);
3477 /* Initialize clocks */
3478 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3479 /* Fence driver */
3480 r = radeon_fence_driver_init(rdev);
3481 if (r)
3482 return r;
d594e46a
JG		 3483 /* initialize AGP */
3484 if (rdev->flags & RADEON_IS_AGP) {
3485 r = radeon_agp_init(rdev);
3486 if (r)
3487 radeon_agp_disable(rdev);
3488 }
3489 /* initialize memory controller */
bcc1c2a1
AD		 3490 r = evergreen_mc_init(rdev);
3491 if (r)
3492 return r;
3493 /* Memory manager */
3494 r = radeon_bo_init(rdev);
3495 if (r)
3496 return r;
45f9a39b 3497
bcc1c2a1
AD		 3498 r = radeon_irq_kms_init(rdev);
3499 if (r)
3500 return r;
3501
e32eb50d
CK		 3502 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3503 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1
AD		 3504
3505 rdev->ih.ring_obj = NULL;
3506 r600_ih_ring_init(rdev, 64 * 1024);
3507
3508 r = r600_pcie_gart_init(rdev);
3509 if (r)
3510 return r;
0fcdb61e 3511
b15ba512 3512 r = radeon_ib_pool_init(rdev);
148a03bc 3513 rdev->accel_working = true;
b15ba512
JG		 3514 if (r) {
3515 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3516 rdev->accel_working = false;
3517 }
3518
bcc1c2a1
AD		 3519 r = evergreen_startup(rdev);
3520 if (r) {
fe251e2f
AD		 3521 dev_err(rdev->dev, "disabling GPU acceleration\n");
3522 r700_cp_fini(rdev);
fe251e2f 3523 r600_irq_fini(rdev);
724c80e1 3524 radeon_wb_fini(rdev);
b15ba512 3525 r100_ib_fini(rdev);
fe251e2f 3526 radeon_irq_kms_fini(rdev);
0fcdb61e 3527 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3528 rdev->accel_working = false;
3529 }
77e00f2e
AD		 3530
3531 /* Don't start up if the MC ucode is missing on BTC parts.
3532 * The default clocks and voltages before the MC ucode
3533 * is loaded are not suffient for advanced operations.
3534 */
3535 if (ASIC_IS_DCE5(rdev)) {
3536 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3537 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3538 return -EINVAL;
3539 }
3540 }
3541
bcc1c2a1
AD		 3542 return 0;
3543}
3544
3545void evergreen_fini(struct radeon_device *rdev)
3546{
69d2ae57 3547 r600_audio_fini(rdev);
fb3d9e97 3548 r600_blit_fini(rdev);
45f9a39b 3549 r700_cp_fini(rdev);
bcc1c2a1 3550 r600_irq_fini(rdev);
724c80e1 3551 radeon_wb_fini(rdev);
b15ba512 3552 r100_ib_fini(rdev);
bcc1c2a1 3553 radeon_irq_kms_fini(rdev);
bcc1c2a1 3554 evergreen_pcie_gart_fini(rdev);
16cdf04d 3555 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 3556 radeon_gem_fini(rdev);
3557 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3558 radeon_agp_fini(rdev);
3559 radeon_bo_fini(rdev);
3560 radeon_atombios_fini(rdev);
3561 kfree(rdev->bios);
3562 rdev->bios = NULL;
bcc1c2a1 3563}
9e46a48d 3564
b07759bf 3565void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d
AD		 3566{
3567 u32 link_width_cntl, speed_cntl;
3568
d42dd579
AD		 3569 if (radeon_pcie_gen2 == 0)
3570 return;
3571
9e46a48d
AD		 3572 if (rdev->flags & RADEON_IS_IGP)
3573 return;
3574
3575 if (!(rdev->flags & RADEON_IS_PCIE))
3576 return;
3577
3578 /* x2 cards have a special sequence */
3579 if (ASIC_IS_X2(rdev))
3580 return;
3581
3582 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3583 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3584 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3585
3586 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3587 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3588 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3589
3590 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3591 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3592 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3593
3594 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3595 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3596 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3597
3598 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3599 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3600 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3601
3602 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3603 speed_cntl |= LC_GEN2_EN_STRAP;
3604 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3605
3606 } else {
3607 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3608 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3609 if (1)
3610 link_width_cntl |= LC_UPCONFIGURE_DIS;
3611 else
3612 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3613 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3614 }
3615}
Linux 6.x block layer and io_uring tree(s)