[linux-2.6-block.git] / drivers / gpu / drm / radeon / dce6_afmt.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include "radeon.h"
#include "radeon_audio.h"
#include "sid.h"

#define DCE8_DCCG_AUDIO_DTO1_PHASE	0x05b8
#define DCE8_DCCG_AUDIO_DTO1_MODULE	0x05bc

u32 dce6_endpoint_rreg(struct radeon_device *rdev,
			      u32 block_offset, u32 reg)
{
	unsigned long flags;
	u32 r;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);

	return r;
}

void dce6_endpoint_wreg(struct radeon_device *rdev,
			       u32 block_offset, u32 reg, u32 v)
{
	unsigned long flags;

	spin_lock_irqsave(&rdev->end_idx_lock, flags);
	if (ASIC_IS_DCE8(rdev))
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	else
		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
}

static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
{
	int i;
	u32 offset, tmp;

	for (i = 0; i < rdev->audio.num_pins; i++) {
		offset = rdev->audio.pin[i].offset;
		tmp = RREG32_ENDPOINT(offset,
				      AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
		if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
			rdev->audio.pin[i].connected = false;
		else
			rdev->audio.pin[i].connected = true;
	}
}

struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
{
	struct drm_encoder *encoder;
	struct radeon_encoder *radeon_encoder;
	struct radeon_encoder_atom_dig *dig;
	struct r600_audio_pin *pin = NULL;
	int i, pin_count;

	dce6_afmt_get_connected_pins(rdev);

	for (i = 0; i < rdev->audio.num_pins; i++) {
		if (rdev->audio.pin[i].connected) {
			pin = &rdev->audio.pin[i];
			pin_count = 0;

			list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) {
				if (radeon_encoder_is_digital(encoder)) {
					radeon_encoder = to_radeon_encoder(encoder);
					dig = radeon_encoder->enc_priv;
					if (dig->pin == pin)
						pin_count++;
				}
			}

			if (pin_count == 0)
				return pin;
		}
	}
	if (!pin)
		DRM_ERROR("No connected audio pins found!\n");
	return pin;
}

void dce6_afmt_select_pin(struct drm_encoder *encoder)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	if (!dig || !dig->afmt || !dig->pin)
		return;

	WREG32(AFMT_AUDIO_SRC_CONTROL +  dig->afmt->offset,
	       AFMT_AUDIO_SRC_SELECT(dig->pin->id));
}

void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
				    struct drm_connector *connector,
				    struct drm_display_mode *mode)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 tmp = 0;

	if (!dig || !dig->afmt || !dig->pin)
		return;

	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
		if (connector->latency_present[1])
			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
				AUDIO_LIPSYNC(connector->audio_latency[1]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	} else {
		if (connector->latency_present[0])
			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
				AUDIO_LIPSYNC(connector->audio_latency[0]);
		else
			tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0);
	}
	WREG32_ENDPOINT(dig->pin->offset,
			AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
}

void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
					     u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 tmp;

	if (!dig || !dig->afmt || !dig->pin)
		return;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(dig->pin->offset,
			      AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set HDMI mode */
	tmp |= HDMI_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(dig->pin->offset,
			AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
					   u8 *sadb, int sad_count)
{
	struct radeon_device *rdev = encoder->dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 tmp;

	if (!dig || !dig->afmt || !dig->pin)
		return;

	/* program the speaker allocation */
	tmp = RREG32_ENDPOINT(dig->pin->offset,
			      AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
	tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
	/* set DP mode */
	tmp |= DP_CONNECTION;
	if (sad_count)
		tmp |= SPEAKER_ALLOCATION(sadb[0]);
	else
		tmp |= SPEAKER_ALLOCATION(5); /* stereo */
	WREG32_ENDPOINT(dig->pin->offset,
			AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
}

void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
			      struct cea_sad *sads, int sad_count)
{
	int i;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct radeon_device *rdev = encoder->dev->dev_private;
	static const u16 eld_reg_to_type[][2] = {
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	};

	if (!dig || !dig->afmt || !dig->pin)
		return;

	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
		u32 value = 0;
		u8 stereo_freqs = 0;
		int max_channels = -1;
		int j;

		for (j = 0; j < sad_count; j++) {
			struct cea_sad *sad = &sads[j];

			if (sad->format == eld_reg_to_type[i][1]) {
				if (sad->channels > max_channels) {
					value = MAX_CHANNELS(sad->channels) |
						DESCRIPTOR_BYTE_2(sad->byte2) |
						SUPPORTED_FREQUENCIES(sad->freq);
					max_channels = sad->channels;
				}

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
					stereo_freqs |= sad->freq;
				else
					break;
			}
		}

		value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);

		WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
	}
}

void dce6_audio_enable(struct radeon_device *rdev,
		       struct r600_audio_pin *pin,
		       u8 enable_mask)
{
	if (!pin)
		return;

	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
			enable_mask ? AUDIO_ENABLED : 0);
}

void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
			     struct radeon_crtc *crtc, unsigned int clock)
{
	/* Two dtos; generally use dto0 for HDMI */
	u32 value = 0;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
}

void dce6_dp_audio_set_dto(struct radeon_device *rdev,
			   struct radeon_crtc *crtc, unsigned int clock)
{
	/* Two dtos; generally use dto1 for DP */
	u32 value = 0;
	value |= DCCG_AUDIO_DTO_SEL;

	if (crtc)
		value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);

	WREG32(DCCG_AUDIO_DTO_SOURCE, value);

	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	if (ASIC_IS_DCE8(rdev)) {
		unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
			DENTIST_DPREFCLK_WDIVIDER_MASK) >>
			DENTIST_DPREFCLK_WDIVIDER_SHIFT;
		div = radeon_audio_decode_dfs_div(div);

		if (div)
			clock = clock * 100 / div;

		WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
		WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
	} else {
		WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
		WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
	}
}
Commit	Line	Data
b530602f AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/hdmi.h>
	24	#include <drm/drmP.h>
	25	#include "radeon.h"
1a626b68	26	#include "radeon_audio.h"
b530602f AD	27	#include "sid.h"
b530602f AD	28
2afa3265 SG	29	#define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8
	30	#define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc
	31
1a626b68	32	u32 dce6_endpoint_rreg(struct radeon_device *rdev,
b530602f AD	33	u32 block_offset, u32 reg)
b530602f AD	34	{
0a5b7b0b	35	unsigned long flags;
b530602f AD	36	u32 r;
b530602f AD	37
0a5b7b0b	38	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	39	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
b530602f AD	40	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
0a5b7b0b AD	41	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
0a5b7b0b AD	42
b530602f AD	43	return r;
	44	}
	45
1a626b68	46	void dce6_endpoint_wreg(struct radeon_device *rdev,
b530602f AD	47	u32 block_offset, u32 reg, u32 v)
b530602f AD	48	{
0a5b7b0b AD	49	unsigned long flags;
	50
	51	spin_lock_irqsave(&rdev->end_idx_lock, flags);
b530602f AD	52	if (ASIC_IS_DCE8(rdev))
	53	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
	54	else
	55	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
	56	AZ_ENDPOINT_REG_WRITE_EN \| AZ_ENDPOINT_REG_INDEX(reg));
	57	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
0a5b7b0b	58	spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
b530602f AD	59	}
b530602f AD	60
b530602f AD	61	static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
	62	{
	63	int i;
	64	u32 offset, tmp;
	65
	66	for (i = 0; i < rdev->audio.num_pins; i++) {
	67	offset = rdev->audio.pin[i].offset;
	68	tmp = RREG32_ENDPOINT(offset,
	69	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
	70	if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
	71	rdev->audio.pin[i].connected = false;
	72	else
	73	rdev->audio.pin[i].connected = true;
	74	}
	75	}
	76
	77	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev)
	78	{
d0465208 AD	79	struct drm_encoder *encoder;
	80	struct radeon_encoder *radeon_encoder;
	81	struct radeon_encoder_atom_dig *dig;
	82	struct r600_audio_pin *pin = NULL;
	83	int i, pin_count;
b530602f AD	84
	85	dce6_afmt_get_connected_pins(rdev);
	86
	87	for (i = 0; i < rdev->audio.num_pins; i++) {
d0465208 AD	88	if (rdev->audio.pin[i].connected) {
	89	pin = &rdev->audio.pin[i];
	90	pin_count = 0;
	91
	92	list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) {
	93	if (radeon_encoder_is_digital(encoder)) {
	94	radeon_encoder = to_radeon_encoder(encoder);
	95	dig = radeon_encoder->enc_priv;
	96	if (dig->pin == pin)
	97	pin_count++;
	98	}
	99	}
	100
	101	if (pin_count == 0)
	102	return pin;
	103	}
b530602f	104	}
d0465208 AD	105	if (!pin)
	106	DRM_ERROR("No connected audio pins found!\n");
	107	return pin;
b530602f AD	108	}
	109
	110	void dce6_afmt_select_pin(struct drm_encoder *encoder)
	111	{
	112	struct radeon_device *rdev = encoder->dev->dev_private;
	113	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	114	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b530602f	115
d0ea397e	116	if (!dig \|\| !dig->afmt \|\| !dig->pin)
b530602f AD	117	return;
b530602f AD	118
d0ea397e AD	119	WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
d0ea397e AD	120	AFMT_AUDIO_SRC_SELECT(dig->pin->id));
b530602f AD	121	}
b530602f AD	122
b1880258	123	void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
d0ea397e AD	124	struct drm_connector *connector,
d0ea397e AD	125	struct drm_display_mode *mode)
b1880258 AD	126	{
	127	struct radeon_device *rdev = encoder->dev->dev_private;
	128	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	129	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
d0ea397e	130	u32 tmp = 0;
b1880258	131
d0ea397e	132	if (!dig \|\| !dig->afmt \|\| !dig->pin)
b1880258 AD	133	return;
b1880258 AD	134
b1880258 AD	135	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
	136	if (connector->latency_present[1])
	137	tmp = VIDEO_LIPSYNC(connector->video_latency[1]) \|
	138	AUDIO_LIPSYNC(connector->audio_latency[1]);
	139	else
c748990b	140	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258 AD	141	} else {
	142	if (connector->latency_present[0])
	143	tmp = VIDEO_LIPSYNC(connector->video_latency[0]) \|
	144	AUDIO_LIPSYNC(connector->audio_latency[0]);
	145	else
c748990b	146	tmp = VIDEO_LIPSYNC(0) \| AUDIO_LIPSYNC(0);
b1880258	147	}
d0ea397e AD	148	WREG32_ENDPOINT(dig->pin->offset,
d0ea397e AD	149	AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
b1880258 AD	150	}
b1880258 AD	151
00a9d4bc	152	void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
d0ea397e	153	u8 *sadb, int sad_count)
b530602f AD	154	{
	155	struct radeon_device *rdev = encoder->dev->dev_private;
	156	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	157	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
d0ea397e	158	u32 tmp;
6159b65a	159
d0ea397e	160	if (!dig \|\| !dig->afmt \|\| !dig->pin)
6159b65a RM	161	return;
6159b65a RM	162
6159b65a	163	/* program the speaker allocation */
d0ea397e AD	164	tmp = RREG32_ENDPOINT(dig->pin->offset,
d0ea397e AD	165	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
6159b65a RM	166	tmp &= ~(DP_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	167	/* set HDMI mode */
	168	tmp \|= HDMI_CONNECTION;
	169	if (sad_count)
	170	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	171	else
	172	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
d0ea397e AD	173	WREG32_ENDPOINT(dig->pin->offset,
d0ea397e AD	174	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
00a9d4bc	175	}
6159b65a	176
00a9d4bc	177	void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
d0ea397e	178	u8 *sadb, int sad_count)
00a9d4bc SG	179	{
	180	struct radeon_device *rdev = encoder->dev->dev_private;
	181	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	182	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
d0ea397e	183	u32 tmp;
00a9d4bc	184
d0ea397e	185	if (!dig \|\| !dig->afmt \|\| !dig->pin)
00a9d4bc SG	186	return;
00a9d4bc SG	187
00a9d4bc	188	/* program the speaker allocation */
d0ea397e AD	189	tmp = RREG32_ENDPOINT(dig->pin->offset,
d0ea397e AD	190	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
00a9d4bc SG	191	tmp &= ~(HDMI_CONNECTION \| SPEAKER_ALLOCATION_MASK);
	192	/* set DP mode */
	193	tmp \|= DP_CONNECTION;
	194	if (sad_count)
	195	tmp \|= SPEAKER_ALLOCATION(sadb[0]);
	196	else
	197	tmp \|= SPEAKER_ALLOCATION(5); /* stereo */
d0ea397e AD	198	WREG32_ENDPOINT(dig->pin->offset,
d0ea397e AD	199	AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
6159b65a RM	200	}
6159b65a RM	201
070a2e63	202	void dce6_afmt_write_sad_regs(struct drm_encoder *encoder,
d0ea397e	203	struct cea_sad *sads, int sad_count)
6159b65a	204	{
070a2e63	205	int i;
6159b65a RM	206	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
6159b65a RM	207	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
070a2e63	208	struct radeon_device *rdev = encoder->dev->dev_private;
b530602f AD	209	static const u16 eld_reg_to_type[][2] = {
	210	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
	211	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
	212	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
	213	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
	214	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
	215	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
	216	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
	217	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
	218	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
	219	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
	220	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
	221	{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
	222	};
	223
d0ea397e	224	if (!dig \|\| !dig->afmt \|\| !dig->pin)
b530602f AD	225	return;
b530602f AD	226
b530602f AD	227	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
b530602f AD	228	u32 value = 0;
0f57bca9 AH	229	u8 stereo_freqs = 0;
0f57bca9 AH	230	int max_channels = -1;
b530602f AD	231	int j;
	232
	233	for (j = 0; j < sad_count; j++) {
	234	struct cea_sad *sad = &sads[j];
	235
	236	if (sad->format == eld_reg_to_type[i][1]) {
0f57bca9 AH	237	if (sad->channels > max_channels) {
	238	value = MAX_CHANNELS(sad->channels) \|
	239	DESCRIPTOR_BYTE_2(sad->byte2) \|
	240	SUPPORTED_FREQUENCIES(sad->freq);
	241	max_channels = sad->channels;
	242	}
	243
b530602f	244	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
0f57bca9 AH	245	stereo_freqs \|= sad->freq;
	246	else
	247	break;
b530602f AD	248	}
b530602f AD	249	}
0f57bca9 AH	250
	251	value \|= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
	252
d0ea397e	253	WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value);
b530602f	254	}
b530602f AD	255	}
b530602f AD	256
832eafaf AD	257	void dce6_audio_enable(struct radeon_device *rdev,
832eafaf AD	258	struct r600_audio_pin *pin,
d3d8c141	259	u8 enable_mask)
b530602f	260	{
832eafaf AD	261	if (!pin)
	262	return;
	263
f68fdbe4	264	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
d3d8c141	265	enable_mask ? AUDIO_ENABLED : 0);
b530602f	266	}
a85d682a SG	267
a85d682a SG	268	void dce6_hdmi_audio_set_dto(struct radeon_device *rdev,
d0ea397e	269	struct radeon_crtc *crtc, unsigned int clock)
a85d682a	270	{
b983a8f4	271	/* Two dtos; generally use dto0 for HDMI */
a85d682a SG	272	u32 value = 0;
a85d682a SG	273
b983a8f4	274	if (crtc)
a85d682a SG	275	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	276
	277	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	278
b983a8f4 SG	279	/* Express [24MHz / target pixel clock] as an exact rational
	280	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	281	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	282	*/
	283	WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);
	284	WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
a85d682a SG	285	}
	286
	287	void dce6_dp_audio_set_dto(struct radeon_device *rdev,
d0ea397e	288	struct radeon_crtc *crtc, unsigned int clock)
a85d682a	289	{
b983a8f4	290	/* Two dtos; generally use dto1 for DP */
a85d682a SG	291	u32 value = 0;
	292	value \|= DCCG_AUDIO_DTO_SEL;
	293
b983a8f4	294	if (crtc)
a85d682a SG	295	value \|= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);
	296
	297	WREG32(DCCG_AUDIO_DTO_SOURCE, value);
	298
b983a8f4 SG	299	/* Express [24MHz / target pixel clock] as an exact rational
	300	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	301	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	302	*/
2afa3265	303	if (ASIC_IS_DCE8(rdev)) {
ac4a9350 SG	304	unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
	305	DENTIST_DPREFCLK_WDIVIDER_MASK) >>
	306	DENTIST_DPREFCLK_WDIVIDER_SHIFT;
a64c9dab	307	div = radeon_audio_decode_dfs_div(div);
ac4a9350 SG	308
ac4a9350 SG	309	if (div)
a64c9dab	310	clock = clock * 100 / div;
ac4a9350	311
2afa3265 SG	312	WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
	313	WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
	314	} else {
	315	WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);
	316	WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
	317	}
a85d682a	318	}