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drm/radeon/atom: add helper to calcuate mpll params
[linux-2.6-block.git] / drivers / gpu / drm / radeon / cypress_dpm.c
CommitLineData
dc50ba7f
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include "drmP.h"
26#include "radeon.h"
27#include "evergreend.h"
28#include "r600_dpm.h"
29#include "cypress_dpm.h"
30#include "atom.h"
31
32#define SMC_RAM_END 0x8000
33
34#define MC_CG_ARB_FREQ_F0 0x0a
35#define MC_CG_ARB_FREQ_F1 0x0b
36#define MC_CG_ARB_FREQ_F2 0x0c
37#define MC_CG_ARB_FREQ_F3 0x0d
38
39#define MC_CG_SEQ_DRAMCONF_S0 0x05
40#define MC_CG_SEQ_DRAMCONF_S1 0x06
41#define MC_CG_SEQ_YCLK_SUSPEND 0x04
42#define MC_CG_SEQ_YCLK_RESUME 0x0a
43
44struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
45struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
46struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
47
dc50ba7f
AD		 48static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
49 bool enable)
50{
51 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
52 u32 tmp, bif;
53
54 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
55 if (enable) {
56 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
57 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
58 if (!pi->boot_in_gen2) {
59 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
60 bif |= CG_CLIENT_REQ(0xd);
61 WREG32(CG_BIF_REQ_AND_RSP, bif);
62
63 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
64 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
65 tmp |= LC_GEN2_EN_STRAP;
66
67 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
68 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
69 udelay(10);
70 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
71 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
72 }
73 }
74 } else {
75 if (!pi->boot_in_gen2) {
76 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
77 tmp &= ~LC_GEN2_EN_STRAP;
78 }
79 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
80 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
81 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
82 }
83}
84
85static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
86 bool enable)
87{
88 cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
89
90 if (enable)
91 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
92 else
93 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
94}
95
96#if 0
97static int cypress_enter_ulp_state(struct radeon_device *rdev)
98{
99 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
100
101 if (pi->gfx_clock_gating) {
102 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
103 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
104 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
105
106 RREG32(GB_ADDR_CONFIG);
107 }
108
109 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
110 ~HOST_SMC_MSG_MASK);
111
112 udelay(7000);
113
114 return 0;
115}
116#endif
117
118static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
119 bool enable)
120{
121 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
122
123 if (enable) {
124 if (eg_pi->light_sleep) {
125 WREG32(GRBM_GFX_INDEX, 0xC0000000);
126
127 WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF);
128 WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF);
129 WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF);
130 WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF);
131 WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF);
132 WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF);
133 WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF);
134 WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF);
135 WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF);
136 WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF);
137 WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF);
138 WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF);
139
140 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
141 }
142 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
143 } else {
144 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
145 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
146 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
147 RREG32(GB_ADDR_CONFIG);
148
149 if (eg_pi->light_sleep) {
150 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
151
152 WREG32(GRBM_GFX_INDEX, 0xC0000000);
153
154 WREG32_CG(CG_CGLS_TILE_0, 0);
155 WREG32_CG(CG_CGLS_TILE_1, 0);
156 WREG32_CG(CG_CGLS_TILE_2, 0);
157 WREG32_CG(CG_CGLS_TILE_3, 0);
158 WREG32_CG(CG_CGLS_TILE_4, 0);
159 WREG32_CG(CG_CGLS_TILE_5, 0);
160 WREG32_CG(CG_CGLS_TILE_6, 0);
161 WREG32_CG(CG_CGLS_TILE_7, 0);
162 WREG32_CG(CG_CGLS_TILE_8, 0);
163 WREG32_CG(CG_CGLS_TILE_9, 0);
164 WREG32_CG(CG_CGLS_TILE_10, 0);
165 WREG32_CG(CG_CGLS_TILE_11, 0);
166 }
167 }
168}
169
170static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
171 bool enable)
172{
173 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
174 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
175
176 if (enable) {
177 u32 cgts_sm_ctrl_reg;
178
179 if (rdev->family == CHIP_CEDAR)
180 cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT;
181 else if (rdev->family == CHIP_REDWOOD)
182 cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT;
183 else
184 cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT;
185
186 WREG32(GRBM_GFX_INDEX, 0xC0000000);
187
188 WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT);
189 WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF);
190 WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT);
191 WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT);
192
193 if (pi->mgcgtssm)
194 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
195
196 if (eg_pi->mcls) {
197 WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
198 WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
199 WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
200 WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
201 WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
202 WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
203 WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
204 WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
205 }
206 } else {
207 WREG32(GRBM_GFX_INDEX, 0xC0000000);
208
209 WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
210 WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF);
211 WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF);
212 WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF);
213
214 if (pi->mgcgtssm)
215 WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
216 }
217}
218
219void cypress_enable_spread_spectrum(struct radeon_device *rdev,
220 bool enable)
221{
222 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
223
224 if (enable) {
225 if (pi->sclk_ss)
226 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
227
228 if (pi->mclk_ss)
229 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
230 } else {
231 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
232 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
233 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
234 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
235 }
236}
237
238void cypress_start_dpm(struct radeon_device *rdev)
239{
240 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
241}
242
243void cypress_enable_sclk_control(struct radeon_device *rdev,
244 bool enable)
245{
246 if (enable)
247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
248 else
249 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
250}
251
252void cypress_enable_mclk_control(struct radeon_device *rdev,
253 bool enable)
254{
255 if (enable)
256 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
257 else
258 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
259}
260
261int cypress_notify_smc_display_change(struct radeon_device *rdev,
262 bool has_display)
263{
264 PPSMC_Msg msg = has_display ?
265 (PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay;
266
267 if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
268 return -EINVAL;
269
270 return 0;
271}
272
273void cypress_program_response_times(struct radeon_device *rdev)
274{
275 u32 reference_clock;
276 u32 mclk_switch_limit;
277
278 reference_clock = radeon_get_xclk(rdev);
279 mclk_switch_limit = (460 * reference_clock) / 100;
280
281 rv770_write_smc_soft_register(rdev,
282 RV770_SMC_SOFT_REGISTER_mclk_switch_lim,
283 mclk_switch_limit);
284
285 rv770_write_smc_soft_register(rdev,
286 RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
287
288 rv770_write_smc_soft_register(rdev,
289 RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
290
291 rv770_program_response_times(rdev);
292
293 if (ASIC_IS_LOMBOK(rdev))
294 rv770_write_smc_soft_register(rdev,
295 RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1);
296
297}
298
299static int cypress_pcie_performance_request(struct radeon_device *rdev,
300 u8 perf_req, bool advertise)
301{
302 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
303 u32 tmp;
304
305 udelay(10);
306 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
307 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
308 return 0;
309
310#if defined(CONFIG_ACPI)
311 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
312 (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
313 eg_pi->pcie_performance_request_registered = true;
314 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
315 } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
316 eg_pi->pcie_performance_request_registered) {
317 eg_pi->pcie_performance_request_registered = false;
318 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
319 }
320#endif
321
322 return 0;
323}
324
325void cypress_advertise_gen2_capability(struct radeon_device *rdev)
326{
327 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
328 u32 tmp;
329
330#if defined(CONFIG_ACPI)
331 radeon_acpi_pcie_notify_device_ready(rdev);
332#endif
333
334 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
335
336 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
337 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
338 pi->pcie_gen2 = true;
339 else
340 pi->pcie_gen2 = false;
341
342 if (!pi->pcie_gen2)
343 cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
344
345}
346
347static u32 cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
348{
349 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
350
351 if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
352 return 1;
353 return 0;
354}
355
dbc34160
AD		 356void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
357 struct radeon_ps *radeon_new_state,
358 struct radeon_ps *radeon_current_state)
dc50ba7f 359{
dc50ba7f
AD		 360 u32 pcie_link_speed_target = cypress_get_maximum_link_speed(radeon_new_state);
361 u32 pcie_link_speed_current = cypress_get_maximum_link_speed(radeon_current_state);
362 u8 request;
363
364 if (pcie_link_speed_target < pcie_link_speed_current) {
365 if (pcie_link_speed_target == 0)
366 request = PCIE_PERF_REQ_PECI_GEN1;
367 else if (pcie_link_speed_target == 1)
368 request = PCIE_PERF_REQ_PECI_GEN2;
369 else
370 request = PCIE_PERF_REQ_PECI_GEN3;
371
372 cypress_pcie_performance_request(rdev, request, false);
373 }
374}
375
dbc34160
AD		 376void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
377 struct radeon_ps *radeon_new_state,
378 struct radeon_ps *radeon_current_state)
dc50ba7f 379{
dc50ba7f
AD		 380 u32 pcie_link_speed_target = cypress_get_maximum_link_speed(radeon_new_state);
381 u32 pcie_link_speed_current = cypress_get_maximum_link_speed(radeon_current_state);
382 u8 request;
383
384 if (pcie_link_speed_target > pcie_link_speed_current) {
385 if (pcie_link_speed_target == 0)
386 request = PCIE_PERF_REQ_PECI_GEN1;
387 else if (pcie_link_speed_target == 1)
388 request = PCIE_PERF_REQ_PECI_GEN2;
389 else
390 request = PCIE_PERF_REQ_PECI_GEN3;
391
392 cypress_pcie_performance_request(rdev, request, false);
393 }
394}
395
396static int cypress_populate_voltage_value(struct radeon_device *rdev,
397 struct atom_voltage_table *table,
398 u16 value, RV770_SMC_VOLTAGE_VALUE *voltage)
399{
400 unsigned int i;
401
402 for (i = 0; i < table->count; i++) {
403 if (value <= table->entries[i].value) {
404 voltage->index = (u8)i;
405 voltage->value = cpu_to_be16(table->entries[i].value);
406 break;
407 }
408 }
409
410 if (i == table->count)
411 return -EINVAL;
412
413 return 0;
414}
415
69e0b57a 416u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
dc50ba7f
AD		 417{
418 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
419 u8 result = 0;
420 bool strobe_mode = false;
421
422 if (pi->mem_gddr5) {
423 if (mclk <= pi->mclk_strobe_mode_threshold)
424 strobe_mode = true;
425 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
426
427 if (strobe_mode)
428 result |= SMC_STROBE_ENABLE;
429 }
430
431 return result;
432}
433
69e0b57a 434u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
dc50ba7f
AD		 435{
436 u32 ref_clk = rdev->clock.mpll.reference_freq;
437 u32 vco = clkf * ref_clk;
438
439 /* 100 Mhz ref clk */
440 if (ref_clk == 10000) {
441 if (vco > 500000)
442 return 0xC6;
443 if (vco > 400000)
444 return 0x9D;
445 if (vco > 330000)
446 return 0x6C;
447 if (vco > 250000)
448 return 0x2B;
449 if (vco > 160000)
450 return 0x5B;
451 if (vco > 120000)
452 return 0x0A;
453 return 0x4B;
454 }
455
456 /* 27 Mhz ref clk */
457 if (vco > 250000)
458 return 0x8B;
459 if (vco > 200000)
460 return 0xCC;
461 if (vco > 150000)
462 return 0x9B;
463 return 0x6B;
464}
465
466static int cypress_populate_mclk_value(struct radeon_device *rdev,
467 u32 engine_clock, u32 memory_clock,
468 RV7XX_SMC_MCLK_VALUE *mclk,
469 bool strobe_mode, bool dll_state_on)
470{
471 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
472
473 u32 mpll_ad_func_cntl =
474 pi->clk_regs.rv770.mpll_ad_func_cntl;
475 u32 mpll_ad_func_cntl_2 =
476 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
477 u32 mpll_dq_func_cntl =
478 pi->clk_regs.rv770.mpll_dq_func_cntl;
479 u32 mpll_dq_func_cntl_2 =
480 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
481 u32 mclk_pwrmgt_cntl =
482 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
483 u32 dll_cntl =
484 pi->clk_regs.rv770.dll_cntl;
485 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
486 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
487 struct atom_clock_dividers dividers;
488 u32 ibias;
489 u32 dll_speed;
490 int ret;
491 u32 mc_seq_misc7;
492
493 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
494 memory_clock, strobe_mode, &dividers);
495 if (ret)
496 return ret;
497
498 if (!strobe_mode) {
499 mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
500
501 if(mc_seq_misc7 & 0x8000000)
502 dividers.post_div = 1;
503 }
504
505 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
506
507 mpll_ad_func_cntl &= ~(CLKR_MASK |
508 YCLK_POST_DIV_MASK |
509 CLKF_MASK |
510 CLKFRAC_MASK |
511 IBIAS_MASK);
512 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
513 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
514 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
515 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
516 mpll_ad_func_cntl |= IBIAS(ibias);
517
518 if (dividers.vco_mode)
519 mpll_ad_func_cntl_2 |= VCO_MODE;
520 else
521 mpll_ad_func_cntl_2 &= ~VCO_MODE;
522
523 if (pi->mem_gddr5) {
524 mpll_dq_func_cntl &= ~(CLKR_MASK |
525 YCLK_POST_DIV_MASK |
526 CLKF_MASK |
527 CLKFRAC_MASK |
528 IBIAS_MASK);
529 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
530 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
531 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
532 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
533 mpll_dq_func_cntl |= IBIAS(ibias);
534
535 if (strobe_mode)
536 mpll_dq_func_cntl &= ~PDNB;
537 else
538 mpll_dq_func_cntl |= PDNB;
539
540 if (dividers.vco_mode)
541 mpll_dq_func_cntl_2 |= VCO_MODE;
542 else
543 mpll_dq_func_cntl_2 &= ~VCO_MODE;
544 }
545
546 if (pi->mclk_ss) {
547 struct radeon_atom_ss ss;
548 u32 vco_freq = memory_clock * dividers.post_div;
549
550 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
551 ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
552 u32 reference_clock = rdev->clock.mpll.reference_freq;
553 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
554 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
555 u32 clk_v = ss.percentage *
556 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
557
558 mpll_ss1 &= ~CLKV_MASK;
559 mpll_ss1 |= CLKV(clk_v);
560
561 mpll_ss2 &= ~CLKS_MASK;
562 mpll_ss2 |= CLKS(clk_s);
563 }
564 }
565
566 dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
567 memory_clock);
568
569 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
570 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
571 if (dll_state_on)
572 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
573 MRDCKA1_PDNB |
574 MRDCKB0_PDNB |
575 MRDCKB1_PDNB |
576 MRDCKC0_PDNB |
577 MRDCKC1_PDNB |
578 MRDCKD0_PDNB |
579 MRDCKD1_PDNB);
580 else
581 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
582 MRDCKA1_PDNB |
583 MRDCKB0_PDNB |
584 MRDCKB1_PDNB |
585 MRDCKC0_PDNB |
586 MRDCKC1_PDNB |
587 MRDCKD0_PDNB |
588 MRDCKD1_PDNB);
589
590 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
591 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
592 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
593 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
594 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
595 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
596 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
597 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
598 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
599
600 return 0;
601}
602
69e0b57a
AD		 603u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
604 u32 memory_clock, bool strobe_mode)
dc50ba7f
AD		 605{
606 u8 mc_para_index;
607
608 if (rdev->family >= CHIP_BARTS) {
609 if (strobe_mode) {
610 if (memory_clock < 10000)
611 mc_para_index = 0x00;
612 else if (memory_clock > 47500)
613 mc_para_index = 0x0f;
614 else
615 mc_para_index = (u8)((memory_clock - 10000) / 2500);
616 } else {
617 if (memory_clock < 65000)
618 mc_para_index = 0x00;
619 else if (memory_clock > 135000)
620 mc_para_index = 0x0f;
621 else
622 mc_para_index = (u8)((memory_clock - 60000) / 5000);
623 }
624 } else {
625 if (strobe_mode) {
626 if (memory_clock < 10000)
627 mc_para_index = 0x00;
628 else if (memory_clock > 47500)
629 mc_para_index = 0x0f;
630 else
631 mc_para_index = (u8)((memory_clock - 10000) / 2500);
632 } else {
633 if (memory_clock < 40000)
634 mc_para_index = 0x00;
635 else if (memory_clock > 115000)
636 mc_para_index = 0x0f;
637 else
638 mc_para_index = (u8)((memory_clock - 40000) / 5000);
639 }
640 }
641 return mc_para_index;
642}
643
644static int cypress_populate_mvdd_value(struct radeon_device *rdev,
645 u32 mclk,
646 RV770_SMC_VOLTAGE_VALUE *voltage)
647{
648 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
649 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
650
651 if (!pi->mvdd_control) {
652 voltage->index = eg_pi->mvdd_high_index;
653 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
654 return 0;
655 }
656
657 if (mclk <= pi->mvdd_split_frequency) {
658 voltage->index = eg_pi->mvdd_low_index;
659 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
660 } else {
661 voltage->index = eg_pi->mvdd_high_index;
662 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
663 }
664
665 return 0;
666}
667
668int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
669 struct rv7xx_pl *pl,
670 RV770_SMC_HW_PERFORMANCE_LEVEL *level,
671 u8 watermark_level)
672{
673 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
674 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
675 int ret;
676 bool dll_state_on;
677
678 level->gen2PCIE = pi->pcie_gen2 ?
679 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
680 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
681 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
682 level->displayWatermark = watermark_level;
683
684 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
685 if (ret)
686 return ret;
687
688 level->mcFlags = 0;
689 if (pi->mclk_stutter_mode_threshold &&
f85392bc
AD		 690 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
691 !eg_pi->uvd_enabled) {
dc50ba7f
AD		 692 level->mcFlags |= SMC_MC_STUTTER_EN;
693 if (eg_pi->sclk_deep_sleep)
694 level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
695 else
696 level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
697 }
698
699 if (pi->mem_gddr5) {
700 if (pl->mclk > pi->mclk_edc_enable_threshold)
701 level->mcFlags |= SMC_MC_EDC_RD_FLAG;
702
703 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
704 level->mcFlags |= SMC_MC_EDC_WR_FLAG;
705
706 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
707
708 if (level->strobeMode & SMC_STROBE_ENABLE) {
709 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
710 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
711 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
712 else
713 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
714 } else
715 dll_state_on = eg_pi->dll_default_on;
716
717 ret = cypress_populate_mclk_value(rdev,
718 pl->sclk,
719 pl->mclk,
720 &level->mclk,
721 (level->strobeMode & SMC_STROBE_ENABLE) != 0,
722 dll_state_on);
723 } else {
724 ret = cypress_populate_mclk_value(rdev,
725 pl->sclk,
726 pl->mclk,
727 &level->mclk,
728 true,
729 true);
730 }
731 if (ret)
732 return ret;
733
734 ret = cypress_populate_voltage_value(rdev,
735 &eg_pi->vddc_voltage_table,
736 pl->vddc,
737 &level->vddc);
738 if (ret)
739 return ret;
740
741 if (eg_pi->vddci_control) {
742 ret = cypress_populate_voltage_value(rdev,
743 &eg_pi->vddci_voltage_table,
744 pl->vddci,
745 &level->vddci);
746 if (ret)
747 return ret;
748 }
749
750 ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
751
752 return ret;
753}
754
755static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
756 struct radeon_ps *radeon_state,
757 RV770_SMC_SWSTATE *smc_state)
758{
759 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
760 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
761 int ret;
762
763 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
764 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
765
766 ret = cypress_convert_power_level_to_smc(rdev,
767 &state->low,
768 &smc_state->levels[0],
769 PPSMC_DISPLAY_WATERMARK_LOW);
770 if (ret)
771 return ret;
772
773 ret = cypress_convert_power_level_to_smc(rdev,
774 &state->medium,
775 &smc_state->levels[1],
776 PPSMC_DISPLAY_WATERMARK_LOW);
777 if (ret)
778 return ret;
779
780 ret = cypress_convert_power_level_to_smc(rdev,
781 &state->high,
782 &smc_state->levels[2],
783 PPSMC_DISPLAY_WATERMARK_HIGH);
784 if (ret)
785 return ret;
786
787 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
788 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
789 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
790
791 if (eg_pi->dynamic_ac_timing) {
792 smc_state->levels[0].ACIndex = 2;
793 smc_state->levels[1].ACIndex = 3;
794 smc_state->levels[2].ACIndex = 4;
795 } else {
796 smc_state->levels[0].ACIndex = 0;
797 smc_state->levels[1].ACIndex = 0;
798 smc_state->levels[2].ACIndex = 0;
799 }
800
801 rv770_populate_smc_sp(rdev, radeon_state, smc_state);
802
803 return rv770_populate_smc_t(rdev, radeon_state, smc_state);
804}
805
806static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry,
807 SMC_Evergreen_MCRegisterSet *data,
808 u32 num_entries, u32 valid_flag)
809{
810 u32 i, j;
811
812 for (i = 0, j = 0; j < num_entries; j++) {
813 if (valid_flag & (1 << j)) {
814 data->value[i] = cpu_to_be32(entry->mc_data[j]);
815 i++;
816 }
817 }
818}
819
820static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
821 struct rv7xx_pl *pl,
822 SMC_Evergreen_MCRegisterSet *mc_reg_table_data)
823{
824 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
825 u32 i = 0;
826
827 for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
828 if (pl->mclk <=
829 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
830 break;
831 }
832
833 if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
834 --i;
835
836 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
837 mc_reg_table_data,
838 eg_pi->mc_reg_table.last,
839 eg_pi->mc_reg_table.valid_flag);
840}
841
842static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
843 struct radeon_ps *radeon_state,
844 SMC_Evergreen_MCRegisters *mc_reg_table)
845{
846 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
847
848 cypress_convert_mc_reg_table_entry_to_smc(rdev,
849 &state->low,
850 &mc_reg_table->data[2]);
851 cypress_convert_mc_reg_table_entry_to_smc(rdev,
852 &state->medium,
853 &mc_reg_table->data[3]);
854 cypress_convert_mc_reg_table_entry_to_smc(rdev,
855 &state->high,
856 &mc_reg_table->data[4]);
857}
858
dbc34160
AD		 859int cypress_upload_sw_state(struct radeon_device *rdev,
860 struct radeon_ps *radeon_new_state)
dc50ba7f
AD		 861{
862 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
dc50ba7f
AD		 863 u16 address = pi->state_table_start +
864 offsetof(RV770_SMC_STATETABLE, driverState);
865 RV770_SMC_SWSTATE state = { 0 };
866 int ret;
867
868 ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
869 if (ret)
870 return ret;
871
872 return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
873 sizeof(RV770_SMC_SWSTATE),
874 pi->sram_end);
875}
876
dbc34160
AD		 877int cypress_upload_mc_reg_table(struct radeon_device *rdev,
878 struct radeon_ps *radeon_new_state)
dc50ba7f
AD		 879{
880 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
881 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
dc50ba7f
AD		 882 SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
883 u16 address;
884
885 cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
886
887 address = eg_pi->mc_reg_table_start +
888 (u16)offsetof(SMC_Evergreen_MCRegisters, data[2]);
889
890 return rv770_copy_bytes_to_smc(rdev, address,
891 (u8 *)&mc_reg_table.data[2],
892 sizeof(SMC_Evergreen_MCRegisterSet) * 3,
893 pi->sram_end);
894}
895
896u32 cypress_calculate_burst_time(struct radeon_device *rdev,
897 u32 engine_clock, u32 memory_clock)
898{
899 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
900 u32 multiplier = pi->mem_gddr5 ? 1 : 2;
901 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
902 u32 burst_time;
903
904 if (result <= 4)
905 burst_time = 0;
906 else if (result < 8)
907 burst_time = result - 4;
908 else {
909 burst_time = result / 2 ;
910 if (burst_time > 18)
911 burst_time = 18;
912 }
913
914 return burst_time;
915}
916
dbc34160
AD		 917void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
918 struct radeon_ps *radeon_new_state)
dc50ba7f 919{
dc50ba7f
AD		 920 struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
921 u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
922
923 mc_arb_burst_time &= ~(STATE1_MASK | STATE2_MASK | STATE3_MASK);
924
925 mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev,
926 new_state->low.sclk,
927 new_state->low.mclk));
928 mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev,
929 new_state->medium.sclk,
930 new_state->medium.mclk));
931 mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev,
932 new_state->high.sclk,
933 new_state->high.mclk));
934
935 rv730_program_memory_timing_parameters(rdev, radeon_new_state);
936
937 WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
938}
939
940static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
941 SMC_Evergreen_MCRegisters *mc_reg_table)
942{
943 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
944 u32 i, j;
945
946 for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
947 if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
948 mc_reg_table->address[i].s0 =
949 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
950 mc_reg_table->address[i].s1 =
951 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
952 i++;
953 }
954 }
955
956 mc_reg_table->last = (u8)i;
957}
958
959static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
960{
961 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
962 u32 i = 0;
963
964 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
965 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
966 i++;
967
968 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
969 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
970 i++;
971
972 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
973 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
974 i++;
975
976 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
977 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
978 i++;
979
980 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
981 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
982 i++;
983
984 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
985 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
986 i++;
987
988 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
989 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
990 i++;
991
992 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
993 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
994 i++;
995
996 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
997 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
998 i++;
999
1000 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1001 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
1002 i++;
1003
1004 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1005 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
1006 i++;
1007
1008 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
1009 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
1010 i++;
1011
1012 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
1013 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
1014 i++;
1015
1016 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
1017 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
1018 i++;
1019
1020 eg_pi->mc_reg_table.last = (u8)i;
1021}
1022
1023static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
1024 struct evergreen_mc_reg_entry *entry)
1025{
1026 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1027 u32 i;
1028
1029 for (i = 0; i < eg_pi->mc_reg_table.last; i++)
1030 entry->mc_data[i] =
1031 RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1032
1033}
1034
1035static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
1036 struct atom_memory_clock_range_table *range_table)
1037{
1038 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1039 u32 i, j;
1040
1041 for (i = 0; i < range_table->num_entries; i++) {
1042 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
1043 range_table->mclk[i];
1044 radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
1045 cypress_retrieve_ac_timing_for_one_entry(rdev,
1046 &eg_pi->mc_reg_table.mc_reg_table_entry[i]);
1047 }
1048
1049 eg_pi->mc_reg_table.num_entries = range_table->num_entries;
1050 eg_pi->mc_reg_table.valid_flag = 0;
1051
1052 for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1053 for (j = 1; j < range_table->num_entries; j++) {
1054 if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
1055 eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
1056 eg_pi->mc_reg_table.valid_flag |= (1 << i);
1057 break;
1058 }
1059 }
1060 }
1061}
1062
1063static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
1064{
1065 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1066 u8 module_index = rv770_get_memory_module_index(rdev);
1067 struct atom_memory_clock_range_table range_table = { 0 };
1068 int ret;
1069
1070 ret = radeon_atom_get_mclk_range_table(rdev,
1071 pi->mem_gddr5,
1072 module_index, &range_table);
1073 if (ret)
1074 return ret;
1075
1076 cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
1077
1078 return 0;
1079}
1080
1081static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
1082{
1083 u32 i, j;
1084 u32 channels = 2;
1085
1086 if ((rdev->family == CHIP_CYPRESS) ||
1087 (rdev->family == CHIP_HEMLOCK))
1088 channels = 4;
1089 else if (rdev->family == CHIP_CEDAR)
1090 channels = 1;
1091
1092 for (i = 0; i < channels; i++) {
1093 if ((rdev->family == CHIP_CYPRESS) ||
1094 (rdev->family == CHIP_HEMLOCK)) {
1095 WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1096 WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
1097 } else {
1098 WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1099 WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
1100 }
1101 for (j = 0; j < rdev->usec_timeout; j++) {
1102 if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
1103 break;
1104 udelay(1);
1105 }
1106 }
1107}
1108
dbc34160
AD		 1109static void cypress_force_mc_use_s1(struct radeon_device *rdev,
1110 struct radeon_ps *radeon_boot_state)
dc50ba7f 1111{
dc50ba7f
AD		 1112 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1113 u32 strobe_mode;
1114 u32 mc_seq_cg;
1115 int i;
1116
1117 if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1118 return;
1119
1120 radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
1121 radeon_mc_wait_for_idle(rdev);
1122
1123 if ((rdev->family == CHIP_CYPRESS) ||
1124 (rdev->family == CHIP_HEMLOCK)) {
1125 WREG32(MC_CONFIG_MCD, 0xf);
1126 WREG32(MC_CG_CONFIG_MCD, 0xf);
1127 } else {
1128 WREG32(MC_CONFIG, 0xf);
1129 WREG32(MC_CG_CONFIG, 0xf);
1130 }
1131
1132 for (i = 0; i < rdev->num_crtc; i++)
1133 radeon_wait_for_vblank(rdev, i);
1134
1135 WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1136 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1137
1138 strobe_mode = cypress_get_strobe_mode_settings(rdev,
1139 boot_state->low.mclk);
1140
1141 mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1);
1142 mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1143 WREG32(MC_SEQ_CG, mc_seq_cg);
1144
1145 for (i = 0; i < rdev->usec_timeout; i++) {
1146 if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
1147 break;
1148 udelay(1);
1149 }
1150
1151 mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1152 mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1153 WREG32(MC_SEQ_CG, mc_seq_cg);
1154
1155 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1156}
1157
1158static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
1159{
1160 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1161 u32 value;
1162 u32 i;
1163
1164 for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
1165 value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
1166 WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
1167 }
1168}
1169
dbc34160
AD		 1170static void cypress_force_mc_use_s0(struct radeon_device *rdev,
1171 struct radeon_ps *radeon_boot_state)
dc50ba7f 1172{
dc50ba7f
AD		 1173 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1174 u32 strobe_mode;
1175 u32 mc_seq_cg;
1176 int i;
1177
1178 cypress_copy_ac_timing_from_s1_to_s0(rdev);
1179 radeon_mc_wait_for_idle(rdev);
1180
1181 if ((rdev->family == CHIP_CYPRESS) ||
1182 (rdev->family == CHIP_HEMLOCK)) {
1183 WREG32(MC_CONFIG_MCD, 0xf);
1184 WREG32(MC_CG_CONFIG_MCD, 0xf);
1185 } else {
1186 WREG32(MC_CONFIG, 0xf);
1187 WREG32(MC_CG_CONFIG, 0xf);
1188 }
1189
1190 for (i = 0; i < rdev->num_crtc; i++)
1191 radeon_wait_for_vblank(rdev, i);
1192
1193 WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
1194 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
1195
1196 strobe_mode = cypress_get_strobe_mode_settings(rdev,
1197 boot_state->low.mclk);
1198
1199 mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0);
1200 mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
1201 WREG32(MC_SEQ_CG, mc_seq_cg);
1202
1203 for (i = 0; i < rdev->usec_timeout; i++) {
1204 if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
1205 break;
1206 udelay(1);
1207 }
1208
1209 mc_seq_cg &= ~CG_SEQ_REQ_MASK;
1210 mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
1211 WREG32(MC_SEQ_CG, mc_seq_cg);
1212
1213 cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
1214}
1215
1216static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
1217 RV770_SMC_VOLTAGE_VALUE *voltage)
1218{
1219 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1220
1221 voltage->index = eg_pi->mvdd_high_index;
1222 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1223
1224 return 0;
1225}
1226
1227int cypress_populate_smc_initial_state(struct radeon_device *rdev,
1228 struct radeon_ps *radeon_initial_state,
1229 RV770_SMC_STATETABLE *table)
1230{
1231 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state);
1232 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1233 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1234 u32 a_t;
1235
1236 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1237 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
1238 table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1239 cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
1240 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1241 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
1242 table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1243 cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
1244 table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1245 cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
1246 table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
1247 cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
1248
1249 table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
1250 cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
1251 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
1252 cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
1253
1254 table->initialState.levels[0].mclk.mclk770.mclk_value =
1255 cpu_to_be32(initial_state->low.mclk);
1256
1257 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1258 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
1259 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1260 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
1261 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1262 cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
1263 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1264 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
1265 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1266 cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
1267
1268 table->initialState.levels[0].sclk.sclk_value =
1269 cpu_to_be32(initial_state->low.sclk);
1270
1271 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1272
1273 table->initialState.levels[0].ACIndex = 0;
1274
1275 cypress_populate_voltage_value(rdev,
1276 &eg_pi->vddc_voltage_table,
1277 initial_state->low.vddc,
1278 &table->initialState.levels[0].vddc);
1279
1280 if (eg_pi->vddci_control)
1281 cypress_populate_voltage_value(rdev,
1282 &eg_pi->vddci_voltage_table,
1283 initial_state->low.vddci,
1284 &table->initialState.levels[0].vddci);
1285
1286 cypress_populate_initial_mvdd_value(rdev,
1287 &table->initialState.levels[0].mvdd);
1288
1289 a_t = CG_R(0xffff) | CG_L(0);
1290 table->initialState.levels[0].aT = cpu_to_be32(a_t);
1291
1292 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1293
1294
1295 if (pi->boot_in_gen2)
1296 table->initialState.levels[0].gen2PCIE = 1;
1297 else
1298 table->initialState.levels[0].gen2PCIE = 0;
1299 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1300 table->initialState.levels[0].gen2XSP = 1;
1301 else
1302 table->initialState.levels[0].gen2XSP = 0;
1303
1304 if (pi->mem_gddr5) {
1305 table->initialState.levels[0].strobeMode =
1306 cypress_get_strobe_mode_settings(rdev,
1307 initial_state->low.mclk);
1308
1309 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
1310 table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
1311 else
1312 table->initialState.levels[0].mcFlags = 0;
1313 }
1314
1315 table->initialState.levels[1] = table->initialState.levels[0];
1316 table->initialState.levels[2] = table->initialState.levels[0];
1317
1318 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1319
1320 return 0;
1321}
1322
1323int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
1324 RV770_SMC_STATETABLE *table)
1325{
1326 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1327 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1328 u32 mpll_ad_func_cntl =
1329 pi->clk_regs.rv770.mpll_ad_func_cntl;
1330 u32 mpll_ad_func_cntl_2 =
1331 pi->clk_regs.rv770.mpll_ad_func_cntl_2;
1332 u32 mpll_dq_func_cntl =
1333 pi->clk_regs.rv770.mpll_dq_func_cntl;
1334 u32 mpll_dq_func_cntl_2 =
1335 pi->clk_regs.rv770.mpll_dq_func_cntl_2;
1336 u32 spll_func_cntl =
1337 pi->clk_regs.rv770.cg_spll_func_cntl;
1338 u32 spll_func_cntl_2 =
1339 pi->clk_regs.rv770.cg_spll_func_cntl_2;
1340 u32 spll_func_cntl_3 =
1341 pi->clk_regs.rv770.cg_spll_func_cntl_3;
1342 u32 mclk_pwrmgt_cntl =
1343 pi->clk_regs.rv770.mclk_pwrmgt_cntl;
1344 u32 dll_cntl =
1345 pi->clk_regs.rv770.dll_cntl;
1346
1347 table->ACPIState = table->initialState;
1348
1349 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1350
1351 if (pi->acpi_vddc) {
1352 cypress_populate_voltage_value(rdev,
1353 &eg_pi->vddc_voltage_table,
1354 pi->acpi_vddc,
1355 &table->ACPIState.levels[0].vddc);
1356 if (pi->pcie_gen2) {
1357 if (pi->acpi_pcie_gen2)
1358 table->ACPIState.levels[0].gen2PCIE = 1;
1359 else
1360 table->ACPIState.levels[0].gen2PCIE = 0;
1361 } else
1362 table->ACPIState.levels[0].gen2PCIE = 0;
1363 if (pi->acpi_pcie_gen2)
1364 table->ACPIState.levels[0].gen2XSP = 1;
1365 else
1366 table->ACPIState.levels[0].gen2XSP = 0;
1367 } else {
1368 cypress_populate_voltage_value(rdev,
1369 &eg_pi->vddc_voltage_table,
1370 pi->min_vddc_in_table,
1371 &table->ACPIState.levels[0].vddc);
1372 table->ACPIState.levels[0].gen2PCIE = 0;
1373 }
1374
1375 if (eg_pi->acpi_vddci) {
1376 if (eg_pi->vddci_control) {
1377 cypress_populate_voltage_value(rdev,
1378 &eg_pi->vddci_voltage_table,
1379 eg_pi->acpi_vddci,
1380 &table->ACPIState.levels[0].vddci);
1381 }
1382 }
1383
1384 mpll_ad_func_cntl &= ~PDNB;
1385
1386 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1387
1388 if (pi->mem_gddr5)
1389 mpll_dq_func_cntl &= ~PDNB;
1390 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1391
1392 mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1393 MRDCKA1_RESET |
1394 MRDCKB0_RESET |
1395 MRDCKB1_RESET |
1396 MRDCKC0_RESET |
1397 MRDCKC1_RESET |
1398 MRDCKD0_RESET |
1399 MRDCKD1_RESET);
1400
1401 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1402 MRDCKA1_PDNB |
1403 MRDCKB0_PDNB |
1404 MRDCKB1_PDNB |
1405 MRDCKC0_PDNB |
1406 MRDCKC1_PDNB |
1407 MRDCKD0_PDNB |
1408 MRDCKD1_PDNB);
1409
1410 dll_cntl |= (MRDCKA0_BYPASS |
1411 MRDCKA1_BYPASS |
1412 MRDCKB0_BYPASS |
1413 MRDCKB1_BYPASS |
1414 MRDCKC0_BYPASS |
1415 MRDCKC1_BYPASS |
1416 MRDCKD0_BYPASS |
1417 MRDCKD1_BYPASS);
1418
1419 /* evergreen only */
1420 if (rdev->family <= CHIP_HEMLOCK)
1421 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
1422
1423 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1424 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1425
1426 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
1427 cpu_to_be32(mpll_ad_func_cntl);
1428 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
1429 cpu_to_be32(mpll_ad_func_cntl_2);
1430 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
1431 cpu_to_be32(mpll_dq_func_cntl);
1432 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
1433 cpu_to_be32(mpll_dq_func_cntl_2);
1434 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
1435 cpu_to_be32(mclk_pwrmgt_cntl);
1436 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
1437
1438 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
1439
1440 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1441 cpu_to_be32(spll_func_cntl);
1442 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1443 cpu_to_be32(spll_func_cntl_2);
1444 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1445 cpu_to_be32(spll_func_cntl_3);
1446
1447 table->ACPIState.levels[0].sclk.sclk_value = 0;
1448
1449 cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1450
1451 if (eg_pi->dynamic_ac_timing)
1452 table->ACPIState.levels[0].ACIndex = 1;
1453
1454 table->ACPIState.levels[1] = table->ACPIState.levels[0];
1455 table->ACPIState.levels[2] = table->ACPIState.levels[0];
1456
1457 return 0;
1458}
1459
1460static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
1461 struct atom_voltage_table *voltage_table)
1462{
1463 unsigned int i, diff;
1464
1465 if (voltage_table->count <= MAX_NO_VREG_STEPS)
1466 return;
1467
1468 diff = voltage_table->count - MAX_NO_VREG_STEPS;
1469
1470 for (i= 0; i < MAX_NO_VREG_STEPS; i++)
1471 voltage_table->entries[i] = voltage_table->entries[i + diff];
1472
1473 voltage_table->count = MAX_NO_VREG_STEPS;
1474}
1475
1476int cypress_construct_voltage_tables(struct radeon_device *rdev)
1477{
1478 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1479 int ret;
1480
1481 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1482 &eg_pi->vddc_voltage_table);
1483 if (ret)
1484 return ret;
1485
1486 if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
1487 cypress_trim_voltage_table_to_fit_state_table(rdev,
1488 &eg_pi->vddc_voltage_table);
1489
1490 if (eg_pi->vddci_control) {
1491 ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
1492 &eg_pi->vddci_voltage_table);
1493 if (ret)
1494 return ret;
1495
1496 if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
1497 cypress_trim_voltage_table_to_fit_state_table(rdev,
1498 &eg_pi->vddci_voltage_table);
1499 }
1500
1501 return 0;
1502}
1503
1504static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
1505 struct atom_voltage_table *voltage_table,
1506 RV770_SMC_STATETABLE *table)
1507{
1508 unsigned int i;
1509
1510 for (i = 0; i < voltage_table->count; i++) {
1511 table->highSMIO[i] = 0;
1512 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1513 }
1514}
1515
1516int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
1517 RV770_SMC_STATETABLE *table)
1518{
1519 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1520 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1521 unsigned char i;
1522
1523 if (eg_pi->vddc_voltage_table.count) {
1524 cypress_populate_smc_voltage_table(rdev,
1525 &eg_pi->vddc_voltage_table,
1526 table);
1527
1528 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
1529 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
1530 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1531
1532 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1533 if (pi->max_vddc_in_table <=
1534 eg_pi->vddc_voltage_table.entries[i].value) {
1535 table->maxVDDCIndexInPPTable = i;
1536 break;
1537 }
1538 }
1539 }
1540
1541 if (eg_pi->vddci_voltage_table.count) {
1542 cypress_populate_smc_voltage_table(rdev,
1543 &eg_pi->vddci_voltage_table,
1544 table);
1545
1546 table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
1547 table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
1548 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1549 }
1550
1551 return 0;
1552}
1553
1554static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)
1555{
1556 if ((memory_info->mem_type == MEM_TYPE_GDDR3) ||
1557 (memory_info->mem_type == MEM_TYPE_DDR3))
1558 return 30000;
1559
1560 return 0;
1561}
1562
1563int cypress_get_mvdd_configuration(struct radeon_device *rdev)
1564{
1565 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1566 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1567 u8 module_index;
1568 struct atom_memory_info memory_info;
1569 u32 tmp = RREG32(GENERAL_PWRMGT);
1570
1571 if (!(tmp & BACKBIAS_PAD_EN)) {
1572 eg_pi->mvdd_high_index = 0;
1573 eg_pi->mvdd_low_index = 1;
1574 pi->mvdd_control = false;
1575 return 0;
1576 }
1577
1578 if (tmp & BACKBIAS_VALUE)
1579 eg_pi->mvdd_high_index = 1;
1580 else
1581 eg_pi->mvdd_high_index = 0;
1582
1583 eg_pi->mvdd_low_index =
1584 (eg_pi->mvdd_high_index == 0) ? 1 : 0;
1585
1586 module_index = rv770_get_memory_module_index(rdev);
1587
1588 if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
1589 pi->mvdd_control = false;
1590 return 0;
1591 }
1592
1593 pi->mvdd_split_frequency =
1594 cypress_get_mclk_split_point(&memory_info);
1595
1596 if (pi->mvdd_split_frequency == 0) {
1597 pi->mvdd_control = false;
1598 return 0;
1599 }
1600
1601 return 0;
1602}
1603
dbc34160
AD		 1604static int cypress_init_smc_table(struct radeon_device *rdev,
1605 struct radeon_ps *radeon_boot_state)
dc50ba7f
AD		 1606{
1607 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
dc50ba7f
AD		 1608 RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1609 int ret;
1610
1611 memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1612
1613 cypress_populate_smc_voltage_tables(rdev, table);
1614
1615 switch (rdev->pm.int_thermal_type) {
1616 case THERMAL_TYPE_EVERGREEN:
1617 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1618 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1619 break;
1620 case THERMAL_TYPE_NONE:
1621 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1622 break;
1623 default:
1624 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1625 break;
1626 }
1627
1628 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1629 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1630
1631 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1632 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1633
1634 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1635 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1636
1637 if (pi->mem_gddr5)
1638 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1639
1640 ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1641 if (ret)
1642 return ret;
1643
1644 ret = cypress_populate_smc_acpi_state(rdev, table);
1645 if (ret)
1646 return ret;
1647
1648 table->driverState = table->initialState;
1649
1650 return rv770_copy_bytes_to_smc(rdev,
1651 pi->state_table_start,
1652 (u8 *)table, sizeof(RV770_SMC_STATETABLE),
1653 pi->sram_end);
1654}
1655
dbc34160
AD		 1656int cypress_populate_mc_reg_table(struct radeon_device *rdev,
1657 struct radeon_ps *radeon_boot_state)
dc50ba7f
AD		 1658{
1659 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1660 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
dc50ba7f
AD		 1661 struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
1662 SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
1663
1664 rv770_write_smc_soft_register(rdev,
1665 RV770_SMC_SOFT_REGISTER_seq_index, 1);
1666
1667 cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
1668
1669 cypress_convert_mc_reg_table_entry_to_smc(rdev,
1670 &boot_state->low,
1671 &mc_reg_table.data[0]);
1672
1673 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
1674 &mc_reg_table.data[1], eg_pi->mc_reg_table.last,
1675 eg_pi->mc_reg_table.valid_flag);
1676
1677 cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
1678
1679 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
1680 (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),
1681 pi->sram_end);
1682}
1683
1684int cypress_get_table_locations(struct radeon_device *rdev)
1685{
1686 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1687 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1688 u32 tmp;
1689 int ret;
1690
1691 ret = rv770_read_smc_sram_dword(rdev,
1692 EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1693 EVERGREEN_SMC_FIRMWARE_HEADER_stateTable,
1694 &tmp, pi->sram_end);
1695 if (ret)
1696 return ret;
1697
1698 pi->state_table_start = (u16)tmp;
1699
1700 ret = rv770_read_smc_sram_dword(rdev,
1701 EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1702 EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters,
1703 &tmp, pi->sram_end);
1704 if (ret)
1705 return ret;
1706
1707 pi->soft_regs_start = (u16)tmp;
1708
1709 ret = rv770_read_smc_sram_dword(rdev,
1710 EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
1711 EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable,
1712 &tmp, pi->sram_end);
1713 if (ret)
1714 return ret;
1715
1716 eg_pi->mc_reg_table_start = (u16)tmp;
1717
1718 return 0;
1719}
1720
1721void cypress_enable_display_gap(struct radeon_device *rdev)
1722{
1723 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1724
1725 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1726 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1727 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
1728
1729 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1730 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
1731 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
1732 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1733}
1734
1735static void cypress_program_display_gap(struct radeon_device *rdev)
1736{
1737 u32 tmp, pipe;
1738 int i;
1739
1740 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
1741 if (rdev->pm.dpm.new_active_crtc_count > 0)
1742 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1743 else
1744 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1745
1746 if (rdev->pm.dpm.new_active_crtc_count > 1)
1747 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1748 else
1749 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1750
1751 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1752
1753 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
1754 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
1755
1756 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
1757 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
1758 /* find the first active crtc */
1759 for (i = 0; i < rdev->num_crtc; i++) {
1760 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
1761 break;
1762 }
1763 if (i == rdev->num_crtc)
1764 pipe = 0;
1765 else
1766 pipe = i;
1767
1768 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
1769 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
1770 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
1771 }
1772
1773 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
1774}
1775
1776void cypress_dpm_setup_asic(struct radeon_device *rdev)
1777{
1778 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1779
1780 rv740_read_clock_registers(rdev);
1781 rv770_read_voltage_smio_registers(rdev);
1782 rv770_get_max_vddc(rdev);
1783 rv770_get_memory_type(rdev);
1784
1785 if (eg_pi->pcie_performance_request)
1786 eg_pi->pcie_performance_request_registered = false;
1787
1788 if (eg_pi->pcie_performance_request)
1789 cypress_advertise_gen2_capability(rdev);
1790
1791 rv770_get_pcie_gen2_status(rdev);
1792
1793 rv770_enable_acpi_pm(rdev);
1794}
1795
1796int cypress_dpm_enable(struct radeon_device *rdev)
1797{
1798 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1799 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
dbc34160 1800 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
dc50ba7f
AD		 1801
1802 if (pi->gfx_clock_gating)
1803 rv770_restore_cgcg(rdev);
1804
1805 if (rv770_dpm_enabled(rdev))
1806 return -EINVAL;
1807
1808 if (pi->voltage_control) {
1809 rv770_enable_voltage_control(rdev, true);
1810 cypress_construct_voltage_tables(rdev);
1811 }
1812
1813 if (pi->mvdd_control)
1814 cypress_get_mvdd_configuration(rdev);
1815
1816 if (eg_pi->dynamic_ac_timing) {
1817 cypress_set_mc_reg_address_table(rdev);
dbc34160 1818 cypress_force_mc_use_s0(rdev, boot_ps);
dc50ba7f 1819 cypress_initialize_mc_reg_table(rdev);
dbc34160 1820 cypress_force_mc_use_s1(rdev, boot_ps);
dc50ba7f
AD		 1821 }
1822
1823 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1824 rv770_enable_backbias(rdev, true);
1825
1826 if (pi->dynamic_ss)
1827 cypress_enable_spread_spectrum(rdev, true);
1828
1829 if (pi->thermal_protection)
1830 rv770_enable_thermal_protection(rdev, true);
1831
1832 rv770_setup_bsp(rdev);
1833 rv770_program_git(rdev);
1834 rv770_program_tp(rdev);
1835 rv770_program_tpp(rdev);
1836 rv770_program_sstp(rdev);
1837 rv770_program_engine_speed_parameters(rdev);
1838 cypress_enable_display_gap(rdev);
1839 rv770_program_vc(rdev);
1840
1841 if (pi->dynamic_pcie_gen2)
1842 cypress_enable_dynamic_pcie_gen2(rdev, true);
1843
1844 if (rv770_upload_firmware(rdev))
1845 return -EINVAL;
1846
1847 cypress_get_table_locations(rdev);
1848
dbc34160 1849 if (cypress_init_smc_table(rdev, boot_ps))
dc50ba7f
AD		 1850 return -EINVAL;
1851
1852 if (eg_pi->dynamic_ac_timing)
dbc34160 1853 cypress_populate_mc_reg_table(rdev, boot_ps);
dc50ba7f
AD		 1854
1855 cypress_program_response_times(rdev);
1856
1857 r7xx_start_smc(rdev);
1858
1859 cypress_notify_smc_display_change(rdev, false);
1860
1861 cypress_enable_sclk_control(rdev, true);
1862
1863 if (eg_pi->memory_transition)
1864 cypress_enable_mclk_control(rdev, true);
1865
1866 cypress_start_dpm(rdev);
1867
1868 if (pi->gfx_clock_gating)
1869 cypress_gfx_clock_gating_enable(rdev, true);
1870
1871 if (pi->mg_clock_gating)
1872 cypress_mg_clock_gating_enable(rdev, true);
1873
1874 if (rdev->irq.installed &&
1875 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1876 PPSMC_Result result;
1877
1878 rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1879 rdev->irq.dpm_thermal = true;
1880 radeon_irq_set(rdev);
1881 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
1882
1883 if (result != PPSMC_Result_OK)
1884 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
1885 }
1886
1887 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1888
1889 return 0;
1890}
1891
1892void cypress_dpm_disable(struct radeon_device *rdev)
1893{
1894 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1895 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
dbc34160 1896 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
dc50ba7f
AD		 1897
1898 if (!rv770_dpm_enabled(rdev))
1899 return;
1900
1901 rv770_clear_vc(rdev);
1902
1903 if (pi->thermal_protection)
1904 rv770_enable_thermal_protection(rdev, false);
1905
1906 if (pi->dynamic_pcie_gen2)
1907 cypress_enable_dynamic_pcie_gen2(rdev, false);
1908
1909 if (rdev->irq.installed &&
1910 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1911 rdev->irq.dpm_thermal = false;
1912 radeon_irq_set(rdev);
1913 }
1914
1915 if (pi->gfx_clock_gating)
1916 cypress_gfx_clock_gating_enable(rdev, false);
1917
1918 if (pi->mg_clock_gating)
1919 cypress_mg_clock_gating_enable(rdev, false);
1920
1921 rv770_stop_dpm(rdev);
1922 r7xx_stop_smc(rdev);
1923
1924 cypress_enable_spread_spectrum(rdev, false);
1925
1926 if (eg_pi->dynamic_ac_timing)
dbc34160 1927 cypress_force_mc_use_s1(rdev, boot_ps);
dc50ba7f
AD		 1928
1929 rv770_reset_smio_status(rdev);
1930}
1931
1932int cypress_dpm_set_power_state(struct radeon_device *rdev)
1933{
1934 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5d77d776
AD		 1935 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1936 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
dc50ba7f
AD		 1937
1938 rv770_restrict_performance_levels_before_switch(rdev);
1939
1940 if (eg_pi->pcie_performance_request)
dbc34160 1941 cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
dc50ba7f 1942
5d77d776 1943 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
dc50ba7f 1944 rv770_halt_smc(rdev);
dbc34160 1945 cypress_upload_sw_state(rdev, new_ps);
dc50ba7f
AD		 1946
1947 if (eg_pi->dynamic_ac_timing)
dbc34160 1948 cypress_upload_mc_reg_table(rdev, new_ps);
dc50ba7f 1949
dbc34160 1950 cypress_program_memory_timing_parameters(rdev, new_ps);
dc50ba7f
AD		 1951
1952 rv770_resume_smc(rdev);
1953 rv770_set_sw_state(rdev);
5d77d776 1954 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
dc50ba7f
AD		 1955
1956 if (eg_pi->pcie_performance_request)
dbc34160 1957 cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
dc50ba7f
AD		 1958
1959 rv770_unrestrict_performance_levels_after_switch(rdev);
1960
1961 return 0;
1962}
1963
1964void cypress_dpm_reset_asic(struct radeon_device *rdev)
1965{
1966 rv770_restrict_performance_levels_before_switch(rdev);
1967 rv770_set_boot_state(rdev);
1968}
1969
1970void cypress_dpm_display_configuration_changed(struct radeon_device *rdev)
1971{
1972 cypress_program_display_gap(rdev);
1973}
1974
1975int cypress_dpm_init(struct radeon_device *rdev)
1976{
1977 struct rv7xx_power_info *pi;
1978 struct evergreen_power_info *eg_pi;
1979 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1980 uint16_t data_offset, size;
1981 uint8_t frev, crev;
1982 struct atom_clock_dividers dividers;
1983 int ret;
1984
1985 eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
1986 if (eg_pi == NULL)
1987 return -ENOMEM;
1988 rdev->pm.dpm.priv = eg_pi;
1989 pi = &eg_pi->rv7xx;
1990
1991 rv770_get_max_vddc(rdev);
1992
1993 eg_pi->ulv.supported = false;
1994 pi->acpi_vddc = 0;
1995 eg_pi->acpi_vddci = 0;
1996 pi->min_vddc_in_table = 0;
1997 pi->max_vddc_in_table = 0;
1998
1999 ret = rv7xx_parse_power_table(rdev);
2000 if (ret)
2001 return ret;
2002
2003 if (rdev->pm.dpm.voltage_response_time == 0)
2004 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2005 if (rdev->pm.dpm.backbias_response_time == 0)
2006 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2007
2008 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2009 0, false, &dividers);
2010 if (ret)
2011 pi->ref_div = dividers.ref_div + 1;
2012 else
2013 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2014
2015 pi->mclk_strobe_mode_threshold = 40000;
2016 pi->mclk_edc_enable_threshold = 40000;
2017 eg_pi->mclk_edc_wr_enable_threshold = 40000;
2018
f85392bc
AD		 2019 pi->rlp = RV770_RLP_DFLT;
2020 pi->rmp = RV770_RMP_DFLT;
2021 pi->lhp = RV770_LHP_DFLT;
2022 pi->lmp = RV770_LMP_DFLT;
2023
dc50ba7f
AD		 2024 pi->voltage_control =
2025 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);
2026
2027 pi->mvdd_control =
2028 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC);
2029
2030 eg_pi->vddci_control =
2031 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI);
2032
2033 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
2034 &frev, &crev, &data_offset)) {
2035 pi->sclk_ss = true;
2036 pi->mclk_ss = true;
2037 pi->dynamic_ss = true;
2038 } else {
2039 pi->sclk_ss = false;
2040 pi->mclk_ss = false;
2041 pi->dynamic_ss = true;
2042 }
2043
2044 pi->asi = RV770_ASI_DFLT;
2045 pi->pasi = CYPRESS_HASI_DFLT;
2046 pi->vrc = CYPRESS_VRC_DFLT;
2047
2048 pi->power_gating = false;
2049
2050 if ((rdev->family == CHIP_CYPRESS) ||
2051 (rdev->family == CHIP_HEMLOCK))
2052 pi->gfx_clock_gating = false;
2053 else
2054 pi->gfx_clock_gating = true;
2055
2056 pi->mg_clock_gating = true;
2057 pi->mgcgtssm = true;
2058 eg_pi->ls_clock_gating = false;
2059 eg_pi->sclk_deep_sleep = false;
2060
2061 pi->dynamic_pcie_gen2 = true;
2062
2063 if (pi->gfx_clock_gating &&
2064 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
2065 pi->thermal_protection = true;
2066 else
2067 pi->thermal_protection = false;
2068
2069 pi->display_gap = true;
2070
2071 if (rdev->flags & RADEON_IS_MOBILITY)
2072 pi->dcodt = true;
2073 else
2074 pi->dcodt = false;
2075
2076 pi->ulps = true;
2077
2078 eg_pi->dynamic_ac_timing = true;
2079 eg_pi->abm = true;
2080 eg_pi->mcls = true;
2081 eg_pi->light_sleep = true;
2082 eg_pi->memory_transition = true;
2083#if defined(CONFIG_ACPI)
2084 eg_pi->pcie_performance_request =
2085 radeon_acpi_is_pcie_performance_request_supported(rdev);
2086#else
2087 eg_pi->pcie_performance_request = false;
2088#endif
2089
2090 if ((rdev->family == CHIP_CYPRESS) ||
2091 (rdev->family == CHIP_HEMLOCK) ||
2092 (rdev->family == CHIP_JUNIPER))
2093 eg_pi->dll_default_on = true;
2094 else
2095 eg_pi->dll_default_on = false;
2096
2097 eg_pi->sclk_deep_sleep = false;
2098 pi->mclk_stutter_mode_threshold = 0;
2099
2100 pi->sram_end = SMC_RAM_END;
2101
2102 return 0;
2103}
2104
2105void cypress_dpm_fini(struct radeon_device *rdev)
2106{
2107 int i;
2108
2109 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2110 kfree(rdev->pm.dpm.ps[i].ps_priv);
2111 }
2112 kfree(rdev->pm.dpm.ps);
2113 kfree(rdev->pm.dpm.priv);
2114}
Linux 6.x block layer and io_uring tree(s)