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Merge remote-tracking branches 'regulator/topic/s2mps11', 'regulator/topic/s5m8767...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / cik_sdma.c
CommitLineData
2483b4ea
CK		 1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "radeon.h"
27#include "radeon_asic.h"
74d360f6 28#include "radeon_trace.h"
2483b4ea
CK		 29#include "cikd.h"
30
31/* sdma */
32#define CIK_SDMA_UCODE_SIZE 1050
33#define CIK_SDMA_UCODE_VERSION 64
34
35u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
36
37/*
38 * sDMA - System DMA
39 * Starting with CIK, the GPU has new asynchronous
40 * DMA engines. These engines are used for compute
41 * and gfx. There are two DMA engines (SDMA0, SDMA1)
42 * and each one supports 1 ring buffer used for gfx
43 * and 2 queues used for compute.
44 *
45 * The programming model is very similar to the CP
46 * (ring buffer, IBs, etc.), but sDMA has it's own
47 * packet format that is different from the PM4 format
48 * used by the CP. sDMA supports copying data, writing
49 * embedded data, solid fills, and a number of other
50 * things. It also has support for tiling/detiling of
51 * buffers.
52 */
53
54/**
55 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
56 *
57 * @rdev: radeon_device pointer
58 * @ib: IB object to schedule
59 *
60 * Schedule an IB in the DMA ring (CIK).
61 */
62void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
63 struct radeon_ib *ib)
64{
65 struct radeon_ring *ring = &rdev->ring[ib->ring];
66 u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf;
67
68 if (rdev->wb.enabled) {
69 u32 next_rptr = ring->wptr + 5;
70 while ((next_rptr & 7) != 4)
71 next_rptr++;
72 next_rptr += 4;
73 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
74 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
75 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
76 radeon_ring_write(ring, 1); /* number of DWs to follow */
77 radeon_ring_write(ring, next_rptr);
78 }
79
80 /* IB packet must end on a 8 DW boundary */
81 while ((ring->wptr & 7) != 4)
82 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
83 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
84 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
85 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
86 radeon_ring_write(ring, ib->length_dw);
87
88}
89
90/**
91 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
92 *
93 * @rdev: radeon_device pointer
94 * @fence: radeon fence object
95 *
96 * Add a DMA fence packet to the ring to write
97 * the fence seq number and DMA trap packet to generate
98 * an interrupt if needed (CIK).
99 */
100void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
101 struct radeon_fence *fence)
102{
103 struct radeon_ring *ring = &rdev->ring[fence->ring];
104 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2483b4ea
CK		 105
106 /* write the fence */
107 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
108 radeon_ring_write(ring, addr & 0xffffffff);
109 radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
110 radeon_ring_write(ring, fence->seq);
111 /* generate an interrupt */
112 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
113 /* flush HDP */
d45fd24d
AD		 114 /* We should be using the new POLL_REG_MEM special op packet here
115 * but it causes sDMA to hang sometimes
116 */
117 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
118 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
119 radeon_ring_write(ring, 0);
2483b4ea
CK		 120}
121
122/**
123 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
124 *
125 * @rdev: radeon_device pointer
126 * @ring: radeon_ring structure holding ring information
127 * @semaphore: radeon semaphore object
128 * @emit_wait: wait or signal semaphore
129 *
130 * Add a DMA semaphore packet to the ring wait on or signal
131 * other rings (CIK).
132 */
1654b817 133bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
2483b4ea
CK		 134 struct radeon_ring *ring,
135 struct radeon_semaphore *semaphore,
136 bool emit_wait)
137{
138 u64 addr = semaphore->gpu_addr;
139 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
140
141 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
142 radeon_ring_write(ring, addr & 0xfffffff8);
143 radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1654b817
CK		 144
145 return true;
2483b4ea
CK		 146}
147
148/**
149 * cik_sdma_gfx_stop - stop the gfx async dma engines
150 *
151 * @rdev: radeon_device pointer
152 *
153 * Stop the gfx async dma ring buffers (CIK).
154 */
155static void cik_sdma_gfx_stop(struct radeon_device *rdev)
156{
157 u32 rb_cntl, reg_offset;
158 int i;
159
160 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
161
162 for (i = 0; i < 2; i++) {
163 if (i == 0)
164 reg_offset = SDMA0_REGISTER_OFFSET;
165 else
166 reg_offset = SDMA1_REGISTER_OFFSET;
167 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
168 rb_cntl &= ~SDMA_RB_ENABLE;
169 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
170 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
171 }
172}
173
174/**
175 * cik_sdma_rlc_stop - stop the compute async dma engines
176 *
177 * @rdev: radeon_device pointer
178 *
179 * Stop the compute async dma queues (CIK).
180 */
181static void cik_sdma_rlc_stop(struct radeon_device *rdev)
182{
183 /* XXX todo */
184}
185
186/**
187 * cik_sdma_enable - stop the async dma engines
188 *
189 * @rdev: radeon_device pointer
190 * @enable: enable/disable the DMA MEs.
191 *
192 * Halt or unhalt the async dma engines (CIK).
193 */
194void cik_sdma_enable(struct radeon_device *rdev, bool enable)
195{
196 u32 me_cntl, reg_offset;
197 int i;
198
199 for (i = 0; i < 2; i++) {
200 if (i == 0)
201 reg_offset = SDMA0_REGISTER_OFFSET;
202 else
203 reg_offset = SDMA1_REGISTER_OFFSET;
204 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
205 if (enable)
206 me_cntl &= ~SDMA_HALT;
207 else
208 me_cntl |= SDMA_HALT;
209 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
210 }
211}
212
213/**
214 * cik_sdma_gfx_resume - setup and start the async dma engines
215 *
216 * @rdev: radeon_device pointer
217 *
218 * Set up the gfx DMA ring buffers and enable them (CIK).
219 * Returns 0 for success, error for failure.
220 */
221static int cik_sdma_gfx_resume(struct radeon_device *rdev)
222{
223 struct radeon_ring *ring;
224 u32 rb_cntl, ib_cntl;
225 u32 rb_bufsz;
226 u32 reg_offset, wb_offset;
227 int i, r;
228
229 for (i = 0; i < 2; i++) {
230 if (i == 0) {
231 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
232 reg_offset = SDMA0_REGISTER_OFFSET;
233 wb_offset = R600_WB_DMA_RPTR_OFFSET;
234 } else {
235 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
236 reg_offset = SDMA1_REGISTER_OFFSET;
237 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
238 }
239
240 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
241 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
242
243 /* Set ring buffer size in dwords */
9c725e5b 244 rb_bufsz = order_base_2(ring->ring_size / 4);
2483b4ea
CK		 245 rb_cntl = rb_bufsz << 1;
246#ifdef __BIG_ENDIAN
247 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
248#endif
249 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
250
251 /* Initialize the ring buffer's read and write pointers */
252 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
253 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
254
255 /* set the wb address whether it's enabled or not */
256 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
257 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
258 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
259 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
260
261 if (rdev->wb.enabled)
262 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
263
264 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
265 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
266
267 ring->wptr = 0;
268 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
269
270 ring->rptr = RREG32(SDMA0_GFX_RB_RPTR + reg_offset) >> 2;
271
272 /* enable DMA RB */
273 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
274
275 ib_cntl = SDMA_IB_ENABLE;
276#ifdef __BIG_ENDIAN
277 ib_cntl |= SDMA_IB_SWAP_ENABLE;
278#endif
279 /* enable DMA IBs */
280 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
281
282 ring->ready = true;
283
284 r = radeon_ring_test(rdev, ring->idx, ring);
285 if (r) {
286 ring->ready = false;
287 return r;
288 }
289 }
290
291 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
292
293 return 0;
294}
295
296/**
297 * cik_sdma_rlc_resume - setup and start the async dma engines
298 *
299 * @rdev: radeon_device pointer
300 *
301 * Set up the compute DMA queues and enable them (CIK).
302 * Returns 0 for success, error for failure.
303 */
304static int cik_sdma_rlc_resume(struct radeon_device *rdev)
305{
306 /* XXX todo */
307 return 0;
308}
309
310/**
311 * cik_sdma_load_microcode - load the sDMA ME ucode
312 *
313 * @rdev: radeon_device pointer
314 *
315 * Loads the sDMA0/1 ucode.
316 * Returns 0 for success, -EINVAL if the ucode is not available.
317 */
318static int cik_sdma_load_microcode(struct radeon_device *rdev)
319{
320 const __be32 *fw_data;
321 int i;
322
323 if (!rdev->sdma_fw)
324 return -EINVAL;
325
326 /* stop the gfx rings and rlc compute queues */
327 cik_sdma_gfx_stop(rdev);
328 cik_sdma_rlc_stop(rdev);
329
330 /* halt the MEs */
331 cik_sdma_enable(rdev, false);
332
333 /* sdma0 */
334 fw_data = (const __be32 *)rdev->sdma_fw->data;
335 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
336 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
337 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
338 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
339
340 /* sdma1 */
341 fw_data = (const __be32 *)rdev->sdma_fw->data;
342 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
343 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
344 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
345 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
346
347 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
348 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
349 return 0;
350}
351
352/**
353 * cik_sdma_resume - setup and start the async dma engines
354 *
355 * @rdev: radeon_device pointer
356 *
357 * Set up the DMA engines and enable them (CIK).
358 * Returns 0 for success, error for failure.
359 */
360int cik_sdma_resume(struct radeon_device *rdev)
361{
362 int r;
363
364 /* Reset dma */
365 WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
366 RREG32(SRBM_SOFT_RESET);
367 udelay(50);
368 WREG32(SRBM_SOFT_RESET, 0);
369 RREG32(SRBM_SOFT_RESET);
370
371 r = cik_sdma_load_microcode(rdev);
372 if (r)
373 return r;
374
375 /* unhalt the MEs */
376 cik_sdma_enable(rdev, true);
377
378 /* start the gfx rings and rlc compute queues */
379 r = cik_sdma_gfx_resume(rdev);
380 if (r)
381 return r;
382 r = cik_sdma_rlc_resume(rdev);
383 if (r)
384 return r;
385
386 return 0;
387}
388
389/**
390 * cik_sdma_fini - tear down the async dma engines
391 *
392 * @rdev: radeon_device pointer
393 *
394 * Stop the async dma engines and free the rings (CIK).
395 */
396void cik_sdma_fini(struct radeon_device *rdev)
397{
398 /* stop the gfx rings and rlc compute queues */
399 cik_sdma_gfx_stop(rdev);
400 cik_sdma_rlc_stop(rdev);
401 /* halt the MEs */
402 cik_sdma_enable(rdev, false);
403 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
404 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
405 /* XXX - compute dma queue tear down */
406}
407
408/**
409 * cik_copy_dma - copy pages using the DMA engine
410 *
411 * @rdev: radeon_device pointer
412 * @src_offset: src GPU address
413 * @dst_offset: dst GPU address
414 * @num_gpu_pages: number of GPU pages to xfer
415 * @fence: radeon fence object
416 *
417 * Copy GPU paging using the DMA engine (CIK).
418 * Used by the radeon ttm implementation to move pages if
419 * registered as the asic copy callback.
420 */
421int cik_copy_dma(struct radeon_device *rdev,
422 uint64_t src_offset, uint64_t dst_offset,
423 unsigned num_gpu_pages,
424 struct radeon_fence **fence)
425{
426 struct radeon_semaphore *sem = NULL;
427 int ring_index = rdev->asic->copy.dma_ring_index;
428 struct radeon_ring *ring = &rdev->ring[ring_index];
429 u32 size_in_bytes, cur_size_in_bytes;
430 int i, num_loops;
431 int r = 0;
432
433 r = radeon_semaphore_create(rdev, &sem);
434 if (r) {
435 DRM_ERROR("radeon: moving bo (%d).\n", r);
436 return r;
437 }
438
439 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
440 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
441 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
442 if (r) {
443 DRM_ERROR("radeon: moving bo (%d).\n", r);
444 radeon_semaphore_free(rdev, &sem, NULL);
445 return r;
446 }
447
1654b817
CK		 448 radeon_semaphore_sync_to(sem, *fence);
449 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
2483b4ea
CK		 450
451 for (i = 0; i < num_loops; i++) {
452 cur_size_in_bytes = size_in_bytes;
453 if (cur_size_in_bytes > 0x1fffff)
454 cur_size_in_bytes = 0x1fffff;
455 size_in_bytes -= cur_size_in_bytes;
456 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
457 radeon_ring_write(ring, cur_size_in_bytes);
458 radeon_ring_write(ring, 0); /* src/dst endian swap */
459 radeon_ring_write(ring, src_offset & 0xffffffff);
460 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);
1b3abef8 461 radeon_ring_write(ring, dst_offset & 0xffffffff);
2483b4ea
CK		 462 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);
463 src_offset += cur_size_in_bytes;
464 dst_offset += cur_size_in_bytes;
465 }
466
467 r = radeon_fence_emit(rdev, fence, ring->idx);
468 if (r) {
469 radeon_ring_unlock_undo(rdev, ring);
470 return r;
471 }
472
473 radeon_ring_unlock_commit(rdev, ring);
474 radeon_semaphore_free(rdev, &sem, *fence);
475
476 return r;
477}
478
479/**
480 * cik_sdma_ring_test - simple async dma engine test
481 *
482 * @rdev: radeon_device pointer
483 * @ring: radeon_ring structure holding ring information
484 *
485 * Test the DMA engine by writing using it to write an
486 * value to memory. (CIK).
487 * Returns 0 for success, error for failure.
488 */
489int cik_sdma_ring_test(struct radeon_device *rdev,
490 struct radeon_ring *ring)
491{
492 unsigned i;
493 int r;
494 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
495 u32 tmp;
496
497 if (!ptr) {
498 DRM_ERROR("invalid vram scratch pointer\n");
499 return -EINVAL;
500 }
501
502 tmp = 0xCAFEDEAD;
503 writel(tmp, ptr);
504
505 r = radeon_ring_lock(rdev, ring, 4);
506 if (r) {
507 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
508 return r;
509 }
510 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
511 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
512 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff);
513 radeon_ring_write(ring, 1); /* number of DWs to follow */
514 radeon_ring_write(ring, 0xDEADBEEF);
515 radeon_ring_unlock_commit(rdev, ring);
516
517 for (i = 0; i < rdev->usec_timeout; i++) {
518 tmp = readl(ptr);
519 if (tmp == 0xDEADBEEF)
520 break;
521 DRM_UDELAY(1);
522 }
523
524 if (i < rdev->usec_timeout) {
525 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
526 } else {
527 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
528 ring->idx, tmp);
529 r = -EINVAL;
530 }
531 return r;
532}
533
534/**
535 * cik_sdma_ib_test - test an IB on the DMA engine
536 *
537 * @rdev: radeon_device pointer
538 * @ring: radeon_ring structure holding ring information
539 *
540 * Test a simple IB in the DMA ring (CIK).
541 * Returns 0 on success, error on failure.
542 */
543int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
544{
545 struct radeon_ib ib;
546 unsigned i;
547 int r;
548 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
549 u32 tmp = 0;
550
551 if (!ptr) {
552 DRM_ERROR("invalid vram scratch pointer\n");
553 return -EINVAL;
554 }
555
556 tmp = 0xCAFEDEAD;
557 writel(tmp, ptr);
558
559 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
560 if (r) {
561 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
562 return r;
563 }
564
565 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
566 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
567 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff;
568 ib.ptr[3] = 1;
569 ib.ptr[4] = 0xDEADBEEF;
570 ib.length_dw = 5;
571
572 r = radeon_ib_schedule(rdev, &ib, NULL);
573 if (r) {
574 radeon_ib_free(rdev, &ib);
575 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
576 return r;
577 }
578 r = radeon_fence_wait(ib.fence, false);
579 if (r) {
580 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
581 return r;
582 }
583 for (i = 0; i < rdev->usec_timeout; i++) {
584 tmp = readl(ptr);
585 if (tmp == 0xDEADBEEF)
586 break;
587 DRM_UDELAY(1);
588 }
589 if (i < rdev->usec_timeout) {
590 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
591 } else {
592 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
593 r = -EINVAL;
594 }
595 radeon_ib_free(rdev, &ib);
596 return r;
597}
598
599/**
600 * cik_sdma_is_lockup - Check if the DMA engine is locked up
601 *
602 * @rdev: radeon_device pointer
603 * @ring: radeon_ring structure holding ring information
604 *
605 * Check if the async DMA engine is locked up (CIK).
606 * Returns true if the engine appears to be locked up, false if not.
607 */
608bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
609{
610 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
611 u32 mask;
612
613 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
614 mask = RADEON_RESET_DMA;
615 else
616 mask = RADEON_RESET_DMA1;
617
618 if (!(reset_mask & mask)) {
619 radeon_ring_lockup_update(ring);
620 return false;
621 }
622 /* force ring activities */
623 radeon_ring_force_activity(rdev, ring);
624 return radeon_ring_test_lockup(rdev, ring);
625}
626
627/**
628 * cik_sdma_vm_set_page - update the page tables using sDMA
629 *
630 * @rdev: radeon_device pointer
631 * @ib: indirect buffer to fill with commands
632 * @pe: addr of the page entry
633 * @addr: dst addr to write into pe
634 * @count: number of page entries to update
635 * @incr: increase next addr by incr bytes
636 * @flags: access flags
637 *
638 * Update the page tables using sDMA (CIK).
639 */
640void cik_sdma_vm_set_page(struct radeon_device *rdev,
641 struct radeon_ib *ib,
642 uint64_t pe,
643 uint64_t addr, unsigned count,
644 uint32_t incr, uint32_t flags)
645{
2483b4ea
CK		 646 uint64_t value;
647 unsigned ndw;
648
24c16439 649 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
74d360f6 650
24c16439 651 if (flags & R600_PTE_SYSTEM) {
2483b4ea
CK		 652 while (count) {
653 ndw = count * 2;
654 if (ndw > 0xFFFFE)
655 ndw = 0xFFFFE;
656
657 /* for non-physically contiguous pages (system) */
658 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
659 ib->ptr[ib->length_dw++] = pe;
660 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
661 ib->ptr[ib->length_dw++] = ndw;
662 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
24c16439
CK		 663 value = radeon_vm_map_gart(rdev, addr);
664 value &= 0xFFFFFFFFFFFFF000ULL;
2483b4ea 665 addr += incr;
24c16439 666 value |= flags;
2483b4ea
CK		 667 ib->ptr[ib->length_dw++] = value;
668 ib->ptr[ib->length_dw++] = upper_32_bits(value);
669 }
670 }
671 } else {
672 while (count) {
673 ndw = count;
674 if (ndw > 0x7FFFF)
675 ndw = 0x7FFFF;
676
24c16439 677 if (flags & R600_PTE_VALID)
2483b4ea
CK		 678 value = addr;
679 else
680 value = 0;
681 /* for physically contiguous pages (vram) */
682 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
683 ib->ptr[ib->length_dw++] = pe; /* dst addr */
684 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
24c16439 685 ib->ptr[ib->length_dw++] = flags; /* mask */
2483b4ea
CK		 686 ib->ptr[ib->length_dw++] = 0;
687 ib->ptr[ib->length_dw++] = value; /* value */
688 ib->ptr[ib->length_dw++] = upper_32_bits(value);
689 ib->ptr[ib->length_dw++] = incr; /* increment size */
690 ib->ptr[ib->length_dw++] = 0;
691 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
692 pe += ndw * 8;
693 addr += ndw * incr;
694 count -= ndw;
695 }
696 }
697 while (ib->length_dw & 0x7)
698 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
699}
700
701/**
702 * cik_dma_vm_flush - cik vm flush using sDMA
703 *
704 * @rdev: radeon_device pointer
705 *
706 * Update the page table base and flush the VM TLB
707 * using sDMA (CIK).
708 */
709void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
710{
711 struct radeon_ring *ring = &rdev->ring[ridx];
2483b4ea
CK		 712
713 if (vm == NULL)
714 return;
715
2483b4ea
CK		 716 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
717 if (vm->id < 8) {
718 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
719 } else {
720 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
721 }
722 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
723
724 /* update SH_MEM_* regs */
725 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
726 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
727 radeon_ring_write(ring, VMID(vm->id));
728
729 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
730 radeon_ring_write(ring, SH_MEM_BASES >> 2);
731 radeon_ring_write(ring, 0);
732
733 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
734 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
735 radeon_ring_write(ring, 0);
736
737 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
738 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
739 radeon_ring_write(ring, 1);
740
741 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
742 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
743 radeon_ring_write(ring, 0);
744
745 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
746 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
747 radeon_ring_write(ring, VMID(0));
748
749 /* flush HDP */
d45fd24d
AD		 750 /* We should be using the new POLL_REG_MEM special op packet here
751 * but it causes sDMA to hang sometimes
752 */
753 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
754 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
755 radeon_ring_write(ring, 0);
2483b4ea
CK		 756
757 /* flush TLB */
758 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
759 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
760 radeon_ring_write(ring, 1 << vm->id);
761}
762
Linux 6.x block layer and io_uring tree(s)