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drm/radeon: add audio support for DCE6/8 GPUs (v12)
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8
AD		 29#include "radeon.h"
30#include "atom.h"
f3728734 31#include <linux/backlight.h>
3f03ced8
AD		 32
33extern int atom_debug;
34
f3728734
AD		 35static u8
36radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37{
38 u8 backlight_level;
39 u32 bios_2_scratch;
40
41 if (rdev->family >= CHIP_R600)
42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 else
44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45
46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48
49 return backlight_level;
50}
51
52static void
53radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 u8 backlight_level)
55{
56 u32 bios_2_scratch;
57
58 if (rdev->family >= CHIP_R600)
59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 else
61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62
63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 ATOM_S2_CURRENT_BL_LEVEL_MASK);
66
67 if (rdev->family >= CHIP_R600)
68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 else
70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71}
72
6d92f81d
AD		 73u8
74atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75{
76 struct drm_device *dev = radeon_encoder->base.dev;
77 struct radeon_device *rdev = dev->dev_private;
78
79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 return 0;
81
82 return radeon_atom_get_backlight_level_from_reg(rdev);
83}
84
fda4b25c 85void
37e9b6a6 86atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 87{
88 struct drm_encoder *encoder = &radeon_encoder->base;
89 struct drm_device *dev = radeon_encoder->base.dev;
90 struct radeon_device *rdev = dev->dev_private;
91 struct radeon_encoder_atom_dig *dig;
92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 int index;
94
37e9b6a6
AD		 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 return;
97
98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 radeon_encoder->enc_priv) {
f3728734 100 dig = radeon_encoder->enc_priv;
37e9b6a6 101 dig->backlight_level = level;
f3728734
AD		 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103
104 switch (radeon_encoder->encoder_id) {
105 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 if (dig->backlight_level == 0) {
109 args.ucAction = ATOM_LCD_BLOFF;
110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 } else {
112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 args.ucAction = ATOM_LCD_BLON;
115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 }
117 break;
118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 if (dig->backlight_level == 0)
123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
124 else {
125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
127 }
128 break;
129 default:
130 break;
131 }
132 }
133}
134
bced76f2
AD		 135#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
136
f3728734
AD		 137static u8 radeon_atom_bl_level(struct backlight_device *bd)
138{
139 u8 level;
140
141 /* Convert brightness to hardware level */
142 if (bd->props.brightness < 0)
143 level = 0;
144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
145 level = RADEON_MAX_BL_LEVEL;
146 else
147 level = bd->props.brightness;
148
149 return level;
150}
151
152static int radeon_atom_backlight_update_status(struct backlight_device *bd)
153{
154 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
155 struct radeon_encoder *radeon_encoder = pdata->encoder;
156
37e9b6a6 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 158
159 return 0;
160}
161
162static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
163{
164 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
165 struct radeon_encoder *radeon_encoder = pdata->encoder;
166 struct drm_device *dev = radeon_encoder->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168
169 return radeon_atom_get_backlight_level_from_reg(rdev);
170}
171
172static const struct backlight_ops radeon_atom_backlight_ops = {
173 .get_brightness = radeon_atom_backlight_get_brightness,
174 .update_status = radeon_atom_backlight_update_status,
175};
176
177void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
178 struct drm_connector *drm_connector)
179{
180 struct drm_device *dev = radeon_encoder->base.dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct backlight_device *bd;
183 struct backlight_properties props;
184 struct radeon_backlight_privdata *pdata;
185 struct radeon_encoder_atom_dig *dig;
186 u8 backlight_level;
614499b4 187 char bl_name[16];
f3728734 188
80101790
AD		 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
f3728734
AD		 196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
614499b4
AD		 214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
216 bd = backlight_device_register(bl_name, &drm_connector->kdev,
f3728734
AD		 217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
225 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
226
227 dig = radeon_encoder->enc_priv;
228 dig->bl_dev = bd;
229
230 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
231 bd->props.power = FB_BLANK_UNBLANK;
232 backlight_update_status(bd);
233
234 DRM_INFO("radeon atom DIG backlight initialized\n");
235
236 return;
237
238error:
239 kfree(pdata);
240 return;
241}
242
243static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
244{
245 struct drm_device *dev = radeon_encoder->base.dev;
246 struct radeon_device *rdev = dev->dev_private;
247 struct backlight_device *bd = NULL;
248 struct radeon_encoder_atom_dig *dig;
249
250 if (!radeon_encoder->enc_priv)
251 return;
252
253 if (!rdev->is_atom_bios)
254 return;
255
256 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
257 return;
258
259 dig = radeon_encoder->enc_priv;
260 bd = dig->bl_dev;
261 dig->bl_dev = NULL;
262
263 if (bd) {
264 struct radeon_legacy_backlight_privdata *pdata;
265
266 pdata = bl_get_data(bd);
267 backlight_device_unregister(bd);
268 kfree(pdata);
269
270 DRM_INFO("radeon atom LVDS backlight unloaded\n");
271 }
272}
273
274#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
275
276void radeon_atom_backlight_init(struct radeon_encoder *encoder)
277{
278}
279
280static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
281{
282}
283
284#endif
285
3f03ced8
AD		 286/* evil but including atombios.h is much worse */
287bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
288 struct drm_display_mode *mode);
289
290
291static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
292{
293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 switch (radeon_encoder->encoder_id) {
295 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
296 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
297 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
298 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
299 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
300 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
301 case ENCODER_OBJECT_ID_INTERNAL_DDI:
302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
303 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 306 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 307 return true;
308 default:
309 return false;
310 }
311}
312
3f03ced8 313static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 314 const struct drm_display_mode *mode,
3f03ced8
AD		 315 struct drm_display_mode *adjusted_mode)
316{
317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
318 struct drm_device *dev = encoder->dev;
319 struct radeon_device *rdev = dev->dev_private;
320
321 /* set the active encoder to connector routing */
322 radeon_encoder_set_active_device(encoder);
323 drm_mode_set_crtcinfo(adjusted_mode, 0);
324
325 /* hw bug */
326 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
327 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
328 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
329
330 /* get the native mode for LVDS */
331 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
332 radeon_panel_mode_fixup(encoder, adjusted_mode);
333
334 /* get the native mode for TV */
335 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
336 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
337 if (tv_dac) {
338 if (tv_dac->tv_std == TV_STD_NTSC ||
339 tv_dac->tv_std == TV_STD_NTSC_J ||
340 tv_dac->tv_std == TV_STD_PAL_M)
341 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
342 else
343 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
344 }
345 }
346
347 if (ASIC_IS_DCE3(rdev) &&
348 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
349 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
350 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 351 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 352 }
353
354 return true;
355}
356
357static void
358atombios_dac_setup(struct drm_encoder *encoder, int action)
359{
360 struct drm_device *dev = encoder->dev;
361 struct radeon_device *rdev = dev->dev_private;
362 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
363 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
364 int index = 0;
365 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
366
367 memset(&args, 0, sizeof(args));
368
369 switch (radeon_encoder->encoder_id) {
370 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
371 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
372 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
373 break;
374 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
375 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
376 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
377 break;
378 }
379
380 args.ucAction = action;
381
382 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
383 args.ucDacStandard = ATOM_DAC1_PS2;
384 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
385 args.ucDacStandard = ATOM_DAC1_CV;
386 else {
387 switch (dac_info->tv_std) {
388 case TV_STD_PAL:
389 case TV_STD_PAL_M:
390 case TV_STD_SCART_PAL:
391 case TV_STD_SECAM:
392 case TV_STD_PAL_CN:
393 args.ucDacStandard = ATOM_DAC1_PAL;
394 break;
395 case TV_STD_NTSC:
396 case TV_STD_NTSC_J:
397 case TV_STD_PAL_60:
398 default:
399 args.ucDacStandard = ATOM_DAC1_NTSC;
400 break;
401 }
402 }
403 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
404
405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
406
407}
408
409static void
410atombios_tv_setup(struct drm_encoder *encoder, int action)
411{
412 struct drm_device *dev = encoder->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
415 TV_ENCODER_CONTROL_PS_ALLOCATION args;
416 int index = 0;
417 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
418
419 memset(&args, 0, sizeof(args));
420
421 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
422
423 args.sTVEncoder.ucAction = action;
424
425 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
426 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
427 else {
428 switch (dac_info->tv_std) {
429 case TV_STD_NTSC:
430 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
431 break;
432 case TV_STD_PAL:
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
434 break;
435 case TV_STD_PAL_M:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
437 break;
438 case TV_STD_PAL_60:
439 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
440 break;
441 case TV_STD_NTSC_J:
442 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
443 break;
444 case TV_STD_SCART_PAL:
445 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
446 break;
447 case TV_STD_SECAM:
448 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
449 break;
450 case TV_STD_PAL_CN:
451 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
452 break;
453 default:
454 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
455 break;
456 }
457 }
458
459 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
460
461 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
462
463}
464
1f0e2943
AD		 465static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
466{
467 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
468 int bpc = 8;
469
470 if (connector)
471 bpc = radeon_get_monitor_bpc(connector);
472
473 switch (bpc) {
474 case 0:
475 return PANEL_BPC_UNDEFINE;
476 case 6:
477 return PANEL_6BIT_PER_COLOR;
478 case 8:
479 default:
480 return PANEL_8BIT_PER_COLOR;
481 case 10:
482 return PANEL_10BIT_PER_COLOR;
483 case 12:
484 return PANEL_12BIT_PER_COLOR;
485 case 16:
486 return PANEL_16BIT_PER_COLOR;
487 }
488}
489
3f03ced8
AD		 490union dvo_encoder_control {
491 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
492 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
493 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
aea65641 494 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
3f03ced8
AD		 495};
496
497void
498atombios_dvo_setup(struct drm_encoder *encoder, int action)
499{
500 struct drm_device *dev = encoder->dev;
501 struct radeon_device *rdev = dev->dev_private;
502 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
503 union dvo_encoder_control args;
504 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 505 uint8_t frev, crev;
3f03ced8
AD		 506
507 memset(&args, 0, sizeof(args));
508
24153dd3
AD		 509 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
510 return;
511
afceb931
AD		 512 /* some R4xx chips have the wrong frev */
513 if (rdev->family <= CHIP_RV410)
514 frev = 1;
515
24153dd3
AD		 516 switch (frev) {
517 case 1:
518 switch (crev) {
519 case 1:
520 /* R4xx, R5xx */
521 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
522
9aa59993 523 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 524 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
525
526 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
527 break;
528 case 2:
529 /* RS600/690/740 */
530 args.dvo.sDVOEncoder.ucAction = action;
531 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
532 /* DFP1, CRT1, TV1 depending on the type of port */
533 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
534
9aa59993 535 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 536 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
537 break;
538 case 3:
539 /* R6xx */
540 args.dvo_v3.ucAction = action;
541 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
542 args.dvo_v3.ucDVOConfig = 0; /* XXX */
543 break;
aea65641
AD		 544 case 4:
545 /* DCE8 */
546 args.dvo_v4.ucAction = action;
547 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
548 args.dvo_v4.ucDVOConfig = 0; /* XXX */
549 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
550 break;
24153dd3
AD		 551 default:
552 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
553 break;
554 }
555 break;
556 default:
557 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
558 break;
3f03ced8
AD		 559 }
560
561 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
562}
563
564union lvds_encoder_control {
565 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
566 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
567};
568
569void
570atombios_digital_setup(struct drm_encoder *encoder, int action)
571{
572 struct drm_device *dev = encoder->dev;
573 struct radeon_device *rdev = dev->dev_private;
574 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
575 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
576 union lvds_encoder_control args;
577 int index = 0;
578 int hdmi_detected = 0;
579 uint8_t frev, crev;
580
581 if (!dig)
582 return;
583
584 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
585 hdmi_detected = 1;
586
587 memset(&args, 0, sizeof(args));
588
589 switch (radeon_encoder->encoder_id) {
590 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
591 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
592 break;
593 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
594 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
595 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
596 break;
597 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
599 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
600 else
601 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
602 break;
603 }
604
605 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
606 return;
607
608 switch (frev) {
609 case 1:
610 case 2:
611 switch (crev) {
612 case 1:
613 args.v1.ucMisc = 0;
614 args.v1.ucAction = action;
615 if (hdmi_detected)
616 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
617 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
618 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
619 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
620 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
621 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
622 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
623 } else {
624 if (dig->linkb)
625 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 626 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 627 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
628 /*if (pScrn->rgbBits == 8) */
629 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
630 }
631 break;
632 case 2:
633 case 3:
634 args.v2.ucMisc = 0;
635 args.v2.ucAction = action;
636 if (crev == 3) {
637 if (dig->coherent_mode)
638 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
639 }
640 if (hdmi_detected)
641 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
642 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
643 args.v2.ucTruncate = 0;
644 args.v2.ucSpatial = 0;
645 args.v2.ucTemporal = 0;
646 args.v2.ucFRC = 0;
647 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
648 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
650 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
651 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
652 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
653 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
654 }
655 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
656 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
657 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
658 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
659 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
660 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
661 }
662 } else {
663 if (dig->linkb)
664 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 665 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 666 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
667 }
668 break;
669 default:
670 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
671 break;
672 }
673 break;
674 default:
675 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
676 break;
677 }
678
679 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
680}
681
682int
683atombios_get_encoder_mode(struct drm_encoder *encoder)
684{
685 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 686 struct drm_connector *connector;
687 struct radeon_connector *radeon_connector;
688 struct radeon_connector_atom_dig *dig_connector;
689
690 /* dp bridges are always DP */
691 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
692 return ATOM_ENCODER_MODE_DP;
693
694 /* DVO is always DVO */
a59fbb8e
AD		 695 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
696 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 697 return ATOM_ENCODER_MODE_DVO;
698
699 connector = radeon_get_connector_for_encoder(encoder);
700 /* if we don't have an active device yet, just use one of
701 * the connectors tied to the encoder.
702 */
703 if (!connector)
704 connector = radeon_get_connector_for_encoder_init(encoder);
705 radeon_connector = to_radeon_connector(connector);
706
707 switch (connector->connector_type) {
708 case DRM_MODE_CONNECTOR_DVII:
709 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
27d9cc84 710 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
b530602f 711 radeon_audio)
f92e70ca
RM		 712 return ATOM_ENCODER_MODE_HDMI;
713 else if (radeon_connector->use_digital)
3f03ced8
AD		 714 return ATOM_ENCODER_MODE_DVI;
715 else
716 return ATOM_ENCODER_MODE_CRT;
717 break;
718 case DRM_MODE_CONNECTOR_DVID:
719 case DRM_MODE_CONNECTOR_HDMIA:
720 default:
27d9cc84 721 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
b530602f 722 radeon_audio)
f92e70ca
RM		 723 return ATOM_ENCODER_MODE_HDMI;
724 else
3f03ced8
AD		 725 return ATOM_ENCODER_MODE_DVI;
726 break;
727 case DRM_MODE_CONNECTOR_LVDS:
728 return ATOM_ENCODER_MODE_LVDS;
729 break;
730 case DRM_MODE_CONNECTOR_DisplayPort:
731 dig_connector = radeon_connector->con_priv;
732 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
733 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
734 return ATOM_ENCODER_MODE_DP;
27d9cc84 735 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
b530602f 736 radeon_audio)
f92e70ca
RM		 737 return ATOM_ENCODER_MODE_HDMI;
738 else
3f03ced8
AD		 739 return ATOM_ENCODER_MODE_DVI;
740 break;
741 case DRM_MODE_CONNECTOR_eDP:
742 return ATOM_ENCODER_MODE_DP;
743 case DRM_MODE_CONNECTOR_DVIA:
744 case DRM_MODE_CONNECTOR_VGA:
745 return ATOM_ENCODER_MODE_CRT;
746 break;
747 case DRM_MODE_CONNECTOR_Composite:
748 case DRM_MODE_CONNECTOR_SVIDEO:
749 case DRM_MODE_CONNECTOR_9PinDIN:
750 /* fix me */
751 return ATOM_ENCODER_MODE_TV;
752 /*return ATOM_ENCODER_MODE_CV;*/
753 break;
754 }
755}
756
757/*
758 * DIG Encoder/Transmitter Setup
759 *
760 * DCE 3.0/3.1
761 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
762 * Supports up to 3 digital outputs
763 * - 2 DIG encoder blocks.
764 * DIG1 can drive UNIPHY link A or link B
765 * DIG2 can drive UNIPHY link B or LVTMA
766 *
767 * DCE 3.2
768 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
769 * Supports up to 5 digital outputs
770 * - 2 DIG encoder blocks.
771 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
772 *
2d415869 773 * DCE 4.0/5.0/6.0
3f03ced8
AD		 774 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
775 * Supports up to 6 digital outputs
776 * - 6 DIG encoder blocks.
777 * - DIG to PHY mapping is hardcoded
778 * DIG1 drives UNIPHY0 link A, A+B
779 * DIG2 drives UNIPHY0 link B
780 * DIG3 drives UNIPHY1 link A, A+B
781 * DIG4 drives UNIPHY1 link B
782 * DIG5 drives UNIPHY2 link A, A+B
783 * DIG6 drives UNIPHY2 link B
784 *
785 * DCE 4.1
786 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
787 * Supports up to 6 digital outputs
788 * - 2 DIG encoder blocks.
2d415869 789 * llano
3f03ced8 790 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 791 * ontario
792 * DIG1 drives UNIPHY0/1/2 link A
793 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 794 *
795 * Routing
796 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
797 * Examples:
798 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
799 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
800 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
801 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
802 */
803
804union dig_encoder_control {
805 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
806 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
807 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
808 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
809};
810
811void
812atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
813{
814 struct drm_device *dev = encoder->dev;
815 struct radeon_device *rdev = dev->dev_private;
816 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
817 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
818 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
819 union dig_encoder_control args;
820 int index = 0;
821 uint8_t frev, crev;
822 int dp_clock = 0;
823 int dp_lane_count = 0;
824 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 825
826 if (connector) {
827 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
828 struct radeon_connector_atom_dig *dig_connector =
829 radeon_connector->con_priv;
830
831 dp_clock = dig_connector->dp_clock;
832 dp_lane_count = dig_connector->dp_lane_count;
833 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 834 }
835
836 /* no dig encoder assigned */
837 if (dig->dig_encoder == -1)
838 return;
839
840 memset(&args, 0, sizeof(args));
841
842 if (ASIC_IS_DCE4(rdev))
843 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
844 else {
845 if (dig->dig_encoder)
846 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
847 else
848 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
849 }
850
851 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
852 return;
853
58cdcb8b
AD		 854 switch (frev) {
855 case 1:
856 switch (crev) {
857 case 1:
858 args.v1.ucAction = action;
859 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
860 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
861 args.v3.ucPanelMode = panel_mode;
862 else
863 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
864
865 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
866 args.v1.ucLaneNum = dp_lane_count;
9aa59993 867 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 868 args.v1.ucLaneNum = 8;
869 else
870 args.v1.ucLaneNum = 4;
871
872 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
873 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
874 switch (radeon_encoder->encoder_id) {
875 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
876 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
877 break;
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
880 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
881 break;
882 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
883 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
884 break;
885 }
886 if (dig->linkb)
887 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
888 else
889 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 890 break;
58cdcb8b
AD		 891 case 2:
892 case 3:
893 args.v3.ucAction = action;
894 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
895 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
896 args.v3.ucPanelMode = panel_mode;
897 else
898 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
899
2f6fa79a 900 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 901 args.v3.ucLaneNum = dp_lane_count;
9aa59993 902 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 903 args.v3.ucLaneNum = 8;
904 else
905 args.v3.ucLaneNum = 4;
906
2f6fa79a 907 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 908 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
909 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 910 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 911 break;
58cdcb8b
AD		 912 case 4:
913 args.v4.ucAction = action;
914 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
915 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
916 args.v4.ucPanelMode = panel_mode;
917 else
918 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
919
2f6fa79a 920 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 921 args.v4.ucLaneNum = dp_lane_count;
9aa59993 922 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 923 args.v4.ucLaneNum = 8;
924 else
925 args.v4.ucLaneNum = 4;
926
2f6fa79a 927 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
e68adef8 928 if (dp_clock == 540000)
58cdcb8b 929 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
e68adef8
AD		 930 else if (dp_clock == 324000)
931 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
932 else if (dp_clock == 270000)
933 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
934 else
935 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
58cdcb8b
AD		 936 }
937 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 938 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 939 if (hpd_id == RADEON_HPD_NONE)
940 args.v4.ucHPD_ID = 0;
941 else
942 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 943 break;
3f03ced8 944 default:
58cdcb8b 945 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 946 break;
947 }
58cdcb8b
AD		 948 break;
949 default:
950 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
951 break;
3f03ced8
AD		 952 }
953
954 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
955
956}
957
958union dig_transmitter_control {
959 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
960 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
961 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
962 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 963 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 964};
965
966void
967atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
968{
969 struct drm_device *dev = encoder->dev;
970 struct radeon_device *rdev = dev->dev_private;
971 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
972 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
973 struct drm_connector *connector;
974 union dig_transmitter_control args;
975 int index = 0;
976 uint8_t frev, crev;
977 bool is_dp = false;
978 int pll_id = 0;
979 int dp_clock = 0;
980 int dp_lane_count = 0;
981 int connector_object_id = 0;
982 int igp_lane_info = 0;
983 int dig_encoder = dig->dig_encoder;
47aef7a8 984 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 985
986 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
987 connector = radeon_get_connector_for_encoder_init(encoder);
988 /* just needed to avoid bailing in the encoder check. the encoder
989 * isn't used for init
990 */
991 dig_encoder = 0;
992 } else
993 connector = radeon_get_connector_for_encoder(encoder);
994
995 if (connector) {
996 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
997 struct radeon_connector_atom_dig *dig_connector =
998 radeon_connector->con_priv;
999
47aef7a8 1000 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 1001 dp_clock = dig_connector->dp_clock;
1002 dp_lane_count = dig_connector->dp_lane_count;
1003 connector_object_id =
1004 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1005 igp_lane_info = dig_connector->igp_lane_info;
1006 }
1007
a3b08294
AD		 1008 if (encoder->crtc) {
1009 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1010 pll_id = radeon_crtc->pll_id;
1011 }
1012
3f03ced8
AD		 1013 /* no dig encoder assigned */
1014 if (dig_encoder == -1)
1015 return;
1016
1017 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1018 is_dp = true;
1019
1020 memset(&args, 0, sizeof(args));
1021
1022 switch (radeon_encoder->encoder_id) {
1023 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1024 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1025 break;
1026 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1027 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1028 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1029 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1030 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1031 break;
1032 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1033 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1034 break;
1035 }
1036
1037 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1038 return;
1039
a3b08294
AD		 1040 switch (frev) {
1041 case 1:
1042 switch (crev) {
1043 case 1:
1044 args.v1.ucAction = action;
1045 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1046 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1047 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1048 args.v1.asMode.ucLaneSel = lane_num;
1049 args.v1.asMode.ucLaneSet = lane_set;
1050 } else {
1051 if (is_dp)
6e76a2df 1052 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1053 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1054 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1055 else
1056 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1057 }
3f03ced8 1058
a3b08294 1059 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1060
a3b08294
AD		 1061 if (dig_encoder)
1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1063 else
1064 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1065
1066 if ((rdev->flags & RADEON_IS_IGP) &&
1067 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1068 if (is_dp ||
1069 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1070 if (igp_lane_info & 0x1)
1071 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1072 else if (igp_lane_info & 0x2)
1073 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1074 else if (igp_lane_info & 0x4)
1075 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1076 else if (igp_lane_info & 0x8)
1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1078 } else {
1079 if (igp_lane_info & 0x3)
1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1081 else if (igp_lane_info & 0xc)
1082 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1083 }
1084 }
1085
1086 if (dig->linkb)
1087 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1088 else
1089 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1090
1091 if (is_dp)
1092 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1093 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1094 if (dig->coherent_mode)
1095 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1096 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1098 }
1099 break;
1100 case 2:
1101 args.v2.ucAction = action;
1102 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1103 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1104 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1105 args.v2.asMode.ucLaneSel = lane_num;
1106 args.v2.asMode.ucLaneSet = lane_set;
1107 } else {
1108 if (is_dp)
6e76a2df 1109 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1110 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1111 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1112 else
1113 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1114 }
1115
1116 args.v2.acConfig.ucEncoderSel = dig_encoder;
1117 if (dig->linkb)
1118 args.v2.acConfig.ucLinkSel = 1;
1119
1120 switch (radeon_encoder->encoder_id) {
1121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1122 args.v2.acConfig.ucTransmitterSel = 0;
1123 break;
1124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1125 args.v2.acConfig.ucTransmitterSel = 1;
1126 break;
1127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1128 args.v2.acConfig.ucTransmitterSel = 2;
1129 break;
1130 }
3f03ced8 1131
3f03ced8 1132 if (is_dp) {
a3b08294
AD		 1133 args.v2.acConfig.fCoherentMode = 1;
1134 args.v2.acConfig.fDPConnector = 1;
1135 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1136 if (dig->coherent_mode)
1137 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1138 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1139 args.v2.acConfig.fDualLinkConnector = 1;
1140 }
1141 break;
1142 case 3:
1143 args.v3.ucAction = action;
1144 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1145 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1146 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1147 args.v3.asMode.ucLaneSel = lane_num;
1148 args.v3.asMode.ucLaneSet = lane_set;
1149 } else {
1150 if (is_dp)
6e76a2df 1151 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1152 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1153 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1154 else
a3b08294
AD		 1155 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1156 }
1157
1158 if (is_dp)
1159 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1160 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1161 args.v3.ucLaneNum = 8;
1162 else
1163 args.v3.ucLaneNum = 4;
1164
1165 if (dig->linkb)
1166 args.v3.acConfig.ucLinkSel = 1;
1167 if (dig_encoder & 1)
1168 args.v3.acConfig.ucEncoderSel = 1;
1169
1170 /* Select the PLL for the PHY
1171 * DP PHY should be clocked from external src if there is
1172 * one.
1173 */
3f03ced8
AD		 1174 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1175 if (is_dp && rdev->clock.dp_extclk)
1176 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1177 else
1178 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1179
a3b08294
AD		 1180 switch (radeon_encoder->encoder_id) {
1181 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1182 args.v3.acConfig.ucTransmitterSel = 0;
1183 break;
1184 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1185 args.v3.acConfig.ucTransmitterSel = 1;
1186 break;
1187 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1188 args.v3.acConfig.ucTransmitterSel = 2;
1189 break;
1190 }
3f03ced8 1191
a3b08294
AD		 1192 if (is_dp)
1193 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1194 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1195 if (dig->coherent_mode)
1196 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1197 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1198 args.v3.acConfig.fDualLinkConnector = 1;
1199 }
3f03ced8 1200 break;
a3b08294
AD		 1201 case 4:
1202 args.v4.ucAction = action;
1203 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1204 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1205 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1206 args.v4.asMode.ucLaneSel = lane_num;
1207 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1208 } else {
a3b08294 1209 if (is_dp)
6e76a2df 1210 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1211 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1212 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1213 else
1214 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1215 }
3f03ced8 1216
a3b08294
AD		 1217 if (is_dp)
1218 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1219 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1220 args.v4.ucLaneNum = 8;
1221 else
1222 args.v4.ucLaneNum = 4;
3f03ced8 1223
a3b08294
AD		 1224 if (dig->linkb)
1225 args.v4.acConfig.ucLinkSel = 1;
1226 if (dig_encoder & 1)
1227 args.v4.acConfig.ucEncoderSel = 1;
1228
1229 /* Select the PLL for the PHY
1230 * DP PHY should be clocked from external src if there is
1231 * one.
1232 */
1233 /* On DCE5 DCPLL usually generates the DP ref clock */
1234 if (is_dp) {
1235 if (rdev->clock.dp_extclk)
1236 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1237 else
1238 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1239 } else
1240 args.v4.acConfig.ucRefClkSource = pll_id;
1241
1242 switch (radeon_encoder->encoder_id) {
1243 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1244 args.v4.acConfig.ucTransmitterSel = 0;
1245 break;
1246 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1247 args.v4.acConfig.ucTransmitterSel = 1;
1248 break;
1249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1250 args.v4.acConfig.ucTransmitterSel = 2;
1251 break;
1252 }
1253
1254 if (is_dp)
1255 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1256 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1257 if (dig->coherent_mode)
1258 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1259 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1260 args.v4.acConfig.fDualLinkConnector = 1;
1261 }
1262 break;
47aef7a8
AD		 1263 case 5:
1264 args.v5.ucAction = action;
1265 if (is_dp)
1266 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1267 else
1268 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1269
1270 switch (radeon_encoder->encoder_id) {
1271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1272 if (dig->linkb)
1273 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1274 else
1275 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1276 break;
1277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1278 if (dig->linkb)
1279 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1280 else
1281 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1282 break;
1283 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1284 if (dig->linkb)
1285 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1286 else
1287 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1288 break;
e68adef8
AD		 1289 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1290 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1291 break;
47aef7a8
AD		 1292 }
1293 if (is_dp)
1294 args.v5.ucLaneNum = dp_lane_count;
1295 else if (radeon_encoder->pixel_clock > 165000)
1296 args.v5.ucLaneNum = 8;
1297 else
1298 args.v5.ucLaneNum = 4;
1299 args.v5.ucConnObjId = connector_object_id;
1300 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1301
1302 if (is_dp && rdev->clock.dp_extclk)
1303 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1304 else
1305 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1306
1307 if (is_dp)
1308 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1309 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1310 if (dig->coherent_mode)
1311 args.v5.asConfig.ucCoherentMode = 1;
1312 }
1313 if (hpd_id == RADEON_HPD_NONE)
1314 args.v5.asConfig.ucHPDSel = 0;
1315 else
1316 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1317 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1318 args.v5.ucDPLaneSet = lane_set;
1319 break;
a3b08294
AD		 1320 default:
1321 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1322 break;
3f03ced8 1323 }
a3b08294
AD		 1324 break;
1325 default:
1326 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1327 break;
3f03ced8
AD		 1328 }
1329
1330 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1331}
1332
1333bool
1334atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1335{
1336 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1337 struct drm_device *dev = radeon_connector->base.dev;
1338 struct radeon_device *rdev = dev->dev_private;
1339 union dig_transmitter_control args;
1340 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1341 uint8_t frev, crev;
1342
1343 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1344 goto done;
1345
1346 if (!ASIC_IS_DCE4(rdev))
1347 goto done;
1348
1349 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1350 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1351 goto done;
1352
1353 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1354 goto done;
1355
1356 memset(&args, 0, sizeof(args));
1357
1358 args.v1.ucAction = action;
1359
1360 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1361
1362 /* wait for the panel to power up */
1363 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1364 int i;
1365
1366 for (i = 0; i < 300; i++) {
1367 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1368 return true;
1369 mdelay(1);
1370 }
1371 return false;
1372 }
1373done:
1374 return true;
1375}
1376
1377union external_encoder_control {
1378 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1379 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1380};
1381
1382static void
1383atombios_external_encoder_setup(struct drm_encoder *encoder,
1384 struct drm_encoder *ext_encoder,
1385 int action)
1386{
1387 struct drm_device *dev = encoder->dev;
1388 struct radeon_device *rdev = dev->dev_private;
1389 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1390 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1391 union external_encoder_control args;
1392 struct drm_connector *connector;
1393 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1394 u8 frev, crev;
1395 int dp_clock = 0;
1396 int dp_lane_count = 0;
1397 int connector_object_id = 0;
1398 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1399
1400 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1401 connector = radeon_get_connector_for_encoder_init(encoder);
1402 else
1403 connector = radeon_get_connector_for_encoder(encoder);
1404
1405 if (connector) {
1406 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1407 struct radeon_connector_atom_dig *dig_connector =
1408 radeon_connector->con_priv;
1409
1410 dp_clock = dig_connector->dp_clock;
1411 dp_lane_count = dig_connector->dp_lane_count;
1412 connector_object_id =
1413 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1414 }
1415
1416 memset(&args, 0, sizeof(args));
1417
1418 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1419 return;
1420
1421 switch (frev) {
1422 case 1:
1423 /* no params on frev 1 */
1424 break;
1425 case 2:
1426 switch (crev) {
1427 case 1:
1428 case 2:
1429 args.v1.sDigEncoder.ucAction = action;
1430 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1431 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1432
1433 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1434 if (dp_clock == 270000)
1435 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1436 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1437 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1438 args.v1.sDigEncoder.ucLaneNum = 8;
1439 else
1440 args.v1.sDigEncoder.ucLaneNum = 4;
1441 break;
1442 case 3:
1443 args.v3.sExtEncoder.ucAction = action;
1444 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1445 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1446 else
1447 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1448 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1449
1450 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1451 if (dp_clock == 270000)
1452 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1453 else if (dp_clock == 540000)
1454 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1455 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1456 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1457 args.v3.sExtEncoder.ucLaneNum = 8;
1458 else
1459 args.v3.sExtEncoder.ucLaneNum = 4;
1460 switch (ext_enum) {
1461 case GRAPH_OBJECT_ENUM_ID1:
1462 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1463 break;
1464 case GRAPH_OBJECT_ENUM_ID2:
1465 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1466 break;
1467 case GRAPH_OBJECT_ENUM_ID3:
1468 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1469 break;
1470 }
1f0e2943 1471 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1472 break;
1473 default:
1474 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1475 return;
1476 }
1477 break;
1478 default:
1479 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1480 return;
1481 }
1482 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1483}
1484
1485static void
1486atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1487{
1488 struct drm_device *dev = encoder->dev;
1489 struct radeon_device *rdev = dev->dev_private;
1490 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1491 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1492 ENABLE_YUV_PS_ALLOCATION args;
1493 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1494 uint32_t temp, reg;
1495
1496 memset(&args, 0, sizeof(args));
1497
1498 if (rdev->family >= CHIP_R600)
1499 reg = R600_BIOS_3_SCRATCH;
1500 else
1501 reg = RADEON_BIOS_3_SCRATCH;
1502
1503 /* XXX: fix up scratch reg handling */
1504 temp = RREG32(reg);
1505 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1506 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1507 (radeon_crtc->crtc_id << 18)));
1508 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1509 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1510 else
1511 WREG32(reg, 0);
1512
1513 if (enable)
1514 args.ucEnable = ATOM_ENABLE;
1515 args.ucCRTC = radeon_crtc->crtc_id;
1516
1517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1518
1519 WREG32(reg, temp);
1520}
1521
1522static void
1523radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1524{
1525 struct drm_device *dev = encoder->dev;
1526 struct radeon_device *rdev = dev->dev_private;
1527 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1528 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1529 int index = 0;
1530
1531 memset(&args, 0, sizeof(args));
1532
1533 switch (radeon_encoder->encoder_id) {
1534 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1536 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1537 break;
1538 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1539 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1540 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1541 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1542 break;
1543 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1544 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1545 break;
1546 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1547 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1548 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1549 else
1550 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1551 break;
1552 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1553 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1554 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1555 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1556 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1557 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1558 else
1559 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1560 break;
1561 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1563 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1564 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1565 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1566 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1567 else
1568 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1569 break;
1570 default:
1571 return;
1572 }
1573
1574 switch (mode) {
1575 case DRM_MODE_DPMS_ON:
1576 args.ucAction = ATOM_ENABLE;
1577 /* workaround for DVOOutputControl on some RS690 systems */
1578 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1579 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1580 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1581 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1582 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1583 } else
1584 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1585 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1586 args.ucAction = ATOM_LCD_BLON;
1587 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1588 }
1589 break;
1590 case DRM_MODE_DPMS_STANDBY:
1591 case DRM_MODE_DPMS_SUSPEND:
1592 case DRM_MODE_DPMS_OFF:
1593 args.ucAction = ATOM_DISABLE;
1594 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1595 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1596 args.ucAction = ATOM_LCD_BLOFF;
1597 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1598 }
1599 break;
1600 }
1601}
1602
1603static void
1604radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1605{
1606 struct drm_device *dev = encoder->dev;
1607 struct radeon_device *rdev = dev->dev_private;
1608 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1609 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1610 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1611 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1612 struct radeon_connector *radeon_connector = NULL;
1613 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1614
1615 if (connector) {
1616 radeon_connector = to_radeon_connector(connector);
1617 radeon_dig_connector = radeon_connector->con_priv;
1618 }
1619
1620 switch (mode) {
1621 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1622 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1623 if (!connector)
1624 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1625 else
1626 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1627
1628 /* setup and enable the encoder */
1629 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1630 atombios_dig_encoder_setup(encoder,
1631 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1632 dig->panel_mode);
1633 if (ext_encoder) {
1634 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1635 atombios_external_encoder_setup(encoder, ext_encoder,
1636 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1637 }
3f03ced8 1638 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
8d1af57a
AD		 1639 } else if (ASIC_IS_DCE4(rdev)) {
1640 /* setup and enable the encoder */
1641 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1642 /* enable the transmitter */
1643 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
3f03ced8 1644 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1645 } else {
1646 /* setup and enable the encoder and transmitter */
1647 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1648 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1649 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1650 /* some early dce3.2 boards have a bug in their transmitter control table */
b9196395 1651 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
8d1af57a 1652 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
fcedac67 1653 }
3f03ced8
AD		 1654 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1655 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1656 atombios_set_edp_panel_power(connector,
1657 ATOM_TRANSMITTER_ACTION_POWER_ON);
1658 radeon_dig_connector->edp_on = true;
1659 }
3f03ced8
AD		 1660 radeon_dp_link_train(encoder, connector);
1661 if (ASIC_IS_DCE4(rdev))
1662 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1663 }
1664 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1666 break;
1667 case DRM_MODE_DPMS_STANDBY:
1668 case DRM_MODE_DPMS_SUSPEND:
1669 case DRM_MODE_DPMS_OFF:
8d1af57a
AD		 1670 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1671 /* disable the transmitter */
3a47824d 1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1673 } else if (ASIC_IS_DCE4(rdev)) {
1674 /* disable the transmitter */
1675 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1676 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1677 } else {
1678 /* disable the encoder and transmitter */
3a47824d 1679 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
8d1af57a
AD		 1680 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1681 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1682 }
3f03ced8
AD		 1683 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1684 if (ASIC_IS_DCE4(rdev))
1685 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1686 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1687 atombios_set_edp_panel_power(connector,
1688 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1689 radeon_dig_connector->edp_on = false;
1690 }
1691 }
1692 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1693 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1694 break;
1695 }
1696}
1697
1698static void
1699radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1700 struct drm_encoder *ext_encoder,
1701 int mode)
1702{
1703 struct drm_device *dev = encoder->dev;
1704 struct radeon_device *rdev = dev->dev_private;
1705
1706 switch (mode) {
1707 case DRM_MODE_DPMS_ON:
1708 default:
1d3949c4 1709 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1710 atombios_external_encoder_setup(encoder, ext_encoder,
1711 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1712 atombios_external_encoder_setup(encoder, ext_encoder,
1713 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1714 } else
1715 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1716 break;
1717 case DRM_MODE_DPMS_STANDBY:
1718 case DRM_MODE_DPMS_SUSPEND:
1719 case DRM_MODE_DPMS_OFF:
1d3949c4 1720 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 1721 atombios_external_encoder_setup(encoder, ext_encoder,
1722 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1723 atombios_external_encoder_setup(encoder, ext_encoder,
1724 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1725 } else
1726 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1727 break;
1728 }
1729}
1730
1731static void
1732radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1733{
1734 struct drm_device *dev = encoder->dev;
1735 struct radeon_device *rdev = dev->dev_private;
1736 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1737 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1738
1739 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1740 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1741 radeon_encoder->active_device);
1742 switch (radeon_encoder->encoder_id) {
1743 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1744 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1745 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1746 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1747 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1748 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1749 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1750 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1751 radeon_atom_encoder_dpms_avivo(encoder, mode);
1752 break;
1753 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1754 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1755 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1758 radeon_atom_encoder_dpms_dig(encoder, mode);
1759 break;
1760 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1761 if (ASIC_IS_DCE5(rdev)) {
1762 switch (mode) {
1763 case DRM_MODE_DPMS_ON:
1764 atombios_dvo_setup(encoder, ATOM_ENABLE);
1765 break;
1766 case DRM_MODE_DPMS_STANDBY:
1767 case DRM_MODE_DPMS_SUSPEND:
1768 case DRM_MODE_DPMS_OFF:
1769 atombios_dvo_setup(encoder, ATOM_DISABLE);
1770 break;
1771 }
1772 } else if (ASIC_IS_DCE3(rdev))
1773 radeon_atom_encoder_dpms_dig(encoder, mode);
1774 else
1775 radeon_atom_encoder_dpms_avivo(encoder, mode);
1776 break;
1777 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1778 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1779 if (ASIC_IS_DCE5(rdev)) {
1780 switch (mode) {
1781 case DRM_MODE_DPMS_ON:
1782 atombios_dac_setup(encoder, ATOM_ENABLE);
1783 break;
1784 case DRM_MODE_DPMS_STANDBY:
1785 case DRM_MODE_DPMS_SUSPEND:
1786 case DRM_MODE_DPMS_OFF:
1787 atombios_dac_setup(encoder, ATOM_DISABLE);
1788 break;
1789 }
1790 } else
1791 radeon_atom_encoder_dpms_avivo(encoder, mode);
1792 break;
1793 default:
1794 return;
1795 }
1796
1797 if (ext_encoder)
1798 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1799
1800 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1801
1802}
1803
1804union crtc_source_param {
1805 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1806 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1807};
1808
1809static void
1810atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1811{
1812 struct drm_device *dev = encoder->dev;
1813 struct radeon_device *rdev = dev->dev_private;
1814 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1815 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1816 union crtc_source_param args;
1817 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1818 uint8_t frev, crev;
1819 struct radeon_encoder_atom_dig *dig;
1820
1821 memset(&args, 0, sizeof(args));
1822
1823 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1824 return;
1825
1826 switch (frev) {
1827 case 1:
1828 switch (crev) {
1829 case 1:
1830 default:
1831 if (ASIC_IS_AVIVO(rdev))
1832 args.v1.ucCRTC = radeon_crtc->crtc_id;
1833 else {
1834 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1835 args.v1.ucCRTC = radeon_crtc->crtc_id;
1836 } else {
1837 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1838 }
1839 }
1840 switch (radeon_encoder->encoder_id) {
1841 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1842 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1843 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1844 break;
1845 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1846 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1847 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1848 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1849 else
1850 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1851 break;
1852 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1853 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1854 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1855 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1856 break;
1857 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1858 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1859 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1860 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1861 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1862 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1863 else
1864 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1865 break;
1866 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1868 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1869 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1870 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1871 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1872 else
1873 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1874 break;
1875 }
1876 break;
1877 case 2:
1878 args.v2.ucCRTC = radeon_crtc->crtc_id;
1879 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1880 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1881
1882 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1883 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1884 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1885 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1886 else
1887 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1888 } else
1889 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1890 switch (radeon_encoder->encoder_id) {
1891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1892 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1893 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1895 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1896 dig = radeon_encoder->enc_priv;
1897 switch (dig->dig_encoder) {
1898 case 0:
1899 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1900 break;
1901 case 1:
1902 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1903 break;
1904 case 2:
1905 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1906 break;
1907 case 3:
1908 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1909 break;
1910 case 4:
1911 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1912 break;
1913 case 5:
1914 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1915 break;
e68adef8
AD		 1916 case 6:
1917 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1918 break;
3f03ced8
AD		 1919 }
1920 break;
1921 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1922 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1923 break;
1924 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1925 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1926 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1927 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1928 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1929 else
1930 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1931 break;
1932 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1933 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1934 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1935 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1936 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1937 else
1938 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1939 break;
1940 }
1941 break;
1942 }
1943 break;
1944 default:
1945 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1946 return;
1947 }
1948
1949 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1950
1951 /* update scratch regs with new routing */
1952 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1953}
1954
1955static void
1956atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1957 struct drm_display_mode *mode)
1958{
1959 struct drm_device *dev = encoder->dev;
1960 struct radeon_device *rdev = dev->dev_private;
1961 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1962 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1963
1964 /* Funky macbooks */
1965 if ((dev->pdev->device == 0x71C5) &&
1966 (dev->pdev->subsystem_vendor == 0x106b) &&
1967 (dev->pdev->subsystem_device == 0x0080)) {
1968 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1969 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1970
1971 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1972 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1973
1974 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1975 }
1976 }
1977
1978 /* set scaler clears this on some chips */
1979 if (ASIC_IS_AVIVO(rdev) &&
1980 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
d798f2f2
AD		 1981 if (ASIC_IS_DCE8(rdev)) {
1982 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1983 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1984 CIK_INTERLEAVE_EN);
1985 else
1986 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1987 } else if (ASIC_IS_DCE4(rdev)) {
3f03ced8
AD		 1988 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1989 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1990 EVERGREEN_INTERLEAVE_EN);
1991 else
1992 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1993 } else {
1994 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1995 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1996 AVIVO_D1MODE_INTERLEAVE_EN);
1997 else
1998 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1999 }
2000 }
2001}
2002
2003static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2004{
2005 struct drm_device *dev = encoder->dev;
2006 struct radeon_device *rdev = dev->dev_private;
2007 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2008 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2009 struct drm_encoder *test_encoder;
41fa5437 2010 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 2011 uint32_t dig_enc_in_use = 0;
2012
41fa5437
AD		 2013 if (ASIC_IS_DCE6(rdev)) {
2014 /* DCE6 */
2015 switch (radeon_encoder->encoder_id) {
2016 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2017 if (dig->linkb)
2018 return 1;
2019 else
2020 return 0;
2021 break;
2022 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2023 if (dig->linkb)
2024 return 3;
2025 else
2026 return 2;
2027 break;
2028 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2029 if (dig->linkb)
2030 return 5;
2031 else
2032 return 4;
2033 break;
e68adef8
AD		 2034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2035 return 6;
2036 break;
41fa5437
AD		 2037 }
2038 } else if (ASIC_IS_DCE4(rdev)) {
2039 /* DCE4/5 */
2040 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2041 /* ontario follows DCE4 */
2042 if (rdev->family == CHIP_PALM) {
2043 if (dig->linkb)
2044 return 1;
2045 else
2046 return 0;
2047 } else
2048 /* llano follows DCE3.2 */
2049 return radeon_crtc->crtc_id;
2050 } else {
2051 switch (radeon_encoder->encoder_id) {
2052 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2053 if (dig->linkb)
2054 return 1;
2055 else
2056 return 0;
2057 break;
2058 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2059 if (dig->linkb)
2060 return 3;
2061 else
2062 return 2;
2063 break;
2064 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2065 if (dig->linkb)
2066 return 5;
2067 else
2068 return 4;
2069 break;
2070 }
2071 }
2072 }
2073
2074 /* on DCE32 and encoder can driver any block so just crtc id */
2075 if (ASIC_IS_DCE32(rdev)) {
2076 return radeon_crtc->crtc_id;
2077 }
2078
2079 /* on DCE3 - LVTMA can only be driven by DIGB */
2080 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2081 struct radeon_encoder *radeon_test_encoder;
2082
2083 if (encoder == test_encoder)
2084 continue;
2085
2086 if (!radeon_encoder_is_digital(test_encoder))
2087 continue;
2088
2089 radeon_test_encoder = to_radeon_encoder(test_encoder);
2090 dig = radeon_test_encoder->enc_priv;
2091
2092 if (dig->dig_encoder >= 0)
2093 dig_enc_in_use |= (1 << dig->dig_encoder);
2094 }
2095
2096 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2097 if (dig_enc_in_use & 0x2)
2098 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2099 return 1;
2100 }
2101 if (!(dig_enc_in_use & 1))
2102 return 0;
2103 return 1;
2104}
2105
2106/* This only needs to be called once at startup */
2107void
2108radeon_atom_encoder_init(struct radeon_device *rdev)
2109{
2110 struct drm_device *dev = rdev->ddev;
2111 struct drm_encoder *encoder;
2112
2113 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2114 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2115 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2116
2117 switch (radeon_encoder->encoder_id) {
2118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2122 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2124 break;
2125 default:
2126 break;
2127 }
2128
1d3949c4 2129 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2130 atombios_external_encoder_setup(encoder, ext_encoder,
2131 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2132 }
2133}
2134
2135static void
2136radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2137 struct drm_display_mode *mode,
2138 struct drm_display_mode *adjusted_mode)
2139{
2140 struct drm_device *dev = encoder->dev;
2141 struct radeon_device *rdev = dev->dev_private;
2142 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2143
2144 radeon_encoder->pixel_clock = adjusted_mode->clock;
2145
8d1af57a
AD		 2146 /* need to call this here rather than in prepare() since we need some crtc info */
2147 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2148
3f03ced8
AD		 2149 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2150 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2151 atombios_yuv_setup(encoder, true);
2152 else
2153 atombios_yuv_setup(encoder, false);
2154 }
2155
2156 switch (radeon_encoder->encoder_id) {
2157 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2158 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2159 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2160 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2161 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2162 break;
2163 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2164 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2165 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2167 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2168 /* handled in dpms */
3f03ced8
AD		 2169 break;
2170 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2171 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2172 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2173 atombios_dvo_setup(encoder, ATOM_ENABLE);
2174 break;
2175 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2176 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2177 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2178 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2179 atombios_dac_setup(encoder, ATOM_ENABLE);
2180 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2181 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2182 atombios_tv_setup(encoder, ATOM_ENABLE);
2183 else
2184 atombios_tv_setup(encoder, ATOM_DISABLE);
2185 }
2186 break;
2187 }
2188
3f03ced8
AD		 2189 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2190
2191 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
a973bea1
AD		 2192 if (rdev->asic->display.hdmi_enable)
2193 radeon_hdmi_enable(rdev, encoder, true);
2194 if (rdev->asic->display.hdmi_setmode)
2195 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
3f03ced8
AD		 2196 }
2197}
2198
2199static bool
2200atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2201{
2202 struct drm_device *dev = encoder->dev;
2203 struct radeon_device *rdev = dev->dev_private;
2204 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2205 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2206
2207 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2208 ATOM_DEVICE_CV_SUPPORT |
2209 ATOM_DEVICE_CRT_SUPPORT)) {
2210 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2211 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2212 uint8_t frev, crev;
2213
2214 memset(&args, 0, sizeof(args));
2215
2216 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2217 return false;
2218
2219 args.sDacload.ucMisc = 0;
2220
2221 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2222 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2223 args.sDacload.ucDacType = ATOM_DAC_A;
2224 else
2225 args.sDacload.ucDacType = ATOM_DAC_B;
2226
2227 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2228 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2229 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2230 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2231 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2232 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2233 if (crev >= 3)
2234 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2235 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2236 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2237 if (crev >= 3)
2238 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2239 }
2240
2241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2242
2243 return true;
2244 } else
2245 return false;
2246}
2247
2248static enum drm_connector_status
2249radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2250{
2251 struct drm_device *dev = encoder->dev;
2252 struct radeon_device *rdev = dev->dev_private;
2253 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2254 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2255 uint32_t bios_0_scratch;
2256
2257 if (!atombios_dac_load_detect(encoder, connector)) {
2258 DRM_DEBUG_KMS("detect returned false \n");
2259 return connector_status_unknown;
2260 }
2261
2262 if (rdev->family >= CHIP_R600)
2263 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2264 else
2265 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2266
2267 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2268 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2269 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2270 return connector_status_connected;
2271 }
2272 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2273 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2274 return connector_status_connected;
2275 }
2276 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2277 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2278 return connector_status_connected;
2279 }
2280 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2281 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2282 return connector_status_connected; /* CTV */
2283 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2284 return connector_status_connected; /* STV */
2285 }
2286 return connector_status_disconnected;
2287}
2288
2289static enum drm_connector_status
2290radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2291{
2292 struct drm_device *dev = encoder->dev;
2293 struct radeon_device *rdev = dev->dev_private;
2294 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2295 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2296 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2297 u32 bios_0_scratch;
2298
2299 if (!ASIC_IS_DCE4(rdev))
2300 return connector_status_unknown;
2301
2302 if (!ext_encoder)
2303 return connector_status_unknown;
2304
2305 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2306 return connector_status_unknown;
2307
2308 /* load detect on the dp bridge */
2309 atombios_external_encoder_setup(encoder, ext_encoder,
2310 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2311
2312 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2313
2314 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2315 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2316 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2317 return connector_status_connected;
2318 }
2319 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2320 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2321 return connector_status_connected;
2322 }
2323 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2324 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2325 return connector_status_connected;
2326 }
2327 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2328 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2329 return connector_status_connected; /* CTV */
2330 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2331 return connector_status_connected; /* STV */
2332 }
2333 return connector_status_disconnected;
2334}
2335
2336void
2337radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2338{
2339 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2340
2341 if (ext_encoder)
2342 /* ddc_setup on the dp bridge */
2343 atombios_external_encoder_setup(encoder, ext_encoder,
2344 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2345
2346}
2347
2348static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2349{
cfcbd6d3 2350 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2351 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2352 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2353
2354 if ((radeon_encoder->active_device &
2355 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2356 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2357 ENCODER_OBJECT_ID_NONE)) {
2358 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2359 if (dig) {
3f03ced8 2360 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2361 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2362 if (rdev->family >= CHIP_R600)
2363 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2364 else
2365 /* RS600/690/740 have only 1 afmt block */
2366 dig->afmt = rdev->mode_info.afmt[0];
2367 }
2368 }
3f03ced8
AD		 2369 }
2370
2371 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2372
2373 if (connector) {
2374 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2375
2376 /* select the clock/data port if it uses a router */
2377 if (radeon_connector->router.cd_valid)
2378 radeon_router_select_cd_port(radeon_connector);
2379
2380 /* turn eDP panel on for mode set */
2381 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2382 atombios_set_edp_panel_power(connector,
2383 ATOM_TRANSMITTER_ACTION_POWER_ON);
2384 }
2385
2386 /* this is needed for the pll/ss setup to work correctly in some cases */
2387 atombios_set_encoder_crtc_source(encoder);
2388}
2389
2390static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2391{
8d1af57a 2392 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2393 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2394 radeon_atom_output_lock(encoder, false);
2395}
2396
2397static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2398{
2399 struct drm_device *dev = encoder->dev;
2400 struct radeon_device *rdev = dev->dev_private;
2401 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2402 struct radeon_encoder_atom_dig *dig;
2403
2404 /* check for pre-DCE3 cards with shared encoders;
2405 * can't really use the links individually, so don't disable
2406 * the encoder if it's in use by another connector
2407 */
2408 if (!ASIC_IS_DCE3(rdev)) {
2409 struct drm_encoder *other_encoder;
2410 struct radeon_encoder *other_radeon_encoder;
2411
2412 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2413 other_radeon_encoder = to_radeon_encoder(other_encoder);
2414 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2415 drm_helper_encoder_in_use(other_encoder))
2416 goto disable_done;
2417 }
2418 }
2419
2420 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2421
2422 switch (radeon_encoder->encoder_id) {
2423 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2424 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2425 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2426 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2427 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2428 break;
2429 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2430 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2431 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2432 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2433 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2434 /* handled in dpms */
3f03ced8
AD		 2435 break;
2436 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2437 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2438 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2439 atombios_dvo_setup(encoder, ATOM_DISABLE);
2440 break;
2441 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2442 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2443 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2444 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2445 atombios_dac_setup(encoder, ATOM_DISABLE);
2446 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2447 atombios_tv_setup(encoder, ATOM_DISABLE);
2448 break;
2449 }
2450
2451disable_done:
2452 if (radeon_encoder_is_digital(encoder)) {
a973bea1
AD		 2453 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2454 if (rdev->asic->display.hdmi_enable)
2455 radeon_hdmi_enable(rdev, encoder, false);
2456 }
3f03ced8
AD		 2457 dig = radeon_encoder->enc_priv;
2458 dig->dig_encoder = -1;
2459 }
2460 radeon_encoder->active_device = 0;
2461}
2462
2463/* these are handled by the primary encoders */
2464static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2465{
2466
2467}
2468
2469static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2470{
2471
2472}
2473
2474static void
2475radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2476 struct drm_display_mode *mode,
2477 struct drm_display_mode *adjusted_mode)
2478{
2479
2480}
2481
2482static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2483{
2484
2485}
2486
2487static void
2488radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2489{
2490
2491}
2492
2493static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2494 const struct drm_display_mode *mode,
3f03ced8
AD		 2495 struct drm_display_mode *adjusted_mode)
2496{
2497 return true;
2498}
2499
2500static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2501 .dpms = radeon_atom_ext_dpms,
2502 .mode_fixup = radeon_atom_ext_mode_fixup,
2503 .prepare = radeon_atom_ext_prepare,
2504 .mode_set = radeon_atom_ext_mode_set,
2505 .commit = radeon_atom_ext_commit,
2506 .disable = radeon_atom_ext_disable,
2507 /* no detect for TMDS/LVDS yet */
2508};
2509
2510static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2511 .dpms = radeon_atom_encoder_dpms,
2512 .mode_fixup = radeon_atom_mode_fixup,
2513 .prepare = radeon_atom_encoder_prepare,
2514 .mode_set = radeon_atom_encoder_mode_set,
2515 .commit = radeon_atom_encoder_commit,
2516 .disable = radeon_atom_encoder_disable,
2517 .detect = radeon_atom_dig_detect,
2518};
2519
2520static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2521 .dpms = radeon_atom_encoder_dpms,
2522 .mode_fixup = radeon_atom_mode_fixup,
2523 .prepare = radeon_atom_encoder_prepare,
2524 .mode_set = radeon_atom_encoder_mode_set,
2525 .commit = radeon_atom_encoder_commit,
2526 .detect = radeon_atom_dac_detect,
2527};
2528
2529void radeon_enc_destroy(struct drm_encoder *encoder)
2530{
2531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2532 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2533 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2534 kfree(radeon_encoder->enc_priv);
2535 drm_encoder_cleanup(encoder);
2536 kfree(radeon_encoder);
2537}
2538
2539static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2540 .destroy = radeon_enc_destroy,
2541};
2542
1109ca09 2543static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2544radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2545{
2546 struct drm_device *dev = radeon_encoder->base.dev;
2547 struct radeon_device *rdev = dev->dev_private;
2548 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2549
2550 if (!dac)
2551 return NULL;
2552
2553 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2554 return dac;
2555}
2556
1109ca09 2557static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2558radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2559{
2560 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2561 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2562
2563 if (!dig)
2564 return NULL;
2565
2566 /* coherent mode by default */
2567 dig->coherent_mode = true;
2568 dig->dig_encoder = -1;
2569
2570 if (encoder_enum == 2)
2571 dig->linkb = true;
2572 else
2573 dig->linkb = false;
2574
2575 return dig;
2576}
2577
2578void
2579radeon_add_atom_encoder(struct drm_device *dev,
2580 uint32_t encoder_enum,
2581 uint32_t supported_device,
2582 u16 caps)
2583{
2584 struct radeon_device *rdev = dev->dev_private;
2585 struct drm_encoder *encoder;
2586 struct radeon_encoder *radeon_encoder;
2587
2588 /* see if we already added it */
2589 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2590 radeon_encoder = to_radeon_encoder(encoder);
2591 if (radeon_encoder->encoder_enum == encoder_enum) {
2592 radeon_encoder->devices |= supported_device;
2593 return;
2594 }
2595
2596 }
2597
2598 /* add a new one */
2599 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2600 if (!radeon_encoder)
2601 return;
2602
2603 encoder = &radeon_encoder->base;
2604 switch (rdev->num_crtc) {
2605 case 1:
2606 encoder->possible_crtcs = 0x1;
2607 break;
2608 case 2:
2609 default:
2610 encoder->possible_crtcs = 0x3;
2611 break;
2612 case 4:
2613 encoder->possible_crtcs = 0xf;
2614 break;
2615 case 6:
2616 encoder->possible_crtcs = 0x3f;
2617 break;
2618 }
2619
2620 radeon_encoder->enc_priv = NULL;
2621
2622 radeon_encoder->encoder_enum = encoder_enum;
2623 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2624 radeon_encoder->devices = supported_device;
2625 radeon_encoder->rmx_type = RMX_OFF;
2626 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2627 radeon_encoder->is_ext_encoder = false;
2628 radeon_encoder->caps = caps;
2629
2630 switch (radeon_encoder->encoder_id) {
2631 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2632 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2634 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2635 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2636 radeon_encoder->rmx_type = RMX_FULL;
2637 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2638 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2639 } else {
2640 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2641 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2642 }
2643 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2644 break;
2645 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2646 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2647 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2648 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2649 break;
2650 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2651 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2652 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2653 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2654 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2655 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2656 break;
2657 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2658 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2659 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2660 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2661 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2664 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2665 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2666 radeon_encoder->rmx_type = RMX_FULL;
2667 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2668 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2669 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2670 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2671 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2672 } else {
2673 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2674 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2675 }
2676 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2677 break;
2678 case ENCODER_OBJECT_ID_SI170B:
2679 case ENCODER_OBJECT_ID_CH7303:
2680 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2681 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2682 case ENCODER_OBJECT_ID_TITFP513:
2683 case ENCODER_OBJECT_ID_VT1623:
2684 case ENCODER_OBJECT_ID_HDMI_SI1930:
2685 case ENCODER_OBJECT_ID_TRAVIS:
2686 case ENCODER_OBJECT_ID_NUTMEG:
2687 /* these are handled by the primary encoders */
2688 radeon_encoder->is_ext_encoder = true;
2689 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2690 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2691 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2692 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2693 else
2694 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2695 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2696 break;
2697 }
2698}
Linux 6.x block layer and io_uring tree(s)