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Merge branches 'amd-iommu/fixes' and 'dma-debug/fixes' into iommu/fixes
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_dp.c
CommitLineData
746c1aa4
DA		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "drm_dp_helper.h"
33
f92a8b67 34/* move these to drm_dp_helper.c/h */
5801ead6
AD		 35#define DP_LINK_CONFIGURATION_SIZE 9
36#define DP_LINK_STATUS_SIZE 6
37#define DP_DPCD_SIZE 8
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
f92a8b67
AD		 45
46static const int dp_clocks[] = {
53c1e09f
AD		 47 54000, /* 1 lane, 1.62 Ghz */
48 90000, /* 1 lane, 2.70 Ghz */
49 108000, /* 2 lane, 1.62 Ghz */
50 180000, /* 2 lane, 2.70 Ghz */
51 216000, /* 4 lane, 1.62 Ghz */
52 360000, /* 4 lane, 2.70 Ghz */
f92a8b67
AD		 53};
54
55static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
56
5801ead6
AD		 57/* common helper functions */
58static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
f92a8b67
AD		 59{
60 int i;
5801ead6
AD		 61 u8 max_link_bw;
62 u8 max_lane_count;
63
64 if (!dpcd)
65 return 0;
66
67 max_link_bw = dpcd[DP_MAX_LINK_RATE];
68 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
f92a8b67
AD		 69
70 switch (max_link_bw) {
71 case DP_LINK_BW_1_62:
72 default:
73 for (i = 0; i < num_dp_clocks; i++) {
74 if (i % 2)
75 continue;
5801ead6
AD		 76 switch (max_lane_count) {
77 case 1:
78 if (i > 1)
79 return 0;
80 break;
81 case 2:
82 if (i > 3)
83 return 0;
84 break;
85 case 4:
86 default:
87 break;
88 }
f92a8b67
AD		 89 if (dp_clocks[i] > mode_clock) {
90 if (i < 2)
91 return 1;
92 else if (i < 4)
93 return 2;
94 else
95 return 4;
96 }
97 }
98 break;
99 case DP_LINK_BW_2_7:
100 for (i = 0; i < num_dp_clocks; i++) {
5801ead6
AD		 101 switch (max_lane_count) {
102 case 1:
103 if (i > 1)
104 return 0;
105 break;
106 case 2:
107 if (i > 3)
108 return 0;
109 break;
110 case 4:
111 default:
112 break;
113 }
f92a8b67
AD		 114 if (dp_clocks[i] > mode_clock) {
115 if (i < 2)
116 return 1;
117 else if (i < 4)
118 return 2;
119 else
120 return 4;
121 }
122 }
123 break;
124 }
125
126 return 0;
127}
128
5801ead6 129static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
f92a8b67
AD		 130{
131 int i;
5801ead6
AD		 132 u8 max_link_bw;
133 u8 max_lane_count;
134
135 if (!dpcd)
136 return 0;
137
138 max_link_bw = dpcd[DP_MAX_LINK_RATE];
139 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
f92a8b67
AD		 140
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
143 default:
5801ead6
AD		 144 for (i = 0; i < num_dp_clocks; i++) {
145 if (i % 2)
146 continue;
147 switch (max_lane_count) {
148 case 1:
149 if (i > 1)
150 return 0;
151 break;
152 case 2:
153 if (i > 3)
154 return 0;
155 break;
156 case 4:
157 default:
158 break;
159 }
160 if (dp_clocks[i] > mode_clock)
161 return 162000;
162 }
f92a8b67
AD		 163 break;
164 case DP_LINK_BW_2_7:
165 for (i = 0; i < num_dp_clocks; i++) {
5801ead6
AD		 166 switch (max_lane_count) {
167 case 1:
168 if (i > 1)
169 return 0;
170 break;
171 case 2:
172 if (i > 3)
173 return 0;
174 break;
175 case 4:
176 default:
177 break;
178 }
f92a8b67
AD		 179 if (dp_clocks[i] > mode_clock)
180 return (i % 2) ? 270000 : 162000;
181 }
182 }
183
184 return 0;
185}
186
5801ead6
AD		 187int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
188{
189 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
190 int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
191
192 if ((lanes == 0) || (bw == 0))
193 return MODE_CLOCK_HIGH;
194
195 return MODE_OK;
196}
197
198static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
199{
200 return link_status[r - DP_LANE0_1_STATUS];
201}
202
203static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
204 int lane)
205{
206 int i = DP_LANE0_1_STATUS + (lane >> 1);
207 int s = (lane & 1) * 4;
208 u8 l = dp_link_status(link_status, i);
209 return (l >> s) & 0xf;
210}
211
212static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
213 int lane_count)
214{
215 int lane;
216 u8 lane_status;
217
218 for (lane = 0; lane < lane_count; lane++) {
219 lane_status = dp_get_lane_status(link_status, lane);
220 if ((lane_status & DP_LANE_CR_DONE) == 0)
221 return false;
222 }
223 return true;
224}
225
226static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
227 int lane_count)
228{
229 u8 lane_align;
230 u8 lane_status;
231 int lane;
232
233 lane_align = dp_link_status(link_status,
234 DP_LANE_ALIGN_STATUS_UPDATED);
235 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
236 return false;
237 for (lane = 0; lane < lane_count; lane++) {
238 lane_status = dp_get_lane_status(link_status, lane);
239 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
240 return false;
241 }
242 return true;
243}
244
245static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
246 int lane)
247
248{
249 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
250 int s = ((lane & 1) ?
251 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
252 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
253 u8 l = dp_link_status(link_status, i);
254
255 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
256}
257
258static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
259 int lane)
260{
261 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
262 int s = ((lane & 1) ?
263 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
264 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
265 u8 l = dp_link_status(link_status, i);
266
267 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
268}
269
270/* XXX fix me -- chip specific */
271#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
272static u8 dp_pre_emphasis_max(u8 voltage_swing)
273{
274 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
275 case DP_TRAIN_VOLTAGE_SWING_400:
276 return DP_TRAIN_PRE_EMPHASIS_6;
277 case DP_TRAIN_VOLTAGE_SWING_600:
278 return DP_TRAIN_PRE_EMPHASIS_6;
279 case DP_TRAIN_VOLTAGE_SWING_800:
280 return DP_TRAIN_PRE_EMPHASIS_3_5;
281 case DP_TRAIN_VOLTAGE_SWING_1200:
282 default:
283 return DP_TRAIN_PRE_EMPHASIS_0;
284 }
285}
286
287static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
288 int lane_count,
289 u8 train_set[4])
290{
291 u8 v = 0;
292 u8 p = 0;
293 int lane;
294
295 for (lane = 0; lane < lane_count; lane++) {
296 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
297 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
298
53c1e09f
AD		 299 DRM_DEBUG("requested signal parameters: lane %d voltage %s pre_emph %s\n",
300 lane,
301 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
302 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 303
304 if (this_v > v)
305 v = this_v;
306 if (this_p > p)
307 p = this_p;
308 }
309
310 if (v >= DP_VOLTAGE_MAX)
311 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
312
313 if (p >= dp_pre_emphasis_max(v))
314 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
315
53c1e09f
AD		 316 DRM_DEBUG("using signal parameters: voltage %s pre_emph %s\n",
317 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
318 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 319
320 for (lane = 0; lane < 4; lane++)
321 train_set[lane] = v | p;
322}
323
324
325/* radeon aux chan functions */
746c1aa4 326bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
1a66c95a 327 int num_bytes, u8 *read_byte,
746c1aa4
DA		 328 u8 read_buf_len, u8 delay)
329{
330 struct drm_device *dev = chan->dev;
331 struct radeon_device *rdev = dev->dev_private;
332 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
333 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
334 unsigned char *base;
1a66c95a 335
746c1aa4 336 memset(&args, 0, sizeof(args));
1a66c95a 337
746c1aa4
DA		 338 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
339
340 memcpy(base, req_bytes, num_bytes);
341
342 args.lpAuxRequest = 0;
343 args.lpDataOut = 16;
344 args.ucDataOutLen = 0;
6a93cb25 345 args.ucChannelID = chan->rec.i2c_id;
1a66c95a 346 args.ucDelay = delay / 10;
746c1aa4
DA		 347
348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
349
350 if (args.ucReplyStatus) {
53c1e09f 351 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n",
746c1aa4 352 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
6a93cb25 353 chan->rec.i2c_id, args.ucReplyStatus);
746c1aa4
DA		 354 return false;
355 }
356
357 if (args.ucDataOutLen && read_byte && read_buf_len) {
358 if (read_buf_len < args.ucDataOutLen) {
359 DRM_ERROR("Buffer to small for return answer %d %d\n",
360 read_buf_len, args.ucDataOutLen);
361 return false;
362 }
363 {
364 int len = min(read_buf_len, args.ucDataOutLen);
365 memcpy(read_byte, base + 16, len);
366 }
367 }
368 return true;
369}
370
746c1aa4
DA		 371bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
372 uint8_t send_bytes, uint8_t *send)
373{
5801ead6 374 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 375 u8 msg[20];
376 u8 msg_len, dp_msg_len;
377 bool ret;
378
379 dp_msg_len = 4;
380 msg[0] = address;
381 msg[1] = address >> 8;
382 msg[2] = AUX_NATIVE_WRITE << 4;
383 dp_msg_len += send_bytes;
384 msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
385
386 if (send_bytes > 16)
387 return false;
388
389 memcpy(&msg[4], send, send_bytes);
390 msg_len = 4 + send_bytes;
5801ead6 391 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
746c1aa4
DA		 392 return ret;
393}
394
395bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
396 uint8_t delay, uint8_t expected_bytes,
397 uint8_t *read_p)
398{
5801ead6 399 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 400 u8 msg[20];
401 u8 msg_len, dp_msg_len;
402 bool ret = false;
403 msg_len = 4;
404 dp_msg_len = 4;
405 msg[0] = address;
406 msg[1] = address >> 8;
407 msg[2] = AUX_NATIVE_READ << 4;
408 msg[3] = (dp_msg_len) << 4;
409 msg[3] |= expected_bytes - 1;
410
5801ead6 411 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
746c1aa4
DA		 412 return ret;
413}
414
5801ead6
AD		 415/* radeon dp functions */
416static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
417 uint8_t ucconfig, uint8_t lane_num)
418{
419 DP_ENCODER_SERVICE_PARAMETERS args;
420 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
421
422 memset(&args, 0, sizeof(args));
423 args.ucLinkClock = dp_clock / 10;
424 args.ucConfig = ucconfig;
425 args.ucAction = action;
426 args.ucLaneNum = lane_num;
427 args.ucStatus = 0;
428
429 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
430 return args.ucStatus;
431}
432
433u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
434{
435 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
436 struct drm_device *dev = radeon_connector->base.dev;
437 struct radeon_device *rdev = dev->dev_private;
438
439 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
440 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
441}
442
9fa05c98 443bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
746c1aa4 444{
5801ead6 445 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4
DA		 446 u8 msg[25];
447 int ret;
448
1a66c95a 449 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
746c1aa4 450 if (ret) {
5801ead6 451 memcpy(dig_connector->dpcd, msg, 8);
1a66c95a 452 {
746c1aa4 453 int i;
53c1e09f 454 DRM_DEBUG("DPCD: ");
746c1aa4 455 for (i = 0; i < 8; i++)
53c1e09f
AD		 456 DRM_DEBUG("%02x ", msg[i]);
457 DRM_DEBUG("\n");
746c1aa4 458 }
9fa05c98 459 return true;
746c1aa4 460 }
5801ead6 461 dig_connector->dpcd[0] = 0;
9fa05c98 462 return false;
746c1aa4
DA		 463}
464
5801ead6
AD		 465void radeon_dp_set_link_config(struct drm_connector *connector,
466 struct drm_display_mode *mode)
467{
468 struct radeon_connector *radeon_connector;
469 struct radeon_connector_atom_dig *dig_connector;
470
196c58d2
AD		 471 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||
472 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
5801ead6
AD		 473 return;
474
475 radeon_connector = to_radeon_connector(connector);
476 if (!radeon_connector->con_priv)
477 return;
478 dig_connector = radeon_connector->con_priv;
479
480 dig_connector->dp_clock =
481 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
482 dig_connector->dp_lane_count =
483 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
484}
485
486int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
487 struct drm_display_mode *mode)
488{
489 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
490
491 return dp_mode_valid(dig_connector->dpcd, mode->clock);
492}
493
746c1aa4
DA		 494static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
495 u8 link_status[DP_LINK_STATUS_SIZE])
496{
497 int ret;
498 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
499 DP_LINK_STATUS_SIZE, link_status);
500 if (!ret) {
501 DRM_ERROR("displayport link status failed\n");
502 return false;
503 }
504
53c1e09f
AD		 505 DRM_DEBUG("link status %02x %02x %02x %02x %02x %02x\n",
506 link_status[0], link_status[1], link_status[2],
507 link_status[3], link_status[4], link_status[5]);
746c1aa4
DA		 508 return true;
509}
510
d4877cf2
AD		 511bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
512{
513 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
514 u8 link_status[DP_LINK_STATUS_SIZE];
515
516 if (!atom_dp_get_link_status(radeon_connector, link_status))
517 return false;
518 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
519 return false;
520 return true;
521}
522
746c1aa4
DA		 523static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
524{
5801ead6
AD		 525 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
526
527 if (dig_connector->dpcd[0] >= 0x11) {
1a66c95a 528 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
746c1aa4
DA		 529 &power_state);
530 }
531}
532
5801ead6
AD		 533static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
534{
535 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
536 &downspread);
537}
538
539static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
540 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
541{
542 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
543 link_configuration);
544}
545
746c1aa4 546static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
5801ead6 547 struct drm_encoder *encoder,
746c1aa4
DA		 548 u8 train_set[4])
549{
5801ead6
AD		 550 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
551 int i;
552
553 for (i = 0; i < dig_connector->dp_lane_count; i++)
554 atombios_dig_transmitter_setup(encoder,
555 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
556 i, train_set[i]);
746c1aa4 557
746c1aa4 558 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
5801ead6 559 dig_connector->dp_lane_count, train_set);
746c1aa4
DA		 560}
561
562static void dp_set_training(struct radeon_connector *radeon_connector,
563 u8 training)
564{
565 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
566 1, &training);
567}
568
5801ead6
AD		 569void dp_link_train(struct drm_encoder *encoder,
570 struct drm_connector *connector)
571{
572 struct drm_device *dev = encoder->dev;
573 struct radeon_device *rdev = dev->dev_private;
574 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
575 struct radeon_encoder_atom_dig *dig;
576 struct radeon_connector *radeon_connector;
577 struct radeon_connector_atom_dig *dig_connector;
578 int enc_id = 0;
579 bool clock_recovery, channel_eq;
580 u8 link_status[DP_LINK_STATUS_SIZE];
581 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
582 u8 tries, voltage;
583 u8 train_set[4];
584 int i;
585
196c58d2
AD		 586 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) ||
587 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
5801ead6
AD		 588 return;
589
590 if (!radeon_encoder->enc_priv)
591 return;
592 dig = radeon_encoder->enc_priv;
593
594 radeon_connector = to_radeon_connector(connector);
595 if (!radeon_connector->con_priv)
596 return;
597 dig_connector = radeon_connector->con_priv;
598
599 if (ASIC_IS_DCE32(rdev)) {
600 if (dig->dig_block)
601 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
602 else
603 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
604 if (dig_connector->linkb)
605 enc_id |= ATOM_DP_CONFIG_LINK_B;
606 else
607 enc_id |= ATOM_DP_CONFIG_LINK_A;
608 } else {
609 if (dig_connector->linkb)
610 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B;
611 else
612 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A;
613 }
614
615 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
616 if (dig_connector->dp_clock == 270000)
617 link_configuration[0] = DP_LINK_BW_2_7;
618 else
619 link_configuration[0] = DP_LINK_BW_1_62;
620 link_configuration[1] = dig_connector->dp_lane_count;
621 if (dig_connector->dpcd[0] >= 0x11)
622 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
623
624 /* power up the sink */
625 dp_set_power(radeon_connector, DP_SET_POWER_D0);
626 /* disable the training pattern on the sink */
627 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
628 /* set link bw and lanes on the sink */
629 dp_set_link_bw_lanes(radeon_connector, link_configuration);
630 /* disable downspread on the sink */
631 dp_set_downspread(radeon_connector, 0);
632 /* start training on the source */
633 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
634 dig_connector->dp_clock, enc_id, 0);
635 /* set training pattern 1 on the source */
636 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
637 dig_connector->dp_clock, enc_id, 0);
638
639 /* set initial vs/emph */
640 memset(train_set, 0, 4);
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AD		 641 udelay(400);
642 /* set training pattern 1 on the sink */
643 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
644
5fbfce7f
DA		 645 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
646
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AD		 647 /* clock recovery loop */
648 clock_recovery = false;
649 tries = 0;
650 voltage = 0xff;
651 for (;;) {
652 udelay(100);
653 if (!atom_dp_get_link_status(radeon_connector, link_status))
654 break;
655
656 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
657 clock_recovery = true;
658 break;
659 }
660
661 for (i = 0; i < dig_connector->dp_lane_count; i++) {
662 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
663 break;
664 }
665 if (i == dig_connector->dp_lane_count) {
666 DRM_ERROR("clock recovery reached max voltage\n");
667 break;
668 }
669
670 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
671 ++tries;
672 if (tries == 5) {
673 DRM_ERROR("clock recovery tried 5 times\n");
674 break;
675 }
676 } else
677 tries = 0;
678
679 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
680
681 /* Compute new train_set as requested by sink */
682 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
683 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
684 }
685 if (!clock_recovery)
686 DRM_ERROR("clock recovery failed\n");
687 else
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AD		 688 DRM_DEBUG("clock recovery at voltage %d pre-emphasis %d\n",
689 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
690 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
691 DP_TRAIN_PRE_EMPHASIS_SHIFT);
5801ead6
AD		 692
693
694 /* set training pattern 2 on the sink */
695 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
696 /* set training pattern 2 on the source */
697 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
698 dig_connector->dp_clock, enc_id, 1);
699
700 /* channel equalization loop */
701 tries = 0;
702 channel_eq = false;
703 for (;;) {
704 udelay(400);
705 if (!atom_dp_get_link_status(radeon_connector, link_status))
706 break;
707
708 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
709 channel_eq = true;
710 break;
711 }
712
713 /* Try 5 times */
714 if (tries > 5) {
715 DRM_ERROR("channel eq failed: 5 tries\n");
716 break;
717 }
718
719 /* Compute new train_set as requested by sink */
720 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
721 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
722
723 tries++;
724 }
725
726 if (!channel_eq)
727 DRM_ERROR("channel eq failed\n");
728 else
53c1e09f
AD		 729 DRM_DEBUG("channel eq at voltage %d pre-emphasis %d\n",
730 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
731 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
732 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
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AD		 733
734 /* disable the training pattern on the sink */
735 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
736
737 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
738 dig_connector->dp_clock, enc_id, 0);
739}
740
746c1aa4
DA		 741int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
742 uint8_t write_byte, uint8_t *read_byte)
743{
744 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
745 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
746 int ret = 0;
747 uint16_t address = algo_data->address;
748 uint8_t msg[5];
749 uint8_t reply[2];
750 int msg_len, dp_msg_len;
751 int reply_bytes;
752
753 /* Set up the command byte */
754 if (mode & MODE_I2C_READ)
755 msg[2] = AUX_I2C_READ << 4;
756 else
757 msg[2] = AUX_I2C_WRITE << 4;
758
759 if (!(mode & MODE_I2C_STOP))
760 msg[2] |= AUX_I2C_MOT << 4;
761
762 msg[0] = address;
763 msg[1] = address >> 8;
764
765 reply_bytes = 1;
766
767 msg_len = 4;
768 dp_msg_len = 3;
769 switch (mode) {
770 case MODE_I2C_WRITE:
771 msg[4] = write_byte;
772 msg_len++;
773 dp_msg_len += 2;
774 break;
775 case MODE_I2C_READ:
776 dp_msg_len += 1;
777 break;
778 default:
779 break;
780 }
781
782 msg[3] = (dp_msg_len) << 4;
783 ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
784
785 if (ret) {
786 if (read_byte)
787 *read_byte = reply[0];
788 return reply_bytes;
789 }
790 return -EREMOTEIO;
791}
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Linux 6.x block layer and io_uring tree(s)