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746c1aa4 DA |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
8d1c702a | 25 | * Jerome Glisse |
746c1aa4 | 26 | */ |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
746c1aa4 DA |
29 | #include "radeon.h" |
30 | ||
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
760285e7 | 33 | #include <drm/drm_dp_helper.h> |
746c1aa4 | 34 | |
f92a8b67 | 35 | /* move these to drm_dp_helper.c/h */ |
5801ead6 | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
5801ead6 AD |
37 | #define DP_DPCD_SIZE 8 |
38 | ||
39 | static char *voltage_names[] = { | |
40 | "0.4V", "0.6V", "0.8V", "1.2V" | |
41 | }; | |
42 | static char *pre_emph_names[] = { | |
43 | "0dB", "3.5dB", "6dB", "9.5dB" | |
44 | }; | |
f92a8b67 | 45 | |
224d94b1 AD |
46 | /***** radeon AUX functions *****/ |
47 | union aux_channel_transaction { | |
48 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; | |
49 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; | |
f92a8b67 AD |
50 | }; |
51 | ||
224d94b1 AD |
52 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
53 | u8 *send, int send_bytes, | |
54 | u8 *recv, int recv_size, | |
55 | u8 delay, u8 *ack) | |
56 | { | |
57 | struct drm_device *dev = chan->dev; | |
58 | struct radeon_device *rdev = dev->dev_private; | |
59 | union aux_channel_transaction args; | |
60 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); | |
61 | unsigned char *base; | |
62 | int recv_bytes; | |
63 | ||
64 | memset(&args, 0, sizeof(args)); | |
f92a8b67 | 65 | |
97412a7a | 66 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
224d94b1 AD |
67 | |
68 | memcpy(base, send, send_bytes); | |
69 | ||
97412a7a AD |
70 | args.v1.lpAuxRequest = 0 + 4; |
71 | args.v1.lpDataOut = 16 + 4; | |
224d94b1 AD |
72 | args.v1.ucDataOutLen = 0; |
73 | args.v1.ucChannelID = chan->rec.i2c_id; | |
74 | args.v1.ucDelay = delay / 10; | |
75 | if (ASIC_IS_DCE4(rdev)) | |
76 | args.v2.ucHPD_ID = chan->rec.hpd; | |
77 | ||
78 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
79 | ||
80 | *ack = args.v1.ucReplyStatus; | |
81 | ||
82 | /* timeout */ | |
83 | if (args.v1.ucReplyStatus == 1) { | |
84 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); | |
85 | return -ETIMEDOUT; | |
86 | } | |
87 | ||
88 | /* flags not zero */ | |
89 | if (args.v1.ucReplyStatus == 2) { | |
90 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); | |
91 | return -EBUSY; | |
92 | } | |
93 | ||
94 | /* error */ | |
95 | if (args.v1.ucReplyStatus == 3) { | |
96 | DRM_DEBUG_KMS("dp_aux_ch error\n"); | |
97 | return -EIO; | |
98 | } | |
99 | ||
100 | recv_bytes = args.v1.ucDataOutLen; | |
101 | if (recv_bytes > recv_size) | |
102 | recv_bytes = recv_size; | |
103 | ||
104 | if (recv && recv_size) | |
105 | memcpy(recv, base + 16, recv_bytes); | |
106 | ||
107 | return recv_bytes; | |
108 | } | |
109 | ||
110 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, | |
111 | u16 address, u8 *send, u8 send_bytes, u8 delay) | |
f92a8b67 | 112 | { |
224d94b1 AD |
113 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
114 | int ret; | |
115 | u8 msg[20]; | |
116 | int msg_bytes = send_bytes + 4; | |
117 | u8 ack; | |
6375bda0 | 118 | unsigned retry; |
5801ead6 | 119 | |
224d94b1 AD |
120 | if (send_bytes > 16) |
121 | return -1; | |
5801ead6 | 122 | |
224d94b1 AD |
123 | msg[0] = address; |
124 | msg[1] = address >> 8; | |
125 | msg[2] = AUX_NATIVE_WRITE << 4; | |
126 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); | |
127 | memcpy(&msg[4], send, send_bytes); | |
f92a8b67 | 128 | |
6375bda0 | 129 | for (retry = 0; retry < 4; retry++) { |
224d94b1 AD |
130 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
131 | msg, msg_bytes, NULL, 0, delay, &ack); | |
4f332844 AD |
132 | if (ret == -EBUSY) |
133 | continue; | |
134 | else if (ret < 0) | |
224d94b1 AD |
135 | return ret; |
136 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
6375bda0 | 137 | return send_bytes; |
224d94b1 AD |
138 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
139 | udelay(400); | |
140 | else | |
141 | return -EIO; | |
f92a8b67 AD |
142 | } |
143 | ||
6375bda0 | 144 | return -EIO; |
f92a8b67 AD |
145 | } |
146 | ||
224d94b1 AD |
147 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
148 | u16 address, u8 *recv, int recv_bytes, u8 delay) | |
f92a8b67 | 149 | { |
224d94b1 AD |
150 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
151 | u8 msg[4]; | |
152 | int msg_bytes = 4; | |
153 | u8 ack; | |
154 | int ret; | |
6375bda0 | 155 | unsigned retry; |
5801ead6 | 156 | |
224d94b1 AD |
157 | msg[0] = address; |
158 | msg[1] = address >> 8; | |
159 | msg[2] = AUX_NATIVE_READ << 4; | |
160 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); | |
5801ead6 | 161 | |
6375bda0 | 162 | for (retry = 0; retry < 4; retry++) { |
224d94b1 AD |
163 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
164 | msg, msg_bytes, recv, recv_bytes, delay, &ack); | |
4f332844 AD |
165 | if (ret == -EBUSY) |
166 | continue; | |
167 | else if (ret < 0) | |
224d94b1 AD |
168 | return ret; |
169 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
170 | return ret; | |
171 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
172 | udelay(400); | |
109bc10d AD |
173 | else if (ret == 0) |
174 | return -EPROTO; | |
224d94b1 AD |
175 | else |
176 | return -EIO; | |
177 | } | |
6375bda0 AD |
178 | |
179 | return -EIO; | |
224d94b1 | 180 | } |
f92a8b67 | 181 | |
224d94b1 AD |
182 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
183 | u16 reg, u8 val) | |
184 | { | |
185 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); | |
186 | } | |
187 | ||
188 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, | |
189 | u16 reg) | |
190 | { | |
191 | u8 val = 0; | |
192 | ||
193 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); | |
194 | ||
195 | return val; | |
196 | } | |
197 | ||
198 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | |
199 | u8 write_byte, u8 *read_byte) | |
200 | { | |
201 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
202 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; | |
203 | u16 address = algo_data->address; | |
204 | u8 msg[5]; | |
205 | u8 reply[2]; | |
206 | unsigned retry; | |
207 | int msg_bytes; | |
208 | int reply_bytes = 1; | |
209 | int ret; | |
210 | u8 ack; | |
211 | ||
212 | /* Set up the command byte */ | |
213 | if (mode & MODE_I2C_READ) | |
214 | msg[2] = AUX_I2C_READ << 4; | |
215 | else | |
216 | msg[2] = AUX_I2C_WRITE << 4; | |
217 | ||
218 | if (!(mode & MODE_I2C_STOP)) | |
219 | msg[2] |= AUX_I2C_MOT << 4; | |
220 | ||
221 | msg[0] = address; | |
222 | msg[1] = address >> 8; | |
223 | ||
224 | switch (mode) { | |
225 | case MODE_I2C_WRITE: | |
226 | msg_bytes = 5; | |
227 | msg[3] = msg_bytes << 4; | |
228 | msg[4] = write_byte; | |
229 | break; | |
230 | case MODE_I2C_READ: | |
231 | msg_bytes = 4; | |
232 | msg[3] = msg_bytes << 4; | |
233 | break; | |
f92a8b67 | 234 | default: |
224d94b1 AD |
235 | msg_bytes = 4; |
236 | msg[3] = 3 << 4; | |
f92a8b67 | 237 | break; |
f92a8b67 AD |
238 | } |
239 | ||
224d94b1 AD |
240 | for (retry = 0; retry < 4; retry++) { |
241 | ret = radeon_process_aux_ch(auxch, | |
242 | msg, msg_bytes, reply, reply_bytes, 0, &ack); | |
4f332844 AD |
243 | if (ret == -EBUSY) |
244 | continue; | |
245 | else if (ret < 0) { | |
224d94b1 AD |
246 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
247 | return ret; | |
248 | } | |
f92a8b67 | 249 | |
224d94b1 AD |
250 | switch (ack & AUX_NATIVE_REPLY_MASK) { |
251 | case AUX_NATIVE_REPLY_ACK: | |
252 | /* I2C-over-AUX Reply field is only valid | |
253 | * when paired with AUX ACK. | |
254 | */ | |
255 | break; | |
256 | case AUX_NATIVE_REPLY_NACK: | |
257 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
258 | return -EREMOTEIO; | |
259 | case AUX_NATIVE_REPLY_DEFER: | |
260 | DRM_DEBUG_KMS("aux_ch native defer\n"); | |
261 | udelay(400); | |
262 | continue; | |
263 | default: | |
264 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); | |
265 | return -EREMOTEIO; | |
266 | } | |
5801ead6 | 267 | |
224d94b1 AD |
268 | switch (ack & AUX_I2C_REPLY_MASK) { |
269 | case AUX_I2C_REPLY_ACK: | |
270 | if (mode == MODE_I2C_READ) | |
271 | *read_byte = reply[0]; | |
272 | return ret; | |
273 | case AUX_I2C_REPLY_NACK: | |
274 | DRM_DEBUG_KMS("aux_i2c nack\n"); | |
275 | return -EREMOTEIO; | |
276 | case AUX_I2C_REPLY_DEFER: | |
277 | DRM_DEBUG_KMS("aux_i2c defer\n"); | |
278 | udelay(400); | |
279 | break; | |
280 | default: | |
281 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); | |
282 | return -EREMOTEIO; | |
283 | } | |
284 | } | |
5801ead6 | 285 | |
091264f0 | 286 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
224d94b1 | 287 | return -EREMOTEIO; |
5801ead6 AD |
288 | } |
289 | ||
224d94b1 AD |
290 | /***** general DP utility functions *****/ |
291 | ||
5801ead6 AD |
292 | static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) |
293 | { | |
294 | return link_status[r - DP_LANE0_1_STATUS]; | |
295 | } | |
296 | ||
297 | static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], | |
298 | int lane) | |
299 | { | |
300 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
301 | int s = (lane & 1) * 4; | |
302 | u8 l = dp_link_status(link_status, i); | |
303 | return (l >> s) & 0xf; | |
304 | } | |
305 | ||
306 | static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], | |
307 | int lane_count) | |
308 | { | |
309 | int lane; | |
310 | u8 lane_status; | |
311 | ||
312 | for (lane = 0; lane < lane_count; lane++) { | |
313 | lane_status = dp_get_lane_status(link_status, lane); | |
314 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
315 | return false; | |
316 | } | |
317 | return true; | |
318 | } | |
319 | ||
224d94b1 | 320 | static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
5801ead6 AD |
321 | int lane) |
322 | ||
323 | { | |
324 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
325 | int s = ((lane & 1) ? | |
326 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
327 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
328 | u8 l = dp_link_status(link_status, i); | |
329 | ||
330 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
331 | } | |
332 | ||
224d94b1 | 333 | static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
5801ead6 AD |
334 | int lane) |
335 | { | |
336 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
337 | int s = ((lane & 1) ? | |
338 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
339 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
340 | u8 l = dp_link_status(link_status, i); | |
341 | ||
342 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
343 | } | |
344 | ||
5801ead6 | 345 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
224d94b1 | 346 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
5801ead6 AD |
347 | |
348 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], | |
349 | int lane_count, | |
350 | u8 train_set[4]) | |
351 | { | |
352 | u8 v = 0; | |
353 | u8 p = 0; | |
354 | int lane; | |
355 | ||
356 | for (lane = 0; lane < lane_count; lane++) { | |
357 | u8 this_v = dp_get_adjust_request_voltage(link_status, lane); | |
358 | u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); | |
359 | ||
d9fdaafb | 360 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
53c1e09f AD |
361 | lane, |
362 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], | |
363 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
364 | |
365 | if (this_v > v) | |
366 | v = this_v; | |
367 | if (this_p > p) | |
368 | p = this_p; | |
369 | } | |
370 | ||
371 | if (v >= DP_VOLTAGE_MAX) | |
224d94b1 | 372 | v |= DP_TRAIN_MAX_SWING_REACHED; |
5801ead6 | 373 | |
224d94b1 AD |
374 | if (p >= DP_PRE_EMPHASIS_MAX) |
375 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
5801ead6 | 376 | |
d9fdaafb | 377 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
53c1e09f AD |
378 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
379 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); | |
5801ead6 AD |
380 | |
381 | for (lane = 0; lane < 4; lane++) | |
382 | train_set[lane] = v | p; | |
383 | } | |
384 | ||
224d94b1 AD |
385 | /* convert bits per color to bits per pixel */ |
386 | /* get bpc from the EDID */ | |
387 | static int convert_bpc_to_bpp(int bpc) | |
746c1aa4 | 388 | { |
224d94b1 AD |
389 | if (bpc == 0) |
390 | return 24; | |
391 | else | |
392 | return bpc * 3; | |
393 | } | |
746c1aa4 | 394 | |
224d94b1 AD |
395 | /* get the max pix clock supported by the link rate and lane num */ |
396 | static int dp_get_max_dp_pix_clock(int link_rate, | |
397 | int lane_num, | |
398 | int bpp) | |
399 | { | |
400 | return (link_rate * lane_num * 8) / bpp; | |
401 | } | |
834b2904 | 402 | |
224d94b1 AD |
403 | static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE]) |
404 | { | |
405 | switch (dpcd[DP_MAX_LINK_RATE]) { | |
406 | case DP_LINK_BW_1_62: | |
407 | default: | |
408 | return 162000; | |
409 | case DP_LINK_BW_2_7: | |
410 | return 270000; | |
411 | case DP_LINK_BW_5_4: | |
412 | return 540000; | |
834b2904 | 413 | } |
746c1aa4 DA |
414 | } |
415 | ||
224d94b1 | 416 | static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE]) |
746c1aa4 | 417 | { |
224d94b1 AD |
418 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
419 | } | |
834b2904 | 420 | |
224d94b1 AD |
421 | static u8 dp_get_dp_link_rate_coded(int link_rate) |
422 | { | |
423 | switch (link_rate) { | |
424 | case 162000: | |
425 | default: | |
426 | return DP_LINK_BW_1_62; | |
427 | case 270000: | |
428 | return DP_LINK_BW_2_7; | |
429 | case 540000: | |
430 | return DP_LINK_BW_5_4; | |
431 | } | |
432 | } | |
746c1aa4 | 433 | |
224d94b1 | 434 | /***** radeon specific DP functions *****/ |
746c1aa4 | 435 | |
224d94b1 AD |
436 | /* First get the min lane# when low rate is used according to pixel clock |
437 | * (prefer low rate), second check max lane# supported by DP panel, | |
438 | * if the max lane# < low rate lane# then use max lane# instead. | |
439 | */ | |
440 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, | |
441 | u8 dpcd[DP_DPCD_SIZE], | |
442 | int pix_clock) | |
443 | { | |
eccea792 | 444 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
224d94b1 AD |
445 | int max_link_rate = dp_get_max_link_rate(dpcd); |
446 | int max_lane_num = dp_get_max_lane_number(dpcd); | |
447 | int lane_num; | |
448 | int max_dp_pix_clock; | |
449 | ||
450 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { | |
451 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); | |
452 | if (pix_clock <= max_dp_pix_clock) | |
453 | break; | |
834b2904 | 454 | } |
746c1aa4 | 455 | |
224d94b1 | 456 | return lane_num; |
746c1aa4 DA |
457 | } |
458 | ||
224d94b1 AD |
459 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
460 | u8 dpcd[DP_DPCD_SIZE], | |
461 | int pix_clock) | |
746c1aa4 | 462 | { |
eccea792 | 463 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
224d94b1 AD |
464 | int lane_num, max_pix_clock; |
465 | ||
fdca78c3 AD |
466 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
467 | ENCODER_OBJECT_ID_NUTMEG) | |
224d94b1 AD |
468 | return 270000; |
469 | ||
470 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); | |
471 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); | |
472 | if (pix_clock <= max_pix_clock) | |
473 | return 162000; | |
474 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); | |
475 | if (pix_clock <= max_pix_clock) | |
476 | return 270000; | |
477 | if (radeon_connector_is_dp12_capable(connector)) { | |
478 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); | |
479 | if (pix_clock <= max_pix_clock) | |
480 | return 540000; | |
834b2904 | 481 | } |
224d94b1 AD |
482 | |
483 | return dp_get_max_link_rate(dpcd); | |
746c1aa4 DA |
484 | } |
485 | ||
834b2904 AD |
486 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
487 | int action, int dp_clock, | |
224d94b1 | 488 | u8 ucconfig, u8 lane_num) |
5801ead6 AD |
489 | { |
490 | DP_ENCODER_SERVICE_PARAMETERS args; | |
491 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
492 | ||
493 | memset(&args, 0, sizeof(args)); | |
494 | args.ucLinkClock = dp_clock / 10; | |
495 | args.ucConfig = ucconfig; | |
496 | args.ucAction = action; | |
497 | args.ucLaneNum = lane_num; | |
498 | args.ucStatus = 0; | |
499 | ||
500 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
501 | return args.ucStatus; | |
502 | } | |
503 | ||
504 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) | |
505 | { | |
506 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
507 | struct drm_device *dev = radeon_connector->base.dev; | |
508 | struct radeon_device *rdev = dev->dev_private; | |
509 | ||
510 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, | |
511 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); | |
512 | } | |
513 | ||
40c5d876 AJ |
514 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
515 | { | |
516 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; | |
517 | u8 buf[3]; | |
518 | ||
519 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
520 | return; | |
521 | ||
522 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) | |
523 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
524 | buf[0], buf[1], buf[2]); | |
525 | ||
526 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) | |
527 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
528 | buf[0], buf[1], buf[2]); | |
529 | } | |
530 | ||
9fa05c98 | 531 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
746c1aa4 | 532 | { |
5801ead6 | 533 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
746c1aa4 | 534 | u8 msg[25]; |
224d94b1 | 535 | int ret, i; |
746c1aa4 | 536 | |
834b2904 AD |
537 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0); |
538 | if (ret > 0) { | |
5801ead6 | 539 | memcpy(dig_connector->dpcd, msg, 8); |
224d94b1 AD |
540 | DRM_DEBUG_KMS("DPCD: "); |
541 | for (i = 0; i < 8; i++) | |
542 | DRM_DEBUG_KMS("%02x ", msg[i]); | |
543 | DRM_DEBUG_KMS("\n"); | |
40c5d876 AJ |
544 | |
545 | radeon_dp_probe_oui(radeon_connector); | |
546 | ||
9fa05c98 | 547 | return true; |
746c1aa4 | 548 | } |
5801ead6 | 549 | dig_connector->dpcd[0] = 0; |
9fa05c98 | 550 | return false; |
746c1aa4 DA |
551 | } |
552 | ||
386d4d75 AD |
553 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
554 | struct drm_connector *connector) | |
224d94b1 AD |
555 | { |
556 | struct drm_device *dev = encoder->dev; | |
557 | struct radeon_device *rdev = dev->dev_private; | |
00dfb8df | 558 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
224d94b1 | 559 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
0ceb996c AD |
560 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
561 | u8 tmp; | |
224d94b1 AD |
562 | |
563 | if (!ASIC_IS_DCE4(rdev)) | |
386d4d75 | 564 | return panel_mode; |
224d94b1 | 565 | |
0ceb996c AD |
566 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
567 | /* DP bridge chips */ | |
568 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | |
569 | if (tmp & 1) | |
570 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
571 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || | |
572 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) | |
304a4840 AD |
573 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
574 | else | |
0ceb996c | 575 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
304a4840 | 576 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
0ceb996c AD |
577 | /* eDP */ |
578 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); | |
00dfb8df AD |
579 | if (tmp & 1) |
580 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; | |
581 | } | |
224d94b1 | 582 | |
386d4d75 | 583 | return panel_mode; |
224d94b1 AD |
584 | } |
585 | ||
5801ead6 | 586 | void radeon_dp_set_link_config(struct drm_connector *connector, |
e811f5ae | 587 | const struct drm_display_mode *mode) |
5801ead6 | 588 | { |
224d94b1 | 589 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
5801ead6 AD |
590 | struct radeon_connector_atom_dig *dig_connector; |
591 | ||
5801ead6 AD |
592 | if (!radeon_connector->con_priv) |
593 | return; | |
594 | dig_connector = radeon_connector->con_priv; | |
595 | ||
224d94b1 AD |
596 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
597 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { | |
598 | dig_connector->dp_clock = | |
599 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
600 | dig_connector->dp_lane_count = | |
601 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); | |
602 | } | |
5801ead6 AD |
603 | } |
604 | ||
224d94b1 | 605 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
5801ead6 AD |
606 | struct drm_display_mode *mode) |
607 | { | |
224d94b1 AD |
608 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
609 | struct radeon_connector_atom_dig *dig_connector; | |
610 | int dp_clock; | |
5801ead6 | 611 | |
224d94b1 AD |
612 | if (!radeon_connector->con_priv) |
613 | return MODE_CLOCK_HIGH; | |
614 | dig_connector = radeon_connector->con_priv; | |
615 | ||
616 | dp_clock = | |
617 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); | |
618 | ||
619 | if ((dp_clock == 540000) && | |
620 | (!radeon_connector_is_dp12_capable(connector))) | |
621 | return MODE_CLOCK_HIGH; | |
622 | ||
623 | return MODE_OK; | |
5801ead6 AD |
624 | } |
625 | ||
224d94b1 AD |
626 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
627 | u8 link_status[DP_LINK_STATUS_SIZE]) | |
746c1aa4 DA |
628 | { |
629 | int ret; | |
834b2904 AD |
630 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
631 | link_status, DP_LINK_STATUS_SIZE, 100); | |
632 | if (ret <= 0) { | |
746c1aa4 DA |
633 | return false; |
634 | } | |
635 | ||
9a6a4b47 | 636 | DRM_DEBUG_KMS("link status %*ph\n", 6, link_status); |
746c1aa4 DA |
637 | return true; |
638 | } | |
639 | ||
d5811e87 AD |
640 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
641 | { | |
642 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
643 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
644 | ||
645 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) | |
646 | return false; | |
1ffdff13 | 647 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
d5811e87 AD |
648 | return false; |
649 | return true; | |
650 | } | |
651 | ||
224d94b1 AD |
652 | struct radeon_dp_link_train_info { |
653 | struct radeon_device *rdev; | |
654 | struct drm_encoder *encoder; | |
655 | struct drm_connector *connector; | |
656 | struct radeon_connector *radeon_connector; | |
657 | int enc_id; | |
658 | int dp_clock; | |
659 | int dp_lane_count; | |
660 | int rd_interval; | |
661 | bool tp3_supported; | |
662 | u8 dpcd[8]; | |
663 | u8 train_set[4]; | |
664 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
665 | u8 tries; | |
5a96a899 | 666 | bool use_dpencoder; |
224d94b1 | 667 | }; |
5801ead6 | 668 | |
224d94b1 | 669 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 670 | { |
224d94b1 AD |
671 | /* set the initial vs/emph on the source */ |
672 | atombios_dig_transmitter_setup(dp_info->encoder, | |
673 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, | |
674 | 0, dp_info->train_set[0]); /* sets all lanes at once */ | |
675 | ||
676 | /* set the vs/emph on the sink */ | |
677 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, | |
678 | dp_info->train_set, dp_info->dp_lane_count, 0); | |
5801ead6 AD |
679 | } |
680 | ||
224d94b1 | 681 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
746c1aa4 | 682 | { |
224d94b1 | 683 | int rtp = 0; |
746c1aa4 | 684 | |
224d94b1 | 685 | /* set training pattern on the source */ |
5a96a899 | 686 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
224d94b1 AD |
687 | switch (tp) { |
688 | case DP_TRAINING_PATTERN_1: | |
689 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; | |
690 | break; | |
691 | case DP_TRAINING_PATTERN_2: | |
692 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; | |
693 | break; | |
694 | case DP_TRAINING_PATTERN_3: | |
695 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; | |
696 | break; | |
697 | } | |
698 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); | |
699 | } else { | |
700 | switch (tp) { | |
701 | case DP_TRAINING_PATTERN_1: | |
702 | rtp = 0; | |
703 | break; | |
704 | case DP_TRAINING_PATTERN_2: | |
705 | rtp = 1; | |
706 | break; | |
707 | } | |
708 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, | |
709 | dp_info->dp_clock, dp_info->enc_id, rtp); | |
710 | } | |
746c1aa4 | 711 | |
224d94b1 AD |
712 | /* enable training pattern on the sink */ |
713 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); | |
746c1aa4 DA |
714 | } |
715 | ||
224d94b1 | 716 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
5801ead6 | 717 | { |
386d4d75 AD |
718 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
719 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
224d94b1 | 720 | u8 tmp; |
5801ead6 | 721 | |
224d94b1 AD |
722 | /* power up the sink */ |
723 | if (dp_info->dpcd[0] >= 0x11) | |
724 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
725 | DP_SET_POWER, DP_SET_POWER_D0); | |
726 | ||
727 | /* possibly enable downspread on the sink */ | |
728 | if (dp_info->dpcd[3] & 0x1) | |
729 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
730 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); | |
731 | else | |
732 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
733 | DP_DOWNSPREAD_CTRL, 0); | |
5801ead6 | 734 | |
386d4d75 AD |
735 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
736 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { | |
737 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); | |
738 | } | |
5801ead6 | 739 | |
224d94b1 AD |
740 | /* set the lane count on the sink */ |
741 | tmp = dp_info->dp_lane_count; | |
abc8113f DA |
742 | if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && |
743 | dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) | |
224d94b1 AD |
744 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
745 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); | |
5801ead6 | 746 | |
224d94b1 AD |
747 | /* set the link rate on the sink */ |
748 | tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock); | |
749 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); | |
5801ead6 | 750 | |
224d94b1 | 751 | /* start training on the source */ |
5a96a899 | 752 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
753 | atombios_dig_encoder_setup(dp_info->encoder, |
754 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); | |
5801ead6 | 755 | else |
224d94b1 AD |
756 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
757 | dp_info->dp_clock, dp_info->enc_id, 0); | |
5801ead6 | 758 | |
5801ead6 | 759 | /* disable the training pattern on the sink */ |
224d94b1 AD |
760 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
761 | DP_TRAINING_PATTERN_SET, | |
762 | DP_TRAINING_PATTERN_DISABLE); | |
763 | ||
764 | return 0; | |
765 | } | |
5801ead6 | 766 | |
224d94b1 AD |
767 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
768 | { | |
5801ead6 | 769 | udelay(400); |
5801ead6 | 770 | |
224d94b1 AD |
771 | /* disable the training pattern on the sink */ |
772 | radeon_write_dpcd_reg(dp_info->radeon_connector, | |
773 | DP_TRAINING_PATTERN_SET, | |
774 | DP_TRAINING_PATTERN_DISABLE); | |
775 | ||
776 | /* disable the training pattern on the source */ | |
5a96a899 | 777 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
224d94b1 AD |
778 | atombios_dig_encoder_setup(dp_info->encoder, |
779 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); | |
780 | else | |
781 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, | |
782 | dp_info->dp_clock, dp_info->enc_id, 0); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
787 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) | |
788 | { | |
789 | bool clock_recovery; | |
790 | u8 voltage; | |
791 | int i; | |
792 | ||
793 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); | |
794 | memset(dp_info->train_set, 0, 4); | |
795 | radeon_dp_update_vs_emph(dp_info); | |
796 | ||
797 | udelay(400); | |
5fbfce7f | 798 | |
5801ead6 AD |
799 | /* clock recovery loop */ |
800 | clock_recovery = false; | |
224d94b1 | 801 | dp_info->tries = 0; |
5801ead6 | 802 | voltage = 0xff; |
224d94b1 AD |
803 | while (1) { |
804 | if (dp_info->rd_interval == 0) | |
805 | udelay(100); | |
806 | else | |
807 | mdelay(dp_info->rd_interval * 4); | |
808 | ||
8d1c702a JG |
809 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
810 | DRM_ERROR("displayport link status failed\n"); | |
5801ead6 | 811 | break; |
8d1c702a | 812 | } |
5801ead6 | 813 | |
224d94b1 | 814 | if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
815 | clock_recovery = true; |
816 | break; | |
817 | } | |
818 | ||
224d94b1 AD |
819 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
820 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
5801ead6 AD |
821 | break; |
822 | } | |
224d94b1 | 823 | if (i == dp_info->dp_lane_count) { |
5801ead6 AD |
824 | DRM_ERROR("clock recovery reached max voltage\n"); |
825 | break; | |
826 | } | |
827 | ||
224d94b1 AD |
828 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
829 | ++dp_info->tries; | |
830 | if (dp_info->tries == 5) { | |
5801ead6 AD |
831 | DRM_ERROR("clock recovery tried 5 times\n"); |
832 | break; | |
833 | } | |
834 | } else | |
224d94b1 | 835 | dp_info->tries = 0; |
5801ead6 | 836 | |
224d94b1 | 837 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
5801ead6 AD |
838 | |
839 | /* Compute new train_set as requested by sink */ | |
224d94b1 AD |
840 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
841 | ||
842 | radeon_dp_update_vs_emph(dp_info); | |
5801ead6 | 843 | } |
224d94b1 | 844 | if (!clock_recovery) { |
5801ead6 | 845 | DRM_ERROR("clock recovery failed\n"); |
224d94b1 AD |
846 | return -1; |
847 | } else { | |
d9fdaafb | 848 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
849 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
850 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
53c1e09f | 851 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
852 | return 0; |
853 | } | |
854 | } | |
5801ead6 | 855 | |
224d94b1 AD |
856 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
857 | { | |
858 | bool channel_eq; | |
5801ead6 | 859 | |
224d94b1 AD |
860 | if (dp_info->tp3_supported) |
861 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); | |
bcc1c2a1 | 862 | else |
224d94b1 | 863 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
5801ead6 AD |
864 | |
865 | /* channel equalization loop */ | |
224d94b1 | 866 | dp_info->tries = 0; |
5801ead6 | 867 | channel_eq = false; |
224d94b1 AD |
868 | while (1) { |
869 | if (dp_info->rd_interval == 0) | |
870 | udelay(400); | |
871 | else | |
872 | mdelay(dp_info->rd_interval * 4); | |
873 | ||
8d1c702a JG |
874 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
875 | DRM_ERROR("displayport link status failed\n"); | |
5801ead6 | 876 | break; |
8d1c702a | 877 | } |
5801ead6 | 878 | |
1ffdff13 | 879 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
5801ead6 AD |
880 | channel_eq = true; |
881 | break; | |
882 | } | |
883 | ||
884 | /* Try 5 times */ | |
224d94b1 | 885 | if (dp_info->tries > 5) { |
5801ead6 AD |
886 | DRM_ERROR("channel eq failed: 5 tries\n"); |
887 | break; | |
888 | } | |
889 | ||
890 | /* Compute new train_set as requested by sink */ | |
224d94b1 | 891 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
5801ead6 | 892 | |
224d94b1 AD |
893 | radeon_dp_update_vs_emph(dp_info); |
894 | dp_info->tries++; | |
5801ead6 AD |
895 | } |
896 | ||
224d94b1 | 897 | if (!channel_eq) { |
5801ead6 | 898 | DRM_ERROR("channel eq failed\n"); |
224d94b1 AD |
899 | return -1; |
900 | } else { | |
d9fdaafb | 901 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
224d94b1 AD |
902 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
903 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) | |
53c1e09f | 904 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
224d94b1 AD |
905 | return 0; |
906 | } | |
5801ead6 AD |
907 | } |
908 | ||
224d94b1 AD |
909 | void radeon_dp_link_train(struct drm_encoder *encoder, |
910 | struct drm_connector *connector) | |
746c1aa4 | 911 | { |
224d94b1 AD |
912 | struct drm_device *dev = encoder->dev; |
913 | struct radeon_device *rdev = dev->dev_private; | |
914 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
915 | struct radeon_encoder_atom_dig *dig; | |
916 | struct radeon_connector *radeon_connector; | |
917 | struct radeon_connector_atom_dig *dig_connector; | |
918 | struct radeon_dp_link_train_info dp_info; | |
5a96a899 JG |
919 | int index; |
920 | u8 tmp, frev, crev; | |
746c1aa4 | 921 | |
224d94b1 AD |
922 | if (!radeon_encoder->enc_priv) |
923 | return; | |
924 | dig = radeon_encoder->enc_priv; | |
746c1aa4 | 925 | |
224d94b1 AD |
926 | radeon_connector = to_radeon_connector(connector); |
927 | if (!radeon_connector->con_priv) | |
928 | return; | |
929 | dig_connector = radeon_connector->con_priv; | |
834b2904 | 930 | |
224d94b1 AD |
931 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
932 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) | |
933 | return; | |
746c1aa4 | 934 | |
5a96a899 JG |
935 | /* DPEncoderService newer than 1.1 can't program properly the |
936 | * training pattern. When facing such version use the | |
937 | * DIGXEncoderControl (X== 1 | 2) | |
938 | */ | |
939 | dp_info.use_dpencoder = true; | |
940 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); | |
941 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { | |
942 | if (crev > 1) { | |
943 | dp_info.use_dpencoder = false; | |
944 | } | |
945 | } | |
946 | ||
224d94b1 AD |
947 | dp_info.enc_id = 0; |
948 | if (dig->dig_encoder) | |
949 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; | |
950 | else | |
951 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; | |
952 | if (dig->linkb) | |
953 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; | |
954 | else | |
955 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; | |
834b2904 | 956 | |
224d94b1 AD |
957 | dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL); |
958 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); | |
959 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) | |
960 | dp_info.tp3_supported = true; | |
961 | else | |
962 | dp_info.tp3_supported = false; | |
963 | ||
964 | memcpy(dp_info.dpcd, dig_connector->dpcd, 8); | |
965 | dp_info.rdev = rdev; | |
966 | dp_info.encoder = encoder; | |
967 | dp_info.connector = connector; | |
968 | dp_info.radeon_connector = radeon_connector; | |
969 | dp_info.dp_lane_count = dig_connector->dp_lane_count; | |
970 | dp_info.dp_clock = dig_connector->dp_clock; | |
971 | ||
972 | if (radeon_dp_link_train_init(&dp_info)) | |
973 | goto done; | |
974 | if (radeon_dp_link_train_cr(&dp_info)) | |
975 | goto done; | |
976 | if (radeon_dp_link_train_ce(&dp_info)) | |
977 | goto done; | |
978 | done: | |
979 | if (radeon_dp_link_train_finish(&dp_info)) | |
980 | return; | |
746c1aa4 | 981 | } |