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Merge tag 'drm-intel-fixes-2014-11-07' of git://anongit.freedesktop.org/drm-intel...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_dp.c
CommitLineData
746c1aa4
DA		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
8d1c702a 25 * Jerome Glisse
746c1aa4 26 */
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/radeon_drm.h>
746c1aa4
DA		 29#include "radeon.h"
30
31#include "atom.h"
32#include "atom-bits.h"
760285e7 33#include <drm/drm_dp_helper.h>
746c1aa4 34
f92a8b67 35/* move these to drm_dp_helper.c/h */
5801ead6 36#define DP_LINK_CONFIGURATION_SIZE 9
1a644cd4 37#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
5801ead6
AD		 38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
f92a8b67 45
224d94b1 46/***** radeon AUX functions *****/
34be8c9a
AD		 47
48/* Atom needs data in little endian format
49 * so swap as appropriate when copying data to
50 * or from atom. Note that atom operates on
51 * dw units.
52 */
4543eda5 53void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
34be8c9a
AD		 54{
55#ifdef __BIG_ENDIAN
56 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57 u32 *dst32, *src32;
58 int i;
59
60 memcpy(src_tmp, src, num_bytes);
61 src32 = (u32 *)src_tmp;
62 dst32 = (u32 *)dst_tmp;
63 if (to_le) {
64 for (i = 0; i < ((num_bytes + 3) / 4); i++)
65 dst32[i] = cpu_to_le32(src32[i]);
66 memcpy(dst, dst_tmp, num_bytes);
67 } else {
68 u8 dws = num_bytes & ~3;
69 for (i = 0; i < ((num_bytes + 3) / 4); i++)
70 dst32[i] = le32_to_cpu(src32[i]);
71 memcpy(dst, dst_tmp, dws);
72 if (num_bytes % 4) {
73 for (i = 0; i < (num_bytes % 4); i++)
74 dst[dws+i] = dst_tmp[dws+i];
75 }
76 }
77#else
78 memcpy(dst, src, num_bytes);
79#endif
80}
81
224d94b1
AD		 82union aux_channel_transaction {
83 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
84 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
f92a8b67
AD		 85};
86
224d94b1
AD		 87static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
88 u8 *send, int send_bytes,
89 u8 *recv, int recv_size,
90 u8 delay, u8 *ack)
91{
92 struct drm_device *dev = chan->dev;
93 struct radeon_device *rdev = dev->dev_private;
94 union aux_channel_transaction args;
95 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
96 unsigned char *base;
97 int recv_bytes;
831719d6 98 int r = 0;
224d94b1
AD		 99
100 memset(&args, 0, sizeof(args));
f92a8b67 101
831719d6
AD		 102 mutex_lock(&chan->mutex);
103
97412a7a 104 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
224d94b1 105
4543eda5 106 radeon_atom_copy_swap(base, send, send_bytes, true);
224d94b1 107
34be8c9a
AD		 108 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
109 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
224d94b1
AD		 110 args.v1.ucDataOutLen = 0;
111 args.v1.ucChannelID = chan->rec.i2c_id;
112 args.v1.ucDelay = delay / 10;
113 if (ASIC_IS_DCE4(rdev))
114 args.v2.ucHPD_ID = chan->rec.hpd;
115
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117
118 *ack = args.v1.ucReplyStatus;
119
120 /* timeout */
121 if (args.v1.ucReplyStatus == 1) {
122 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
831719d6
AD		 123 r = -ETIMEDOUT;
124 goto done;
224d94b1
AD		 125 }
126
127 /* flags not zero */
128 if (args.v1.ucReplyStatus == 2) {
129 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
f6be5e64 130 r = -EIO;
831719d6 131 goto done;
224d94b1
AD		 132 }
133
134 /* error */
135 if (args.v1.ucReplyStatus == 3) {
136 DRM_DEBUG_KMS("dp_aux_ch error\n");
831719d6
AD		 137 r = -EIO;
138 goto done;
224d94b1
AD		 139 }
140
141 recv_bytes = args.v1.ucDataOutLen;
142 if (recv_bytes > recv_size)
143 recv_bytes = recv_size;
144
145 if (recv && recv_size)
4543eda5 146 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
224d94b1 147
831719d6
AD		 148 r = recv_bytes;
149done:
150 mutex_unlock(&chan->mutex);
151
152 return r;
224d94b1
AD		 153}
154
25377b92
AD		 155#define BARE_ADDRESS_SIZE 3
156#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
5801ead6 157
496263bf
AD		 158static ssize_t
159radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
f92a8b67 160{
496263bf
AD		 161 struct radeon_i2c_chan *chan =
162 container_of(aux, struct radeon_i2c_chan, aux);
224d94b1 163 int ret;
496263bf
AD		 164 u8 tx_buf[20];
165 size_t tx_size;
166 u8 ack, delay = 0;
167
168 if (WARN_ON(msg->size > 16))
169 return -E2BIG;
170
171 tx_buf[0] = msg->address & 0xff;
172 tx_buf[1] = msg->address >> 8;
173 tx_buf[2] = msg->request << 4;
25377b92 174 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
496263bf
AD		 175
176 switch (msg->request & ~DP_AUX_I2C_MOT) {
177 case DP_AUX_NATIVE_WRITE:
178 case DP_AUX_I2C_WRITE:
25377b92
AD		 179 /* tx_size needs to be 4 even for bare address packets since the atom
180 * table needs the info in tx_buf[3].
181 */
496263bf 182 tx_size = HEADER_SIZE + msg->size;
25377b92
AD		 183 if (msg->size == 0)
184 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
185 else
186 tx_buf[3] |= tx_size << 4;
496263bf
AD		 187 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
188 ret = radeon_process_aux_ch(chan,
189 tx_buf, tx_size, NULL, 0, delay, &ack);
190 if (ret >= 0)
191 /* Return payload size. */
192 ret = msg->size;
193 break;
194 case DP_AUX_NATIVE_READ:
195 case DP_AUX_I2C_READ:
25377b92
AD		 196 /* tx_size needs to be 4 even for bare address packets since the atom
197 * table needs the info in tx_buf[3].
198 */
496263bf 199 tx_size = HEADER_SIZE;
25377b92
AD		 200 if (msg->size == 0)
201 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
202 else
203 tx_buf[3] |= tx_size << 4;
496263bf
AD		 204 ret = radeon_process_aux_ch(chan,
205 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
206 break;
207 default:
208 ret = -EINVAL;
209 break;
224d94b1 210 }
6375bda0 211
25377b92 212 if (ret >= 0)
496263bf 213 msg->reply = ack >> 4;
f92a8b67 214
496263bf 215 return ret;
224d94b1
AD		 216}
217
496263bf 218void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
224d94b1 219{
224d94b1 220 int ret;
f92a8b67 221
ad47b8fa 222 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
379dfc25
AD		 223 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
224 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
4f71d0cb
DA		 225
226 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
379dfc25
AD		 227 if (!ret)
228 radeon_connector->ddc_bus->has_aux = true;
f92a8b67 229
4f71d0cb 230 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
5801ead6
AD		 231}
232
224d94b1
AD		 233/***** general DP utility functions *****/
234
9cecb371
SJ		 235#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
236#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
5801ead6
AD		 237
238static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
239 int lane_count,
240 u8 train_set[4])
241{
242 u8 v = 0;
243 u8 p = 0;
244 int lane;
245
246 for (lane = 0; lane < lane_count; lane++) {
0f037bde
DV		 247 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
248 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
5801ead6 249
d9fdaafb 250 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
53c1e09f
AD		 251 lane,
252 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
253 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 254
255 if (this_v > v)
256 v = this_v;
257 if (this_p > p)
258 p = this_p;
259 }
260
261 if (v >= DP_VOLTAGE_MAX)
224d94b1 262 v |= DP_TRAIN_MAX_SWING_REACHED;
5801ead6 263
224d94b1
AD		 264 if (p >= DP_PRE_EMPHASIS_MAX)
265 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
5801ead6 266
d9fdaafb 267 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
53c1e09f
AD		 268 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
269 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 270
271 for (lane = 0; lane < 4; lane++)
272 train_set[lane] = v | p;
273}
274
224d94b1
AD		 275/* convert bits per color to bits per pixel */
276/* get bpc from the EDID */
277static int convert_bpc_to_bpp(int bpc)
746c1aa4 278{
224d94b1
AD		 279 if (bpc == 0)
280 return 24;
281 else
282 return bpc * 3;
283}
746c1aa4 284
224d94b1
AD		 285/* get the max pix clock supported by the link rate and lane num */
286static int dp_get_max_dp_pix_clock(int link_rate,
287 int lane_num,
288 int bpp)
289{
290 return (link_rate * lane_num * 8) / bpp;
291}
834b2904 292
224d94b1 293/***** radeon specific DP functions *****/
746c1aa4 294
3b6d9fd2
AD		 295static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
296 u8 dpcd[DP_DPCD_SIZE])
297{
298 int max_link_rate;
299
300 if (radeon_connector_is_dp12_capable(connector))
301 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
302 else
303 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
304
305 return max_link_rate;
306}
307
224d94b1
AD		 308/* First get the min lane# when low rate is used according to pixel clock
309 * (prefer low rate), second check max lane# supported by DP panel,
310 * if the max lane# < low rate lane# then use max lane# instead.
311 */
312static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
313 u8 dpcd[DP_DPCD_SIZE],
314 int pix_clock)
315{
eccea792 316 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
3b6d9fd2 317 int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
397fe157 318 int max_lane_num = drm_dp_max_lane_count(dpcd);
224d94b1
AD		 319 int lane_num;
320 int max_dp_pix_clock;
321
322 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
323 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
324 if (pix_clock <= max_dp_pix_clock)
325 break;
834b2904 326 }
746c1aa4 327
224d94b1 328 return lane_num;
746c1aa4
DA		 329}
330
224d94b1
AD		 331static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
332 u8 dpcd[DP_DPCD_SIZE],
333 int pix_clock)
746c1aa4 334{
eccea792 335 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
224d94b1
AD		 336 int lane_num, max_pix_clock;
337
fdca78c3
AD		 338 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
339 ENCODER_OBJECT_ID_NUTMEG)
224d94b1
AD		 340 return 270000;
341
342 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
343 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
344 if (pix_clock <= max_pix_clock)
345 return 162000;
346 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
347 if (pix_clock <= max_pix_clock)
348 return 270000;
349 if (radeon_connector_is_dp12_capable(connector)) {
350 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
351 if (pix_clock <= max_pix_clock)
352 return 540000;
834b2904 353 }
224d94b1 354
3b6d9fd2 355 return radeon_dp_get_max_link_rate(connector, dpcd);
746c1aa4
DA		 356}
357
834b2904
AD		 358static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
359 int action, int dp_clock,
224d94b1 360 u8 ucconfig, u8 lane_num)
5801ead6
AD		 361{
362 DP_ENCODER_SERVICE_PARAMETERS args;
363 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
364
365 memset(&args, 0, sizeof(args));
366 args.ucLinkClock = dp_clock / 10;
367 args.ucConfig = ucconfig;
368 args.ucAction = action;
369 args.ucLaneNum = lane_num;
370 args.ucStatus = 0;
371
372 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
373 return args.ucStatus;
374}
375
376u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
377{
5801ead6
AD		 378 struct drm_device *dev = radeon_connector->base.dev;
379 struct radeon_device *rdev = dev->dev_private;
380
381 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
379dfc25 382 radeon_connector->ddc_bus->rec.i2c_id, 0);
5801ead6
AD		 383}
384
40c5d876
AJ		 385static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
386{
387 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
388 u8 buf[3];
389
390 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
391 return;
392
aa019b79 393 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
40c5d876
AJ		 394 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
395 buf[0], buf[1], buf[2]);
396
aa019b79 397 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
40c5d876
AJ		 398 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
399 buf[0], buf[1], buf[2]);
400}
401
9fa05c98 402bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
746c1aa4 403{
5801ead6 404 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
1a644cd4 405 u8 msg[DP_DPCD_SIZE];
4e5f97de
SB		 406 int ret;
407
379dfc25 408 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
496263bf 409 DP_DPCD_SIZE);
834b2904 410 if (ret > 0) {
1a644cd4 411 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
4e5f97de 412
df8fbc23
AS		 413 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
414 dig_connector->dpcd);
40c5d876
AJ		 415
416 radeon_dp_probe_oui(radeon_connector);
417
9fa05c98 418 return true;
746c1aa4 419 }
5801ead6 420 dig_connector->dpcd[0] = 0;
9fa05c98 421 return false;
746c1aa4
DA		 422}
423
386d4d75
AD		 424int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
425 struct drm_connector *connector)
224d94b1
AD		 426{
427 struct drm_device *dev = encoder->dev;
428 struct radeon_device *rdev = dev->dev_private;
00dfb8df 429 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
496263bf 430 struct radeon_connector_atom_dig *dig_connector;
224d94b1 431 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
0ceb996c
AD		 432 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
433 u8 tmp;
224d94b1
AD		 434
435 if (!ASIC_IS_DCE4(rdev))
386d4d75 436 return panel_mode;
224d94b1 437
496263bf
AD		 438 if (!radeon_connector->con_priv)
439 return panel_mode;
440
441 dig_connector = radeon_connector->con_priv;
442
0ceb996c
AD		 443 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
444 /* DP bridge chips */
aa019b79
AD		 445 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
446 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
447 if (tmp & 1)
448 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
449 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
450 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
451 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
452 else
453 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
454 }
304a4840 455 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
0ceb996c 456 /* eDP */
aa019b79
AD		 457 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
458 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
459 if (tmp & 1)
460 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
461 }
00dfb8df 462 }
224d94b1 463
386d4d75 464 return panel_mode;
224d94b1
AD		 465}
466
5801ead6 467void radeon_dp_set_link_config(struct drm_connector *connector,
e811f5ae 468 const struct drm_display_mode *mode)
5801ead6 469{
224d94b1 470 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
5801ead6
AD		 471 struct radeon_connector_atom_dig *dig_connector;
472
5801ead6
AD		 473 if (!radeon_connector->con_priv)
474 return;
475 dig_connector = radeon_connector->con_priv;
476
224d94b1
AD		 477 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
478 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
479 dig_connector->dp_clock =
480 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
481 dig_connector->dp_lane_count =
482 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
483 }
5801ead6
AD		 484}
485
224d94b1 486int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 487 struct drm_display_mode *mode)
488{
224d94b1
AD		 489 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
490 struct radeon_connector_atom_dig *dig_connector;
491 int dp_clock;
5801ead6 492
224d94b1
AD		 493 if (!radeon_connector->con_priv)
494 return MODE_CLOCK_HIGH;
495 dig_connector = radeon_connector->con_priv;
496
497 dp_clock =
498 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
499
500 if ((dp_clock == 540000) &&
501 (!radeon_connector_is_dp12_capable(connector)))
502 return MODE_CLOCK_HIGH;
503
504 return MODE_OK;
5801ead6
AD		 505}
506
d5811e87
AD		 507bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
508{
509 u8 link_status[DP_LINK_STATUS_SIZE];
510 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
511
379dfc25
AD		 512 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
513 <= 0)
d5811e87 514 return false;
1ffdff13 515 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
d5811e87
AD		 516 return false;
517 return true;
518}
519
2953da15
AD		 520void radeon_dp_set_rx_power_state(struct drm_connector *connector,
521 u8 power_state)
522{
523 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
524 struct radeon_connector_atom_dig *dig_connector;
525
526 if (!radeon_connector->con_priv)
527 return;
528
529 dig_connector = radeon_connector->con_priv;
530
531 /* power up/down the sink */
532 if (dig_connector->dpcd[0] >= 0x11) {
379dfc25 533 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
2953da15
AD		 534 DP_SET_POWER, power_state);
535 usleep_range(1000, 2000);
536 }
537}
538
539
224d94b1
AD		 540struct radeon_dp_link_train_info {
541 struct radeon_device *rdev;
542 struct drm_encoder *encoder;
543 struct drm_connector *connector;
224d94b1
AD		 544 int enc_id;
545 int dp_clock;
546 int dp_lane_count;
224d94b1 547 bool tp3_supported;
1a644cd4 548 u8 dpcd[DP_RECEIVER_CAP_SIZE];
224d94b1
AD		 549 u8 train_set[4];
550 u8 link_status[DP_LINK_STATUS_SIZE];
551 u8 tries;
5a96a899 552 bool use_dpencoder;
496263bf 553 struct drm_dp_aux *aux;
224d94b1 554};
5801ead6 555
224d94b1 556static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
5801ead6 557{
224d94b1
AD		 558 /* set the initial vs/emph on the source */
559 atombios_dig_transmitter_setup(dp_info->encoder,
560 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
561 0, dp_info->train_set[0]); /* sets all lanes at once */
562
563 /* set the vs/emph on the sink */
496263bf
AD		 564 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
565 dp_info->train_set, dp_info->dp_lane_count);
5801ead6
AD		 566}
567
224d94b1 568static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
746c1aa4 569{
224d94b1 570 int rtp = 0;
746c1aa4 571
224d94b1 572 /* set training pattern on the source */
5a96a899 573 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
224d94b1
AD		 574 switch (tp) {
575 case DP_TRAINING_PATTERN_1:
576 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
577 break;
578 case DP_TRAINING_PATTERN_2:
579 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
580 break;
581 case DP_TRAINING_PATTERN_3:
582 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
583 break;
584 }
585 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
586 } else {
587 switch (tp) {
588 case DP_TRAINING_PATTERN_1:
589 rtp = 0;
590 break;
591 case DP_TRAINING_PATTERN_2:
592 rtp = 1;
593 break;
594 }
595 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
596 dp_info->dp_clock, dp_info->enc_id, rtp);
597 }
746c1aa4 598
224d94b1 599 /* enable training pattern on the sink */
496263bf 600 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
746c1aa4
DA		 601}
602
224d94b1 603static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
5801ead6 604{
386d4d75
AD		 605 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
606 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
224d94b1 607 u8 tmp;
5801ead6 608
224d94b1 609 /* power up the sink */
2953da15 610 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
224d94b1
AD		 611
612 /* possibly enable downspread on the sink */
613 if (dp_info->dpcd[3] & 0x1)
496263bf
AD		 614 drm_dp_dpcd_writeb(dp_info->aux,
615 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
224d94b1 616 else
496263bf
AD		 617 drm_dp_dpcd_writeb(dp_info->aux,
618 DP_DOWNSPREAD_CTRL, 0);
5801ead6 619
386d4d75
AD		 620 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
621 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
496263bf 622 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
386d4d75 623 }
5801ead6 624
224d94b1
AD		 625 /* set the lane count on the sink */
626 tmp = dp_info->dp_lane_count;
27f75dc6 627 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
224d94b1 628 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
496263bf 629 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
5801ead6 630
224d94b1 631 /* set the link rate on the sink */
3b5c662e 632 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
496263bf 633 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
5801ead6 634
224d94b1 635 /* start training on the source */
5a96a899 636 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
224d94b1
AD		 637 atombios_dig_encoder_setup(dp_info->encoder,
638 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
5801ead6 639 else
224d94b1
AD		 640 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
641 dp_info->dp_clock, dp_info->enc_id, 0);
5801ead6 642
5801ead6 643 /* disable the training pattern on the sink */
496263bf
AD		 644 drm_dp_dpcd_writeb(dp_info->aux,
645 DP_TRAINING_PATTERN_SET,
646 DP_TRAINING_PATTERN_DISABLE);
224d94b1
AD		 647
648 return 0;
649}
5801ead6 650
224d94b1
AD		 651static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
652{
5801ead6 653 udelay(400);
5801ead6 654
224d94b1 655 /* disable the training pattern on the sink */
496263bf
AD		 656 drm_dp_dpcd_writeb(dp_info->aux,
657 DP_TRAINING_PATTERN_SET,
658 DP_TRAINING_PATTERN_DISABLE);
224d94b1
AD		 659
660 /* disable the training pattern on the source */
5a96a899 661 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
224d94b1
AD		 662 atombios_dig_encoder_setup(dp_info->encoder,
663 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
664 else
665 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
666 dp_info->dp_clock, dp_info->enc_id, 0);
667
668 return 0;
669}
670
671static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
672{
673 bool clock_recovery;
674 u8 voltage;
675 int i;
676
677 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
678 memset(dp_info->train_set, 0, 4);
679 radeon_dp_update_vs_emph(dp_info);
680
681 udelay(400);
5fbfce7f 682
5801ead6
AD		 683 /* clock recovery loop */
684 clock_recovery = false;
224d94b1 685 dp_info->tries = 0;
5801ead6 686 voltage = 0xff;
224d94b1 687 while (1) {
1a644cd4 688 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
224d94b1 689
ab8f1a2a
AD		 690 if (drm_dp_dpcd_read_link_status(dp_info->aux,
691 dp_info->link_status) <= 0) {
8d1c702a 692 DRM_ERROR("displayport link status failed\n");
5801ead6 693 break;
8d1c702a 694 }
5801ead6 695
01916270 696 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
5801ead6
AD		 697 clock_recovery = true;
698 break;
699 }
700
224d94b1
AD		 701 for (i = 0; i < dp_info->dp_lane_count; i++) {
702 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
5801ead6
AD		 703 break;
704 }
224d94b1 705 if (i == dp_info->dp_lane_count) {
5801ead6
AD		 706 DRM_ERROR("clock recovery reached max voltage\n");
707 break;
708 }
709
224d94b1
AD		 710 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
711 ++dp_info->tries;
712 if (dp_info->tries == 5) {
5801ead6
AD		 713 DRM_ERROR("clock recovery tried 5 times\n");
714 break;
715 }
716 } else
224d94b1 717 dp_info->tries = 0;
5801ead6 718
224d94b1 719 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
5801ead6
AD		 720
721 /* Compute new train_set as requested by sink */
224d94b1
AD		 722 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
723
724 radeon_dp_update_vs_emph(dp_info);
5801ead6 725 }
224d94b1 726 if (!clock_recovery) {
5801ead6 727 DRM_ERROR("clock recovery failed\n");
224d94b1
AD		 728 return -1;
729 } else {
d9fdaafb 730 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
224d94b1
AD		 731 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
732 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
53c1e09f 733 DP_TRAIN_PRE_EMPHASIS_SHIFT);
224d94b1
AD		 734 return 0;
735 }
736}
5801ead6 737
224d94b1
AD		 738static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
739{
740 bool channel_eq;
5801ead6 741
224d94b1
AD		 742 if (dp_info->tp3_supported)
743 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
bcc1c2a1 744 else
224d94b1 745 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
5801ead6
AD		 746
747 /* channel equalization loop */
224d94b1 748 dp_info->tries = 0;
5801ead6 749 channel_eq = false;
224d94b1 750 while (1) {
1a644cd4 751 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
224d94b1 752
ab8f1a2a
AD		 753 if (drm_dp_dpcd_read_link_status(dp_info->aux,
754 dp_info->link_status) <= 0) {
8d1c702a 755 DRM_ERROR("displayport link status failed\n");
5801ead6 756 break;
8d1c702a 757 }
5801ead6 758
1ffdff13 759 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
5801ead6
AD		 760 channel_eq = true;
761 break;
762 }
763
764 /* Try 5 times */
224d94b1 765 if (dp_info->tries > 5) {
5801ead6
AD		 766 DRM_ERROR("channel eq failed: 5 tries\n");
767 break;
768 }
769
770 /* Compute new train_set as requested by sink */
224d94b1 771 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
5801ead6 772
224d94b1
AD		 773 radeon_dp_update_vs_emph(dp_info);
774 dp_info->tries++;
5801ead6
AD		 775 }
776
224d94b1 777 if (!channel_eq) {
5801ead6 778 DRM_ERROR("channel eq failed\n");
224d94b1
AD		 779 return -1;
780 } else {
d9fdaafb 781 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
224d94b1
AD		 782 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
783 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
53c1e09f 784 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
224d94b1
AD		 785 return 0;
786 }
5801ead6
AD		 787}
788
224d94b1
AD		 789void radeon_dp_link_train(struct drm_encoder *encoder,
790 struct drm_connector *connector)
746c1aa4 791{
224d94b1
AD		 792 struct drm_device *dev = encoder->dev;
793 struct radeon_device *rdev = dev->dev_private;
794 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
795 struct radeon_encoder_atom_dig *dig;
796 struct radeon_connector *radeon_connector;
797 struct radeon_connector_atom_dig *dig_connector;
798 struct radeon_dp_link_train_info dp_info;
5a96a899
JG		 799 int index;
800 u8 tmp, frev, crev;
746c1aa4 801
224d94b1
AD		 802 if (!radeon_encoder->enc_priv)
803 return;
804 dig = radeon_encoder->enc_priv;
746c1aa4 805
224d94b1
AD		 806 radeon_connector = to_radeon_connector(connector);
807 if (!radeon_connector->con_priv)
808 return;
809 dig_connector = radeon_connector->con_priv;
834b2904 810
224d94b1
AD		 811 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
812 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
813 return;
746c1aa4 814
5a96a899
JG		 815 /* DPEncoderService newer than 1.1 can't program properly the
816 * training pattern. When facing such version use the
817 * DIGXEncoderControl (X== 1 | 2)
818 */
819 dp_info.use_dpencoder = true;
820 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
821 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
822 if (crev > 1) {
823 dp_info.use_dpencoder = false;
824 }
825 }
826
224d94b1
AD		 827 dp_info.enc_id = 0;
828 if (dig->dig_encoder)
829 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
830 else
831 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
832 if (dig->linkb)
833 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
834 else
835 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
834b2904 836
aa019b79
AD		 837 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
838 == 1) {
839 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
840 dp_info.tp3_supported = true;
841 else
842 dp_info.tp3_supported = false;
843 } else {
224d94b1 844 dp_info.tp3_supported = false;
aa019b79 845 }
224d94b1 846
1a644cd4 847 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
224d94b1
AD		 848 dp_info.rdev = rdev;
849 dp_info.encoder = encoder;
850 dp_info.connector = connector;
224d94b1
AD		 851 dp_info.dp_lane_count = dig_connector->dp_lane_count;
852 dp_info.dp_clock = dig_connector->dp_clock;
379dfc25 853 dp_info.aux = &radeon_connector->ddc_bus->aux;
224d94b1
AD		 854
855 if (radeon_dp_link_train_init(&dp_info))
856 goto done;
857 if (radeon_dp_link_train_cr(&dp_info))
858 goto done;
859 if (radeon_dp_link_train_ce(&dp_info))
860 goto done;
861done:
862 if (radeon_dp_link_train_finish(&dp_info))
863 return;
746c1aa4 864}
Linux 6.x block layer and io_uring tree(s)