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drm/radeon/kms/atom: force bpc to 8 for now
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_dp.c
CommitLineData
746c1aa4
DA		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "drm_dp_helper.h"
33
f92a8b67 34/* move these to drm_dp_helper.c/h */
5801ead6
AD		 35#define DP_LINK_CONFIGURATION_SIZE 9
36#define DP_LINK_STATUS_SIZE 6
37#define DP_DPCD_SIZE 8
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
f92a8b67 45
224d94b1
AD		 46/***** radeon AUX functions *****/
47union aux_channel_transaction {
48 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
f92a8b67
AD		 50};
51
224d94b1
AD		 52static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
53 u8 *send, int send_bytes,
54 u8 *recv, int recv_size,
55 u8 delay, u8 *ack)
56{
57 struct drm_device *dev = chan->dev;
58 struct radeon_device *rdev = dev->dev_private;
59 union aux_channel_transaction args;
60 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
61 unsigned char *base;
62 int recv_bytes;
63
64 memset(&args, 0, sizeof(args));
f92a8b67 65
97412a7a 66 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
224d94b1
AD		 67
68 memcpy(base, send, send_bytes);
69
97412a7a
AD		 70 args.v1.lpAuxRequest = 0 + 4;
71 args.v1.lpDataOut = 16 + 4;
224d94b1
AD		 72 args.v1.ucDataOutLen = 0;
73 args.v1.ucChannelID = chan->rec.i2c_id;
74 args.v1.ucDelay = delay / 10;
75 if (ASIC_IS_DCE4(rdev))
76 args.v2.ucHPD_ID = chan->rec.hpd;
77
78 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79
80 *ack = args.v1.ucReplyStatus;
81
82 /* timeout */
83 if (args.v1.ucReplyStatus == 1) {
84 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
85 return -ETIMEDOUT;
86 }
87
88 /* flags not zero */
89 if (args.v1.ucReplyStatus == 2) {
90 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
91 return -EBUSY;
92 }
93
94 /* error */
95 if (args.v1.ucReplyStatus == 3) {
96 DRM_DEBUG_KMS("dp_aux_ch error\n");
97 return -EIO;
98 }
99
100 recv_bytes = args.v1.ucDataOutLen;
101 if (recv_bytes > recv_size)
102 recv_bytes = recv_size;
103
104 if (recv && recv_size)
105 memcpy(recv, base + 16, recv_bytes);
106
107 return recv_bytes;
108}
109
110static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
111 u16 address, u8 *send, u8 send_bytes, u8 delay)
f92a8b67 112{
224d94b1
AD		 113 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
114 int ret;
115 u8 msg[20];
116 int msg_bytes = send_bytes + 4;
117 u8 ack;
6375bda0 118 unsigned retry;
5801ead6 119
224d94b1
AD		 120 if (send_bytes > 16)
121 return -1;
5801ead6 122
224d94b1
AD		 123 msg[0] = address;
124 msg[1] = address >> 8;
125 msg[2] = AUX_NATIVE_WRITE << 4;
126 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
127 memcpy(&msg[4], send, send_bytes);
f92a8b67 128
6375bda0 129 for (retry = 0; retry < 4; retry++) {
224d94b1
AD		 130 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
131 msg, msg_bytes, NULL, 0, delay, &ack);
4f332844
AD		 132 if (ret == -EBUSY)
133 continue;
134 else if (ret < 0)
224d94b1
AD		 135 return ret;
136 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
6375bda0 137 return send_bytes;
224d94b1
AD		 138 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
139 udelay(400);
140 else
141 return -EIO;
f92a8b67
AD		 142 }
143
6375bda0 144 return -EIO;
f92a8b67
AD		 145}
146
224d94b1
AD		 147static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
148 u16 address, u8 *recv, int recv_bytes, u8 delay)
f92a8b67 149{
224d94b1
AD		 150 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
151 u8 msg[4];
152 int msg_bytes = 4;
153 u8 ack;
154 int ret;
6375bda0 155 unsigned retry;
5801ead6 156
224d94b1
AD		 157 msg[0] = address;
158 msg[1] = address >> 8;
159 msg[2] = AUX_NATIVE_READ << 4;
160 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
5801ead6 161
6375bda0 162 for (retry = 0; retry < 4; retry++) {
224d94b1
AD		 163 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
164 msg, msg_bytes, recv, recv_bytes, delay, &ack);
4f332844
AD		 165 if (ret == -EBUSY)
166 continue;
167 else if (ret < 0)
224d94b1
AD		 168 return ret;
169 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
170 return ret;
171 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
172 udelay(400);
109bc10d
AD		 173 else if (ret == 0)
174 return -EPROTO;
224d94b1
AD		 175 else
176 return -EIO;
177 }
6375bda0
AD		 178
179 return -EIO;
224d94b1 180}
f92a8b67 181
224d94b1
AD		 182static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
183 u16 reg, u8 val)
184{
185 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
186}
187
188static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
189 u16 reg)
190{
191 u8 val = 0;
192
193 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
194
195 return val;
196}
197
198int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
199 u8 write_byte, u8 *read_byte)
200{
201 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
202 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
203 u16 address = algo_data->address;
204 u8 msg[5];
205 u8 reply[2];
206 unsigned retry;
207 int msg_bytes;
208 int reply_bytes = 1;
209 int ret;
210 u8 ack;
211
212 /* Set up the command byte */
213 if (mode & MODE_I2C_READ)
214 msg[2] = AUX_I2C_READ << 4;
215 else
216 msg[2] = AUX_I2C_WRITE << 4;
217
218 if (!(mode & MODE_I2C_STOP))
219 msg[2] |= AUX_I2C_MOT << 4;
220
221 msg[0] = address;
222 msg[1] = address >> 8;
223
224 switch (mode) {
225 case MODE_I2C_WRITE:
226 msg_bytes = 5;
227 msg[3] = msg_bytes << 4;
228 msg[4] = write_byte;
229 break;
230 case MODE_I2C_READ:
231 msg_bytes = 4;
232 msg[3] = msg_bytes << 4;
233 break;
f92a8b67 234 default:
224d94b1
AD		 235 msg_bytes = 4;
236 msg[3] = 3 << 4;
f92a8b67 237 break;
f92a8b67
AD		 238 }
239
224d94b1
AD		 240 for (retry = 0; retry < 4; retry++) {
241 ret = radeon_process_aux_ch(auxch,
242 msg, msg_bytes, reply, reply_bytes, 0, &ack);
4f332844
AD		 243 if (ret == -EBUSY)
244 continue;
245 else if (ret < 0) {
224d94b1
AD		 246 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
247 return ret;
248 }
f92a8b67 249
224d94b1
AD		 250 switch (ack & AUX_NATIVE_REPLY_MASK) {
251 case AUX_NATIVE_REPLY_ACK:
252 /* I2C-over-AUX Reply field is only valid
253 * when paired with AUX ACK.
254 */
255 break;
256 case AUX_NATIVE_REPLY_NACK:
257 DRM_DEBUG_KMS("aux_ch native nack\n");
258 return -EREMOTEIO;
259 case AUX_NATIVE_REPLY_DEFER:
260 DRM_DEBUG_KMS("aux_ch native defer\n");
261 udelay(400);
262 continue;
263 default:
264 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
265 return -EREMOTEIO;
266 }
5801ead6 267
224d94b1
AD		 268 switch (ack & AUX_I2C_REPLY_MASK) {
269 case AUX_I2C_REPLY_ACK:
270 if (mode == MODE_I2C_READ)
271 *read_byte = reply[0];
272 return ret;
273 case AUX_I2C_REPLY_NACK:
274 DRM_DEBUG_KMS("aux_i2c nack\n");
275 return -EREMOTEIO;
276 case AUX_I2C_REPLY_DEFER:
277 DRM_DEBUG_KMS("aux_i2c defer\n");
278 udelay(400);
279 break;
280 default:
281 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
282 return -EREMOTEIO;
283 }
284 }
5801ead6 285
091264f0 286 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
224d94b1 287 return -EREMOTEIO;
5801ead6
AD		 288}
289
224d94b1
AD		 290/***** general DP utility functions *****/
291
5801ead6
AD		 292static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
293{
294 return link_status[r - DP_LANE0_1_STATUS];
295}
296
297static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
298 int lane)
299{
300 int i = DP_LANE0_1_STATUS + (lane >> 1);
301 int s = (lane & 1) * 4;
302 u8 l = dp_link_status(link_status, i);
303 return (l >> s) & 0xf;
304}
305
306static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
307 int lane_count)
308{
309 int lane;
310 u8 lane_status;
311
312 for (lane = 0; lane < lane_count; lane++) {
313 lane_status = dp_get_lane_status(link_status, lane);
314 if ((lane_status & DP_LANE_CR_DONE) == 0)
315 return false;
316 }
317 return true;
318}
319
320static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
321 int lane_count)
322{
323 u8 lane_align;
324 u8 lane_status;
325 int lane;
326
327 lane_align = dp_link_status(link_status,
328 DP_LANE_ALIGN_STATUS_UPDATED);
329 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
330 return false;
331 for (lane = 0; lane < lane_count; lane++) {
332 lane_status = dp_get_lane_status(link_status, lane);
333 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
334 return false;
335 }
336 return true;
337}
338
224d94b1 339static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
5801ead6
AD		 340 int lane)
341
342{
343 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
344 int s = ((lane & 1) ?
345 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
346 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
347 u8 l = dp_link_status(link_status, i);
348
349 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
350}
351
224d94b1 352static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
5801ead6
AD		 353 int lane)
354{
355 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
356 int s = ((lane & 1) ?
357 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
358 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
359 u8 l = dp_link_status(link_status, i);
360
361 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
362}
363
5801ead6 364#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
224d94b1 365#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
5801ead6
AD		 366
367static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
368 int lane_count,
369 u8 train_set[4])
370{
371 u8 v = 0;
372 u8 p = 0;
373 int lane;
374
375 for (lane = 0; lane < lane_count; lane++) {
376 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
377 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
378
d9fdaafb 379 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
53c1e09f
AD		 380 lane,
381 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
382 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 383
384 if (this_v > v)
385 v = this_v;
386 if (this_p > p)
387 p = this_p;
388 }
389
390 if (v >= DP_VOLTAGE_MAX)
224d94b1 391 v |= DP_TRAIN_MAX_SWING_REACHED;
5801ead6 392
224d94b1
AD		 393 if (p >= DP_PRE_EMPHASIS_MAX)
394 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
5801ead6 395
d9fdaafb 396 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
53c1e09f
AD		 397 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
398 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
5801ead6
AD		 399
400 for (lane = 0; lane < 4; lane++)
401 train_set[lane] = v | p;
402}
403
224d94b1
AD		 404/* convert bits per color to bits per pixel */
405/* get bpc from the EDID */
406static int convert_bpc_to_bpp(int bpc)
746c1aa4 407{
017d213f 408#if 0
224d94b1
AD		 409 if (bpc == 0)
410 return 24;
411 else
412 return bpc * 3;
017d213f
AD		 413#endif
414 return 24;
224d94b1 415}
746c1aa4 416
224d94b1
AD		 417/* get the max pix clock supported by the link rate and lane num */
418static int dp_get_max_dp_pix_clock(int link_rate,
419 int lane_num,
420 int bpp)
421{
422 return (link_rate * lane_num * 8) / bpp;
423}
834b2904 424
224d94b1
AD		 425static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
426{
427 switch (dpcd[DP_MAX_LINK_RATE]) {
428 case DP_LINK_BW_1_62:
429 default:
430 return 162000;
431 case DP_LINK_BW_2_7:
432 return 270000;
433 case DP_LINK_BW_5_4:
434 return 540000;
834b2904 435 }
746c1aa4
DA		 436}
437
224d94b1 438static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
746c1aa4 439{
224d94b1
AD		 440 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
441}
834b2904 442
224d94b1
AD		 443static u8 dp_get_dp_link_rate_coded(int link_rate)
444{
445 switch (link_rate) {
446 case 162000:
447 default:
448 return DP_LINK_BW_1_62;
449 case 270000:
450 return DP_LINK_BW_2_7;
451 case 540000:
452 return DP_LINK_BW_5_4;
453 }
454}
746c1aa4 455
224d94b1 456/***** radeon specific DP functions *****/
746c1aa4 457
224d94b1
AD		 458/* First get the min lane# when low rate is used according to pixel clock
459 * (prefer low rate), second check max lane# supported by DP panel,
460 * if the max lane# < low rate lane# then use max lane# instead.
461 */
462static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
463 u8 dpcd[DP_DPCD_SIZE],
464 int pix_clock)
465{
466 int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
467 int max_link_rate = dp_get_max_link_rate(dpcd);
468 int max_lane_num = dp_get_max_lane_number(dpcd);
469 int lane_num;
470 int max_dp_pix_clock;
471
472 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
473 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
474 if (pix_clock <= max_dp_pix_clock)
475 break;
834b2904 476 }
746c1aa4 477
224d94b1 478 return lane_num;
746c1aa4
DA		 479}
480
224d94b1
AD		 481static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
482 u8 dpcd[DP_DPCD_SIZE],
483 int pix_clock)
746c1aa4 484{
224d94b1
AD		 485 int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
486 int lane_num, max_pix_clock;
487
fdca78c3
AD		 488 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
489 ENCODER_OBJECT_ID_NUTMEG)
224d94b1
AD		 490 return 270000;
491
492 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
493 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
494 if (pix_clock <= max_pix_clock)
495 return 162000;
496 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
497 if (pix_clock <= max_pix_clock)
498 return 270000;
499 if (radeon_connector_is_dp12_capable(connector)) {
500 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
501 if (pix_clock <= max_pix_clock)
502 return 540000;
834b2904 503 }
224d94b1
AD		 504
505 return dp_get_max_link_rate(dpcd);
746c1aa4
DA		 506}
507
834b2904
AD		 508static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
509 int action, int dp_clock,
224d94b1 510 u8 ucconfig, u8 lane_num)
5801ead6
AD		 511{
512 DP_ENCODER_SERVICE_PARAMETERS args;
513 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
514
515 memset(&args, 0, sizeof(args));
516 args.ucLinkClock = dp_clock / 10;
517 args.ucConfig = ucconfig;
518 args.ucAction = action;
519 args.ucLaneNum = lane_num;
520 args.ucStatus = 0;
521
522 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
523 return args.ucStatus;
524}
525
526u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
527{
528 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
529 struct drm_device *dev = radeon_connector->base.dev;
530 struct radeon_device *rdev = dev->dev_private;
531
532 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
533 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
534}
535
9fa05c98 536bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
746c1aa4 537{
5801ead6 538 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
746c1aa4 539 u8 msg[25];
224d94b1 540 int ret, i;
746c1aa4 541
834b2904
AD		 542 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
543 if (ret > 0) {
5801ead6 544 memcpy(dig_connector->dpcd, msg, 8);
224d94b1
AD		 545 DRM_DEBUG_KMS("DPCD: ");
546 for (i = 0; i < 8; i++)
547 DRM_DEBUG_KMS("%02x ", msg[i]);
548 DRM_DEBUG_KMS("\n");
9fa05c98 549 return true;
746c1aa4 550 }
5801ead6 551 dig_connector->dpcd[0] = 0;
9fa05c98 552 return false;
746c1aa4
DA		 553}
554
386d4d75
AD		 555int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
556 struct drm_connector *connector)
224d94b1
AD		 557{
558 struct drm_device *dev = encoder->dev;
559 struct radeon_device *rdev = dev->dev_private;
00dfb8df 560 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
224d94b1
AD		 561 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
562
563 if (!ASIC_IS_DCE4(rdev))
386d4d75 564 return panel_mode;
224d94b1 565
cf2aff6e
AD		 566 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
567 ENCODER_OBJECT_ID_NUTMEG)
224d94b1 568 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
cf2aff6e 569 else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
304a4840
AD		 570 ENCODER_OBJECT_ID_TRAVIS) {
571 u8 id[6];
572 int i;
573 for (i = 0; i < 6; i++)
574 id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
575 if (id[0] == 0x73 &&
576 id[1] == 0x69 &&
577 id[2] == 0x76 &&
578 id[3] == 0x61 &&
579 id[4] == 0x72 &&
580 id[5] == 0x54)
581 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
582 else
583 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
584 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
00dfb8df
AD		 585 u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
586 if (tmp & 1)
587 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
588 }
224d94b1 589
386d4d75 590 return panel_mode;
224d94b1
AD		 591}
592
5801ead6
AD		 593void radeon_dp_set_link_config(struct drm_connector *connector,
594 struct drm_display_mode *mode)
595{
224d94b1 596 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
5801ead6
AD		 597 struct radeon_connector_atom_dig *dig_connector;
598
5801ead6
AD		 599 if (!radeon_connector->con_priv)
600 return;
601 dig_connector = radeon_connector->con_priv;
602
224d94b1
AD		 603 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
604 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
605 dig_connector->dp_clock =
606 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
607 dig_connector->dp_lane_count =
608 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
609 }
5801ead6
AD		 610}
611
224d94b1 612int radeon_dp_mode_valid_helper(struct drm_connector *connector,
5801ead6
AD		 613 struct drm_display_mode *mode)
614{
224d94b1
AD		 615 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
616 struct radeon_connector_atom_dig *dig_connector;
617 int dp_clock;
5801ead6 618
224d94b1
AD		 619 if (!radeon_connector->con_priv)
620 return MODE_CLOCK_HIGH;
621 dig_connector = radeon_connector->con_priv;
622
623 dp_clock =
624 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
625
626 if ((dp_clock == 540000) &&
627 (!radeon_connector_is_dp12_capable(connector)))
628 return MODE_CLOCK_HIGH;
629
630 return MODE_OK;
5801ead6
AD		 631}
632
224d94b1
AD		 633static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
634 u8 link_status[DP_LINK_STATUS_SIZE])
746c1aa4
DA		 635{
636 int ret;
834b2904
AD		 637 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
638 link_status, DP_LINK_STATUS_SIZE, 100);
639 if (ret <= 0) {
746c1aa4
DA		 640 DRM_ERROR("displayport link status failed\n");
641 return false;
642 }
643
d9fdaafb 644 DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n",
53c1e09f
AD		 645 link_status[0], link_status[1], link_status[2],
646 link_status[3], link_status[4], link_status[5]);
746c1aa4
DA		 647 return true;
648}
649
d5811e87
AD		 650bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
651{
652 u8 link_status[DP_LINK_STATUS_SIZE];
653 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
654
655 if (!radeon_dp_get_link_status(radeon_connector, link_status))
656 return false;
657 if (dp_channel_eq_ok(link_status, dig->dp_lane_count))
658 return false;
659 return true;
660}
661
224d94b1
AD		 662struct radeon_dp_link_train_info {
663 struct radeon_device *rdev;
664 struct drm_encoder *encoder;
665 struct drm_connector *connector;
666 struct radeon_connector *radeon_connector;
667 int enc_id;
668 int dp_clock;
669 int dp_lane_count;
670 int rd_interval;
671 bool tp3_supported;
672 u8 dpcd[8];
673 u8 train_set[4];
674 u8 link_status[DP_LINK_STATUS_SIZE];
675 u8 tries;
5a96a899 676 bool use_dpencoder;
224d94b1 677};
5801ead6 678
224d94b1 679static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
5801ead6 680{
224d94b1
AD		 681 /* set the initial vs/emph on the source */
682 atombios_dig_transmitter_setup(dp_info->encoder,
683 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
684 0, dp_info->train_set[0]); /* sets all lanes at once */
685
686 /* set the vs/emph on the sink */
687 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
688 dp_info->train_set, dp_info->dp_lane_count, 0);
5801ead6
AD		 689}
690
224d94b1 691static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
746c1aa4 692{
224d94b1 693 int rtp = 0;
746c1aa4 694
224d94b1 695 /* set training pattern on the source */
5a96a899 696 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
224d94b1
AD		 697 switch (tp) {
698 case DP_TRAINING_PATTERN_1:
699 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
700 break;
701 case DP_TRAINING_PATTERN_2:
702 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
703 break;
704 case DP_TRAINING_PATTERN_3:
705 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
706 break;
707 }
708 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
709 } else {
710 switch (tp) {
711 case DP_TRAINING_PATTERN_1:
712 rtp = 0;
713 break;
714 case DP_TRAINING_PATTERN_2:
715 rtp = 1;
716 break;
717 }
718 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
719 dp_info->dp_clock, dp_info->enc_id, rtp);
720 }
746c1aa4 721
224d94b1
AD		 722 /* enable training pattern on the sink */
723 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
746c1aa4
DA		 724}
725
224d94b1 726static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
5801ead6 727{
386d4d75
AD		 728 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
729 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
224d94b1 730 u8 tmp;
5801ead6 731
224d94b1
AD		 732 /* power up the sink */
733 if (dp_info->dpcd[0] >= 0x11)
734 radeon_write_dpcd_reg(dp_info->radeon_connector,
735 DP_SET_POWER, DP_SET_POWER_D0);
736
737 /* possibly enable downspread on the sink */
738 if (dp_info->dpcd[3] & 0x1)
739 radeon_write_dpcd_reg(dp_info->radeon_connector,
740 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
741 else
742 radeon_write_dpcd_reg(dp_info->radeon_connector,
743 DP_DOWNSPREAD_CTRL, 0);
5801ead6 744
386d4d75
AD		 745 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
746 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
747 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
748 }
5801ead6 749
224d94b1
AD		 750 /* set the lane count on the sink */
751 tmp = dp_info->dp_lane_count;
abc8113f
DA		 752 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
753 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
224d94b1
AD		 754 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
755 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
5801ead6 756
224d94b1
AD		 757 /* set the link rate on the sink */
758 tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
759 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
5801ead6 760
224d94b1 761 /* start training on the source */
5a96a899 762 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
224d94b1
AD		 763 atombios_dig_encoder_setup(dp_info->encoder,
764 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
5801ead6 765 else
224d94b1
AD		 766 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
767 dp_info->dp_clock, dp_info->enc_id, 0);
5801ead6 768
5801ead6 769 /* disable the training pattern on the sink */
224d94b1
AD		 770 radeon_write_dpcd_reg(dp_info->radeon_connector,
771 DP_TRAINING_PATTERN_SET,
772 DP_TRAINING_PATTERN_DISABLE);
773
774 return 0;
775}
5801ead6 776
224d94b1
AD		 777static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
778{
5801ead6 779 udelay(400);
5801ead6 780
224d94b1
AD		 781 /* disable the training pattern on the sink */
782 radeon_write_dpcd_reg(dp_info->radeon_connector,
783 DP_TRAINING_PATTERN_SET,
784 DP_TRAINING_PATTERN_DISABLE);
785
786 /* disable the training pattern on the source */
5a96a899 787 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
224d94b1
AD		 788 atombios_dig_encoder_setup(dp_info->encoder,
789 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
790 else
791 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
792 dp_info->dp_clock, dp_info->enc_id, 0);
793
794 return 0;
795}
796
797static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
798{
799 bool clock_recovery;
800 u8 voltage;
801 int i;
802
803 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
804 memset(dp_info->train_set, 0, 4);
805 radeon_dp_update_vs_emph(dp_info);
806
807 udelay(400);
5fbfce7f 808
5801ead6
AD		 809 /* clock recovery loop */
810 clock_recovery = false;
224d94b1 811 dp_info->tries = 0;
5801ead6 812 voltage = 0xff;
224d94b1
AD		 813 while (1) {
814 if (dp_info->rd_interval == 0)
815 udelay(100);
816 else
817 mdelay(dp_info->rd_interval * 4);
818
819 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
5801ead6
AD		 820 break;
821
224d94b1 822 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
5801ead6
AD		 823 clock_recovery = true;
824 break;
825 }
826
224d94b1
AD		 827 for (i = 0; i < dp_info->dp_lane_count; i++) {
828 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
5801ead6
AD		 829 break;
830 }
224d94b1 831 if (i == dp_info->dp_lane_count) {
5801ead6
AD		 832 DRM_ERROR("clock recovery reached max voltage\n");
833 break;
834 }
835
224d94b1
AD		 836 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
837 ++dp_info->tries;
838 if (dp_info->tries == 5) {
5801ead6
AD		 839 DRM_ERROR("clock recovery tried 5 times\n");
840 break;
841 }
842 } else
224d94b1 843 dp_info->tries = 0;
5801ead6 844
224d94b1 845 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
5801ead6
AD		 846
847 /* Compute new train_set as requested by sink */
224d94b1
AD		 848 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
849
850 radeon_dp_update_vs_emph(dp_info);
5801ead6 851 }
224d94b1 852 if (!clock_recovery) {
5801ead6 853 DRM_ERROR("clock recovery failed\n");
224d94b1
AD		 854 return -1;
855 } else {
d9fdaafb 856 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
224d94b1
AD		 857 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
858 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
53c1e09f 859 DP_TRAIN_PRE_EMPHASIS_SHIFT);
224d94b1
AD		 860 return 0;
861 }
862}
5801ead6 863
224d94b1
AD		 864static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
865{
866 bool channel_eq;
5801ead6 867
224d94b1
AD		 868 if (dp_info->tp3_supported)
869 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
bcc1c2a1 870 else
224d94b1 871 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
5801ead6
AD		 872
873 /* channel equalization loop */
224d94b1 874 dp_info->tries = 0;
5801ead6 875 channel_eq = false;
224d94b1
AD		 876 while (1) {
877 if (dp_info->rd_interval == 0)
878 udelay(400);
879 else
880 mdelay(dp_info->rd_interval * 4);
881
882 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
5801ead6
AD		 883 break;
884
224d94b1 885 if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
5801ead6
AD		 886 channel_eq = true;
887 break;
888 }
889
890 /* Try 5 times */
224d94b1 891 if (dp_info->tries > 5) {
5801ead6
AD		 892 DRM_ERROR("channel eq failed: 5 tries\n");
893 break;
894 }
895
896 /* Compute new train_set as requested by sink */
224d94b1 897 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
5801ead6 898
224d94b1
AD		 899 radeon_dp_update_vs_emph(dp_info);
900 dp_info->tries++;
5801ead6
AD		 901 }
902
224d94b1 903 if (!channel_eq) {
5801ead6 904 DRM_ERROR("channel eq failed\n");
224d94b1
AD		 905 return -1;
906 } else {
d9fdaafb 907 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
224d94b1
AD		 908 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
909 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
53c1e09f 910 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
224d94b1
AD		 911 return 0;
912 }
5801ead6
AD		 913}
914
224d94b1
AD		 915void radeon_dp_link_train(struct drm_encoder *encoder,
916 struct drm_connector *connector)
746c1aa4 917{
224d94b1
AD		 918 struct drm_device *dev = encoder->dev;
919 struct radeon_device *rdev = dev->dev_private;
920 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
921 struct radeon_encoder_atom_dig *dig;
922 struct radeon_connector *radeon_connector;
923 struct radeon_connector_atom_dig *dig_connector;
924 struct radeon_dp_link_train_info dp_info;
5a96a899
JG		 925 int index;
926 u8 tmp, frev, crev;
746c1aa4 927
224d94b1
AD		 928 if (!radeon_encoder->enc_priv)
929 return;
930 dig = radeon_encoder->enc_priv;
746c1aa4 931
224d94b1
AD		 932 radeon_connector = to_radeon_connector(connector);
933 if (!radeon_connector->con_priv)
934 return;
935 dig_connector = radeon_connector->con_priv;
834b2904 936
224d94b1
AD		 937 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
938 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
939 return;
746c1aa4 940
5a96a899
JG		 941 /* DPEncoderService newer than 1.1 can't program properly the
942 * training pattern. When facing such version use the
943 * DIGXEncoderControl (X== 1 | 2)
944 */
945 dp_info.use_dpencoder = true;
946 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
947 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
948 if (crev > 1) {
949 dp_info.use_dpencoder = false;
950 }
951 }
952
224d94b1
AD		 953 dp_info.enc_id = 0;
954 if (dig->dig_encoder)
955 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
956 else
957 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
958 if (dig->linkb)
959 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
960 else
961 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
834b2904 962
224d94b1
AD		 963 dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
964 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
965 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
966 dp_info.tp3_supported = true;
967 else
968 dp_info.tp3_supported = false;
969
970 memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
971 dp_info.rdev = rdev;
972 dp_info.encoder = encoder;
973 dp_info.connector = connector;
974 dp_info.radeon_connector = radeon_connector;
975 dp_info.dp_lane_count = dig_connector->dp_lane_count;
976 dp_info.dp_clock = dig_connector->dp_clock;
977
978 if (radeon_dp_link_train_init(&dp_info))
979 goto done;
980 if (radeon_dp_link_train_cr(&dp_info))
981 goto done;
982 if (radeon_dp_link_train_ce(&dp_info))
983 goto done;
984done:
985 if (radeon_dp_link_train_finish(&dp_info))
986 return;
746c1aa4 987}
Linux 6.x block layer and io_uring tree(s)