[linux-block.git] / drivers / gpu / drm / r128 / ati_pcigart.c

/*
 * \file ati_pcigart.c
 * ATI PCI GART support
 *
 * \author Gareth Hughes <gareth@valinux.com>
 */

/*
 * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
 *
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <linux/export.h>
#include <linux/pci.h>

#include <drm/drm_device.h>
#include <drm/drm_legacy.h>
#include <drm/drm_print.h>

#include "ati_pcigart.h"

# define ATI_PCIGART_PAGE_SIZE		4096	/**< PCI GART page size */

static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
				       struct drm_ati_pcigart_info *gart_info)
{
	drm_dma_handle_t *dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);

	if (!dmah)
		return -ENOMEM;

	dmah->size = gart_info->table_size;
	dmah->vaddr = dma_alloc_coherent(dev->dev,
					 dmah->size,
					 &dmah->busaddr,
					 GFP_KERNEL);

	if (!dmah->vaddr) {
		kfree(dmah);
		return -ENOMEM;
	}

	gart_info->table_handle = dmah;
	return 0;
}

static void drm_ati_free_pcigart_table(struct drm_device *dev,
				       struct drm_ati_pcigart_info *gart_info)
{
	drm_dma_handle_t *dmah = gart_info->table_handle;

	dma_free_coherent(dev->dev, dmah->size, dmah->vaddr, dmah->busaddr);
	kfree(dmah);

	gart_info->table_handle = NULL;
}

int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
{
	struct drm_sg_mem *entry = dev->sg;
	struct pci_dev *pdev = to_pci_dev(dev->dev);
	unsigned long pages;
	int i;
	int max_pages;

	/* we need to support large memory configurations */
	if (!entry) {
		DRM_ERROR("no scatter/gather memory!\n");
		return 0;
	}

	if (gart_info->bus_addr) {

		max_pages = (gart_info->table_size / sizeof(u32));
		pages = (entry->pages <= max_pages)
		  ? entry->pages : max_pages;

		for (i = 0; i < pages; i++) {
			if (!entry->busaddr[i])
				break;
			dma_unmap_page(&pdev->dev, entry->busaddr[i],
				       PAGE_SIZE, DMA_BIDIRECTIONAL);
		}

		if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
			gart_info->bus_addr = 0;
	}

	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
	    gart_info->table_handle) {
		drm_ati_free_pcigart_table(dev, gart_info);
	}

	return 1;
}

int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
{
	struct drm_local_map *map = &gart_info->mapping;
	struct drm_sg_mem *entry = dev->sg;
	struct pci_dev *pdev = to_pci_dev(dev->dev);
	void *address = NULL;
	unsigned long pages;
	u32 *pci_gart = NULL, page_base, gart_idx;
	dma_addr_t bus_address = 0;
	int i, j, ret = -ENOMEM;
	int max_ati_pages, max_real_pages;

	if (!entry) {
		DRM_ERROR("no scatter/gather memory!\n");
		goto done;
	}

	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
		DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");

		if (dma_set_mask(&pdev->dev, gart_info->table_mask)) {
			DRM_ERROR("fail to set dma mask to 0x%Lx\n",
				  (unsigned long long)gart_info->table_mask);
			ret = -EFAULT;
			goto done;
		}

		ret = drm_ati_alloc_pcigart_table(dev, gart_info);
		if (ret) {
			DRM_ERROR("cannot allocate PCI GART page!\n");
			goto done;
		}

		pci_gart = gart_info->table_handle->vaddr;
		address = gart_info->table_handle->vaddr;
		bus_address = gart_info->table_handle->busaddr;
	} else {
		address = gart_info->addr;
		bus_address = gart_info->bus_addr;
		DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
			  (unsigned long long)bus_address,
			  (unsigned long)address);
	}


	max_ati_pages = (gart_info->table_size / sizeof(u32));
	max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
	pages = (entry->pages <= max_real_pages)
	    ? entry->pages : max_real_pages;

	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
		memset(pci_gart, 0, max_ati_pages * sizeof(u32));
	} else {
		memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32));
	}

	gart_idx = 0;
	for (i = 0; i < pages; i++) {
		/* we need to support large memory configurations */
		entry->busaddr[i] = dma_map_page(&pdev->dev, entry->pagelist[i],
						 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
		if (dma_mapping_error(&pdev->dev, entry->busaddr[i])) {
			DRM_ERROR("unable to map PCIGART pages!\n");
			drm_ati_pcigart_cleanup(dev, gart_info);
			address = NULL;
			bus_address = 0;
			ret = -ENOMEM;
			goto done;
		}
		page_base = (u32) entry->busaddr[i];

		for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
			u32 offset;
			u32 val;

			switch(gart_info->gart_reg_if) {
			case DRM_ATI_GART_IGP:
				val = page_base | 0xc;
				break;
			case DRM_ATI_GART_PCIE:
				val = (page_base >> 8) | 0xc;
				break;
			default:
			case DRM_ATI_GART_PCI:
				val = page_base;
				break;
			}
			if (gart_info->gart_table_location ==
			    DRM_ATI_GART_MAIN) {
				pci_gart[gart_idx] = cpu_to_le32(val);
			} else {
				offset = gart_idx * sizeof(u32);
				writel(val, (void __iomem *)map->handle + offset);
			}
			gart_idx++;
			page_base += ATI_PCIGART_PAGE_SIZE;
		}
	}
	ret = 0;

#ifdef CONFIG_X86
	wbinvd();
#else
	mb();
#endif

      done:
	gart_info->addr = address;
	gart_info->bus_addr = bus_address;
	return ret;
}
Commit	Line	Data
6ef2b857	1	/*
b5e89ed5	2	* \file ati_pcigart.c
1da177e4 LT	3	* ATI PCI GART support
	4	*
	5	* \author Gareth Hughes <gareth@valinux.com>
	6	*/
	7
	8	/*
	9	* Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
	10	*
	11	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
	12	* All Rights Reserved.
	13	*
	14	* Permission is hereby granted, free of charge, to any person obtaining a
	15	* copy of this software and associated documentation files (the "Software"),
	16	* to deal in the Software without restriction, including without limitation
	17	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	18	* and/or sell copies of the Software, and to permit persons to whom the
	19	* Software is furnished to do so, subject to the following conditions:
	20	*
	21	* The above copyright notice and this permission notice (including the next
	22	* paragraph) shall be included in all copies or substantial portions of the
	23	* Software.
	24	*
	25	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	26	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	27	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	28	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	29	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	30	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	31	* DEALINGS IN THE SOFTWARE.
	32	*/
	33
2d1a8a48	34	#include <linux/export.h>
625c18d7	35	#include <linux/pci.h>
1da177e4	36
0500c04e	37	#include <drm/drm_device.h>
625c18d7	38	#include <drm/drm_legacy.h>
0500c04e	39	#include <drm/drm_print.h>
fd7e0d71	40
be143124 JN	41	#include "ati_pcigart.h"
be143124 JN	42
1da177e4 LT	43	# define ATI_PCIGART_PAGE_SIZE 4096 /*< PCI GART page size /
1da177e4 LT	44
b05c2385 DA	45	static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
b05c2385 DA	46	struct drm_ati_pcigart_info *gart_info)
1da177e4	47	{
70556e24 JK	48	drm_dma_handle_t *dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
	49
	50	if (!dmah)
	51	return -ENOMEM;
	52
	53	dmah->size = gart_info->table_size;
	54	dmah->vaddr = dma_alloc_coherent(dev->dev,
	55	dmah->size,
	56	&dmah->busaddr,
	57	GFP_KERNEL);
	58
	59	if (!dmah->vaddr) {
	60	kfree(dmah);
b05c2385	61	return -ENOMEM;
70556e24	62	}
1da177e4	63
70556e24	64	gart_info->table_handle = dmah;
b05c2385	65	return 0;
1da177e4 LT	66	}
1da177e4 LT	67
b05c2385 DA	68	static void drm_ati_free_pcigart_table(struct drm_device *dev,
b05c2385 DA	69	struct drm_ati_pcigart_info *gart_info)
1da177e4	70	{
70556e24 JK	71	drm_dma_handle_t *dmah = gart_info->table_handle;
	72
	73	dma_free_coherent(dev->dev, dmah->size, dmah->vaddr, dmah->busaddr);
5562f75c JK	74	kfree(dmah);
5562f75c JK	75
b05c2385	76	gart_info->table_handle = NULL;
1da177e4 LT	77	}
1da177e4 LT	78
55910517	79	int drm_ati_pcigart_cleanup(struct drm_device dev, struct drm_ati_pcigart_info gart_info)
1da177e4	80	{
55910517	81	struct drm_sg_mem *entry = dev->sg;
aa96a16a	82	struct pci_dev *pdev = to_pci_dev(dev->dev);
1da177e4 LT	83	unsigned long pages;
1da177e4 LT	84	int i;
b05c2385	85	int max_pages;
1da177e4 LT	86
1da177e4 LT	87	/* we need to support large memory configurations */
b5e89ed5 DA	88	if (!entry) {
b5e89ed5 DA	89	DRM_ERROR("no scatter/gather memory!\n");
1da177e4 LT	90	return 0;
	91	}
	92
ea98a92f	93	if (gart_info->bus_addr) {
1da177e4	94
f2b04cd2 DA	95	max_pages = (gart_info->table_size / sizeof(u32));
	96	pages = (entry->pages <= max_pages)
	97	? entry->pages : max_pages;
1da177e4	98
b5e89ed5 DA	99	for (i = 0; i < pages; i++) {
	100	if (!entry->busaddr[i])
	101	break;
8bc92f66 CJ	102	dma_unmap_page(&pdev->dev, entry->busaddr[i],
8bc92f66 CJ	103	PAGE_SIZE, DMA_BIDIRECTIONAL);
1da177e4	104	}
b5e89ed5 DA	105
	106	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
	107	gart_info->bus_addr = 0;
1da177e4 LT	108	}
1da177e4 LT	109
b05c2385 DA	110	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
	111	gart_info->table_handle) {
	112	drm_ati_free_pcigart_table(dev, gart_info);
1da177e4 LT	113	}
	114
	115	return 1;
	116	}
1da177e4	117
55910517	118	int drm_ati_pcigart_init(struct drm_device dev, struct drm_ati_pcigart_info gart_info)
1da177e4	119	{
5a7aad9a	120	struct drm_local_map *map = &gart_info->mapping;
55910517	121	struct drm_sg_mem *entry = dev->sg;
aa96a16a	122	struct pci_dev *pdev = to_pci_dev(dev->dev);
f26c473c	123	void *address = NULL;
1da177e4	124	unsigned long pages;
6abf6601	125	u32 *pci_gart = NULL, page_base, gart_idx;
b05c2385	126	dma_addr_t bus_address = 0;
c27889ca	127	int i, j, ret = -ENOMEM;
d30333bb	128	int max_ati_pages, max_real_pages;
1da177e4	129
b5e89ed5 DA	130	if (!entry) {
b5e89ed5 DA	131	DRM_ERROR("no scatter/gather memory!\n");
1da177e4 LT	132	goto done;
	133	}
	134
b5e89ed5	135	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
ea98a92f	136	DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
b5e89ed5	137
8bc92f66	138	if (dma_set_mask(&pdev->dev, gart_info->table_mask)) {
e6be8d9d	139	DRM_ERROR("fail to set dma mask to 0x%Lx\n",
d7748bac	140	(unsigned long long)gart_info->table_mask);
c27889ca	141	ret = -EFAULT;
e6be8d9d ZW	142	goto done;
	143	}
	144
b05c2385 DA	145	ret = drm_ati_alloc_pcigart_table(dev, gart_info);
b05c2385 DA	146	if (ret) {
b5e89ed5	147	DRM_ERROR("cannot allocate PCI GART page!\n");
ea98a92f DA	148	goto done;
ea98a92f DA	149	}
b5e89ed5	150
6abf6601	151	pci_gart = gart_info->table_handle->vaddr;
b05c2385 DA	152	address = gart_info->table_handle->vaddr;
b05c2385 DA	153	bus_address = gart_info->table_handle->busaddr;
b5e89ed5	154	} else {
ea98a92f DA	155	address = gart_info->addr;
ea98a92f DA	156	bus_address = gart_info->bus_addr;
f67e74ca AM	157	DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
	158	(unsigned long long)bus_address,
	159	(unsigned long)address);
1da177e4 LT	160	}
1da177e4 LT	161
1da177e4	162
d30333bb DM	163	max_ati_pages = (gart_info->table_size / sizeof(u32));
	164	max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
	165	pages = (entry->pages <= max_real_pages)
	166	? entry->pages : max_real_pages;
1da177e4	167
5a7aad9a	168	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
d30333bb	169	memset(pci_gart, 0, max_ati_pages * sizeof(u32));
5a7aad9a	170	} else {
6abf6601	171	memset_io((void __iomem )map->handle, 0, max_ati_pages sizeof(u32));
5a7aad9a	172	}
1da177e4	173
5a7aad9a	174	gart_idx = 0;
b5e89ed5	175	for (i = 0; i < pages; i++) {
1da177e4	176	/* we need to support large memory configurations */
8bc92f66 CJ	177	entry->busaddr[i] = dma_map_page(&pdev->dev, entry->pagelist[i],
	178	0, PAGE_SIZE, DMA_BIDIRECTIONAL);
	179	if (dma_mapping_error(&pdev->dev, entry->busaddr[i])) {
b5e89ed5	180	DRM_ERROR("unable to map PCIGART pages!\n");
ea98a92f	181	drm_ati_pcigart_cleanup(dev, gart_info);
f26c473c	182	address = NULL;
1da177e4	183	bus_address = 0;
c27889ca	184	ret = -ENOMEM;
1da177e4 LT	185	goto done;
	186	}
	187	page_base = (u32) entry->busaddr[i];
	188
	189	for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
03fda35d	190	u32 offset;
5a7aad9a DM	191	u32 val;
5a7aad9a DM	192
f2b04cd2 DA	193	switch(gart_info->gart_reg_if) {
f2b04cd2 DA	194	case DRM_ATI_GART_IGP:
5a7aad9a	195	val = page_base \| 0xc;
f2b04cd2 DA	196	break;
f2b04cd2 DA	197	case DRM_ATI_GART_PCIE:
5a7aad9a	198	val = (page_base >> 8) \| 0xc;
f2b04cd2 DA	199	break;
	200	default:
	201	case DRM_ATI_GART_PCI:
5a7aad9a	202	val = page_base;
f2b04cd2 DA	203	break;
f2b04cd2 DA	204	}
5a7aad9a	205	if (gart_info->gart_table_location ==
03fda35d	206	DRM_ATI_GART_MAIN) {
5a7aad9a	207	pci_gart[gart_idx] = cpu_to_le32(val);
03fda35d SR	208	} else {
	209	offset = gart_idx * sizeof(u32);
	210	writel(val, (void __iomem *)map->handle + offset);
	211	}
5a7aad9a	212	gart_idx++;
1da177e4 LT	213	page_base += ATI_PCIGART_PAGE_SIZE;
	214	}
	215	}
c27889ca	216	ret = 0;
1da177e4	217
1a361b41	218	#ifdef CONFIG_X86
1da177e4 LT	219	wbinvd();
	220	#else
	221	mb();
	222	#endif
	223
b5e89ed5	224	done:
ea98a92f	225	gart_info->addr = address;
b5e89ed5	226	gart_info->bus_addr = bus_address;
1da177e4 LT	227	return ret;
1da177e4 LT	228	}