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f64122c1 DA |
1 | /* |
2 | * Copyright 2013 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Dave Airlie | |
23 | * Alon Levy | |
24 | */ | |
25 | ||
26 | /* QXL cmd/ring handling */ | |
27 | ||
28 | #include "qxl_drv.h" | |
29 | #include "qxl_object.h" | |
30 | ||
31 | static int qxl_reap_surface_id(struct qxl_device *qdev, int max_to_reap); | |
32 | ||
33 | struct ring { | |
34 | struct qxl_ring_header header; | |
35 | uint8_t elements[0]; | |
36 | }; | |
37 | ||
38 | struct qxl_ring { | |
39 | struct ring *ring; | |
40 | int element_size; | |
41 | int n_elements; | |
42 | int prod_notify; | |
43 | wait_queue_head_t *push_event; | |
44 | spinlock_t lock; | |
45 | }; | |
46 | ||
47 | void qxl_ring_free(struct qxl_ring *ring) | |
48 | { | |
49 | kfree(ring); | |
50 | } | |
51 | ||
1e209117 DA |
52 | void qxl_ring_init_hdr(struct qxl_ring *ring) |
53 | { | |
54 | ring->ring->header.notify_on_prod = ring->n_elements; | |
55 | } | |
56 | ||
f64122c1 DA |
57 | struct qxl_ring * |
58 | qxl_ring_create(struct qxl_ring_header *header, | |
59 | int element_size, | |
60 | int n_elements, | |
61 | int prod_notify, | |
62 | bool set_prod_notify, | |
63 | wait_queue_head_t *push_event) | |
64 | { | |
65 | struct qxl_ring *ring; | |
66 | ||
67 | ring = kmalloc(sizeof(*ring), GFP_KERNEL); | |
68 | if (!ring) | |
69 | return NULL; | |
70 | ||
71 | ring->ring = (struct ring *)header; | |
72 | ring->element_size = element_size; | |
73 | ring->n_elements = n_elements; | |
74 | ring->prod_notify = prod_notify; | |
75 | ring->push_event = push_event; | |
76 | if (set_prod_notify) | |
1e209117 | 77 | qxl_ring_init_hdr(ring); |
f64122c1 DA |
78 | spin_lock_init(&ring->lock); |
79 | return ring; | |
80 | } | |
81 | ||
82 | static int qxl_check_header(struct qxl_ring *ring) | |
83 | { | |
84 | int ret; | |
85 | struct qxl_ring_header *header = &(ring->ring->header); | |
86 | unsigned long flags; | |
87 | spin_lock_irqsave(&ring->lock, flags); | |
88 | ret = header->prod - header->cons < header->num_items; | |
89 | if (ret == 0) | |
90 | header->notify_on_cons = header->cons + 1; | |
91 | spin_unlock_irqrestore(&ring->lock, flags); | |
92 | return ret; | |
93 | } | |
94 | ||
1e209117 | 95 | int qxl_check_idle(struct qxl_ring *ring) |
f64122c1 DA |
96 | { |
97 | int ret; | |
98 | struct qxl_ring_header *header = &(ring->ring->header); | |
99 | unsigned long flags; | |
100 | spin_lock_irqsave(&ring->lock, flags); | |
101 | ret = header->prod == header->cons; | |
102 | spin_unlock_irqrestore(&ring->lock, flags); | |
103 | return ret; | |
104 | } | |
105 | ||
106 | int qxl_ring_push(struct qxl_ring *ring, | |
107 | const void *new_elt, bool interruptible) | |
108 | { | |
109 | struct qxl_ring_header *header = &(ring->ring->header); | |
110 | uint8_t *elt; | |
111 | int idx, ret; | |
112 | unsigned long flags; | |
113 | spin_lock_irqsave(&ring->lock, flags); | |
114 | if (header->prod - header->cons == header->num_items) { | |
115 | header->notify_on_cons = header->cons + 1; | |
116 | mb(); | |
117 | spin_unlock_irqrestore(&ring->lock, flags); | |
118 | if (!drm_can_sleep()) { | |
119 | while (!qxl_check_header(ring)) | |
120 | udelay(1); | |
121 | } else { | |
122 | if (interruptible) { | |
123 | ret = wait_event_interruptible(*ring->push_event, | |
124 | qxl_check_header(ring)); | |
125 | if (ret) | |
126 | return ret; | |
127 | } else { | |
128 | wait_event(*ring->push_event, | |
129 | qxl_check_header(ring)); | |
130 | } | |
131 | ||
132 | } | |
133 | spin_lock_irqsave(&ring->lock, flags); | |
134 | } | |
135 | ||
136 | idx = header->prod & (ring->n_elements - 1); | |
137 | elt = ring->ring->elements + idx * ring->element_size; | |
138 | ||
139 | memcpy((void *)elt, new_elt, ring->element_size); | |
140 | ||
141 | header->prod++; | |
142 | ||
143 | mb(); | |
144 | ||
145 | if (header->prod == header->notify_on_prod) | |
146 | outb(0, ring->prod_notify); | |
147 | ||
148 | spin_unlock_irqrestore(&ring->lock, flags); | |
149 | return 0; | |
150 | } | |
151 | ||
6d01f1f5 DA |
152 | static bool qxl_ring_pop(struct qxl_ring *ring, |
153 | void *element) | |
f64122c1 DA |
154 | { |
155 | volatile struct qxl_ring_header *header = &(ring->ring->header); | |
156 | volatile uint8_t *ring_elt; | |
157 | int idx; | |
158 | unsigned long flags; | |
159 | spin_lock_irqsave(&ring->lock, flags); | |
160 | if (header->cons == header->prod) { | |
161 | header->notify_on_prod = header->cons + 1; | |
162 | spin_unlock_irqrestore(&ring->lock, flags); | |
163 | return false; | |
164 | } | |
165 | ||
166 | idx = header->cons & (ring->n_elements - 1); | |
167 | ring_elt = ring->ring->elements + idx * ring->element_size; | |
168 | ||
169 | memcpy(element, (void *)ring_elt, ring->element_size); | |
170 | ||
171 | header->cons++; | |
172 | ||
173 | spin_unlock_irqrestore(&ring->lock, flags); | |
174 | return true; | |
175 | } | |
176 | ||
f64122c1 DA |
177 | int |
178 | qxl_push_command_ring_release(struct qxl_device *qdev, struct qxl_release *release, | |
179 | uint32_t type, bool interruptible) | |
180 | { | |
181 | struct qxl_command cmd; | |
8002db63 | 182 | struct qxl_bo_list *entry = list_first_entry(&release->bos, struct qxl_bo_list, tv.head); |
f64122c1 DA |
183 | |
184 | cmd.type = type; | |
8002db63 | 185 | cmd.data = qxl_bo_physical_address(qdev, to_qxl_bo(entry->tv.bo), release->release_offset); |
f64122c1 DA |
186 | |
187 | return qxl_ring_push(qdev->command_ring, &cmd, interruptible); | |
188 | } | |
189 | ||
190 | int | |
191 | qxl_push_cursor_ring_release(struct qxl_device *qdev, struct qxl_release *release, | |
192 | uint32_t type, bool interruptible) | |
193 | { | |
194 | struct qxl_command cmd; | |
8002db63 | 195 | struct qxl_bo_list *entry = list_first_entry(&release->bos, struct qxl_bo_list, tv.head); |
f64122c1 DA |
196 | |
197 | cmd.type = type; | |
8002db63 | 198 | cmd.data = qxl_bo_physical_address(qdev, to_qxl_bo(entry->tv.bo), release->release_offset); |
f64122c1 DA |
199 | |
200 | return qxl_ring_push(qdev->cursor_ring, &cmd, interruptible); | |
201 | } | |
202 | ||
203 | bool qxl_queue_garbage_collect(struct qxl_device *qdev, bool flush) | |
204 | { | |
205 | if (!qxl_check_idle(qdev->release_ring)) { | |
206 | queue_work(qdev->gc_queue, &qdev->gc_work); | |
207 | if (flush) | |
208 | flush_work(&qdev->gc_work); | |
209 | return true; | |
210 | } | |
211 | return false; | |
212 | } | |
213 | ||
214 | int qxl_garbage_collect(struct qxl_device *qdev) | |
215 | { | |
216 | struct qxl_release *release; | |
217 | uint64_t id, next_id; | |
218 | int i = 0; | |
f64122c1 DA |
219 | union qxl_release_info *info; |
220 | ||
221 | while (qxl_ring_pop(qdev->release_ring, &id)) { | |
222 | QXL_INFO(qdev, "popped %lld\n", id); | |
223 | while (id) { | |
224 | release = qxl_release_from_id_locked(qdev, id); | |
225 | if (release == NULL) | |
226 | break; | |
227 | ||
f64122c1 DA |
228 | info = qxl_release_map(qdev, release); |
229 | next_id = info->next; | |
230 | qxl_release_unmap(qdev, release, info); | |
231 | ||
f64122c1 DA |
232 | QXL_INFO(qdev, "popped %lld, next %lld\n", id, |
233 | next_id); | |
234 | ||
235 | switch (release->type) { | |
236 | case QXL_RELEASE_DRAWABLE: | |
237 | case QXL_RELEASE_SURFACE_CMD: | |
238 | case QXL_RELEASE_CURSOR_CMD: | |
239 | break; | |
240 | default: | |
241 | DRM_ERROR("unexpected release type\n"); | |
242 | break; | |
243 | } | |
244 | id = next_id; | |
245 | ||
246 | qxl_release_free(qdev, release); | |
247 | ++i; | |
248 | } | |
249 | } | |
250 | ||
72ec5650 | 251 | QXL_INFO(qdev, "%s: %d\n", __func__, i); |
f64122c1 DA |
252 | |
253 | return i; | |
254 | } | |
255 | ||
8002db63 DA |
256 | int qxl_alloc_bo_reserved(struct qxl_device *qdev, |
257 | struct qxl_release *release, | |
258 | unsigned long size, | |
f64122c1 DA |
259 | struct qxl_bo **_bo) |
260 | { | |
261 | struct qxl_bo *bo; | |
262 | int ret; | |
263 | ||
264 | ret = qxl_bo_create(qdev, size, false /* not kernel - device */, | |
4f49ec92 | 265 | false, QXL_GEM_DOMAIN_VRAM, NULL, &bo); |
f64122c1 DA |
266 | if (ret) { |
267 | DRM_ERROR("failed to allocate VRAM BO\n"); | |
268 | return ret; | |
269 | } | |
8002db63 DA |
270 | ret = qxl_release_list_add(release, bo); |
271 | if (ret) | |
f64122c1 DA |
272 | goto out_unref; |
273 | ||
274 | *_bo = bo; | |
275 | return 0; | |
276 | out_unref: | |
277 | qxl_bo_unref(&bo); | |
8002db63 | 278 | return ret; |
f64122c1 DA |
279 | } |
280 | ||
a6ac1bc3 | 281 | static int wait_for_io_cmd_user(struct qxl_device *qdev, uint8_t val, long port, bool intr) |
f64122c1 DA |
282 | { |
283 | int irq_num; | |
284 | long addr = qdev->io_base + port; | |
285 | int ret; | |
286 | ||
287 | mutex_lock(&qdev->async_io_mutex); | |
288 | irq_num = atomic_read(&qdev->irq_received_io_cmd); | |
f64122c1 | 289 | if (qdev->last_sent_io_cmd > irq_num) { |
a6ac1bc3 DA |
290 | if (intr) |
291 | ret = wait_event_interruptible_timeout(qdev->io_cmd_event, | |
292 | atomic_read(&qdev->irq_received_io_cmd) > irq_num, 5*HZ); | |
293 | else | |
294 | ret = wait_event_timeout(qdev->io_cmd_event, | |
295 | atomic_read(&qdev->irq_received_io_cmd) > irq_num, 5*HZ); | |
296 | /* 0 is timeout, just bail the "hw" has gone away */ | |
297 | if (ret <= 0) | |
f64122c1 DA |
298 | goto out; |
299 | irq_num = atomic_read(&qdev->irq_received_io_cmd); | |
300 | } | |
301 | outb(val, addr); | |
302 | qdev->last_sent_io_cmd = irq_num + 1; | |
a6ac1bc3 DA |
303 | if (intr) |
304 | ret = wait_event_interruptible_timeout(qdev->io_cmd_event, | |
305 | atomic_read(&qdev->irq_received_io_cmd) > irq_num, 5*HZ); | |
306 | else | |
307 | ret = wait_event_timeout(qdev->io_cmd_event, | |
308 | atomic_read(&qdev->irq_received_io_cmd) > irq_num, 5*HZ); | |
f64122c1 | 309 | out: |
a6ac1bc3 DA |
310 | if (ret > 0) |
311 | ret = 0; | |
f64122c1 DA |
312 | mutex_unlock(&qdev->async_io_mutex); |
313 | return ret; | |
314 | } | |
315 | ||
316 | static void wait_for_io_cmd(struct qxl_device *qdev, uint8_t val, long port) | |
317 | { | |
318 | int ret; | |
319 | ||
320 | restart: | |
a6ac1bc3 | 321 | ret = wait_for_io_cmd_user(qdev, val, port, false); |
f64122c1 DA |
322 | if (ret == -ERESTARTSYS) |
323 | goto restart; | |
324 | } | |
325 | ||
326 | int qxl_io_update_area(struct qxl_device *qdev, struct qxl_bo *surf, | |
327 | const struct qxl_rect *area) | |
328 | { | |
329 | int surface_id; | |
330 | uint32_t surface_width, surface_height; | |
331 | int ret; | |
332 | ||
333 | if (!surf->hw_surf_alloc) | |
334 | DRM_ERROR("got io update area with no hw surface\n"); | |
335 | ||
336 | if (surf->is_primary) | |
337 | surface_id = 0; | |
338 | else | |
339 | surface_id = surf->surface_id; | |
340 | surface_width = surf->surf.width; | |
341 | surface_height = surf->surf.height; | |
342 | ||
343 | if (area->left < 0 || area->top < 0 || | |
344 | area->right > surface_width || area->bottom > surface_height) { | |
345 | qxl_io_log(qdev, "%s: not doing area update for " | |
346 | "%d, (%d,%d,%d,%d) (%d,%d)\n", __func__, surface_id, area->left, | |
347 | area->top, area->right, area->bottom, surface_width, surface_height); | |
348 | return -EINVAL; | |
349 | } | |
350 | mutex_lock(&qdev->update_area_mutex); | |
351 | qdev->ram_header->update_area = *area; | |
352 | qdev->ram_header->update_surface = surface_id; | |
a6ac1bc3 | 353 | ret = wait_for_io_cmd_user(qdev, 0, QXL_IO_UPDATE_AREA_ASYNC, true); |
f64122c1 DA |
354 | mutex_unlock(&qdev->update_area_mutex); |
355 | return ret; | |
356 | } | |
357 | ||
358 | void qxl_io_notify_oom(struct qxl_device *qdev) | |
359 | { | |
360 | outb(0, qdev->io_base + QXL_IO_NOTIFY_OOM); | |
361 | } | |
362 | ||
363 | void qxl_io_flush_release(struct qxl_device *qdev) | |
364 | { | |
365 | outb(0, qdev->io_base + QXL_IO_FLUSH_RELEASE); | |
366 | } | |
367 | ||
368 | void qxl_io_flush_surfaces(struct qxl_device *qdev) | |
369 | { | |
370 | wait_for_io_cmd(qdev, 0, QXL_IO_FLUSH_SURFACES_ASYNC); | |
371 | } | |
372 | ||
373 | ||
374 | void qxl_io_destroy_primary(struct qxl_device *qdev) | |
375 | { | |
376 | wait_for_io_cmd(qdev, 0, QXL_IO_DESTROY_PRIMARY_ASYNC); | |
377 | } | |
378 | ||
07f8d9bd DA |
379 | void qxl_io_create_primary(struct qxl_device *qdev, |
380 | unsigned offset, struct qxl_bo *bo) | |
f64122c1 DA |
381 | { |
382 | struct qxl_surface_create *create; | |
383 | ||
384 | QXL_INFO(qdev, "%s: qdev %p, ram_header %p\n", __func__, qdev, | |
385 | qdev->ram_header); | |
386 | create = &qdev->ram_header->create_surface; | |
387 | create->format = bo->surf.format; | |
07f8d9bd DA |
388 | create->width = bo->surf.width; |
389 | create->height = bo->surf.height; | |
f64122c1 DA |
390 | create->stride = bo->surf.stride; |
391 | create->mem = qxl_bo_physical_address(qdev, bo, offset); | |
392 | ||
393 | QXL_INFO(qdev, "%s: mem = %llx, from %p\n", __func__, create->mem, | |
394 | bo->kptr); | |
395 | ||
396 | create->flags = QXL_SURF_FLAG_KEEP_DATA; | |
397 | create->type = QXL_SURF_TYPE_PRIMARY; | |
398 | ||
399 | wait_for_io_cmd(qdev, 0, QXL_IO_CREATE_PRIMARY_ASYNC); | |
400 | } | |
401 | ||
402 | void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id) | |
403 | { | |
404 | QXL_INFO(qdev, "qxl_memslot_add %d\n", id); | |
405 | wait_for_io_cmd(qdev, id, QXL_IO_MEMSLOT_ADD_ASYNC); | |
406 | } | |
407 | ||
408 | void qxl_io_log(struct qxl_device *qdev, const char *fmt, ...) | |
409 | { | |
410 | va_list args; | |
411 | ||
412 | va_start(args, fmt); | |
413 | vsnprintf(qdev->ram_header->log_buf, QXL_LOG_BUF_SIZE, fmt, args); | |
414 | va_end(args); | |
415 | /* | |
416 | * DO not do a DRM output here - this will call printk, which will | |
417 | * call back into qxl for rendering (qxl_fb) | |
418 | */ | |
419 | outb(0, qdev->io_base + QXL_IO_LOG); | |
420 | } | |
421 | ||
422 | void qxl_io_reset(struct qxl_device *qdev) | |
423 | { | |
424 | outb(0, qdev->io_base + QXL_IO_RESET); | |
425 | } | |
426 | ||
427 | void qxl_io_monitors_config(struct qxl_device *qdev) | |
428 | { | |
429 | qxl_io_log(qdev, "%s: %d [%dx%d+%d+%d]\n", __func__, | |
430 | qdev->monitors_config ? | |
431 | qdev->monitors_config->count : -1, | |
432 | qdev->monitors_config && qdev->monitors_config->count ? | |
433 | qdev->monitors_config->heads[0].width : -1, | |
434 | qdev->monitors_config && qdev->monitors_config->count ? | |
435 | qdev->monitors_config->heads[0].height : -1, | |
436 | qdev->monitors_config && qdev->monitors_config->count ? | |
437 | qdev->monitors_config->heads[0].x : -1, | |
438 | qdev->monitors_config && qdev->monitors_config->count ? | |
439 | qdev->monitors_config->heads[0].y : -1 | |
440 | ); | |
441 | ||
442 | wait_for_io_cmd(qdev, 0, QXL_IO_MONITORS_CONFIG_ASYNC); | |
443 | } | |
444 | ||
445 | int qxl_surface_id_alloc(struct qxl_device *qdev, | |
446 | struct qxl_bo *surf) | |
447 | { | |
307b9c02 | 448 | uint32_t handle; |
f64122c1 DA |
449 | int idr_ret; |
450 | int count = 0; | |
451 | again: | |
307b9c02 | 452 | idr_preload(GFP_ATOMIC); |
f64122c1 | 453 | spin_lock(&qdev->surf_id_idr_lock); |
307b9c02 | 454 | idr_ret = idr_alloc(&qdev->surf_id_idr, NULL, 1, 0, GFP_NOWAIT); |
f64122c1 | 455 | spin_unlock(&qdev->surf_id_idr_lock); |
307b9c02 DA |
456 | idr_preload_end(); |
457 | if (idr_ret < 0) | |
458 | return idr_ret; | |
459 | handle = idr_ret; | |
f64122c1 DA |
460 | |
461 | if (handle >= qdev->rom->n_surfaces) { | |
462 | count++; | |
463 | spin_lock(&qdev->surf_id_idr_lock); | |
464 | idr_remove(&qdev->surf_id_idr, handle); | |
465 | spin_unlock(&qdev->surf_id_idr_lock); | |
466 | qxl_reap_surface_id(qdev, 2); | |
467 | goto again; | |
468 | } | |
469 | surf->surface_id = handle; | |
470 | ||
471 | spin_lock(&qdev->surf_id_idr_lock); | |
472 | qdev->last_alloced_surf_id = handle; | |
473 | spin_unlock(&qdev->surf_id_idr_lock); | |
f64122c1 DA |
474 | return 0; |
475 | } | |
476 | ||
477 | void qxl_surface_id_dealloc(struct qxl_device *qdev, | |
478 | uint32_t surface_id) | |
479 | { | |
480 | spin_lock(&qdev->surf_id_idr_lock); | |
481 | idr_remove(&qdev->surf_id_idr, surface_id); | |
482 | spin_unlock(&qdev->surf_id_idr_lock); | |
483 | } | |
484 | ||
485 | int qxl_hw_surface_alloc(struct qxl_device *qdev, | |
486 | struct qxl_bo *surf, | |
487 | struct ttm_mem_reg *new_mem) | |
488 | { | |
489 | struct qxl_surface_cmd *cmd; | |
490 | struct qxl_release *release; | |
491 | int ret; | |
492 | ||
493 | if (surf->hw_surf_alloc) | |
494 | return 0; | |
495 | ||
496 | ret = qxl_alloc_surface_release_reserved(qdev, QXL_SURFACE_CMD_CREATE, | |
497 | NULL, | |
498 | &release); | |
499 | if (ret) | |
500 | return ret; | |
501 | ||
8002db63 DA |
502 | ret = qxl_release_reserve_list(release, true); |
503 | if (ret) | |
504 | return ret; | |
505 | ||
f64122c1 DA |
506 | cmd = (struct qxl_surface_cmd *)qxl_release_map(qdev, release); |
507 | cmd->type = QXL_SURFACE_CMD_CREATE; | |
2fa19535 | 508 | cmd->flags = QXL_SURF_FLAG_KEEP_DATA; |
f64122c1 DA |
509 | cmd->u.surface_create.format = surf->surf.format; |
510 | cmd->u.surface_create.width = surf->surf.width; | |
511 | cmd->u.surface_create.height = surf->surf.height; | |
512 | cmd->u.surface_create.stride = surf->surf.stride; | |
513 | if (new_mem) { | |
514 | int slot_id = surf->type == QXL_GEM_DOMAIN_VRAM ? qdev->main_mem_slot : qdev->surfaces_mem_slot; | |
515 | struct qxl_memslot *slot = &(qdev->mem_slots[slot_id]); | |
516 | ||
517 | /* TODO - need to hold one of the locks to read tbo.offset */ | |
518 | cmd->u.surface_create.data = slot->high_bits; | |
519 | ||
520 | cmd->u.surface_create.data |= (new_mem->start << PAGE_SHIFT) + surf->tbo.bdev->man[new_mem->mem_type].gpu_offset; | |
521 | } else | |
522 | cmd->u.surface_create.data = qxl_bo_physical_address(qdev, surf, 0); | |
523 | cmd->surface_id = surf->surface_id; | |
524 | qxl_release_unmap(qdev, release, &cmd->release_info); | |
525 | ||
526 | surf->surf_create = release; | |
527 | ||
8002db63 | 528 | /* no need to add a release to the fence for this surface bo, |
f64122c1 DA |
529 | since it is only released when we ask to destroy the surface |
530 | and it would never signal otherwise */ | |
f64122c1 | 531 | qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false); |
8002db63 | 532 | qxl_release_fence_buffer_objects(release); |
f64122c1 DA |
533 | |
534 | surf->hw_surf_alloc = true; | |
535 | spin_lock(&qdev->surf_id_idr_lock); | |
536 | idr_replace(&qdev->surf_id_idr, surf, surf->surface_id); | |
537 | spin_unlock(&qdev->surf_id_idr_lock); | |
538 | return 0; | |
539 | } | |
540 | ||
541 | int qxl_hw_surface_dealloc(struct qxl_device *qdev, | |
542 | struct qxl_bo *surf) | |
543 | { | |
544 | struct qxl_surface_cmd *cmd; | |
545 | struct qxl_release *release; | |
546 | int ret; | |
547 | int id; | |
548 | ||
549 | if (!surf->hw_surf_alloc) | |
550 | return 0; | |
551 | ||
552 | ret = qxl_alloc_surface_release_reserved(qdev, QXL_SURFACE_CMD_DESTROY, | |
553 | surf->surf_create, | |
554 | &release); | |
555 | if (ret) | |
556 | return ret; | |
557 | ||
558 | surf->surf_create = NULL; | |
559 | /* remove the surface from the idr, but not the surface id yet */ | |
560 | spin_lock(&qdev->surf_id_idr_lock); | |
561 | idr_replace(&qdev->surf_id_idr, NULL, surf->surface_id); | |
562 | spin_unlock(&qdev->surf_id_idr_lock); | |
563 | surf->hw_surf_alloc = false; | |
564 | ||
565 | id = surf->surface_id; | |
566 | surf->surface_id = 0; | |
567 | ||
568 | release->surface_release_id = id; | |
569 | cmd = (struct qxl_surface_cmd *)qxl_release_map(qdev, release); | |
570 | cmd->type = QXL_SURFACE_CMD_DESTROY; | |
571 | cmd->surface_id = id; | |
572 | qxl_release_unmap(qdev, release, &cmd->release_info); | |
573 | ||
f64122c1 DA |
574 | qxl_push_command_ring_release(qdev, release, QXL_CMD_SURFACE, false); |
575 | ||
8002db63 | 576 | qxl_release_fence_buffer_objects(release); |
f64122c1 DA |
577 | |
578 | return 0; | |
579 | } | |
580 | ||
581 | int qxl_update_surface(struct qxl_device *qdev, struct qxl_bo *surf) | |
582 | { | |
583 | struct qxl_rect rect; | |
584 | int ret; | |
585 | ||
586 | /* if we are evicting, we need to make sure the surface is up | |
587 | to date */ | |
588 | rect.left = 0; | |
589 | rect.right = surf->surf.width; | |
590 | rect.top = 0; | |
591 | rect.bottom = surf->surf.height; | |
592 | retry: | |
593 | ret = qxl_io_update_area(qdev, surf, &rect); | |
594 | if (ret == -ERESTARTSYS) | |
595 | goto retry; | |
596 | return ret; | |
597 | } | |
598 | ||
6d01f1f5 | 599 | static void qxl_surface_evict_locked(struct qxl_device *qdev, struct qxl_bo *surf, bool do_update_area) |
f64122c1 DA |
600 | { |
601 | /* no need to update area if we are just freeing the surface normally */ | |
602 | if (do_update_area) | |
603 | qxl_update_surface(qdev, surf); | |
604 | ||
605 | /* nuke the surface id at the hw */ | |
606 | qxl_hw_surface_dealloc(qdev, surf); | |
607 | } | |
608 | ||
609 | void qxl_surface_evict(struct qxl_device *qdev, struct qxl_bo *surf, bool do_update_area) | |
610 | { | |
611 | mutex_lock(&qdev->surf_evict_mutex); | |
612 | qxl_surface_evict_locked(qdev, surf, do_update_area); | |
613 | mutex_unlock(&qdev->surf_evict_mutex); | |
614 | } | |
615 | ||
616 | static int qxl_reap_surf(struct qxl_device *qdev, struct qxl_bo *surf, bool stall) | |
617 | { | |
618 | int ret; | |
619 | ||
620 | ret = qxl_bo_reserve(surf, false); | |
c610c713 FZ |
621 | if (ret) |
622 | return ret; | |
f64122c1 | 623 | |
f64122c1 DA |
624 | if (stall) |
625 | mutex_unlock(&qdev->surf_evict_mutex); | |
626 | ||
8aa6d4fc | 627 | ret = ttm_bo_wait(&surf->tbo, true, !stall); |
f64122c1 DA |
628 | |
629 | if (stall) | |
630 | mutex_lock(&qdev->surf_evict_mutex); | |
c610c713 | 631 | if (ret) { |
f64122c1 | 632 | qxl_bo_unreserve(surf); |
c610c713 | 633 | return ret; |
f64122c1 DA |
634 | } |
635 | ||
636 | qxl_surface_evict_locked(qdev, surf, true); | |
637 | qxl_bo_unreserve(surf); | |
638 | return 0; | |
639 | } | |
640 | ||
641 | static int qxl_reap_surface_id(struct qxl_device *qdev, int max_to_reap) | |
642 | { | |
643 | int num_reaped = 0; | |
644 | int i, ret; | |
645 | bool stall = false; | |
646 | int start = 0; | |
647 | ||
648 | mutex_lock(&qdev->surf_evict_mutex); | |
649 | again: | |
650 | ||
651 | spin_lock(&qdev->surf_id_idr_lock); | |
652 | start = qdev->last_alloced_surf_id + 1; | |
653 | spin_unlock(&qdev->surf_id_idr_lock); | |
654 | ||
655 | for (i = start; i < start + qdev->rom->n_surfaces; i++) { | |
656 | void *objptr; | |
657 | int surfid = i % qdev->rom->n_surfaces; | |
658 | ||
659 | /* this avoids the case where the objects is in the | |
660 | idr but has been evicted half way - its makes | |
661 | the idr lookup atomic with the eviction */ | |
662 | spin_lock(&qdev->surf_id_idr_lock); | |
663 | objptr = idr_find(&qdev->surf_id_idr, surfid); | |
664 | spin_unlock(&qdev->surf_id_idr_lock); | |
665 | ||
666 | if (!objptr) | |
667 | continue; | |
668 | ||
669 | ret = qxl_reap_surf(qdev, objptr, stall); | |
670 | if (ret == 0) | |
671 | num_reaped++; | |
672 | if (num_reaped >= max_to_reap) | |
673 | break; | |
674 | } | |
675 | if (num_reaped == 0 && stall == false) { | |
676 | stall = true; | |
677 | goto again; | |
678 | } | |
679 | ||
680 | mutex_unlock(&qdev->surf_evict_mutex); | |
681 | if (num_reaped) { | |
682 | usleep_range(500, 1000); | |
683 | qxl_queue_garbage_collect(qdev, true); | |
684 | } | |
685 | ||
686 | return 0; | |
687 | } |