Commit | Line | Data |
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280921de TR |
1 | /* |
2 | * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the | |
12 | * next paragraph) shall be included in all copies or substantial portions | |
13 | * of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
cb23eae3 | 24 | #include <linux/delay.h> |
cfdf0549 | 25 | #include <linux/gpio/consumer.h> |
a204f974 | 26 | #include <linux/i2c.h> |
72bd9ea3 | 27 | #include <linux/media-bus-format.h> |
280921de | 28 | #include <linux/module.h> |
280921de TR |
29 | #include <linux/of_platform.h> |
30 | #include <linux/platform_device.h> | |
3235b0f2 | 31 | #include <linux/pm_runtime.h> |
280921de TR |
32 | #include <linux/regulator/consumer.h> |
33 | ||
cb23eae3 | 34 | #include <video/display_timing.h> |
b8a2948f | 35 | #include <video/of_display_timing.h> |
cb23eae3 SR |
36 | #include <video/videomode.h> |
37 | ||
280921de | 38 | #include <drm/drm_crtc.h> |
cb23eae3 | 39 | #include <drm/drm_device.h> |
255490f9 | 40 | #include <drm/drm_edid.h> |
210fcd9d | 41 | #include <drm/drm_mipi_dsi.h> |
280921de | 42 | #include <drm/drm_panel.h> |
1cd3ea3e | 43 | #include <drm/drm_of.h> |
280921de | 44 | |
e362cc6a | 45 | /** |
a00fa428 | 46 | * struct panel_desc - Describes a simple panel. |
e362cc6a | 47 | */ |
280921de | 48 | struct panel_desc { |
a00fa428 DA |
49 | /** |
50 | * @modes: Pointer to array of fixed modes appropriate for this panel. | |
51 | * | |
52 | * If only one mode then this can just be the address of the mode. | |
53 | * NOTE: cannot be used with "timings" and also if this is specified | |
54 | * then you cannot override the mode in the device tree. | |
55 | */ | |
280921de | 56 | const struct drm_display_mode *modes; |
a00fa428 DA |
57 | |
58 | /** @num_modes: Number of elements in modes array. */ | |
280921de | 59 | unsigned int num_modes; |
a00fa428 DA |
60 | |
61 | /** | |
62 | * @timings: Pointer to array of display timings | |
63 | * | |
64 | * NOTE: cannot be used with "modes" and also these will be used to | |
65 | * validate a device tree override if one is present. | |
66 | */ | |
a5d3e625 | 67 | const struct display_timing *timings; |
a00fa428 DA |
68 | |
69 | /** @num_timings: Number of elements in timings array. */ | |
a5d3e625 | 70 | unsigned int num_timings; |
280921de | 71 | |
a00fa428 | 72 | /** @bpc: Bits per color. */ |
0208d511 SM |
73 | unsigned int bpc; |
74 | ||
a00fa428 | 75 | /** @size: Structure containing the physical size of this panel. */ |
280921de | 76 | struct { |
131f909a DA |
77 | /** |
78 | * @size.width: Width (in mm) of the active display area. | |
79 | */ | |
280921de | 80 | unsigned int width; |
131f909a DA |
81 | |
82 | /** | |
83 | * @size.height: Height (in mm) of the active display area. | |
84 | */ | |
280921de TR |
85 | unsigned int height; |
86 | } size; | |
f673c37e | 87 | |
a00fa428 | 88 | /** @delay: Structure containing various delay values for this panel. */ |
f673c37e | 89 | struct { |
131f909a DA |
90 | /** |
91 | * @delay.prepare: Time for the panel to become ready. | |
92 | * | |
93 | * The time (in milliseconds) that it takes for the panel to | |
94 | * become ready and start receiving video data | |
95 | */ | |
f673c37e | 96 | unsigned int prepare; |
131f909a | 97 | |
131f909a DA |
98 | /** |
99 | * @delay.enable: Time for the panel to display a valid frame. | |
100 | * | |
101 | * The time (in milliseconds) that it takes for the panel to | |
102 | * display the first valid frame after starting to receive | |
103 | * video data. | |
104 | */ | |
f673c37e | 105 | unsigned int enable; |
131f909a DA |
106 | |
107 | /** | |
108 | * @delay.disable: Time for the panel to turn the display off. | |
109 | * | |
110 | * The time (in milliseconds) that it takes for the panel to | |
111 | * turn the display off (no content is visible). | |
112 | */ | |
f673c37e | 113 | unsigned int disable; |
131f909a DA |
114 | |
115 | /** | |
116 | * @delay.unprepare: Time to power down completely. | |
117 | * | |
118 | * The time (in milliseconds) that it takes for the panel | |
119 | * to power itself down completely. | |
e5e30dfc DA |
120 | * |
121 | * This time is used to prevent a future "prepare" from | |
122 | * starting until at least this many milliseconds has passed. | |
123 | * If at prepare time less time has passed since unprepare | |
124 | * finished, the driver waits for the remaining time. | |
131f909a | 125 | */ |
f673c37e AK |
126 | unsigned int unprepare; |
127 | } delay; | |
795f7ab3 | 128 | |
a00fa428 | 129 | /** @bus_format: See MEDIA_BUS_FMT_... defines. */ |
795f7ab3 | 130 | u32 bus_format; |
a00fa428 DA |
131 | |
132 | /** @bus_flags: See DRM_BUS_FLAG_... defines. */ | |
f0aa0838 | 133 | u32 bus_flags; |
a00fa428 DA |
134 | |
135 | /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ | |
9a2654c0 | 136 | int connector_type; |
280921de TR |
137 | }; |
138 | ||
280921de TR |
139 | struct panel_simple { |
140 | struct drm_panel base; | |
3235b0f2 | 141 | |
e5e30dfc DA |
142 | ktime_t unprepared_time; |
143 | ||
280921de TR |
144 | const struct panel_desc *desc; |
145 | ||
280921de TR |
146 | struct regulator *supply; |
147 | struct i2c_adapter *ddc; | |
148 | ||
cfdf0549 | 149 | struct gpio_desc *enable_gpio; |
b8a2948f | 150 | |
e69da902 | 151 | const struct drm_edid *drm_edid; |
63358e24 | 152 | |
b8a2948f | 153 | struct drm_display_mode override_mode; |
5759c967 DO |
154 | |
155 | enum drm_panel_orientation orientation; | |
280921de TR |
156 | }; |
157 | ||
158 | static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) | |
159 | { | |
160 | return container_of(panel, struct panel_simple, base); | |
161 | } | |
162 | ||
0ce8ddd8 SR |
163 | static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, |
164 | struct drm_connector *connector) | |
280921de | 165 | { |
280921de TR |
166 | struct drm_display_mode *mode; |
167 | unsigned int i, num = 0; | |
168 | ||
a5d3e625 PZ |
169 | for (i = 0; i < panel->desc->num_timings; i++) { |
170 | const struct display_timing *dt = &panel->desc->timings[i]; | |
171 | struct videomode vm; | |
172 | ||
173 | videomode_from_timing(dt, &vm); | |
aa6c4364 | 174 | mode = drm_mode_create(connector->dev); |
a5d3e625 | 175 | if (!mode) { |
aa6c4364 | 176 | dev_err(panel->base.dev, "failed to add mode %ux%u\n", |
a5d3e625 PZ |
177 | dt->hactive.typ, dt->vactive.typ); |
178 | continue; | |
179 | } | |
180 | ||
181 | drm_display_mode_from_videomode(&vm, mode); | |
cda55372 BB |
182 | |
183 | mode->type |= DRM_MODE_TYPE_DRIVER; | |
184 | ||
230c5b44 | 185 | if (panel->desc->num_timings == 1) |
cda55372 BB |
186 | mode->type |= DRM_MODE_TYPE_PREFERRED; |
187 | ||
a5d3e625 PZ |
188 | drm_mode_probed_add(connector, mode); |
189 | num++; | |
190 | } | |
191 | ||
b8a2948f SP |
192 | return num; |
193 | } | |
194 | ||
0ce8ddd8 SR |
195 | static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, |
196 | struct drm_connector *connector) | |
b8a2948f | 197 | { |
b8a2948f SP |
198 | struct drm_display_mode *mode; |
199 | unsigned int i, num = 0; | |
200 | ||
280921de TR |
201 | for (i = 0; i < panel->desc->num_modes; i++) { |
202 | const struct drm_display_mode *m = &panel->desc->modes[i]; | |
203 | ||
aa6c4364 | 204 | mode = drm_mode_duplicate(connector->dev, m); |
280921de | 205 | if (!mode) { |
aa6c4364 | 206 | dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", |
0425662f VS |
207 | m->hdisplay, m->vdisplay, |
208 | drm_mode_vrefresh(m)); | |
280921de TR |
209 | continue; |
210 | } | |
211 | ||
cda55372 BB |
212 | mode->type |= DRM_MODE_TYPE_DRIVER; |
213 | ||
214 | if (panel->desc->num_modes == 1) | |
215 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
216 | ||
280921de TR |
217 | drm_mode_set_name(mode); |
218 | ||
219 | drm_mode_probed_add(connector, mode); | |
220 | num++; | |
221 | } | |
222 | ||
b8a2948f SP |
223 | return num; |
224 | } | |
225 | ||
0ce8ddd8 SR |
226 | static int panel_simple_get_non_edid_modes(struct panel_simple *panel, |
227 | struct drm_connector *connector) | |
b8a2948f | 228 | { |
b8a2948f SP |
229 | struct drm_display_mode *mode; |
230 | bool has_override = panel->override_mode.type; | |
231 | unsigned int num = 0; | |
232 | ||
233 | if (!panel->desc) | |
234 | return 0; | |
235 | ||
236 | if (has_override) { | |
aa6c4364 SR |
237 | mode = drm_mode_duplicate(connector->dev, |
238 | &panel->override_mode); | |
b8a2948f SP |
239 | if (mode) { |
240 | drm_mode_probed_add(connector, mode); | |
241 | num = 1; | |
242 | } else { | |
aa6c4364 | 243 | dev_err(panel->base.dev, "failed to add override mode\n"); |
b8a2948f SP |
244 | } |
245 | } | |
246 | ||
247 | /* Only add timings if override was not there or failed to validate */ | |
248 | if (num == 0 && panel->desc->num_timings) | |
0ce8ddd8 | 249 | num = panel_simple_get_timings_modes(panel, connector); |
b8a2948f SP |
250 | |
251 | /* | |
252 | * Only add fixed modes if timings/override added no mode. | |
253 | * | |
254 | * We should only ever have either the display timings specified | |
255 | * or a fixed mode. Anything else is rather bogus. | |
256 | */ | |
257 | WARN_ON(panel->desc->num_timings && panel->desc->num_modes); | |
258 | if (num == 0) | |
0ce8ddd8 | 259 | num = panel_simple_get_display_modes(panel, connector); |
b8a2948f | 260 | |
0208d511 | 261 | connector->display_info.bpc = panel->desc->bpc; |
280921de TR |
262 | connector->display_info.width_mm = panel->desc->size.width; |
263 | connector->display_info.height_mm = panel->desc->size.height; | |
795f7ab3 BB |
264 | if (panel->desc->bus_format) |
265 | drm_display_info_set_bus_formats(&connector->display_info, | |
266 | &panel->desc->bus_format, 1); | |
f0aa0838 | 267 | connector->display_info.bus_flags = panel->desc->bus_flags; |
280921de TR |
268 | |
269 | return num; | |
270 | } | |
271 | ||
e5e30dfc DA |
272 | static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) |
273 | { | |
274 | ktime_t now_ktime, min_ktime; | |
275 | ||
276 | if (!min_ms) | |
277 | return; | |
278 | ||
279 | min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); | |
7e682946 | 280 | now_ktime = ktime_get_boottime(); |
e5e30dfc DA |
281 | |
282 | if (ktime_before(now_ktime, min_ktime)) | |
283 | msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); | |
284 | } | |
285 | ||
280921de TR |
286 | static int panel_simple_disable(struct drm_panel *panel) |
287 | { | |
288 | struct panel_simple *p = to_panel_simple(panel); | |
289 | ||
f673c37e AK |
290 | if (p->desc->delay.disable) |
291 | msleep(p->desc->delay.disable); | |
292 | ||
280921de TR |
293 | return 0; |
294 | } | |
295 | ||
3235b0f2 DA |
296 | static int panel_simple_suspend(struct device *dev) |
297 | { | |
298 | struct panel_simple *p = dev_get_drvdata(dev); | |
299 | ||
300 | gpiod_set_value_cansleep(p->enable_gpio, 0); | |
301 | regulator_disable(p->supply); | |
7e682946 | 302 | p->unprepared_time = ktime_get_boottime(); |
3235b0f2 | 303 | |
e69da902 JN |
304 | drm_edid_free(p->drm_edid); |
305 | p->drm_edid = NULL; | |
63358e24 | 306 | |
3235b0f2 DA |
307 | return 0; |
308 | } | |
309 | ||
c0e1d170 AK |
310 | static int panel_simple_unprepare(struct drm_panel *panel) |
311 | { | |
3235b0f2 | 312 | int ret; |
613a633e | 313 | |
3235b0f2 DA |
314 | pm_runtime_mark_last_busy(panel->dev); |
315 | ret = pm_runtime_put_autosuspend(panel->dev); | |
316 | if (ret < 0) | |
317 | return ret; | |
c0e1d170 | 318 | |
c0e1d170 AK |
319 | return 0; |
320 | } | |
321 | ||
b6d5ffce | 322 | static int panel_simple_resume(struct device *dev) |
280921de | 323 | { |
b6d5ffce | 324 | struct panel_simple *p = dev_get_drvdata(dev); |
280921de TR |
325 | int err; |
326 | ||
e5e30dfc DA |
327 | panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); |
328 | ||
280921de TR |
329 | err = regulator_enable(p->supply); |
330 | if (err < 0) { | |
3235b0f2 | 331 | dev_err(dev, "failed to enable supply: %d\n", err); |
280921de TR |
332 | return err; |
333 | } | |
334 | ||
756b918d | 335 | gpiod_set_value_cansleep(p->enable_gpio, 1); |
280921de | 336 | |
b6d5ffce DA |
337 | if (p->desc->delay.prepare) |
338 | msleep(p->desc->delay.prepare); | |
48834e60 | 339 | |
613a633e | 340 | return 0; |
87b49717 DA |
341 | } |
342 | ||
3235b0f2 DA |
343 | static int panel_simple_prepare(struct drm_panel *panel) |
344 | { | |
3235b0f2 DA |
345 | int ret; |
346 | ||
3235b0f2 DA |
347 | ret = pm_runtime_get_sync(panel->dev); |
348 | if (ret < 0) { | |
349 | pm_runtime_put_autosuspend(panel->dev); | |
350 | return ret; | |
351 | } | |
352 | ||
3235b0f2 DA |
353 | return 0; |
354 | } | |
355 | ||
613a633e AK |
356 | static int panel_simple_enable(struct drm_panel *panel) |
357 | { | |
358 | struct panel_simple *p = to_panel_simple(panel); | |
359 | ||
f673c37e AK |
360 | if (p->desc->delay.enable) |
361 | msleep(p->desc->delay.enable); | |
362 | ||
280921de TR |
363 | return 0; |
364 | } | |
365 | ||
0ce8ddd8 SR |
366 | static int panel_simple_get_modes(struct drm_panel *panel, |
367 | struct drm_connector *connector) | |
280921de TR |
368 | { |
369 | struct panel_simple *p = to_panel_simple(panel); | |
370 | int num = 0; | |
371 | ||
372 | /* probe EDID if a DDC bus is available */ | |
373 | if (p->ddc) { | |
31e25395 DA |
374 | pm_runtime_get_sync(panel->dev); |
375 | ||
e69da902 JN |
376 | if (!p->drm_edid) |
377 | p->drm_edid = drm_edid_read_ddc(connector, p->ddc); | |
63358e24 | 378 | |
e69da902 JN |
379 | drm_edid_connector_update(connector, p->drm_edid); |
380 | ||
381 | num += drm_edid_connector_add_modes(connector); | |
31e25395 DA |
382 | |
383 | pm_runtime_mark_last_busy(panel->dev); | |
384 | pm_runtime_put_autosuspend(panel->dev); | |
280921de TR |
385 | } |
386 | ||
387 | /* add hard-coded panel modes */ | |
0ce8ddd8 | 388 | num += panel_simple_get_non_edid_modes(p, connector); |
280921de | 389 | |
a960e35a HYW |
390 | /* |
391 | * TODO: Remove once all drm drivers call | |
392 | * drm_connector_set_orientation_from_panel() | |
393 | */ | |
5759c967 DO |
394 | drm_connector_set_panel_orientation(connector, p->orientation); |
395 | ||
280921de TR |
396 | return num; |
397 | } | |
398 | ||
a5d3e625 PZ |
399 | static int panel_simple_get_timings(struct drm_panel *panel, |
400 | unsigned int num_timings, | |
401 | struct display_timing *timings) | |
402 | { | |
403 | struct panel_simple *p = to_panel_simple(panel); | |
404 | unsigned int i; | |
405 | ||
406 | if (p->desc->num_timings < num_timings) | |
407 | num_timings = p->desc->num_timings; | |
408 | ||
409 | if (timings) | |
410 | for (i = 0; i < num_timings; i++) | |
411 | timings[i] = p->desc->timings[i]; | |
412 | ||
413 | return p->desc->num_timings; | |
414 | } | |
415 | ||
a960e35a HYW |
416 | static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) |
417 | { | |
418 | struct panel_simple *p = to_panel_simple(panel); | |
419 | ||
420 | return p->orientation; | |
421 | } | |
422 | ||
280921de TR |
423 | static const struct drm_panel_funcs panel_simple_funcs = { |
424 | .disable = panel_simple_disable, | |
c0e1d170 AK |
425 | .unprepare = panel_simple_unprepare, |
426 | .prepare = panel_simple_prepare, | |
280921de TR |
427 | .enable = panel_simple_enable, |
428 | .get_modes = panel_simple_get_modes, | |
a960e35a | 429 | .get_orientation = panel_simple_get_orientation, |
a5d3e625 | 430 | .get_timings = panel_simple_get_timings, |
280921de TR |
431 | }; |
432 | ||
4a1d0dbc SR |
433 | static struct panel_desc panel_dpi; |
434 | ||
435 | static int panel_dpi_probe(struct device *dev, | |
436 | struct panel_simple *panel) | |
437 | { | |
438 | struct display_timing *timing; | |
439 | const struct device_node *np; | |
440 | struct panel_desc *desc; | |
441 | unsigned int bus_flags; | |
442 | struct videomode vm; | |
4a1d0dbc SR |
443 | int ret; |
444 | ||
445 | np = dev->of_node; | |
446 | desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); | |
447 | if (!desc) | |
448 | return -ENOMEM; | |
449 | ||
450 | timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); | |
451 | if (!timing) | |
452 | return -ENOMEM; | |
453 | ||
454 | ret = of_get_display_timing(np, "panel-timing", timing); | |
455 | if (ret < 0) { | |
456 | dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", | |
457 | np); | |
458 | return ret; | |
459 | } | |
460 | ||
461 | desc->timings = timing; | |
462 | desc->num_timings = 1; | |
463 | ||
464 | of_property_read_u32(np, "width-mm", &desc->size.width); | |
465 | of_property_read_u32(np, "height-mm", &desc->size.height); | |
466 | ||
4a1d0dbc SR |
467 | /* Extract bus_flags from display_timing */ |
468 | bus_flags = 0; | |
469 | vm.flags = timing->flags; | |
470 | drm_bus_flags_from_videomode(&vm, &bus_flags); | |
471 | desc->bus_flags = bus_flags; | |
472 | ||
473 | /* We do not know the connector for the DT node, so guess it */ | |
474 | desc->connector_type = DRM_MODE_CONNECTOR_DPI; | |
475 | ||
476 | panel->desc = desc; | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
b8a2948f SP |
481 | #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ |
482 | (to_check->field.typ >= bounds->field.min && \ | |
483 | to_check->field.typ <= bounds->field.max) | |
e362cc6a DA |
484 | static void panel_simple_parse_panel_timing_node(struct device *dev, |
485 | struct panel_simple *panel, | |
486 | const struct display_timing *ot) | |
b8a2948f SP |
487 | { |
488 | const struct panel_desc *desc = panel->desc; | |
489 | struct videomode vm; | |
490 | unsigned int i; | |
491 | ||
492 | if (WARN_ON(desc->num_modes)) { | |
493 | dev_err(dev, "Reject override mode: panel has a fixed mode\n"); | |
494 | return; | |
495 | } | |
496 | if (WARN_ON(!desc->num_timings)) { | |
497 | dev_err(dev, "Reject override mode: no timings specified\n"); | |
498 | return; | |
499 | } | |
500 | ||
501 | for (i = 0; i < panel->desc->num_timings; i++) { | |
502 | const struct display_timing *dt = &panel->desc->timings[i]; | |
503 | ||
504 | if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || | |
505 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || | |
506 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || | |
507 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || | |
508 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || | |
509 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || | |
510 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || | |
511 | !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) | |
512 | continue; | |
513 | ||
514 | if (ot->flags != dt->flags) | |
515 | continue; | |
516 | ||
517 | videomode_from_timing(ot, &vm); | |
518 | drm_display_mode_from_videomode(&vm, &panel->override_mode); | |
519 | panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | | |
520 | DRM_MODE_TYPE_PREFERRED; | |
521 | break; | |
522 | } | |
523 | ||
524 | if (WARN_ON(!panel->override_mode.type)) | |
525 | dev_err(dev, "Reject override mode: No display_timing found\n"); | |
526 | } | |
527 | ||
1cd3ea3e JZ |
528 | static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, |
529 | struct panel_simple *panel) | |
530 | { | |
531 | int ret, bpc; | |
532 | ||
533 | ret = drm_of_lvds_get_data_mapping(dev->of_node); | |
534 | if (ret < 0) { | |
535 | if (ret == -EINVAL) | |
536 | dev_warn(dev, "Ignore invalid data-mapping property\n"); | |
537 | ||
538 | /* | |
539 | * Ignore non-existing or malformatted property, fallback to | |
540 | * default data-mapping, and return 0. | |
541 | */ | |
542 | return 0; | |
543 | } | |
544 | ||
545 | switch (ret) { | |
546 | default: | |
547 | WARN_ON(1); | |
548 | fallthrough; | |
549 | case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: | |
550 | fallthrough; | |
551 | case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: | |
552 | bpc = 8; | |
553 | break; | |
554 | case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: | |
555 | bpc = 6; | |
556 | } | |
557 | ||
558 | if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { | |
559 | struct panel_desc *override_desc; | |
560 | ||
561 | override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); | |
562 | if (!override_desc) | |
563 | return -ENOMEM; | |
564 | ||
565 | override_desc->bus_format = ret; | |
566 | override_desc->bpc = bpc; | |
567 | panel->desc = override_desc; | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
5f04e7ce | 573 | static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) |
280921de | 574 | { |
280921de | 575 | struct panel_simple *panel; |
b8a2948f | 576 | struct display_timing dt; |
0fe1564b | 577 | struct device_node *ddc; |
9f069c6f | 578 | int connector_type; |
ddb8e853 | 579 | u32 bus_flags; |
280921de TR |
580 | int err; |
581 | ||
582 | panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); | |
583 | if (!panel) | |
584 | return -ENOMEM; | |
585 | ||
280921de TR |
586 | panel->desc = desc; |
587 | ||
588 | panel->supply = devm_regulator_get(dev, "power"); | |
589 | if (IS_ERR(panel->supply)) | |
590 | return PTR_ERR(panel->supply); | |
591 | ||
a61400d8 AC |
592 | panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", |
593 | GPIOD_OUT_LOW); | |
c9b48b91 YC |
594 | if (IS_ERR(panel->enable_gpio)) |
595 | return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), | |
596 | "failed to request GPIO\n"); | |
280921de | 597 | |
5759c967 DO |
598 | err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); |
599 | if (err) { | |
600 | dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); | |
601 | return err; | |
602 | } | |
603 | ||
280921de TR |
604 | ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); |
605 | if (ddc) { | |
606 | panel->ddc = of_find_i2c_adapter_by_node(ddc); | |
607 | of_node_put(ddc); | |
608 | ||
0fe1564b SR |
609 | if (!panel->ddc) |
610 | return -EPROBE_DEFER; | |
280921de TR |
611 | } |
612 | ||
4a1d0dbc SR |
613 | if (desc == &panel_dpi) { |
614 | /* Handle the generic panel-dpi binding */ | |
615 | err = panel_dpi_probe(dev, panel); | |
616 | if (err) | |
617 | goto free_ddc; | |
6df4432a | 618 | desc = panel->desc; |
4a1d0dbc SR |
619 | } else { |
620 | if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) | |
621 | panel_simple_parse_panel_timing_node(dev, panel, &dt); | |
622 | } | |
b8a2948f | 623 | |
1cd3ea3e JZ |
624 | if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { |
625 | /* Optional data-mapping property for overriding bus format */ | |
626 | err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); | |
627 | if (err) | |
628 | goto free_ddc; | |
629 | } | |
630 | ||
9f069c6f | 631 | connector_type = desc->connector_type; |
ddb8e853 | 632 | /* Catch common mistakes for panels. */ |
9f069c6f | 633 | switch (connector_type) { |
ddb8e853 SR |
634 | case 0: |
635 | dev_warn(dev, "Specify missing connector_type\n"); | |
9f069c6f | 636 | connector_type = DRM_MODE_CONNECTOR_DPI; |
ddb8e853 SR |
637 | break; |
638 | case DRM_MODE_CONNECTOR_LVDS: | |
c4715837 LP |
639 | WARN_ON(desc->bus_flags & |
640 | ~(DRM_BUS_FLAG_DE_LOW | | |
641 | DRM_BUS_FLAG_DE_HIGH | | |
642 | DRM_BUS_FLAG_DATA_MSB_TO_LSB | | |
643 | DRM_BUS_FLAG_DATA_LSB_TO_MSB)); | |
1185c406 LP |
644 | WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && |
645 | desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && | |
646 | desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); | |
647 | WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && | |
648 | desc->bpc != 6); | |
649 | WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || | |
650 | desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && | |
651 | desc->bpc != 8); | |
ddb8e853 SR |
652 | break; |
653 | case DRM_MODE_CONNECTOR_eDP: | |
5f04e7ce DA |
654 | dev_warn(dev, "eDP panels moved to panel-edp\n"); |
655 | err = -EINVAL; | |
656 | goto free_ddc; | |
ddb8e853 SR |
657 | case DRM_MODE_CONNECTOR_DSI: |
658 | if (desc->bpc != 6 && desc->bpc != 8) | |
659 | dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); | |
660 | break; | |
661 | case DRM_MODE_CONNECTOR_DPI: | |
662 | bus_flags = DRM_BUS_FLAG_DE_LOW | | |
663 | DRM_BUS_FLAG_DE_HIGH | | |
664 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | | |
665 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
666 | DRM_BUS_FLAG_DATA_MSB_TO_LSB | | |
667 | DRM_BUS_FLAG_DATA_LSB_TO_MSB | | |
668 | DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | | |
669 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; | |
670 | if (desc->bus_flags & ~bus_flags) | |
671 | dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); | |
672 | if (!(desc->bus_flags & bus_flags)) | |
673 | dev_warn(dev, "Specify missing bus_flags\n"); | |
674 | if (desc->bus_format == 0) | |
675 | dev_warn(dev, "Specify missing bus_format\n"); | |
676 | if (desc->bpc != 6 && desc->bpc != 8) | |
677 | dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); | |
678 | break; | |
679 | default: | |
680 | dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); | |
9f069c6f | 681 | connector_type = DRM_MODE_CONNECTOR_DPI; |
ddb8e853 | 682 | break; |
1185c406 | 683 | } |
c4715837 | 684 | |
3235b0f2 DA |
685 | dev_set_drvdata(dev, panel); |
686 | ||
687 | /* | |
688 | * We use runtime PM for prepare / unprepare since those power the panel | |
689 | * on and off and those can be very slow operations. This is important | |
690 | * to optimize powering the panel on briefly to read the EDID before | |
691 | * fully enabling the panel. | |
692 | */ | |
693 | pm_runtime_enable(dev); | |
694 | pm_runtime_set_autosuspend_delay(dev, 1000); | |
695 | pm_runtime_use_autosuspend(dev); | |
696 | ||
9f069c6f | 697 | drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); |
280921de | 698 | |
0fe1564b | 699 | err = drm_panel_of_backlight(&panel->base); |
d9e74da2 AS |
700 | if (err) { |
701 | dev_err_probe(dev, err, "Could not find backlight\n"); | |
70e12560 | 702 | goto disable_pm_runtime; |
d9e74da2 | 703 | } |
0fe1564b | 704 | |
c3ee8c65 | 705 | drm_panel_add(&panel->base); |
280921de | 706 | |
280921de TR |
707 | return 0; |
708 | ||
70e12560 | 709 | disable_pm_runtime: |
a596fcd9 | 710 | pm_runtime_dont_use_autosuspend(dev); |
70e12560 | 711 | pm_runtime_disable(dev); |
280921de | 712 | free_ddc: |
5f04e7ce | 713 | if (panel->ddc) |
280921de | 714 | put_device(&panel->ddc->dev); |
280921de TR |
715 | |
716 | return err; | |
717 | } | |
718 | ||
bc62654d | 719 | static void panel_simple_shutdown(struct device *dev) |
280921de TR |
720 | { |
721 | struct panel_simple *panel = dev_get_drvdata(dev); | |
722 | ||
bc62654d DA |
723 | /* |
724 | * NOTE: the following two calls don't really belong here. It is the | |
725 | * responsibility of a correctly written DRM modeset driver to call | |
726 | * drm_atomic_helper_shutdown() at shutdown time and that should | |
727 | * cause the panel to be disabled / unprepared if needed. For now, | |
728 | * however, we'll keep these calls due to the sheer number of | |
f00bfaca DA |
729 | * different DRM modeset drivers used with panel-simple. Once we've |
730 | * confirmed that all DRM modeset drivers using this panel properly | |
731 | * call drm_atomic_helper_shutdown() we can simply delete the two | |
732 | * calls below. | |
733 | * | |
734 | * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW | |
735 | * PANEL DRIVERS. | |
736 | * | |
737 | * FIXME: If we're still haven't figured out if all DRM modeset | |
738 | * drivers properly call drm_atomic_helper_shutdown() but we _have_ | |
739 | * managed to make sure that DRM modeset drivers get their shutdown() | |
740 | * callback before the panel's shutdown() callback (perhaps using | |
741 | * device link), we could add a WARN_ON here to help move forward. | |
bc62654d | 742 | */ |
f00bfaca DA |
743 | if (panel->base.enabled) |
744 | drm_panel_disable(&panel->base); | |
745 | if (panel->base.prepared) | |
746 | drm_panel_unprepare(&panel->base); | |
280921de TR |
747 | } |
748 | ||
bc62654d | 749 | static void panel_simple_remove(struct device *dev) |
d02fd93e TR |
750 | { |
751 | struct panel_simple *panel = dev_get_drvdata(dev); | |
752 | ||
bc62654d DA |
753 | drm_panel_remove(&panel->base); |
754 | panel_simple_shutdown(dev); | |
755 | ||
756 | pm_runtime_dont_use_autosuspend(dev); | |
757 | pm_runtime_disable(dev); | |
758 | if (panel->ddc) | |
759 | put_device(&panel->ddc->dev); | |
d02fd93e TR |
760 | } |
761 | ||
bca684e6 JT |
762 | static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { |
763 | .clock = 71100, | |
764 | .hdisplay = 1280, | |
765 | .hsync_start = 1280 + 40, | |
766 | .hsync_end = 1280 + 40 + 80, | |
767 | .htotal = 1280 + 40 + 80 + 40, | |
768 | .vdisplay = 800, | |
769 | .vsync_start = 800 + 3, | |
770 | .vsync_end = 800 + 3 + 10, | |
771 | .vtotal = 800 + 3 + 10 + 10, | |
772 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, | |
773 | }; | |
774 | ||
775 | static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { | |
776 | .modes = &ire_am_1280800n3tzqw_t00h_mode, | |
777 | .num_modes = 1, | |
7eafbecd | 778 | .bpc = 8, |
bca684e6 JT |
779 | .size = { |
780 | .width = 217, | |
781 | .height = 136, | |
782 | }, | |
783 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
784 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
785 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
786 | }; | |
787 | ||
966fea78 YF |
788 | static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { |
789 | .clock = 9000, | |
790 | .hdisplay = 480, | |
791 | .hsync_start = 480 + 2, | |
792 | .hsync_end = 480 + 2 + 41, | |
793 | .htotal = 480 + 2 + 41 + 2, | |
794 | .vdisplay = 272, | |
795 | .vsync_start = 272 + 2, | |
796 | .vsync_end = 272 + 2 + 10, | |
797 | .vtotal = 272 + 2 + 10 + 2, | |
966fea78 YF |
798 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
799 | }; | |
800 | ||
801 | static const struct panel_desc ampire_am_480272h3tmqw_t01h = { | |
802 | .modes = &ire_am_480272h3tmqw_t01h_mode, | |
803 | .num_modes = 1, | |
804 | .bpc = 8, | |
805 | .size = { | |
f24b4955 DB |
806 | .width = 99, |
807 | .height = 58, | |
966fea78 YF |
808 | }, |
809 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
810 | }; | |
811 | ||
1c550fa1 PZ |
812 | static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { |
813 | .clock = 33333, | |
814 | .hdisplay = 800, | |
815 | .hsync_start = 800 + 0, | |
816 | .hsync_end = 800 + 0 + 255, | |
817 | .htotal = 800 + 0 + 255 + 0, | |
818 | .vdisplay = 480, | |
819 | .vsync_start = 480 + 2, | |
820 | .vsync_end = 480 + 2 + 45, | |
821 | .vtotal = 480 + 2 + 45 + 0, | |
1c550fa1 PZ |
822 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
823 | }; | |
824 | ||
410bb213 GU |
825 | static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { |
826 | .pixelclock = { 29930000, 33260000, 36590000 }, | |
827 | .hactive = { 800, 800, 800 }, | |
828 | .hfront_porch = { 1, 40, 168 }, | |
829 | .hback_porch = { 88, 88, 88 }, | |
830 | .hsync_len = { 1, 128, 128 }, | |
831 | .vactive = { 480, 480, 480 }, | |
832 | .vfront_porch = { 1, 35, 37 }, | |
833 | .vback_porch = { 8, 8, 8 }, | |
834 | .vsync_len = { 1, 2, 2 }, | |
835 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
836 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
837 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
838 | }; | |
839 | ||
840 | static const struct panel_desc ampire_am_800480l1tmqw_t00h = { | |
841 | .timings = &ire_am_800480l1tmqw_t00h_timing, | |
842 | .num_timings = 1, | |
843 | .bpc = 8, | |
844 | .size = { | |
845 | .width = 111, | |
846 | .height = 67, | |
847 | }, | |
848 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
849 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
850 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
851 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
852 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
853 | }; | |
854 | ||
1c550fa1 PZ |
855 | static const struct panel_desc ampire_am800480r3tmqwa1h = { |
856 | .modes = &ire_am800480r3tmqwa1h_mode, | |
857 | .num_modes = 1, | |
858 | .bpc = 6, | |
859 | .size = { | |
860 | .width = 152, | |
861 | .height = 91, | |
862 | }, | |
863 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
864 | }; | |
865 | ||
103f06fd BK |
866 | static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { |
867 | .pixelclock = { 34500000, 39600000, 50400000 }, | |
868 | .hactive = { 800, 800, 800 }, | |
869 | .hfront_porch = { 12, 112, 312 }, | |
870 | .hback_porch = { 87, 87, 48 }, | |
871 | .hsync_len = { 1, 1, 40 }, | |
872 | .vactive = { 600, 600, 600 }, | |
873 | .vfront_porch = { 1, 21, 61 }, | |
874 | .vback_porch = { 38, 38, 19 }, | |
875 | .vsync_len = { 1, 1, 20 }, | |
876 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
877 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
878 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
879 | }; | |
880 | ||
881 | static const struct panel_desc ampire_am800600p5tmqwtb8h = { | |
882 | .timings = &ire_am800600p5tmqw_tb8h_timing, | |
883 | .num_timings = 1, | |
884 | .bpc = 6, | |
885 | .size = { | |
886 | .width = 162, | |
887 | .height = 122, | |
888 | }, | |
889 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
890 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
891 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
892 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
893 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
894 | }; | |
895 | ||
c479450f SS |
896 | static const struct display_timing santek_st0700i5y_rbslw_f_timing = { |
897 | .pixelclock = { 26400000, 33300000, 46800000 }, | |
898 | .hactive = { 800, 800, 800 }, | |
899 | .hfront_porch = { 16, 210, 354 }, | |
900 | .hback_porch = { 45, 36, 6 }, | |
901 | .hsync_len = { 1, 10, 40 }, | |
902 | .vactive = { 480, 480, 480 }, | |
903 | .vfront_porch = { 7, 22, 147 }, | |
904 | .vback_porch = { 22, 13, 3 }, | |
905 | .vsync_len = { 1, 10, 20 }, | |
906 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
907 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
908 | }; | |
909 | ||
910 | static const struct panel_desc armadeus_st0700_adapt = { | |
911 | .timings = &santek_st0700i5y_rbslw_f_timing, | |
912 | .num_timings = 1, | |
913 | .bpc = 6, | |
914 | .size = { | |
915 | .width = 154, | |
916 | .height = 86, | |
917 | }, | |
918 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
f5436f77 | 919 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
c479450f SS |
920 | }; |
921 | ||
280921de TR |
922 | static const struct drm_display_mode auo_b101aw03_mode = { |
923 | .clock = 51450, | |
924 | .hdisplay = 1024, | |
925 | .hsync_start = 1024 + 156, | |
926 | .hsync_end = 1024 + 156 + 8, | |
927 | .htotal = 1024 + 156 + 8 + 156, | |
928 | .vdisplay = 600, | |
929 | .vsync_start = 600 + 16, | |
930 | .vsync_end = 600 + 16 + 6, | |
931 | .vtotal = 600 + 16 + 6 + 16, | |
280921de TR |
932 | }; |
933 | ||
934 | static const struct panel_desc auo_b101aw03 = { | |
935 | .modes = &auo_b101aw03_mode, | |
936 | .num_modes = 1, | |
0208d511 | 937 | .bpc = 6, |
280921de TR |
938 | .size = { |
939 | .width = 223, | |
940 | .height = 125, | |
941 | }, | |
85560829 | 942 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c4715837 | 943 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
94f07917 | 944 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
280921de TR |
945 | }; |
946 | ||
dac746e0 RC |
947 | static const struct drm_display_mode auo_b101xtn01_mode = { |
948 | .clock = 72000, | |
949 | .hdisplay = 1366, | |
950 | .hsync_start = 1366 + 20, | |
951 | .hsync_end = 1366 + 20 + 70, | |
952 | .htotal = 1366 + 20 + 70, | |
953 | .vdisplay = 768, | |
954 | .vsync_start = 768 + 14, | |
955 | .vsync_end = 768 + 14 + 42, | |
956 | .vtotal = 768 + 14 + 42, | |
dac746e0 RC |
957 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
958 | }; | |
959 | ||
960 | static const struct panel_desc auo_b101xtn01 = { | |
961 | .modes = &auo_b101xtn01_mode, | |
962 | .num_modes = 1, | |
963 | .bpc = 6, | |
964 | .size = { | |
965 | .width = 223, | |
966 | .height = 125, | |
967 | }, | |
968 | }; | |
969 | ||
ad3e33fe DA |
970 | static const struct drm_display_mode auo_b116xw03_mode = { |
971 | .clock = 70589, | |
972 | .hdisplay = 1366, | |
973 | .hsync_start = 1366 + 40, | |
974 | .hsync_end = 1366 + 40 + 40, | |
975 | .htotal = 1366 + 40 + 40 + 32, | |
976 | .vdisplay = 768, | |
977 | .vsync_start = 768 + 10, | |
978 | .vsync_end = 768 + 10 + 12, | |
979 | .vtotal = 768 + 10 + 12 + 6, | |
980 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
981 | }; | |
982 | ||
983 | static const struct panel_desc auo_b116xw03 = { | |
984 | .modes = &auo_b116xw03_mode, | |
985 | .num_modes = 1, | |
986 | .bpc = 6, | |
987 | .size = { | |
988 | .width = 256, | |
989 | .height = 144, | |
990 | }, | |
991 | .delay = { | |
992 | .prepare = 1, | |
993 | .enable = 200, | |
994 | .disable = 200, | |
995 | .unprepare = 500, | |
996 | }, | |
997 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
998 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
999 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1000 | }; | |
1001 | ||
bccfaffb LM |
1002 | static const struct display_timing auo_g070vvn01_timings = { |
1003 | .pixelclock = { 33300000, 34209000, 45000000 }, | |
1004 | .hactive = { 800, 800, 800 }, | |
1005 | .hfront_porch = { 20, 40, 200 }, | |
1006 | .hback_porch = { 87, 40, 1 }, | |
1007 | .hsync_len = { 1, 48, 87 }, | |
1008 | .vactive = { 480, 480, 480 }, | |
1009 | .vfront_porch = { 5, 13, 200 }, | |
1010 | .vback_porch = { 31, 31, 29 }, | |
1011 | .vsync_len = { 1, 1, 3 }, | |
1012 | }; | |
1013 | ||
1014 | static const struct panel_desc auo_g070vvn01 = { | |
1015 | .timings = &auo_g070vvn01_timings, | |
1016 | .num_timings = 1, | |
1017 | .bpc = 8, | |
1018 | .size = { | |
1019 | .width = 152, | |
1020 | .height = 91, | |
1021 | }, | |
1022 | .delay = { | |
1023 | .prepare = 200, | |
1024 | .enable = 50, | |
1025 | .disable = 50, | |
1026 | .unprepare = 1000, | |
1027 | }, | |
1028 | }; | |
1029 | ||
4fb86404 AG |
1030 | static const struct drm_display_mode auo_g101evn010_mode = { |
1031 | .clock = 68930, | |
1032 | .hdisplay = 1280, | |
1033 | .hsync_start = 1280 + 82, | |
1034 | .hsync_end = 1280 + 82 + 2, | |
1035 | .htotal = 1280 + 82 + 2 + 84, | |
1036 | .vdisplay = 800, | |
1037 | .vsync_start = 800 + 8, | |
1038 | .vsync_end = 800 + 8 + 2, | |
1039 | .vtotal = 800 + 8 + 2 + 6, | |
4fb86404 AG |
1040 | }; |
1041 | ||
1042 | static const struct panel_desc auo_g101evn010 = { | |
1043 | .modes = &auo_g101evn010_mode, | |
1044 | .num_modes = 1, | |
1045 | .bpc = 6, | |
1046 | .size = { | |
1047 | .width = 216, | |
1048 | .height = 135, | |
1049 | }, | |
27a46fb7 TV |
1050 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
1051 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
4fb86404 AG |
1052 | }; |
1053 | ||
4451c287 CF |
1054 | static const struct drm_display_mode auo_g104sn02_mode = { |
1055 | .clock = 40000, | |
1056 | .hdisplay = 800, | |
1057 | .hsync_start = 800 + 40, | |
1058 | .hsync_end = 800 + 40 + 216, | |
1059 | .htotal = 800 + 40 + 216 + 128, | |
1060 | .vdisplay = 600, | |
1061 | .vsync_start = 600 + 10, | |
1062 | .vsync_end = 600 + 10 + 35, | |
1063 | .vtotal = 600 + 10 + 35 + 2, | |
4451c287 CF |
1064 | }; |
1065 | ||
1066 | static const struct panel_desc auo_g104sn02 = { | |
1067 | .modes = &auo_g104sn02_mode, | |
1068 | .num_modes = 1, | |
1069 | .bpc = 8, | |
1070 | .size = { | |
1071 | .width = 211, | |
1072 | .height = 158, | |
1073 | }, | |
a3050f23 SR |
1074 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1075 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
4451c287 CF |
1076 | }; |
1077 | ||
6c2b2cd3 PG |
1078 | static const struct drm_display_mode auo_g104stn01_mode = { |
1079 | .clock = 40000, | |
1080 | .hdisplay = 800, | |
1081 | .hsync_start = 800 + 40, | |
1082 | .hsync_end = 800 + 40 + 88, | |
1083 | .htotal = 800 + 40 + 88 + 128, | |
1084 | .vdisplay = 600, | |
1085 | .vsync_start = 600 + 1, | |
1086 | .vsync_end = 600 + 1 + 23, | |
1087 | .vtotal = 600 + 1 + 23 + 4, | |
1088 | }; | |
1089 | ||
1090 | static const struct panel_desc auo_g104stn01 = { | |
1091 | .modes = &auo_g104stn01_mode, | |
1092 | .num_modes = 1, | |
1093 | .bpc = 8, | |
1094 | .size = { | |
1095 | .width = 211, | |
1096 | .height = 158, | |
1097 | }, | |
1098 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1099 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1100 | }; | |
1101 | ||
e8470c0a LC |
1102 | static const struct display_timing auo_g121ean01_timing = { |
1103 | .pixelclock = { 60000000, 74400000, 90000000 }, | |
1104 | .hactive = { 1280, 1280, 1280 }, | |
1105 | .hfront_porch = { 20, 50, 100 }, | |
1106 | .hback_porch = { 20, 50, 100 }, | |
1107 | .hsync_len = { 30, 100, 200 }, | |
1108 | .vactive = { 800, 800, 800 }, | |
1109 | .vfront_porch = { 2, 10, 25 }, | |
1110 | .vback_porch = { 2, 10, 25 }, | |
1111 | .vsync_len = { 4, 18, 50 }, | |
03e909ac SR |
1112 | }; |
1113 | ||
1114 | static const struct panel_desc auo_g121ean01 = { | |
e8470c0a LC |
1115 | .timings = &auo_g121ean01_timing, |
1116 | .num_timings = 1, | |
03e909ac SR |
1117 | .bpc = 8, |
1118 | .size = { | |
1119 | .width = 261, | |
1120 | .height = 163, | |
1121 | }, | |
1122 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1123 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1124 | }; | |
1125 | ||
697035c6 LS |
1126 | static const struct display_timing auo_g133han01_timings = { |
1127 | .pixelclock = { 134000000, 141200000, 149000000 }, | |
1128 | .hactive = { 1920, 1920, 1920 }, | |
1129 | .hfront_porch = { 39, 58, 77 }, | |
1130 | .hback_porch = { 59, 88, 117 }, | |
1131 | .hsync_len = { 28, 42, 56 }, | |
1132 | .vactive = { 1080, 1080, 1080 }, | |
1133 | .vfront_porch = { 3, 8, 11 }, | |
1134 | .vback_porch = { 5, 14, 19 }, | |
1135 | .vsync_len = { 4, 14, 19 }, | |
1136 | }; | |
1137 | ||
1138 | static const struct panel_desc auo_g133han01 = { | |
1139 | .timings = &auo_g133han01_timings, | |
1140 | .num_timings = 1, | |
1141 | .bpc = 8, | |
1142 | .size = { | |
1143 | .width = 293, | |
1144 | .height = 165, | |
1145 | }, | |
1146 | .delay = { | |
1147 | .prepare = 200, | |
1148 | .enable = 50, | |
1149 | .disable = 50, | |
1150 | .unprepare = 1000, | |
1151 | }, | |
1152 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, | |
9a2654c0 | 1153 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
697035c6 LS |
1154 | }; |
1155 | ||
9e52d5c8 EA |
1156 | static const struct display_timing auo_g156han04_timings = { |
1157 | .pixelclock = { 137000000, 141000000, 146000000 }, | |
1158 | .hactive = { 1920, 1920, 1920 }, | |
1159 | .hfront_porch = { 60, 60, 60 }, | |
1160 | .hback_porch = { 90, 92, 111 }, | |
1161 | .hsync_len = { 32, 32, 32 }, | |
1162 | .vactive = { 1080, 1080, 1080 }, | |
1163 | .vfront_porch = { 12, 12, 12 }, | |
1164 | .vback_porch = { 24, 36, 56 }, | |
1165 | .vsync_len = { 8, 8, 8 }, | |
1166 | }; | |
1167 | ||
1168 | static const struct panel_desc auo_g156han04 = { | |
1169 | .timings = &auo_g156han04_timings, | |
1170 | .num_timings = 1, | |
1171 | .bpc = 8, | |
1172 | .size = { | |
1173 | .width = 344, | |
1174 | .height = 194, | |
1175 | }, | |
1176 | .delay = { | |
1177 | .prepare = 50, /* T2 */ | |
1178 | .enable = 200, /* T3 */ | |
1179 | .disable = 110, /* T10 */ | |
1180 | .unprepare = 1000, /* T13 */ | |
1181 | }, | |
1182 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1183 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
1184 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1185 | }; | |
1186 | ||
d9ccd1f2 SR |
1187 | static const struct drm_display_mode auo_g156xtn01_mode = { |
1188 | .clock = 76000, | |
1189 | .hdisplay = 1366, | |
1190 | .hsync_start = 1366 + 33, | |
1191 | .hsync_end = 1366 + 33 + 67, | |
1192 | .htotal = 1560, | |
1193 | .vdisplay = 768, | |
1194 | .vsync_start = 768 + 4, | |
1195 | .vsync_end = 768 + 4 + 4, | |
1196 | .vtotal = 806, | |
d9ccd1f2 SR |
1197 | }; |
1198 | ||
1199 | static const struct panel_desc auo_g156xtn01 = { | |
1200 | .modes = &auo_g156xtn01_mode, | |
1201 | .num_modes = 1, | |
1202 | .bpc = 8, | |
1203 | .size = { | |
1204 | .width = 344, | |
1205 | .height = 194, | |
1206 | }, | |
1207 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1208 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1209 | }; | |
1210 | ||
8c31f603 LS |
1211 | static const struct display_timing auo_g185han01_timings = { |
1212 | .pixelclock = { 120000000, 144000000, 175000000 }, | |
1213 | .hactive = { 1920, 1920, 1920 }, | |
f8c6bfc6 LS |
1214 | .hfront_porch = { 36, 120, 148 }, |
1215 | .hback_porch = { 24, 88, 108 }, | |
1216 | .hsync_len = { 20, 48, 64 }, | |
8c31f603 LS |
1217 | .vactive = { 1080, 1080, 1080 }, |
1218 | .vfront_porch = { 6, 10, 40 }, | |
1219 | .vback_porch = { 2, 5, 20 }, | |
1220 | .vsync_len = { 2, 5, 20 }, | |
1221 | }; | |
1222 | ||
1223 | static const struct panel_desc auo_g185han01 = { | |
1224 | .timings = &auo_g185han01_timings, | |
1225 | .num_timings = 1, | |
1226 | .bpc = 8, | |
1227 | .size = { | |
1228 | .width = 409, | |
1229 | .height = 230, | |
1230 | }, | |
1231 | .delay = { | |
1232 | .prepare = 50, | |
1233 | .enable = 200, | |
1234 | .disable = 110, | |
1235 | .unprepare = 1000, | |
1236 | }, | |
1237 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 1238 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
8c31f603 LS |
1239 | }; |
1240 | ||
2f7b832f SR |
1241 | static const struct display_timing auo_g190ean01_timings = { |
1242 | .pixelclock = { 90000000, 108000000, 135000000 }, | |
1243 | .hactive = { 1280, 1280, 1280 }, | |
1244 | .hfront_porch = { 126, 184, 1266 }, | |
1245 | .hback_porch = { 84, 122, 844 }, | |
1246 | .hsync_len = { 70, 102, 704 }, | |
1247 | .vactive = { 1024, 1024, 1024 }, | |
1248 | .vfront_porch = { 4, 26, 76 }, | |
1249 | .vback_porch = { 2, 8, 25 }, | |
1250 | .vsync_len = { 2, 8, 25 }, | |
1251 | }; | |
1252 | ||
1253 | static const struct panel_desc auo_g190ean01 = { | |
1254 | .timings = &auo_g190ean01_timings, | |
1255 | .num_timings = 1, | |
1256 | .bpc = 8, | |
1257 | .size = { | |
1258 | .width = 376, | |
1259 | .height = 301, | |
1260 | }, | |
1261 | .delay = { | |
1262 | .prepare = 50, | |
1263 | .enable = 200, | |
1264 | .disable = 110, | |
1265 | .unprepare = 1000, | |
1266 | }, | |
1267 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1268 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1269 | }; | |
1270 | ||
70c0d5b7 LS |
1271 | static const struct display_timing auo_p320hvn03_timings = { |
1272 | .pixelclock = { 106000000, 148500000, 164000000 }, | |
1273 | .hactive = { 1920, 1920, 1920 }, | |
1274 | .hfront_porch = { 25, 50, 130 }, | |
1275 | .hback_porch = { 25, 50, 130 }, | |
1276 | .hsync_len = { 20, 40, 105 }, | |
1277 | .vactive = { 1080, 1080, 1080 }, | |
1278 | .vfront_porch = { 8, 17, 150 }, | |
1279 | .vback_porch = { 8, 17, 150 }, | |
1280 | .vsync_len = { 4, 11, 100 }, | |
1281 | }; | |
1282 | ||
1283 | static const struct panel_desc auo_p320hvn03 = { | |
1284 | .timings = &auo_p320hvn03_timings, | |
1285 | .num_timings = 1, | |
1286 | .bpc = 8, | |
1287 | .size = { | |
1288 | .width = 698, | |
1289 | .height = 393, | |
1290 | }, | |
1291 | .delay = { | |
1292 | .prepare = 1, | |
1293 | .enable = 450, | |
1294 | .unprepare = 500, | |
1295 | }, | |
2554f154 | 1296 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
9a2654c0 | 1297 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
70c0d5b7 LS |
1298 | }; |
1299 | ||
7ee933a1 HS |
1300 | static const struct drm_display_mode auo_t215hvn01_mode = { |
1301 | .clock = 148800, | |
1302 | .hdisplay = 1920, | |
1303 | .hsync_start = 1920 + 88, | |
1304 | .hsync_end = 1920 + 88 + 44, | |
1305 | .htotal = 1920 + 88 + 44 + 148, | |
1306 | .vdisplay = 1080, | |
1307 | .vsync_start = 1080 + 4, | |
1308 | .vsync_end = 1080 + 4 + 5, | |
1309 | .vtotal = 1080 + 4 + 5 + 36, | |
7ee933a1 HS |
1310 | }; |
1311 | ||
1312 | static const struct panel_desc auo_t215hvn01 = { | |
1313 | .modes = &auo_t215hvn01_mode, | |
1314 | .num_modes = 1, | |
1315 | .bpc = 8, | |
1316 | .size = { | |
1317 | .width = 430, | |
1318 | .height = 270, | |
1319 | }, | |
1320 | .delay = { | |
1321 | .disable = 5, | |
1322 | .unprepare = 1000, | |
7a675a8f MV |
1323 | }, |
1324 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1325 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
7ee933a1 HS |
1326 | }; |
1327 | ||
d47df633 PZ |
1328 | static const struct drm_display_mode avic_tm070ddh03_mode = { |
1329 | .clock = 51200, | |
1330 | .hdisplay = 1024, | |
1331 | .hsync_start = 1024 + 160, | |
1332 | .hsync_end = 1024 + 160 + 4, | |
1333 | .htotal = 1024 + 160 + 4 + 156, | |
1334 | .vdisplay = 600, | |
1335 | .vsync_start = 600 + 17, | |
1336 | .vsync_end = 600 + 17 + 1, | |
1337 | .vtotal = 600 + 17 + 1 + 17, | |
d47df633 PZ |
1338 | }; |
1339 | ||
1340 | static const struct panel_desc avic_tm070ddh03 = { | |
1341 | .modes = &avic_tm070ddh03_mode, | |
1342 | .num_modes = 1, | |
1343 | .bpc = 8, | |
1344 | .size = { | |
1345 | .width = 154, | |
1346 | .height = 90, | |
1347 | }, | |
1348 | .delay = { | |
1349 | .prepare = 20, | |
1350 | .enable = 200, | |
1351 | .disable = 200, | |
1352 | }, | |
1353 | }; | |
1354 | ||
7ad8b41c CYT |
1355 | static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { |
1356 | .clock = 30000, | |
1357 | .hdisplay = 800, | |
1358 | .hsync_start = 800 + 40, | |
1359 | .hsync_end = 800 + 40 + 48, | |
1360 | .htotal = 800 + 40 + 48 + 40, | |
1361 | .vdisplay = 480, | |
1362 | .vsync_start = 480 + 13, | |
1363 | .vsync_end = 480 + 13 + 3, | |
1364 | .vtotal = 480 + 13 + 3 + 29, | |
1365 | }; | |
1366 | ||
1367 | static const struct panel_desc bananapi_s070wv20_ct16 = { | |
1368 | .modes = &bananapi_s070wv20_ct16_mode, | |
1369 | .num_modes = 1, | |
1370 | .bpc = 6, | |
1371 | .size = { | |
1372 | .width = 154, | |
1373 | .height = 86, | |
1374 | }, | |
1375 | }; | |
1376 | ||
eeaddab4 TL |
1377 | static const struct drm_display_mode boe_bp101wx1_100_mode = { |
1378 | .clock = 78945, | |
1379 | .hdisplay = 1280, | |
1380 | .hsync_start = 1280 + 0, | |
1381 | .hsync_end = 1280 + 0 + 2, | |
1382 | .htotal = 1280 + 62 + 0 + 2, | |
1383 | .vdisplay = 800, | |
1384 | .vsync_start = 800 + 8, | |
1385 | .vsync_end = 800 + 8 + 2, | |
1386 | .vtotal = 800 + 6 + 8 + 2, | |
1387 | }; | |
1388 | ||
dc90214f TL |
1389 | static const struct panel_desc boe_bp082wx1_100 = { |
1390 | .modes = &boe_bp101wx1_100_mode, | |
1391 | .num_modes = 1, | |
1392 | .bpc = 8, | |
1393 | .size = { | |
1394 | .width = 177, | |
1395 | .height = 110, | |
1396 | }, | |
1397 | .delay = { | |
1398 | .enable = 50, | |
1399 | .disable = 50, | |
1400 | }, | |
1401 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, | |
1402 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
1403 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1404 | }; | |
1405 | ||
eeaddab4 TL |
1406 | static const struct panel_desc boe_bp101wx1_100 = { |
1407 | .modes = &boe_bp101wx1_100_mode, | |
1408 | .num_modes = 1, | |
1409 | .bpc = 8, | |
1410 | .size = { | |
1411 | .width = 217, | |
1412 | .height = 136, | |
1413 | }, | |
1414 | .delay = { | |
1415 | .enable = 50, | |
1416 | .disable = 50, | |
1417 | }, | |
1418 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, | |
1419 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
1420 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1421 | }; | |
1422 | ||
8bb7c7bc LY |
1423 | static const struct display_timing boe_ev121wxm_n10_1850_timing = { |
1424 | .pixelclock = { 69922000, 71000000, 72293000 }, | |
1425 | .hactive = { 1280, 1280, 1280 }, | |
1426 | .hfront_porch = { 48, 48, 48 }, | |
1427 | .hback_porch = { 80, 80, 80 }, | |
1428 | .hsync_len = { 32, 32, 32 }, | |
1429 | .vactive = { 800, 800, 800 }, | |
1430 | .vfront_porch = { 3, 3, 3 }, | |
1431 | .vback_porch = { 14, 14, 14 }, | |
1432 | .vsync_len = { 6, 6, 6 }, | |
1433 | }; | |
1434 | ||
1435 | static const struct panel_desc boe_ev121wxm_n10_1850 = { | |
1436 | .timings = &boe_ev121wxm_n10_1850_timing, | |
1437 | .num_timings = 1, | |
1438 | .bpc = 8, | |
1439 | .size = { | |
1440 | .width = 261, | |
1441 | .height = 163, | |
1442 | }, | |
1443 | .delay = { | |
1444 | .prepare = 9, | |
1445 | .enable = 300, | |
1446 | .unprepare = 300, | |
1447 | .disable = 560, | |
1448 | }, | |
1449 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1450 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
1451 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1452 | }; | |
1453 | ||
ae8cf41b | 1454 | static const struct drm_display_mode boe_hv070wsa_mode = { |
e077e2f5 | 1455 | .clock = 42105, |
ae8cf41b | 1456 | .hdisplay = 1024, |
e077e2f5 AH |
1457 | .hsync_start = 1024 + 30, |
1458 | .hsync_end = 1024 + 30 + 30, | |
1459 | .htotal = 1024 + 30 + 30 + 30, | |
ae8cf41b | 1460 | .vdisplay = 600, |
e077e2f5 AH |
1461 | .vsync_start = 600 + 10, |
1462 | .vsync_end = 600 + 10 + 10, | |
1463 | .vtotal = 600 + 10 + 10 + 10, | |
ae8cf41b AH |
1464 | }; |
1465 | ||
1466 | static const struct panel_desc boe_hv070wsa = { | |
1467 | .modes = &boe_hv070wsa_mode, | |
1468 | .num_modes = 1, | |
2a5c2ff5 | 1469 | .bpc = 8, |
ae8cf41b AH |
1470 | .size = { |
1471 | .width = 154, | |
1472 | .height = 90, | |
1473 | }, | |
2a5c2ff5 SR |
1474 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
1475 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
1476 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
ae8cf41b AH |
1477 | }; |
1478 | ||
751b5841 JD |
1479 | static const struct display_timing cct_cmt430b19n00_timing = { |
1480 | .pixelclock = { 8000000, 9000000, 12000000 }, | |
1481 | .hactive = { 480, 480, 480 }, | |
1482 | .hfront_porch = { 2, 8, 75 }, | |
1483 | .hback_porch = { 3, 43, 43 }, | |
1484 | .hsync_len = { 2, 4, 75 }, | |
1485 | .vactive = { 272, 272, 272 }, | |
1486 | .vfront_porch = { 2, 8, 37 }, | |
1487 | .vback_porch = { 2, 12, 12 }, | |
1488 | .vsync_len = { 2, 4, 37 }, | |
1489 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | |
1490 | }; | |
1491 | ||
1492 | static const struct panel_desc cct_cmt430b19n00 = { | |
1493 | .timings = &cct_cmt430b19n00_timing, | |
1494 | .num_timings = 1, | |
1495 | .bpc = 8, | |
1496 | .size = { | |
1497 | .width = 95, | |
1498 | .height = 53, | |
1499 | }, | |
1500 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
1501 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, | |
1502 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
1503 | }; | |
1504 | ||
e58edce6 GB |
1505 | static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { |
1506 | .clock = 9000, | |
1507 | .hdisplay = 480, | |
1508 | .hsync_start = 480 + 5, | |
1509 | .hsync_end = 480 + 5 + 5, | |
1510 | .htotal = 480 + 5 + 5 + 40, | |
1511 | .vdisplay = 272, | |
1512 | .vsync_start = 272 + 8, | |
1513 | .vsync_end = 272 + 8 + 8, | |
1514 | .vtotal = 272 + 8 + 8 + 8, | |
e58edce6 GB |
1515 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1516 | }; | |
1517 | ||
1518 | static const struct panel_desc cdtech_s043wq26h_ct7 = { | |
1519 | .modes = &cdtech_s043wq26h_ct7_mode, | |
1520 | .num_modes = 1, | |
1521 | .bpc = 8, | |
1522 | .size = { | |
1523 | .width = 95, | |
1524 | .height = 54, | |
1525 | }, | |
88bc4178 | 1526 | .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
e58edce6 GB |
1527 | }; |
1528 | ||
0e3b67f6 MK |
1529 | /* S070PWS19HP-FC21 2017/04/22 */ |
1530 | static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { | |
1531 | .clock = 51200, | |
1532 | .hdisplay = 1024, | |
1533 | .hsync_start = 1024 + 160, | |
1534 | .hsync_end = 1024 + 160 + 20, | |
1535 | .htotal = 1024 + 160 + 20 + 140, | |
1536 | .vdisplay = 600, | |
1537 | .vsync_start = 600 + 12, | |
1538 | .vsync_end = 600 + 12 + 3, | |
1539 | .vtotal = 600 + 12 + 3 + 20, | |
1540 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
1541 | }; | |
1542 | ||
1543 | static const struct panel_desc cdtech_s070pws19hp_fc21 = { | |
1544 | .modes = &cdtech_s070pws19hp_fc21_mode, | |
1545 | .num_modes = 1, | |
1546 | .bpc = 6, | |
1547 | .size = { | |
1548 | .width = 154, | |
1549 | .height = 86, | |
1550 | }, | |
1551 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
f5436f77 | 1552 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
0e3b67f6 MK |
1553 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1554 | }; | |
1555 | ||
1556 | /* S070SWV29HG-DC44 2017/09/21 */ | |
1557 | static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { | |
1558 | .clock = 33300, | |
1559 | .hdisplay = 800, | |
1560 | .hsync_start = 800 + 210, | |
1561 | .hsync_end = 800 + 210 + 2, | |
1562 | .htotal = 800 + 210 + 2 + 44, | |
1563 | .vdisplay = 480, | |
1564 | .vsync_start = 480 + 22, | |
1565 | .vsync_end = 480 + 22 + 2, | |
1566 | .vtotal = 480 + 22 + 2 + 21, | |
1567 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
1568 | }; | |
1569 | ||
1570 | static const struct panel_desc cdtech_s070swv29hg_dc44 = { | |
1571 | .modes = &cdtech_s070swv29hg_dc44_mode, | |
1572 | .num_modes = 1, | |
1573 | .bpc = 6, | |
1574 | .size = { | |
1575 | .width = 154, | |
1576 | .height = 86, | |
1577 | }, | |
1578 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
f5436f77 | 1579 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
0e3b67f6 MK |
1580 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
1581 | }; | |
1582 | ||
982f944e GB |
1583 | static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { |
1584 | .clock = 35000, | |
1585 | .hdisplay = 800, | |
1586 | .hsync_start = 800 + 40, | |
1587 | .hsync_end = 800 + 40 + 40, | |
1588 | .htotal = 800 + 40 + 40 + 48, | |
1589 | .vdisplay = 480, | |
1590 | .vsync_start = 480 + 29, | |
1591 | .vsync_end = 480 + 29 + 13, | |
1592 | .vtotal = 480 + 29 + 13 + 3, | |
982f944e GB |
1593 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1594 | }; | |
1595 | ||
1596 | static const struct panel_desc cdtech_s070wv95_ct16 = { | |
1597 | .modes = &cdtech_s070wv95_ct16_mode, | |
1598 | .num_modes = 1, | |
1599 | .bpc = 8, | |
1600 | .size = { | |
1601 | .width = 154, | |
1602 | .height = 85, | |
1603 | }, | |
1604 | }; | |
1605 | ||
07c913c4 MV |
1606 | static const struct display_timing chefree_ch101olhlwh_002_timing = { |
1607 | .pixelclock = { 68900000, 71100000, 73400000 }, | |
1608 | .hactive = { 1280, 1280, 1280 }, | |
1609 | .hfront_porch = { 65, 80, 95 }, | |
1610 | .hback_porch = { 64, 79, 94 }, | |
1611 | .hsync_len = { 1, 1, 1 }, | |
1612 | .vactive = { 800, 800, 800 }, | |
1613 | .vfront_porch = { 7, 11, 14 }, | |
1614 | .vback_porch = { 7, 11, 14 }, | |
1615 | .vsync_len = { 1, 1, 1 }, | |
1616 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
1617 | }; | |
1618 | ||
1619 | static const struct panel_desc chefree_ch101olhlwh_002 = { | |
1620 | .timings = &chefree_ch101olhlwh_002_timing, | |
1621 | .num_timings = 1, | |
1622 | .bpc = 8, | |
1623 | .size = { | |
1624 | .width = 217, | |
1625 | .height = 135, | |
1626 | }, | |
1627 | .delay = { | |
1628 | .enable = 200, | |
1629 | .disable = 200, | |
1630 | }, | |
1631 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
1632 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
1633 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
1634 | }; | |
1635 | ||
2cb35c80 RL |
1636 | static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { |
1637 | .clock = 66770, | |
1638 | .hdisplay = 800, | |
1639 | .hsync_start = 800 + 49, | |
1640 | .hsync_end = 800 + 49 + 33, | |
1641 | .htotal = 800 + 49 + 33 + 17, | |
1642 | .vdisplay = 1280, | |
1643 | .vsync_start = 1280 + 1, | |
1644 | .vsync_end = 1280 + 1 + 7, | |
1645 | .vtotal = 1280 + 1 + 7 + 15, | |
2cb35c80 RL |
1646 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1647 | }; | |
1648 | ||
1649 | static const struct panel_desc chunghwa_claa070wp03xg = { | |
1650 | .modes = &chunghwa_claa070wp03xg_mode, | |
1651 | .num_modes = 1, | |
1652 | .bpc = 6, | |
1653 | .size = { | |
1654 | .width = 94, | |
1655 | .height = 150, | |
1656 | }, | |
85560829 | 1657 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c4715837 | 1658 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
94f07917 | 1659 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2cb35c80 RL |
1660 | }; |
1661 | ||
4c930757 SW |
1662 | static const struct drm_display_mode chunghwa_claa101wa01a_mode = { |
1663 | .clock = 72070, | |
1664 | .hdisplay = 1366, | |
1665 | .hsync_start = 1366 + 58, | |
1666 | .hsync_end = 1366 + 58 + 58, | |
1667 | .htotal = 1366 + 58 + 58 + 58, | |
1668 | .vdisplay = 768, | |
1669 | .vsync_start = 768 + 4, | |
1670 | .vsync_end = 768 + 4 + 4, | |
1671 | .vtotal = 768 + 4 + 4 + 4, | |
4c930757 SW |
1672 | }; |
1673 | ||
1674 | static const struct panel_desc chunghwa_claa101wa01a = { | |
1675 | .modes = &chunghwa_claa101wa01a_mode, | |
1676 | .num_modes = 1, | |
0208d511 | 1677 | .bpc = 6, |
4c930757 SW |
1678 | .size = { |
1679 | .width = 220, | |
1680 | .height = 120, | |
1681 | }, | |
85560829 | 1682 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c4715837 | 1683 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
94f07917 | 1684 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4c930757 SW |
1685 | }; |
1686 | ||
280921de TR |
1687 | static const struct drm_display_mode chunghwa_claa101wb01_mode = { |
1688 | .clock = 69300, | |
1689 | .hdisplay = 1366, | |
1690 | .hsync_start = 1366 + 48, | |
1691 | .hsync_end = 1366 + 48 + 32, | |
1692 | .htotal = 1366 + 48 + 32 + 20, | |
1693 | .vdisplay = 768, | |
1694 | .vsync_start = 768 + 16, | |
1695 | .vsync_end = 768 + 16 + 8, | |
1696 | .vtotal = 768 + 16 + 8 + 16, | |
280921de TR |
1697 | }; |
1698 | ||
1699 | static const struct panel_desc chunghwa_claa101wb01 = { | |
1700 | .modes = &chunghwa_claa101wb01_mode, | |
1701 | .num_modes = 1, | |
0208d511 | 1702 | .bpc = 6, |
280921de TR |
1703 | .size = { |
1704 | .width = 223, | |
1705 | .height = 125, | |
1706 | }, | |
85560829 | 1707 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c4715837 | 1708 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
94f07917 | 1709 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
280921de TR |
1710 | }; |
1711 | ||
4dd024d4 MV |
1712 | static const struct display_timing dataimage_fg040346dsswbg04_timing = { |
1713 | .pixelclock = { 5000000, 9000000, 12000000 }, | |
1714 | .hactive = { 480, 480, 480 }, | |
1715 | .hfront_porch = { 12, 12, 12 }, | |
1716 | .hback_porch = { 12, 12, 12 }, | |
1717 | .hsync_len = { 21, 21, 21 }, | |
1718 | .vactive = { 272, 272, 272 }, | |
1719 | .vfront_porch = { 4, 4, 4 }, | |
1720 | .vback_porch = { 4, 4, 4 }, | |
1721 | .vsync_len = { 8, 8, 8 }, | |
1722 | }; | |
1723 | ||
1724 | static const struct panel_desc dataimage_fg040346dsswbg04 = { | |
1725 | .timings = &dataimage_fg040346dsswbg04_timing, | |
1726 | .num_timings = 1, | |
1727 | .bpc = 8, | |
1728 | .size = { | |
1729 | .width = 95, | |
1730 | .height = 54, | |
1731 | }, | |
1732 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
1733 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, | |
1734 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
1735 | }; | |
1736 | ||
803481d8 PO |
1737 | static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { |
1738 | .pixelclock = { 68900000, 71110000, 73400000 }, | |
1739 | .hactive = { 1280, 1280, 1280 }, | |
1740 | .vactive = { 800, 800, 800 }, | |
1741 | .hback_porch = { 100, 100, 100 }, | |
1742 | .hfront_porch = { 100, 100, 100 }, | |
1743 | .vback_porch = { 5, 5, 5 }, | |
1744 | .vfront_porch = { 5, 5, 5 }, | |
1745 | .hsync_len = { 24, 24, 24 }, | |
1746 | .vsync_len = { 3, 3, 3 }, | |
1747 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
1748 | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, | |
1749 | }; | |
1750 | ||
1751 | static const struct panel_desc dataimage_fg1001l0dsswmg01 = { | |
1752 | .timings = &dataimage_fg1001l0dsswmg01_timing, | |
1753 | .num_timings = 1, | |
1754 | .bpc = 8, | |
1755 | .size = { | |
1756 | .width = 217, | |
1757 | .height = 136, | |
1758 | }, | |
1759 | }; | |
1760 | ||
97ceb1fb MV |
1761 | static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { |
1762 | .clock = 33260, | |
1763 | .hdisplay = 800, | |
1764 | .hsync_start = 800 + 40, | |
1765 | .hsync_end = 800 + 40 + 128, | |
1766 | .htotal = 800 + 40 + 128 + 88, | |
1767 | .vdisplay = 480, | |
1768 | .vsync_start = 480 + 10, | |
1769 | .vsync_end = 480 + 10 + 2, | |
1770 | .vtotal = 480 + 10 + 2 + 33, | |
97ceb1fb MV |
1771 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1772 | }; | |
1773 | ||
1774 | static const struct panel_desc dataimage_scf0700c48ggu18 = { | |
1775 | .modes = &dataimage_scf0700c48ggu18_mode, | |
1776 | .num_modes = 1, | |
1777 | .bpc = 8, | |
1778 | .size = { | |
1779 | .width = 152, | |
1780 | .height = 91, | |
1781 | }, | |
1782 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
88bc4178 | 1783 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
97ceb1fb MV |
1784 | }; |
1785 | ||
0ca0c827 PZ |
1786 | static const struct display_timing dlc_dlc0700yzg_1_timing = { |
1787 | .pixelclock = { 45000000, 51200000, 57000000 }, | |
1788 | .hactive = { 1024, 1024, 1024 }, | |
1789 | .hfront_porch = { 100, 106, 113 }, | |
1790 | .hback_porch = { 100, 106, 113 }, | |
1791 | .hsync_len = { 100, 108, 114 }, | |
1792 | .vactive = { 600, 600, 600 }, | |
1793 | .vfront_porch = { 8, 11, 15 }, | |
1794 | .vback_porch = { 8, 11, 15 }, | |
1795 | .vsync_len = { 9, 13, 15 }, | |
1796 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
1797 | }; | |
1798 | ||
1799 | static const struct panel_desc dlc_dlc0700yzg_1 = { | |
1800 | .timings = &dlc_dlc0700yzg_1_timing, | |
1801 | .num_timings = 1, | |
1802 | .bpc = 6, | |
1803 | .size = { | |
1804 | .width = 154, | |
1805 | .height = 86, | |
1806 | }, | |
1807 | .delay = { | |
1808 | .prepare = 30, | |
1809 | .enable = 200, | |
1810 | .disable = 200, | |
1811 | }, | |
1812 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
9a2654c0 | 1813 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
0ca0c827 PZ |
1814 | }; |
1815 | ||
6cbe7cd1 MF |
1816 | static const struct display_timing dlc_dlc1010gig_timing = { |
1817 | .pixelclock = { 68900000, 71100000, 73400000 }, | |
1818 | .hactive = { 1280, 1280, 1280 }, | |
1819 | .hfront_porch = { 43, 53, 63 }, | |
1820 | .hback_porch = { 43, 53, 63 }, | |
1821 | .hsync_len = { 44, 54, 64 }, | |
1822 | .vactive = { 800, 800, 800 }, | |
1823 | .vfront_porch = { 5, 8, 11 }, | |
1824 | .vback_porch = { 5, 8, 11 }, | |
1825 | .vsync_len = { 5, 7, 11 }, | |
1826 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
1827 | }; | |
1828 | ||
1829 | static const struct panel_desc dlc_dlc1010gig = { | |
1830 | .timings = &dlc_dlc1010gig_timing, | |
1831 | .num_timings = 1, | |
1832 | .bpc = 8, | |
1833 | .size = { | |
1834 | .width = 216, | |
1835 | .height = 135, | |
1836 | }, | |
1837 | .delay = { | |
1838 | .prepare = 60, | |
1839 | .enable = 150, | |
1840 | .disable = 100, | |
1841 | .unprepare = 60, | |
1842 | }, | |
1843 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 1844 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
6cbe7cd1 MF |
1845 | }; |
1846 | ||
c2d24af6 AP |
1847 | static const struct drm_display_mode edt_et035012dm6_mode = { |
1848 | .clock = 6500, | |
1849 | .hdisplay = 320, | |
1850 | .hsync_start = 320 + 20, | |
1851 | .hsync_end = 320 + 20 + 30, | |
1852 | .htotal = 320 + 20 + 68, | |
1853 | .vdisplay = 240, | |
1854 | .vsync_start = 240 + 4, | |
1855 | .vsync_end = 240 + 4 + 4, | |
1856 | .vtotal = 240 + 4 + 4 + 14, | |
c2d24af6 AP |
1857 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1858 | }; | |
1859 | ||
1860 | static const struct panel_desc edt_et035012dm6 = { | |
1861 | .modes = &edt_et035012dm6_mode, | |
1862 | .num_modes = 1, | |
1863 | .bpc = 8, | |
1864 | .size = { | |
1865 | .width = 70, | |
1866 | .height = 52, | |
1867 | }, | |
1868 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 1869 | .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
c2d24af6 AP |
1870 | }; |
1871 | ||
f08a2a1e SR |
1872 | static const struct drm_display_mode edt_etm0350g0dh6_mode = { |
1873 | .clock = 6520, | |
1874 | .hdisplay = 320, | |
1875 | .hsync_start = 320 + 20, | |
1876 | .hsync_end = 320 + 20 + 68, | |
1877 | .htotal = 320 + 20 + 68, | |
1878 | .vdisplay = 240, | |
1879 | .vsync_start = 240 + 4, | |
1880 | .vsync_end = 240 + 4 + 18, | |
1881 | .vtotal = 240 + 4 + 18, | |
1882 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
1883 | }; | |
1884 | ||
1885 | static const struct panel_desc edt_etm0350g0dh6 = { | |
1886 | .modes = &edt_etm0350g0dh6_mode, | |
1887 | .num_modes = 1, | |
1888 | .bpc = 6, | |
1889 | .size = { | |
1890 | .width = 70, | |
1891 | .height = 53, | |
1892 | }, | |
1893 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
1894 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, | |
1895 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
1896 | }; | |
1897 | ||
82d57a59 MCR |
1898 | static const struct drm_display_mode edt_etm043080dh6gp_mode = { |
1899 | .clock = 10870, | |
1900 | .hdisplay = 480, | |
1901 | .hsync_start = 480 + 8, | |
1902 | .hsync_end = 480 + 8 + 4, | |
1903 | .htotal = 480 + 8 + 4 + 41, | |
1904 | ||
1905 | /* | |
1906 | * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while | |
1907 | * fb_align | |
1908 | */ | |
1909 | ||
1910 | .vdisplay = 288, | |
1911 | .vsync_start = 288 + 2, | |
1912 | .vsync_end = 288 + 2 + 4, | |
1913 | .vtotal = 288 + 2 + 4 + 10, | |
82d57a59 MCR |
1914 | }; |
1915 | ||
1916 | static const struct panel_desc edt_etm043080dh6gp = { | |
1917 | .modes = &edt_etm043080dh6gp_mode, | |
1918 | .num_modes = 1, | |
1919 | .bpc = 8, | |
1920 | .size = { | |
1921 | .width = 100, | |
1922 | .height = 65, | |
1923 | }, | |
1924 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
1925 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
1926 | }; | |
1927 | ||
fd819bff MV |
1928 | static const struct drm_display_mode edt_etm0430g0dh6_mode = { |
1929 | .clock = 9000, | |
1930 | .hdisplay = 480, | |
1931 | .hsync_start = 480 + 2, | |
1932 | .hsync_end = 480 + 2 + 41, | |
1933 | .htotal = 480 + 2 + 41 + 2, | |
1934 | .vdisplay = 272, | |
1935 | .vsync_start = 272 + 2, | |
1936 | .vsync_end = 272 + 2 + 10, | |
1937 | .vtotal = 272 + 2 + 10 + 2, | |
fd819bff MV |
1938 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1939 | }; | |
1940 | ||
1941 | static const struct panel_desc edt_etm0430g0dh6 = { | |
1942 | .modes = &edt_etm0430g0dh6_mode, | |
1943 | .num_modes = 1, | |
1944 | .bpc = 6, | |
1945 | .size = { | |
1946 | .width = 95, | |
1947 | .height = 54, | |
1948 | }, | |
4824a5f7 SR |
1949 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
1950 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, | |
d112e10f | 1951 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
fd819bff MV |
1952 | }; |
1953 | ||
26ab0065 SA |
1954 | static const struct drm_display_mode edt_et057090dhu_mode = { |
1955 | .clock = 25175, | |
1956 | .hdisplay = 640, | |
1957 | .hsync_start = 640 + 16, | |
1958 | .hsync_end = 640 + 16 + 30, | |
1959 | .htotal = 640 + 16 + 30 + 114, | |
1960 | .vdisplay = 480, | |
1961 | .vsync_start = 480 + 10, | |
1962 | .vsync_end = 480 + 10 + 3, | |
1963 | .vtotal = 480 + 10 + 3 + 32, | |
26ab0065 SA |
1964 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
1965 | }; | |
1966 | ||
1967 | static const struct panel_desc edt_et057090dhu = { | |
1968 | .modes = &edt_et057090dhu_mode, | |
1969 | .num_modes = 1, | |
0208d511 | 1970 | .bpc = 6, |
26ab0065 SA |
1971 | .size = { |
1972 | .width = 115, | |
1973 | .height = 86, | |
1974 | }, | |
eaeebffa | 1975 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
88bc4178 | 1976 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
75e73224 | 1977 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
26ab0065 SA |
1978 | }; |
1979 | ||
fff5de45 PZ |
1980 | static const struct drm_display_mode edt_etm0700g0dh6_mode = { |
1981 | .clock = 33260, | |
1982 | .hdisplay = 800, | |
1983 | .hsync_start = 800 + 40, | |
1984 | .hsync_end = 800 + 40 + 128, | |
1985 | .htotal = 800 + 40 + 128 + 88, | |
1986 | .vdisplay = 480, | |
1987 | .vsync_start = 480 + 10, | |
1988 | .vsync_end = 480 + 10 + 2, | |
1989 | .vtotal = 480 + 10 + 2 + 33, | |
fff5de45 PZ |
1990 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
1991 | }; | |
1992 | ||
1993 | static const struct panel_desc edt_etm0700g0dh6 = { | |
1994 | .modes = &edt_etm0700g0dh6_mode, | |
1995 | .num_modes = 1, | |
0208d511 | 1996 | .bpc = 6, |
fff5de45 PZ |
1997 | .size = { |
1998 | .width = 152, | |
1999 | .height = 91, | |
2000 | }, | |
eaeebffa | 2001 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
88bc4178 | 2002 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, |
281edb9f | 2003 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
fff5de45 PZ |
2004 | }; |
2005 | ||
aa7e6455 JT |
2006 | static const struct panel_desc edt_etm0700g0bdh6 = { |
2007 | .modes = &edt_etm0700g0dh6_mode, | |
2008 | .num_modes = 1, | |
2009 | .bpc = 6, | |
2010 | .size = { | |
2011 | .width = 152, | |
2012 | .height = 91, | |
2013 | }, | |
2014 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
88bc4178 | 2015 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
d112e10f | 2016 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
aa7e6455 JT |
2017 | }; |
2018 | ||
a6cc3c72 MF |
2019 | static const struct display_timing edt_etml0700y5dha_timing = { |
2020 | .pixelclock = { 40800000, 51200000, 67200000 }, | |
2021 | .hactive = { 1024, 1024, 1024 }, | |
2022 | .hfront_porch = { 30, 106, 125 }, | |
2023 | .hback_porch = { 30, 106, 125 }, | |
2024 | .hsync_len = { 30, 108, 126 }, | |
2025 | .vactive = { 600, 600, 600 }, | |
2026 | .vfront_porch = { 3, 12, 67}, | |
2027 | .vback_porch = { 3, 12, 67 }, | |
2028 | .vsync_len = { 4, 11, 66 }, | |
2029 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
2030 | DISPLAY_FLAGS_DE_HIGH, | |
2031 | }; | |
2032 | ||
2033 | static const struct panel_desc edt_etml0700y5dha = { | |
2034 | .timings = &edt_etml0700y5dha_timing, | |
2035 | .num_timings = 1, | |
2036 | .bpc = 8, | |
2037 | .size = { | |
2038 | .width = 155, | |
2039 | .height = 86, | |
2040 | }, | |
2041 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2042 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2043 | }; | |
2044 | ||
aeb262c3 PF |
2045 | static const struct display_timing edt_etml1010g3dra_timing = { |
2046 | .pixelclock = { 66300000, 72400000, 78900000 }, | |
2047 | .hactive = { 1280, 1280, 1280 }, | |
2048 | .hfront_porch = { 12, 72, 132 }, | |
2049 | .hback_porch = { 86, 86, 86 }, | |
2050 | .hsync_len = { 2, 2, 2 }, | |
2051 | .vactive = { 800, 800, 800 }, | |
2052 | .vfront_porch = { 1, 15, 49 }, | |
2053 | .vback_porch = { 21, 21, 21 }, | |
2054 | .vsync_len = { 2, 2, 2 }, | |
2055 | .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | | |
2056 | DISPLAY_FLAGS_DE_HIGH, | |
2057 | }; | |
2058 | ||
2059 | static const struct panel_desc edt_etml1010g3dra = { | |
2060 | .timings = &edt_etml1010g3dra_timing, | |
2061 | .num_timings = 1, | |
2062 | .bpc = 8, | |
2063 | .size = { | |
2064 | .width = 216, | |
2065 | .height = 135, | |
2066 | }, | |
2067 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2068 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2069 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2070 | }; | |
2071 | ||
e46f73fb SR |
2072 | static const struct drm_display_mode edt_etmv570g2dhu_mode = { |
2073 | .clock = 25175, | |
2074 | .hdisplay = 640, | |
2075 | .hsync_start = 640, | |
2076 | .hsync_end = 640 + 16, | |
2077 | .htotal = 640 + 16 + 30 + 114, | |
2078 | .vdisplay = 480, | |
2079 | .vsync_start = 480 + 10, | |
2080 | .vsync_end = 480 + 10 + 3, | |
2081 | .vtotal = 480 + 10 + 3 + 35, | |
2082 | .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, | |
2083 | }; | |
2084 | ||
2085 | static const struct panel_desc edt_etmv570g2dhu = { | |
2086 | .modes = &edt_etmv570g2dhu_mode, | |
2087 | .num_modes = 1, | |
2088 | .bpc = 6, | |
2089 | .size = { | |
2090 | .width = 115, | |
2091 | .height = 86, | |
2092 | }, | |
2093 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
2094 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, | |
2095 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
2096 | }; | |
2097 | ||
9746f5fe AF |
2098 | static const struct display_timing eink_vb3300_kca_timing = { |
2099 | .pixelclock = { 40000000, 40000000, 40000000 }, | |
2100 | .hactive = { 334, 334, 334 }, | |
2101 | .hfront_porch = { 1, 1, 1 }, | |
2102 | .hback_porch = { 1, 1, 1 }, | |
2103 | .hsync_len = { 1, 1, 1 }, | |
2104 | .vactive = { 1405, 1405, 1405 }, | |
2105 | .vfront_porch = { 1, 1, 1 }, | |
2106 | .vback_porch = { 1, 1, 1 }, | |
2107 | .vsync_len = { 1, 1, 1 }, | |
2108 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
2109 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, | |
2110 | }; | |
2111 | ||
2112 | static const struct panel_desc eink_vb3300_kca = { | |
2113 | .timings = &eink_vb3300_kca_timing, | |
2114 | .num_timings = 1, | |
2115 | .bpc = 6, | |
2116 | .size = { | |
2117 | .width = 157, | |
2118 | .height = 209, | |
2119 | }, | |
2120 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
2121 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, | |
2122 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
2123 | }; | |
2124 | ||
1319f217 MW |
2125 | static const struct display_timing evervision_vgg644804_timing = { |
2126 | .pixelclock = { 25175000, 25175000, 25175000 }, | |
2127 | .hactive = { 640, 640, 640 }, | |
2128 | .hfront_porch = { 16, 16, 16 }, | |
2129 | .hback_porch = { 82, 114, 170 }, | |
2130 | .hsync_len = { 5, 30, 30 }, | |
2131 | .vactive = { 480, 480, 480 }, | |
2132 | .vfront_porch = { 10, 10, 10 }, | |
2133 | .vback_porch = { 30, 32, 34 }, | |
2134 | .vsync_len = { 1, 3, 5 }, | |
2135 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
2136 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
2137 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
2138 | }; | |
2139 | ||
2140 | static const struct panel_desc evervision_vgg644804 = { | |
2141 | .timings = &evervision_vgg644804_timing, | |
2142 | .num_timings = 1, | |
2143 | .bpc = 8, | |
2144 | .size = { | |
2145 | .width = 115, | |
2146 | .height = 86, | |
2147 | }, | |
2148 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
2149 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
2150 | }; | |
2151 | ||
9158e3c3 MF |
2152 | static const struct display_timing evervision_vgg804821_timing = { |
2153 | .pixelclock = { 27600000, 33300000, 50000000 }, | |
2154 | .hactive = { 800, 800, 800 }, | |
2155 | .hfront_porch = { 40, 66, 70 }, | |
2156 | .hback_porch = { 40, 67, 70 }, | |
2157 | .hsync_len = { 40, 67, 70 }, | |
2158 | .vactive = { 480, 480, 480 }, | |
2159 | .vfront_porch = { 6, 10, 10 }, | |
2160 | .vback_porch = { 7, 11, 11 }, | |
2161 | .vsync_len = { 7, 11, 11 }, | |
2162 | .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | | |
2163 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | | |
2164 | DISPLAY_FLAGS_SYNC_NEGEDGE, | |
2165 | }; | |
2166 | ||
2167 | static const struct panel_desc evervision_vgg804821 = { | |
2168 | .timings = &evervision_vgg804821_timing, | |
2169 | .num_timings = 1, | |
2170 | .bpc = 8, | |
2171 | .size = { | |
2172 | .width = 108, | |
2173 | .height = 64, | |
2174 | }, | |
2175 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 2176 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
9158e3c3 MF |
2177 | }; |
2178 | ||
102932b0 BB |
2179 | static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { |
2180 | .clock = 32260, | |
2181 | .hdisplay = 800, | |
2182 | .hsync_start = 800 + 168, | |
2183 | .hsync_end = 800 + 168 + 64, | |
2184 | .htotal = 800 + 168 + 64 + 88, | |
2185 | .vdisplay = 480, | |
2186 | .vsync_start = 480 + 37, | |
2187 | .vsync_end = 480 + 37 + 2, | |
2188 | .vtotal = 480 + 37 + 2 + 8, | |
102932b0 BB |
2189 | }; |
2190 | ||
2191 | static const struct panel_desc foxlink_fl500wvr00_a0t = { | |
2192 | .modes = &foxlink_fl500wvr00_a0t_mode, | |
2193 | .num_modes = 1, | |
d7a839cd | 2194 | .bpc = 8, |
102932b0 BB |
2195 | .size = { |
2196 | .width = 108, | |
2197 | .height = 65, | |
2198 | }, | |
bb276cb3 | 2199 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
102932b0 BB |
2200 | }; |
2201 | ||
795db2af PC |
2202 | static const struct drm_display_mode frida_frd350h54004_modes[] = { |
2203 | { /* 60 Hz */ | |
2204 | .clock = 6000, | |
2205 | .hdisplay = 320, | |
2206 | .hsync_start = 320 + 44, | |
2207 | .hsync_end = 320 + 44 + 16, | |
2208 | .htotal = 320 + 44 + 16 + 20, | |
2209 | .vdisplay = 240, | |
2210 | .vsync_start = 240 + 2, | |
2211 | .vsync_end = 240 + 2 + 6, | |
2212 | .vtotal = 240 + 2 + 6 + 2, | |
2213 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
2214 | }, | |
2215 | { /* 50 Hz */ | |
2216 | .clock = 5400, | |
2217 | .hdisplay = 320, | |
2218 | .hsync_start = 320 + 56, | |
2219 | .hsync_end = 320 + 56 + 16, | |
2220 | .htotal = 320 + 56 + 16 + 40, | |
2221 | .vdisplay = 240, | |
2222 | .vsync_start = 240 + 2, | |
2223 | .vsync_end = 240 + 2 + 6, | |
2224 | .vtotal = 240 + 2 + 6 + 2, | |
2225 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
2226 | }, | |
7b6bd843 PC |
2227 | }; |
2228 | ||
2229 | static const struct panel_desc frida_frd350h54004 = { | |
795db2af PC |
2230 | .modes = frida_frd350h54004_modes, |
2231 | .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), | |
7b6bd843 PC |
2232 | .bpc = 8, |
2233 | .size = { | |
2234 | .width = 77, | |
2235 | .height = 64, | |
2236 | }, | |
2237 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 2238 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
7b6bd843 PC |
2239 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
2240 | }; | |
2241 | ||
3be20710 JT |
2242 | static const struct drm_display_mode friendlyarm_hd702e_mode = { |
2243 | .clock = 67185, | |
2244 | .hdisplay = 800, | |
2245 | .hsync_start = 800 + 20, | |
2246 | .hsync_end = 800 + 20 + 24, | |
2247 | .htotal = 800 + 20 + 24 + 20, | |
2248 | .vdisplay = 1280, | |
2249 | .vsync_start = 1280 + 4, | |
2250 | .vsync_end = 1280 + 4 + 8, | |
2251 | .vtotal = 1280 + 4 + 8 + 4, | |
3be20710 JT |
2252 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
2253 | }; | |
2254 | ||
2255 | static const struct panel_desc friendlyarm_hd702e = { | |
2256 | .modes = &friendlyarm_hd702e_mode, | |
2257 | .num_modes = 1, | |
2258 | .size = { | |
2259 | .width = 94, | |
2260 | .height = 151, | |
2261 | }, | |
2262 | }; | |
2263 | ||
d435a2af PZ |
2264 | static const struct drm_display_mode giantplus_gpg482739qs5_mode = { |
2265 | .clock = 9000, | |
2266 | .hdisplay = 480, | |
2267 | .hsync_start = 480 + 5, | |
2268 | .hsync_end = 480 + 5 + 1, | |
2269 | .htotal = 480 + 5 + 1 + 40, | |
2270 | .vdisplay = 272, | |
2271 | .vsync_start = 272 + 8, | |
2272 | .vsync_end = 272 + 8 + 1, | |
2273 | .vtotal = 272 + 8 + 1 + 8, | |
d435a2af PZ |
2274 | }; |
2275 | ||
2276 | static const struct panel_desc giantplus_gpg482739qs5 = { | |
2277 | .modes = &giantplus_gpg482739qs5_mode, | |
2278 | .num_modes = 1, | |
2279 | .bpc = 8, | |
2280 | .size = { | |
2281 | .width = 95, | |
2282 | .height = 54, | |
2283 | }, | |
33536a09 | 2284 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
d435a2af PZ |
2285 | }; |
2286 | ||
2c6574a9 PC |
2287 | static const struct display_timing giantplus_gpm940b0_timing = { |
2288 | .pixelclock = { 13500000, 27000000, 27500000 }, | |
2289 | .hactive = { 320, 320, 320 }, | |
2290 | .hfront_porch = { 14, 686, 718 }, | |
2291 | .hback_porch = { 50, 70, 255 }, | |
2292 | .hsync_len = { 1, 1, 1 }, | |
2293 | .vactive = { 240, 240, 240 }, | |
2294 | .vfront_porch = { 1, 1, 179 }, | |
2295 | .vback_porch = { 1, 21, 31 }, | |
2296 | .vsync_len = { 1, 1, 6 }, | |
2297 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, | |
2298 | }; | |
2299 | ||
2300 | static const struct panel_desc giantplus_gpm940b0 = { | |
2301 | .timings = &giantplus_gpm940b0_timing, | |
2302 | .num_timings = 1, | |
2303 | .bpc = 8, | |
2304 | .size = { | |
2305 | .width = 60, | |
2306 | .height = 45, | |
2307 | }, | |
2308 | .bus_format = MEDIA_BUS_FMT_RGB888_3X8, | |
f5436f77 | 2309 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
2c6574a9 PC |
2310 | }; |
2311 | ||
ab07725a PZ |
2312 | static const struct display_timing hannstar_hsd070pww1_timing = { |
2313 | .pixelclock = { 64300000, 71100000, 82000000 }, | |
2314 | .hactive = { 1280, 1280, 1280 }, | |
2315 | .hfront_porch = { 1, 1, 10 }, | |
2316 | .hback_porch = { 1, 1, 10 }, | |
d901d2ba PZ |
2317 | /* |
2318 | * According to the data sheet, the minimum horizontal blanking interval | |
2319 | * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the | |
2320 | * minimum working horizontal blanking interval to be 60 clocks. | |
2321 | */ | |
2322 | .hsync_len = { 58, 158, 661 }, | |
ab07725a PZ |
2323 | .vactive = { 800, 800, 800 }, |
2324 | .vfront_porch = { 1, 1, 10 }, | |
2325 | .vback_porch = { 1, 1, 10 }, | |
2326 | .vsync_len = { 1, 21, 203 }, | |
2327 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
a853205e PZ |
2328 | }; |
2329 | ||
2330 | static const struct panel_desc hannstar_hsd070pww1 = { | |
ab07725a PZ |
2331 | .timings = &hannstar_hsd070pww1_timing, |
2332 | .num_timings = 1, | |
a853205e PZ |
2333 | .bpc = 6, |
2334 | .size = { | |
2335 | .width = 151, | |
2336 | .height = 94, | |
2337 | }, | |
58d6a7bc | 2338 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
9a2654c0 | 2339 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
a853205e PZ |
2340 | }; |
2341 | ||
c0d607e5 EN |
2342 | static const struct display_timing hannstar_hsd100pxn1_timing = { |
2343 | .pixelclock = { 55000000, 65000000, 75000000 }, | |
2344 | .hactive = { 1024, 1024, 1024 }, | |
2345 | .hfront_porch = { 40, 40, 40 }, | |
2346 | .hback_porch = { 220, 220, 220 }, | |
2347 | .hsync_len = { 20, 60, 100 }, | |
2348 | .vactive = { 768, 768, 768 }, | |
2349 | .vfront_porch = { 7, 7, 7 }, | |
2350 | .vback_porch = { 21, 21, 21 }, | |
2351 | .vsync_len = { 10, 10, 10 }, | |
2352 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2353 | }; | |
2354 | ||
2355 | static const struct panel_desc hannstar_hsd100pxn1 = { | |
2356 | .timings = &hannstar_hsd100pxn1_timing, | |
2357 | .num_timings = 1, | |
2358 | .bpc = 6, | |
2359 | .size = { | |
2360 | .width = 203, | |
2361 | .height = 152, | |
2362 | }, | |
4946b043 | 2363 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
9a2654c0 | 2364 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
c0d607e5 EN |
2365 | }; |
2366 | ||
170a41e9 SR |
2367 | static const struct display_timing hannstar_hsd101pww2_timing = { |
2368 | .pixelclock = { 64300000, 71100000, 82000000 }, | |
2369 | .hactive = { 1280, 1280, 1280 }, | |
2370 | .hfront_porch = { 1, 1, 10 }, | |
2371 | .hback_porch = { 1, 1, 10 }, | |
2372 | .hsync_len = { 58, 158, 661 }, | |
2373 | .vactive = { 800, 800, 800 }, | |
2374 | .vfront_porch = { 1, 1, 10 }, | |
2375 | .vback_porch = { 1, 1, 10 }, | |
2376 | .vsync_len = { 1, 21, 203 }, | |
2377 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2378 | }; | |
2379 | ||
2380 | static const struct panel_desc hannstar_hsd101pww2 = { | |
2381 | .timings = &hannstar_hsd101pww2_timing, | |
2382 | .num_timings = 1, | |
2383 | .bpc = 8, | |
2384 | .size = { | |
2385 | .width = 217, | |
2386 | .height = 136, | |
2387 | }, | |
2388 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2389 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2390 | }; | |
2391 | ||
61ac0bf8 LS |
2392 | static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { |
2393 | .clock = 33333, | |
2394 | .hdisplay = 800, | |
2395 | .hsync_start = 800 + 85, | |
2396 | .hsync_end = 800 + 85 + 86, | |
2397 | .htotal = 800 + 85 + 86 + 85, | |
2398 | .vdisplay = 480, | |
2399 | .vsync_start = 480 + 16, | |
2400 | .vsync_end = 480 + 16 + 13, | |
2401 | .vtotal = 480 + 16 + 13 + 16, | |
61ac0bf8 LS |
2402 | }; |
2403 | ||
2404 | static const struct panel_desc hitachi_tx23d38vm0caa = { | |
2405 | .modes = &hitachi_tx23d38vm0caa_mode, | |
2406 | .num_modes = 1, | |
2407 | .bpc = 6, | |
2408 | .size = { | |
2409 | .width = 195, | |
2410 | .height = 117, | |
2411 | }, | |
6c684e3b PZ |
2412 | .delay = { |
2413 | .enable = 160, | |
2414 | .disable = 160, | |
2415 | }, | |
61ac0bf8 LS |
2416 | }; |
2417 | ||
41bcceb4 NF |
2418 | static const struct drm_display_mode innolux_at043tn24_mode = { |
2419 | .clock = 9000, | |
2420 | .hdisplay = 480, | |
2421 | .hsync_start = 480 + 2, | |
2422 | .hsync_end = 480 + 2 + 41, | |
2423 | .htotal = 480 + 2 + 41 + 2, | |
2424 | .vdisplay = 272, | |
2425 | .vsync_start = 272 + 2, | |
a483159d PZ |
2426 | .vsync_end = 272 + 2 + 10, |
2427 | .vtotal = 272 + 2 + 10 + 2, | |
41bcceb4 NF |
2428 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
2429 | }; | |
2430 | ||
2431 | static const struct panel_desc innolux_at043tn24 = { | |
2432 | .modes = &innolux_at043tn24_mode, | |
2433 | .num_modes = 1, | |
2434 | .bpc = 8, | |
2435 | .size = { | |
2436 | .width = 95, | |
2437 | .height = 54, | |
2438 | }, | |
2439 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
2c56a751 | 2440 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
88bc4178 | 2441 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
41bcceb4 NF |
2442 | }; |
2443 | ||
4fc24ab3 RB |
2444 | static const struct drm_display_mode innolux_at070tn92_mode = { |
2445 | .clock = 33333, | |
2446 | .hdisplay = 800, | |
2447 | .hsync_start = 800 + 210, | |
2448 | .hsync_end = 800 + 210 + 20, | |
2449 | .htotal = 800 + 210 + 20 + 46, | |
2450 | .vdisplay = 480, | |
2451 | .vsync_start = 480 + 22, | |
2452 | .vsync_end = 480 + 22 + 10, | |
2453 | .vtotal = 480 + 22 + 23 + 10, | |
4fc24ab3 RB |
2454 | }; |
2455 | ||
2456 | static const struct panel_desc innolux_at070tn92 = { | |
2457 | .modes = &innolux_at070tn92_mode, | |
2458 | .num_modes = 1, | |
2459 | .size = { | |
2460 | .width = 154, | |
2461 | .height = 86, | |
2462 | }, | |
2463 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
2464 | }; | |
2465 | ||
1993f598 RL |
2466 | static const struct display_timing innolux_g070ace_l01_timing = { |
2467 | .pixelclock = { 25200000, 35000000, 35700000 }, | |
2468 | .hactive = { 800, 800, 800 }, | |
2469 | .hfront_porch = { 30, 32, 87 }, | |
2470 | .hback_porch = { 30, 32, 87 }, | |
2471 | .hsync_len = { 1, 1, 1 }, | |
2472 | .vactive = { 480, 480, 480 }, | |
2473 | .vfront_porch = { 3, 3, 3 }, | |
2474 | .vback_porch = { 13, 13, 13 }, | |
2475 | .vsync_len = { 1, 1, 4 }, | |
2476 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2477 | }; | |
2478 | ||
2479 | static const struct panel_desc innolux_g070ace_l01 = { | |
2480 | .timings = &innolux_g070ace_l01_timing, | |
2481 | .num_timings = 1, | |
2482 | .bpc = 8, | |
2483 | .size = { | |
2484 | .width = 152, | |
2485 | .height = 91, | |
2486 | }, | |
2487 | .delay = { | |
2488 | .prepare = 10, | |
2489 | .enable = 50, | |
2490 | .disable = 50, | |
2491 | .unprepare = 500, | |
2492 | }, | |
2493 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2494 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2495 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2496 | }; | |
2497 | ||
a5d2ade6 CF |
2498 | static const struct display_timing innolux_g070y2_l01_timing = { |
2499 | .pixelclock = { 28000000, 29500000, 32000000 }, | |
2500 | .hactive = { 800, 800, 800 }, | |
2501 | .hfront_porch = { 61, 91, 141 }, | |
2502 | .hback_porch = { 60, 90, 140 }, | |
2503 | .hsync_len = { 12, 12, 12 }, | |
2504 | .vactive = { 480, 480, 480 }, | |
2505 | .vfront_porch = { 4, 9, 30 }, | |
2506 | .vback_porch = { 4, 8, 28 }, | |
2507 | .vsync_len = { 2, 2, 2 }, | |
2508 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2509 | }; | |
2510 | ||
2511 | static const struct panel_desc innolux_g070y2_l01 = { | |
2512 | .timings = &innolux_g070y2_l01_timing, | |
2513 | .num_timings = 1, | |
fc1b6ef7 | 2514 | .bpc = 8, |
a5d2ade6 CF |
2515 | .size = { |
2516 | .width = 152, | |
2517 | .height = 91, | |
2518 | }, | |
2519 | .delay = { | |
2520 | .prepare = 10, | |
2521 | .enable = 100, | |
2522 | .disable = 100, | |
2523 | .unprepare = 800, | |
2524 | }, | |
2525 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
0f73a559 | 2526 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
9a2654c0 | 2527 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
a5d2ade6 CF |
2528 | }; |
2529 | ||
b9d228a5 ST |
2530 | static const struct display_timing innolux_g070ace_lh3_timing = { |
2531 | .pixelclock = { 25200000, 25400000, 35700000 }, | |
2532 | .hactive = { 800, 800, 800 }, | |
2533 | .hfront_porch = { 30, 32, 87 }, | |
2534 | .hback_porch = { 29, 31, 86 }, | |
2535 | .hsync_len = { 1, 1, 1 }, | |
2536 | .vactive = { 480, 480, 480 }, | |
2537 | .vfront_porch = { 4, 5, 65 }, | |
2538 | .vback_porch = { 3, 4, 65 }, | |
2539 | .vsync_len = { 1, 1, 1 }, | |
2540 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2541 | }; | |
2542 | ||
2543 | static const struct panel_desc innolux_g070ace_lh3 = { | |
2544 | .timings = &innolux_g070ace_lh3_timing, | |
2545 | .num_timings = 1, | |
2546 | .bpc = 8, | |
2547 | .size = { | |
2548 | .width = 152, | |
2549 | .height = 91, | |
2550 | }, | |
2551 | .delay = { | |
2552 | .prepare = 10, | |
2553 | .enable = 450, | |
2554 | .disable = 200, | |
2555 | .unprepare = 510, | |
2556 | }, | |
2557 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2558 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2559 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2560 | }; | |
2561 | ||
57a06e90 OR |
2562 | static const struct drm_display_mode innolux_g070y2_t02_mode = { |
2563 | .clock = 33333, | |
2564 | .hdisplay = 800, | |
2565 | .hsync_start = 800 + 210, | |
2566 | .hsync_end = 800 + 210 + 20, | |
2567 | .htotal = 800 + 210 + 20 + 46, | |
2568 | .vdisplay = 480, | |
2569 | .vsync_start = 480 + 22, | |
2570 | .vsync_end = 480 + 22 + 10, | |
2571 | .vtotal = 480 + 22 + 23 + 10, | |
2572 | }; | |
2573 | ||
2574 | static const struct panel_desc innolux_g070y2_t02 = { | |
2575 | .modes = &innolux_g070y2_t02_mode, | |
2576 | .num_modes = 1, | |
2577 | .bpc = 8, | |
2578 | .size = { | |
2579 | .width = 152, | |
2580 | .height = 92, | |
2581 | }, | |
2582 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
2583 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, | |
2584 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
2585 | }; | |
2586 | ||
1e29b840 MO |
2587 | static const struct display_timing innolux_g101ice_l01_timing = { |
2588 | .pixelclock = { 60400000, 71100000, 74700000 }, | |
2589 | .hactive = { 1280, 1280, 1280 }, | |
3f9a91b6 MV |
2590 | .hfront_porch = { 30, 60, 70 }, |
2591 | .hback_porch = { 30, 60, 70 }, | |
2592 | .hsync_len = { 22, 40, 60 }, | |
1e29b840 | 2593 | .vactive = { 800, 800, 800 }, |
3f9a91b6 MV |
2594 | .vfront_porch = { 3, 8, 14 }, |
2595 | .vback_porch = { 3, 8, 14 }, | |
2596 | .vsync_len = { 4, 7, 12 }, | |
1e29b840 MO |
2597 | .flags = DISPLAY_FLAGS_DE_HIGH, |
2598 | }; | |
2599 | ||
2600 | static const struct panel_desc innolux_g101ice_l01 = { | |
2601 | .timings = &innolux_g101ice_l01_timing, | |
2602 | .num_timings = 1, | |
2603 | .bpc = 8, | |
2604 | .size = { | |
2605 | .width = 217, | |
2606 | .height = 135, | |
2607 | }, | |
2608 | .delay = { | |
2609 | .enable = 200, | |
2610 | .disable = 200, | |
2611 | }, | |
2612 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
06fc41b0 | 2613 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
9a2654c0 | 2614 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
1e29b840 MO |
2615 | }; |
2616 | ||
4ae13e48 LS |
2617 | static const struct display_timing innolux_g121i1_l01_timing = { |
2618 | .pixelclock = { 67450000, 71000000, 74550000 }, | |
2619 | .hactive = { 1280, 1280, 1280 }, | |
2620 | .hfront_porch = { 40, 80, 160 }, | |
2621 | .hback_porch = { 39, 79, 159 }, | |
2622 | .hsync_len = { 1, 1, 1 }, | |
2623 | .vactive = { 800, 800, 800 }, | |
2624 | .vfront_porch = { 5, 11, 100 }, | |
2625 | .vback_porch = { 4, 11, 99 }, | |
2626 | .vsync_len = { 1, 1, 1 }, | |
d731f661 LS |
2627 | }; |
2628 | ||
2629 | static const struct panel_desc innolux_g121i1_l01 = { | |
4ae13e48 LS |
2630 | .timings = &innolux_g121i1_l01_timing, |
2631 | .num_timings = 1, | |
d731f661 LS |
2632 | .bpc = 6, |
2633 | .size = { | |
2634 | .width = 261, | |
2635 | .height = 163, | |
2636 | }, | |
4ae13e48 LS |
2637 | .delay = { |
2638 | .enable = 200, | |
2639 | .disable = 20, | |
2640 | }, | |
a7c48a0a | 2641 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
9a2654c0 | 2642 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
d731f661 LS |
2643 | }; |
2644 | ||
90c53f2b MV |
2645 | static const struct display_timing innolux_g121x1_l03_timings = { |
2646 | .pixelclock = { 57500000, 64900000, 74400000 }, | |
2647 | .hactive = { 1024, 1024, 1024 }, | |
2648 | .hfront_porch = { 90, 140, 190 }, | |
2649 | .hback_porch = { 90, 140, 190 }, | |
2650 | .hsync_len = { 36, 40, 60 }, | |
2651 | .vactive = { 768, 768, 768 }, | |
2652 | .vfront_porch = { 2, 15, 30 }, | |
2653 | .vback_porch = { 2, 15, 30 }, | |
2654 | .vsync_len = { 2, 8, 20 }, | |
2655 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, | |
f8fa17ba AB |
2656 | }; |
2657 | ||
2658 | static const struct panel_desc innolux_g121x1_l03 = { | |
90c53f2b MV |
2659 | .timings = &innolux_g121x1_l03_timings, |
2660 | .num_timings = 1, | |
f8fa17ba AB |
2661 | .bpc = 6, |
2662 | .size = { | |
2663 | .width = 246, | |
2664 | .height = 185, | |
2665 | }, | |
2666 | .delay = { | |
2667 | .enable = 200, | |
2668 | .unprepare = 200, | |
2669 | .disable = 400, | |
2670 | }, | |
11ac72d0 MV |
2671 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
2672 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2673 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
f8fa17ba AB |
2674 | }; |
2675 | ||
f7ad2ce5 MV |
2676 | static const struct panel_desc innolux_g121xce_l01 = { |
2677 | .timings = &innolux_g121x1_l03_timings, | |
2678 | .num_timings = 1, | |
2679 | .bpc = 8, | |
2680 | .size = { | |
2681 | .width = 246, | |
2682 | .height = 185, | |
2683 | }, | |
2684 | .delay = { | |
2685 | .enable = 200, | |
2686 | .unprepare = 200, | |
2687 | .disable = 400, | |
2688 | }, | |
2689 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2690 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2691 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2692 | }; | |
2693 | ||
eae74888 | 2694 | static const struct display_timing innolux_g156hce_l01_timings = { |
438cf327 | 2695 | .pixelclock = { 120000000, 141860000, 150000000 }, |
eae74888 MV |
2696 | .hactive = { 1920, 1920, 1920 }, |
2697 | .hfront_porch = { 80, 90, 100 }, | |
2698 | .hback_porch = { 80, 90, 100 }, | |
2699 | .hsync_len = { 20, 30, 30 }, | |
2700 | .vactive = { 1080, 1080, 1080 }, | |
2701 | .vfront_porch = { 3, 10, 20 }, | |
2702 | .vback_porch = { 3, 10, 20 }, | |
2703 | .vsync_len = { 4, 10, 10 }, | |
2704 | }; | |
2705 | ||
2706 | static const struct panel_desc innolux_g156hce_l01 = { | |
2707 | .timings = &innolux_g156hce_l01_timings, | |
2708 | .num_timings = 1, | |
2709 | .bpc = 8, | |
2710 | .size = { | |
2711 | .width = 344, | |
2712 | .height = 194, | |
2713 | }, | |
2714 | .delay = { | |
2715 | .prepare = 1, /* T1+T2 */ | |
2716 | .enable = 450, /* T5 */ | |
2717 | .disable = 200, /* T6 */ | |
2718 | .unprepare = 10, /* T3+T7 */ | |
2719 | }, | |
2720 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2721 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2722 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2723 | }; | |
2724 | ||
ea44739d AB |
2725 | static const struct drm_display_mode innolux_n156bge_l21_mode = { |
2726 | .clock = 69300, | |
2727 | .hdisplay = 1366, | |
2728 | .hsync_start = 1366 + 16, | |
2729 | .hsync_end = 1366 + 16 + 34, | |
2730 | .htotal = 1366 + 16 + 34 + 50, | |
2731 | .vdisplay = 768, | |
2732 | .vsync_start = 768 + 2, | |
2733 | .vsync_end = 768 + 2 + 6, | |
2734 | .vtotal = 768 + 2 + 6 + 12, | |
ea44739d AB |
2735 | }; |
2736 | ||
2737 | static const struct panel_desc innolux_n156bge_l21 = { | |
2738 | .modes = &innolux_n156bge_l21_mode, | |
2739 | .num_modes = 1, | |
0208d511 | 2740 | .bpc = 6, |
ea44739d AB |
2741 | .size = { |
2742 | .width = 344, | |
2743 | .height = 193, | |
2744 | }, | |
85560829 | 2745 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c4715837 | 2746 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
94f07917 | 2747 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
ea44739d AB |
2748 | }; |
2749 | ||
bccac3f1 MG |
2750 | static const struct drm_display_mode innolux_zj070na_01p_mode = { |
2751 | .clock = 51501, | |
2752 | .hdisplay = 1024, | |
2753 | .hsync_start = 1024 + 128, | |
2754 | .hsync_end = 1024 + 128 + 64, | |
2755 | .htotal = 1024 + 128 + 64 + 128, | |
2756 | .vdisplay = 600, | |
2757 | .vsync_start = 600 + 16, | |
2758 | .vsync_end = 600 + 16 + 4, | |
2759 | .vtotal = 600 + 16 + 4 + 16, | |
bccac3f1 MG |
2760 | }; |
2761 | ||
2762 | static const struct panel_desc innolux_zj070na_01p = { | |
2763 | .modes = &innolux_zj070na_01p_mode, | |
2764 | .num_modes = 1, | |
2765 | .bpc = 6, | |
2766 | .size = { | |
81598846 TR |
2767 | .width = 154, |
2768 | .height = 90, | |
bccac3f1 MG |
2769 | }, |
2770 | }; | |
2771 | ||
14bf60c4 LM |
2772 | static const struct display_timing koe_tx14d24vm1bpa_timing = { |
2773 | .pixelclock = { 5580000, 5850000, 6200000 }, | |
2774 | .hactive = { 320, 320, 320 }, | |
2775 | .hfront_porch = { 30, 30, 30 }, | |
2776 | .hback_porch = { 30, 30, 30 }, | |
2777 | .hsync_len = { 1, 5, 17 }, | |
2778 | .vactive = { 240, 240, 240 }, | |
2779 | .vfront_porch = { 6, 6, 6 }, | |
2780 | .vback_porch = { 5, 5, 5 }, | |
2781 | .vsync_len = { 1, 2, 11 }, | |
2782 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2783 | }; | |
2784 | ||
2785 | static const struct panel_desc koe_tx14d24vm1bpa = { | |
2786 | .timings = &koe_tx14d24vm1bpa_timing, | |
2787 | .num_timings = 1, | |
2788 | .bpc = 6, | |
2789 | .size = { | |
2790 | .width = 115, | |
2791 | .height = 86, | |
2792 | }, | |
2793 | }; | |
2794 | ||
8a070524 LY |
2795 | static const struct display_timing koe_tx26d202vm0bwa_timing = { |
2796 | .pixelclock = { 151820000, 156720000, 159780000 }, | |
2797 | .hactive = { 1920, 1920, 1920 }, | |
2798 | .hfront_porch = { 105, 130, 142 }, | |
2799 | .hback_porch = { 45, 70, 82 }, | |
2800 | .hsync_len = { 30, 30, 30 }, | |
2801 | .vactive = { 1200, 1200, 1200}, | |
2802 | .vfront_porch = { 3, 5, 10 }, | |
2803 | .vback_porch = { 2, 5, 10 }, | |
2804 | .vsync_len = { 5, 5, 5 }, | |
37ce99b7 | 2805 | .flags = DISPLAY_FLAGS_DE_HIGH, |
8a070524 LY |
2806 | }; |
2807 | ||
2808 | static const struct panel_desc koe_tx26d202vm0bwa = { | |
2809 | .timings = &koe_tx26d202vm0bwa_timing, | |
2810 | .num_timings = 1, | |
2811 | .bpc = 8, | |
2812 | .size = { | |
2813 | .width = 217, | |
2814 | .height = 136, | |
2815 | }, | |
2816 | .delay = { | |
2817 | .prepare = 1000, | |
2818 | .enable = 1000, | |
2819 | .unprepare = 1000, | |
2820 | .disable = 1000, | |
2821 | }, | |
2822 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
c4715837 | 2823 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
8a070524 LY |
2824 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
2825 | }; | |
2826 | ||
8cfe8341 JT |
2827 | static const struct display_timing koe_tx31d200vm0baa_timing = { |
2828 | .pixelclock = { 39600000, 43200000, 48000000 }, | |
2829 | .hactive = { 1280, 1280, 1280 }, | |
2830 | .hfront_porch = { 16, 36, 56 }, | |
2831 | .hback_porch = { 16, 36, 56 }, | |
2832 | .hsync_len = { 8, 8, 8 }, | |
2833 | .vactive = { 480, 480, 480 }, | |
c9b6be7d SA |
2834 | .vfront_porch = { 6, 21, 33 }, |
2835 | .vback_porch = { 6, 21, 33 }, | |
8cfe8341 JT |
2836 | .vsync_len = { 8, 8, 8 }, |
2837 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2838 | }; | |
2839 | ||
2840 | static const struct panel_desc koe_tx31d200vm0baa = { | |
2841 | .timings = &koe_tx31d200vm0baa_timing, | |
2842 | .num_timings = 1, | |
2843 | .bpc = 6, | |
2844 | .size = { | |
2845 | .width = 292, | |
2846 | .height = 109, | |
2847 | }, | |
2848 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
9a2654c0 | 2849 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
8cfe8341 JT |
2850 | }; |
2851 | ||
8def22e5 LS |
2852 | static const struct display_timing kyo_tcg121xglp_timing = { |
2853 | .pixelclock = { 52000000, 65000000, 71000000 }, | |
2854 | .hactive = { 1024, 1024, 1024 }, | |
2855 | .hfront_porch = { 2, 2, 2 }, | |
2856 | .hback_porch = { 2, 2, 2 }, | |
2857 | .hsync_len = { 86, 124, 244 }, | |
2858 | .vactive = { 768, 768, 768 }, | |
2859 | .vfront_porch = { 2, 2, 2 }, | |
2860 | .vback_porch = { 2, 2, 2 }, | |
2861 | .vsync_len = { 6, 34, 73 }, | |
2862 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
2863 | }; | |
2864 | ||
2865 | static const struct panel_desc kyo_tcg121xglp = { | |
2866 | .timings = &kyo_tcg121xglp_timing, | |
2867 | .num_timings = 1, | |
2868 | .bpc = 8, | |
2869 | .size = { | |
2870 | .width = 246, | |
2871 | .height = 184, | |
2872 | }, | |
2873 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 2874 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
8def22e5 LS |
2875 | }; |
2876 | ||
27abdd83 PK |
2877 | static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { |
2878 | .clock = 7000, | |
2879 | .hdisplay = 320, | |
2880 | .hsync_start = 320 + 20, | |
2881 | .hsync_end = 320 + 20 + 30, | |
2882 | .htotal = 320 + 20 + 30 + 38, | |
2883 | .vdisplay = 240, | |
2884 | .vsync_start = 240 + 4, | |
2885 | .vsync_end = 240 + 4 + 3, | |
2886 | .vtotal = 240 + 4 + 3 + 15, | |
27abdd83 PK |
2887 | }; |
2888 | ||
2889 | static const struct panel_desc lemaker_bl035_rgb_002 = { | |
2890 | .modes = &lemaker_bl035_rgb_002_mode, | |
2891 | .num_modes = 1, | |
2892 | .size = { | |
2893 | .width = 70, | |
2894 | .height = 52, | |
2895 | }, | |
2896 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
2897 | .bus_flags = DRM_BUS_FLAG_DE_LOW, | |
2898 | }; | |
2899 | ||
c3ba13a0 AS |
2900 | static const struct display_timing lg_lb070wv8_timing = { |
2901 | .pixelclock = { 31950000, 33260000, 34600000 }, | |
2902 | .hactive = { 800, 800, 800 }, | |
2903 | .hfront_porch = { 88, 88, 88 }, | |
2904 | .hback_porch = { 88, 88, 88 }, | |
2905 | .hsync_len = { 80, 80, 80 }, | |
2906 | .vactive = { 480, 480, 480 }, | |
2907 | .vfront_porch = { 10, 10, 10 }, | |
2908 | .vback_porch = { 10, 10, 10 }, | |
2909 | .vsync_len = { 25, 25, 25 }, | |
dd015002 HS |
2910 | }; |
2911 | ||
2912 | static const struct panel_desc lg_lb070wv8 = { | |
c3ba13a0 AS |
2913 | .timings = &lg_lb070wv8_timing, |
2914 | .num_timings = 1, | |
a6ae2fe5 | 2915 | .bpc = 8, |
dd015002 HS |
2916 | .size = { |
2917 | .width = 151, | |
2918 | .height = 91, | |
2919 | }, | |
2920 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 2921 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
dd015002 HS |
2922 | }; |
2923 | ||
ac9b8b7f AB |
2924 | static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { |
2925 | .clock = 155127, | |
2926 | .hdisplay = 1920, | |
2927 | .hsync_start = 1920 + 128, | |
2928 | .hsync_end = 1920 + 128 + 20, | |
2929 | .htotal = 1920 + 128 + 20 + 12, | |
2930 | .vdisplay = 1200, | |
2931 | .vsync_start = 1200 + 19, | |
2932 | .vsync_end = 1200 + 19 + 4, | |
2933 | .vtotal = 1200 + 19 + 4 + 20, | |
2934 | }; | |
2935 | ||
2936 | static const struct panel_desc lincolntech_lcd185_101ct = { | |
2937 | .modes = &lincolntech_lcd185_101ct_mode, | |
2938 | .bpc = 8, | |
2939 | .num_modes = 1, | |
2940 | .size = { | |
2941 | .width = 217, | |
2942 | .height = 136, | |
2943 | }, | |
2944 | .delay = { | |
2945 | .prepare = 50, | |
2946 | .disable = 50, | |
2947 | }, | |
2948 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
2949 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
2950 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
2951 | }; | |
2952 | ||
5728fe7f MZ |
2953 | static const struct display_timing logictechno_lt161010_2nh_timing = { |
2954 | .pixelclock = { 26400000, 33300000, 46800000 }, | |
2955 | .hactive = { 800, 800, 800 }, | |
2956 | .hfront_porch = { 16, 210, 354 }, | |
2957 | .hback_porch = { 46, 46, 46 }, | |
2958 | .hsync_len = { 1, 20, 40 }, | |
2959 | .vactive = { 480, 480, 480 }, | |
2960 | .vfront_porch = { 7, 22, 147 }, | |
2961 | .vback_porch = { 23, 23, 23 }, | |
2962 | .vsync_len = { 1, 10, 20 }, | |
2963 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
2964 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
2965 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
2966 | }; | |
2967 | ||
2968 | static const struct panel_desc logictechno_lt161010_2nh = { | |
2969 | .timings = &logictechno_lt161010_2nh_timing, | |
2970 | .num_timings = 1, | |
876153ab | 2971 | .bpc = 6, |
5728fe7f MZ |
2972 | .size = { |
2973 | .width = 154, | |
2974 | .height = 86, | |
2975 | }, | |
2976 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
2977 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
2978 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
2979 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
2980 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
2981 | }; | |
2982 | ||
2983 | static const struct display_timing logictechno_lt170410_2whc_timing = { | |
2984 | .pixelclock = { 68900000, 71100000, 73400000 }, | |
2985 | .hactive = { 1280, 1280, 1280 }, | |
2986 | .hfront_porch = { 23, 60, 71 }, | |
2987 | .hback_porch = { 23, 60, 71 }, | |
2988 | .hsync_len = { 15, 40, 47 }, | |
2989 | .vactive = { 800, 800, 800 }, | |
2990 | .vfront_porch = { 5, 7, 10 }, | |
2991 | .vback_porch = { 5, 7, 10 }, | |
2992 | .vsync_len = { 6, 9, 12 }, | |
2993 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
2994 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
2995 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
2996 | }; | |
2997 | ||
2998 | static const struct panel_desc logictechno_lt170410_2whc = { | |
2999 | .timings = &logictechno_lt170410_2whc_timing, | |
3000 | .num_timings = 1, | |
876153ab | 3001 | .bpc = 8, |
5728fe7f MZ |
3002 | .size = { |
3003 | .width = 217, | |
3004 | .height = 136, | |
3005 | }, | |
3006 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
c4715837 | 3007 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
5728fe7f MZ |
3008 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3009 | }; | |
3010 | ||
19f036ea SA |
3011 | static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { |
3012 | .clock = 33000, | |
3013 | .hdisplay = 800, | |
3014 | .hsync_start = 800 + 112, | |
3015 | .hsync_end = 800 + 112 + 3, | |
3016 | .htotal = 800 + 112 + 3 + 85, | |
3017 | .vdisplay = 480, | |
3018 | .vsync_start = 480 + 38, | |
3019 | .vsync_end = 480 + 38 + 3, | |
3020 | .vtotal = 480 + 38 + 3 + 29, | |
3021 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
3022 | }; | |
3023 | ||
3024 | static const struct panel_desc logictechno_lttd800480070_l2rt = { | |
3025 | .modes = &logictechno_lttd800480070_l2rt_mode, | |
3026 | .num_modes = 1, | |
3027 | .bpc = 8, | |
3028 | .size = { | |
3029 | .width = 154, | |
3030 | .height = 86, | |
3031 | }, | |
3032 | .delay = { | |
3033 | .prepare = 45, | |
3034 | .enable = 100, | |
3035 | .disable = 100, | |
3036 | .unprepare = 45 | |
3037 | }, | |
3038 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3039 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
3040 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3041 | }; | |
3042 | ||
0c044f7d SA |
3043 | static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { |
3044 | .clock = 33000, | |
3045 | .hdisplay = 800, | |
3046 | .hsync_start = 800 + 154, | |
3047 | .hsync_end = 800 + 154 + 3, | |
3048 | .htotal = 800 + 154 + 3 + 43, | |
3049 | .vdisplay = 480, | |
3050 | .vsync_start = 480 + 47, | |
3051 | .vsync_end = 480 + 47 + 3, | |
3052 | .vtotal = 480 + 47 + 3 + 20, | |
3053 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
3054 | }; | |
3055 | ||
3056 | static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { | |
3057 | .modes = &logictechno_lttd800480070_l6wh_rt_mode, | |
3058 | .num_modes = 1, | |
3059 | .bpc = 8, | |
3060 | .size = { | |
3061 | .width = 154, | |
3062 | .height = 86, | |
3063 | }, | |
3064 | .delay = { | |
3065 | .prepare = 45, | |
3066 | .enable = 100, | |
3067 | .disable = 100, | |
3068 | .unprepare = 45 | |
3069 | }, | |
3070 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3071 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
3072 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3073 | }; | |
3074 | ||
0d35408a | 3075 | static const struct drm_display_mode logicpd_type_28_mode = { |
f873c5d8 | 3076 | .clock = 9107, |
0d35408a AF |
3077 | .hdisplay = 480, |
3078 | .hsync_start = 480 + 3, | |
3079 | .hsync_end = 480 + 3 + 42, | |
3080 | .htotal = 480 + 3 + 42 + 2, | |
3081 | ||
3082 | .vdisplay = 272, | |
3083 | .vsync_start = 272 + 2, | |
3084 | .vsync_end = 272 + 2 + 11, | |
3085 | .vtotal = 272 + 2 + 11 + 3, | |
0d35408a AF |
3086 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
3087 | }; | |
3088 | ||
3089 | static const struct panel_desc logicpd_type_28 = { | |
3090 | .modes = &logicpd_type_28_mode, | |
3091 | .num_modes = 1, | |
3092 | .bpc = 8, | |
3093 | .size = { | |
3094 | .width = 105, | |
3095 | .height = 67, | |
3096 | }, | |
3097 | .delay = { | |
3098 | .prepare = 200, | |
3099 | .enable = 200, | |
3100 | .unprepare = 200, | |
3101 | .disable = 200, | |
3102 | }, | |
3103 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3104 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | | |
3105 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, | |
efb94790 | 3106 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
0d35408a AF |
3107 | }; |
3108 | ||
f558d676 AB |
3109 | static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { |
3110 | .clock = 150275, | |
3111 | .hdisplay = 1920, | |
3112 | .hsync_start = 1920 + 32, | |
3113 | .hsync_end = 1920 + 32 + 52, | |
3114 | .htotal = 1920 + 32 + 52 + 24, | |
3115 | .vdisplay = 1200, | |
3116 | .vsync_start = 1200 + 24, | |
3117 | .vsync_end = 1200 + 24 + 8, | |
3118 | .vtotal = 1200 + 24 + 8 + 3, | |
3119 | }; | |
3120 | ||
3121 | static const struct panel_desc microtips_mf_101hiebcaf0_c = { | |
3122 | .modes = µtips_mf_101hiebcaf0_c_mode, | |
3123 | .bpc = 8, | |
3124 | .num_modes = 1, | |
3125 | .size = { | |
3126 | .width = 217, | |
3127 | .height = 136, | |
3128 | }, | |
3129 | .delay = { | |
3130 | .prepare = 50, | |
3131 | .disable = 50, | |
3132 | }, | |
3133 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
3134 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
3135 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
3136 | }; | |
3137 | ||
2c3d1bd2 AB |
3138 | static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { |
3139 | .clock = 93301, | |
3140 | .hdisplay = 1920, | |
3141 | .hsync_start = 1920 + 72, | |
3142 | .hsync_end = 1920 + 72 + 72, | |
3143 | .htotal = 1920 + 72 + 72 + 72, | |
3144 | .vdisplay = 720, | |
3145 | .vsync_start = 720 + 3, | |
3146 | .vsync_end = 720 + 3 + 3, | |
3147 | .vtotal = 720 + 3 + 3 + 2, | |
3148 | }; | |
3149 | ||
3150 | static const struct panel_desc microtips_mf_103hieb0ga0 = { | |
3151 | .modes = µtips_mf_103hieb0ga0_mode, | |
3152 | .bpc = 8, | |
3153 | .num_modes = 1, | |
3154 | .size = { | |
3155 | .width = 244, | |
3156 | .height = 92, | |
3157 | }, | |
3158 | .delay = { | |
3159 | .prepare = 50, | |
3160 | .disable = 50, | |
3161 | }, | |
3162 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
3163 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
3164 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
3165 | }; | |
3166 | ||
c8527b9a DA |
3167 | static const struct drm_display_mode mitsubishi_aa070mc01_mode = { |
3168 | .clock = 30400, | |
3169 | .hdisplay = 800, | |
3170 | .hsync_start = 800 + 0, | |
3171 | .hsync_end = 800 + 1, | |
3172 | .htotal = 800 + 0 + 1 + 160, | |
3173 | .vdisplay = 480, | |
3174 | .vsync_start = 480 + 0, | |
3175 | .vsync_end = 480 + 48 + 1, | |
3176 | .vtotal = 480 + 48 + 1 + 0, | |
3177 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
3178 | }; | |
3179 | ||
65c766ca LM |
3180 | static const struct panel_desc mitsubishi_aa070mc01 = { |
3181 | .modes = &mitsubishi_aa070mc01_mode, | |
3182 | .num_modes = 1, | |
3183 | .bpc = 8, | |
3184 | .size = { | |
3185 | .width = 152, | |
3186 | .height = 91, | |
3187 | }, | |
3188 | ||
3189 | .delay = { | |
3190 | .enable = 200, | |
3191 | .unprepare = 200, | |
3192 | .disable = 400, | |
3193 | }, | |
3194 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 3195 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
65c766ca LM |
3196 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
3197 | }; | |
3198 | ||
637d3fdc TW |
3199 | static const struct drm_display_mode mitsubishi_aa084xe01_mode = { |
3200 | .clock = 56234, | |
3201 | .hdisplay = 1024, | |
3202 | .hsync_start = 1024 + 24, | |
3203 | .hsync_end = 1024 + 24 + 63, | |
3204 | .htotal = 1024 + 24 + 63 + 1, | |
3205 | .vdisplay = 768, | |
3206 | .vsync_start = 768 + 3, | |
3207 | .vsync_end = 768 + 3 + 6, | |
3208 | .vtotal = 768 + 3 + 6 + 1, | |
3209 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, | |
3210 | }; | |
3211 | ||
3212 | static const struct panel_desc mitsubishi_aa084xe01 = { | |
3213 | .modes = &mitsubishi_aa084xe01_mode, | |
3214 | .num_modes = 1, | |
3215 | .bpc = 8, | |
3216 | .size = { | |
3217 | .width = 1024, | |
3218 | .height = 768, | |
3219 | }, | |
3220 | .bus_format = MEDIA_BUS_FMT_RGB565_1X16, | |
3221 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3222 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
3223 | }; | |
3224 | ||
a5d092d3 MV |
3225 | static const struct display_timing multi_inno_mi0700s4t_6_timing = { |
3226 | .pixelclock = { 29000000, 33000000, 38000000 }, | |
3227 | .hactive = { 800, 800, 800 }, | |
3228 | .hfront_porch = { 180, 210, 240 }, | |
3229 | .hback_porch = { 16, 16, 16 }, | |
3230 | .hsync_len = { 30, 30, 30 }, | |
3231 | .vactive = { 480, 480, 480 }, | |
3232 | .vfront_porch = { 12, 22, 32 }, | |
3233 | .vback_porch = { 10, 10, 10 }, | |
3234 | .vsync_len = { 13, 13, 13 }, | |
3235 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
3236 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
3237 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
3238 | }; | |
3239 | ||
3240 | static const struct panel_desc multi_inno_mi0700s4t_6 = { | |
3241 | .timings = &multi_inno_mi0700s4t_6_timing, | |
3242 | .num_timings = 1, | |
3243 | .bpc = 8, | |
3244 | .size = { | |
3245 | .width = 154, | |
3246 | .height = 86, | |
3247 | }, | |
3248 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3249 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
3250 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
3251 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
3252 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3253 | }; | |
3254 | ||
b55002b9 CN |
3255 | static const struct display_timing multi_inno_mi0800ft_9_timing = { |
3256 | .pixelclock = { 32000000, 40000000, 50000000 }, | |
3257 | .hactive = { 800, 800, 800 }, | |
3258 | .hfront_porch = { 16, 210, 354 }, | |
3259 | .hback_porch = { 6, 26, 45 }, | |
3260 | .hsync_len = { 1, 20, 40 }, | |
3261 | .vactive = { 600, 600, 600 }, | |
3262 | .vfront_porch = { 1, 12, 77 }, | |
3263 | .vback_porch = { 3, 13, 22 }, | |
3264 | .vsync_len = { 1, 10, 20 }, | |
3265 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
3266 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
3267 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
3268 | }; | |
3269 | ||
3270 | static const struct panel_desc multi_inno_mi0800ft_9 = { | |
3271 | .timings = &multi_inno_mi0800ft_9_timing, | |
3272 | .num_timings = 1, | |
3273 | .bpc = 8, | |
3274 | .size = { | |
3275 | .width = 162, | |
3276 | .height = 122, | |
3277 | }, | |
3278 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3279 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
3280 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
3281 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
3282 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3283 | }; | |
3284 | ||
81162f4b SR |
3285 | static const struct display_timing multi_inno_mi1010ait_1cp_timing = { |
3286 | .pixelclock = { 68900000, 70000000, 73400000 }, | |
3287 | .hactive = { 1280, 1280, 1280 }, | |
3288 | .hfront_porch = { 30, 60, 71 }, | |
3289 | .hback_porch = { 30, 60, 71 }, | |
3290 | .hsync_len = { 10, 10, 48 }, | |
3291 | .vactive = { 800, 800, 800 }, | |
3292 | .vfront_porch = { 5, 10, 10 }, | |
3293 | .vback_porch = { 5, 10, 10 }, | |
3294 | .vsync_len = { 5, 6, 13 }, | |
3295 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
3296 | DISPLAY_FLAGS_DE_HIGH, | |
3297 | }; | |
3298 | ||
3299 | static const struct panel_desc multi_inno_mi1010ait_1cp = { | |
3300 | .timings = &multi_inno_mi1010ait_1cp_timing, | |
3301 | .num_timings = 1, | |
3302 | .bpc = 8, | |
3303 | .size = { | |
3304 | .width = 217, | |
3305 | .height = 136, | |
3306 | }, | |
3307 | .delay = { | |
3308 | .enable = 50, | |
3309 | .disable = 50, | |
3310 | }, | |
3311 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
3312 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
3313 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
3314 | }; | |
3315 | ||
01bacc13 LS |
3316 | static const struct display_timing nec_nl12880bc20_05_timing = { |
3317 | .pixelclock = { 67000000, 71000000, 75000000 }, | |
3318 | .hactive = { 1280, 1280, 1280 }, | |
3319 | .hfront_porch = { 2, 30, 30 }, | |
3320 | .hback_porch = { 6, 100, 100 }, | |
3321 | .hsync_len = { 2, 30, 30 }, | |
3322 | .vactive = { 800, 800, 800 }, | |
3323 | .vfront_porch = { 5, 5, 5 }, | |
3324 | .vback_porch = { 11, 11, 11 }, | |
3325 | .vsync_len = { 7, 7, 7 }, | |
3326 | }; | |
3327 | ||
3328 | static const struct panel_desc nec_nl12880bc20_05 = { | |
3329 | .timings = &nec_nl12880bc20_05_timing, | |
3330 | .num_timings = 1, | |
3331 | .bpc = 8, | |
3332 | .size = { | |
3333 | .width = 261, | |
3334 | .height = 163, | |
3335 | }, | |
3336 | .delay = { | |
3337 | .enable = 50, | |
3338 | .disable = 50, | |
3339 | }, | |
3340 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 3341 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
01bacc13 LS |
3342 | }; |
3343 | ||
c6e87f91 | 3344 | static const struct drm_display_mode nec_nl4827hc19_05b_mode = { |
3345 | .clock = 10870, | |
3346 | .hdisplay = 480, | |
3347 | .hsync_start = 480 + 2, | |
3348 | .hsync_end = 480 + 2 + 41, | |
3349 | .htotal = 480 + 2 + 41 + 2, | |
3350 | .vdisplay = 272, | |
3351 | .vsync_start = 272 + 2, | |
3352 | .vsync_end = 272 + 2 + 4, | |
3353 | .vtotal = 272 + 2 + 4 + 2, | |
4bc390c6 | 3354 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
c6e87f91 | 3355 | }; |
3356 | ||
3357 | static const struct panel_desc nec_nl4827hc19_05b = { | |
3358 | .modes = &nec_nl4827hc19_05b_mode, | |
3359 | .num_modes = 1, | |
3360 | .bpc = 8, | |
3361 | .size = { | |
3362 | .width = 95, | |
3363 | .height = 54, | |
3364 | }, | |
2c80661d | 3365 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
88bc4178 | 3366 | .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
c6e87f91 | 3367 | }; |
3368 | ||
e6c2f066 MR |
3369 | static const struct drm_display_mode netron_dy_e231732_mode = { |
3370 | .clock = 66000, | |
3371 | .hdisplay = 1024, | |
3372 | .hsync_start = 1024 + 160, | |
3373 | .hsync_end = 1024 + 160 + 70, | |
3374 | .htotal = 1024 + 160 + 70 + 90, | |
3375 | .vdisplay = 600, | |
3376 | .vsync_start = 600 + 127, | |
3377 | .vsync_end = 600 + 127 + 20, | |
3378 | .vtotal = 600 + 127 + 20 + 3, | |
e6c2f066 MR |
3379 | }; |
3380 | ||
3381 | static const struct panel_desc netron_dy_e231732 = { | |
3382 | .modes = &netron_dy_e231732_mode, | |
3383 | .num_modes = 1, | |
3384 | .size = { | |
3385 | .width = 154, | |
3386 | .height = 87, | |
3387 | }, | |
3388 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
3389 | }; | |
3390 | ||
3b39ad7a TV |
3391 | static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { |
3392 | .clock = 9000, | |
3393 | .hdisplay = 480, | |
3394 | .hsync_start = 480 + 2, | |
3395 | .hsync_end = 480 + 2 + 41, | |
3396 | .htotal = 480 + 2 + 41 + 2, | |
3397 | .vdisplay = 272, | |
3398 | .vsync_start = 272 + 2, | |
3399 | .vsync_end = 272 + 2 + 10, | |
3400 | .vtotal = 272 + 2 + 10 + 2, | |
3b39ad7a TV |
3401 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3402 | }; | |
3403 | ||
3404 | static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { | |
3405 | .modes = &newhaven_nhd_43_480272ef_atxl_mode, | |
3406 | .num_modes = 1, | |
3407 | .bpc = 8, | |
3408 | .size = { | |
3409 | .width = 95, | |
3410 | .height = 54, | |
3411 | }, | |
3412 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
88bc4178 LP |
3413 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | |
3414 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, | |
8a4f5e11 | 3415 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
3b39ad7a TV |
3416 | }; |
3417 | ||
4177fa66 LS |
3418 | static const struct display_timing nlt_nl192108ac18_02d_timing = { |
3419 | .pixelclock = { 130000000, 148350000, 163000000 }, | |
3420 | .hactive = { 1920, 1920, 1920 }, | |
3421 | .hfront_porch = { 80, 100, 100 }, | |
3422 | .hback_porch = { 100, 120, 120 }, | |
3423 | .hsync_len = { 50, 60, 60 }, | |
3424 | .vactive = { 1080, 1080, 1080 }, | |
3425 | .vfront_porch = { 12, 30, 30 }, | |
3426 | .vback_porch = { 4, 10, 10 }, | |
3427 | .vsync_len = { 4, 5, 5 }, | |
3428 | }; | |
3429 | ||
3430 | static const struct panel_desc nlt_nl192108ac18_02d = { | |
3431 | .timings = &nlt_nl192108ac18_02d_timing, | |
3432 | .num_timings = 1, | |
3433 | .bpc = 8, | |
3434 | .size = { | |
3435 | .width = 344, | |
3436 | .height = 194, | |
3437 | }, | |
3438 | .delay = { | |
3439 | .unprepare = 500, | |
3440 | }, | |
3441 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 3442 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
4177fa66 LS |
3443 | }; |
3444 | ||
05ec0e45 FL |
3445 | static const struct drm_display_mode nvd_9128_mode = { |
3446 | .clock = 29500, | |
3447 | .hdisplay = 800, | |
3448 | .hsync_start = 800 + 130, | |
3449 | .hsync_end = 800 + 130 + 98, | |
3450 | .htotal = 800 + 0 + 130 + 98, | |
3451 | .vdisplay = 480, | |
3452 | .vsync_start = 480 + 10, | |
3453 | .vsync_end = 480 + 10 + 50, | |
3454 | .vtotal = 480 + 0 + 10 + 50, | |
3455 | }; | |
3456 | ||
3457 | static const struct panel_desc nvd_9128 = { | |
3458 | .modes = &nvd_9128_mode, | |
3459 | .num_modes = 1, | |
3460 | .bpc = 8, | |
3461 | .size = { | |
3462 | .width = 156, | |
3463 | .height = 88, | |
3464 | }, | |
3465 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 3466 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
05ec0e45 FL |
3467 | }; |
3468 | ||
a99fb626 GB |
3469 | static const struct display_timing okaya_rs800480t_7x0gp_timing = { |
3470 | .pixelclock = { 30000000, 30000000, 40000000 }, | |
3471 | .hactive = { 800, 800, 800 }, | |
3472 | .hfront_porch = { 40, 40, 40 }, | |
3473 | .hback_porch = { 40, 40, 40 }, | |
3474 | .hsync_len = { 1, 48, 48 }, | |
3475 | .vactive = { 480, 480, 480 }, | |
3476 | .vfront_porch = { 13, 13, 13 }, | |
3477 | .vback_porch = { 29, 29, 29 }, | |
3478 | .vsync_len = { 3, 3, 3 }, | |
3479 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
3480 | }; | |
3481 | ||
3482 | static const struct panel_desc okaya_rs800480t_7x0gp = { | |
3483 | .timings = &okaya_rs800480t_7x0gp_timing, | |
3484 | .num_timings = 1, | |
3485 | .bpc = 6, | |
3486 | .size = { | |
3487 | .width = 154, | |
3488 | .height = 87, | |
3489 | }, | |
3490 | .delay = { | |
3491 | .prepare = 41, | |
3492 | .enable = 50, | |
3493 | .unprepare = 41, | |
3494 | .disable = 50, | |
3495 | }, | |
3496 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
3497 | }; | |
3498 | ||
cf5c9e6d MR |
3499 | static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { |
3500 | .clock = 9000, | |
3501 | .hdisplay = 480, | |
3502 | .hsync_start = 480 + 5, | |
3503 | .hsync_end = 480 + 5 + 30, | |
3504 | .htotal = 480 + 5 + 30 + 10, | |
3505 | .vdisplay = 272, | |
3506 | .vsync_start = 272 + 8, | |
3507 | .vsync_end = 272 + 8 + 5, | |
3508 | .vtotal = 272 + 8 + 5 + 3, | |
cf5c9e6d MR |
3509 | }; |
3510 | ||
3511 | static const struct panel_desc olimex_lcd_olinuxino_43ts = { | |
3512 | .modes = &olimex_lcd_olinuxino_43ts_mode, | |
3513 | .num_modes = 1, | |
3514 | .size = { | |
30c6d7ab JL |
3515 | .width = 95, |
3516 | .height = 54, | |
cf5c9e6d | 3517 | }, |
5c2a7c6b | 3518 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, |
cf5c9e6d MR |
3519 | }; |
3520 | ||
91a759d4 LY |
3521 | static const struct display_timing ontat_kd50g21_40nt_a1_timing = { |
3522 | .pixelclock = { 30000000, 30000000, 50000000 }, | |
3523 | .hactive = { 800, 800, 800 }, | |
3524 | .hfront_porch = { 1, 40, 255 }, | |
3525 | .hback_porch = { 1, 40, 87 }, | |
3526 | .hsync_len = { 1, 48, 87 }, | |
3527 | .vactive = { 480, 480, 480 }, | |
3528 | .vfront_porch = { 1, 13, 255 }, | |
3529 | .vback_porch = { 1, 29, 29 }, | |
3530 | .vsync_len = { 3, 3, 31 }, | |
3531 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
3532 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, | |
3533 | }; | |
3534 | ||
3535 | static const struct panel_desc ontat_kd50g21_40nt_a1 = { | |
3536 | .timings = &ontat_kd50g21_40nt_a1_timing, | |
3537 | .num_timings = 1, | |
3538 | .bpc = 8, | |
3539 | .size = { | |
3540 | .width = 108, | |
3541 | .height = 65, | |
3542 | }, | |
3543 | .delay = { | |
3544 | .prepare = 147, /* 5 VSDs */ | |
3545 | .enable = 147, /* 5 VSDs */ | |
3546 | .disable = 88, /* 3 VSDs */ | |
3547 | .unprepare = 117, /* 4 VSDs */ | |
3548 | }, | |
3549 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3550 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
3551 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3552 | }; | |
3553 | ||
e8b6f561 EA |
3554 | /* |
3555 | * 800x480 CVT. The panel appears to be quite accepting, at least as far as | |
3556 | * pixel clocks, but this is the timing that was being used in the Adafruit | |
3557 | * installation instructions. | |
3558 | */ | |
3559 | static const struct drm_display_mode ontat_yx700wv03_mode = { | |
3560 | .clock = 29500, | |
3561 | .hdisplay = 800, | |
3562 | .hsync_start = 824, | |
3563 | .hsync_end = 896, | |
3564 | .htotal = 992, | |
3565 | .vdisplay = 480, | |
3566 | .vsync_start = 483, | |
3567 | .vsync_end = 493, | |
3568 | .vtotal = 500, | |
e8b6f561 EA |
3569 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3570 | }; | |
3571 | ||
3572 | /* | |
3573 | * Specification at: | |
3574 | * https://www.adafruit.com/images/product-files/2406/c3163.pdf | |
3575 | */ | |
3576 | static const struct panel_desc ontat_yx700wv03 = { | |
3577 | .modes = &ontat_yx700wv03_mode, | |
3578 | .num_modes = 1, | |
3579 | .bpc = 8, | |
3580 | .size = { | |
3581 | .width = 154, | |
3582 | .height = 83, | |
3583 | }, | |
5651e5e0 | 3584 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
e8b6f561 EA |
3585 | }; |
3586 | ||
9c31dcb6 | 3587 | static const struct drm_display_mode ortustech_com37h3m_mode = { |
855e764d | 3588 | .clock = 22230, |
9c31dcb6 | 3589 | .hdisplay = 480, |
855e764d NS |
3590 | .hsync_start = 480 + 40, |
3591 | .hsync_end = 480 + 40 + 10, | |
3592 | .htotal = 480 + 40 + 10 + 40, | |
9c31dcb6 NS |
3593 | .vdisplay = 640, |
3594 | .vsync_start = 640 + 4, | |
855e764d NS |
3595 | .vsync_end = 640 + 4 + 2, |
3596 | .vtotal = 640 + 4 + 2 + 4, | |
9c31dcb6 NS |
3597 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3598 | }; | |
3599 | ||
3600 | static const struct panel_desc ortustech_com37h3m = { | |
3601 | .modes = &ortustech_com37h3m_mode, | |
3602 | .num_modes = 1, | |
3603 | .bpc = 8, | |
3604 | .size = { | |
3605 | .width = 56, /* 56.16mm */ | |
3606 | .height = 75, /* 74.88mm */ | |
3607 | }, | |
3608 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 3609 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
9c31dcb6 NS |
3610 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, |
3611 | }; | |
3612 | ||
725c9d40 PZ |
3613 | static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { |
3614 | .clock = 25000, | |
3615 | .hdisplay = 480, | |
3616 | .hsync_start = 480 + 10, | |
3617 | .hsync_end = 480 + 10 + 10, | |
3618 | .htotal = 480 + 10 + 10 + 15, | |
3619 | .vdisplay = 800, | |
3620 | .vsync_start = 800 + 3, | |
3621 | .vsync_end = 800 + 3 + 3, | |
3622 | .vtotal = 800 + 3 + 3 + 3, | |
725c9d40 PZ |
3623 | }; |
3624 | ||
3625 | static const struct panel_desc ortustech_com43h4m85ulc = { | |
3626 | .modes = &ortustech_com43h4m85ulc_mode, | |
3627 | .num_modes = 1, | |
3b809516 | 3628 | .bpc = 6, |
725c9d40 PZ |
3629 | .size = { |
3630 | .width = 56, | |
3631 | .height = 93, | |
3632 | }, | |
f098f168 | 3633 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, |
88bc4178 | 3634 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
2ccedf46 | 3635 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
725c9d40 PZ |
3636 | }; |
3637 | ||
163f7a35 LP |
3638 | static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { |
3639 | .clock = 33000, | |
3640 | .hdisplay = 800, | |
3641 | .hsync_start = 800 + 210, | |
3642 | .hsync_end = 800 + 210 + 30, | |
3643 | .htotal = 800 + 210 + 30 + 16, | |
3644 | .vdisplay = 480, | |
3645 | .vsync_start = 480 + 22, | |
3646 | .vsync_end = 480 + 22 + 13, | |
3647 | .vtotal = 480 + 22 + 13 + 10, | |
163f7a35 LP |
3648 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
3649 | }; | |
3650 | ||
3651 | static const struct panel_desc osddisplays_osd070t1718_19ts = { | |
3652 | .modes = &osddisplays_osd070t1718_19ts_mode, | |
3653 | .num_modes = 1, | |
3654 | .bpc = 8, | |
3655 | .size = { | |
3656 | .width = 152, | |
3657 | .height = 91, | |
3658 | }, | |
3659 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
fb0629ee TV |
3660 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | |
3661 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, | |
a793f0ee | 3662 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
163f7a35 LP |
3663 | }; |
3664 | ||
4ba3e563 EH |
3665 | static const struct drm_display_mode pda_91_00156_a0_mode = { |
3666 | .clock = 33300, | |
3667 | .hdisplay = 800, | |
3668 | .hsync_start = 800 + 1, | |
3669 | .hsync_end = 800 + 1 + 64, | |
3670 | .htotal = 800 + 1 + 64 + 64, | |
3671 | .vdisplay = 480, | |
3672 | .vsync_start = 480 + 1, | |
3673 | .vsync_end = 480 + 1 + 23, | |
3674 | .vtotal = 480 + 1 + 23 + 22, | |
4ba3e563 EH |
3675 | }; |
3676 | ||
3677 | static const struct panel_desc pda_91_00156_a0 = { | |
3678 | .modes = &pda_91_00156_a0_mode, | |
3679 | .num_modes = 1, | |
3680 | .size = { | |
3681 | .width = 152, | |
3682 | .height = 91, | |
3683 | }, | |
3684 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3685 | }; | |
3686 | ||
fd6aa8f2 NM |
3687 | static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { |
3688 | .clock = 66500, | |
3689 | .hdisplay = 1280, | |
3690 | .hsync_start = 1280 + 12, | |
3691 | .hsync_end = 1280 + 12 + 20, | |
3692 | .htotal = 1280 + 12 + 20 + 56, | |
3693 | .vdisplay = 800, | |
3694 | .vsync_start = 800 + 1, | |
3695 | .vsync_end = 800 + 1 + 3, | |
3696 | .vtotal = 800 + 1 + 3 + 20, | |
3697 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, | |
3698 | }; | |
3699 | ||
3700 | static const struct panel_desc powertip_ph128800t006_zhc01 = { | |
3701 | .modes = &powertip_ph128800t006_zhc01_mode, | |
3702 | .num_modes = 1, | |
3703 | .bpc = 8, | |
3704 | .size = { | |
3705 | .width = 216, | |
3706 | .height = 135, | |
3707 | }, | |
3708 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
3709 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
3710 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
3711 | }; | |
3712 | ||
d69de69f MV |
3713 | static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { |
3714 | .clock = 24750, | |
3715 | .hdisplay = 800, | |
3716 | .hsync_start = 800 + 54, | |
3717 | .hsync_end = 800 + 54 + 2, | |
3718 | .htotal = 800 + 54 + 2 + 44, | |
3719 | .vdisplay = 480, | |
3720 | .vsync_start = 480 + 49, | |
3721 | .vsync_end = 480 + 49 + 2, | |
3722 | .vtotal = 480 + 49 + 2 + 22, | |
1c519980 | 3723 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
d69de69f MV |
3724 | }; |
3725 | ||
3726 | static const struct panel_desc powertip_ph800480t013_idf02 = { | |
3727 | .modes = &powertip_ph800480t013_idf02_mode, | |
3728 | .num_modes = 1, | |
65f4937f | 3729 | .bpc = 8, |
d69de69f MV |
3730 | .size = { |
3731 | .width = 152, | |
3732 | .height = 91, | |
3733 | }, | |
3734 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
3735 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
3736 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
3737 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3738 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3739 | }; | |
4ba3e563 | 3740 | |
8d1330d2 PF |
3741 | static const struct drm_display_mode primeview_pm070wl4_mode = { |
3742 | .clock = 32000, | |
3743 | .hdisplay = 800, | |
3744 | .hsync_start = 800 + 42, | |
3745 | .hsync_end = 800 + 42 + 128, | |
3746 | .htotal = 800 + 42 + 128 + 86, | |
3747 | .vdisplay = 480, | |
3748 | .vsync_start = 480 + 10, | |
3749 | .vsync_end = 480 + 10 + 2, | |
3750 | .vtotal = 480 + 10 + 2 + 33, | |
3751 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, | |
3752 | }; | |
3753 | ||
3754 | static const struct panel_desc primeview_pm070wl4 = { | |
3755 | .modes = &primeview_pm070wl4_mode, | |
3756 | .num_modes = 1, | |
3757 | .bpc = 6, | |
3758 | .size = { | |
3759 | .width = 152, | |
3760 | .height = 91, | |
3761 | }, | |
3762 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, | |
3763 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
3764 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3765 | }; | |
3766 | ||
d2a6f0f5 JW |
3767 | static const struct drm_display_mode qd43003c0_40_mode = { |
3768 | .clock = 9000, | |
3769 | .hdisplay = 480, | |
3770 | .hsync_start = 480 + 8, | |
3771 | .hsync_end = 480 + 8 + 4, | |
3772 | .htotal = 480 + 8 + 4 + 39, | |
3773 | .vdisplay = 272, | |
3774 | .vsync_start = 272 + 4, | |
3775 | .vsync_end = 272 + 4 + 10, | |
3776 | .vtotal = 272 + 4 + 10 + 2, | |
d2a6f0f5 JW |
3777 | }; |
3778 | ||
3779 | static const struct panel_desc qd43003c0_40 = { | |
3780 | .modes = &qd43003c0_40_mode, | |
3781 | .num_modes = 1, | |
3782 | .bpc = 8, | |
3783 | .size = { | |
3784 | .width = 95, | |
3785 | .height = 53, | |
3786 | }, | |
3787 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3788 | }; | |
3789 | ||
49179e66 AV |
3790 | static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { |
3791 | { /* 60 Hz */ | |
3792 | .clock = 10800, | |
3793 | .hdisplay = 480, | |
3794 | .hsync_start = 480 + 77, | |
3795 | .hsync_end = 480 + 77 + 41, | |
3796 | .htotal = 480 + 77 + 41 + 2, | |
3797 | .vdisplay = 272, | |
3798 | .vsync_start = 272 + 16, | |
3799 | .vsync_end = 272 + 16 + 10, | |
3800 | .vtotal = 272 + 16 + 10 + 2, | |
3801 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
3802 | }, | |
3803 | { /* 50 Hz */ | |
3804 | .clock = 10800, | |
3805 | .hdisplay = 480, | |
3806 | .hsync_start = 480 + 17, | |
3807 | .hsync_end = 480 + 17 + 41, | |
3808 | .htotal = 480 + 17 + 41 + 2, | |
3809 | .vdisplay = 272, | |
3810 | .vsync_start = 272 + 116, | |
3811 | .vsync_end = 272 + 116 + 10, | |
3812 | .vtotal = 272 + 116 + 10 + 2, | |
3813 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, | |
3814 | }, | |
3815 | }; | |
3816 | ||
3817 | static const struct panel_desc qishenglong_gopher2b_lcd = { | |
3818 | .modes = qishenglong_gopher2b_lcd_modes, | |
3819 | .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), | |
3820 | .bpc = 8, | |
3821 | .size = { | |
3822 | .width = 95, | |
3823 | .height = 54, | |
3824 | }, | |
3825 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3826 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
3827 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3828 | }; | |
3829 | ||
13cdd12a DB |
3830 | static const struct display_timing rocktech_rk043fn48h_timing = { |
3831 | .pixelclock = { 6000000, 9000000, 12000000 }, | |
3832 | .hactive = { 480, 480, 480 }, | |
3833 | .hback_porch = { 8, 43, 43 }, | |
c9424076 | 3834 | .hfront_porch = { 2, 8, 10 }, |
13cdd12a DB |
3835 | .hsync_len = { 1, 1, 1 }, |
3836 | .vactive = { 272, 272, 272 }, | |
c9424076 | 3837 | .vback_porch = { 2, 12, 26 }, |
13cdd12a DB |
3838 | .vfront_porch = { 1, 4, 4 }, |
3839 | .vsync_len = { 1, 10, 10 }, | |
3840 | .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | | |
536090b6 RGP |
3841 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | |
3842 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
13cdd12a DB |
3843 | }; |
3844 | ||
3845 | static const struct panel_desc rocktech_rk043fn48h = { | |
3846 | .timings = &rocktech_rk043fn48h_timing, | |
3847 | .num_timings = 1, | |
3848 | .bpc = 8, | |
3849 | .size = { | |
3850 | .width = 95, | |
3851 | .height = 54, | |
3852 | }, | |
3853 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
3854 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
3855 | }; | |
3856 | ||
23167fa9 JT |
3857 | static const struct display_timing rocktech_rk070er9427_timing = { |
3858 | .pixelclock = { 26400000, 33300000, 46800000 }, | |
3859 | .hactive = { 800, 800, 800 }, | |
3860 | .hfront_porch = { 16, 210, 354 }, | |
3861 | .hback_porch = { 46, 46, 46 }, | |
3862 | .hsync_len = { 1, 1, 1 }, | |
3863 | .vactive = { 480, 480, 480 }, | |
3864 | .vfront_porch = { 7, 22, 147 }, | |
3865 | .vback_porch = { 23, 23, 23 }, | |
3866 | .vsync_len = { 1, 1, 1 }, | |
3867 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
3868 | }; | |
3869 | ||
3870 | static const struct panel_desc rocktech_rk070er9427 = { | |
3871 | .timings = &rocktech_rk070er9427_timing, | |
3872 | .num_timings = 1, | |
3873 | .bpc = 6, | |
3874 | .size = { | |
3875 | .width = 154, | |
3876 | .height = 86, | |
3877 | }, | |
3878 | .delay = { | |
3879 | .prepare = 41, | |
3880 | .enable = 50, | |
3881 | .unprepare = 41, | |
3882 | .disable = 50, | |
3883 | }, | |
3884 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
3885 | }; | |
3886 | ||
f305047b JS |
3887 | static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { |
3888 | .clock = 71100, | |
3889 | .hdisplay = 1280, | |
3890 | .hsync_start = 1280 + 48, | |
3891 | .hsync_end = 1280 + 48 + 32, | |
3892 | .htotal = 1280 + 48 + 32 + 80, | |
3893 | .vdisplay = 800, | |
3894 | .vsync_start = 800 + 2, | |
3895 | .vsync_end = 800 + 2 + 5, | |
3896 | .vtotal = 800 + 2 + 5 + 16, | |
f305047b JS |
3897 | }; |
3898 | ||
3899 | static const struct panel_desc rocktech_rk101ii01d_ct = { | |
3900 | .modes = &rocktech_rk101ii01d_ct_mode, | |
f85b3f80 | 3901 | .bpc = 8, |
f305047b JS |
3902 | .num_modes = 1, |
3903 | .size = { | |
3904 | .width = 217, | |
3905 | .height = 136, | |
3906 | }, | |
3907 | .delay = { | |
3908 | .prepare = 50, | |
3909 | .disable = 50, | |
3910 | }, | |
3911 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
3912 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
3913 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
3914 | }; | |
3915 | ||
a6aa679a MJ |
3916 | static const struct display_timing samsung_ltl101al01_timing = { |
3917 | .pixelclock = { 66663000, 66663000, 66663000 }, | |
3918 | .hactive = { 1280, 1280, 1280 }, | |
3919 | .hfront_porch = { 18, 18, 18 }, | |
3920 | .hback_porch = { 36, 36, 36 }, | |
3921 | .hsync_len = { 16, 16, 16 }, | |
3922 | .vactive = { 800, 800, 800 }, | |
3923 | .vfront_porch = { 4, 4, 4 }, | |
3924 | .vback_porch = { 16, 16, 16 }, | |
3925 | .vsync_len = { 3, 3, 3 }, | |
3926 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, | |
3927 | }; | |
3928 | ||
3929 | static const struct panel_desc samsung_ltl101al01 = { | |
3930 | .timings = &samsung_ltl101al01_timing, | |
3931 | .num_timings = 1, | |
3932 | .bpc = 8, | |
3933 | .size = { | |
3934 | .width = 217, | |
3935 | .height = 135, | |
3936 | }, | |
3937 | .delay = { | |
3938 | .prepare = 40, | |
3939 | .enable = 300, | |
3940 | .disable = 200, | |
3941 | .unprepare = 600, | |
3942 | }, | |
3943 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
3944 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
3945 | }; | |
3946 | ||
6d54e3d2 MD |
3947 | static const struct drm_display_mode samsung_ltn101nt05_mode = { |
3948 | .clock = 54030, | |
3949 | .hdisplay = 1024, | |
3950 | .hsync_start = 1024 + 24, | |
3951 | .hsync_end = 1024 + 24 + 136, | |
3952 | .htotal = 1024 + 24 + 136 + 160, | |
3953 | .vdisplay = 600, | |
3954 | .vsync_start = 600 + 3, | |
3955 | .vsync_end = 600 + 3 + 6, | |
3956 | .vtotal = 600 + 3 + 6 + 61, | |
6d54e3d2 MD |
3957 | }; |
3958 | ||
3959 | static const struct panel_desc samsung_ltn101nt05 = { | |
3960 | .modes = &samsung_ltn101nt05_mode, | |
3961 | .num_modes = 1, | |
0208d511 | 3962 | .bpc = 6, |
6d54e3d2 | 3963 | .size = { |
81598846 TR |
3964 | .width = 223, |
3965 | .height = 125, | |
6d54e3d2 | 3966 | }, |
85560829 | 3967 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, |
c4715837 | 3968 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
94f07917 | 3969 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
6d54e3d2 MD |
3970 | }; |
3971 | ||
44c58c52 MR |
3972 | static const struct display_timing satoz_sat050at40h12r2_timing = { |
3973 | .pixelclock = {33300000, 33300000, 50000000}, | |
3974 | .hactive = {800, 800, 800}, | |
3975 | .hfront_porch = {16, 210, 354}, | |
3976 | .hback_porch = {46, 46, 46}, | |
3977 | .hsync_len = {1, 1, 40}, | |
3978 | .vactive = {480, 480, 480}, | |
3979 | .vfront_porch = {7, 22, 147}, | |
3980 | .vback_porch = {23, 23, 23}, | |
3981 | .vsync_len = {1, 1, 20}, | |
3982 | }; | |
3983 | ||
3984 | static const struct panel_desc satoz_sat050at40h12r2 = { | |
3985 | .timings = &satoz_sat050at40h12r2_timing, | |
3986 | .num_timings = 1, | |
3987 | .bpc = 8, | |
3988 | .size = { | |
3989 | .width = 108, | |
3990 | .height = 65, | |
3991 | }, | |
34ca6b53 | 3992 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, |
44c58c52 MR |
3993 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
3994 | }; | |
3995 | ||
dda0e4bd NS |
3996 | static const struct drm_display_mode sharp_lq070y3dg3b_mode = { |
3997 | .clock = 33260, | |
3998 | .hdisplay = 800, | |
3999 | .hsync_start = 800 + 64, | |
4000 | .hsync_end = 800 + 64 + 128, | |
4001 | .htotal = 800 + 64 + 128 + 64, | |
4002 | .vdisplay = 480, | |
4003 | .vsync_start = 480 + 8, | |
4004 | .vsync_end = 480 + 8 + 2, | |
4005 | .vtotal = 480 + 8 + 2 + 35, | |
dda0e4bd NS |
4006 | .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, |
4007 | }; | |
4008 | ||
4009 | static const struct panel_desc sharp_lq070y3dg3b = { | |
4010 | .modes = &sharp_lq070y3dg3b_mode, | |
4011 | .num_modes = 1, | |
4012 | .bpc = 8, | |
4013 | .size = { | |
4014 | .width = 152, /* 152.4mm */ | |
4015 | .height = 91, /* 91.4mm */ | |
4016 | }, | |
4017 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 4018 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | |
dda0e4bd NS |
4019 | DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, |
4020 | }; | |
4021 | ||
03e3ec9a VZ |
4022 | static const struct drm_display_mode sharp_lq035q7db03_mode = { |
4023 | .clock = 5500, | |
4024 | .hdisplay = 240, | |
4025 | .hsync_start = 240 + 16, | |
4026 | .hsync_end = 240 + 16 + 7, | |
4027 | .htotal = 240 + 16 + 7 + 5, | |
4028 | .vdisplay = 320, | |
4029 | .vsync_start = 320 + 9, | |
4030 | .vsync_end = 320 + 9 + 1, | |
4031 | .vtotal = 320 + 9 + 1 + 7, | |
03e3ec9a VZ |
4032 | }; |
4033 | ||
4034 | static const struct panel_desc sharp_lq035q7db03 = { | |
4035 | .modes = &sharp_lq035q7db03_mode, | |
4036 | .num_modes = 1, | |
4037 | .bpc = 6, | |
4038 | .size = { | |
4039 | .width = 54, | |
4040 | .height = 72, | |
4041 | }, | |
4042 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
4043 | }; | |
4044 | ||
592aa02b JC |
4045 | static const struct display_timing sharp_lq101k1ly04_timing = { |
4046 | .pixelclock = { 60000000, 65000000, 80000000 }, | |
4047 | .hactive = { 1280, 1280, 1280 }, | |
4048 | .hfront_porch = { 20, 20, 20 }, | |
4049 | .hback_porch = { 20, 20, 20 }, | |
4050 | .hsync_len = { 10, 10, 10 }, | |
4051 | .vactive = { 800, 800, 800 }, | |
4052 | .vfront_porch = { 4, 4, 4 }, | |
4053 | .vback_porch = { 4, 4, 4 }, | |
4054 | .vsync_len = { 4, 4, 4 }, | |
4055 | .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, | |
4056 | }; | |
4057 | ||
4058 | static const struct panel_desc sharp_lq101k1ly04 = { | |
4059 | .timings = &sharp_lq101k1ly04_timing, | |
4060 | .num_timings = 1, | |
4061 | .bpc = 8, | |
4062 | .size = { | |
4063 | .width = 217, | |
4064 | .height = 136, | |
4065 | }, | |
4066 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, | |
9a2654c0 | 4067 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
592aa02b JC |
4068 | }; |
4069 | ||
656b7596 | 4070 | static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { |
e6c21e6f PC |
4071 | { /* 50 Hz */ |
4072 | .clock = 3000, | |
4073 | .hdisplay = 240, | |
4074 | .hsync_start = 240 + 58, | |
4075 | .hsync_end = 240 + 58 + 1, | |
4076 | .htotal = 240 + 58 + 1 + 1, | |
4077 | .vdisplay = 160, | |
4078 | .vsync_start = 160 + 24, | |
4079 | .vsync_end = 160 + 24 + 10, | |
4080 | .vtotal = 160 + 24 + 10 + 6, | |
4081 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, | |
4082 | }, | |
656b7596 | 4083 | { /* 60 Hz */ |
c1bd32b5 | 4084 | .clock = 3000, |
656b7596 | 4085 | .hdisplay = 240, |
c1bd32b5 PC |
4086 | .hsync_start = 240 + 8, |
4087 | .hsync_end = 240 + 8 + 1, | |
4088 | .htotal = 240 + 8 + 1 + 1, | |
656b7596 | 4089 | .vdisplay = 160, |
c1bd32b5 PC |
4090 | .vsync_start = 160 + 24, |
4091 | .vsync_end = 160 + 24 + 10, | |
4092 | .vtotal = 160 + 24 + 10 + 6, | |
656b7596 PC |
4093 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, |
4094 | }, | |
f1bd37f3 PC |
4095 | }; |
4096 | ||
4097 | static const struct panel_desc sharp_ls020b1dd01d = { | |
656b7596 PC |
4098 | .modes = sharp_ls020b1dd01d_modes, |
4099 | .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), | |
f1bd37f3 PC |
4100 | .bpc = 6, |
4101 | .size = { | |
4102 | .width = 42, | |
4103 | .height = 28, | |
4104 | }, | |
4105 | .bus_format = MEDIA_BUS_FMT_RGB565_1X16, | |
4106 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | |
f5436f77 | 4107 | | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
f1bd37f3 PC |
4108 | | DRM_BUS_FLAG_SHARP_SIGNALS, |
4109 | }; | |
4110 | ||
9c6615bc BB |
4111 | static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { |
4112 | .clock = 33300, | |
4113 | .hdisplay = 800, | |
4114 | .hsync_start = 800 + 1, | |
4115 | .hsync_end = 800 + 1 + 64, | |
4116 | .htotal = 800 + 1 + 64 + 64, | |
4117 | .vdisplay = 480, | |
4118 | .vsync_start = 480 + 1, | |
4119 | .vsync_end = 480 + 1 + 23, | |
4120 | .vtotal = 480 + 1 + 23 + 22, | |
9c6615bc BB |
4121 | }; |
4122 | ||
4123 | static const struct panel_desc shelly_sca07010_bfn_lnn = { | |
4124 | .modes = &shelly_sca07010_bfn_lnn_mode, | |
4125 | .num_modes = 1, | |
4126 | .size = { | |
4127 | .width = 152, | |
4128 | .height = 91, | |
4129 | }, | |
4130 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
4131 | }; | |
4132 | ||
105235e4 PR |
4133 | static const struct drm_display_mode starry_kr070pe2t_mode = { |
4134 | .clock = 33000, | |
4135 | .hdisplay = 800, | |
4136 | .hsync_start = 800 + 209, | |
4137 | .hsync_end = 800 + 209 + 1, | |
4138 | .htotal = 800 + 209 + 1 + 45, | |
4139 | .vdisplay = 480, | |
4140 | .vsync_start = 480 + 22, | |
4141 | .vsync_end = 480 + 22 + 1, | |
4142 | .vtotal = 480 + 22 + 1 + 22, | |
105235e4 PR |
4143 | }; |
4144 | ||
4145 | static const struct panel_desc starry_kr070pe2t = { | |
4146 | .modes = &starry_kr070pe2t_mode, | |
4147 | .num_modes = 1, | |
4148 | .bpc = 8, | |
4149 | .size = { | |
4150 | .width = 152, | |
4151 | .height = 86, | |
4152 | }, | |
4153 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
4154 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, | |
41fad307 | 4155 | .connector_type = DRM_MODE_CONNECTOR_DPI, |
105235e4 PR |
4156 | }; |
4157 | ||
9ff92363 HS |
4158 | static const struct display_timing startek_kd070wvfpa_mode = { |
4159 | .pixelclock = { 25200000, 27200000, 30500000 }, | |
4160 | .hactive = { 800, 800, 800 }, | |
4161 | .hfront_porch = { 19, 44, 115 }, | |
4162 | .hback_porch = { 5, 16, 101 }, | |
4163 | .hsync_len = { 1, 2, 100 }, | |
4164 | .vactive = { 480, 480, 480 }, | |
4165 | .vfront_porch = { 5, 43, 67 }, | |
4166 | .vback_porch = { 5, 5, 67 }, | |
4167 | .vsync_len = { 1, 2, 66 }, | |
4168 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
4169 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | | |
4170 | DISPLAY_FLAGS_SYNC_POSEDGE, | |
4171 | }; | |
4172 | ||
4173 | static const struct panel_desc startek_kd070wvfpa = { | |
4174 | .timings = &startek_kd070wvfpa_mode, | |
4175 | .num_timings = 1, | |
4176 | .bpc = 8, | |
4177 | .size = { | |
4178 | .width = 152, | |
4179 | .height = 91, | |
4180 | }, | |
4181 | .delay = { | |
4182 | .prepare = 20, | |
4183 | .enable = 200, | |
4184 | .disable = 200, | |
4185 | }, | |
4186 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
4187 | .connector_type = DRM_MODE_CONNECTOR_DPI, | |
4188 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | | |
4189 | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | | |
4190 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, | |
4191 | }; | |
4192 | ||
938db276 MV |
4193 | static const struct display_timing tsd_tst043015cmhx_timing = { |
4194 | .pixelclock = { 5000000, 9000000, 12000000 }, | |
4195 | .hactive = { 480, 480, 480 }, | |
4196 | .hfront_porch = { 4, 5, 65 }, | |
4197 | .hback_porch = { 36, 40, 255 }, | |
4198 | .hsync_len = { 1, 1, 1 }, | |
4199 | .vactive = { 272, 272, 272 }, | |
4200 | .vfront_porch = { 2, 8, 97 }, | |
4201 | .vback_porch = { 3, 8, 31 }, | |
4202 | .vsync_len = { 1, 1, 1 }, | |
4203 | ||
4204 | .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | | |
4205 | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, | |
4206 | }; | |
4207 | ||
4208 | static const struct panel_desc tsd_tst043015cmhx = { | |
4209 | .timings = &tsd_tst043015cmhx_timing, | |
4210 | .num_timings = 1, | |
4211 | .bpc = 8, | |
4212 | .size = { | |
4213 | .width = 105, | |
4214 | .height = 67, | |
4215 | }, | |
4216 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
4217 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, | |
4218 | }; | |
4219 | ||
42161531 JS |
4220 | static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { |
4221 | .clock = 30000, | |
4222 | .hdisplay = 800, | |
4223 | .hsync_start = 800 + 39, | |
4224 | .hsync_end = 800 + 39 + 47, | |
4225 | .htotal = 800 + 39 + 47 + 39, | |
4226 | .vdisplay = 480, | |
4227 | .vsync_start = 480 + 13, | |
4228 | .vsync_end = 480 + 13 + 2, | |
4229 | .vtotal = 480 + 13 + 2 + 29, | |
42161531 JS |
4230 | }; |
4231 | ||
4232 | static const struct panel_desc tfc_s9700rtwv43tr_01b = { | |
4233 | .modes = &tfc_s9700rtwv43tr_01b_mode, | |
4234 | .num_modes = 1, | |
4235 | .bpc = 8, | |
4236 | .size = { | |
4237 | .width = 155, | |
4238 | .height = 90, | |
4239 | }, | |
4240 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 4241 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
42161531 JS |
4242 | }; |
4243 | ||
adb973ef GB |
4244 | static const struct display_timing tianma_tm070jdhg30_timing = { |
4245 | .pixelclock = { 62600000, 68200000, 78100000 }, | |
4246 | .hactive = { 1280, 1280, 1280 }, | |
4247 | .hfront_porch = { 15, 64, 159 }, | |
4248 | .hback_porch = { 5, 5, 5 }, | |
4249 | .hsync_len = { 1, 1, 256 }, | |
4250 | .vactive = { 800, 800, 800 }, | |
4251 | .vfront_porch = { 3, 40, 99 }, | |
4252 | .vback_porch = { 2, 2, 2 }, | |
4253 | .vsync_len = { 1, 1, 128 }, | |
4254 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
4255 | }; | |
4256 | ||
4257 | static const struct panel_desc tianma_tm070jdhg30 = { | |
4258 | .timings = &tianma_tm070jdhg30_timing, | |
4259 | .num_timings = 1, | |
4260 | .bpc = 8, | |
4261 | .size = { | |
4262 | .width = 151, | |
4263 | .height = 95, | |
4264 | }, | |
4265 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 4266 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
45dd7df2 | 4267 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
adb973ef GB |
4268 | }; |
4269 | ||
b3bfcdf8 MM |
4270 | static const struct panel_desc tianma_tm070jvhg33 = { |
4271 | .timings = &tianma_tm070jdhg30_timing, | |
4272 | .num_timings = 1, | |
4273 | .bpc = 8, | |
4274 | .size = { | |
4275 | .width = 150, | |
4276 | .height = 94, | |
4277 | }, | |
4278 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
4279 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
45dd7df2 | 4280 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
b3bfcdf8 MM |
4281 | }; |
4282 | ||
870a0b12 LM |
4283 | static const struct display_timing tianma_tm070rvhg71_timing = { |
4284 | .pixelclock = { 27700000, 29200000, 39600000 }, | |
4285 | .hactive = { 800, 800, 800 }, | |
4286 | .hfront_porch = { 12, 40, 212 }, | |
4287 | .hback_porch = { 88, 88, 88 }, | |
4288 | .hsync_len = { 1, 1, 40 }, | |
4289 | .vactive = { 480, 480, 480 }, | |
4290 | .vfront_porch = { 1, 13, 88 }, | |
4291 | .vback_porch = { 32, 32, 32 }, | |
4292 | .vsync_len = { 1, 1, 3 }, | |
4293 | .flags = DISPLAY_FLAGS_DE_HIGH, | |
4294 | }; | |
4295 | ||
4296 | static const struct panel_desc tianma_tm070rvhg71 = { | |
4297 | .timings = &tianma_tm070rvhg71_timing, | |
4298 | .num_timings = 1, | |
4299 | .bpc = 8, | |
4300 | .size = { | |
4301 | .width = 154, | |
4302 | .height = 86, | |
4303 | }, | |
4304 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
9a2654c0 | 4305 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
870a0b12 LM |
4306 | }; |
4307 | ||
d8a0d6a3 LW |
4308 | static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { |
4309 | { | |
4310 | .clock = 10000, | |
4311 | .hdisplay = 320, | |
4312 | .hsync_start = 320 + 50, | |
4313 | .hsync_end = 320 + 50 + 6, | |
4314 | .htotal = 320 + 50 + 6 + 38, | |
4315 | .vdisplay = 240, | |
4316 | .vsync_start = 240 + 3, | |
4317 | .vsync_end = 240 + 3 + 1, | |
4318 | .vtotal = 240 + 3 + 1 + 17, | |
d8a0d6a3 LW |
4319 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
4320 | }, | |
4321 | }; | |
4322 | ||
4323 | static const struct panel_desc ti_nspire_cx_lcd_panel = { | |
4324 | .modes = ti_nspire_cx_lcd_mode, | |
4325 | .num_modes = 1, | |
4326 | .bpc = 8, | |
4327 | .size = { | |
4328 | .width = 65, | |
4329 | .height = 49, | |
4330 | }, | |
4331 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 4332 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, |
d8a0d6a3 LW |
4333 | }; |
4334 | ||
4335 | static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { | |
4336 | { | |
4337 | .clock = 10000, | |
4338 | .hdisplay = 320, | |
4339 | .hsync_start = 320 + 6, | |
4340 | .hsync_end = 320 + 6 + 6, | |
4341 | .htotal = 320 + 6 + 6 + 6, | |
4342 | .vdisplay = 240, | |
4343 | .vsync_start = 240 + 0, | |
4344 | .vsync_end = 240 + 0 + 1, | |
4345 | .vtotal = 240 + 0 + 1 + 0, | |
d8a0d6a3 LW |
4346 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, |
4347 | }, | |
4348 | }; | |
4349 | ||
4350 | static const struct panel_desc ti_nspire_classic_lcd_panel = { | |
4351 | .modes = ti_nspire_classic_lcd_mode, | |
4352 | .num_modes = 1, | |
4353 | /* The grayscale panel has 8 bit for the color .. Y (black) */ | |
4354 | .bpc = 8, | |
4355 | .size = { | |
4356 | .width = 71, | |
4357 | .height = 53, | |
4358 | }, | |
4359 | /* This is the grayscale bus format */ | |
4360 | .bus_format = MEDIA_BUS_FMT_Y8_1X8, | |
f5436f77 | 4361 | .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
d8a0d6a3 LW |
4362 | }; |
4363 | ||
06e733e4 LS |
4364 | static const struct drm_display_mode toshiba_lt089ac29000_mode = { |
4365 | .clock = 79500, | |
4366 | .hdisplay = 1280, | |
4367 | .hsync_start = 1280 + 192, | |
4368 | .hsync_end = 1280 + 192 + 128, | |
4369 | .htotal = 1280 + 192 + 128 + 64, | |
4370 | .vdisplay = 768, | |
4371 | .vsync_start = 768 + 20, | |
4372 | .vsync_end = 768 + 20 + 7, | |
4373 | .vtotal = 768 + 20 + 7 + 3, | |
06e733e4 LS |
4374 | }; |
4375 | ||
4376 | static const struct panel_desc toshiba_lt089ac29000 = { | |
4377 | .modes = &toshiba_lt089ac29000_mode, | |
4378 | .num_modes = 1, | |
4379 | .size = { | |
4380 | .width = 194, | |
4381 | .height = 116, | |
4382 | }, | |
9781bd1d | 4383 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, |
c4715837 | 4384 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, |
9a2654c0 | 4385 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
06e733e4 LS |
4386 | }; |
4387 | ||
227e4f40 BD |
4388 | static const struct drm_display_mode tpk_f07a_0102_mode = { |
4389 | .clock = 33260, | |
4390 | .hdisplay = 800, | |
4391 | .hsync_start = 800 + 40, | |
4392 | .hsync_end = 800 + 40 + 128, | |
4393 | .htotal = 800 + 40 + 128 + 88, | |
4394 | .vdisplay = 480, | |
4395 | .vsync_start = 480 + 10, | |
4396 | .vsync_end = 480 + 10 + 2, | |
4397 | .vtotal = 480 + 10 + 2 + 33, | |
227e4f40 BD |
4398 | }; |
4399 | ||
4400 | static const struct panel_desc tpk_f07a_0102 = { | |
4401 | .modes = &tpk_f07a_0102_mode, | |
4402 | .num_modes = 1, | |
4403 | .size = { | |
4404 | .width = 152, | |
4405 | .height = 91, | |
4406 | }, | |
88bc4178 | 4407 | .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, |
227e4f40 BD |
4408 | }; |
4409 | ||
4410 | static const struct drm_display_mode tpk_f10a_0102_mode = { | |
4411 | .clock = 45000, | |
4412 | .hdisplay = 1024, | |
4413 | .hsync_start = 1024 + 176, | |
4414 | .hsync_end = 1024 + 176 + 5, | |
4415 | .htotal = 1024 + 176 + 5 + 88, | |
4416 | .vdisplay = 600, | |
4417 | .vsync_start = 600 + 20, | |
4418 | .vsync_end = 600 + 20 + 5, | |
4419 | .vtotal = 600 + 20 + 5 + 25, | |
227e4f40 BD |
4420 | }; |
4421 | ||
4422 | static const struct panel_desc tpk_f10a_0102 = { | |
4423 | .modes = &tpk_f10a_0102_mode, | |
4424 | .num_modes = 1, | |
4425 | .size = { | |
4426 | .width = 223, | |
4427 | .height = 125, | |
4428 | }, | |
4429 | }; | |
4430 | ||
06a9dc65 MS |
4431 | static const struct display_timing urt_umsh_8596md_timing = { |
4432 | .pixelclock = { 33260000, 33260000, 33260000 }, | |
4433 | .hactive = { 800, 800, 800 }, | |
4434 | .hfront_porch = { 41, 41, 41 }, | |
4435 | .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, | |
4436 | .hsync_len = { 71, 128, 128 }, | |
4437 | .vactive = { 480, 480, 480 }, | |
4438 | .vfront_porch = { 10, 10, 10 }, | |
4439 | .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, | |
4440 | .vsync_len = { 2, 2, 2 }, | |
4441 | .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | | |
4442 | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, | |
4443 | }; | |
4444 | ||
4445 | static const struct panel_desc urt_umsh_8596md_lvds = { | |
4446 | .timings = &urt_umsh_8596md_timing, | |
4447 | .num_timings = 1, | |
4448 | .bpc = 6, | |
4449 | .size = { | |
4450 | .width = 152, | |
4451 | .height = 91, | |
4452 | }, | |
4453 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
9a2654c0 | 4454 | .connector_type = DRM_MODE_CONNECTOR_LVDS, |
06a9dc65 MS |
4455 | }; |
4456 | ||
4457 | static const struct panel_desc urt_umsh_8596md_parallel = { | |
4458 | .timings = &urt_umsh_8596md_timing, | |
4459 | .num_timings = 1, | |
4460 | .bpc = 6, | |
4461 | .size = { | |
4462 | .width = 152, | |
4463 | .height = 91, | |
4464 | }, | |
4465 | .bus_format = MEDIA_BUS_FMT_RGB666_1X18, | |
4466 | }; | |
4467 | ||
1a84a308 NP |
4468 | static const struct drm_display_mode vivax_tpc9150_panel_mode = { |
4469 | .clock = 60000, | |
4470 | .hdisplay = 1024, | |
4471 | .hsync_start = 1024 + 160, | |
4472 | .hsync_end = 1024 + 160 + 100, | |
4473 | .htotal = 1024 + 160 + 100 + 60, | |
4474 | .vdisplay = 600, | |
4475 | .vsync_start = 600 + 12, | |
4476 | .vsync_end = 600 + 12 + 10, | |
4477 | .vtotal = 600 + 12 + 10 + 13, | |
4478 | }; | |
4479 | ||
4480 | static const struct panel_desc vivax_tpc9150_panel = { | |
4481 | .modes = &vivax_tpc9150_panel_mode, | |
4482 | .num_modes = 1, | |
4483 | .bpc = 6, | |
4484 | .size = { | |
4485 | .width = 200, | |
4486 | .height = 115, | |
4487 | }, | |
4488 | .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, | |
4489 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
4490 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
4491 | }; | |
4492 | ||
04206185 FE |
4493 | static const struct drm_display_mode vl050_8048nt_c01_mode = { |
4494 | .clock = 33333, | |
4495 | .hdisplay = 800, | |
4496 | .hsync_start = 800 + 210, | |
4497 | .hsync_end = 800 + 210 + 20, | |
4498 | .htotal = 800 + 210 + 20 + 46, | |
4499 | .vdisplay = 480, | |
4500 | .vsync_start = 480 + 22, | |
4501 | .vsync_end = 480 + 22 + 10, | |
4502 | .vtotal = 480 + 22 + 10 + 23, | |
04206185 FE |
4503 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
4504 | }; | |
4505 | ||
4506 | static const struct panel_desc vl050_8048nt_c01 = { | |
4507 | .modes = &vl050_8048nt_c01_mode, | |
4508 | .num_modes = 1, | |
4509 | .bpc = 8, | |
4510 | .size = { | |
4511 | .width = 120, | |
4512 | .height = 76, | |
4513 | }, | |
4514 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
f5436f77 | 4515 | .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, |
04206185 FE |
4516 | }; |
4517 | ||
e4bac408 RG |
4518 | static const struct drm_display_mode winstar_wf35ltiacd_mode = { |
4519 | .clock = 6410, | |
4520 | .hdisplay = 320, | |
4521 | .hsync_start = 320 + 20, | |
4522 | .hsync_end = 320 + 20 + 30, | |
4523 | .htotal = 320 + 20 + 30 + 38, | |
4524 | .vdisplay = 240, | |
4525 | .vsync_start = 240 + 4, | |
4526 | .vsync_end = 240 + 4 + 3, | |
4527 | .vtotal = 240 + 4 + 3 + 15, | |
e4bac408 RG |
4528 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
4529 | }; | |
4530 | ||
4531 | static const struct panel_desc winstar_wf35ltiacd = { | |
4532 | .modes = &winstar_wf35ltiacd_mode, | |
4533 | .num_modes = 1, | |
4534 | .bpc = 8, | |
4535 | .size = { | |
4536 | .width = 70, | |
4537 | .height = 53, | |
4538 | }, | |
4539 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
4540 | }; | |
4541 | ||
7a1f4fa4 JT |
4542 | static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { |
4543 | .clock = 51200, | |
4544 | .hdisplay = 1024, | |
4545 | .hsync_start = 1024 + 100, | |
4546 | .hsync_end = 1024 + 100 + 100, | |
4547 | .htotal = 1024 + 100 + 100 + 120, | |
4548 | .vdisplay = 600, | |
4549 | .vsync_start = 600 + 10, | |
4550 | .vsync_end = 600 + 10 + 10, | |
4551 | .vtotal = 600 + 10 + 10 + 15, | |
4552 | .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, | |
4553 | }; | |
4554 | ||
4555 | static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { | |
4556 | .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, | |
4557 | .num_modes = 1, | |
44379b98 | 4558 | .bpc = 8, |
7a1f4fa4 JT |
4559 | .size = { |
4560 | .width = 154, | |
4561 | .height = 90, | |
4562 | }, | |
4563 | .bus_flags = DRM_BUS_FLAG_DE_HIGH, | |
4564 | .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, | |
4565 | .connector_type = DRM_MODE_CONNECTOR_LVDS, | |
4566 | }; | |
4567 | ||
fcec4163 LW |
4568 | static const struct drm_display_mode arm_rtsm_mode[] = { |
4569 | { | |
4570 | .clock = 65000, | |
4571 | .hdisplay = 1024, | |
4572 | .hsync_start = 1024 + 24, | |
4573 | .hsync_end = 1024 + 24 + 136, | |
4574 | .htotal = 1024 + 24 + 136 + 160, | |
4575 | .vdisplay = 768, | |
4576 | .vsync_start = 768 + 3, | |
4577 | .vsync_end = 768 + 3 + 6, | |
4578 | .vtotal = 768 + 3 + 6 + 29, | |
fcec4163 LW |
4579 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
4580 | }, | |
4581 | }; | |
4582 | ||
4583 | static const struct panel_desc arm_rtsm = { | |
4584 | .modes = arm_rtsm_mode, | |
4585 | .num_modes = 1, | |
4586 | .bpc = 8, | |
4587 | .size = { | |
4588 | .width = 400, | |
4589 | .height = 300, | |
4590 | }, | |
4591 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, | |
4592 | }; | |
4593 | ||
280921de TR |
4594 | static const struct of_device_id platform_of_match[] = { |
4595 | { | |
bca684e6 JT |
4596 | .compatible = "ampire,am-1280800n3tzqw-t00h", |
4597 | .data = &ire_am_1280800n3tzqw_t00h, | |
4598 | }, { | |
966fea78 YF |
4599 | .compatible = "ampire,am-480272h3tmqw-t01h", |
4600 | .data = &ire_am_480272h3tmqw_t01h, | |
410bb213 GU |
4601 | }, { |
4602 | .compatible = "ampire,am-800480l1tmqw-t00h", | |
4603 | .data = &ire_am_800480l1tmqw_t00h, | |
966fea78 | 4604 | }, { |
1c550fa1 PZ |
4605 | .compatible = "ampire,am800480r3tmqwa1h", |
4606 | .data = &ire_am800480r3tmqwa1h, | |
103f06fd BK |
4607 | }, { |
4608 | .compatible = "ampire,am800600p5tmqw-tb8h", | |
4609 | .data = &ire_am800600p5tmqwtb8h, | |
fcec4163 LW |
4610 | }, { |
4611 | .compatible = "arm,rtsm-display", | |
4612 | .data = &arm_rtsm, | |
c479450f SS |
4613 | }, { |
4614 | .compatible = "armadeus,st0700-adapt", | |
4615 | .data = &armadeus_st0700_adapt, | |
1c550fa1 | 4616 | }, { |
280921de TR |
4617 | .compatible = "auo,b101aw03", |
4618 | .data = &auo_b101aw03, | |
dac746e0 RC |
4619 | }, { |
4620 | .compatible = "auo,b101xtn01", | |
4621 | .data = &auo_b101xtn01, | |
ad3e33fe DA |
4622 | }, { |
4623 | .compatible = "auo,b116xw03", | |
4624 | .data = &auo_b116xw03, | |
bccfaffb LM |
4625 | }, { |
4626 | .compatible = "auo,g070vvn01", | |
4627 | .data = &auo_g070vvn01, | |
4fb86404 AG |
4628 | }, { |
4629 | .compatible = "auo,g101evn010", | |
4630 | .data = &auo_g101evn010, | |
4451c287 CF |
4631 | }, { |
4632 | .compatible = "auo,g104sn02", | |
4633 | .data = &auo_g104sn02, | |
6c2b2cd3 PG |
4634 | }, { |
4635 | .compatible = "auo,g104stn01", | |
4636 | .data = &auo_g104stn01, | |
03e909ac SR |
4637 | }, { |
4638 | .compatible = "auo,g121ean01", | |
4639 | .data = &auo_g121ean01, | |
697035c6 LS |
4640 | }, { |
4641 | .compatible = "auo,g133han01", | |
4642 | .data = &auo_g133han01, | |
9e52d5c8 EA |
4643 | }, { |
4644 | .compatible = "auo,g156han04", | |
4645 | .data = &auo_g156han04, | |
d9ccd1f2 SR |
4646 | }, { |
4647 | .compatible = "auo,g156xtn01", | |
4648 | .data = &auo_g156xtn01, | |
8c31f603 LS |
4649 | }, { |
4650 | .compatible = "auo,g185han01", | |
4651 | .data = &auo_g185han01, | |
2f7b832f SR |
4652 | }, { |
4653 | .compatible = "auo,g190ean01", | |
4654 | .data = &auo_g190ean01, | |
70c0d5b7 LS |
4655 | }, { |
4656 | .compatible = "auo,p320hvn03", | |
4657 | .data = &auo_p320hvn03, | |
7ee933a1 HS |
4658 | }, { |
4659 | .compatible = "auo,t215hvn01", | |
4660 | .data = &auo_t215hvn01, | |
d47df633 PZ |
4661 | }, { |
4662 | .compatible = "avic,tm070ddh03", | |
4663 | .data = &avic_tm070ddh03, | |
7ad8b41c CYT |
4664 | }, { |
4665 | .compatible = "bananapi,s070wv20-ct16", | |
4666 | .data = &bananapi_s070wv20_ct16, | |
dc90214f TL |
4667 | }, { |
4668 | .compatible = "boe,bp082wx1-100", | |
4669 | .data = &boe_bp082wx1_100, | |
eeaddab4 TL |
4670 | }, { |
4671 | .compatible = "boe,bp101wx1-100", | |
4672 | .data = &boe_bp101wx1_100, | |
8bb7c7bc LY |
4673 | }, { |
4674 | .compatible = "boe,ev121wxm-n10-1850", | |
4675 | .data = &boe_ev121wxm_n10_1850, | |
ae8cf41b AH |
4676 | }, { |
4677 | .compatible = "boe,hv070wsa-100", | |
4678 | .data = &boe_hv070wsa | |
751b5841 JD |
4679 | }, { |
4680 | .compatible = "cct,cmt430b19n00", | |
4681 | .data = &cct_cmt430b19n00, | |
e58edce6 GB |
4682 | }, { |
4683 | .compatible = "cdtech,s043wq26h-ct7", | |
4684 | .data = &cdtech_s043wq26h_ct7, | |
0e3b67f6 MK |
4685 | }, { |
4686 | .compatible = "cdtech,s070pws19hp-fc21", | |
4687 | .data = &cdtech_s070pws19hp_fc21, | |
4688 | }, { | |
4689 | .compatible = "cdtech,s070swv29hg-dc44", | |
4690 | .data = &cdtech_s070swv29hg_dc44, | |
982f944e GB |
4691 | }, { |
4692 | .compatible = "cdtech,s070wv95-ct16", | |
4693 | .data = &cdtech_s070wv95_ct16, | |
07c913c4 MV |
4694 | }, { |
4695 | .compatible = "chefree,ch101olhlwh-002", | |
4696 | .data = &chefree_ch101olhlwh_002, | |
2cb35c80 RL |
4697 | }, { |
4698 | .compatible = "chunghwa,claa070wp03xg", | |
4699 | .data = &chunghwa_claa070wp03xg, | |
4c930757 SW |
4700 | }, { |
4701 | .compatible = "chunghwa,claa101wa01a", | |
4702 | .data = &chunghwa_claa101wa01a | |
280921de TR |
4703 | }, { |
4704 | .compatible = "chunghwa,claa101wb01", | |
4705 | .data = &chunghwa_claa101wb01 | |
4dd024d4 MV |
4706 | }, { |
4707 | .compatible = "dataimage,fg040346dsswbg04", | |
4708 | .data = &dataimage_fg040346dsswbg04, | |
803481d8 PO |
4709 | }, { |
4710 | .compatible = "dataimage,fg1001l0dsswmg01", | |
4711 | .data = &dataimage_fg1001l0dsswmg01, | |
97ceb1fb MV |
4712 | }, { |
4713 | .compatible = "dataimage,scf0700c48ggu18", | |
4714 | .data = &dataimage_scf0700c48ggu18, | |
0ca0c827 PZ |
4715 | }, { |
4716 | .compatible = "dlc,dlc0700yzg-1", | |
4717 | .data = &dlc_dlc0700yzg_1, | |
6cbe7cd1 MF |
4718 | }, { |
4719 | .compatible = "dlc,dlc1010gig", | |
4720 | .data = &dlc_dlc1010gig, | |
c2d24af6 AP |
4721 | }, { |
4722 | .compatible = "edt,et035012dm6", | |
4723 | .data = &edt_et035012dm6, | |
f08a2a1e SR |
4724 | }, { |
4725 | .compatible = "edt,etm0350g0dh6", | |
4726 | .data = &edt_etm0350g0dh6, | |
82d57a59 MCR |
4727 | }, { |
4728 | .compatible = "edt,etm043080dh6gp", | |
4729 | .data = &edt_etm043080dh6gp, | |
fd819bff MV |
4730 | }, { |
4731 | .compatible = "edt,etm0430g0dh6", | |
4732 | .data = &edt_etm0430g0dh6, | |
26ab0065 SA |
4733 | }, { |
4734 | .compatible = "edt,et057090dhu", | |
4735 | .data = &edt_et057090dhu, | |
fff5de45 PZ |
4736 | }, { |
4737 | .compatible = "edt,et070080dh6", | |
4738 | .data = &edt_etm0700g0dh6, | |
4739 | }, { | |
4740 | .compatible = "edt,etm0700g0dh6", | |
4741 | .data = &edt_etm0700g0dh6, | |
aa7e6455 JT |
4742 | }, { |
4743 | .compatible = "edt,etm0700g0bdh6", | |
4744 | .data = &edt_etm0700g0bdh6, | |
aad34de2 JT |
4745 | }, { |
4746 | .compatible = "edt,etm0700g0edh6", | |
4747 | .data = &edt_etm0700g0bdh6, | |
a6cc3c72 MF |
4748 | }, { |
4749 | .compatible = "edt,etml0700y5dha", | |
4750 | .data = &edt_etml0700y5dha, | |
aeb262c3 PF |
4751 | }, { |
4752 | .compatible = "edt,etml1010g3dra", | |
4753 | .data = &edt_etml1010g3dra, | |
e46f73fb SR |
4754 | }, { |
4755 | .compatible = "edt,etmv570g2dhu", | |
4756 | .data = &edt_etmv570g2dhu, | |
9746f5fe AF |
4757 | }, { |
4758 | .compatible = "eink,vb3300-kca", | |
4759 | .data = &eink_vb3300_kca, | |
1319f217 MW |
4760 | }, { |
4761 | .compatible = "evervision,vgg644804", | |
4762 | .data = &evervision_vgg644804, | |
9158e3c3 MF |
4763 | }, { |
4764 | .compatible = "evervision,vgg804821", | |
4765 | .data = &evervision_vgg804821, | |
102932b0 BB |
4766 | }, { |
4767 | .compatible = "foxlink,fl500wvr00-a0t", | |
4768 | .data = &foxlink_fl500wvr00_a0t, | |
7b6bd843 PC |
4769 | }, { |
4770 | .compatible = "frida,frd350h54004", | |
4771 | .data = &frida_frd350h54004, | |
3be20710 JT |
4772 | }, { |
4773 | .compatible = "friendlyarm,hd702e", | |
4774 | .data = &friendlyarm_hd702e, | |
d435a2af PZ |
4775 | }, { |
4776 | .compatible = "giantplus,gpg482739qs5", | |
4777 | .data = &giantplus_gpg482739qs5 | |
2c6574a9 PC |
4778 | }, { |
4779 | .compatible = "giantplus,gpm940b0", | |
4780 | .data = &giantplus_gpm940b0, | |
a853205e PZ |
4781 | }, { |
4782 | .compatible = "hannstar,hsd070pww1", | |
4783 | .data = &hannstar_hsd070pww1, | |
c0d607e5 EN |
4784 | }, { |
4785 | .compatible = "hannstar,hsd100pxn1", | |
4786 | .data = &hannstar_hsd100pxn1, | |
170a41e9 SR |
4787 | }, { |
4788 | .compatible = "hannstar,hsd101pww2", | |
4789 | .data = &hannstar_hsd101pww2, | |
61ac0bf8 LS |
4790 | }, { |
4791 | .compatible = "hit,tx23d38vm0caa", | |
4792 | .data = &hitachi_tx23d38vm0caa | |
41bcceb4 NF |
4793 | }, { |
4794 | .compatible = "innolux,at043tn24", | |
4795 | .data = &innolux_at043tn24, | |
4fc24ab3 RB |
4796 | }, { |
4797 | .compatible = "innolux,at070tn92", | |
4798 | .data = &innolux_at070tn92, | |
1993f598 RL |
4799 | }, { |
4800 | .compatible = "innolux,g070ace-l01", | |
4801 | .data = &innolux_g070ace_l01, | |
b9d228a5 ST |
4802 | }, { |
4803 | .compatible = "innolux,g070ace-lh3", | |
4804 | .data = &innolux_g070ace_lh3, | |
1e29b840 | 4805 | }, { |
a5d2ade6 CF |
4806 | .compatible = "innolux,g070y2-l01", |
4807 | .data = &innolux_g070y2_l01, | |
57a06e90 OR |
4808 | }, { |
4809 | .compatible = "innolux,g070y2-t02", | |
4810 | .data = &innolux_g070y2_t02, | |
a5d2ade6 CF |
4811 | }, { |
4812 | .compatible = "innolux,g101ice-l01", | |
1e29b840 | 4813 | .data = &innolux_g101ice_l01 |
d731f661 | 4814 | }, { |
a5d2ade6 | 4815 | .compatible = "innolux,g121i1-l01", |
d731f661 | 4816 | .data = &innolux_g121i1_l01 |
f8fa17ba AB |
4817 | }, { |
4818 | .compatible = "innolux,g121x1-l03", | |
4819 | .data = &innolux_g121x1_l03, | |
f7ad2ce5 MV |
4820 | }, { |
4821 | .compatible = "innolux,g121xce-l01", | |
4822 | .data = &innolux_g121xce_l01, | |
eae74888 MV |
4823 | }, { |
4824 | .compatible = "innolux,g156hce-l01", | |
4825 | .data = &innolux_g156hce_l01, | |
ea44739d AB |
4826 | }, { |
4827 | .compatible = "innolux,n156bge-l21", | |
4828 | .data = &innolux_n156bge_l21, | |
bccac3f1 MG |
4829 | }, { |
4830 | .compatible = "innolux,zj070na-01p", | |
4831 | .data = &innolux_zj070na_01p, | |
14bf60c4 LM |
4832 | }, { |
4833 | .compatible = "koe,tx14d24vm1bpa", | |
4834 | .data = &koe_tx14d24vm1bpa, | |
8a070524 LY |
4835 | }, { |
4836 | .compatible = "koe,tx26d202vm0bwa", | |
4837 | .data = &koe_tx26d202vm0bwa, | |
8cfe8341 JT |
4838 | }, { |
4839 | .compatible = "koe,tx31d200vm0baa", | |
4840 | .data = &koe_tx31d200vm0baa, | |
8def22e5 LS |
4841 | }, { |
4842 | .compatible = "kyo,tcg121xglp", | |
4843 | .data = &kyo_tcg121xglp, | |
27abdd83 PK |
4844 | }, { |
4845 | .compatible = "lemaker,bl035-rgb-002", | |
4846 | .data = &lemaker_bl035_rgb_002, | |
dd015002 HS |
4847 | }, { |
4848 | .compatible = "lg,lb070wv8", | |
4849 | .data = &lg_lb070wv8, | |
ac9b8b7f AB |
4850 | }, { |
4851 | .compatible = "lincolntech,lcd185-101ct", | |
4852 | .data = &lincolntech_lcd185_101ct, | |
0d35408a AF |
4853 | }, { |
4854 | .compatible = "logicpd,type28", | |
4855 | .data = &logicpd_type_28, | |
5728fe7f MZ |
4856 | }, { |
4857 | .compatible = "logictechno,lt161010-2nhc", | |
4858 | .data = &logictechno_lt161010_2nh, | |
4859 | }, { | |
4860 | .compatible = "logictechno,lt161010-2nhr", | |
4861 | .data = &logictechno_lt161010_2nh, | |
4862 | }, { | |
4863 | .compatible = "logictechno,lt170410-2whc", | |
4864 | .data = &logictechno_lt170410_2whc, | |
19f036ea SA |
4865 | }, { |
4866 | .compatible = "logictechno,lttd800480070-l2rt", | |
4867 | .data = &logictechno_lttd800480070_l2rt, | |
0c044f7d SA |
4868 | }, { |
4869 | .compatible = "logictechno,lttd800480070-l6wh-rt", | |
4870 | .data = &logictechno_lttd800480070_l6wh_rt, | |
f558d676 AB |
4871 | }, { |
4872 | .compatible = "microtips,mf-101hiebcaf0", | |
4873 | .data = µtips_mf_101hiebcaf0_c, | |
2c3d1bd2 AB |
4874 | }, { |
4875 | .compatible = "microtips,mf-103hieb0ga0", | |
4876 | .data = µtips_mf_103hieb0ga0, | |
65c766ca LM |
4877 | }, { |
4878 | .compatible = "mitsubishi,aa070mc01-ca1", | |
4879 | .data = &mitsubishi_aa070mc01, | |
637d3fdc TW |
4880 | }, { |
4881 | .compatible = "mitsubishi,aa084xe01", | |
4882 | .data = &mitsubishi_aa084xe01, | |
a5d092d3 MV |
4883 | }, { |
4884 | .compatible = "multi-inno,mi0700s4t-6", | |
4885 | .data = &multi_inno_mi0700s4t_6, | |
b55002b9 CN |
4886 | }, { |
4887 | .compatible = "multi-inno,mi0800ft-9", | |
4888 | .data = &multi_inno_mi0800ft_9, | |
81162f4b SR |
4889 | }, { |
4890 | .compatible = "multi-inno,mi1010ait-1cp", | |
4891 | .data = &multi_inno_mi1010ait_1cp, | |
01bacc13 LS |
4892 | }, { |
4893 | .compatible = "nec,nl12880bc20-05", | |
4894 | .data = &nec_nl12880bc20_05, | |
c6e87f91 | 4895 | }, { |
4896 | .compatible = "nec,nl4827hc19-05b", | |
4897 | .data = &nec_nl4827hc19_05b, | |
e6c2f066 MR |
4898 | }, { |
4899 | .compatible = "netron-dy,e231732", | |
4900 | .data = &netron_dy_e231732, | |
3b39ad7a TV |
4901 | }, { |
4902 | .compatible = "newhaven,nhd-4.3-480272ef-atxl", | |
4903 | .data = &newhaven_nhd_43_480272ef_atxl, | |
4177fa66 LS |
4904 | }, { |
4905 | .compatible = "nlt,nl192108ac18-02d", | |
4906 | .data = &nlt_nl192108ac18_02d, | |
05ec0e45 FL |
4907 | }, { |
4908 | .compatible = "nvd,9128", | |
4909 | .data = &nvd_9128, | |
a99fb626 GB |
4910 | }, { |
4911 | .compatible = "okaya,rs800480t-7x0gp", | |
4912 | .data = &okaya_rs800480t_7x0gp, | |
cf5c9e6d MR |
4913 | }, { |
4914 | .compatible = "olimex,lcd-olinuxino-43-ts", | |
4915 | .data = &olimex_lcd_olinuxino_43ts, | |
91a759d4 LY |
4916 | }, { |
4917 | .compatible = "ontat,kd50g21-40nt-a1", | |
4918 | .data = &ontat_kd50g21_40nt_a1, | |
e8b6f561 EA |
4919 | }, { |
4920 | .compatible = "ontat,yx700wv03", | |
4921 | .data = &ontat_yx700wv03, | |
9c31dcb6 NS |
4922 | }, { |
4923 | .compatible = "ortustech,com37h3m05dtc", | |
4924 | .data = &ortustech_com37h3m, | |
4925 | }, { | |
4926 | .compatible = "ortustech,com37h3m99dtc", | |
4927 | .data = &ortustech_com37h3m, | |
725c9d40 PZ |
4928 | }, { |
4929 | .compatible = "ortustech,com43h4m85ulc", | |
4930 | .data = &ortustech_com43h4m85ulc, | |
163f7a35 LP |
4931 | }, { |
4932 | .compatible = "osddisplays,osd070t1718-19ts", | |
4933 | .data = &osddisplays_osd070t1718_19ts, | |
4ba3e563 EH |
4934 | }, { |
4935 | .compatible = "pda,91-00156-a0", | |
4936 | .data = &pda_91_00156_a0, | |
fd6aa8f2 NM |
4937 | }, { |
4938 | .compatible = "powertip,ph128800t006-zhc01", | |
4939 | .data = &powertip_ph128800t006_zhc01, | |
d69de69f MV |
4940 | }, { |
4941 | .compatible = "powertip,ph800480t013-idf02", | |
4942 | .data = &powertip_ph800480t013_idf02, | |
8d1330d2 PF |
4943 | }, { |
4944 | .compatible = "primeview,pm070wl4", | |
4945 | .data = &primeview_pm070wl4, | |
d2a6f0f5 JW |
4946 | }, { |
4947 | .compatible = "qiaodian,qd43003c0-40", | |
4948 | .data = &qd43003c0_40, | |
49179e66 AV |
4949 | }, { |
4950 | .compatible = "qishenglong,gopher2b-lcd", | |
4951 | .data = &qishenglong_gopher2b_lcd, | |
13cdd12a DB |
4952 | }, { |
4953 | .compatible = "rocktech,rk043fn48h", | |
4954 | .data = &rocktech_rk043fn48h, | |
23167fa9 JT |
4955 | }, { |
4956 | .compatible = "rocktech,rk070er9427", | |
4957 | .data = &rocktech_rk070er9427, | |
f305047b JS |
4958 | }, { |
4959 | .compatible = "rocktech,rk101ii01d-ct", | |
4960 | .data = &rocktech_rk101ii01d_ct, | |
a6aa679a MJ |
4961 | }, { |
4962 | .compatible = "samsung,ltl101al01", | |
4963 | .data = &samsung_ltl101al01, | |
6d54e3d2 MD |
4964 | }, { |
4965 | .compatible = "samsung,ltn101nt05", | |
4966 | .data = &samsung_ltn101nt05, | |
44c58c52 MR |
4967 | }, { |
4968 | .compatible = "satoz,sat050at40h12r2", | |
4969 | .data = &satoz_sat050at40h12r2, | |
03e3ec9a VZ |
4970 | }, { |
4971 | .compatible = "sharp,lq035q7db03", | |
4972 | .data = &sharp_lq035q7db03, | |
dda0e4bd NS |
4973 | }, { |
4974 | .compatible = "sharp,lq070y3dg3b", | |
4975 | .data = &sharp_lq070y3dg3b, | |
592aa02b JC |
4976 | }, { |
4977 | .compatible = "sharp,lq101k1ly04", | |
4978 | .data = &sharp_lq101k1ly04, | |
f1bd37f3 PC |
4979 | }, { |
4980 | .compatible = "sharp,ls020b1dd01d", | |
4981 | .data = &sharp_ls020b1dd01d, | |
9c6615bc BB |
4982 | }, { |
4983 | .compatible = "shelly,sca07010-bfn-lnn", | |
4984 | .data = &shelly_sca07010_bfn_lnn, | |
105235e4 PR |
4985 | }, { |
4986 | .compatible = "starry,kr070pe2t", | |
4987 | .data = &starry_kr070pe2t, | |
9ff92363 HS |
4988 | }, { |
4989 | .compatible = "startek,kd070wvfpa", | |
4990 | .data = &startek_kd070wvfpa, | |
938db276 MV |
4991 | }, { |
4992 | .compatible = "team-source-display,tst043015cmhx", | |
4993 | .data = &tsd_tst043015cmhx, | |
42161531 JS |
4994 | }, { |
4995 | .compatible = "tfc,s9700rtwv43tr-01b", | |
4996 | .data = &tfc_s9700rtwv43tr_01b, | |
adb973ef GB |
4997 | }, { |
4998 | .compatible = "tianma,tm070jdhg30", | |
4999 | .data = &tianma_tm070jdhg30, | |
b3bfcdf8 MM |
5000 | }, { |
5001 | .compatible = "tianma,tm070jvhg33", | |
5002 | .data = &tianma_tm070jvhg33, | |
870a0b12 LM |
5003 | }, { |
5004 | .compatible = "tianma,tm070rvhg71", | |
5005 | .data = &tianma_tm070rvhg71, | |
d8a0d6a3 LW |
5006 | }, { |
5007 | .compatible = "ti,nspire-cx-lcd-panel", | |
5008 | .data = &ti_nspire_cx_lcd_panel, | |
5009 | }, { | |
5010 | .compatible = "ti,nspire-classic-lcd-panel", | |
5011 | .data = &ti_nspire_classic_lcd_panel, | |
06e733e4 LS |
5012 | }, { |
5013 | .compatible = "toshiba,lt089ac29000", | |
5014 | .data = &toshiba_lt089ac29000, | |
227e4f40 BD |
5015 | }, { |
5016 | .compatible = "tpk,f07a-0102", | |
5017 | .data = &tpk_f07a_0102, | |
5018 | }, { | |
5019 | .compatible = "tpk,f10a-0102", | |
5020 | .data = &tpk_f10a_0102, | |
06a9dc65 MS |
5021 | }, { |
5022 | .compatible = "urt,umsh-8596md-t", | |
5023 | .data = &urt_umsh_8596md_parallel, | |
5024 | }, { | |
5025 | .compatible = "urt,umsh-8596md-1t", | |
5026 | .data = &urt_umsh_8596md_parallel, | |
5027 | }, { | |
5028 | .compatible = "urt,umsh-8596md-7t", | |
5029 | .data = &urt_umsh_8596md_parallel, | |
5030 | }, { | |
5031 | .compatible = "urt,umsh-8596md-11t", | |
5032 | .data = &urt_umsh_8596md_lvds, | |
5033 | }, { | |
5034 | .compatible = "urt,umsh-8596md-19t", | |
5035 | .data = &urt_umsh_8596md_lvds, | |
5036 | }, { | |
5037 | .compatible = "urt,umsh-8596md-20t", | |
5038 | .data = &urt_umsh_8596md_parallel, | |
1a84a308 NP |
5039 | }, { |
5040 | .compatible = "vivax,tpc9150-panel", | |
5041 | .data = &vivax_tpc9150_panel, | |
04206185 FE |
5042 | }, { |
5043 | .compatible = "vxt,vl050-8048nt-c01", | |
5044 | .data = &vl050_8048nt_c01, | |
e4bac408 RG |
5045 | }, { |
5046 | .compatible = "winstar,wf35ltiacd", | |
5047 | .data = &winstar_wf35ltiacd, | |
7a1f4fa4 JT |
5048 | }, { |
5049 | .compatible = "yes-optoelectronics,ytc700tlag-05-201c", | |
5050 | .data = &yes_optoelectronics_ytc700tlag_05_201c, | |
4a1d0dbc SR |
5051 | }, { |
5052 | /* Must be the last entry */ | |
5053 | .compatible = "panel-dpi", | |
5054 | .data = &panel_dpi, | |
280921de TR |
5055 | }, { |
5056 | /* sentinel */ | |
5057 | } | |
5058 | }; | |
5059 | MODULE_DEVICE_TABLE(of, platform_of_match); | |
5060 | ||
5061 | static int panel_simple_platform_probe(struct platform_device *pdev) | |
5062 | { | |
a7f880bc | 5063 | const struct panel_desc *desc; |
280921de | 5064 | |
a7f880bc GU |
5065 | desc = of_device_get_match_data(&pdev->dev); |
5066 | if (!desc) | |
280921de TR |
5067 | return -ENODEV; |
5068 | ||
a7f880bc | 5069 | return panel_simple_probe(&pdev->dev, desc); |
280921de TR |
5070 | } |
5071 | ||
cef3776d | 5072 | static void panel_simple_platform_remove(struct platform_device *pdev) |
280921de | 5073 | { |
d72ac4bb | 5074 | panel_simple_remove(&pdev->dev); |
280921de TR |
5075 | } |
5076 | ||
d02fd93e TR |
5077 | static void panel_simple_platform_shutdown(struct platform_device *pdev) |
5078 | { | |
5079 | panel_simple_shutdown(&pdev->dev); | |
5080 | } | |
5081 | ||
3235b0f2 DA |
5082 | static const struct dev_pm_ops panel_simple_pm_ops = { |
5083 | SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) | |
5084 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
5085 | pm_runtime_force_resume) | |
5086 | }; | |
5087 | ||
280921de TR |
5088 | static struct platform_driver panel_simple_platform_driver = { |
5089 | .driver = { | |
5090 | .name = "panel-simple", | |
280921de | 5091 | .of_match_table = platform_of_match, |
3235b0f2 | 5092 | .pm = &panel_simple_pm_ops, |
280921de TR |
5093 | }, |
5094 | .probe = panel_simple_platform_probe, | |
cef3776d | 5095 | .remove_new = panel_simple_platform_remove, |
d02fd93e | 5096 | .shutdown = panel_simple_platform_shutdown, |
280921de TR |
5097 | }; |
5098 | ||
210fcd9d TR |
5099 | struct panel_desc_dsi { |
5100 | struct panel_desc desc; | |
5101 | ||
462658b8 | 5102 | unsigned long flags; |
210fcd9d TR |
5103 | enum mipi_dsi_pixel_format format; |
5104 | unsigned int lanes; | |
5105 | }; | |
5106 | ||
d718d79e TR |
5107 | static const struct drm_display_mode auo_b080uan01_mode = { |
5108 | .clock = 154500, | |
5109 | .hdisplay = 1200, | |
5110 | .hsync_start = 1200 + 62, | |
5111 | .hsync_end = 1200 + 62 + 4, | |
5112 | .htotal = 1200 + 62 + 4 + 62, | |
5113 | .vdisplay = 1920, | |
5114 | .vsync_start = 1920 + 9, | |
5115 | .vsync_end = 1920 + 9 + 2, | |
5116 | .vtotal = 1920 + 9 + 2 + 8, | |
d718d79e TR |
5117 | }; |
5118 | ||
5119 | static const struct panel_desc_dsi auo_b080uan01 = { | |
5120 | .desc = { | |
5121 | .modes = &auo_b080uan01_mode, | |
5122 | .num_modes = 1, | |
5123 | .bpc = 8, | |
5124 | .size = { | |
5125 | .width = 108, | |
5126 | .height = 272, | |
5127 | }, | |
cb62cdec | 5128 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
d718d79e TR |
5129 | }, |
5130 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, | |
5131 | .format = MIPI_DSI_FMT_RGB888, | |
5132 | .lanes = 4, | |
5133 | }; | |
5134 | ||
c8521969 CZ |
5135 | static const struct drm_display_mode boe_tv080wum_nl0_mode = { |
5136 | .clock = 160000, | |
5137 | .hdisplay = 1200, | |
5138 | .hsync_start = 1200 + 120, | |
5139 | .hsync_end = 1200 + 120 + 20, | |
5140 | .htotal = 1200 + 120 + 20 + 21, | |
5141 | .vdisplay = 1920, | |
5142 | .vsync_start = 1920 + 21, | |
5143 | .vsync_end = 1920 + 21 + 3, | |
5144 | .vtotal = 1920 + 21 + 3 + 18, | |
c8521969 CZ |
5145 | .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, |
5146 | }; | |
5147 | ||
5148 | static const struct panel_desc_dsi boe_tv080wum_nl0 = { | |
5149 | .desc = { | |
5150 | .modes = &boe_tv080wum_nl0_mode, | |
5151 | .num_modes = 1, | |
5152 | .size = { | |
5153 | .width = 107, | |
5154 | .height = 172, | |
5155 | }, | |
cb62cdec | 5156 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
c8521969 CZ |
5157 | }, |
5158 | .flags = MIPI_DSI_MODE_VIDEO | | |
5159 | MIPI_DSI_MODE_VIDEO_BURST | | |
5160 | MIPI_DSI_MODE_VIDEO_SYNC_PULSE, | |
5161 | .format = MIPI_DSI_FMT_RGB888, | |
5162 | .lanes = 4, | |
5163 | }; | |
5164 | ||
712ac1ba AC |
5165 | static const struct drm_display_mode lg_ld070wx3_sl01_mode = { |
5166 | .clock = 71000, | |
5167 | .hdisplay = 800, | |
5168 | .hsync_start = 800 + 32, | |
5169 | .hsync_end = 800 + 32 + 1, | |
5170 | .htotal = 800 + 32 + 1 + 57, | |
5171 | .vdisplay = 1280, | |
5172 | .vsync_start = 1280 + 28, | |
5173 | .vsync_end = 1280 + 28 + 1, | |
5174 | .vtotal = 1280 + 28 + 1 + 14, | |
712ac1ba AC |
5175 | }; |
5176 | ||
5177 | static const struct panel_desc_dsi lg_ld070wx3_sl01 = { | |
5178 | .desc = { | |
5179 | .modes = &lg_ld070wx3_sl01_mode, | |
5180 | .num_modes = 1, | |
d7a839cd | 5181 | .bpc = 8, |
712ac1ba AC |
5182 | .size = { |
5183 | .width = 94, | |
5184 | .height = 151, | |
5185 | }, | |
cb62cdec | 5186 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
712ac1ba | 5187 | }, |
5e4cc278 | 5188 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, |
712ac1ba AC |
5189 | .format = MIPI_DSI_FMT_RGB888, |
5190 | .lanes = 4, | |
5191 | }; | |
5192 | ||
499ce85a AC |
5193 | static const struct drm_display_mode lg_lh500wx1_sd03_mode = { |
5194 | .clock = 67000, | |
5195 | .hdisplay = 720, | |
5196 | .hsync_start = 720 + 12, | |
5197 | .hsync_end = 720 + 12 + 4, | |
5198 | .htotal = 720 + 12 + 4 + 112, | |
5199 | .vdisplay = 1280, | |
5200 | .vsync_start = 1280 + 8, | |
5201 | .vsync_end = 1280 + 8 + 4, | |
5202 | .vtotal = 1280 + 8 + 4 + 12, | |
499ce85a AC |
5203 | }; |
5204 | ||
5205 | static const struct panel_desc_dsi lg_lh500wx1_sd03 = { | |
5206 | .desc = { | |
5207 | .modes = &lg_lh500wx1_sd03_mode, | |
5208 | .num_modes = 1, | |
d7a839cd | 5209 | .bpc = 8, |
499ce85a AC |
5210 | .size = { |
5211 | .width = 62, | |
5212 | .height = 110, | |
5213 | }, | |
cb62cdec | 5214 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
499ce85a AC |
5215 | }, |
5216 | .flags = MIPI_DSI_MODE_VIDEO, | |
5217 | .format = MIPI_DSI_FMT_RGB888, | |
5218 | .lanes = 4, | |
5219 | }; | |
5220 | ||
280921de TR |
5221 | static const struct drm_display_mode panasonic_vvx10f004b00_mode = { |
5222 | .clock = 157200, | |
5223 | .hdisplay = 1920, | |
5224 | .hsync_start = 1920 + 154, | |
5225 | .hsync_end = 1920 + 154 + 16, | |
5226 | .htotal = 1920 + 154 + 16 + 32, | |
5227 | .vdisplay = 1200, | |
5228 | .vsync_start = 1200 + 17, | |
5229 | .vsync_end = 1200 + 17 + 2, | |
5230 | .vtotal = 1200 + 17 + 2 + 16, | |
280921de TR |
5231 | }; |
5232 | ||
210fcd9d TR |
5233 | static const struct panel_desc_dsi panasonic_vvx10f004b00 = { |
5234 | .desc = { | |
5235 | .modes = &panasonic_vvx10f004b00_mode, | |
5236 | .num_modes = 1, | |
d7a839cd | 5237 | .bpc = 8, |
210fcd9d TR |
5238 | .size = { |
5239 | .width = 217, | |
5240 | .height = 136, | |
5241 | }, | |
cb62cdec | 5242 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
280921de | 5243 | }, |
5e4cc278 AC |
5244 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | |
5245 | MIPI_DSI_CLOCK_NON_CONTINUOUS, | |
210fcd9d TR |
5246 | .format = MIPI_DSI_FMT_RGB888, |
5247 | .lanes = 4, | |
5248 | }; | |
5249 | ||
debcd8f9 JM |
5250 | static const struct drm_display_mode lg_acx467akm_7_mode = { |
5251 | .clock = 150000, | |
5252 | .hdisplay = 1080, | |
5253 | .hsync_start = 1080 + 2, | |
5254 | .hsync_end = 1080 + 2 + 2, | |
5255 | .htotal = 1080 + 2 + 2 + 2, | |
5256 | .vdisplay = 1920, | |
5257 | .vsync_start = 1920 + 2, | |
5258 | .vsync_end = 1920 + 2 + 2, | |
5259 | .vtotal = 1920 + 2 + 2 + 2, | |
debcd8f9 JM |
5260 | }; |
5261 | ||
5262 | static const struct panel_desc_dsi lg_acx467akm_7 = { | |
5263 | .desc = { | |
5264 | .modes = &lg_acx467akm_7_mode, | |
5265 | .num_modes = 1, | |
5266 | .bpc = 8, | |
5267 | .size = { | |
5268 | .width = 62, | |
5269 | .height = 110, | |
5270 | }, | |
cb62cdec | 5271 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
debcd8f9 JM |
5272 | }, |
5273 | .flags = 0, | |
5274 | .format = MIPI_DSI_FMT_RGB888, | |
5275 | .lanes = 4, | |
5276 | }; | |
5277 | ||
62967232 PU |
5278 | static const struct drm_display_mode osd101t2045_53ts_mode = { |
5279 | .clock = 154500, | |
5280 | .hdisplay = 1920, | |
5281 | .hsync_start = 1920 + 112, | |
5282 | .hsync_end = 1920 + 112 + 16, | |
5283 | .htotal = 1920 + 112 + 16 + 32, | |
5284 | .vdisplay = 1200, | |
5285 | .vsync_start = 1200 + 16, | |
5286 | .vsync_end = 1200 + 16 + 2, | |
5287 | .vtotal = 1200 + 16 + 2 + 16, | |
62967232 PU |
5288 | .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, |
5289 | }; | |
5290 | ||
5291 | static const struct panel_desc_dsi osd101t2045_53ts = { | |
5292 | .desc = { | |
5293 | .modes = &osd101t2045_53ts_mode, | |
5294 | .num_modes = 1, | |
5295 | .bpc = 8, | |
5296 | .size = { | |
5297 | .width = 217, | |
5298 | .height = 136, | |
5299 | }, | |
cb62cdec | 5300 | .connector_type = DRM_MODE_CONNECTOR_DSI, |
62967232 PU |
5301 | }, |
5302 | .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | | |
5303 | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | | |
0f3b68b6 | 5304 | MIPI_DSI_MODE_NO_EOT_PACKET, |
62967232 PU |
5305 | .format = MIPI_DSI_FMT_RGB888, |
5306 | .lanes = 4, | |
5307 | }; | |
5308 | ||
210fcd9d TR |
5309 | static const struct of_device_id dsi_of_match[] = { |
5310 | { | |
d718d79e TR |
5311 | .compatible = "auo,b080uan01", |
5312 | .data = &auo_b080uan01 | |
c8521969 CZ |
5313 | }, { |
5314 | .compatible = "boe,tv080wum-nl0", | |
5315 | .data = &boe_tv080wum_nl0 | |
d718d79e | 5316 | }, { |
712ac1ba AC |
5317 | .compatible = "lg,ld070wx3-sl01", |
5318 | .data = &lg_ld070wx3_sl01 | |
5319 | }, { | |
499ce85a AC |
5320 | .compatible = "lg,lh500wx1-sd03", |
5321 | .data = &lg_lh500wx1_sd03 | |
5322 | }, { | |
210fcd9d TR |
5323 | .compatible = "panasonic,vvx10f004b00", |
5324 | .data = &panasonic_vvx10f004b00 | |
debcd8f9 JM |
5325 | }, { |
5326 | .compatible = "lg,acx467akm-7", | |
5327 | .data = &lg_acx467akm_7 | |
62967232 PU |
5328 | }, { |
5329 | .compatible = "osddisplays,osd101t2045-53ts", | |
5330 | .data = &osd101t2045_53ts | |
210fcd9d TR |
5331 | }, { |
5332 | /* sentinel */ | |
5333 | } | |
5334 | }; | |
5335 | MODULE_DEVICE_TABLE(of, dsi_of_match); | |
5336 | ||
5337 | static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) | |
5338 | { | |
5339 | const struct panel_desc_dsi *desc; | |
210fcd9d TR |
5340 | int err; |
5341 | ||
a7f880bc GU |
5342 | desc = of_device_get_match_data(&dsi->dev); |
5343 | if (!desc) | |
210fcd9d TR |
5344 | return -ENODEV; |
5345 | ||
5f04e7ce | 5346 | err = panel_simple_probe(&dsi->dev, &desc->desc); |
210fcd9d TR |
5347 | if (err < 0) |
5348 | return err; | |
5349 | ||
462658b8 | 5350 | dsi->mode_flags = desc->flags; |
210fcd9d TR |
5351 | dsi->format = desc->format; |
5352 | dsi->lanes = desc->lanes; | |
5353 | ||
7ad9db66 PU |
5354 | err = mipi_dsi_attach(dsi); |
5355 | if (err) { | |
5dd331d4 | 5356 | struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); |
7ad9db66 PU |
5357 | |
5358 | drm_panel_remove(&panel->base); | |
5359 | } | |
5360 | ||
5361 | return err; | |
210fcd9d TR |
5362 | } |
5363 | ||
79abca2b | 5364 | static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) |
210fcd9d TR |
5365 | { |
5366 | int err; | |
5367 | ||
5368 | err = mipi_dsi_detach(dsi); | |
5369 | if (err < 0) | |
5370 | dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); | |
5371 | ||
d72ac4bb | 5372 | panel_simple_remove(&dsi->dev); |
210fcd9d TR |
5373 | } |
5374 | ||
d02fd93e TR |
5375 | static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) |
5376 | { | |
5377 | panel_simple_shutdown(&dsi->dev); | |
5378 | } | |
5379 | ||
210fcd9d TR |
5380 | static struct mipi_dsi_driver panel_simple_dsi_driver = { |
5381 | .driver = { | |
5382 | .name = "panel-simple-dsi", | |
210fcd9d | 5383 | .of_match_table = dsi_of_match, |
3235b0f2 | 5384 | .pm = &panel_simple_pm_ops, |
210fcd9d TR |
5385 | }, |
5386 | .probe = panel_simple_dsi_probe, | |
5387 | .remove = panel_simple_dsi_remove, | |
d02fd93e | 5388 | .shutdown = panel_simple_dsi_shutdown, |
280921de TR |
5389 | }; |
5390 | ||
5391 | static int __init panel_simple_init(void) | |
5392 | { | |
210fcd9d TR |
5393 | int err; |
5394 | ||
5395 | err = platform_driver_register(&panel_simple_platform_driver); | |
5396 | if (err < 0) | |
5397 | return err; | |
5398 | ||
5399 | if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { | |
5400 | err = mipi_dsi_driver_register(&panel_simple_dsi_driver); | |
74c06c28 | 5401 | if (err < 0) |
5f04e7ce | 5402 | goto err_did_platform_register; |
210fcd9d TR |
5403 | } |
5404 | ||
5405 | return 0; | |
74c06c28 | 5406 | |
74c06c28 DA |
5407 | err_did_platform_register: |
5408 | platform_driver_unregister(&panel_simple_platform_driver); | |
5409 | ||
5410 | return err; | |
280921de TR |
5411 | } |
5412 | module_init(panel_simple_init); | |
5413 | ||
5414 | static void __exit panel_simple_exit(void) | |
5415 | { | |
210fcd9d TR |
5416 | if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) |
5417 | mipi_dsi_driver_unregister(&panel_simple_dsi_driver); | |
5418 | ||
280921de TR |
5419 | platform_driver_unregister(&panel_simple_platform_driver); |
5420 | } | |
5421 | module_exit(panel_simple_exit); | |
5422 | ||
5423 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
5424 | MODULE_DESCRIPTION("DRM Driver for Simple Panels"); | |
5425 | MODULE_LICENSE("GPL and additional rights"); |