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Linux 6.10-rc6
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
a204f974 26#include <linux/i2c.h>
72bd9ea3 27#include <linux/media-bus-format.h>
280921de 28#include <linux/module.h>
280921de
TR		 29#include <linux/of_platform.h>
30#include <linux/platform_device.h>
3235b0f2 31#include <linux/pm_runtime.h>
280921de
TR		 32#include <linux/regulator/consumer.h>
33
cb23eae3 34#include <video/display_timing.h>
b8a2948f 35#include <video/of_display_timing.h>
cb23eae3
SR		 36#include <video/videomode.h>
37
280921de 38#include <drm/drm_crtc.h>
cb23eae3 39#include <drm/drm_device.h>
255490f9 40#include <drm/drm_edid.h>
210fcd9d 41#include <drm/drm_mipi_dsi.h>
280921de 42#include <drm/drm_panel.h>
1cd3ea3e 43#include <drm/drm_of.h>
280921de 44
e362cc6a 45/**
a00fa428 46 * struct panel_desc - Describes a simple panel.
e362cc6a 47 */
280921de 48struct panel_desc {
a00fa428
DA		 49 /**
50 * @modes: Pointer to array of fixed modes appropriate for this panel.
51 *
52 * If only one mode then this can just be the address of the mode.
53 * NOTE: cannot be used with "timings" and also if this is specified
54 * then you cannot override the mode in the device tree.
55 */
280921de 56 const struct drm_display_mode *modes;
a00fa428
DA		 57
58 /** @num_modes: Number of elements in modes array. */
280921de 59 unsigned int num_modes;
a00fa428
DA		 60
61 /**
62 * @timings: Pointer to array of display timings
63 *
64 * NOTE: cannot be used with "modes" and also these will be used to
65 * validate a device tree override if one is present.
66 */
a5d3e625 67 const struct display_timing *timings;
a00fa428
DA		 68
69 /** @num_timings: Number of elements in timings array. */
a5d3e625 70 unsigned int num_timings;
280921de 71
a00fa428 72 /** @bpc: Bits per color. */
0208d511
SM		 73 unsigned int bpc;
74
a00fa428 75 /** @size: Structure containing the physical size of this panel. */
280921de 76 struct {
131f909a
DA		 77 /**
78 * @size.width: Width (in mm) of the active display area.
79 */
280921de 80 unsigned int width;
131f909a
DA		 81
82 /**
83 * @size.height: Height (in mm) of the active display area.
84 */
280921de
TR		 85 unsigned int height;
86 } size;
f673c37e 87
a00fa428 88 /** @delay: Structure containing various delay values for this panel. */
f673c37e 89 struct {
131f909a
DA		 90 /**
91 * @delay.prepare: Time for the panel to become ready.
92 *
93 * The time (in milliseconds) that it takes for the panel to
94 * become ready and start receiving video data
95 */
f673c37e 96 unsigned int prepare;
131f909a 97
131f909a
DA		 98 /**
99 * @delay.enable: Time for the panel to display a valid frame.
100 *
101 * The time (in milliseconds) that it takes for the panel to
102 * display the first valid frame after starting to receive
103 * video data.
104 */
f673c37e 105 unsigned int enable;
131f909a
DA		 106
107 /**
108 * @delay.disable: Time for the panel to turn the display off.
109 *
110 * The time (in milliseconds) that it takes for the panel to
111 * turn the display off (no content is visible).
112 */
f673c37e 113 unsigned int disable;
131f909a
DA		 114
115 /**
116 * @delay.unprepare: Time to power down completely.
117 *
118 * The time (in milliseconds) that it takes for the panel
119 * to power itself down completely.
e5e30dfc
DA		 120 *
121 * This time is used to prevent a future "prepare" from
122 * starting until at least this many milliseconds has passed.
123 * If at prepare time less time has passed since unprepare
124 * finished, the driver waits for the remaining time.
131f909a 125 */
f673c37e
AK		 126 unsigned int unprepare;
127 } delay;
795f7ab3 128
a00fa428 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
795f7ab3 130 u32 bus_format;
a00fa428
DA		 131
132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
f0aa0838 133 u32 bus_flags;
a00fa428
DA		 134
135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
9a2654c0 136 int connector_type;
280921de
TR		 137};
138
280921de
TR		 139struct panel_simple {
140 struct drm_panel base;
141 bool enabled;
142
3235b0f2
DA		 143 bool prepared;
144
e5e30dfc
DA		 145 ktime_t unprepared_time;
146
280921de
TR		 147 const struct panel_desc *desc;
148
280921de
TR		 149 struct regulator *supply;
150 struct i2c_adapter *ddc;
151
cfdf0549 152 struct gpio_desc *enable_gpio;
b8a2948f 153
e69da902 154 const struct drm_edid *drm_edid;
63358e24 155
b8a2948f 156 struct drm_display_mode override_mode;
5759c967
DO		 157
158 enum drm_panel_orientation orientation;
280921de
TR		 159};
160
161static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
162{
163 return container_of(panel, struct panel_simple, base);
164}
165
0ce8ddd8
SR		 166static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 struct drm_connector *connector)
280921de 168{
280921de
TR		 169 struct drm_display_mode *mode;
170 unsigned int i, num = 0;
171
a5d3e625
PZ		 172 for (i = 0; i < panel->desc->num_timings; i++) {
173 const struct display_timing *dt = &panel->desc->timings[i];
174 struct videomode vm;
175
176 videomode_from_timing(dt, &vm);
aa6c4364 177 mode = drm_mode_create(connector->dev);
a5d3e625 178 if (!mode) {
aa6c4364 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 180 dt->hactive.typ, dt->vactive.typ);
181 continue;
182 }
183
184 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 185
186 mode->type |= DRM_MODE_TYPE_DRIVER;
187
230c5b44 188 if (panel->desc->num_timings == 1)
cda55372
BB		 189 mode->type |= DRM_MODE_TYPE_PREFERRED;
190
a5d3e625
PZ		 191 drm_mode_probed_add(connector, mode);
192 num++;
193 }
194
b8a2948f
SP		 195 return num;
196}
197
0ce8ddd8
SR		 198static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 struct drm_connector *connector)
b8a2948f 200{
b8a2948f
SP		 201 struct drm_display_mode *mode;
202 unsigned int i, num = 0;
203
280921de
TR		 204 for (i = 0; i < panel->desc->num_modes; i++) {
205 const struct drm_display_mode *m = &panel->desc->modes[i];
206
aa6c4364 207 mode = drm_mode_duplicate(connector->dev, m);
280921de 208 if (!mode) {
aa6c4364 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
0425662f
VS		 210 m->hdisplay, m->vdisplay,
211 drm_mode_vrefresh(m));
280921de
TR		 212 continue;
213 }
214
cda55372
BB		 215 mode->type |= DRM_MODE_TYPE_DRIVER;
216
217 if (panel->desc->num_modes == 1)
218 mode->type |= DRM_MODE_TYPE_PREFERRED;
219
280921de
TR		 220 drm_mode_set_name(mode);
221
222 drm_mode_probed_add(connector, mode);
223 num++;
224 }
225
b8a2948f
SP		 226 return num;
227}
228
0ce8ddd8
SR		 229static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 struct drm_connector *connector)
b8a2948f 231{
b8a2948f
SP		 232 struct drm_display_mode *mode;
233 bool has_override = panel->override_mode.type;
234 unsigned int num = 0;
235
236 if (!panel->desc)
237 return 0;
238
239 if (has_override) {
aa6c4364
SR		 240 mode = drm_mode_duplicate(connector->dev,
241 &panel->override_mode);
b8a2948f
SP		 242 if (mode) {
243 drm_mode_probed_add(connector, mode);
244 num = 1;
245 } else {
aa6c4364 246 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 247 }
248 }
249
250 /* Only add timings if override was not there or failed to validate */
251 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 252 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 253
254 /*
255 * Only add fixed modes if timings/override added no mode.
256 *
257 * We should only ever have either the display timings specified
258 * or a fixed mode. Anything else is rather bogus.
259 */
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
261 if (num == 0)
0ce8ddd8 262 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 263
0208d511 264 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 265 connector->display_info.width_mm = panel->desc->size.width;
266 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 267 if (panel->desc->bus_format)
268 drm_display_info_set_bus_formats(&connector->display_info,
269 &panel->desc->bus_format, 1);
f0aa0838 270 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 271
272 return num;
273}
274
e5e30dfc
DA		 275static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
276{
277 ktime_t now_ktime, min_ktime;
278
279 if (!min_ms)
280 return;
281
282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
7e682946 283 now_ktime = ktime_get_boottime();
e5e30dfc
DA		 284
285 if (ktime_before(now_ktime, min_ktime))
286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
287}
288
280921de
TR		 289static int panel_simple_disable(struct drm_panel *panel)
290{
291 struct panel_simple *p = to_panel_simple(panel);
292
293 if (!p->enabled)
294 return 0;
295
f673c37e
AK		 296 if (p->desc->delay.disable)
297 msleep(p->desc->delay.disable);
298
280921de
TR		 299 p->enabled = false;
300
301 return 0;
302}
303
3235b0f2
DA		 304static int panel_simple_suspend(struct device *dev)
305{
306 struct panel_simple *p = dev_get_drvdata(dev);
307
308 gpiod_set_value_cansleep(p->enable_gpio, 0);
309 regulator_disable(p->supply);
7e682946 310 p->unprepared_time = ktime_get_boottime();
3235b0f2 311
e69da902
JN		 312 drm_edid_free(p->drm_edid);
313 p->drm_edid = NULL;
63358e24 314
3235b0f2
DA		 315 return 0;
316}
317
c0e1d170
AK		 318static int panel_simple_unprepare(struct drm_panel *panel)
319{
613a633e 320 struct panel_simple *p = to_panel_simple(panel);
3235b0f2 321 int ret;
613a633e 322
3235b0f2
DA		 323 /* Unpreparing when already unprepared is a no-op */
324 if (!p->prepared)
613a633e
AK		 325 return 0;
326
3235b0f2
DA		 327 pm_runtime_mark_last_busy(panel->dev);
328 ret = pm_runtime_put_autosuspend(panel->dev);
329 if (ret < 0)
330 return ret;
331 p->prepared = false;
c0e1d170 332
c0e1d170
AK		 333 return 0;
334}
335
b6d5ffce 336static int panel_simple_resume(struct device *dev)
280921de 337{
b6d5ffce 338 struct panel_simple *p = dev_get_drvdata(dev);
280921de
TR		 339 int err;
340
e5e30dfc
DA		 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
342
280921de
TR		 343 err = regulator_enable(p->supply);
344 if (err < 0) {
3235b0f2 345 dev_err(dev, "failed to enable supply: %d\n", err);
280921de
TR		 346 return err;
347 }
348
756b918d 349 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 350
b6d5ffce
DA		 351 if (p->desc->delay.prepare)
352 msleep(p->desc->delay.prepare);
48834e60 353
613a633e 354 return 0;
87b49717
DA		 355}
356
3235b0f2
DA		 357static int panel_simple_prepare(struct drm_panel *panel)
358{
359 struct panel_simple *p = to_panel_simple(panel);
360 int ret;
361
362 /* Preparing when already prepared is a no-op */
363 if (p->prepared)
364 return 0;
365
366 ret = pm_runtime_get_sync(panel->dev);
367 if (ret < 0) {
368 pm_runtime_put_autosuspend(panel->dev);
369 return ret;
370 }
371
372 p->prepared = true;
373
374 return 0;
375}
376
613a633e
AK		 377static int panel_simple_enable(struct drm_panel *panel)
378{
379 struct panel_simple *p = to_panel_simple(panel);
380
381 if (p->enabled)
382 return 0;
383
f673c37e
AK		 384 if (p->desc->delay.enable)
385 msleep(p->desc->delay.enable);
386
280921de
TR		 387 p->enabled = true;
388
389 return 0;
390}
391
0ce8ddd8
SR		 392static int panel_simple_get_modes(struct drm_panel *panel,
393 struct drm_connector *connector)
280921de
TR		 394{
395 struct panel_simple *p = to_panel_simple(panel);
396 int num = 0;
397
398 /* probe EDID if a DDC bus is available */
399 if (p->ddc) {
31e25395
DA		 400 pm_runtime_get_sync(panel->dev);
401
e69da902
JN		 402 if (!p->drm_edid)
403 p->drm_edid = drm_edid_read_ddc(connector, p->ddc);
63358e24 404
e69da902
JN		 405 drm_edid_connector_update(connector, p->drm_edid);
406
407 num += drm_edid_connector_add_modes(connector);
31e25395
DA		 408
409 pm_runtime_mark_last_busy(panel->dev);
410 pm_runtime_put_autosuspend(panel->dev);
280921de
TR		 411 }
412
413 /* add hard-coded panel modes */
0ce8ddd8 414 num += panel_simple_get_non_edid_modes(p, connector);
280921de 415
a960e35a
HYW		 416 /*
417 * TODO: Remove once all drm drivers call
418 * drm_connector_set_orientation_from_panel()
419 */
5759c967
DO		 420 drm_connector_set_panel_orientation(connector, p->orientation);
421
280921de
TR		 422 return num;
423}
424
a5d3e625
PZ		 425static int panel_simple_get_timings(struct drm_panel *panel,
426 unsigned int num_timings,
427 struct display_timing *timings)
428{
429 struct panel_simple *p = to_panel_simple(panel);
430 unsigned int i;
431
432 if (p->desc->num_timings < num_timings)
433 num_timings = p->desc->num_timings;
434
435 if (timings)
436 for (i = 0; i < num_timings; i++)
437 timings[i] = p->desc->timings[i];
438
439 return p->desc->num_timings;
440}
441
a960e35a
HYW		 442static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
443{
444 struct panel_simple *p = to_panel_simple(panel);
445
446 return p->orientation;
447}
448
280921de
TR		 449static const struct drm_panel_funcs panel_simple_funcs = {
450 .disable = panel_simple_disable,
c0e1d170
AK		 451 .unprepare = panel_simple_unprepare,
452 .prepare = panel_simple_prepare,
280921de
TR		 453 .enable = panel_simple_enable,
454 .get_modes = panel_simple_get_modes,
a960e35a 455 .get_orientation = panel_simple_get_orientation,
a5d3e625 456 .get_timings = panel_simple_get_timings,
280921de
TR		 457};
458
4a1d0dbc
SR		 459static struct panel_desc panel_dpi;
460
461static int panel_dpi_probe(struct device *dev,
462 struct panel_simple *panel)
463{
464 struct display_timing *timing;
465 const struct device_node *np;
466 struct panel_desc *desc;
467 unsigned int bus_flags;
468 struct videomode vm;
4a1d0dbc
SR		 469 int ret;
470
471 np = dev->of_node;
472 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
473 if (!desc)
474 return -ENOMEM;
475
476 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
477 if (!timing)
478 return -ENOMEM;
479
480 ret = of_get_display_timing(np, "panel-timing", timing);
481 if (ret < 0) {
482 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
483 np);
484 return ret;
485 }
486
487 desc->timings = timing;
488 desc->num_timings = 1;
489
490 of_property_read_u32(np, "width-mm", &desc->size.width);
491 of_property_read_u32(np, "height-mm", &desc->size.height);
492
4a1d0dbc
SR		 493 /* Extract bus_flags from display_timing */
494 bus_flags = 0;
495 vm.flags = timing->flags;
496 drm_bus_flags_from_videomode(&vm, &bus_flags);
497 desc->bus_flags = bus_flags;
498
499 /* We do not know the connector for the DT node, so guess it */
500 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
501
502 panel->desc = desc;
503
504 return 0;
505}
506
b8a2948f
SP		 507#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
508 (to_check->field.typ >= bounds->field.min && \
509 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 510static void panel_simple_parse_panel_timing_node(struct device *dev,
511 struct panel_simple *panel,
512 const struct display_timing *ot)
b8a2948f
SP		 513{
514 const struct panel_desc *desc = panel->desc;
515 struct videomode vm;
516 unsigned int i;
517
518 if (WARN_ON(desc->num_modes)) {
519 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
520 return;
521 }
522 if (WARN_ON(!desc->num_timings)) {
523 dev_err(dev, "Reject override mode: no timings specified\n");
524 return;
525 }
526
527 for (i = 0; i < panel->desc->num_timings; i++) {
528 const struct display_timing *dt = &panel->desc->timings[i];
529
530 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
538 continue;
539
540 if (ot->flags != dt->flags)
541 continue;
542
543 videomode_from_timing(ot, &vm);
544 drm_display_mode_from_videomode(&vm, &panel->override_mode);
545 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
546 DRM_MODE_TYPE_PREFERRED;
547 break;
548 }
549
550 if (WARN_ON(!panel->override_mode.type))
551 dev_err(dev, "Reject override mode: No display_timing found\n");
552}
553
1cd3ea3e
JZ		 554static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
555 struct panel_simple *panel)
556{
557 int ret, bpc;
558
559 ret = drm_of_lvds_get_data_mapping(dev->of_node);
560 if (ret < 0) {
561 if (ret == -EINVAL)
562 dev_warn(dev, "Ignore invalid data-mapping property\n");
563
564 /*
565 * Ignore non-existing or malformatted property, fallback to
566 * default data-mapping, and return 0.
567 */
568 return 0;
569 }
570
571 switch (ret) {
572 default:
573 WARN_ON(1);
574 fallthrough;
575 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
576 fallthrough;
577 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
578 bpc = 8;
579 break;
580 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
581 bpc = 6;
582 }
583
584 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
585 struct panel_desc *override_desc;
586
587 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
588 if (!override_desc)
589 return -ENOMEM;
590
591 override_desc->bus_format = ret;
592 override_desc->bpc = bpc;
593 panel->desc = override_desc;
594 }
595
596 return 0;
597}
598
5f04e7ce 599static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
280921de 600{
280921de 601 struct panel_simple *panel;
b8a2948f 602 struct display_timing dt;
0fe1564b 603 struct device_node *ddc;
9f069c6f 604 int connector_type;
ddb8e853 605 u32 bus_flags;
280921de
TR		 606 int err;
607
608 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
609 if (!panel)
610 return -ENOMEM;
611
612 panel->enabled = false;
613 panel->desc = desc;
614
615 panel->supply = devm_regulator_get(dev, "power");
616 if (IS_ERR(panel->supply))
617 return PTR_ERR(panel->supply);
618
a61400d8
AC		 619 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
620 GPIOD_OUT_LOW);
c9b48b91
YC		 621 if (IS_ERR(panel->enable_gpio))
622 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
623 "failed to request GPIO\n");
280921de 624
5759c967
DO		 625 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
626 if (err) {
627 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
628 return err;
629 }
630
280921de
TR		 631 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
632 if (ddc) {
633 panel->ddc = of_find_i2c_adapter_by_node(ddc);
634 of_node_put(ddc);
635
0fe1564b
SR		 636 if (!panel->ddc)
637 return -EPROBE_DEFER;
280921de
TR		 638 }
639
4a1d0dbc
SR		 640 if (desc == &panel_dpi) {
641 /* Handle the generic panel-dpi binding */
642 err = panel_dpi_probe(dev, panel);
643 if (err)
644 goto free_ddc;
6df4432a 645 desc = panel->desc;
4a1d0dbc
SR		 646 } else {
647 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
648 panel_simple_parse_panel_timing_node(dev, panel, &dt);
649 }
b8a2948f 650
1cd3ea3e
JZ		 651 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
652 /* Optional data-mapping property for overriding bus format */
653 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
654 if (err)
655 goto free_ddc;
656 }
657
9f069c6f 658 connector_type = desc->connector_type;
ddb8e853 659 /* Catch common mistakes for panels. */
9f069c6f 660 switch (connector_type) {
ddb8e853
SR		 661 case 0:
662 dev_warn(dev, "Specify missing connector_type\n");
9f069c6f 663 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853
SR		 664 break;
665 case DRM_MODE_CONNECTOR_LVDS:
c4715837
LP		 666 WARN_ON(desc->bus_flags &
667 ~(DRM_BUS_FLAG_DE_LOW |
668 DRM_BUS_FLAG_DE_HIGH |
669 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
670 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
1185c406
LP		 671 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
673 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
674 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
675 desc->bpc != 6);
676 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
677 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
678 desc->bpc != 8);
ddb8e853
SR		 679 break;
680 case DRM_MODE_CONNECTOR_eDP:
5f04e7ce
DA		 681 dev_warn(dev, "eDP panels moved to panel-edp\n");
682 err = -EINVAL;
683 goto free_ddc;
ddb8e853
SR		 684 case DRM_MODE_CONNECTOR_DSI:
685 if (desc->bpc != 6 && desc->bpc != 8)
686 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
687 break;
688 case DRM_MODE_CONNECTOR_DPI:
689 bus_flags = DRM_BUS_FLAG_DE_LOW |
690 DRM_BUS_FLAG_DE_HIGH |
691 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
692 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
693 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
694 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
695 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
696 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
697 if (desc->bus_flags & ~bus_flags)
698 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
699 if (!(desc->bus_flags & bus_flags))
700 dev_warn(dev, "Specify missing bus_flags\n");
701 if (desc->bus_format == 0)
702 dev_warn(dev, "Specify missing bus_format\n");
703 if (desc->bpc != 6 && desc->bpc != 8)
704 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
705 break;
706 default:
707 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
9f069c6f 708 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853 709 break;
1185c406 710 }
c4715837 711
3235b0f2
DA		 712 dev_set_drvdata(dev, panel);
713
714 /*
715 * We use runtime PM for prepare / unprepare since those power the panel
716 * on and off and those can be very slow operations. This is important
717 * to optimize powering the panel on briefly to read the EDID before
718 * fully enabling the panel.
719 */
720 pm_runtime_enable(dev);
721 pm_runtime_set_autosuspend_delay(dev, 1000);
722 pm_runtime_use_autosuspend(dev);
723
9f069c6f 724 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
280921de 725
0fe1564b 726 err = drm_panel_of_backlight(&panel->base);
d9e74da2
AS		 727 if (err) {
728 dev_err_probe(dev, err, "Could not find backlight\n");
70e12560 729 goto disable_pm_runtime;
d9e74da2 730 }
0fe1564b 731
c3ee8c65 732 drm_panel_add(&panel->base);
280921de 733
280921de
TR		 734 return 0;
735
70e12560 736disable_pm_runtime:
a596fcd9 737 pm_runtime_dont_use_autosuspend(dev);
70e12560 738 pm_runtime_disable(dev);
280921de 739free_ddc:
5f04e7ce 740 if (panel->ddc)
280921de 741 put_device(&panel->ddc->dev);
280921de
TR		 742
743 return err;
744}
745
d72ac4bb 746static void panel_simple_remove(struct device *dev)
280921de
TR		 747{
748 struct panel_simple *panel = dev_get_drvdata(dev);
749
280921de 750 drm_panel_remove(&panel->base);
0fe1564b
SR		 751 drm_panel_disable(&panel->base);
752 drm_panel_unprepare(&panel->base);
280921de 753
a596fcd9 754 pm_runtime_dont_use_autosuspend(dev);
70e12560 755 pm_runtime_disable(dev);
5f04e7ce 756 if (panel->ddc)
280921de 757 put_device(&panel->ddc->dev);
280921de
TR		 758}
759
d02fd93e
TR		 760static void panel_simple_shutdown(struct device *dev)
761{
762 struct panel_simple *panel = dev_get_drvdata(dev);
763
0fe1564b
SR		 764 drm_panel_disable(&panel->base);
765 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 766}
767
bca684e6
JT		 768static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
769 .clock = 71100,
770 .hdisplay = 1280,
771 .hsync_start = 1280 + 40,
772 .hsync_end = 1280 + 40 + 80,
773 .htotal = 1280 + 40 + 80 + 40,
774 .vdisplay = 800,
775 .vsync_start = 800 + 3,
776 .vsync_end = 800 + 3 + 10,
777 .vtotal = 800 + 3 + 10 + 10,
778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
779};
780
781static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
782 .modes = &ampire_am_1280800n3tzqw_t00h_mode,
783 .num_modes = 1,
7eafbecd 784 .bpc = 8,
bca684e6
JT		 785 .size = {
786 .width = 217,
787 .height = 136,
788 },
789 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
790 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
791 .connector_type = DRM_MODE_CONNECTOR_LVDS,
792};
793
966fea78
YF		 794static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
795 .clock = 9000,
796 .hdisplay = 480,
797 .hsync_start = 480 + 2,
798 .hsync_end = 480 + 2 + 41,
799 .htotal = 480 + 2 + 41 + 2,
800 .vdisplay = 272,
801 .vsync_start = 272 + 2,
802 .vsync_end = 272 + 2 + 10,
803 .vtotal = 272 + 2 + 10 + 2,
966fea78
YF		 804 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
805};
806
807static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
808 .modes = &ampire_am_480272h3tmqw_t01h_mode,
809 .num_modes = 1,
810 .bpc = 8,
811 .size = {
f24b4955
DB		 812 .width = 99,
813 .height = 58,
966fea78
YF		 814 },
815 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
816};
817
1c550fa1
PZ		 818static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
819 .clock = 33333,
820 .hdisplay = 800,
821 .hsync_start = 800 + 0,
822 .hsync_end = 800 + 0 + 255,
823 .htotal = 800 + 0 + 255 + 0,
824 .vdisplay = 480,
825 .vsync_start = 480 + 2,
826 .vsync_end = 480 + 2 + 45,
827 .vtotal = 480 + 2 + 45 + 0,
1c550fa1
PZ		 828 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
829};
830
410bb213
GU		 831static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
832 .pixelclock = { 29930000, 33260000, 36590000 },
833 .hactive = { 800, 800, 800 },
834 .hfront_porch = { 1, 40, 168 },
835 .hback_porch = { 88, 88, 88 },
836 .hsync_len = { 1, 128, 128 },
837 .vactive = { 480, 480, 480 },
838 .vfront_porch = { 1, 35, 37 },
839 .vback_porch = { 8, 8, 8 },
840 .vsync_len = { 1, 2, 2 },
841 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
842 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
843 DISPLAY_FLAGS_SYNC_POSEDGE,
844};
845
846static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
847 .timings = &ampire_am_800480l1tmqw_t00h_timing,
848 .num_timings = 1,
849 .bpc = 8,
850 .size = {
851 .width = 111,
852 .height = 67,
853 },
854 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
855 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
856 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
857 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
858 .connector_type = DRM_MODE_CONNECTOR_DPI,
859};
860
1c550fa1
PZ		 861static const struct panel_desc ampire_am800480r3tmqwa1h = {
862 .modes = &ampire_am800480r3tmqwa1h_mode,
863 .num_modes = 1,
864 .bpc = 6,
865 .size = {
866 .width = 152,
867 .height = 91,
868 },
869 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
870};
871
103f06fd
BK		 872static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
873 .pixelclock = { 34500000, 39600000, 50400000 },
874 .hactive = { 800, 800, 800 },
875 .hfront_porch = { 12, 112, 312 },
876 .hback_porch = { 87, 87, 48 },
877 .hsync_len = { 1, 1, 40 },
878 .vactive = { 600, 600, 600 },
879 .vfront_porch = { 1, 21, 61 },
880 .vback_porch = { 38, 38, 19 },
881 .vsync_len = { 1, 1, 20 },
882 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
883 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
884 DISPLAY_FLAGS_SYNC_POSEDGE,
885};
886
887static const struct panel_desc ampire_am800600p5tmqwtb8h = {
888 .timings = &ampire_am800600p5tmqw_tb8h_timing,
889 .num_timings = 1,
890 .bpc = 6,
891 .size = {
892 .width = 162,
893 .height = 122,
894 },
895 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
896 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
897 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
898 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
899 .connector_type = DRM_MODE_CONNECTOR_DPI,
900};
901
c479450f
SS		 902static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
903 .pixelclock = { 26400000, 33300000, 46800000 },
904 .hactive = { 800, 800, 800 },
905 .hfront_porch = { 16, 210, 354 },
906 .hback_porch = { 45, 36, 6 },
907 .hsync_len = { 1, 10, 40 },
908 .vactive = { 480, 480, 480 },
909 .vfront_porch = { 7, 22, 147 },
910 .vback_porch = { 22, 13, 3 },
911 .vsync_len = { 1, 10, 20 },
912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
914};
915
916static const struct panel_desc armadeus_st0700_adapt = {
917 .timings = &santek_st0700i5y_rbslw_f_timing,
918 .num_timings = 1,
919 .bpc = 6,
920 .size = {
921 .width = 154,
922 .height = 86,
923 },
924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
c479450f
SS		 926};
927
280921de
TR		 928static const struct drm_display_mode auo_b101aw03_mode = {
929 .clock = 51450,
930 .hdisplay = 1024,
931 .hsync_start = 1024 + 156,
932 .hsync_end = 1024 + 156 + 8,
933 .htotal = 1024 + 156 + 8 + 156,
934 .vdisplay = 600,
935 .vsync_start = 600 + 16,
936 .vsync_end = 600 + 16 + 6,
937 .vtotal = 600 + 16 + 6 + 16,
280921de
TR		 938};
939
940static const struct panel_desc auo_b101aw03 = {
941 .modes = &auo_b101aw03_mode,
942 .num_modes = 1,
0208d511 943 .bpc = 6,
280921de
TR		 944 .size = {
945 .width = 223,
946 .height = 125,
947 },
85560829 948 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 949 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 950 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 951};
952
dac746e0
RC		 953static const struct drm_display_mode auo_b101xtn01_mode = {
954 .clock = 72000,
955 .hdisplay = 1366,
956 .hsync_start = 1366 + 20,
957 .hsync_end = 1366 + 20 + 70,
958 .htotal = 1366 + 20 + 70,
959 .vdisplay = 768,
960 .vsync_start = 768 + 14,
961 .vsync_end = 768 + 14 + 42,
962 .vtotal = 768 + 14 + 42,
dac746e0
RC		 963 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
964};
965
966static const struct panel_desc auo_b101xtn01 = {
967 .modes = &auo_b101xtn01_mode,
968 .num_modes = 1,
969 .bpc = 6,
970 .size = {
971 .width = 223,
972 .height = 125,
973 },
974};
975
ad3e33fe
DA		 976static const struct drm_display_mode auo_b116xw03_mode = {
977 .clock = 70589,
978 .hdisplay = 1366,
979 .hsync_start = 1366 + 40,
980 .hsync_end = 1366 + 40 + 40,
981 .htotal = 1366 + 40 + 40 + 32,
982 .vdisplay = 768,
983 .vsync_start = 768 + 10,
984 .vsync_end = 768 + 10 + 12,
985 .vtotal = 768 + 10 + 12 + 6,
986 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
987};
988
989static const struct panel_desc auo_b116xw03 = {
990 .modes = &auo_b116xw03_mode,
991 .num_modes = 1,
992 .bpc = 6,
993 .size = {
994 .width = 256,
995 .height = 144,
996 },
997 .delay = {
998 .prepare = 1,
999 .enable = 200,
1000 .disable = 200,
1001 .unprepare = 500,
1002 },
1003 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1004 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1005 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1006};
1007
bccfaffb
LM		 1008static const struct display_timing auo_g070vvn01_timings = {
1009 .pixelclock = { 33300000, 34209000, 45000000 },
1010 .hactive = { 800, 800, 800 },
1011 .hfront_porch = { 20, 40, 200 },
1012 .hback_porch = { 87, 40, 1 },
1013 .hsync_len = { 1, 48, 87 },
1014 .vactive = { 480, 480, 480 },
1015 .vfront_porch = { 5, 13, 200 },
1016 .vback_porch = { 31, 31, 29 },
1017 .vsync_len = { 1, 1, 3 },
1018};
1019
1020static const struct panel_desc auo_g070vvn01 = {
1021 .timings = &auo_g070vvn01_timings,
1022 .num_timings = 1,
1023 .bpc = 8,
1024 .size = {
1025 .width = 152,
1026 .height = 91,
1027 },
1028 .delay = {
1029 .prepare = 200,
1030 .enable = 50,
1031 .disable = 50,
1032 .unprepare = 1000,
1033 },
1034};
1035
4fb86404
AG		 1036static const struct drm_display_mode auo_g101evn010_mode = {
1037 .clock = 68930,
1038 .hdisplay = 1280,
1039 .hsync_start = 1280 + 82,
1040 .hsync_end = 1280 + 82 + 2,
1041 .htotal = 1280 + 82 + 2 + 84,
1042 .vdisplay = 800,
1043 .vsync_start = 800 + 8,
1044 .vsync_end = 800 + 8 + 2,
1045 .vtotal = 800 + 8 + 2 + 6,
4fb86404
AG		 1046};
1047
1048static const struct panel_desc auo_g101evn010 = {
1049 .modes = &auo_g101evn010_mode,
1050 .num_modes = 1,
1051 .bpc = 6,
1052 .size = {
1053 .width = 216,
1054 .height = 135,
1055 },
27a46fb7
TV		 1056 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1057 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4fb86404
AG		 1058};
1059
4451c287
CF		 1060static const struct drm_display_mode auo_g104sn02_mode = {
1061 .clock = 40000,
1062 .hdisplay = 800,
1063 .hsync_start = 800 + 40,
1064 .hsync_end = 800 + 40 + 216,
1065 .htotal = 800 + 40 + 216 + 128,
1066 .vdisplay = 600,
1067 .vsync_start = 600 + 10,
1068 .vsync_end = 600 + 10 + 35,
1069 .vtotal = 600 + 10 + 35 + 2,
4451c287
CF		 1070};
1071
1072static const struct panel_desc auo_g104sn02 = {
1073 .modes = &auo_g104sn02_mode,
1074 .num_modes = 1,
1075 .bpc = 8,
1076 .size = {
1077 .width = 211,
1078 .height = 158,
1079 },
a3050f23
SR		 1080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1081 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4451c287
CF		 1082};
1083
e8470c0a
LC		 1084static const struct display_timing auo_g121ean01_timing = {
1085 .pixelclock = { 60000000, 74400000, 90000000 },
1086 .hactive = { 1280, 1280, 1280 },
1087 .hfront_porch = { 20, 50, 100 },
1088 .hback_porch = { 20, 50, 100 },
1089 .hsync_len = { 30, 100, 200 },
1090 .vactive = { 800, 800, 800 },
1091 .vfront_porch = { 2, 10, 25 },
1092 .vback_porch = { 2, 10, 25 },
1093 .vsync_len = { 4, 18, 50 },
03e909ac
SR		 1094};
1095
1096static const struct panel_desc auo_g121ean01 = {
e8470c0a
LC		 1097 .timings = &auo_g121ean01_timing,
1098 .num_timings = 1,
03e909ac
SR		 1099 .bpc = 8,
1100 .size = {
1101 .width = 261,
1102 .height = 163,
1103 },
1104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1105 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1106};
1107
697035c6
LS		 1108static const struct display_timing auo_g133han01_timings = {
1109 .pixelclock = { 134000000, 141200000, 149000000 },
1110 .hactive = { 1920, 1920, 1920 },
1111 .hfront_porch = { 39, 58, 77 },
1112 .hback_porch = { 59, 88, 117 },
1113 .hsync_len = { 28, 42, 56 },
1114 .vactive = { 1080, 1080, 1080 },
1115 .vfront_porch = { 3, 8, 11 },
1116 .vback_porch = { 5, 14, 19 },
1117 .vsync_len = { 4, 14, 19 },
1118};
1119
1120static const struct panel_desc auo_g133han01 = {
1121 .timings = &auo_g133han01_timings,
1122 .num_timings = 1,
1123 .bpc = 8,
1124 .size = {
1125 .width = 293,
1126 .height = 165,
1127 },
1128 .delay = {
1129 .prepare = 200,
1130 .enable = 50,
1131 .disable = 50,
1132 .unprepare = 1000,
1133 },
1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 1136};
1137
9e52d5c8
EA		 1138static const struct display_timing auo_g156han04_timings = {
1139 .pixelclock = { 137000000, 141000000, 146000000 },
1140 .hactive = { 1920, 1920, 1920 },
1141 .hfront_porch = { 60, 60, 60 },
1142 .hback_porch = { 90, 92, 111 },
1143 .hsync_len = { 32, 32, 32 },
1144 .vactive = { 1080, 1080, 1080 },
1145 .vfront_porch = { 12, 12, 12 },
1146 .vback_porch = { 24, 36, 56 },
1147 .vsync_len = { 8, 8, 8 },
1148};
1149
1150static const struct panel_desc auo_g156han04 = {
1151 .timings = &auo_g156han04_timings,
1152 .num_timings = 1,
1153 .bpc = 8,
1154 .size = {
1155 .width = 344,
1156 .height = 194,
1157 },
1158 .delay = {
1159 .prepare = 50, /* T2 */
1160 .enable = 200, /* T3 */
1161 .disable = 110, /* T10 */
1162 .unprepare = 1000, /* T13 */
1163 },
1164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1165 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1166 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1167};
1168
d9ccd1f2
SR		 1169static const struct drm_display_mode auo_g156xtn01_mode = {
1170 .clock = 76000,
1171 .hdisplay = 1366,
1172 .hsync_start = 1366 + 33,
1173 .hsync_end = 1366 + 33 + 67,
1174 .htotal = 1560,
1175 .vdisplay = 768,
1176 .vsync_start = 768 + 4,
1177 .vsync_end = 768 + 4 + 4,
1178 .vtotal = 806,
d9ccd1f2
SR		 1179};
1180
1181static const struct panel_desc auo_g156xtn01 = {
1182 .modes = &auo_g156xtn01_mode,
1183 .num_modes = 1,
1184 .bpc = 8,
1185 .size = {
1186 .width = 344,
1187 .height = 194,
1188 },
1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1190 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1191};
1192
8c31f603
LS		 1193static const struct display_timing auo_g185han01_timings = {
1194 .pixelclock = { 120000000, 144000000, 175000000 },
1195 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 1196 .hfront_porch = { 36, 120, 148 },
1197 .hback_porch = { 24, 88, 108 },
1198 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 1199 .vactive = { 1080, 1080, 1080 },
1200 .vfront_porch = { 6, 10, 40 },
1201 .vback_porch = { 2, 5, 20 },
1202 .vsync_len = { 2, 5, 20 },
1203};
1204
1205static const struct panel_desc auo_g185han01 = {
1206 .timings = &auo_g185han01_timings,
1207 .num_timings = 1,
1208 .bpc = 8,
1209 .size = {
1210 .width = 409,
1211 .height = 230,
1212 },
1213 .delay = {
1214 .prepare = 50,
1215 .enable = 200,
1216 .disable = 110,
1217 .unprepare = 1000,
1218 },
1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 1221};
1222
2f7b832f
SR		 1223static const struct display_timing auo_g190ean01_timings = {
1224 .pixelclock = { 90000000, 108000000, 135000000 },
1225 .hactive = { 1280, 1280, 1280 },
1226 .hfront_porch = { 126, 184, 1266 },
1227 .hback_porch = { 84, 122, 844 },
1228 .hsync_len = { 70, 102, 704 },
1229 .vactive = { 1024, 1024, 1024 },
1230 .vfront_porch = { 4, 26, 76 },
1231 .vback_porch = { 2, 8, 25 },
1232 .vsync_len = { 2, 8, 25 },
1233};
1234
1235static const struct panel_desc auo_g190ean01 = {
1236 .timings = &auo_g190ean01_timings,
1237 .num_timings = 1,
1238 .bpc = 8,
1239 .size = {
1240 .width = 376,
1241 .height = 301,
1242 },
1243 .delay = {
1244 .prepare = 50,
1245 .enable = 200,
1246 .disable = 110,
1247 .unprepare = 1000,
1248 },
1249 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1250 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1251};
1252
70c0d5b7
LS		 1253static const struct display_timing auo_p320hvn03_timings = {
1254 .pixelclock = { 106000000, 148500000, 164000000 },
1255 .hactive = { 1920, 1920, 1920 },
1256 .hfront_porch = { 25, 50, 130 },
1257 .hback_porch = { 25, 50, 130 },
1258 .hsync_len = { 20, 40, 105 },
1259 .vactive = { 1080, 1080, 1080 },
1260 .vfront_porch = { 8, 17, 150 },
1261 .vback_porch = { 8, 17, 150 },
1262 .vsync_len = { 4, 11, 100 },
1263};
1264
1265static const struct panel_desc auo_p320hvn03 = {
1266 .timings = &auo_p320hvn03_timings,
1267 .num_timings = 1,
1268 .bpc = 8,
1269 .size = {
1270 .width = 698,
1271 .height = 393,
1272 },
1273 .delay = {
1274 .prepare = 1,
1275 .enable = 450,
1276 .unprepare = 500,
1277 },
2554f154 1278 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1279 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 1280};
1281
7ee933a1
HS		 1282static const struct drm_display_mode auo_t215hvn01_mode = {
1283 .clock = 148800,
1284 .hdisplay = 1920,
1285 .hsync_start = 1920 + 88,
1286 .hsync_end = 1920 + 88 + 44,
1287 .htotal = 1920 + 88 + 44 + 148,
1288 .vdisplay = 1080,
1289 .vsync_start = 1080 + 4,
1290 .vsync_end = 1080 + 4 + 5,
1291 .vtotal = 1080 + 4 + 5 + 36,
7ee933a1
HS		 1292};
1293
1294static const struct panel_desc auo_t215hvn01 = {
1295 .modes = &auo_t215hvn01_mode,
1296 .num_modes = 1,
1297 .bpc = 8,
1298 .size = {
1299 .width = 430,
1300 .height = 270,
1301 },
1302 .delay = {
1303 .disable = 5,
1304 .unprepare = 1000,
7a675a8f
MV		 1305 },
1306 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1307 .connector_type = DRM_MODE_CONNECTOR_LVDS,
7ee933a1
HS		 1308};
1309
d47df633
PZ		 1310static const struct drm_display_mode avic_tm070ddh03_mode = {
1311 .clock = 51200,
1312 .hdisplay = 1024,
1313 .hsync_start = 1024 + 160,
1314 .hsync_end = 1024 + 160 + 4,
1315 .htotal = 1024 + 160 + 4 + 156,
1316 .vdisplay = 600,
1317 .vsync_start = 600 + 17,
1318 .vsync_end = 600 + 17 + 1,
1319 .vtotal = 600 + 17 + 1 + 17,
d47df633
PZ		 1320};
1321
1322static const struct panel_desc avic_tm070ddh03 = {
1323 .modes = &avic_tm070ddh03_mode,
1324 .num_modes = 1,
1325 .bpc = 8,
1326 .size = {
1327 .width = 154,
1328 .height = 90,
1329 },
1330 .delay = {
1331 .prepare = 20,
1332 .enable = 200,
1333 .disable = 200,
1334 },
1335};
1336
7ad8b41c
CYT		 1337static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1338 .clock = 30000,
1339 .hdisplay = 800,
1340 .hsync_start = 800 + 40,
1341 .hsync_end = 800 + 40 + 48,
1342 .htotal = 800 + 40 + 48 + 40,
1343 .vdisplay = 480,
1344 .vsync_start = 480 + 13,
1345 .vsync_end = 480 + 13 + 3,
1346 .vtotal = 480 + 13 + 3 + 29,
1347};
1348
1349static const struct panel_desc bananapi_s070wv20_ct16 = {
1350 .modes = &bananapi_s070wv20_ct16_mode,
1351 .num_modes = 1,
1352 .bpc = 6,
1353 .size = {
1354 .width = 154,
1355 .height = 86,
1356 },
1357};
1358
eeaddab4
TL		 1359static const struct drm_display_mode boe_bp101wx1_100_mode = {
1360 .clock = 78945,
1361 .hdisplay = 1280,
1362 .hsync_start = 1280 + 0,
1363 .hsync_end = 1280 + 0 + 2,
1364 .htotal = 1280 + 62 + 0 + 2,
1365 .vdisplay = 800,
1366 .vsync_start = 800 + 8,
1367 .vsync_end = 800 + 8 + 2,
1368 .vtotal = 800 + 6 + 8 + 2,
1369};
1370
dc90214f
TL		 1371static const struct panel_desc boe_bp082wx1_100 = {
1372 .modes = &boe_bp101wx1_100_mode,
1373 .num_modes = 1,
1374 .bpc = 8,
1375 .size = {
1376 .width = 177,
1377 .height = 110,
1378 },
1379 .delay = {
1380 .enable = 50,
1381 .disable = 50,
1382 },
1383 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1384 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1385 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1386};
1387
eeaddab4
TL		 1388static const struct panel_desc boe_bp101wx1_100 = {
1389 .modes = &boe_bp101wx1_100_mode,
1390 .num_modes = 1,
1391 .bpc = 8,
1392 .size = {
1393 .width = 217,
1394 .height = 136,
1395 },
1396 .delay = {
1397 .enable = 50,
1398 .disable = 50,
1399 },
1400 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1401 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1402 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1403};
1404
8bb7c7bc
LY		 1405static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1406 .pixelclock = { 69922000, 71000000, 72293000 },
1407 .hactive = { 1280, 1280, 1280 },
1408 .hfront_porch = { 48, 48, 48 },
1409 .hback_porch = { 80, 80, 80 },
1410 .hsync_len = { 32, 32, 32 },
1411 .vactive = { 800, 800, 800 },
1412 .vfront_porch = { 3, 3, 3 },
1413 .vback_porch = { 14, 14, 14 },
1414 .vsync_len = { 6, 6, 6 },
1415};
1416
1417static const struct panel_desc boe_ev121wxm_n10_1850 = {
1418 .timings = &boe_ev121wxm_n10_1850_timing,
1419 .num_timings = 1,
1420 .bpc = 8,
1421 .size = {
1422 .width = 261,
1423 .height = 163,
1424 },
1425 .delay = {
1426 .prepare = 9,
1427 .enable = 300,
1428 .unprepare = 300,
1429 .disable = 560,
1430 },
1431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1432 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1433 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1434};
1435
ae8cf41b 1436static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 1437 .clock = 42105,
ae8cf41b 1438 .hdisplay = 1024,
e077e2f5
AH		 1439 .hsync_start = 1024 + 30,
1440 .hsync_end = 1024 + 30 + 30,
1441 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 1442 .vdisplay = 600,
e077e2f5
AH		 1443 .vsync_start = 600 + 10,
1444 .vsync_end = 600 + 10 + 10,
1445 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 1446};
1447
1448static const struct panel_desc boe_hv070wsa = {
1449 .modes = &boe_hv070wsa_mode,
1450 .num_modes = 1,
2a5c2ff5 1451 .bpc = 8,
ae8cf41b
AH		 1452 .size = {
1453 .width = 154,
1454 .height = 90,
1455 },
2a5c2ff5
SR		 1456 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1457 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1458 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ae8cf41b
AH		 1459};
1460
751b5841
JD		 1461static const struct display_timing cct_cmt430b19n00_timing = {
1462 .pixelclock = { 8000000, 9000000, 12000000 },
1463 .hactive = { 480, 480, 480 },
1464 .hfront_porch = { 2, 8, 75 },
1465 .hback_porch = { 3, 43, 43 },
1466 .hsync_len = { 2, 4, 75 },
1467 .vactive = { 272, 272, 272 },
1468 .vfront_porch = { 2, 8, 37 },
1469 .vback_porch = { 2, 12, 12 },
1470 .vsync_len = { 2, 4, 37 },
1471 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW
1472};
1473
1474static const struct panel_desc cct_cmt430b19n00 = {
1475 .timings = &cct_cmt430b19n00_timing,
1476 .num_timings = 1,
1477 .bpc = 8,
1478 .size = {
1479 .width = 95,
1480 .height = 53,
1481 },
1482 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1483 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1484 .connector_type = DRM_MODE_CONNECTOR_DPI,
1485};
1486
e58edce6
GB		 1487static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1488 .clock = 9000,
1489 .hdisplay = 480,
1490 .hsync_start = 480 + 5,
1491 .hsync_end = 480 + 5 + 5,
1492 .htotal = 480 + 5 + 5 + 40,
1493 .vdisplay = 272,
1494 .vsync_start = 272 + 8,
1495 .vsync_end = 272 + 8 + 8,
1496 .vtotal = 272 + 8 + 8 + 8,
e58edce6
GB		 1497 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1498};
1499
1500static const struct panel_desc cdtech_s043wq26h_ct7 = {
1501 .modes = &cdtech_s043wq26h_ct7_mode,
1502 .num_modes = 1,
1503 .bpc = 8,
1504 .size = {
1505 .width = 95,
1506 .height = 54,
1507 },
88bc4178 1508 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1509};
1510
0e3b67f6
MK		 1511/* S070PWS19HP-FC21 2017/04/22 */
1512static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1513 .clock = 51200,
1514 .hdisplay = 1024,
1515 .hsync_start = 1024 + 160,
1516 .hsync_end = 1024 + 160 + 20,
1517 .htotal = 1024 + 160 + 20 + 140,
1518 .vdisplay = 600,
1519 .vsync_start = 600 + 12,
1520 .vsync_end = 600 + 12 + 3,
1521 .vtotal = 600 + 12 + 3 + 20,
1522 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1523};
1524
1525static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1526 .modes = &cdtech_s070pws19hp_fc21_mode,
1527 .num_modes = 1,
1528 .bpc = 6,
1529 .size = {
1530 .width = 154,
1531 .height = 86,
1532 },
1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1534 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1535 .connector_type = DRM_MODE_CONNECTOR_DPI,
1536};
1537
1538/* S070SWV29HG-DC44 2017/09/21 */
1539static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1540 .clock = 33300,
1541 .hdisplay = 800,
1542 .hsync_start = 800 + 210,
1543 .hsync_end = 800 + 210 + 2,
1544 .htotal = 800 + 210 + 2 + 44,
1545 .vdisplay = 480,
1546 .vsync_start = 480 + 22,
1547 .vsync_end = 480 + 22 + 2,
1548 .vtotal = 480 + 22 + 2 + 21,
1549 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1550};
1551
1552static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1553 .modes = &cdtech_s070swv29hg_dc44_mode,
1554 .num_modes = 1,
1555 .bpc = 6,
1556 .size = {
1557 .width = 154,
1558 .height = 86,
1559 },
1560 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1562 .connector_type = DRM_MODE_CONNECTOR_DPI,
1563};
1564
982f944e
GB		 1565static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1566 .clock = 35000,
1567 .hdisplay = 800,
1568 .hsync_start = 800 + 40,
1569 .hsync_end = 800 + 40 + 40,
1570 .htotal = 800 + 40 + 40 + 48,
1571 .vdisplay = 480,
1572 .vsync_start = 480 + 29,
1573 .vsync_end = 480 + 29 + 13,
1574 .vtotal = 480 + 29 + 13 + 3,
982f944e
GB		 1575 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1576};
1577
1578static const struct panel_desc cdtech_s070wv95_ct16 = {
1579 .modes = &cdtech_s070wv95_ct16_mode,
1580 .num_modes = 1,
1581 .bpc = 8,
1582 .size = {
1583 .width = 154,
1584 .height = 85,
1585 },
1586};
1587
07c913c4
MV		 1588static const struct display_timing chefree_ch101olhlwh_002_timing = {
1589 .pixelclock = { 68900000, 71100000, 73400000 },
1590 .hactive = { 1280, 1280, 1280 },
1591 .hfront_porch = { 65, 80, 95 },
1592 .hback_porch = { 64, 79, 94 },
1593 .hsync_len = { 1, 1, 1 },
1594 .vactive = { 800, 800, 800 },
1595 .vfront_porch = { 7, 11, 14 },
1596 .vback_porch = { 7, 11, 14 },
1597 .vsync_len = { 1, 1, 1 },
1598 .flags = DISPLAY_FLAGS_DE_HIGH,
1599};
1600
1601static const struct panel_desc chefree_ch101olhlwh_002 = {
1602 .timings = &chefree_ch101olhlwh_002_timing,
1603 .num_timings = 1,
1604 .bpc = 8,
1605 .size = {
1606 .width = 217,
1607 .height = 135,
1608 },
1609 .delay = {
1610 .enable = 200,
1611 .disable = 200,
1612 },
1613 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1614 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1615 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1616};
1617
2cb35c80
RL		 1618static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1619 .clock = 66770,
1620 .hdisplay = 800,
1621 .hsync_start = 800 + 49,
1622 .hsync_end = 800 + 49 + 33,
1623 .htotal = 800 + 49 + 33 + 17,
1624 .vdisplay = 1280,
1625 .vsync_start = 1280 + 1,
1626 .vsync_end = 1280 + 1 + 7,
1627 .vtotal = 1280 + 1 + 7 + 15,
2cb35c80
RL		 1628 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1629};
1630
1631static const struct panel_desc chunghwa_claa070wp03xg = {
1632 .modes = &chunghwa_claa070wp03xg_mode,
1633 .num_modes = 1,
1634 .bpc = 6,
1635 .size = {
1636 .width = 94,
1637 .height = 150,
1638 },
85560829 1639 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1640 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1641 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2cb35c80
RL		 1642};
1643
4c930757
SW		 1644static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1645 .clock = 72070,
1646 .hdisplay = 1366,
1647 .hsync_start = 1366 + 58,
1648 .hsync_end = 1366 + 58 + 58,
1649 .htotal = 1366 + 58 + 58 + 58,
1650 .vdisplay = 768,
1651 .vsync_start = 768 + 4,
1652 .vsync_end = 768 + 4 + 4,
1653 .vtotal = 768 + 4 + 4 + 4,
4c930757
SW		 1654};
1655
1656static const struct panel_desc chunghwa_claa101wa01a = {
1657 .modes = &chunghwa_claa101wa01a_mode,
1658 .num_modes = 1,
0208d511 1659 .bpc = 6,
4c930757
SW		 1660 .size = {
1661 .width = 220,
1662 .height = 120,
1663 },
85560829 1664 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1665 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1666 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4c930757
SW		 1667};
1668
280921de
TR		 1669static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1670 .clock = 69300,
1671 .hdisplay = 1366,
1672 .hsync_start = 1366 + 48,
1673 .hsync_end = 1366 + 48 + 32,
1674 .htotal = 1366 + 48 + 32 + 20,
1675 .vdisplay = 768,
1676 .vsync_start = 768 + 16,
1677 .vsync_end = 768 + 16 + 8,
1678 .vtotal = 768 + 16 + 8 + 16,
280921de
TR		 1679};
1680
1681static const struct panel_desc chunghwa_claa101wb01 = {
1682 .modes = &chunghwa_claa101wb01_mode,
1683 .num_modes = 1,
0208d511 1684 .bpc = 6,
280921de
TR		 1685 .size = {
1686 .width = 223,
1687 .height = 125,
1688 },
85560829 1689 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1690 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1691 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 1692};
1693
4dd024d4
MV		 1694static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1695 .pixelclock = { 5000000, 9000000, 12000000 },
1696 .hactive = { 480, 480, 480 },
1697 .hfront_porch = { 12, 12, 12 },
1698 .hback_porch = { 12, 12, 12 },
1699 .hsync_len = { 21, 21, 21 },
1700 .vactive = { 272, 272, 272 },
1701 .vfront_porch = { 4, 4, 4 },
1702 .vback_porch = { 4, 4, 4 },
1703 .vsync_len = { 8, 8, 8 },
1704};
1705
1706static const struct panel_desc dataimage_fg040346dsswbg04 = {
1707 .timings = &dataimage_fg040346dsswbg04_timing,
1708 .num_timings = 1,
1709 .bpc = 8,
1710 .size = {
1711 .width = 95,
1712 .height = 54,
1713 },
1714 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1715 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1716 .connector_type = DRM_MODE_CONNECTOR_DPI,
1717};
1718
803481d8
PO		 1719static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1720 .pixelclock = { 68900000, 71110000, 73400000 },
1721 .hactive = { 1280, 1280, 1280 },
1722 .vactive = { 800, 800, 800 },
1723 .hback_porch = { 100, 100, 100 },
1724 .hfront_porch = { 100, 100, 100 },
1725 .vback_porch = { 5, 5, 5 },
1726 .vfront_porch = { 5, 5, 5 },
1727 .hsync_len = { 24, 24, 24 },
1728 .vsync_len = { 3, 3, 3 },
1729 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1730 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1731};
1732
1733static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1734 .timings = &dataimage_fg1001l0dsswmg01_timing,
1735 .num_timings = 1,
1736 .bpc = 8,
1737 .size = {
1738 .width = 217,
1739 .height = 136,
1740 },
1741};
1742
97ceb1fb
MV		 1743static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1744 .clock = 33260,
1745 .hdisplay = 800,
1746 .hsync_start = 800 + 40,
1747 .hsync_end = 800 + 40 + 128,
1748 .htotal = 800 + 40 + 128 + 88,
1749 .vdisplay = 480,
1750 .vsync_start = 480 + 10,
1751 .vsync_end = 480 + 10 + 2,
1752 .vtotal = 480 + 10 + 2 + 33,
97ceb1fb
MV		 1753 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1754};
1755
1756static const struct panel_desc dataimage_scf0700c48ggu18 = {
1757 .modes = &dataimage_scf0700c48ggu18_mode,
1758 .num_modes = 1,
1759 .bpc = 8,
1760 .size = {
1761 .width = 152,
1762 .height = 91,
1763 },
1764 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1766};
1767
0ca0c827
PZ		 1768static const struct display_timing dlc_dlc0700yzg_1_timing = {
1769 .pixelclock = { 45000000, 51200000, 57000000 },
1770 .hactive = { 1024, 1024, 1024 },
1771 .hfront_porch = { 100, 106, 113 },
1772 .hback_porch = { 100, 106, 113 },
1773 .hsync_len = { 100, 108, 114 },
1774 .vactive = { 600, 600, 600 },
1775 .vfront_porch = { 8, 11, 15 },
1776 .vback_porch = { 8, 11, 15 },
1777 .vsync_len = { 9, 13, 15 },
1778 .flags = DISPLAY_FLAGS_DE_HIGH,
1779};
1780
1781static const struct panel_desc dlc_dlc0700yzg_1 = {
1782 .timings = &dlc_dlc0700yzg_1_timing,
1783 .num_timings = 1,
1784 .bpc = 6,
1785 .size = {
1786 .width = 154,
1787 .height = 86,
1788 },
1789 .delay = {
1790 .prepare = 30,
1791 .enable = 200,
1792 .disable = 200,
1793 },
1794 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1795 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1796};
1797
6cbe7cd1
MF		 1798static const struct display_timing dlc_dlc1010gig_timing = {
1799 .pixelclock = { 68900000, 71100000, 73400000 },
1800 .hactive = { 1280, 1280, 1280 },
1801 .hfront_porch = { 43, 53, 63 },
1802 .hback_porch = { 43, 53, 63 },
1803 .hsync_len = { 44, 54, 64 },
1804 .vactive = { 800, 800, 800 },
1805 .vfront_porch = { 5, 8, 11 },
1806 .vback_porch = { 5, 8, 11 },
1807 .vsync_len = { 5, 7, 11 },
1808 .flags = DISPLAY_FLAGS_DE_HIGH,
1809};
1810
1811static const struct panel_desc dlc_dlc1010gig = {
1812 .timings = &dlc_dlc1010gig_timing,
1813 .num_timings = 1,
1814 .bpc = 8,
1815 .size = {
1816 .width = 216,
1817 .height = 135,
1818 },
1819 .delay = {
1820 .prepare = 60,
1821 .enable = 150,
1822 .disable = 100,
1823 .unprepare = 60,
1824 },
1825 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1826 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1827};
1828
c2d24af6
AP		 1829static const struct drm_display_mode edt_et035012dm6_mode = {
1830 .clock = 6500,
1831 .hdisplay = 320,
1832 .hsync_start = 320 + 20,
1833 .hsync_end = 320 + 20 + 30,
1834 .htotal = 320 + 20 + 68,
1835 .vdisplay = 240,
1836 .vsync_start = 240 + 4,
1837 .vsync_end = 240 + 4 + 4,
1838 .vtotal = 240 + 4 + 4 + 14,
c2d24af6
AP		 1839 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1840};
1841
1842static const struct panel_desc edt_et035012dm6 = {
1843 .modes = &edt_et035012dm6_mode,
1844 .num_modes = 1,
1845 .bpc = 8,
1846 .size = {
1847 .width = 70,
1848 .height = 52,
1849 },
1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1851 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
c2d24af6
AP		 1852};
1853
f08a2a1e
SR		 1854static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1855 .clock = 6520,
1856 .hdisplay = 320,
1857 .hsync_start = 320 + 20,
1858 .hsync_end = 320 + 20 + 68,
1859 .htotal = 320 + 20 + 68,
1860 .vdisplay = 240,
1861 .vsync_start = 240 + 4,
1862 .vsync_end = 240 + 4 + 18,
1863 .vtotal = 240 + 4 + 18,
1864 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1865};
1866
1867static const struct panel_desc edt_etm0350g0dh6 = {
1868 .modes = &edt_etm0350g0dh6_mode,
1869 .num_modes = 1,
1870 .bpc = 6,
1871 .size = {
1872 .width = 70,
1873 .height = 53,
1874 },
1875 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1876 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1877 .connector_type = DRM_MODE_CONNECTOR_DPI,
1878};
1879
82d57a59
MCR		 1880static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1881 .clock = 10870,
1882 .hdisplay = 480,
1883 .hsync_start = 480 + 8,
1884 .hsync_end = 480 + 8 + 4,
1885 .htotal = 480 + 8 + 4 + 41,
1886
1887 /*
1888 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1889 * fb_align
1890 */
1891
1892 .vdisplay = 288,
1893 .vsync_start = 288 + 2,
1894 .vsync_end = 288 + 2 + 4,
1895 .vtotal = 288 + 2 + 4 + 10,
82d57a59
MCR		 1896};
1897
1898static const struct panel_desc edt_etm043080dh6gp = {
1899 .modes = &edt_etm043080dh6gp_mode,
1900 .num_modes = 1,
1901 .bpc = 8,
1902 .size = {
1903 .width = 100,
1904 .height = 65,
1905 },
1906 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1907 .connector_type = DRM_MODE_CONNECTOR_DPI,
1908};
1909
fd819bff
MV		 1910static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1911 .clock = 9000,
1912 .hdisplay = 480,
1913 .hsync_start = 480 + 2,
1914 .hsync_end = 480 + 2 + 41,
1915 .htotal = 480 + 2 + 41 + 2,
1916 .vdisplay = 272,
1917 .vsync_start = 272 + 2,
1918 .vsync_end = 272 + 2 + 10,
1919 .vtotal = 272 + 2 + 10 + 2,
fd819bff
MV		 1920 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1921};
1922
1923static const struct panel_desc edt_etm0430g0dh6 = {
1924 .modes = &edt_etm0430g0dh6_mode,
1925 .num_modes = 1,
1926 .bpc = 6,
1927 .size = {
1928 .width = 95,
1929 .height = 54,
1930 },
4824a5f7
SR		 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1932 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d112e10f 1933 .connector_type = DRM_MODE_CONNECTOR_DPI,
fd819bff
MV		 1934};
1935
26ab0065
SA		 1936static const struct drm_display_mode edt_et057090dhu_mode = {
1937 .clock = 25175,
1938 .hdisplay = 640,
1939 .hsync_start = 640 + 16,
1940 .hsync_end = 640 + 16 + 30,
1941 .htotal = 640 + 16 + 30 + 114,
1942 .vdisplay = 480,
1943 .vsync_start = 480 + 10,
1944 .vsync_end = 480 + 10 + 3,
1945 .vtotal = 480 + 10 + 3 + 32,
26ab0065
SA		 1946 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1947};
1948
1949static const struct panel_desc edt_et057090dhu = {
1950 .modes = &edt_et057090dhu_mode,
1951 .num_modes = 1,
0208d511 1952 .bpc = 6,
26ab0065
SA		 1953 .size = {
1954 .width = 115,
1955 .height = 86,
1956 },
eaeebffa 1957 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1958 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
75e73224 1959 .connector_type = DRM_MODE_CONNECTOR_DPI,
26ab0065
SA		 1960};
1961
fff5de45
PZ		 1962static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1963 .clock = 33260,
1964 .hdisplay = 800,
1965 .hsync_start = 800 + 40,
1966 .hsync_end = 800 + 40 + 128,
1967 .htotal = 800 + 40 + 128 + 88,
1968 .vdisplay = 480,
1969 .vsync_start = 480 + 10,
1970 .vsync_end = 480 + 10 + 2,
1971 .vtotal = 480 + 10 + 2 + 33,
fff5de45
PZ		 1972 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1973};
1974
1975static const struct panel_desc edt_etm0700g0dh6 = {
1976 .modes = &edt_etm0700g0dh6_mode,
1977 .num_modes = 1,
0208d511 1978 .bpc = 6,
fff5de45
PZ		 1979 .size = {
1980 .width = 152,
1981 .height = 91,
1982 },
eaeebffa 1983 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1984 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
281edb9f 1985 .connector_type = DRM_MODE_CONNECTOR_DPI,
fff5de45
PZ		 1986};
1987
aa7e6455
JT		 1988static const struct panel_desc edt_etm0700g0bdh6 = {
1989 .modes = &edt_etm0700g0dh6_mode,
1990 .num_modes = 1,
1991 .bpc = 6,
1992 .size = {
1993 .width = 152,
1994 .height = 91,
1995 },
1996 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1997 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
d112e10f 1998 .connector_type = DRM_MODE_CONNECTOR_DPI,
aa7e6455
JT		 1999};
2000
a6cc3c72
MF		 2001static const struct display_timing edt_etml0700y5dha_timing = {
2002 .pixelclock = { 40800000, 51200000, 67200000 },
2003 .hactive = { 1024, 1024, 1024 },
2004 .hfront_porch = { 30, 106, 125 },
2005 .hback_porch = { 30, 106, 125 },
2006 .hsync_len = { 30, 108, 126 },
2007 .vactive = { 600, 600, 600 },
2008 .vfront_porch = { 3, 12, 67},
2009 .vback_porch = { 3, 12, 67 },
2010 .vsync_len = { 4, 11, 66 },
2011 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2012 DISPLAY_FLAGS_DE_HIGH,
2013};
2014
2015static const struct panel_desc edt_etml0700y5dha = {
2016 .timings = &edt_etml0700y5dha_timing,
2017 .num_timings = 1,
2018 .bpc = 8,
2019 .size = {
2020 .width = 155,
2021 .height = 86,
2022 },
2023 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2024 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2025};
2026
aeb262c3
PF		 2027static const struct display_timing edt_etml1010g3dra_timing = {
2028 .pixelclock = { 66300000, 72400000, 78900000 },
2029 .hactive = { 1280, 1280, 1280 },
2030 .hfront_porch = { 12, 72, 132 },
2031 .hback_porch = { 86, 86, 86 },
2032 .hsync_len = { 2, 2, 2 },
2033 .vactive = { 800, 800, 800 },
2034 .vfront_porch = { 1, 15, 49 },
2035 .vback_porch = { 21, 21, 21 },
2036 .vsync_len = { 2, 2, 2 },
2037 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
2038 DISPLAY_FLAGS_DE_HIGH,
2039};
2040
2041static const struct panel_desc edt_etml1010g3dra = {
2042 .timings = &edt_etml1010g3dra_timing,
2043 .num_timings = 1,
2044 .bpc = 8,
2045 .size = {
2046 .width = 216,
2047 .height = 135,
2048 },
2049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2050 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2051 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2052};
2053
e46f73fb
SR		 2054static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2055 .clock = 25175,
2056 .hdisplay = 640,
2057 .hsync_start = 640,
2058 .hsync_end = 640 + 16,
2059 .htotal = 640 + 16 + 30 + 114,
2060 .vdisplay = 480,
2061 .vsync_start = 480 + 10,
2062 .vsync_end = 480 + 10 + 3,
2063 .vtotal = 480 + 10 + 3 + 35,
2064 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2065};
2066
2067static const struct panel_desc edt_etmv570g2dhu = {
2068 .modes = &edt_etmv570g2dhu_mode,
2069 .num_modes = 1,
2070 .bpc = 6,
2071 .size = {
2072 .width = 115,
2073 .height = 86,
2074 },
2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2076 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2077 .connector_type = DRM_MODE_CONNECTOR_DPI,
2078};
2079
9746f5fe
AF		 2080static const struct display_timing eink_vb3300_kca_timing = {
2081 .pixelclock = { 40000000, 40000000, 40000000 },
2082 .hactive = { 334, 334, 334 },
2083 .hfront_porch = { 1, 1, 1 },
2084 .hback_porch = { 1, 1, 1 },
2085 .hsync_len = { 1, 1, 1 },
2086 .vactive = { 1405, 1405, 1405 },
2087 .vfront_porch = { 1, 1, 1 },
2088 .vback_porch = { 1, 1, 1 },
2089 .vsync_len = { 1, 1, 1 },
2090 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2091 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2092};
2093
2094static const struct panel_desc eink_vb3300_kca = {
2095 .timings = &eink_vb3300_kca_timing,
2096 .num_timings = 1,
2097 .bpc = 6,
2098 .size = {
2099 .width = 157,
2100 .height = 209,
2101 },
2102 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2103 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2104 .connector_type = DRM_MODE_CONNECTOR_DPI,
2105};
2106
1319f217
MW		 2107static const struct display_timing evervision_vgg644804_timing = {
2108 .pixelclock = { 25175000, 25175000, 25175000 },
2109 .hactive = { 640, 640, 640 },
2110 .hfront_porch = { 16, 16, 16 },
2111 .hback_porch = { 82, 114, 170 },
2112 .hsync_len = { 5, 30, 30 },
2113 .vactive = { 480, 480, 480 },
2114 .vfront_porch = { 10, 10, 10 },
2115 .vback_porch = { 30, 32, 34 },
2116 .vsync_len = { 1, 3, 5 },
2117 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2118 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2119 DISPLAY_FLAGS_SYNC_POSEDGE,
2120};
2121
2122static const struct panel_desc evervision_vgg644804 = {
2123 .timings = &evervision_vgg644804_timing,
2124 .num_timings = 1,
2125 .bpc = 8,
2126 .size = {
2127 .width = 115,
2128 .height = 86,
2129 },
2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2131 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2132};
2133
9158e3c3
MF		 2134static const struct display_timing evervision_vgg804821_timing = {
2135 .pixelclock = { 27600000, 33300000, 50000000 },
2136 .hactive = { 800, 800, 800 },
2137 .hfront_porch = { 40, 66, 70 },
2138 .hback_porch = { 40, 67, 70 },
2139 .hsync_len = { 40, 67, 70 },
2140 .vactive = { 480, 480, 480 },
2141 .vfront_porch = { 6, 10, 10 },
2142 .vback_porch = { 7, 11, 11 },
2143 .vsync_len = { 7, 11, 11 },
2144 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2145 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2146 DISPLAY_FLAGS_SYNC_NEGEDGE,
2147};
2148
2149static const struct panel_desc evervision_vgg804821 = {
2150 .timings = &evervision_vgg804821_timing,
2151 .num_timings = 1,
2152 .bpc = 8,
2153 .size = {
2154 .width = 108,
2155 .height = 64,
2156 },
2157 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2158 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
9158e3c3
MF		 2159};
2160
102932b0
BB		 2161static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2162 .clock = 32260,
2163 .hdisplay = 800,
2164 .hsync_start = 800 + 168,
2165 .hsync_end = 800 + 168 + 64,
2166 .htotal = 800 + 168 + 64 + 88,
2167 .vdisplay = 480,
2168 .vsync_start = 480 + 37,
2169 .vsync_end = 480 + 37 + 2,
2170 .vtotal = 480 + 37 + 2 + 8,
102932b0
BB		 2171};
2172
2173static const struct panel_desc foxlink_fl500wvr00_a0t = {
2174 .modes = &foxlink_fl500wvr00_a0t_mode,
2175 .num_modes = 1,
d7a839cd 2176 .bpc = 8,
102932b0
BB		 2177 .size = {
2178 .width = 108,
2179 .height = 65,
2180 },
bb276cb3 2181 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 2182};
2183
795db2af
PC		 2184static const struct drm_display_mode frida_frd350h54004_modes[] = {
2185 { /* 60 Hz */
2186 .clock = 6000,
2187 .hdisplay = 320,
2188 .hsync_start = 320 + 44,
2189 .hsync_end = 320 + 44 + 16,
2190 .htotal = 320 + 44 + 16 + 20,
2191 .vdisplay = 240,
2192 .vsync_start = 240 + 2,
2193 .vsync_end = 240 + 2 + 6,
2194 .vtotal = 240 + 2 + 6 + 2,
2195 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2196 },
2197 { /* 50 Hz */
2198 .clock = 5400,
2199 .hdisplay = 320,
2200 .hsync_start = 320 + 56,
2201 .hsync_end = 320 + 56 + 16,
2202 .htotal = 320 + 56 + 16 + 40,
2203 .vdisplay = 240,
2204 .vsync_start = 240 + 2,
2205 .vsync_end = 240 + 2 + 6,
2206 .vtotal = 240 + 2 + 6 + 2,
2207 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2208 },
7b6bd843
PC		 2209};
2210
2211static const struct panel_desc frida_frd350h54004 = {
795db2af
PC		 2212 .modes = frida_frd350h54004_modes,
2213 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
7b6bd843
PC		 2214 .bpc = 8,
2215 .size = {
2216 .width = 77,
2217 .height = 64,
2218 },
2219 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2220 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
7b6bd843
PC		 2221 .connector_type = DRM_MODE_CONNECTOR_DPI,
2222};
2223
3be20710
JT		 2224static const struct drm_display_mode friendlyarm_hd702e_mode = {
2225 .clock = 67185,
2226 .hdisplay = 800,
2227 .hsync_start = 800 + 20,
2228 .hsync_end = 800 + 20 + 24,
2229 .htotal = 800 + 20 + 24 + 20,
2230 .vdisplay = 1280,
2231 .vsync_start = 1280 + 4,
2232 .vsync_end = 1280 + 4 + 8,
2233 .vtotal = 1280 + 4 + 8 + 4,
3be20710
JT		 2234 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2235};
2236
2237static const struct panel_desc friendlyarm_hd702e = {
2238 .modes = &friendlyarm_hd702e_mode,
2239 .num_modes = 1,
2240 .size = {
2241 .width = 94,
2242 .height = 151,
2243 },
2244};
2245
d435a2af
PZ		 2246static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2247 .clock = 9000,
2248 .hdisplay = 480,
2249 .hsync_start = 480 + 5,
2250 .hsync_end = 480 + 5 + 1,
2251 .htotal = 480 + 5 + 1 + 40,
2252 .vdisplay = 272,
2253 .vsync_start = 272 + 8,
2254 .vsync_end = 272 + 8 + 1,
2255 .vtotal = 272 + 8 + 1 + 8,
d435a2af
PZ		 2256};
2257
2258static const struct panel_desc giantplus_gpg482739qs5 = {
2259 .modes = &giantplus_gpg482739qs5_mode,
2260 .num_modes = 1,
2261 .bpc = 8,
2262 .size = {
2263 .width = 95,
2264 .height = 54,
2265 },
33536a09 2266 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 2267};
2268
2c6574a9
PC		 2269static const struct display_timing giantplus_gpm940b0_timing = {
2270 .pixelclock = { 13500000, 27000000, 27500000 },
2271 .hactive = { 320, 320, 320 },
2272 .hfront_porch = { 14, 686, 718 },
2273 .hback_porch = { 50, 70, 255 },
2274 .hsync_len = { 1, 1, 1 },
2275 .vactive = { 240, 240, 240 },
2276 .vfront_porch = { 1, 1, 179 },
2277 .vback_porch = { 1, 21, 31 },
2278 .vsync_len = { 1, 1, 6 },
2279 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2280};
2281
2282static const struct panel_desc giantplus_gpm940b0 = {
2283 .timings = &giantplus_gpm940b0_timing,
2284 .num_timings = 1,
2285 .bpc = 8,
2286 .size = {
2287 .width = 60,
2288 .height = 45,
2289 },
2290 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
f5436f77 2291 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2c6574a9
PC		 2292};
2293
ab07725a
PZ		 2294static const struct display_timing hannstar_hsd070pww1_timing = {
2295 .pixelclock = { 64300000, 71100000, 82000000 },
2296 .hactive = { 1280, 1280, 1280 },
2297 .hfront_porch = { 1, 1, 10 },
2298 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 2299 /*
2300 * According to the data sheet, the minimum horizontal blanking interval
2301 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2302 * minimum working horizontal blanking interval to be 60 clocks.
2303 */
2304 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 2305 .vactive = { 800, 800, 800 },
2306 .vfront_porch = { 1, 1, 10 },
2307 .vback_porch = { 1, 1, 10 },
2308 .vsync_len = { 1, 21, 203 },
2309 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 2310};
2311
2312static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 2313 .timings = &hannstar_hsd070pww1_timing,
2314 .num_timings = 1,
a853205e
PZ		 2315 .bpc = 6,
2316 .size = {
2317 .width = 151,
2318 .height = 94,
2319 },
58d6a7bc 2320 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2321 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 2322};
2323
c0d607e5
EN		 2324static const struct display_timing hannstar_hsd100pxn1_timing = {
2325 .pixelclock = { 55000000, 65000000, 75000000 },
2326 .hactive = { 1024, 1024, 1024 },
2327 .hfront_porch = { 40, 40, 40 },
2328 .hback_porch = { 220, 220, 220 },
2329 .hsync_len = { 20, 60, 100 },
2330 .vactive = { 768, 768, 768 },
2331 .vfront_porch = { 7, 7, 7 },
2332 .vback_porch = { 21, 21, 21 },
2333 .vsync_len = { 10, 10, 10 },
2334 .flags = DISPLAY_FLAGS_DE_HIGH,
2335};
2336
2337static const struct panel_desc hannstar_hsd100pxn1 = {
2338 .timings = &hannstar_hsd100pxn1_timing,
2339 .num_timings = 1,
2340 .bpc = 6,
2341 .size = {
2342 .width = 203,
2343 .height = 152,
2344 },
4946b043 2345 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2346 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 2347};
2348
170a41e9
SR		 2349static const struct display_timing hannstar_hsd101pww2_timing = {
2350 .pixelclock = { 64300000, 71100000, 82000000 },
2351 .hactive = { 1280, 1280, 1280 },
2352 .hfront_porch = { 1, 1, 10 },
2353 .hback_porch = { 1, 1, 10 },
2354 .hsync_len = { 58, 158, 661 },
2355 .vactive = { 800, 800, 800 },
2356 .vfront_porch = { 1, 1, 10 },
2357 .vback_porch = { 1, 1, 10 },
2358 .vsync_len = { 1, 21, 203 },
2359 .flags = DISPLAY_FLAGS_DE_HIGH,
2360};
2361
2362static const struct panel_desc hannstar_hsd101pww2 = {
2363 .timings = &hannstar_hsd101pww2_timing,
2364 .num_timings = 1,
2365 .bpc = 8,
2366 .size = {
2367 .width = 217,
2368 .height = 136,
2369 },
2370 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2371 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2372};
2373
61ac0bf8
LS		 2374static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2375 .clock = 33333,
2376 .hdisplay = 800,
2377 .hsync_start = 800 + 85,
2378 .hsync_end = 800 + 85 + 86,
2379 .htotal = 800 + 85 + 86 + 85,
2380 .vdisplay = 480,
2381 .vsync_start = 480 + 16,
2382 .vsync_end = 480 + 16 + 13,
2383 .vtotal = 480 + 16 + 13 + 16,
61ac0bf8
LS		 2384};
2385
2386static const struct panel_desc hitachi_tx23d38vm0caa = {
2387 .modes = &hitachi_tx23d38vm0caa_mode,
2388 .num_modes = 1,
2389 .bpc = 6,
2390 .size = {
2391 .width = 195,
2392 .height = 117,
2393 },
6c684e3b
PZ		 2394 .delay = {
2395 .enable = 160,
2396 .disable = 160,
2397 },
61ac0bf8
LS		 2398};
2399
41bcceb4
NF		 2400static const struct drm_display_mode innolux_at043tn24_mode = {
2401 .clock = 9000,
2402 .hdisplay = 480,
2403 .hsync_start = 480 + 2,
2404 .hsync_end = 480 + 2 + 41,
2405 .htotal = 480 + 2 + 41 + 2,
2406 .vdisplay = 272,
2407 .vsync_start = 272 + 2,
a483159d
PZ		 2408 .vsync_end = 272 + 2 + 10,
2409 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 2410 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2411};
2412
2413static const struct panel_desc innolux_at043tn24 = {
2414 .modes = &innolux_at043tn24_mode,
2415 .num_modes = 1,
2416 .bpc = 8,
2417 .size = {
2418 .width = 95,
2419 .height = 54,
2420 },
2421 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2c56a751 2422 .connector_type = DRM_MODE_CONNECTOR_DPI,
88bc4178 2423 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 2424};
2425
4fc24ab3
RB		 2426static const struct drm_display_mode innolux_at070tn92_mode = {
2427 .clock = 33333,
2428 .hdisplay = 800,
2429 .hsync_start = 800 + 210,
2430 .hsync_end = 800 + 210 + 20,
2431 .htotal = 800 + 210 + 20 + 46,
2432 .vdisplay = 480,
2433 .vsync_start = 480 + 22,
2434 .vsync_end = 480 + 22 + 10,
2435 .vtotal = 480 + 22 + 23 + 10,
4fc24ab3
RB		 2436};
2437
2438static const struct panel_desc innolux_at070tn92 = {
2439 .modes = &innolux_at070tn92_mode,
2440 .num_modes = 1,
2441 .size = {
2442 .width = 154,
2443 .height = 86,
2444 },
2445 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2446};
2447
1993f598
RL		 2448static const struct display_timing innolux_g070ace_l01_timing = {
2449 .pixelclock = { 25200000, 35000000, 35700000 },
2450 .hactive = { 800, 800, 800 },
2451 .hfront_porch = { 30, 32, 87 },
2452 .hback_porch = { 30, 32, 87 },
2453 .hsync_len = { 1, 1, 1 },
2454 .vactive = { 480, 480, 480 },
2455 .vfront_porch = { 3, 3, 3 },
2456 .vback_porch = { 13, 13, 13 },
2457 .vsync_len = { 1, 1, 4 },
2458 .flags = DISPLAY_FLAGS_DE_HIGH,
2459};
2460
2461static const struct panel_desc innolux_g070ace_l01 = {
2462 .timings = &innolux_g070ace_l01_timing,
2463 .num_timings = 1,
2464 .bpc = 8,
2465 .size = {
2466 .width = 152,
2467 .height = 91,
2468 },
2469 .delay = {
2470 .prepare = 10,
2471 .enable = 50,
2472 .disable = 50,
2473 .unprepare = 500,
2474 },
2475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2476 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2477 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2478};
2479
a5d2ade6
CF		 2480static const struct display_timing innolux_g070y2_l01_timing = {
2481 .pixelclock = { 28000000, 29500000, 32000000 },
2482 .hactive = { 800, 800, 800 },
2483 .hfront_porch = { 61, 91, 141 },
2484 .hback_porch = { 60, 90, 140 },
2485 .hsync_len = { 12, 12, 12 },
2486 .vactive = { 480, 480, 480 },
2487 .vfront_porch = { 4, 9, 30 },
2488 .vback_porch = { 4, 8, 28 },
2489 .vsync_len = { 2, 2, 2 },
2490 .flags = DISPLAY_FLAGS_DE_HIGH,
2491};
2492
2493static const struct panel_desc innolux_g070y2_l01 = {
2494 .timings = &innolux_g070y2_l01_timing,
2495 .num_timings = 1,
fc1b6ef7 2496 .bpc = 8,
a5d2ade6
CF		 2497 .size = {
2498 .width = 152,
2499 .height = 91,
2500 },
2501 .delay = {
2502 .prepare = 10,
2503 .enable = 100,
2504 .disable = 100,
2505 .unprepare = 800,
2506 },
2507 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
0f73a559 2508 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 2509 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 2510};
2511
57a06e90
OR		 2512static const struct drm_display_mode innolux_g070y2_t02_mode = {
2513 .clock = 33333,
2514 .hdisplay = 800,
2515 .hsync_start = 800 + 210,
2516 .hsync_end = 800 + 210 + 20,
2517 .htotal = 800 + 210 + 20 + 46,
2518 .vdisplay = 480,
2519 .vsync_start = 480 + 22,
2520 .vsync_end = 480 + 22 + 10,
2521 .vtotal = 480 + 22 + 23 + 10,
2522};
2523
2524static const struct panel_desc innolux_g070y2_t02 = {
2525 .modes = &innolux_g070y2_t02_mode,
2526 .num_modes = 1,
2527 .bpc = 8,
2528 .size = {
2529 .width = 152,
2530 .height = 92,
2531 },
2532 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2533 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2534 .connector_type = DRM_MODE_CONNECTOR_DPI,
2535};
2536
1e29b840
MO		 2537static const struct display_timing innolux_g101ice_l01_timing = {
2538 .pixelclock = { 60400000, 71100000, 74700000 },
2539 .hactive = { 1280, 1280, 1280 },
3f9a91b6
MV		 2540 .hfront_porch = { 30, 60, 70 },
2541 .hback_porch = { 30, 60, 70 },
2542 .hsync_len = { 22, 40, 60 },
1e29b840 2543 .vactive = { 800, 800, 800 },
3f9a91b6
MV		 2544 .vfront_porch = { 3, 8, 14 },
2545 .vback_porch = { 3, 8, 14 },
2546 .vsync_len = { 4, 7, 12 },
1e29b840
MO		 2547 .flags = DISPLAY_FLAGS_DE_HIGH,
2548};
2549
2550static const struct panel_desc innolux_g101ice_l01 = {
2551 .timings = &innolux_g101ice_l01_timing,
2552 .num_timings = 1,
2553 .bpc = 8,
2554 .size = {
2555 .width = 217,
2556 .height = 135,
2557 },
2558 .delay = {
2559 .enable = 200,
2560 .disable = 200,
2561 },
2562 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
06fc41b0 2563 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 2564 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 2565};
2566
4ae13e48
LS		 2567static const struct display_timing innolux_g121i1_l01_timing = {
2568 .pixelclock = { 67450000, 71000000, 74550000 },
2569 .hactive = { 1280, 1280, 1280 },
2570 .hfront_porch = { 40, 80, 160 },
2571 .hback_porch = { 39, 79, 159 },
2572 .hsync_len = { 1, 1, 1 },
2573 .vactive = { 800, 800, 800 },
2574 .vfront_porch = { 5, 11, 100 },
2575 .vback_porch = { 4, 11, 99 },
2576 .vsync_len = { 1, 1, 1 },
d731f661
LS		 2577};
2578
2579static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 2580 .timings = &innolux_g121i1_l01_timing,
2581 .num_timings = 1,
d731f661
LS		 2582 .bpc = 6,
2583 .size = {
2584 .width = 261,
2585 .height = 163,
2586 },
4ae13e48
LS		 2587 .delay = {
2588 .enable = 200,
2589 .disable = 20,
2590 },
a7c48a0a 2591 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2592 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 2593};
2594
90c53f2b
MV		 2595static const struct display_timing innolux_g121x1_l03_timings = {
2596 .pixelclock = { 57500000, 64900000, 74400000 },
2597 .hactive = { 1024, 1024, 1024 },
2598 .hfront_porch = { 90, 140, 190 },
2599 .hback_porch = { 90, 140, 190 },
2600 .hsync_len = { 36, 40, 60 },
2601 .vactive = { 768, 768, 768 },
2602 .vfront_porch = { 2, 15, 30 },
2603 .vback_porch = { 2, 15, 30 },
2604 .vsync_len = { 2, 8, 20 },
2605 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
f8fa17ba
AB		 2606};
2607
2608static const struct panel_desc innolux_g121x1_l03 = {
90c53f2b
MV		 2609 .timings = &innolux_g121x1_l03_timings,
2610 .num_timings = 1,
f8fa17ba
AB		 2611 .bpc = 6,
2612 .size = {
2613 .width = 246,
2614 .height = 185,
2615 },
2616 .delay = {
2617 .enable = 200,
2618 .unprepare = 200,
2619 .disable = 400,
2620 },
11ac72d0
MV		 2621 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2622 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2623 .connector_type = DRM_MODE_CONNECTOR_LVDS,
f8fa17ba
AB		 2624};
2625
f7ad2ce5
MV		 2626static const struct panel_desc innolux_g121xce_l01 = {
2627 .timings = &innolux_g121x1_l03_timings,
2628 .num_timings = 1,
2629 .bpc = 8,
2630 .size = {
2631 .width = 246,
2632 .height = 185,
2633 },
2634 .delay = {
2635 .enable = 200,
2636 .unprepare = 200,
2637 .disable = 400,
2638 },
2639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2640 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2641 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2642};
2643
eae74888 2644static const struct display_timing innolux_g156hce_l01_timings = {
438cf327 2645 .pixelclock = { 120000000, 141860000, 150000000 },
eae74888
MV		 2646 .hactive = { 1920, 1920, 1920 },
2647 .hfront_porch = { 80, 90, 100 },
2648 .hback_porch = { 80, 90, 100 },
2649 .hsync_len = { 20, 30, 30 },
2650 .vactive = { 1080, 1080, 1080 },
2651 .vfront_porch = { 3, 10, 20 },
2652 .vback_porch = { 3, 10, 20 },
2653 .vsync_len = { 4, 10, 10 },
2654};
2655
2656static const struct panel_desc innolux_g156hce_l01 = {
2657 .timings = &innolux_g156hce_l01_timings,
2658 .num_timings = 1,
2659 .bpc = 8,
2660 .size = {
2661 .width = 344,
2662 .height = 194,
2663 },
2664 .delay = {
2665 .prepare = 1, /* T1+T2 */
2666 .enable = 450, /* T5 */
2667 .disable = 200, /* T6 */
2668 .unprepare = 10, /* T3+T7 */
2669 },
2670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2672 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2673};
2674
ea44739d
AB		 2675static const struct drm_display_mode innolux_n156bge_l21_mode = {
2676 .clock = 69300,
2677 .hdisplay = 1366,
2678 .hsync_start = 1366 + 16,
2679 .hsync_end = 1366 + 16 + 34,
2680 .htotal = 1366 + 16 + 34 + 50,
2681 .vdisplay = 768,
2682 .vsync_start = 768 + 2,
2683 .vsync_end = 768 + 2 + 6,
2684 .vtotal = 768 + 2 + 6 + 12,
ea44739d
AB		 2685};
2686
2687static const struct panel_desc innolux_n156bge_l21 = {
2688 .modes = &innolux_n156bge_l21_mode,
2689 .num_modes = 1,
0208d511 2690 .bpc = 6,
ea44739d
AB		 2691 .size = {
2692 .width = 344,
2693 .height = 193,
2694 },
85560829 2695 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 2696 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 2697 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ea44739d
AB		 2698};
2699
bccac3f1
MG		 2700static const struct drm_display_mode innolux_zj070na_01p_mode = {
2701 .clock = 51501,
2702 .hdisplay = 1024,
2703 .hsync_start = 1024 + 128,
2704 .hsync_end = 1024 + 128 + 64,
2705 .htotal = 1024 + 128 + 64 + 128,
2706 .vdisplay = 600,
2707 .vsync_start = 600 + 16,
2708 .vsync_end = 600 + 16 + 4,
2709 .vtotal = 600 + 16 + 4 + 16,
bccac3f1
MG		 2710};
2711
2712static const struct panel_desc innolux_zj070na_01p = {
2713 .modes = &innolux_zj070na_01p_mode,
2714 .num_modes = 1,
2715 .bpc = 6,
2716 .size = {
81598846
TR		 2717 .width = 154,
2718 .height = 90,
bccac3f1
MG		 2719 },
2720};
2721
14bf60c4
LM		 2722static const struct display_timing koe_tx14d24vm1bpa_timing = {
2723 .pixelclock = { 5580000, 5850000, 6200000 },
2724 .hactive = { 320, 320, 320 },
2725 .hfront_porch = { 30, 30, 30 },
2726 .hback_porch = { 30, 30, 30 },
2727 .hsync_len = { 1, 5, 17 },
2728 .vactive = { 240, 240, 240 },
2729 .vfront_porch = { 6, 6, 6 },
2730 .vback_porch = { 5, 5, 5 },
2731 .vsync_len = { 1, 2, 11 },
2732 .flags = DISPLAY_FLAGS_DE_HIGH,
2733};
2734
2735static const struct panel_desc koe_tx14d24vm1bpa = {
2736 .timings = &koe_tx14d24vm1bpa_timing,
2737 .num_timings = 1,
2738 .bpc = 6,
2739 .size = {
2740 .width = 115,
2741 .height = 86,
2742 },
2743};
2744
8a070524
LY		 2745static const struct display_timing koe_tx26d202vm0bwa_timing = {
2746 .pixelclock = { 151820000, 156720000, 159780000 },
2747 .hactive = { 1920, 1920, 1920 },
2748 .hfront_porch = { 105, 130, 142 },
2749 .hback_porch = { 45, 70, 82 },
2750 .hsync_len = { 30, 30, 30 },
2751 .vactive = { 1200, 1200, 1200},
2752 .vfront_porch = { 3, 5, 10 },
2753 .vback_porch = { 2, 5, 10 },
2754 .vsync_len = { 5, 5, 5 },
37ce99b7 2755 .flags = DISPLAY_FLAGS_DE_HIGH,
8a070524
LY		 2756};
2757
2758static const struct panel_desc koe_tx26d202vm0bwa = {
2759 .timings = &koe_tx26d202vm0bwa_timing,
2760 .num_timings = 1,
2761 .bpc = 8,
2762 .size = {
2763 .width = 217,
2764 .height = 136,
2765 },
2766 .delay = {
2767 .prepare = 1000,
2768 .enable = 1000,
2769 .unprepare = 1000,
2770 .disable = 1000,
2771 },
2772 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2773 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
8a070524
LY		 2774 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2775};
2776
8cfe8341
JT		 2777static const struct display_timing koe_tx31d200vm0baa_timing = {
2778 .pixelclock = { 39600000, 43200000, 48000000 },
2779 .hactive = { 1280, 1280, 1280 },
2780 .hfront_porch = { 16, 36, 56 },
2781 .hback_porch = { 16, 36, 56 },
2782 .hsync_len = { 8, 8, 8 },
2783 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 2784 .vfront_porch = { 6, 21, 33 },
2785 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 2786 .vsync_len = { 8, 8, 8 },
2787 .flags = DISPLAY_FLAGS_DE_HIGH,
2788};
2789
2790static const struct panel_desc koe_tx31d200vm0baa = {
2791 .timings = &koe_tx31d200vm0baa_timing,
2792 .num_timings = 1,
2793 .bpc = 6,
2794 .size = {
2795 .width = 292,
2796 .height = 109,
2797 },
2798 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2799 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 2800};
2801
8def22e5
LS		 2802static const struct display_timing kyo_tcg121xglp_timing = {
2803 .pixelclock = { 52000000, 65000000, 71000000 },
2804 .hactive = { 1024, 1024, 1024 },
2805 .hfront_porch = { 2, 2, 2 },
2806 .hback_porch = { 2, 2, 2 },
2807 .hsync_len = { 86, 124, 244 },
2808 .vactive = { 768, 768, 768 },
2809 .vfront_porch = { 2, 2, 2 },
2810 .vback_porch = { 2, 2, 2 },
2811 .vsync_len = { 6, 34, 73 },
2812 .flags = DISPLAY_FLAGS_DE_HIGH,
2813};
2814
2815static const struct panel_desc kyo_tcg121xglp = {
2816 .timings = &kyo_tcg121xglp_timing,
2817 .num_timings = 1,
2818 .bpc = 8,
2819 .size = {
2820 .width = 246,
2821 .height = 184,
2822 },
2823 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2824 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 2825};
2826
27abdd83
PK		 2827static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2828 .clock = 7000,
2829 .hdisplay = 320,
2830 .hsync_start = 320 + 20,
2831 .hsync_end = 320 + 20 + 30,
2832 .htotal = 320 + 20 + 30 + 38,
2833 .vdisplay = 240,
2834 .vsync_start = 240 + 4,
2835 .vsync_end = 240 + 4 + 3,
2836 .vtotal = 240 + 4 + 3 + 15,
27abdd83
PK		 2837};
2838
2839static const struct panel_desc lemaker_bl035_rgb_002 = {
2840 .modes = &lemaker_bl035_rgb_002_mode,
2841 .num_modes = 1,
2842 .size = {
2843 .width = 70,
2844 .height = 52,
2845 },
2846 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2847 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2848};
2849
c3ba13a0
AS		 2850static const struct display_timing lg_lb070wv8_timing = {
2851 .pixelclock = { 31950000, 33260000, 34600000 },
2852 .hactive = { 800, 800, 800 },
2853 .hfront_porch = { 88, 88, 88 },
2854 .hback_porch = { 88, 88, 88 },
2855 .hsync_len = { 80, 80, 80 },
2856 .vactive = { 480, 480, 480 },
2857 .vfront_porch = { 10, 10, 10 },
2858 .vback_porch = { 10, 10, 10 },
2859 .vsync_len = { 25, 25, 25 },
dd015002
HS		 2860};
2861
2862static const struct panel_desc lg_lb070wv8 = {
c3ba13a0
AS		 2863 .timings = &lg_lb070wv8_timing,
2864 .num_timings = 1,
a6ae2fe5 2865 .bpc = 8,
dd015002
HS		 2866 .size = {
2867 .width = 151,
2868 .height = 91,
2869 },
2870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2871 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 2872};
2873
5728fe7f
MZ		 2874static const struct display_timing logictechno_lt161010_2nh_timing = {
2875 .pixelclock = { 26400000, 33300000, 46800000 },
2876 .hactive = { 800, 800, 800 },
2877 .hfront_porch = { 16, 210, 354 },
2878 .hback_porch = { 46, 46, 46 },
2879 .hsync_len = { 1, 20, 40 },
2880 .vactive = { 480, 480, 480 },
2881 .vfront_porch = { 7, 22, 147 },
2882 .vback_porch = { 23, 23, 23 },
2883 .vsync_len = { 1, 10, 20 },
2884 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2885 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2886 DISPLAY_FLAGS_SYNC_POSEDGE,
2887};
2888
2889static const struct panel_desc logictechno_lt161010_2nh = {
2890 .timings = &logictechno_lt161010_2nh_timing,
2891 .num_timings = 1,
876153ab 2892 .bpc = 6,
5728fe7f
MZ		 2893 .size = {
2894 .width = 154,
2895 .height = 86,
2896 },
2897 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2898 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2899 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2900 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2901 .connector_type = DRM_MODE_CONNECTOR_DPI,
2902};
2903
2904static const struct display_timing logictechno_lt170410_2whc_timing = {
2905 .pixelclock = { 68900000, 71100000, 73400000 },
2906 .hactive = { 1280, 1280, 1280 },
2907 .hfront_porch = { 23, 60, 71 },
2908 .hback_porch = { 23, 60, 71 },
2909 .hsync_len = { 15, 40, 47 },
2910 .vactive = { 800, 800, 800 },
2911 .vfront_porch = { 5, 7, 10 },
2912 .vback_porch = { 5, 7, 10 },
2913 .vsync_len = { 6, 9, 12 },
2914 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2915 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2916 DISPLAY_FLAGS_SYNC_POSEDGE,
2917};
2918
2919static const struct panel_desc logictechno_lt170410_2whc = {
2920 .timings = &logictechno_lt170410_2whc_timing,
2921 .num_timings = 1,
876153ab 2922 .bpc = 8,
5728fe7f
MZ		 2923 .size = {
2924 .width = 217,
2925 .height = 136,
2926 },
2927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2928 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
5728fe7f
MZ		 2929 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2930};
2931
19f036ea
SA		 2932static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2933 .clock = 33000,
2934 .hdisplay = 800,
2935 .hsync_start = 800 + 112,
2936 .hsync_end = 800 + 112 + 3,
2937 .htotal = 800 + 112 + 3 + 85,
2938 .vdisplay = 480,
2939 .vsync_start = 480 + 38,
2940 .vsync_end = 480 + 38 + 3,
2941 .vtotal = 480 + 38 + 3 + 29,
2942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2943};
2944
2945static const struct panel_desc logictechno_lttd800480070_l2rt = {
2946 .modes = &logictechno_lttd800480070_l2rt_mode,
2947 .num_modes = 1,
2948 .bpc = 8,
2949 .size = {
2950 .width = 154,
2951 .height = 86,
2952 },
2953 .delay = {
2954 .prepare = 45,
2955 .enable = 100,
2956 .disable = 100,
2957 .unprepare = 45
2958 },
2959 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2960 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2961 .connector_type = DRM_MODE_CONNECTOR_DPI,
2962};
2963
0c044f7d
SA		 2964static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2965 .clock = 33000,
2966 .hdisplay = 800,
2967 .hsync_start = 800 + 154,
2968 .hsync_end = 800 + 154 + 3,
2969 .htotal = 800 + 154 + 3 + 43,
2970 .vdisplay = 480,
2971 .vsync_start = 480 + 47,
2972 .vsync_end = 480 + 47 + 3,
2973 .vtotal = 480 + 47 + 3 + 20,
2974 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2975};
2976
2977static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2978 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2979 .num_modes = 1,
2980 .bpc = 8,
2981 .size = {
2982 .width = 154,
2983 .height = 86,
2984 },
2985 .delay = {
2986 .prepare = 45,
2987 .enable = 100,
2988 .disable = 100,
2989 .unprepare = 45
2990 },
2991 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2992 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2993 .connector_type = DRM_MODE_CONNECTOR_DPI,
2994};
2995
0d35408a 2996static const struct drm_display_mode logicpd_type_28_mode = {
f873c5d8 2997 .clock = 9107,
0d35408a
AF		 2998 .hdisplay = 480,
2999 .hsync_start = 480 + 3,
3000 .hsync_end = 480 + 3 + 42,
3001 .htotal = 480 + 3 + 42 + 2,
3002
3003 .vdisplay = 272,
3004 .vsync_start = 272 + 2,
3005 .vsync_end = 272 + 2 + 11,
3006 .vtotal = 272 + 2 + 11 + 3,
0d35408a
AF		 3007 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3008};
3009
3010static const struct panel_desc logicpd_type_28 = {
3011 .modes = &logicpd_type_28_mode,
3012 .num_modes = 1,
3013 .bpc = 8,
3014 .size = {
3015 .width = 105,
3016 .height = 67,
3017 },
3018 .delay = {
3019 .prepare = 200,
3020 .enable = 200,
3021 .unprepare = 200,
3022 .disable = 200,
3023 },
3024 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3025 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3026 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
efb94790 3027 .connector_type = DRM_MODE_CONNECTOR_DPI,
0d35408a
AF		 3028};
3029
c8527b9a
DA		 3030static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3031 .clock = 30400,
3032 .hdisplay = 800,
3033 .hsync_start = 800 + 0,
3034 .hsync_end = 800 + 1,
3035 .htotal = 800 + 0 + 1 + 160,
3036 .vdisplay = 480,
3037 .vsync_start = 480 + 0,
3038 .vsync_end = 480 + 48 + 1,
3039 .vtotal = 480 + 48 + 1 + 0,
3040 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3041};
3042
65c766ca
LM		 3043static const struct panel_desc mitsubishi_aa070mc01 = {
3044 .modes = &mitsubishi_aa070mc01_mode,
3045 .num_modes = 1,
3046 .bpc = 8,
3047 .size = {
3048 .width = 152,
3049 .height = 91,
3050 },
3051
3052 .delay = {
3053 .enable = 200,
3054 .unprepare = 200,
3055 .disable = 400,
3056 },
3057 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3058 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 3059 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3060};
3061
637d3fdc
TW		 3062static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
3063 .clock = 56234,
3064 .hdisplay = 1024,
3065 .hsync_start = 1024 + 24,
3066 .hsync_end = 1024 + 24 + 63,
3067 .htotal = 1024 + 24 + 63 + 1,
3068 .vdisplay = 768,
3069 .vsync_start = 768 + 3,
3070 .vsync_end = 768 + 3 + 6,
3071 .vtotal = 768 + 3 + 6 + 1,
3072 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3073};
3074
3075static const struct panel_desc mitsubishi_aa084xe01 = {
3076 .modes = &mitsubishi_aa084xe01_mode,
3077 .num_modes = 1,
3078 .bpc = 8,
3079 .size = {
3080 .width = 1024,
3081 .height = 768,
3082 },
3083 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3084 .connector_type = DRM_MODE_CONNECTOR_DPI,
3085 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3086};
3087
a5d092d3
MV		 3088static const struct display_timing multi_inno_mi0700s4t_6_timing = {
3089 .pixelclock = { 29000000, 33000000, 38000000 },
3090 .hactive = { 800, 800, 800 },
3091 .hfront_porch = { 180, 210, 240 },
3092 .hback_porch = { 16, 16, 16 },
3093 .hsync_len = { 30, 30, 30 },
3094 .vactive = { 480, 480, 480 },
3095 .vfront_porch = { 12, 22, 32 },
3096 .vback_porch = { 10, 10, 10 },
3097 .vsync_len = { 13, 13, 13 },
3098 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3099 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3100 DISPLAY_FLAGS_SYNC_POSEDGE,
3101};
3102
3103static const struct panel_desc multi_inno_mi0700s4t_6 = {
3104 .timings = &multi_inno_mi0700s4t_6_timing,
3105 .num_timings = 1,
3106 .bpc = 8,
3107 .size = {
3108 .width = 154,
3109 .height = 86,
3110 },
3111 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3112 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3113 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3114 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3115 .connector_type = DRM_MODE_CONNECTOR_DPI,
3116};
3117
b55002b9
CN		 3118static const struct display_timing multi_inno_mi0800ft_9_timing = {
3119 .pixelclock = { 32000000, 40000000, 50000000 },
3120 .hactive = { 800, 800, 800 },
3121 .hfront_porch = { 16, 210, 354 },
3122 .hback_porch = { 6, 26, 45 },
3123 .hsync_len = { 1, 20, 40 },
3124 .vactive = { 600, 600, 600 },
3125 .vfront_porch = { 1, 12, 77 },
3126 .vback_porch = { 3, 13, 22 },
3127 .vsync_len = { 1, 10, 20 },
3128 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3129 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3130 DISPLAY_FLAGS_SYNC_POSEDGE,
3131};
3132
3133static const struct panel_desc multi_inno_mi0800ft_9 = {
3134 .timings = &multi_inno_mi0800ft_9_timing,
3135 .num_timings = 1,
3136 .bpc = 8,
3137 .size = {
3138 .width = 162,
3139 .height = 122,
3140 },
3141 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3142 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3143 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3144 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3145 .connector_type = DRM_MODE_CONNECTOR_DPI,
3146};
3147
81162f4b
SR		 3148static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3149 .pixelclock = { 68900000, 70000000, 73400000 },
3150 .hactive = { 1280, 1280, 1280 },
3151 .hfront_porch = { 30, 60, 71 },
3152 .hback_porch = { 30, 60, 71 },
3153 .hsync_len = { 10, 10, 48 },
3154 .vactive = { 800, 800, 800 },
3155 .vfront_porch = { 5, 10, 10 },
3156 .vback_porch = { 5, 10, 10 },
3157 .vsync_len = { 5, 6, 13 },
3158 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3159 DISPLAY_FLAGS_DE_HIGH,
3160};
3161
3162static const struct panel_desc multi_inno_mi1010ait_1cp = {
3163 .timings = &multi_inno_mi1010ait_1cp_timing,
3164 .num_timings = 1,
3165 .bpc = 8,
3166 .size = {
3167 .width = 217,
3168 .height = 136,
3169 },
3170 .delay = {
3171 .enable = 50,
3172 .disable = 50,
3173 },
3174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3175 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3176 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3177};
3178
01bacc13
LS		 3179static const struct display_timing nec_nl12880bc20_05_timing = {
3180 .pixelclock = { 67000000, 71000000, 75000000 },
3181 .hactive = { 1280, 1280, 1280 },
3182 .hfront_porch = { 2, 30, 30 },
3183 .hback_porch = { 6, 100, 100 },
3184 .hsync_len = { 2, 30, 30 },
3185 .vactive = { 800, 800, 800 },
3186 .vfront_porch = { 5, 5, 5 },
3187 .vback_porch = { 11, 11, 11 },
3188 .vsync_len = { 7, 7, 7 },
3189};
3190
3191static const struct panel_desc nec_nl12880bc20_05 = {
3192 .timings = &nec_nl12880bc20_05_timing,
3193 .num_timings = 1,
3194 .bpc = 8,
3195 .size = {
3196 .width = 261,
3197 .height = 163,
3198 },
3199 .delay = {
3200 .enable = 50,
3201 .disable = 50,
3202 },
3203 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3204 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 3205};
3206
c6e87f91 3207static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3208 .clock = 10870,
3209 .hdisplay = 480,
3210 .hsync_start = 480 + 2,
3211 .hsync_end = 480 + 2 + 41,
3212 .htotal = 480 + 2 + 41 + 2,
3213 .vdisplay = 272,
3214 .vsync_start = 272 + 2,
3215 .vsync_end = 272 + 2 + 4,
3216 .vtotal = 272 + 2 + 4 + 2,
4bc390c6 3217 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 3218};
3219
3220static const struct panel_desc nec_nl4827hc19_05b = {
3221 .modes = &nec_nl4827hc19_05b_mode,
3222 .num_modes = 1,
3223 .bpc = 8,
3224 .size = {
3225 .width = 95,
3226 .height = 54,
3227 },
2c80661d 3228 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 3229 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 3230};
3231
e6c2f066
MR		 3232static const struct drm_display_mode netron_dy_e231732_mode = {
3233 .clock = 66000,
3234 .hdisplay = 1024,
3235 .hsync_start = 1024 + 160,
3236 .hsync_end = 1024 + 160 + 70,
3237 .htotal = 1024 + 160 + 70 + 90,
3238 .vdisplay = 600,
3239 .vsync_start = 600 + 127,
3240 .vsync_end = 600 + 127 + 20,
3241 .vtotal = 600 + 127 + 20 + 3,
e6c2f066
MR		 3242};
3243
3244static const struct panel_desc netron_dy_e231732 = {
3245 .modes = &netron_dy_e231732_mode,
3246 .num_modes = 1,
3247 .size = {
3248 .width = 154,
3249 .height = 87,
3250 },
3251 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3252};
3253
3b39ad7a
TV		 3254static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3255 .clock = 9000,
3256 .hdisplay = 480,
3257 .hsync_start = 480 + 2,
3258 .hsync_end = 480 + 2 + 41,
3259 .htotal = 480 + 2 + 41 + 2,
3260 .vdisplay = 272,
3261 .vsync_start = 272 + 2,
3262 .vsync_end = 272 + 2 + 10,
3263 .vtotal = 272 + 2 + 10 + 2,
3b39ad7a
TV		 3264 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3265};
3266
3267static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3268 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3269 .num_modes = 1,
3270 .bpc = 8,
3271 .size = {
3272 .width = 95,
3273 .height = 54,
3274 },
3275 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 3276 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3277 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
8a4f5e11 3278 .connector_type = DRM_MODE_CONNECTOR_DPI,
3b39ad7a
TV		 3279};
3280
4177fa66
LS		 3281static const struct display_timing nlt_nl192108ac18_02d_timing = {
3282 .pixelclock = { 130000000, 148350000, 163000000 },
3283 .hactive = { 1920, 1920, 1920 },
3284 .hfront_porch = { 80, 100, 100 },
3285 .hback_porch = { 100, 120, 120 },
3286 .hsync_len = { 50, 60, 60 },
3287 .vactive = { 1080, 1080, 1080 },
3288 .vfront_porch = { 12, 30, 30 },
3289 .vback_porch = { 4, 10, 10 },
3290 .vsync_len = { 4, 5, 5 },
3291};
3292
3293static const struct panel_desc nlt_nl192108ac18_02d = {
3294 .timings = &nlt_nl192108ac18_02d_timing,
3295 .num_timings = 1,
3296 .bpc = 8,
3297 .size = {
3298 .width = 344,
3299 .height = 194,
3300 },
3301 .delay = {
3302 .unprepare = 500,
3303 },
3304 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3305 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 3306};
3307
05ec0e45
FL		 3308static const struct drm_display_mode nvd_9128_mode = {
3309 .clock = 29500,
3310 .hdisplay = 800,
3311 .hsync_start = 800 + 130,
3312 .hsync_end = 800 + 130 + 98,
3313 .htotal = 800 + 0 + 130 + 98,
3314 .vdisplay = 480,
3315 .vsync_start = 480 + 10,
3316 .vsync_end = 480 + 10 + 50,
3317 .vtotal = 480 + 0 + 10 + 50,
3318};
3319
3320static const struct panel_desc nvd_9128 = {
3321 .modes = &nvd_9128_mode,
3322 .num_modes = 1,
3323 .bpc = 8,
3324 .size = {
3325 .width = 156,
3326 .height = 88,
3327 },
3328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3329 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 3330};
3331
a99fb626
GB		 3332static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3333 .pixelclock = { 30000000, 30000000, 40000000 },
3334 .hactive = { 800, 800, 800 },
3335 .hfront_porch = { 40, 40, 40 },
3336 .hback_porch = { 40, 40, 40 },
3337 .hsync_len = { 1, 48, 48 },
3338 .vactive = { 480, 480, 480 },
3339 .vfront_porch = { 13, 13, 13 },
3340 .vback_porch = { 29, 29, 29 },
3341 .vsync_len = { 3, 3, 3 },
3342 .flags = DISPLAY_FLAGS_DE_HIGH,
3343};
3344
3345static const struct panel_desc okaya_rs800480t_7x0gp = {
3346 .timings = &okaya_rs800480t_7x0gp_timing,
3347 .num_timings = 1,
3348 .bpc = 6,
3349 .size = {
3350 .width = 154,
3351 .height = 87,
3352 },
3353 .delay = {
3354 .prepare = 41,
3355 .enable = 50,
3356 .unprepare = 41,
3357 .disable = 50,
3358 },
3359 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3360};
3361
cf5c9e6d
MR		 3362static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3363 .clock = 9000,
3364 .hdisplay = 480,
3365 .hsync_start = 480 + 5,
3366 .hsync_end = 480 + 5 + 30,
3367 .htotal = 480 + 5 + 30 + 10,
3368 .vdisplay = 272,
3369 .vsync_start = 272 + 8,
3370 .vsync_end = 272 + 8 + 5,
3371 .vtotal = 272 + 8 + 5 + 3,
cf5c9e6d
MR		 3372};
3373
3374static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3375 .modes = &olimex_lcd_olinuxino_43ts_mode,
3376 .num_modes = 1,
3377 .size = {
30c6d7ab
JL		 3378 .width = 95,
3379 .height = 54,
cf5c9e6d 3380 },
5c2a7c6b 3381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 3382};
3383
e8b6f561
EA		 3384/*
3385 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3386 * pixel clocks, but this is the timing that was being used in the Adafruit
3387 * installation instructions.
3388 */
3389static const struct drm_display_mode ontat_yx700wv03_mode = {
3390 .clock = 29500,
3391 .hdisplay = 800,
3392 .hsync_start = 824,
3393 .hsync_end = 896,
3394 .htotal = 992,
3395 .vdisplay = 480,
3396 .vsync_start = 483,
3397 .vsync_end = 493,
3398 .vtotal = 500,
e8b6f561
EA		 3399 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3400};
3401
3402/*
3403 * Specification at:
3404 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3405 */
3406static const struct panel_desc ontat_yx700wv03 = {
3407 .modes = &ontat_yx700wv03_mode,
3408 .num_modes = 1,
3409 .bpc = 8,
3410 .size = {
3411 .width = 154,
3412 .height = 83,
3413 },
5651e5e0 3414 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 3415};
3416
9c31dcb6 3417static const struct drm_display_mode ortustech_com37h3m_mode = {
855e764d 3418 .clock = 22230,
9c31dcb6 3419 .hdisplay = 480,
855e764d
NS		 3420 .hsync_start = 480 + 40,
3421 .hsync_end = 480 + 40 + 10,
3422 .htotal = 480 + 40 + 10 + 40,
9c31dcb6
NS		 3423 .vdisplay = 640,
3424 .vsync_start = 640 + 4,
855e764d
NS		 3425 .vsync_end = 640 + 4 + 2,
3426 .vtotal = 640 + 4 + 2 + 4,
9c31dcb6
NS		 3427 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3428};
3429
3430static const struct panel_desc ortustech_com37h3m = {
3431 .modes = &ortustech_com37h3m_mode,
3432 .num_modes = 1,
3433 .bpc = 8,
3434 .size = {
3435 .width = 56, /* 56.16mm */
3436 .height = 75, /* 74.88mm */
3437 },
3438 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3439 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
9c31dcb6
NS		 3440 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3441};
3442
725c9d40
PZ		 3443static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3444 .clock = 25000,
3445 .hdisplay = 480,
3446 .hsync_start = 480 + 10,
3447 .hsync_end = 480 + 10 + 10,
3448 .htotal = 480 + 10 + 10 + 15,
3449 .vdisplay = 800,
3450 .vsync_start = 800 + 3,
3451 .vsync_end = 800 + 3 + 3,
3452 .vtotal = 800 + 3 + 3 + 3,
725c9d40
PZ		 3453};
3454
3455static const struct panel_desc ortustech_com43h4m85ulc = {
3456 .modes = &ortustech_com43h4m85ulc_mode,
3457 .num_modes = 1,
3b809516 3458 .bpc = 6,
725c9d40
PZ		 3459 .size = {
3460 .width = 56,
3461 .height = 93,
3462 },
f098f168 3463 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 3464 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2ccedf46 3465 .connector_type = DRM_MODE_CONNECTOR_DPI,
725c9d40
PZ		 3466};
3467
163f7a35
LP		 3468static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3469 .clock = 33000,
3470 .hdisplay = 800,
3471 .hsync_start = 800 + 210,
3472 .hsync_end = 800 + 210 + 30,
3473 .htotal = 800 + 210 + 30 + 16,
3474 .vdisplay = 480,
3475 .vsync_start = 480 + 22,
3476 .vsync_end = 480 + 22 + 13,
3477 .vtotal = 480 + 22 + 13 + 10,
163f7a35
LP		 3478 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3479};
3480
3481static const struct panel_desc osddisplays_osd070t1718_19ts = {
3482 .modes = &osddisplays_osd070t1718_19ts_mode,
3483 .num_modes = 1,
3484 .bpc = 8,
3485 .size = {
3486 .width = 152,
3487 .height = 91,
3488 },
3489 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
fb0629ee
TV		 3490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3491 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
a793f0ee 3492 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 3493};
3494
4ba3e563
EH		 3495static const struct drm_display_mode pda_91_00156_a0_mode = {
3496 .clock = 33300,
3497 .hdisplay = 800,
3498 .hsync_start = 800 + 1,
3499 .hsync_end = 800 + 1 + 64,
3500 .htotal = 800 + 1 + 64 + 64,
3501 .vdisplay = 480,
3502 .vsync_start = 480 + 1,
3503 .vsync_end = 480 + 1 + 23,
3504 .vtotal = 480 + 1 + 23 + 22,
4ba3e563
EH		 3505};
3506
3507static const struct panel_desc pda_91_00156_a0 = {
3508 .modes = &pda_91_00156_a0_mode,
3509 .num_modes = 1,
3510 .size = {
3511 .width = 152,
3512 .height = 91,
3513 },
3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3515};
3516
fd6aa8f2
NM		 3517static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = {
3518 .clock = 66500,
3519 .hdisplay = 1280,
3520 .hsync_start = 1280 + 12,
3521 .hsync_end = 1280 + 12 + 20,
3522 .htotal = 1280 + 12 + 20 + 56,
3523 .vdisplay = 800,
3524 .vsync_start = 800 + 1,
3525 .vsync_end = 800 + 1 + 3,
3526 .vtotal = 800 + 1 + 3 + 20,
3527 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3528};
3529
3530static const struct panel_desc powertip_ph128800t006_zhc01 = {
3531 .modes = &powertip_ph128800t006_zhc01_mode,
3532 .num_modes = 1,
3533 .bpc = 8,
3534 .size = {
3535 .width = 216,
3536 .height = 135,
3537 },
3538 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3539 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3540 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3541};
3542
d69de69f
MV		 3543static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3544 .clock = 24750,
3545 .hdisplay = 800,
3546 .hsync_start = 800 + 54,
3547 .hsync_end = 800 + 54 + 2,
3548 .htotal = 800 + 54 + 2 + 44,
3549 .vdisplay = 480,
3550 .vsync_start = 480 + 49,
3551 .vsync_end = 480 + 49 + 2,
3552 .vtotal = 480 + 49 + 2 + 22,
1c519980 3553 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
d69de69f
MV		 3554};
3555
3556static const struct panel_desc powertip_ph800480t013_idf02 = {
3557 .modes = &powertip_ph800480t013_idf02_mode,
3558 .num_modes = 1,
65f4937f 3559 .bpc = 8,
d69de69f
MV		 3560 .size = {
3561 .width = 152,
3562 .height = 91,
3563 },
3564 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3565 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3566 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3567 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3568 .connector_type = DRM_MODE_CONNECTOR_DPI,
3569};
4ba3e563 3570
d2a6f0f5
JW		 3571static const struct drm_display_mode qd43003c0_40_mode = {
3572 .clock = 9000,
3573 .hdisplay = 480,
3574 .hsync_start = 480 + 8,
3575 .hsync_end = 480 + 8 + 4,
3576 .htotal = 480 + 8 + 4 + 39,
3577 .vdisplay = 272,
3578 .vsync_start = 272 + 4,
3579 .vsync_end = 272 + 4 + 10,
3580 .vtotal = 272 + 4 + 10 + 2,
d2a6f0f5
JW		 3581};
3582
3583static const struct panel_desc qd43003c0_40 = {
3584 .modes = &qd43003c0_40_mode,
3585 .num_modes = 1,
3586 .bpc = 8,
3587 .size = {
3588 .width = 95,
3589 .height = 53,
3590 },
3591 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3592};
3593
49179e66
AV		 3594static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3595 { /* 60 Hz */
3596 .clock = 10800,
3597 .hdisplay = 480,
3598 .hsync_start = 480 + 77,
3599 .hsync_end = 480 + 77 + 41,
3600 .htotal = 480 + 77 + 41 + 2,
3601 .vdisplay = 272,
3602 .vsync_start = 272 + 16,
3603 .vsync_end = 272 + 16 + 10,
3604 .vtotal = 272 + 16 + 10 + 2,
3605 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3606 },
3607 { /* 50 Hz */
3608 .clock = 10800,
3609 .hdisplay = 480,
3610 .hsync_start = 480 + 17,
3611 .hsync_end = 480 + 17 + 41,
3612 .htotal = 480 + 17 + 41 + 2,
3613 .vdisplay = 272,
3614 .vsync_start = 272 + 116,
3615 .vsync_end = 272 + 116 + 10,
3616 .vtotal = 272 + 116 + 10 + 2,
3617 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3618 },
3619};
3620
3621static const struct panel_desc qishenglong_gopher2b_lcd = {
3622 .modes = qishenglong_gopher2b_lcd_modes,
3623 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3624 .bpc = 8,
3625 .size = {
3626 .width = 95,
3627 .height = 54,
3628 },
3629 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3630 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3631 .connector_type = DRM_MODE_CONNECTOR_DPI,
3632};
3633
13cdd12a
DB		 3634static const struct display_timing rocktech_rk043fn48h_timing = {
3635 .pixelclock = { 6000000, 9000000, 12000000 },
3636 .hactive = { 480, 480, 480 },
3637 .hback_porch = { 8, 43, 43 },
c9424076 3638 .hfront_porch = { 2, 8, 10 },
13cdd12a
DB		 3639 .hsync_len = { 1, 1, 1 },
3640 .vactive = { 272, 272, 272 },
c9424076 3641 .vback_porch = { 2, 12, 26 },
13cdd12a
DB		 3642 .vfront_porch = { 1, 4, 4 },
3643 .vsync_len = { 1, 10, 10 },
3644 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
536090b6
RGP		 3645 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3646 DISPLAY_FLAGS_SYNC_POSEDGE,
13cdd12a
DB		 3647};
3648
3649static const struct panel_desc rocktech_rk043fn48h = {
3650 .timings = &rocktech_rk043fn48h_timing,
3651 .num_timings = 1,
3652 .bpc = 8,
3653 .size = {
3654 .width = 95,
3655 .height = 54,
3656 },
3657 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3658 .connector_type = DRM_MODE_CONNECTOR_DPI,
3659};
3660
23167fa9
JT		 3661static const struct display_timing rocktech_rk070er9427_timing = {
3662 .pixelclock = { 26400000, 33300000, 46800000 },
3663 .hactive = { 800, 800, 800 },
3664 .hfront_porch = { 16, 210, 354 },
3665 .hback_porch = { 46, 46, 46 },
3666 .hsync_len = { 1, 1, 1 },
3667 .vactive = { 480, 480, 480 },
3668 .vfront_porch = { 7, 22, 147 },
3669 .vback_porch = { 23, 23, 23 },
3670 .vsync_len = { 1, 1, 1 },
3671 .flags = DISPLAY_FLAGS_DE_HIGH,
3672};
3673
3674static const struct panel_desc rocktech_rk070er9427 = {
3675 .timings = &rocktech_rk070er9427_timing,
3676 .num_timings = 1,
3677 .bpc = 6,
3678 .size = {
3679 .width = 154,
3680 .height = 86,
3681 },
3682 .delay = {
3683 .prepare = 41,
3684 .enable = 50,
3685 .unprepare = 41,
3686 .disable = 50,
3687 },
3688 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3689};
3690
f305047b
JS		 3691static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3692 .clock = 71100,
3693 .hdisplay = 1280,
3694 .hsync_start = 1280 + 48,
3695 .hsync_end = 1280 + 48 + 32,
3696 .htotal = 1280 + 48 + 32 + 80,
3697 .vdisplay = 800,
3698 .vsync_start = 800 + 2,
3699 .vsync_end = 800 + 2 + 5,
3700 .vtotal = 800 + 2 + 5 + 16,
f305047b
JS		 3701};
3702
3703static const struct panel_desc rocktech_rk101ii01d_ct = {
3704 .modes = &rocktech_rk101ii01d_ct_mode,
f85b3f80 3705 .bpc = 8,
f305047b
JS		 3706 .num_modes = 1,
3707 .size = {
3708 .width = 217,
3709 .height = 136,
3710 },
3711 .delay = {
3712 .prepare = 50,
3713 .disable = 50,
3714 },
3715 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3716 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3717 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3718};
3719
a6aa679a
MJ		 3720static const struct display_timing samsung_ltl101al01_timing = {
3721 .pixelclock = { 66663000, 66663000, 66663000 },
3722 .hactive = { 1280, 1280, 1280 },
3723 .hfront_porch = { 18, 18, 18 },
3724 .hback_porch = { 36, 36, 36 },
3725 .hsync_len = { 16, 16, 16 },
3726 .vactive = { 800, 800, 800 },
3727 .vfront_porch = { 4, 4, 4 },
3728 .vback_porch = { 16, 16, 16 },
3729 .vsync_len = { 3, 3, 3 },
3730 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3731};
3732
3733static const struct panel_desc samsung_ltl101al01 = {
3734 .timings = &samsung_ltl101al01_timing,
3735 .num_timings = 1,
3736 .bpc = 8,
3737 .size = {
3738 .width = 217,
3739 .height = 135,
3740 },
3741 .delay = {
3742 .prepare = 40,
3743 .enable = 300,
3744 .disable = 200,
3745 .unprepare = 600,
3746 },
3747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3748 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3749};
3750
6d54e3d2
MD		 3751static const struct drm_display_mode samsung_ltn101nt05_mode = {
3752 .clock = 54030,
3753 .hdisplay = 1024,
3754 .hsync_start = 1024 + 24,
3755 .hsync_end = 1024 + 24 + 136,
3756 .htotal = 1024 + 24 + 136 + 160,
3757 .vdisplay = 600,
3758 .vsync_start = 600 + 3,
3759 .vsync_end = 600 + 3 + 6,
3760 .vtotal = 600 + 3 + 6 + 61,
6d54e3d2
MD		 3761};
3762
3763static const struct panel_desc samsung_ltn101nt05 = {
3764 .modes = &samsung_ltn101nt05_mode,
3765 .num_modes = 1,
0208d511 3766 .bpc = 6,
6d54e3d2 3767 .size = {
81598846
TR		 3768 .width = 223,
3769 .height = 125,
6d54e3d2 3770 },
85560829 3771 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 3772 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 3773 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6d54e3d2
MD		 3774};
3775
44c58c52
MR		 3776static const struct display_timing satoz_sat050at40h12r2_timing = {
3777 .pixelclock = {33300000, 33300000, 50000000},
3778 .hactive = {800, 800, 800},
3779 .hfront_porch = {16, 210, 354},
3780 .hback_porch = {46, 46, 46},
3781 .hsync_len = {1, 1, 40},
3782 .vactive = {480, 480, 480},
3783 .vfront_porch = {7, 22, 147},
3784 .vback_porch = {23, 23, 23},
3785 .vsync_len = {1, 1, 20},
3786};
3787
3788static const struct panel_desc satoz_sat050at40h12r2 = {
3789 .timings = &satoz_sat050at40h12r2_timing,
3790 .num_timings = 1,
3791 .bpc = 8,
3792 .size = {
3793 .width = 108,
3794 .height = 65,
3795 },
34ca6b53 3796 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
44c58c52
MR		 3797 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3798};
3799
dda0e4bd
NS		 3800static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3801 .clock = 33260,
3802 .hdisplay = 800,
3803 .hsync_start = 800 + 64,
3804 .hsync_end = 800 + 64 + 128,
3805 .htotal = 800 + 64 + 128 + 64,
3806 .vdisplay = 480,
3807 .vsync_start = 480 + 8,
3808 .vsync_end = 480 + 8 + 2,
3809 .vtotal = 480 + 8 + 2 + 35,
dda0e4bd
NS		 3810 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3811};
3812
3813static const struct panel_desc sharp_lq070y3dg3b = {
3814 .modes = &sharp_lq070y3dg3b_mode,
3815 .num_modes = 1,
3816 .bpc = 8,
3817 .size = {
3818 .width = 152, /* 152.4mm */
3819 .height = 91, /* 91.4mm */
3820 },
3821 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3822 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
dda0e4bd
NS		 3823 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3824};
3825
03e3ec9a
VZ		 3826static const struct drm_display_mode sharp_lq035q7db03_mode = {
3827 .clock = 5500,
3828 .hdisplay = 240,
3829 .hsync_start = 240 + 16,
3830 .hsync_end = 240 + 16 + 7,
3831 .htotal = 240 + 16 + 7 + 5,
3832 .vdisplay = 320,
3833 .vsync_start = 320 + 9,
3834 .vsync_end = 320 + 9 + 1,
3835 .vtotal = 320 + 9 + 1 + 7,
03e3ec9a
VZ		 3836};
3837
3838static const struct panel_desc sharp_lq035q7db03 = {
3839 .modes = &sharp_lq035q7db03_mode,
3840 .num_modes = 1,
3841 .bpc = 6,
3842 .size = {
3843 .width = 54,
3844 .height = 72,
3845 },
3846 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3847};
3848
592aa02b
JC		 3849static const struct display_timing sharp_lq101k1ly04_timing = {
3850 .pixelclock = { 60000000, 65000000, 80000000 },
3851 .hactive = { 1280, 1280, 1280 },
3852 .hfront_porch = { 20, 20, 20 },
3853 .hback_porch = { 20, 20, 20 },
3854 .hsync_len = { 10, 10, 10 },
3855 .vactive = { 800, 800, 800 },
3856 .vfront_porch = { 4, 4, 4 },
3857 .vback_porch = { 4, 4, 4 },
3858 .vsync_len = { 4, 4, 4 },
3859 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3860};
3861
3862static const struct panel_desc sharp_lq101k1ly04 = {
3863 .timings = &sharp_lq101k1ly04_timing,
3864 .num_timings = 1,
3865 .bpc = 8,
3866 .size = {
3867 .width = 217,
3868 .height = 136,
3869 },
3870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 3871 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 3872};
3873
656b7596 3874static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
e6c21e6f
PC		 3875 { /* 50 Hz */
3876 .clock = 3000,
3877 .hdisplay = 240,
3878 .hsync_start = 240 + 58,
3879 .hsync_end = 240 + 58 + 1,
3880 .htotal = 240 + 58 + 1 + 1,
3881 .vdisplay = 160,
3882 .vsync_start = 160 + 24,
3883 .vsync_end = 160 + 24 + 10,
3884 .vtotal = 160 + 24 + 10 + 6,
3885 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3886 },
656b7596 3887 { /* 60 Hz */
c1bd32b5 3888 .clock = 3000,
656b7596 3889 .hdisplay = 240,
c1bd32b5
PC		 3890 .hsync_start = 240 + 8,
3891 .hsync_end = 240 + 8 + 1,
3892 .htotal = 240 + 8 + 1 + 1,
656b7596 3893 .vdisplay = 160,
c1bd32b5
PC		 3894 .vsync_start = 160 + 24,
3895 .vsync_end = 160 + 24 + 10,
3896 .vtotal = 160 + 24 + 10 + 6,
656b7596
PC		 3897 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3898 },
f1bd37f3
PC		 3899};
3900
3901static const struct panel_desc sharp_ls020b1dd01d = {
656b7596
PC		 3902 .modes = sharp_ls020b1dd01d_modes,
3903 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
f1bd37f3
PC		 3904 .bpc = 6,
3905 .size = {
3906 .width = 42,
3907 .height = 28,
3908 },
3909 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3910 .bus_flags = DRM_BUS_FLAG_DE_HIGH
f5436f77 3911 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
f1bd37f3
PC		 3912 | DRM_BUS_FLAG_SHARP_SIGNALS,
3913};
3914
9c6615bc
BB		 3915static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3916 .clock = 33300,
3917 .hdisplay = 800,
3918 .hsync_start = 800 + 1,
3919 .hsync_end = 800 + 1 + 64,
3920 .htotal = 800 + 1 + 64 + 64,
3921 .vdisplay = 480,
3922 .vsync_start = 480 + 1,
3923 .vsync_end = 480 + 1 + 23,
3924 .vtotal = 480 + 1 + 23 + 22,
9c6615bc
BB		 3925};
3926
3927static const struct panel_desc shelly_sca07010_bfn_lnn = {
3928 .modes = &shelly_sca07010_bfn_lnn_mode,
3929 .num_modes = 1,
3930 .size = {
3931 .width = 152,
3932 .height = 91,
3933 },
3934 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3935};
3936
105235e4
PR		 3937static const struct drm_display_mode starry_kr070pe2t_mode = {
3938 .clock = 33000,
3939 .hdisplay = 800,
3940 .hsync_start = 800 + 209,
3941 .hsync_end = 800 + 209 + 1,
3942 .htotal = 800 + 209 + 1 + 45,
3943 .vdisplay = 480,
3944 .vsync_start = 480 + 22,
3945 .vsync_end = 480 + 22 + 1,
3946 .vtotal = 480 + 22 + 1 + 22,
105235e4
PR		 3947};
3948
3949static const struct panel_desc starry_kr070pe2t = {
3950 .modes = &starry_kr070pe2t_mode,
3951 .num_modes = 1,
3952 .bpc = 8,
3953 .size = {
3954 .width = 152,
3955 .height = 86,
3956 },
3957 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3958 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
41fad307 3959 .connector_type = DRM_MODE_CONNECTOR_DPI,
105235e4
PR		 3960};
3961
9ff92363
HS		 3962static const struct display_timing startek_kd070wvfpa_mode = {
3963 .pixelclock = { 25200000, 27200000, 30500000 },
3964 .hactive = { 800, 800, 800 },
3965 .hfront_porch = { 19, 44, 115 },
3966 .hback_porch = { 5, 16, 101 },
3967 .hsync_len = { 1, 2, 100 },
3968 .vactive = { 480, 480, 480 },
3969 .vfront_porch = { 5, 43, 67 },
3970 .vback_porch = { 5, 5, 67 },
3971 .vsync_len = { 1, 2, 66 },
3972 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3973 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3974 DISPLAY_FLAGS_SYNC_POSEDGE,
3975};
3976
3977static const struct panel_desc startek_kd070wvfpa = {
3978 .timings = &startek_kd070wvfpa_mode,
3979 .num_timings = 1,
3980 .bpc = 8,
3981 .size = {
3982 .width = 152,
3983 .height = 91,
3984 },
3985 .delay = {
3986 .prepare = 20,
3987 .enable = 200,
3988 .disable = 200,
3989 },
3990 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3991 .connector_type = DRM_MODE_CONNECTOR_DPI,
3992 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3993 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3994 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3995};
3996
938db276
MV		 3997static const struct display_timing tsd_tst043015cmhx_timing = {
3998 .pixelclock = { 5000000, 9000000, 12000000 },
3999 .hactive = { 480, 480, 480 },
4000 .hfront_porch = { 4, 5, 65 },
4001 .hback_porch = { 36, 40, 255 },
4002 .hsync_len = { 1, 1, 1 },
4003 .vactive = { 272, 272, 272 },
4004 .vfront_porch = { 2, 8, 97 },
4005 .vback_porch = { 3, 8, 31 },
4006 .vsync_len = { 1, 1, 1 },
4007
4008 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4009 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
4010};
4011
4012static const struct panel_desc tsd_tst043015cmhx = {
4013 .timings = &tsd_tst043015cmhx_timing,
4014 .num_timings = 1,
4015 .bpc = 8,
4016 .size = {
4017 .width = 105,
4018 .height = 67,
4019 },
4020 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4021 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4022};
4023
42161531
JS		 4024static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4025 .clock = 30000,
4026 .hdisplay = 800,
4027 .hsync_start = 800 + 39,
4028 .hsync_end = 800 + 39 + 47,
4029 .htotal = 800 + 39 + 47 + 39,
4030 .vdisplay = 480,
4031 .vsync_start = 480 + 13,
4032 .vsync_end = 480 + 13 + 2,
4033 .vtotal = 480 + 13 + 2 + 29,
42161531
JS		 4034};
4035
4036static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4037 .modes = &tfc_s9700rtwv43tr_01b_mode,
4038 .num_modes = 1,
4039 .bpc = 8,
4040 .size = {
4041 .width = 155,
4042 .height = 90,
4043 },
4044 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4045 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
42161531
JS		 4046};
4047
adb973ef
GB		 4048static const struct display_timing tianma_tm070jdhg30_timing = {
4049 .pixelclock = { 62600000, 68200000, 78100000 },
4050 .hactive = { 1280, 1280, 1280 },
4051 .hfront_porch = { 15, 64, 159 },
4052 .hback_porch = { 5, 5, 5 },
4053 .hsync_len = { 1, 1, 256 },
4054 .vactive = { 800, 800, 800 },
4055 .vfront_porch = { 3, 40, 99 },
4056 .vback_porch = { 2, 2, 2 },
4057 .vsync_len = { 1, 1, 128 },
4058 .flags = DISPLAY_FLAGS_DE_HIGH,
4059};
4060
4061static const struct panel_desc tianma_tm070jdhg30 = {
4062 .timings = &tianma_tm070jdhg30_timing,
4063 .num_timings = 1,
4064 .bpc = 8,
4065 .size = {
4066 .width = 151,
4067 .height = 95,
4068 },
4069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 4070 .connector_type = DRM_MODE_CONNECTOR_LVDS,
45dd7df2 4071 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
adb973ef
GB		 4072};
4073
b3bfcdf8
MM		 4074static const struct panel_desc tianma_tm070jvhg33 = {
4075 .timings = &tianma_tm070jdhg30_timing,
4076 .num_timings = 1,
4077 .bpc = 8,
4078 .size = {
4079 .width = 150,
4080 .height = 94,
4081 },
4082 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4083 .connector_type = DRM_MODE_CONNECTOR_LVDS,
45dd7df2 4084 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
b3bfcdf8
MM		 4085};
4086
870a0b12
LM		 4087static const struct display_timing tianma_tm070rvhg71_timing = {
4088 .pixelclock = { 27700000, 29200000, 39600000 },
4089 .hactive = { 800, 800, 800 },
4090 .hfront_porch = { 12, 40, 212 },
4091 .hback_porch = { 88, 88, 88 },
4092 .hsync_len = { 1, 1, 40 },
4093 .vactive = { 480, 480, 480 },
4094 .vfront_porch = { 1, 13, 88 },
4095 .vback_porch = { 32, 32, 32 },
4096 .vsync_len = { 1, 1, 3 },
4097 .flags = DISPLAY_FLAGS_DE_HIGH,
4098};
4099
4100static const struct panel_desc tianma_tm070rvhg71 = {
4101 .timings = &tianma_tm070rvhg71_timing,
4102 .num_timings = 1,
4103 .bpc = 8,
4104 .size = {
4105 .width = 154,
4106 .height = 86,
4107 },
4108 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 4109 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 4110};
4111
d8a0d6a3
LW		 4112static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4113 {
4114 .clock = 10000,
4115 .hdisplay = 320,
4116 .hsync_start = 320 + 50,
4117 .hsync_end = 320 + 50 + 6,
4118 .htotal = 320 + 50 + 6 + 38,
4119 .vdisplay = 240,
4120 .vsync_start = 240 + 3,
4121 .vsync_end = 240 + 3 + 1,
4122 .vtotal = 240 + 3 + 1 + 17,
d8a0d6a3
LW		 4123 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4124 },
4125};
4126
4127static const struct panel_desc ti_nspire_cx_lcd_panel = {
4128 .modes = ti_nspire_cx_lcd_mode,
4129 .num_modes = 1,
4130 .bpc = 8,
4131 .size = {
4132 .width = 65,
4133 .height = 49,
4134 },
4135 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4136 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d8a0d6a3
LW		 4137};
4138
4139static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4140 {
4141 .clock = 10000,
4142 .hdisplay = 320,
4143 .hsync_start = 320 + 6,
4144 .hsync_end = 320 + 6 + 6,
4145 .htotal = 320 + 6 + 6 + 6,
4146 .vdisplay = 240,
4147 .vsync_start = 240 + 0,
4148 .vsync_end = 240 + 0 + 1,
4149 .vtotal = 240 + 0 + 1 + 0,
d8a0d6a3
LW		 4150 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4151 },
4152};
4153
4154static const struct panel_desc ti_nspire_classic_lcd_panel = {
4155 .modes = ti_nspire_classic_lcd_mode,
4156 .num_modes = 1,
4157 /* The grayscale panel has 8 bit for the color .. Y (black) */
4158 .bpc = 8,
4159 .size = {
4160 .width = 71,
4161 .height = 53,
4162 },
4163 /* This is the grayscale bus format */
4164 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
f5436f77 4165 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
d8a0d6a3
LW		 4166};
4167
06e733e4
LS		 4168static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4169 .clock = 79500,
4170 .hdisplay = 1280,
4171 .hsync_start = 1280 + 192,
4172 .hsync_end = 1280 + 192 + 128,
4173 .htotal = 1280 + 192 + 128 + 64,
4174 .vdisplay = 768,
4175 .vsync_start = 768 + 20,
4176 .vsync_end = 768 + 20 + 7,
4177 .vtotal = 768 + 20 + 7 + 3,
06e733e4
LS		 4178};
4179
4180static const struct panel_desc toshiba_lt089ac29000 = {
4181 .modes = &toshiba_lt089ac29000_mode,
4182 .num_modes = 1,
4183 .size = {
4184 .width = 194,
4185 .height = 116,
4186 },
9781bd1d 4187 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
c4715837 4188 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 4189 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 4190};
4191
227e4f40
BD		 4192static const struct drm_display_mode tpk_f07a_0102_mode = {
4193 .clock = 33260,
4194 .hdisplay = 800,
4195 .hsync_start = 800 + 40,
4196 .hsync_end = 800 + 40 + 128,
4197 .htotal = 800 + 40 + 128 + 88,
4198 .vdisplay = 480,
4199 .vsync_start = 480 + 10,
4200 .vsync_end = 480 + 10 + 2,
4201 .vtotal = 480 + 10 + 2 + 33,
227e4f40
BD		 4202};
4203
4204static const struct panel_desc tpk_f07a_0102 = {
4205 .modes = &tpk_f07a_0102_mode,
4206 .num_modes = 1,
4207 .size = {
4208 .width = 152,
4209 .height = 91,
4210 },
88bc4178 4211 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 4212};
4213
4214static const struct drm_display_mode tpk_f10a_0102_mode = {
4215 .clock = 45000,
4216 .hdisplay = 1024,
4217 .hsync_start = 1024 + 176,
4218 .hsync_end = 1024 + 176 + 5,
4219 .htotal = 1024 + 176 + 5 + 88,
4220 .vdisplay = 600,
4221 .vsync_start = 600 + 20,
4222 .vsync_end = 600 + 20 + 5,
4223 .vtotal = 600 + 20 + 5 + 25,
227e4f40
BD		 4224};
4225
4226static const struct panel_desc tpk_f10a_0102 = {
4227 .modes = &tpk_f10a_0102_mode,
4228 .num_modes = 1,
4229 .size = {
4230 .width = 223,
4231 .height = 125,
4232 },
4233};
4234
06a9dc65
MS		 4235static const struct display_timing urt_umsh_8596md_timing = {
4236 .pixelclock = { 33260000, 33260000, 33260000 },
4237 .hactive = { 800, 800, 800 },
4238 .hfront_porch = { 41, 41, 41 },
4239 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4240 .hsync_len = { 71, 128, 128 },
4241 .vactive = { 480, 480, 480 },
4242 .vfront_porch = { 10, 10, 10 },
4243 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4244 .vsync_len = { 2, 2, 2 },
4245 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4246 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4247};
4248
4249static const struct panel_desc urt_umsh_8596md_lvds = {
4250 .timings = &urt_umsh_8596md_timing,
4251 .num_timings = 1,
4252 .bpc = 6,
4253 .size = {
4254 .width = 152,
4255 .height = 91,
4256 },
4257 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 4258 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 4259};
4260
4261static const struct panel_desc urt_umsh_8596md_parallel = {
4262 .timings = &urt_umsh_8596md_timing,
4263 .num_timings = 1,
4264 .bpc = 6,
4265 .size = {
4266 .width = 152,
4267 .height = 91,
4268 },
4269 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4270};
4271
1a84a308
NP		 4272static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4273 .clock = 60000,
4274 .hdisplay = 1024,
4275 .hsync_start = 1024 + 160,
4276 .hsync_end = 1024 + 160 + 100,
4277 .htotal = 1024 + 160 + 100 + 60,
4278 .vdisplay = 600,
4279 .vsync_start = 600 + 12,
4280 .vsync_end = 600 + 12 + 10,
4281 .vtotal = 600 + 12 + 10 + 13,
4282};
4283
4284static const struct panel_desc vivax_tpc9150_panel = {
4285 .modes = &vivax_tpc9150_panel_mode,
4286 .num_modes = 1,
4287 .bpc = 6,
4288 .size = {
4289 .width = 200,
4290 .height = 115,
4291 },
4292 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4293 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4294 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4295};
4296
04206185
FE		 4297static const struct drm_display_mode vl050_8048nt_c01_mode = {
4298 .clock = 33333,
4299 .hdisplay = 800,
4300 .hsync_start = 800 + 210,
4301 .hsync_end = 800 + 210 + 20,
4302 .htotal = 800 + 210 + 20 + 46,
4303 .vdisplay = 480,
4304 .vsync_start = 480 + 22,
4305 .vsync_end = 480 + 22 + 10,
4306 .vtotal = 480 + 22 + 10 + 23,
04206185
FE		 4307 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4308};
4309
4310static const struct panel_desc vl050_8048nt_c01 = {
4311 .modes = &vl050_8048nt_c01_mode,
4312 .num_modes = 1,
4313 .bpc = 8,
4314 .size = {
4315 .width = 120,
4316 .height = 76,
4317 },
4318 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4319 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
04206185
FE		 4320};
4321
e4bac408
RG		 4322static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4323 .clock = 6410,
4324 .hdisplay = 320,
4325 .hsync_start = 320 + 20,
4326 .hsync_end = 320 + 20 + 30,
4327 .htotal = 320 + 20 + 30 + 38,
4328 .vdisplay = 240,
4329 .vsync_start = 240 + 4,
4330 .vsync_end = 240 + 4 + 3,
4331 .vtotal = 240 + 4 + 3 + 15,
e4bac408
RG		 4332 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4333};
4334
4335static const struct panel_desc winstar_wf35ltiacd = {
4336 .modes = &winstar_wf35ltiacd_mode,
4337 .num_modes = 1,
4338 .bpc = 8,
4339 .size = {
4340 .width = 70,
4341 .height = 53,
4342 },
4343 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4344};
4345
7a1f4fa4
JT		 4346static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4347 .clock = 51200,
4348 .hdisplay = 1024,
4349 .hsync_start = 1024 + 100,
4350 .hsync_end = 1024 + 100 + 100,
4351 .htotal = 1024 + 100 + 100 + 120,
4352 .vdisplay = 600,
4353 .vsync_start = 600 + 10,
4354 .vsync_end = 600 + 10 + 10,
4355 .vtotal = 600 + 10 + 10 + 15,
4356 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4357};
4358
4359static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4360 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4361 .num_modes = 1,
44379b98 4362 .bpc = 8,
7a1f4fa4
JT		 4363 .size = {
4364 .width = 154,
4365 .height = 90,
4366 },
4367 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4368 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4369 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4370};
4371
fcec4163
LW		 4372static const struct drm_display_mode arm_rtsm_mode[] = {
4373 {
4374 .clock = 65000,
4375 .hdisplay = 1024,
4376 .hsync_start = 1024 + 24,
4377 .hsync_end = 1024 + 24 + 136,
4378 .htotal = 1024 + 24 + 136 + 160,
4379 .vdisplay = 768,
4380 .vsync_start = 768 + 3,
4381 .vsync_end = 768 + 3 + 6,
4382 .vtotal = 768 + 3 + 6 + 29,
fcec4163
LW		 4383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4384 },
4385};
4386
4387static const struct panel_desc arm_rtsm = {
4388 .modes = arm_rtsm_mode,
4389 .num_modes = 1,
4390 .bpc = 8,
4391 .size = {
4392 .width = 400,
4393 .height = 300,
4394 },
4395 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4396};
4397
280921de
TR		 4398static const struct of_device_id platform_of_match[] = {
4399 {
bca684e6
JT		 4400 .compatible = "ampire,am-1280800n3tzqw-t00h",
4401 .data = &ampire_am_1280800n3tzqw_t00h,
4402 }, {
966fea78
YF		 4403 .compatible = "ampire,am-480272h3tmqw-t01h",
4404 .data = &ampire_am_480272h3tmqw_t01h,
410bb213
GU		 4405 }, {
4406 .compatible = "ampire,am-800480l1tmqw-t00h",
4407 .data = &ampire_am_800480l1tmqw_t00h,
966fea78 4408 }, {
1c550fa1
PZ		 4409 .compatible = "ampire,am800480r3tmqwa1h",
4410 .data = &ampire_am800480r3tmqwa1h,
103f06fd
BK		 4411 }, {
4412 .compatible = "ampire,am800600p5tmqw-tb8h",
4413 .data = &ampire_am800600p5tmqwtb8h,
fcec4163
LW		 4414 }, {
4415 .compatible = "arm,rtsm-display",
4416 .data = &arm_rtsm,
c479450f
SS		 4417 }, {
4418 .compatible = "armadeus,st0700-adapt",
4419 .data = &armadeus_st0700_adapt,
1c550fa1 4420 }, {
280921de
TR		 4421 .compatible = "auo,b101aw03",
4422 .data = &auo_b101aw03,
dac746e0
RC		 4423 }, {
4424 .compatible = "auo,b101xtn01",
4425 .data = &auo_b101xtn01,
ad3e33fe
DA		 4426 }, {
4427 .compatible = "auo,b116xw03",
4428 .data = &auo_b116xw03,
bccfaffb
LM		 4429 }, {
4430 .compatible = "auo,g070vvn01",
4431 .data = &auo_g070vvn01,
4fb86404
AG		 4432 }, {
4433 .compatible = "auo,g101evn010",
4434 .data = &auo_g101evn010,
4451c287
CF		 4435 }, {
4436 .compatible = "auo,g104sn02",
4437 .data = &auo_g104sn02,
03e909ac
SR		 4438 }, {
4439 .compatible = "auo,g121ean01",
4440 .data = &auo_g121ean01,
697035c6
LS		 4441 }, {
4442 .compatible = "auo,g133han01",
4443 .data = &auo_g133han01,
9e52d5c8
EA		 4444 }, {
4445 .compatible = "auo,g156han04",
4446 .data = &auo_g156han04,
d9ccd1f2
SR		 4447 }, {
4448 .compatible = "auo,g156xtn01",
4449 .data = &auo_g156xtn01,
8c31f603
LS		 4450 }, {
4451 .compatible = "auo,g185han01",
4452 .data = &auo_g185han01,
2f7b832f
SR		 4453 }, {
4454 .compatible = "auo,g190ean01",
4455 .data = &auo_g190ean01,
70c0d5b7
LS		 4456 }, {
4457 .compatible = "auo,p320hvn03",
4458 .data = &auo_p320hvn03,
7ee933a1
HS		 4459 }, {
4460 .compatible = "auo,t215hvn01",
4461 .data = &auo_t215hvn01,
d47df633
PZ		 4462 }, {
4463 .compatible = "avic,tm070ddh03",
4464 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 4465 }, {
4466 .compatible = "bananapi,s070wv20-ct16",
4467 .data = &bananapi_s070wv20_ct16,
dc90214f
TL		 4468 }, {
4469 .compatible = "boe,bp082wx1-100",
4470 .data = &boe_bp082wx1_100,
eeaddab4
TL		 4471 }, {
4472 .compatible = "boe,bp101wx1-100",
4473 .data = &boe_bp101wx1_100,
8bb7c7bc
LY		 4474 }, {
4475 .compatible = "boe,ev121wxm-n10-1850",
4476 .data = &boe_ev121wxm_n10_1850,
ae8cf41b
AH		 4477 }, {
4478 .compatible = "boe,hv070wsa-100",
4479 .data = &boe_hv070wsa
751b5841
JD		 4480 }, {
4481 .compatible = "cct,cmt430b19n00",
4482 .data = &cct_cmt430b19n00,
e58edce6
GB		 4483 }, {
4484 .compatible = "cdtech,s043wq26h-ct7",
4485 .data = &cdtech_s043wq26h_ct7,
0e3b67f6
MK		 4486 }, {
4487 .compatible = "cdtech,s070pws19hp-fc21",
4488 .data = &cdtech_s070pws19hp_fc21,
4489 }, {
4490 .compatible = "cdtech,s070swv29hg-dc44",
4491 .data = &cdtech_s070swv29hg_dc44,
982f944e
GB		 4492 }, {
4493 .compatible = "cdtech,s070wv95-ct16",
4494 .data = &cdtech_s070wv95_ct16,
07c913c4
MV		 4495 }, {
4496 .compatible = "chefree,ch101olhlwh-002",
4497 .data = &chefree_ch101olhlwh_002,
2cb35c80
RL		 4498 }, {
4499 .compatible = "chunghwa,claa070wp03xg",
4500 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 4501 }, {
4502 .compatible = "chunghwa,claa101wa01a",
4503 .data = &chunghwa_claa101wa01a
280921de
TR		 4504 }, {
4505 .compatible = "chunghwa,claa101wb01",
4506 .data = &chunghwa_claa101wb01
4dd024d4
MV		 4507 }, {
4508 .compatible = "dataimage,fg040346dsswbg04",
4509 .data = &dataimage_fg040346dsswbg04,
803481d8
PO		 4510 }, {
4511 .compatible = "dataimage,fg1001l0dsswmg01",
4512 .data = &dataimage_fg1001l0dsswmg01,
97ceb1fb
MV		 4513 }, {
4514 .compatible = "dataimage,scf0700c48ggu18",
4515 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 4516 }, {
4517 .compatible = "dlc,dlc0700yzg-1",
4518 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 4519 }, {
4520 .compatible = "dlc,dlc1010gig",
4521 .data = &dlc_dlc1010gig,
c2d24af6
AP		 4522 }, {
4523 .compatible = "edt,et035012dm6",
4524 .data = &edt_et035012dm6,
f08a2a1e
SR		 4525 }, {
4526 .compatible = "edt,etm0350g0dh6",
4527 .data = &edt_etm0350g0dh6,
82d57a59
MCR		 4528 }, {
4529 .compatible = "edt,etm043080dh6gp",
4530 .data = &edt_etm043080dh6gp,
fd819bff
MV		 4531 }, {
4532 .compatible = "edt,etm0430g0dh6",
4533 .data = &edt_etm0430g0dh6,
26ab0065
SA		 4534 }, {
4535 .compatible = "edt,et057090dhu",
4536 .data = &edt_et057090dhu,
fff5de45
PZ		 4537 }, {
4538 .compatible = "edt,et070080dh6",
4539 .data = &edt_etm0700g0dh6,
4540 }, {
4541 .compatible = "edt,etm0700g0dh6",
4542 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 4543 }, {
4544 .compatible = "edt,etm0700g0bdh6",
4545 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 4546 }, {
4547 .compatible = "edt,etm0700g0edh6",
4548 .data = &edt_etm0700g0bdh6,
a6cc3c72
MF		 4549 }, {
4550 .compatible = "edt,etml0700y5dha",
4551 .data = &edt_etml0700y5dha,
aeb262c3
PF		 4552 }, {
4553 .compatible = "edt,etml1010g3dra",
4554 .data = &edt_etml1010g3dra,
e46f73fb
SR		 4555 }, {
4556 .compatible = "edt,etmv570g2dhu",
4557 .data = &edt_etmv570g2dhu,
9746f5fe
AF		 4558 }, {
4559 .compatible = "eink,vb3300-kca",
4560 .data = &eink_vb3300_kca,
1319f217
MW		 4561 }, {
4562 .compatible = "evervision,vgg644804",
4563 .data = &evervision_vgg644804,
9158e3c3
MF		 4564 }, {
4565 .compatible = "evervision,vgg804821",
4566 .data = &evervision_vgg804821,
102932b0
BB		 4567 }, {
4568 .compatible = "foxlink,fl500wvr00-a0t",
4569 .data = &foxlink_fl500wvr00_a0t,
7b6bd843
PC		 4570 }, {
4571 .compatible = "frida,frd350h54004",
4572 .data = &frida_frd350h54004,
3be20710
JT		 4573 }, {
4574 .compatible = "friendlyarm,hd702e",
4575 .data = &friendlyarm_hd702e,
d435a2af
PZ		 4576 }, {
4577 .compatible = "giantplus,gpg482739qs5",
4578 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 4579 }, {
4580 .compatible = "giantplus,gpm940b0",
4581 .data = &giantplus_gpm940b0,
a853205e
PZ		 4582 }, {
4583 .compatible = "hannstar,hsd070pww1",
4584 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 4585 }, {
4586 .compatible = "hannstar,hsd100pxn1",
4587 .data = &hannstar_hsd100pxn1,
170a41e9
SR		 4588 }, {
4589 .compatible = "hannstar,hsd101pww2",
4590 .data = &hannstar_hsd101pww2,
61ac0bf8
LS		 4591 }, {
4592 .compatible = "hit,tx23d38vm0caa",
4593 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 4594 }, {
4595 .compatible = "innolux,at043tn24",
4596 .data = &innolux_at043tn24,
4fc24ab3
RB		 4597 }, {
4598 .compatible = "innolux,at070tn92",
4599 .data = &innolux_at070tn92,
1993f598
RL		 4600 }, {
4601 .compatible = "innolux,g070ace-l01",
4602 .data = &innolux_g070ace_l01,
1e29b840 4603 }, {
a5d2ade6
CF		 4604 .compatible = "innolux,g070y2-l01",
4605 .data = &innolux_g070y2_l01,
57a06e90
OR		 4606 }, {
4607 .compatible = "innolux,g070y2-t02",
4608 .data = &innolux_g070y2_t02,
a5d2ade6
CF		 4609 }, {
4610 .compatible = "innolux,g101ice-l01",
1e29b840 4611 .data = &innolux_g101ice_l01
d731f661 4612 }, {
a5d2ade6 4613 .compatible = "innolux,g121i1-l01",
d731f661 4614 .data = &innolux_g121i1_l01
f8fa17ba
AB		 4615 }, {
4616 .compatible = "innolux,g121x1-l03",
4617 .data = &innolux_g121x1_l03,
f7ad2ce5
MV		 4618 }, {
4619 .compatible = "innolux,g121xce-l01",
4620 .data = &innolux_g121xce_l01,
eae74888
MV		 4621 }, {
4622 .compatible = "innolux,g156hce-l01",
4623 .data = &innolux_g156hce_l01,
ea44739d
AB		 4624 }, {
4625 .compatible = "innolux,n156bge-l21",
4626 .data = &innolux_n156bge_l21,
bccac3f1
MG		 4627 }, {
4628 .compatible = "innolux,zj070na-01p",
4629 .data = &innolux_zj070na_01p,
14bf60c4
LM		 4630 }, {
4631 .compatible = "koe,tx14d24vm1bpa",
4632 .data = &koe_tx14d24vm1bpa,
8a070524
LY		 4633 }, {
4634 .compatible = "koe,tx26d202vm0bwa",
4635 .data = &koe_tx26d202vm0bwa,
8cfe8341
JT		 4636 }, {
4637 .compatible = "koe,tx31d200vm0baa",
4638 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 4639 }, {
4640 .compatible = "kyo,tcg121xglp",
4641 .data = &kyo_tcg121xglp,
27abdd83
PK		 4642 }, {
4643 .compatible = "lemaker,bl035-rgb-002",
4644 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 4645 }, {
4646 .compatible = "lg,lb070wv8",
4647 .data = &lg_lb070wv8,
0d35408a
AF		 4648 }, {
4649 .compatible = "logicpd,type28",
4650 .data = &logicpd_type_28,
5728fe7f
MZ		 4651 }, {
4652 .compatible = "logictechno,lt161010-2nhc",
4653 .data = &logictechno_lt161010_2nh,
4654 }, {
4655 .compatible = "logictechno,lt161010-2nhr",
4656 .data = &logictechno_lt161010_2nh,
4657 }, {
4658 .compatible = "logictechno,lt170410-2whc",
4659 .data = &logictechno_lt170410_2whc,
19f036ea
SA		 4660 }, {
4661 .compatible = "logictechno,lttd800480070-l2rt",
4662 .data = &logictechno_lttd800480070_l2rt,
0c044f7d
SA		 4663 }, {
4664 .compatible = "logictechno,lttd800480070-l6wh-rt",
4665 .data = &logictechno_lttd800480070_l6wh_rt,
65c766ca
LM		 4666 }, {
4667 .compatible = "mitsubishi,aa070mc01-ca1",
4668 .data = &mitsubishi_aa070mc01,
637d3fdc
TW		 4669 }, {
4670 .compatible = "mitsubishi,aa084xe01",
4671 .data = &mitsubishi_aa084xe01,
a5d092d3
MV		 4672 }, {
4673 .compatible = "multi-inno,mi0700s4t-6",
4674 .data = &multi_inno_mi0700s4t_6,
b55002b9
CN		 4675 }, {
4676 .compatible = "multi-inno,mi0800ft-9",
4677 .data = &multi_inno_mi0800ft_9,
81162f4b
SR		 4678 }, {
4679 .compatible = "multi-inno,mi1010ait-1cp",
4680 .data = &multi_inno_mi1010ait_1cp,
01bacc13
LS		 4681 }, {
4682 .compatible = "nec,nl12880bc20-05",
4683 .data = &nec_nl12880bc20_05,
c6e87f91 4684 }, {
4685 .compatible = "nec,nl4827hc19-05b",
4686 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 4687 }, {
4688 .compatible = "netron-dy,e231732",
4689 .data = &netron_dy_e231732,
3b39ad7a
TV		 4690 }, {
4691 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4692 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 4693 }, {
4694 .compatible = "nlt,nl192108ac18-02d",
4695 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 4696 }, {
4697 .compatible = "nvd,9128",
4698 .data = &nvd_9128,
a99fb626
GB		 4699 }, {
4700 .compatible = "okaya,rs800480t-7x0gp",
4701 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 4702 }, {
4703 .compatible = "olimex,lcd-olinuxino-43-ts",
4704 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 4705 }, {
4706 .compatible = "ontat,yx700wv03",
4707 .data = &ontat_yx700wv03,
9c31dcb6
NS		 4708 }, {
4709 .compatible = "ortustech,com37h3m05dtc",
4710 .data = &ortustech_com37h3m,
4711 }, {
4712 .compatible = "ortustech,com37h3m99dtc",
4713 .data = &ortustech_com37h3m,
725c9d40
PZ		 4714 }, {
4715 .compatible = "ortustech,com43h4m85ulc",
4716 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 4717 }, {
4718 .compatible = "osddisplays,osd070t1718-19ts",
4719 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 4720 }, {
4721 .compatible = "pda,91-00156-a0",
4722 .data = &pda_91_00156_a0,
fd6aa8f2
NM		 4723 }, {
4724 .compatible = "powertip,ph128800t006-zhc01",
4725 .data = &powertip_ph128800t006_zhc01,
d69de69f
MV		 4726 }, {
4727 .compatible = "powertip,ph800480t013-idf02",
4728 .data = &powertip_ph800480t013_idf02,
d2a6f0f5
JW		 4729 }, {
4730 .compatible = "qiaodian,qd43003c0-40",
4731 .data = &qd43003c0_40,
49179e66
AV		 4732 }, {
4733 .compatible = "qishenglong,gopher2b-lcd",
4734 .data = &qishenglong_gopher2b_lcd,
13cdd12a
DB		 4735 }, {
4736 .compatible = "rocktech,rk043fn48h",
4737 .data = &rocktech_rk043fn48h,
23167fa9
JT		 4738 }, {
4739 .compatible = "rocktech,rk070er9427",
4740 .data = &rocktech_rk070er9427,
f305047b
JS		 4741 }, {
4742 .compatible = "rocktech,rk101ii01d-ct",
4743 .data = &rocktech_rk101ii01d_ct,
a6aa679a
MJ		 4744 }, {
4745 .compatible = "samsung,ltl101al01",
4746 .data = &samsung_ltl101al01,
6d54e3d2
MD		 4747 }, {
4748 .compatible = "samsung,ltn101nt05",
4749 .data = &samsung_ltn101nt05,
44c58c52
MR		 4750 }, {
4751 .compatible = "satoz,sat050at40h12r2",
4752 .data = &satoz_sat050at40h12r2,
03e3ec9a
VZ		 4753 }, {
4754 .compatible = "sharp,lq035q7db03",
4755 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 4756 }, {
4757 .compatible = "sharp,lq070y3dg3b",
4758 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 4759 }, {
4760 .compatible = "sharp,lq101k1ly04",
4761 .data = &sharp_lq101k1ly04,
f1bd37f3
PC		 4762 }, {
4763 .compatible = "sharp,ls020b1dd01d",
4764 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 4765 }, {
4766 .compatible = "shelly,sca07010-bfn-lnn",
4767 .data = &shelly_sca07010_bfn_lnn,
105235e4
PR		 4768 }, {
4769 .compatible = "starry,kr070pe2t",
4770 .data = &starry_kr070pe2t,
9ff92363
HS		 4771 }, {
4772 .compatible = "startek,kd070wvfpa",
4773 .data = &startek_kd070wvfpa,
938db276
MV		 4774 }, {
4775 .compatible = "team-source-display,tst043015cmhx",
4776 .data = &tsd_tst043015cmhx,
42161531
JS		 4777 }, {
4778 .compatible = "tfc,s9700rtwv43tr-01b",
4779 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 4780 }, {
4781 .compatible = "tianma,tm070jdhg30",
4782 .data = &tianma_tm070jdhg30,
b3bfcdf8
MM		 4783 }, {
4784 .compatible = "tianma,tm070jvhg33",
4785 .data = &tianma_tm070jvhg33,
870a0b12
LM		 4786 }, {
4787 .compatible = "tianma,tm070rvhg71",
4788 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 4789 }, {
4790 .compatible = "ti,nspire-cx-lcd-panel",
4791 .data = &ti_nspire_cx_lcd_panel,
4792 }, {
4793 .compatible = "ti,nspire-classic-lcd-panel",
4794 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 4795 }, {
4796 .compatible = "toshiba,lt089ac29000",
4797 .data = &toshiba_lt089ac29000,
227e4f40
BD		 4798 }, {
4799 .compatible = "tpk,f07a-0102",
4800 .data = &tpk_f07a_0102,
4801 }, {
4802 .compatible = "tpk,f10a-0102",
4803 .data = &tpk_f10a_0102,
06a9dc65
MS		 4804 }, {
4805 .compatible = "urt,umsh-8596md-t",
4806 .data = &urt_umsh_8596md_parallel,
4807 }, {
4808 .compatible = "urt,umsh-8596md-1t",
4809 .data = &urt_umsh_8596md_parallel,
4810 }, {
4811 .compatible = "urt,umsh-8596md-7t",
4812 .data = &urt_umsh_8596md_parallel,
4813 }, {
4814 .compatible = "urt,umsh-8596md-11t",
4815 .data = &urt_umsh_8596md_lvds,
4816 }, {
4817 .compatible = "urt,umsh-8596md-19t",
4818 .data = &urt_umsh_8596md_lvds,
4819 }, {
4820 .compatible = "urt,umsh-8596md-20t",
4821 .data = &urt_umsh_8596md_parallel,
1a84a308
NP		 4822 }, {
4823 .compatible = "vivax,tpc9150-panel",
4824 .data = &vivax_tpc9150_panel,
04206185
FE		 4825 }, {
4826 .compatible = "vxt,vl050-8048nt-c01",
4827 .data = &vl050_8048nt_c01,
e4bac408
RG		 4828 }, {
4829 .compatible = "winstar,wf35ltiacd",
4830 .data = &winstar_wf35ltiacd,
7a1f4fa4
JT		 4831 }, {
4832 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4833 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4a1d0dbc
SR		 4834 }, {
4835 /* Must be the last entry */
4836 .compatible = "panel-dpi",
4837 .data = &panel_dpi,
280921de
TR		 4838 }, {
4839 /* sentinel */
4840 }
4841};
4842MODULE_DEVICE_TABLE(of, platform_of_match);
4843
4844static int panel_simple_platform_probe(struct platform_device *pdev)
4845{
a7f880bc 4846 const struct panel_desc *desc;
280921de 4847
a7f880bc
GU		 4848 desc = of_device_get_match_data(&pdev->dev);
4849 if (!desc)
280921de
TR		 4850 return -ENODEV;
4851
a7f880bc 4852 return panel_simple_probe(&pdev->dev, desc);
280921de
TR		 4853}
4854
cef3776d 4855static void panel_simple_platform_remove(struct platform_device *pdev)
280921de 4856{
d72ac4bb 4857 panel_simple_remove(&pdev->dev);
280921de
TR		 4858}
4859
d02fd93e
TR		 4860static void panel_simple_platform_shutdown(struct platform_device *pdev)
4861{
4862 panel_simple_shutdown(&pdev->dev);
4863}
4864
3235b0f2
DA		 4865static const struct dev_pm_ops panel_simple_pm_ops = {
4866 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4867 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4868 pm_runtime_force_resume)
4869};
4870
280921de
TR		 4871static struct platform_driver panel_simple_platform_driver = {
4872 .driver = {
4873 .name = "panel-simple",
280921de 4874 .of_match_table = platform_of_match,
3235b0f2 4875 .pm = &panel_simple_pm_ops,
280921de
TR		 4876 },
4877 .probe = panel_simple_platform_probe,
cef3776d 4878 .remove_new = panel_simple_platform_remove,
d02fd93e 4879 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 4880};
4881
210fcd9d
TR		 4882struct panel_desc_dsi {
4883 struct panel_desc desc;
4884
462658b8 4885 unsigned long flags;
210fcd9d
TR		 4886 enum mipi_dsi_pixel_format format;
4887 unsigned int lanes;
4888};
4889
d718d79e
TR		 4890static const struct drm_display_mode auo_b080uan01_mode = {
4891 .clock = 154500,
4892 .hdisplay = 1200,
4893 .hsync_start = 1200 + 62,
4894 .hsync_end = 1200 + 62 + 4,
4895 .htotal = 1200 + 62 + 4 + 62,
4896 .vdisplay = 1920,
4897 .vsync_start = 1920 + 9,
4898 .vsync_end = 1920 + 9 + 2,
4899 .vtotal = 1920 + 9 + 2 + 8,
d718d79e
TR		 4900};
4901
4902static const struct panel_desc_dsi auo_b080uan01 = {
4903 .desc = {
4904 .modes = &auo_b080uan01_mode,
4905 .num_modes = 1,
4906 .bpc = 8,
4907 .size = {
4908 .width = 108,
4909 .height = 272,
4910 },
cb62cdec 4911 .connector_type = DRM_MODE_CONNECTOR_DSI,
d718d79e
TR		 4912 },
4913 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4914 .format = MIPI_DSI_FMT_RGB888,
4915 .lanes = 4,
4916};
4917
c8521969
CZ		 4918static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4919 .clock = 160000,
4920 .hdisplay = 1200,
4921 .hsync_start = 1200 + 120,
4922 .hsync_end = 1200 + 120 + 20,
4923 .htotal = 1200 + 120 + 20 + 21,
4924 .vdisplay = 1920,
4925 .vsync_start = 1920 + 21,
4926 .vsync_end = 1920 + 21 + 3,
4927 .vtotal = 1920 + 21 + 3 + 18,
c8521969
CZ		 4928 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4929};
4930
4931static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4932 .desc = {
4933 .modes = &boe_tv080wum_nl0_mode,
4934 .num_modes = 1,
4935 .size = {
4936 .width = 107,
4937 .height = 172,
4938 },
cb62cdec 4939 .connector_type = DRM_MODE_CONNECTOR_DSI,
c8521969
CZ		 4940 },
4941 .flags = MIPI_DSI_MODE_VIDEO |
4942 MIPI_DSI_MODE_VIDEO_BURST |
4943 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4944 .format = MIPI_DSI_FMT_RGB888,
4945 .lanes = 4,
4946};
4947
712ac1ba
AC		 4948static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4949 .clock = 71000,
4950 .hdisplay = 800,
4951 .hsync_start = 800 + 32,
4952 .hsync_end = 800 + 32 + 1,
4953 .htotal = 800 + 32 + 1 + 57,
4954 .vdisplay = 1280,
4955 .vsync_start = 1280 + 28,
4956 .vsync_end = 1280 + 28 + 1,
4957 .vtotal = 1280 + 28 + 1 + 14,
712ac1ba
AC		 4958};
4959
4960static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4961 .desc = {
4962 .modes = &lg_ld070wx3_sl01_mode,
4963 .num_modes = 1,
d7a839cd 4964 .bpc = 8,
712ac1ba
AC		 4965 .size = {
4966 .width = 94,
4967 .height = 151,
4968 },
cb62cdec 4969 .connector_type = DRM_MODE_CONNECTOR_DSI,
712ac1ba 4970 },
5e4cc278 4971 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 4972 .format = MIPI_DSI_FMT_RGB888,
4973 .lanes = 4,
4974};
4975
499ce85a
AC		 4976static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4977 .clock = 67000,
4978 .hdisplay = 720,
4979 .hsync_start = 720 + 12,
4980 .hsync_end = 720 + 12 + 4,
4981 .htotal = 720 + 12 + 4 + 112,
4982 .vdisplay = 1280,
4983 .vsync_start = 1280 + 8,
4984 .vsync_end = 1280 + 8 + 4,
4985 .vtotal = 1280 + 8 + 4 + 12,
499ce85a
AC		 4986};
4987
4988static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4989 .desc = {
4990 .modes = &lg_lh500wx1_sd03_mode,
4991 .num_modes = 1,
d7a839cd 4992 .bpc = 8,
499ce85a
AC		 4993 .size = {
4994 .width = 62,
4995 .height = 110,
4996 },
cb62cdec 4997 .connector_type = DRM_MODE_CONNECTOR_DSI,
499ce85a
AC		 4998 },
4999 .flags = MIPI_DSI_MODE_VIDEO,
5000 .format = MIPI_DSI_FMT_RGB888,
5001 .lanes = 4,
5002};
5003
280921de
TR		 5004static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5005 .clock = 157200,
5006 .hdisplay = 1920,
5007 .hsync_start = 1920 + 154,
5008 .hsync_end = 1920 + 154 + 16,
5009 .htotal = 1920 + 154 + 16 + 32,
5010 .vdisplay = 1200,
5011 .vsync_start = 1200 + 17,
5012 .vsync_end = 1200 + 17 + 2,
5013 .vtotal = 1200 + 17 + 2 + 16,
280921de
TR		 5014};
5015
210fcd9d
TR		 5016static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5017 .desc = {
5018 .modes = &panasonic_vvx10f004b00_mode,
5019 .num_modes = 1,
d7a839cd 5020 .bpc = 8,
210fcd9d
TR		 5021 .size = {
5022 .width = 217,
5023 .height = 136,
5024 },
cb62cdec 5025 .connector_type = DRM_MODE_CONNECTOR_DSI,
280921de 5026 },
5e4cc278
AC		 5027 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5028 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 5029 .format = MIPI_DSI_FMT_RGB888,
5030 .lanes = 4,
5031};
5032
debcd8f9
JM		 5033static const struct drm_display_mode lg_acx467akm_7_mode = {
5034 .clock = 150000,
5035 .hdisplay = 1080,
5036 .hsync_start = 1080 + 2,
5037 .hsync_end = 1080 + 2 + 2,
5038 .htotal = 1080 + 2 + 2 + 2,
5039 .vdisplay = 1920,
5040 .vsync_start = 1920 + 2,
5041 .vsync_end = 1920 + 2 + 2,
5042 .vtotal = 1920 + 2 + 2 + 2,
debcd8f9
JM		 5043};
5044
5045static const struct panel_desc_dsi lg_acx467akm_7 = {
5046 .desc = {
5047 .modes = &lg_acx467akm_7_mode,
5048 .num_modes = 1,
5049 .bpc = 8,
5050 .size = {
5051 .width = 62,
5052 .height = 110,
5053 },
cb62cdec 5054 .connector_type = DRM_MODE_CONNECTOR_DSI,
debcd8f9
JM		 5055 },
5056 .flags = 0,
5057 .format = MIPI_DSI_FMT_RGB888,
5058 .lanes = 4,
5059};
5060
62967232
PU		 5061static const struct drm_display_mode osd101t2045_53ts_mode = {
5062 .clock = 154500,
5063 .hdisplay = 1920,
5064 .hsync_start = 1920 + 112,
5065 .hsync_end = 1920 + 112 + 16,
5066 .htotal = 1920 + 112 + 16 + 32,
5067 .vdisplay = 1200,
5068 .vsync_start = 1200 + 16,
5069 .vsync_end = 1200 + 16 + 2,
5070 .vtotal = 1200 + 16 + 2 + 16,
62967232
PU		 5071 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5072};
5073
5074static const struct panel_desc_dsi osd101t2045_53ts = {
5075 .desc = {
5076 .modes = &osd101t2045_53ts_mode,
5077 .num_modes = 1,
5078 .bpc = 8,
5079 .size = {
5080 .width = 217,
5081 .height = 136,
5082 },
cb62cdec 5083 .connector_type = DRM_MODE_CONNECTOR_DSI,
62967232
PU		 5084 },
5085 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5086 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
0f3b68b6 5087 MIPI_DSI_MODE_NO_EOT_PACKET,
62967232
PU		 5088 .format = MIPI_DSI_FMT_RGB888,
5089 .lanes = 4,
5090};
5091
210fcd9d
TR		 5092static const struct of_device_id dsi_of_match[] = {
5093 {
d718d79e
TR		 5094 .compatible = "auo,b080uan01",
5095 .data = &auo_b080uan01
c8521969
CZ		 5096 }, {
5097 .compatible = "boe,tv080wum-nl0",
5098 .data = &boe_tv080wum_nl0
d718d79e 5099 }, {
712ac1ba
AC		 5100 .compatible = "lg,ld070wx3-sl01",
5101 .data = &lg_ld070wx3_sl01
5102 }, {
499ce85a
AC		 5103 .compatible = "lg,lh500wx1-sd03",
5104 .data = &lg_lh500wx1_sd03
5105 }, {
210fcd9d
TR		 5106 .compatible = "panasonic,vvx10f004b00",
5107 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 5108 }, {
5109 .compatible = "lg,acx467akm-7",
5110 .data = &lg_acx467akm_7
62967232
PU		 5111 }, {
5112 .compatible = "osddisplays,osd101t2045-53ts",
5113 .data = &osd101t2045_53ts
210fcd9d
TR		 5114 }, {
5115 /* sentinel */
5116 }
5117};
5118MODULE_DEVICE_TABLE(of, dsi_of_match);
5119
5120static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5121{
5122 const struct panel_desc_dsi *desc;
210fcd9d
TR		 5123 int err;
5124
a7f880bc
GU		 5125 desc = of_device_get_match_data(&dsi->dev);
5126 if (!desc)
210fcd9d
TR		 5127 return -ENODEV;
5128
5f04e7ce 5129 err = panel_simple_probe(&dsi->dev, &desc->desc);
210fcd9d
TR		 5130 if (err < 0)
5131 return err;
5132
462658b8 5133 dsi->mode_flags = desc->flags;
210fcd9d
TR		 5134 dsi->format = desc->format;
5135 dsi->lanes = desc->lanes;
5136
7ad9db66
PU		 5137 err = mipi_dsi_attach(dsi);
5138 if (err) {
5dd331d4 5139 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
7ad9db66
PU		 5140
5141 drm_panel_remove(&panel->base);
5142 }
5143
5144 return err;
210fcd9d
TR		 5145}
5146
79abca2b 5147static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
210fcd9d
TR		 5148{
5149 int err;
5150
5151 err = mipi_dsi_detach(dsi);
5152 if (err < 0)
5153 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5154
d72ac4bb 5155 panel_simple_remove(&dsi->dev);
210fcd9d
TR		 5156}
5157
d02fd93e
TR		 5158static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5159{
5160 panel_simple_shutdown(&dsi->dev);
5161}
5162
210fcd9d
TR		 5163static struct mipi_dsi_driver panel_simple_dsi_driver = {
5164 .driver = {
5165 .name = "panel-simple-dsi",
210fcd9d 5166 .of_match_table = dsi_of_match,
3235b0f2 5167 .pm = &panel_simple_pm_ops,
210fcd9d
TR		 5168 },
5169 .probe = panel_simple_dsi_probe,
5170 .remove = panel_simple_dsi_remove,
d02fd93e 5171 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 5172};
5173
5174static int __init panel_simple_init(void)
5175{
210fcd9d
TR		 5176 int err;
5177
5178 err = platform_driver_register(&panel_simple_platform_driver);
5179 if (err < 0)
5180 return err;
5181
5182 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5183 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
74c06c28 5184 if (err < 0)
5f04e7ce 5185 goto err_did_platform_register;
210fcd9d
TR		 5186 }
5187
5188 return 0;
74c06c28 5189
74c06c28
DA		 5190err_did_platform_register:
5191 platform_driver_unregister(&panel_simple_platform_driver);
5192
5193 return err;
280921de
TR		 5194}
5195module_init(panel_simple_init);
5196
5197static void __exit panel_simple_exit(void)
5198{
210fcd9d
TR		 5199 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5200 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5201
280921de
TR		 5202 platform_driver_unregister(&panel_simple_platform_driver);
5203}
5204module_exit(panel_simple_exit);
5205
5206MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5207MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5208MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)