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Linux 6.17-rc6
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
a204f974 26#include <linux/i2c.h>
72bd9ea3 27#include <linux/media-bus-format.h>
280921de 28#include <linux/module.h>
47c08262 29#include <linux/of_device.h>
280921de
TR		 30#include <linux/of_platform.h>
31#include <linux/platform_device.h>
3235b0f2 32#include <linux/pm_runtime.h>
280921de
TR		 33#include <linux/regulator/consumer.h>
34
cb23eae3 35#include <video/display_timing.h>
b8a2948f 36#include <video/of_display_timing.h>
cb23eae3
SR		 37#include <video/videomode.h>
38
280921de 39#include <drm/drm_crtc.h>
cb23eae3 40#include <drm/drm_device.h>
255490f9 41#include <drm/drm_edid.h>
210fcd9d 42#include <drm/drm_mipi_dsi.h>
280921de 43#include <drm/drm_panel.h>
1cd3ea3e 44#include <drm/drm_of.h>
280921de 45
e362cc6a 46/**
a00fa428 47 * struct panel_desc - Describes a simple panel.
e362cc6a 48 */
280921de 49struct panel_desc {
a00fa428
DA		 50 /**
51 * @modes: Pointer to array of fixed modes appropriate for this panel.
52 *
53 * If only one mode then this can just be the address of the mode.
54 * NOTE: cannot be used with "timings" and also if this is specified
55 * then you cannot override the mode in the device tree.
56 */
280921de 57 const struct drm_display_mode *modes;
a00fa428
DA		 58
59 /** @num_modes: Number of elements in modes array. */
280921de 60 unsigned int num_modes;
a00fa428
DA		 61
62 /**
63 * @timings: Pointer to array of display timings
64 *
65 * NOTE: cannot be used with "modes" and also these will be used to
66 * validate a device tree override if one is present.
67 */
a5d3e625 68 const struct display_timing *timings;
a00fa428
DA		 69
70 /** @num_timings: Number of elements in timings array. */
a5d3e625 71 unsigned int num_timings;
280921de 72
a00fa428 73 /** @bpc: Bits per color. */
0208d511
SM		 74 unsigned int bpc;
75
a00fa428 76 /** @size: Structure containing the physical size of this panel. */
280921de 77 struct {
131f909a
DA		 78 /**
79 * @size.width: Width (in mm) of the active display area.
80 */
280921de 81 unsigned int width;
131f909a
DA		 82
83 /**
84 * @size.height: Height (in mm) of the active display area.
85 */
280921de
TR		 86 unsigned int height;
87 } size;
f673c37e 88
a00fa428 89 /** @delay: Structure containing various delay values for this panel. */
f673c37e 90 struct {
131f909a
DA		 91 /**
92 * @delay.prepare: Time for the panel to become ready.
93 *
94 * The time (in milliseconds) that it takes for the panel to
95 * become ready and start receiving video data
96 */
f673c37e 97 unsigned int prepare;
131f909a 98
131f909a
DA		 99 /**
100 * @delay.enable: Time for the panel to display a valid frame.
101 *
102 * The time (in milliseconds) that it takes for the panel to
103 * display the first valid frame after starting to receive
104 * video data.
105 */
f673c37e 106 unsigned int enable;
131f909a
DA		 107
108 /**
109 * @delay.disable: Time for the panel to turn the display off.
110 *
111 * The time (in milliseconds) that it takes for the panel to
112 * turn the display off (no content is visible).
113 */
f673c37e 114 unsigned int disable;
131f909a
DA		 115
116 /**
117 * @delay.unprepare: Time to power down completely.
118 *
119 * The time (in milliseconds) that it takes for the panel
120 * to power itself down completely.
e5e30dfc
DA		 121 *
122 * This time is used to prevent a future "prepare" from
123 * starting until at least this many milliseconds has passed.
124 * If at prepare time less time has passed since unprepare
125 * finished, the driver waits for the remaining time.
131f909a 126 */
f673c37e
AK		 127 unsigned int unprepare;
128 } delay;
795f7ab3 129
a00fa428 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
795f7ab3 131 u32 bus_format;
a00fa428
DA		 132
133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
f0aa0838 134 u32 bus_flags;
a00fa428
DA		 135
136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
9a2654c0 137 int connector_type;
280921de
TR		 138};
139
47c08262
MR		 140struct panel_desc_dsi {
141 struct panel_desc desc;
142
143 unsigned long flags;
144 enum mipi_dsi_pixel_format format;
145 unsigned int lanes;
146};
147
280921de
TR		 148struct panel_simple {
149 struct drm_panel base;
3235b0f2 150
e5e30dfc
DA		 151 ktime_t unprepared_time;
152
280921de
TR		 153 const struct panel_desc *desc;
154
280921de
TR		 155 struct regulator *supply;
156 struct i2c_adapter *ddc;
157
cfdf0549 158 struct gpio_desc *enable_gpio;
b8a2948f 159
e69da902 160 const struct drm_edid *drm_edid;
63358e24 161
b8a2948f 162 struct drm_display_mode override_mode;
5759c967
DO		 163
164 enum drm_panel_orientation orientation;
280921de
TR		 165};
166
167static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
168{
169 return container_of(panel, struct panel_simple, base);
170}
171
0ce8ddd8
SR		 172static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
173 struct drm_connector *connector)
280921de 174{
280921de
TR		 175 struct drm_display_mode *mode;
176 unsigned int i, num = 0;
177
a5d3e625
PZ		 178 for (i = 0; i < panel->desc->num_timings; i++) {
179 const struct display_timing *dt = &panel->desc->timings[i];
180 struct videomode vm;
181
182 videomode_from_timing(dt, &vm);
aa6c4364 183 mode = drm_mode_create(connector->dev);
a5d3e625 184 if (!mode) {
aa6c4364 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 186 dt->hactive.typ, dt->vactive.typ);
187 continue;
188 }
189
190 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 191
192 mode->type |= DRM_MODE_TYPE_DRIVER;
193
230c5b44 194 if (panel->desc->num_timings == 1)
cda55372
BB		 195 mode->type |= DRM_MODE_TYPE_PREFERRED;
196
a5d3e625
PZ		 197 drm_mode_probed_add(connector, mode);
198 num++;
199 }
200
b8a2948f
SP		 201 return num;
202}
203
0ce8ddd8
SR		 204static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
205 struct drm_connector *connector)
b8a2948f 206{
b8a2948f
SP		 207 struct drm_display_mode *mode;
208 unsigned int i, num = 0;
209
280921de
TR		 210 for (i = 0; i < panel->desc->num_modes; i++) {
211 const struct drm_display_mode *m = &panel->desc->modes[i];
212
aa6c4364 213 mode = drm_mode_duplicate(connector->dev, m);
280921de 214 if (!mode) {
aa6c4364 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
0425662f
VS		 216 m->hdisplay, m->vdisplay,
217 drm_mode_vrefresh(m));
280921de
TR		 218 continue;
219 }
220
cda55372
BB		 221 mode->type |= DRM_MODE_TYPE_DRIVER;
222
223 if (panel->desc->num_modes == 1)
224 mode->type |= DRM_MODE_TYPE_PREFERRED;
225
280921de
TR		 226 drm_mode_set_name(mode);
227
228 drm_mode_probed_add(connector, mode);
229 num++;
230 }
231
b8a2948f
SP		 232 return num;
233}
234
0ce8ddd8
SR		 235static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
236 struct drm_connector *connector)
b8a2948f 237{
b8a2948f
SP		 238 struct drm_display_mode *mode;
239 bool has_override = panel->override_mode.type;
240 unsigned int num = 0;
241
242 if (!panel->desc)
243 return 0;
244
245 if (has_override) {
aa6c4364
SR		 246 mode = drm_mode_duplicate(connector->dev,
247 &panel->override_mode);
b8a2948f
SP		 248 if (mode) {
249 drm_mode_probed_add(connector, mode);
250 num = 1;
251 } else {
aa6c4364 252 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 253 }
254 }
255
256 /* Only add timings if override was not there or failed to validate */
257 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 258 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 259
260 /*
261 * Only add fixed modes if timings/override added no mode.
262 *
263 * We should only ever have either the display timings specified
264 * or a fixed mode. Anything else is rather bogus.
265 */
266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
267 if (num == 0)
0ce8ddd8 268 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 269
0208d511 270 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 271 connector->display_info.width_mm = panel->desc->size.width;
272 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 273 if (panel->desc->bus_format)
274 drm_display_info_set_bus_formats(&connector->display_info,
275 &panel->desc->bus_format, 1);
f0aa0838 276 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 277
278 return num;
279}
280
e5e30dfc
DA		 281static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
282{
283 ktime_t now_ktime, min_ktime;
284
285 if (!min_ms)
286 return;
287
288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
7e682946 289 now_ktime = ktime_get_boottime();
e5e30dfc
DA		 290
291 if (ktime_before(now_ktime, min_ktime))
292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
293}
294
280921de
TR		 295static int panel_simple_disable(struct drm_panel *panel)
296{
297 struct panel_simple *p = to_panel_simple(panel);
298
f673c37e
AK		 299 if (p->desc->delay.disable)
300 msleep(p->desc->delay.disable);
301
280921de
TR		 302 return 0;
303}
304
3235b0f2
DA		 305static int panel_simple_suspend(struct device *dev)
306{
307 struct panel_simple *p = dev_get_drvdata(dev);
308
309 gpiod_set_value_cansleep(p->enable_gpio, 0);
310 regulator_disable(p->supply);
7e682946 311 p->unprepared_time = ktime_get_boottime();
3235b0f2 312
e69da902
JN		 313 drm_edid_free(p->drm_edid);
314 p->drm_edid = NULL;
63358e24 315
3235b0f2
DA		 316 return 0;
317}
318
c0e1d170
AK		 319static int panel_simple_unprepare(struct drm_panel *panel)
320{
3235b0f2 321 int ret;
613a633e 322
3235b0f2
DA		 323 pm_runtime_mark_last_busy(panel->dev);
324 ret = pm_runtime_put_autosuspend(panel->dev);
325 if (ret < 0)
326 return ret;
c0e1d170 327
c0e1d170
AK		 328 return 0;
329}
330
b6d5ffce 331static int panel_simple_resume(struct device *dev)
280921de 332{
b6d5ffce 333 struct panel_simple *p = dev_get_drvdata(dev);
280921de
TR		 334 int err;
335
e5e30dfc
DA		 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
337
280921de
TR		 338 err = regulator_enable(p->supply);
339 if (err < 0) {
3235b0f2 340 dev_err(dev, "failed to enable supply: %d\n", err);
280921de
TR		 341 return err;
342 }
343
756b918d 344 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 345
b6d5ffce
DA		 346 if (p->desc->delay.prepare)
347 msleep(p->desc->delay.prepare);
48834e60 348
613a633e 349 return 0;
87b49717
DA		 350}
351
3235b0f2
DA		 352static int panel_simple_prepare(struct drm_panel *panel)
353{
3235b0f2
DA		 354 int ret;
355
3235b0f2
DA		 356 ret = pm_runtime_get_sync(panel->dev);
357 if (ret < 0) {
358 pm_runtime_put_autosuspend(panel->dev);
359 return ret;
360 }
361
3235b0f2
DA		 362 return 0;
363}
364
613a633e
AK		 365static int panel_simple_enable(struct drm_panel *panel)
366{
367 struct panel_simple *p = to_panel_simple(panel);
368
f673c37e
AK		 369 if (p->desc->delay.enable)
370 msleep(p->desc->delay.enable);
371
280921de
TR		 372 return 0;
373}
374
0ce8ddd8
SR		 375static int panel_simple_get_modes(struct drm_panel *panel,
376 struct drm_connector *connector)
280921de
TR		 377{
378 struct panel_simple *p = to_panel_simple(panel);
379 int num = 0;
380
381 /* probe EDID if a DDC bus is available */
382 if (p->ddc) {
31e25395
DA		 383 pm_runtime_get_sync(panel->dev);
384
e69da902
JN		 385 if (!p->drm_edid)
386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc);
63358e24 387
e69da902
JN		 388 drm_edid_connector_update(connector, p->drm_edid);
389
390 num += drm_edid_connector_add_modes(connector);
31e25395
DA		 391
392 pm_runtime_mark_last_busy(panel->dev);
393 pm_runtime_put_autosuspend(panel->dev);
280921de
TR		 394 }
395
396 /* add hard-coded panel modes */
0ce8ddd8 397 num += panel_simple_get_non_edid_modes(p, connector);
280921de 398
a960e35a
HYW		 399 /*
400 * TODO: Remove once all drm drivers call
401 * drm_connector_set_orientation_from_panel()
402 */
5759c967
DO		 403 drm_connector_set_panel_orientation(connector, p->orientation);
404
280921de
TR		 405 return num;
406}
407
a5d3e625
PZ		 408static int panel_simple_get_timings(struct drm_panel *panel,
409 unsigned int num_timings,
410 struct display_timing *timings)
411{
412 struct panel_simple *p = to_panel_simple(panel);
413 unsigned int i;
414
415 if (p->desc->num_timings < num_timings)
416 num_timings = p->desc->num_timings;
417
418 if (timings)
419 for (i = 0; i < num_timings; i++)
420 timings[i] = p->desc->timings[i];
421
422 return p->desc->num_timings;
423}
424
a960e35a
HYW		 425static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
426{
427 struct panel_simple *p = to_panel_simple(panel);
428
429 return p->orientation;
430}
431
280921de
TR		 432static const struct drm_panel_funcs panel_simple_funcs = {
433 .disable = panel_simple_disable,
c0e1d170
AK		 434 .unprepare = panel_simple_unprepare,
435 .prepare = panel_simple_prepare,
280921de
TR		 436 .enable = panel_simple_enable,
437 .get_modes = panel_simple_get_modes,
a960e35a 438 .get_orientation = panel_simple_get_orientation,
a5d3e625 439 .get_timings = panel_simple_get_timings,
280921de
TR		 440};
441
073667fc 442static struct panel_desc *panel_dpi_probe(struct device *dev)
4a1d0dbc
SR		 443{
444 struct display_timing *timing;
445 const struct device_node *np;
446 struct panel_desc *desc;
447 unsigned int bus_flags;
448 struct videomode vm;
4a1d0dbc
SR		 449 int ret;
450
451 np = dev->of_node;
452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
453 if (!desc)
073667fc 454 return ERR_PTR(-ENOMEM);
4a1d0dbc
SR		 455
456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
457 if (!timing)
073667fc 458 return ERR_PTR(-ENOMEM);
4a1d0dbc
SR		 459
460 ret = of_get_display_timing(np, "panel-timing", timing);
461 if (ret < 0) {
462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
463 np);
073667fc 464 return ERR_PTR(ret);
4a1d0dbc
SR		 465 }
466
467 desc->timings = timing;
468 desc->num_timings = 1;
469
470 of_property_read_u32(np, "width-mm", &desc->size.width);
471 of_property_read_u32(np, "height-mm", &desc->size.height);
472
4a1d0dbc
SR		 473 /* Extract bus_flags from display_timing */
474 bus_flags = 0;
475 vm.flags = timing->flags;
476 drm_bus_flags_from_videomode(&vm, &bus_flags);
477 desc->bus_flags = bus_flags;
478
479 /* We do not know the connector for the DT node, so guess it */
480 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
481
073667fc 482 return desc;
4a1d0dbc
SR		 483}
484
b8a2948f
SP		 485#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
486 (to_check->field.typ >= bounds->field.min && \
487 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 488static void panel_simple_parse_panel_timing_node(struct device *dev,
489 struct panel_simple *panel,
490 const struct display_timing *ot)
b8a2948f
SP		 491{
492 const struct panel_desc *desc = panel->desc;
493 struct videomode vm;
494 unsigned int i;
495
496 if (WARN_ON(desc->num_modes)) {
497 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
498 return;
499 }
500 if (WARN_ON(!desc->num_timings)) {
501 dev_err(dev, "Reject override mode: no timings specified\n");
502 return;
503 }
504
505 for (i = 0; i < panel->desc->num_timings; i++) {
506 const struct display_timing *dt = &panel->desc->timings[i];
507
508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
516 continue;
517
518 if (ot->flags != dt->flags)
519 continue;
520
521 videomode_from_timing(ot, &vm);
522 drm_display_mode_from_videomode(&vm, &panel->override_mode);
523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
524 DRM_MODE_TYPE_PREFERRED;
525 break;
526 }
527
528 if (WARN_ON(!panel->override_mode.type))
529 dev_err(dev, "Reject override mode: No display_timing found\n");
530}
531
1cd3ea3e
JZ		 532static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
533 struct panel_simple *panel)
534{
535 int ret, bpc;
536
537 ret = drm_of_lvds_get_data_mapping(dev->of_node);
538 if (ret < 0) {
539 if (ret == -EINVAL)
540 dev_warn(dev, "Ignore invalid data-mapping property\n");
541
542 /*
543 * Ignore non-existing or malformatted property, fallback to
544 * default data-mapping, and return 0.
545 */
546 return 0;
547 }
548
549 switch (ret) {
550 default:
551 WARN_ON(1);
552 fallthrough;
553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
554 fallthrough;
555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
556 bpc = 8;
557 break;
558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
559 bpc = 6;
560 }
561
562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
563 struct panel_desc *override_desc;
564
565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
566 if (!override_desc)
567 return -ENOMEM;
568
569 override_desc->bus_format = ret;
570 override_desc->bpc = bpc;
571 panel->desc = override_desc;
572 }
573
574 return 0;
575}
576
47c08262
MR		 577static const struct panel_desc *panel_simple_get_desc(struct device *dev)
578{
579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) &&
580 dev_is_mipi_dsi(dev)) {
581 const struct panel_desc_dsi *dsi_desc;
582
583 dsi_desc = of_device_get_match_data(dev);
584 if (!dsi_desc)
585 return ERR_PTR(-ENODEV);
586
587 return &dsi_desc->desc;
588 }
589
590 if (dev_is_platform(dev)) {
591 const struct panel_desc *desc;
592
593 desc = of_device_get_match_data(dev);
f6faebc1
MR		 594 if (!desc) {
595 /*
596 * panel-dpi probes without a descriptor and
597 * panel_dpi_probe() will initialize one for us
598 * based on the device tree.
599 */
600 if (of_device_is_compatible(dev->of_node, "panel-dpi"))
601 return panel_dpi_probe(dev);
602 else
603 return ERR_PTR(-ENODEV);
604 }
47c08262
MR		 605
606 return desc;
607 }
608
609 return ERR_PTR(-ENODEV);
610}
611
612static struct panel_simple *panel_simple_probe(struct device *dev)
280921de 613{
47c08262 614 const struct panel_desc *desc;
280921de 615 struct panel_simple *panel;
b8a2948f 616 struct display_timing dt;
0fe1564b 617 struct device_node *ddc;
9f069c6f 618 int connector_type;
ddb8e853 619 u32 bus_flags;
280921de
TR		 620 int err;
621
47c08262
MR		 622 desc = panel_simple_get_desc(dev);
623 if (IS_ERR(desc))
624 return ERR_CAST(desc);
625
de04bb00
AS		 626 panel = devm_drm_panel_alloc(dev, struct panel_simple, base,
627 &panel_simple_funcs, desc->connector_type);
628 if (IS_ERR(panel))
921c41e5 629 return ERR_CAST(panel);
280921de 630
280921de
TR		 631 panel->desc = desc;
632
633 panel->supply = devm_regulator_get(dev, "power");
634 if (IS_ERR(panel->supply))
921c41e5 635 return ERR_CAST(panel->supply);
280921de 636
a61400d8
AC		 637 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
638 GPIOD_OUT_LOW);
c9b48b91 639 if (IS_ERR(panel->enable_gpio))
921c41e5
MR		 640 return dev_err_cast_probe(dev, panel->enable_gpio,
641 "failed to request GPIO\n");
280921de 642
5759c967
DO		 643 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
644 if (err) {
645 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
921c41e5 646 return ERR_PTR(err);
5759c967
DO		 647 }
648
280921de
TR		 649 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
650 if (ddc) {
651 panel->ddc = of_find_i2c_adapter_by_node(ddc);
652 of_node_put(ddc);
653
0fe1564b 654 if (!panel->ddc)
921c41e5 655 return ERR_PTR(-EPROBE_DEFER);
280921de
TR		 656 }
657
f6faebc1 658 if (!of_device_is_compatible(dev->of_node, "panel-dpi") &&
47c08262
MR		 659 !of_get_display_timing(dev->of_node, "panel-timing", &dt))
660 panel_simple_parse_panel_timing_node(dev, panel, &dt);
b8a2948f 661
1cd3ea3e
JZ		 662 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
663 /* Optional data-mapping property for overriding bus format */
664 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
665 if (err)
666 goto free_ddc;
667 }
668
9f069c6f 669 connector_type = desc->connector_type;
ddb8e853 670 /* Catch common mistakes for panels. */
9f069c6f 671 switch (connector_type) {
ddb8e853
SR		 672 case 0:
673 dev_warn(dev, "Specify missing connector_type\n");
9f069c6f 674 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853
SR		 675 break;
676 case DRM_MODE_CONNECTOR_LVDS:
c4715837
LP		 677 WARN_ON(desc->bus_flags &
678 ~(DRM_BUS_FLAG_DE_LOW |
679 DRM_BUS_FLAG_DE_HIGH |
680 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
681 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
1185c406
LP		 682 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
683 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
684 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
685 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
686 desc->bpc != 6);
687 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
688 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
689 desc->bpc != 8);
ddb8e853
SR		 690 break;
691 case DRM_MODE_CONNECTOR_eDP:
5f04e7ce
DA		 692 dev_warn(dev, "eDP panels moved to panel-edp\n");
693 err = -EINVAL;
694 goto free_ddc;
ddb8e853
SR		 695 case DRM_MODE_CONNECTOR_DSI:
696 if (desc->bpc != 6 && desc->bpc != 8)
697 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
698 break;
699 case DRM_MODE_CONNECTOR_DPI:
700 bus_flags = DRM_BUS_FLAG_DE_LOW |
701 DRM_BUS_FLAG_DE_HIGH |
702 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
703 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
704 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
705 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
706 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
707 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
708 if (desc->bus_flags & ~bus_flags)
709 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
710 if (!(desc->bus_flags & bus_flags))
711 dev_warn(dev, "Specify missing bus_flags\n");
712 if (desc->bus_format == 0)
713 dev_warn(dev, "Specify missing bus_format\n");
714 if (desc->bpc != 6 && desc->bpc != 8)
715 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
716 break;
717 default:
718 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
9f069c6f 719 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853 720 break;
1185c406 721 }
c4715837 722
3235b0f2
DA		 723 dev_set_drvdata(dev, panel);
724
725 /*
726 * We use runtime PM for prepare / unprepare since those power the panel
727 * on and off and those can be very slow operations. This is important
728 * to optimize powering the panel on briefly to read the EDID before
729 * fully enabling the panel.
730 */
731 pm_runtime_enable(dev);
732 pm_runtime_set_autosuspend_delay(dev, 1000);
733 pm_runtime_use_autosuspend(dev);
734
0fe1564b 735 err = drm_panel_of_backlight(&panel->base);
d9e74da2
AS		 736 if (err) {
737 dev_err_probe(dev, err, "Could not find backlight\n");
70e12560 738 goto disable_pm_runtime;
d9e74da2 739 }
0fe1564b 740
c3ee8c65 741 drm_panel_add(&panel->base);
280921de 742
921c41e5 743 return panel;
280921de 744
70e12560 745disable_pm_runtime:
a596fcd9 746 pm_runtime_dont_use_autosuspend(dev);
70e12560 747 pm_runtime_disable(dev);
280921de 748free_ddc:
5f04e7ce 749 if (panel->ddc)
280921de 750 put_device(&panel->ddc->dev);
280921de 751
921c41e5 752 return ERR_PTR(err);
280921de
TR		 753}
754
bc62654d 755static void panel_simple_shutdown(struct device *dev)
280921de
TR		 756{
757 struct panel_simple *panel = dev_get_drvdata(dev);
758
bc62654d
DA		 759 /*
760 * NOTE: the following two calls don't really belong here. It is the
761 * responsibility of a correctly written DRM modeset driver to call
762 * drm_atomic_helper_shutdown() at shutdown time and that should
763 * cause the panel to be disabled / unprepared if needed. For now,
764 * however, we'll keep these calls due to the sheer number of
f00bfaca
DA		 765 * different DRM modeset drivers used with panel-simple. Once we've
766 * confirmed that all DRM modeset drivers using this panel properly
767 * call drm_atomic_helper_shutdown() we can simply delete the two
768 * calls below.
769 *
770 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW
771 * PANEL DRIVERS.
772 *
773 * FIXME: If we're still haven't figured out if all DRM modeset
774 * drivers properly call drm_atomic_helper_shutdown() but we _have_
775 * managed to make sure that DRM modeset drivers get their shutdown()
776 * callback before the panel's shutdown() callback (perhaps using
777 * device link), we could add a WARN_ON here to help move forward.
bc62654d 778 */
f00bfaca
DA		 779 if (panel->base.enabled)
780 drm_panel_disable(&panel->base);
781 if (panel->base.prepared)
782 drm_panel_unprepare(&panel->base);
280921de
TR		 783}
784
bc62654d 785static void panel_simple_remove(struct device *dev)
d02fd93e
TR		 786{
787 struct panel_simple *panel = dev_get_drvdata(dev);
788
bc62654d
DA		 789 drm_panel_remove(&panel->base);
790 panel_simple_shutdown(dev);
791
792 pm_runtime_dont_use_autosuspend(dev);
793 pm_runtime_disable(dev);
794 if (panel->ddc)
795 put_device(&panel->ddc->dev);
d02fd93e
TR		 796}
797
bca684e6
JT		 798static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
799 .clock = 71100,
800 .hdisplay = 1280,
801 .hsync_start = 1280 + 40,
802 .hsync_end = 1280 + 40 + 80,
803 .htotal = 1280 + 40 + 80 + 40,
804 .vdisplay = 800,
805 .vsync_start = 800 + 3,
806 .vsync_end = 800 + 3 + 10,
807 .vtotal = 800 + 3 + 10 + 10,
808 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
809};
810
811static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
812 .modes = &ampire_am_1280800n3tzqw_t00h_mode,
813 .num_modes = 1,
7eafbecd 814 .bpc = 8,
bca684e6
JT		 815 .size = {
816 .width = 217,
817 .height = 136,
818 },
819 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
821 .connector_type = DRM_MODE_CONNECTOR_LVDS,
822};
823
966fea78
YF		 824static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
825 .clock = 9000,
826 .hdisplay = 480,
827 .hsync_start = 480 + 2,
828 .hsync_end = 480 + 2 + 41,
829 .htotal = 480 + 2 + 41 + 2,
830 .vdisplay = 272,
831 .vsync_start = 272 + 2,
832 .vsync_end = 272 + 2 + 10,
833 .vtotal = 272 + 2 + 10 + 2,
966fea78
YF		 834 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
835};
836
837static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
838 .modes = &ampire_am_480272h3tmqw_t01h_mode,
839 .num_modes = 1,
840 .bpc = 8,
841 .size = {
f24b4955
DB		 842 .width = 99,
843 .height = 58,
966fea78
YF		 844 },
845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
846};
847
1c550fa1
PZ		 848static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
849 .clock = 33333,
850 .hdisplay = 800,
851 .hsync_start = 800 + 0,
852 .hsync_end = 800 + 0 + 255,
853 .htotal = 800 + 0 + 255 + 0,
854 .vdisplay = 480,
855 .vsync_start = 480 + 2,
856 .vsync_end = 480 + 2 + 45,
857 .vtotal = 480 + 2 + 45 + 0,
1c550fa1
PZ		 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
859};
860
410bb213
GU		 861static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
862 .pixelclock = { 29930000, 33260000, 36590000 },
863 .hactive = { 800, 800, 800 },
864 .hfront_porch = { 1, 40, 168 },
865 .hback_porch = { 88, 88, 88 },
866 .hsync_len = { 1, 128, 128 },
867 .vactive = { 480, 480, 480 },
868 .vfront_porch = { 1, 35, 37 },
869 .vback_porch = { 8, 8, 8 },
870 .vsync_len = { 1, 2, 2 },
871 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
872 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
873 DISPLAY_FLAGS_SYNC_POSEDGE,
874};
875
876static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
877 .timings = &ampire_am_800480l1tmqw_t00h_timing,
878 .num_timings = 1,
879 .bpc = 8,
880 .size = {
881 .width = 111,
882 .height = 67,
883 },
884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
885 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
886 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
887 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
888 .connector_type = DRM_MODE_CONNECTOR_DPI,
889};
890
1c550fa1
PZ		 891static const struct panel_desc ampire_am800480r3tmqwa1h = {
892 .modes = &ampire_am800480r3tmqwa1h_mode,
893 .num_modes = 1,
894 .bpc = 6,
895 .size = {
896 .width = 152,
897 .height = 91,
898 },
899 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
900};
901
103f06fd
BK		 902static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
903 .pixelclock = { 34500000, 39600000, 50400000 },
904 .hactive = { 800, 800, 800 },
905 .hfront_porch = { 12, 112, 312 },
906 .hback_porch = { 87, 87, 48 },
907 .hsync_len = { 1, 1, 40 },
908 .vactive = { 600, 600, 600 },
909 .vfront_porch = { 1, 21, 61 },
910 .vback_porch = { 38, 38, 19 },
911 .vsync_len = { 1, 1, 20 },
912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
914 DISPLAY_FLAGS_SYNC_POSEDGE,
915};
916
917static const struct panel_desc ampire_am800600p5tmqwtb8h = {
918 .timings = &ampire_am800600p5tmqw_tb8h_timing,
919 .num_timings = 1,
920 .bpc = 6,
921 .size = {
922 .width = 162,
923 .height = 122,
924 },
925 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
926 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
927 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
928 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
929 .connector_type = DRM_MODE_CONNECTOR_DPI,
930};
931
c479450f
SS		 932static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
933 .pixelclock = { 26400000, 33300000, 46800000 },
934 .hactive = { 800, 800, 800 },
935 .hfront_porch = { 16, 210, 354 },
936 .hback_porch = { 45, 36, 6 },
937 .hsync_len = { 1, 10, 40 },
938 .vactive = { 480, 480, 480 },
939 .vfront_porch = { 7, 22, 147 },
940 .vback_porch = { 22, 13, 3 },
941 .vsync_len = { 1, 10, 20 },
942 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
943 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
944};
945
946static const struct panel_desc armadeus_st0700_adapt = {
947 .timings = &santek_st0700i5y_rbslw_f_timing,
948 .num_timings = 1,
949 .bpc = 6,
950 .size = {
951 .width = 154,
952 .height = 86,
953 },
954 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
c479450f
SS		 956};
957
280921de
TR		 958static const struct drm_display_mode auo_b101aw03_mode = {
959 .clock = 51450,
960 .hdisplay = 1024,
961 .hsync_start = 1024 + 156,
962 .hsync_end = 1024 + 156 + 8,
963 .htotal = 1024 + 156 + 8 + 156,
964 .vdisplay = 600,
965 .vsync_start = 600 + 16,
966 .vsync_end = 600 + 16 + 6,
967 .vtotal = 600 + 16 + 6 + 16,
280921de
TR		 968};
969
970static const struct panel_desc auo_b101aw03 = {
971 .modes = &auo_b101aw03_mode,
972 .num_modes = 1,
0208d511 973 .bpc = 6,
280921de
TR		 974 .size = {
975 .width = 223,
976 .height = 125,
977 },
85560829 978 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 979 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 980 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 981};
982
dac746e0
RC		 983static const struct drm_display_mode auo_b101xtn01_mode = {
984 .clock = 72000,
985 .hdisplay = 1366,
986 .hsync_start = 1366 + 20,
987 .hsync_end = 1366 + 20 + 70,
988 .htotal = 1366 + 20 + 70,
989 .vdisplay = 768,
990 .vsync_start = 768 + 14,
991 .vsync_end = 768 + 14 + 42,
992 .vtotal = 768 + 14 + 42,
dac746e0
RC		 993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
994};
995
996static const struct panel_desc auo_b101xtn01 = {
997 .modes = &auo_b101xtn01_mode,
998 .num_modes = 1,
999 .bpc = 6,
1000 .size = {
1001 .width = 223,
1002 .height = 125,
1003 },
1004};
1005
ad3e33fe
DA		 1006static const struct drm_display_mode auo_b116xw03_mode = {
1007 .clock = 70589,
1008 .hdisplay = 1366,
1009 .hsync_start = 1366 + 40,
1010 .hsync_end = 1366 + 40 + 40,
1011 .htotal = 1366 + 40 + 40 + 32,
1012 .vdisplay = 768,
1013 .vsync_start = 768 + 10,
1014 .vsync_end = 768 + 10 + 12,
1015 .vtotal = 768 + 10 + 12 + 6,
1016 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1017};
1018
1019static const struct panel_desc auo_b116xw03 = {
1020 .modes = &auo_b116xw03_mode,
1021 .num_modes = 1,
1022 .bpc = 6,
1023 .size = {
1024 .width = 256,
1025 .height = 144,
1026 },
1027 .delay = {
1028 .prepare = 1,
1029 .enable = 200,
1030 .disable = 200,
1031 .unprepare = 500,
1032 },
1033 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1034 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1035 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1036};
1037
bccfaffb
LM		 1038static const struct display_timing auo_g070vvn01_timings = {
1039 .pixelclock = { 33300000, 34209000, 45000000 },
1040 .hactive = { 800, 800, 800 },
1041 .hfront_porch = { 20, 40, 200 },
1042 .hback_porch = { 87, 40, 1 },
1043 .hsync_len = { 1, 48, 87 },
1044 .vactive = { 480, 480, 480 },
1045 .vfront_porch = { 5, 13, 200 },
1046 .vback_porch = { 31, 31, 29 },
1047 .vsync_len = { 1, 1, 3 },
1048};
1049
1050static const struct panel_desc auo_g070vvn01 = {
1051 .timings = &auo_g070vvn01_timings,
1052 .num_timings = 1,
1053 .bpc = 8,
1054 .size = {
1055 .width = 152,
1056 .height = 91,
1057 },
1058 .delay = {
1059 .prepare = 200,
1060 .enable = 50,
1061 .disable = 50,
1062 .unprepare = 1000,
1063 },
1064};
1065
d5d283d4
KB		 1066static const struct display_timing auo_g101evn010_timing = {
1067 .pixelclock = { 64000000, 68930000, 85000000 },
1068 .hactive = { 1280, 1280, 1280 },
1069 .hfront_porch = { 8, 64, 256 },
1070 .hback_porch = { 8, 64, 256 },
1071 .hsync_len = { 40, 168, 767 },
1072 .vactive = { 800, 800, 800 },
1073 .vfront_porch = { 4, 8, 100 },
1074 .vback_porch = { 4, 8, 100 },
1075 .vsync_len = { 8, 16, 223 },
4fb86404
AG		 1076};
1077
1078static const struct panel_desc auo_g101evn010 = {
d5d283d4
KB		 1079 .timings = &auo_g101evn010_timing,
1080 .num_timings = 1,
4fb86404
AG		 1081 .bpc = 6,
1082 .size = {
1083 .width = 216,
1084 .height = 135,
1085 },
27a46fb7 1086 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
d5d283d4 1087 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
27a46fb7 1088 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4fb86404
AG		 1089};
1090
4451c287
CF		 1091static const struct drm_display_mode auo_g104sn02_mode = {
1092 .clock = 40000,
1093 .hdisplay = 800,
1094 .hsync_start = 800 + 40,
1095 .hsync_end = 800 + 40 + 216,
1096 .htotal = 800 + 40 + 216 + 128,
1097 .vdisplay = 600,
1098 .vsync_start = 600 + 10,
1099 .vsync_end = 600 + 10 + 35,
1100 .vtotal = 600 + 10 + 35 + 2,
4451c287
CF		 1101};
1102
1103static const struct panel_desc auo_g104sn02 = {
1104 .modes = &auo_g104sn02_mode,
1105 .num_modes = 1,
1106 .bpc = 8,
1107 .size = {
1108 .width = 211,
1109 .height = 158,
1110 },
a3050f23
SR		 1111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1112 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4451c287
CF		 1113};
1114
6c2b2cd3
PG		 1115static const struct drm_display_mode auo_g104stn01_mode = {
1116 .clock = 40000,
1117 .hdisplay = 800,
1118 .hsync_start = 800 + 40,
1119 .hsync_end = 800 + 40 + 88,
1120 .htotal = 800 + 40 + 88 + 128,
1121 .vdisplay = 600,
1122 .vsync_start = 600 + 1,
1123 .vsync_end = 600 + 1 + 23,
1124 .vtotal = 600 + 1 + 23 + 4,
1125};
1126
1127static const struct panel_desc auo_g104stn01 = {
1128 .modes = &auo_g104stn01_mode,
1129 .num_modes = 1,
1130 .bpc = 8,
1131 .size = {
1132 .width = 211,
1133 .height = 158,
1134 },
1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1136 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1137};
1138
e8470c0a
LC		 1139static const struct display_timing auo_g121ean01_timing = {
1140 .pixelclock = { 60000000, 74400000, 90000000 },
1141 .hactive = { 1280, 1280, 1280 },
1142 .hfront_porch = { 20, 50, 100 },
1143 .hback_porch = { 20, 50, 100 },
1144 .hsync_len = { 30, 100, 200 },
1145 .vactive = { 800, 800, 800 },
1146 .vfront_porch = { 2, 10, 25 },
1147 .vback_porch = { 2, 10, 25 },
1148 .vsync_len = { 4, 18, 50 },
03e909ac
SR		 1149};
1150
1151static const struct panel_desc auo_g121ean01 = {
e8470c0a
LC		 1152 .timings = &auo_g121ean01_timing,
1153 .num_timings = 1,
03e909ac
SR		 1154 .bpc = 8,
1155 .size = {
1156 .width = 261,
1157 .height = 163,
1158 },
1159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1160 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1161};
1162
697035c6
LS		 1163static const struct display_timing auo_g133han01_timings = {
1164 .pixelclock = { 134000000, 141200000, 149000000 },
1165 .hactive = { 1920, 1920, 1920 },
1166 .hfront_porch = { 39, 58, 77 },
1167 .hback_porch = { 59, 88, 117 },
1168 .hsync_len = { 28, 42, 56 },
1169 .vactive = { 1080, 1080, 1080 },
1170 .vfront_porch = { 3, 8, 11 },
1171 .vback_porch = { 5, 14, 19 },
1172 .vsync_len = { 4, 14, 19 },
1173};
1174
1175static const struct panel_desc auo_g133han01 = {
1176 .timings = &auo_g133han01_timings,
1177 .num_timings = 1,
1178 .bpc = 8,
1179 .size = {
1180 .width = 293,
1181 .height = 165,
1182 },
1183 .delay = {
1184 .prepare = 200,
1185 .enable = 50,
1186 .disable = 50,
1187 .unprepare = 1000,
1188 },
1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 1191};
1192
9e52d5c8
EA		 1193static const struct display_timing auo_g156han04_timings = {
1194 .pixelclock = { 137000000, 141000000, 146000000 },
1195 .hactive = { 1920, 1920, 1920 },
1196 .hfront_porch = { 60, 60, 60 },
1197 .hback_porch = { 90, 92, 111 },
1198 .hsync_len = { 32, 32, 32 },
1199 .vactive = { 1080, 1080, 1080 },
1200 .vfront_porch = { 12, 12, 12 },
1201 .vback_porch = { 24, 36, 56 },
1202 .vsync_len = { 8, 8, 8 },
1203};
1204
1205static const struct panel_desc auo_g156han04 = {
1206 .timings = &auo_g156han04_timings,
1207 .num_timings = 1,
1208 .bpc = 8,
1209 .size = {
1210 .width = 344,
1211 .height = 194,
1212 },
1213 .delay = {
1214 .prepare = 50, /* T2 */
1215 .enable = 200, /* T3 */
1216 .disable = 110, /* T10 */
1217 .unprepare = 1000, /* T13 */
1218 },
1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1220 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1221 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1222};
1223
d9ccd1f2
SR		 1224static const struct drm_display_mode auo_g156xtn01_mode = {
1225 .clock = 76000,
1226 .hdisplay = 1366,
1227 .hsync_start = 1366 + 33,
1228 .hsync_end = 1366 + 33 + 67,
1229 .htotal = 1560,
1230 .vdisplay = 768,
1231 .vsync_start = 768 + 4,
1232 .vsync_end = 768 + 4 + 4,
1233 .vtotal = 806,
d9ccd1f2
SR		 1234};
1235
1236static const struct panel_desc auo_g156xtn01 = {
1237 .modes = &auo_g156xtn01_mode,
1238 .num_modes = 1,
1239 .bpc = 8,
1240 .size = {
1241 .width = 344,
1242 .height = 194,
1243 },
1244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1245 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1246};
1247
8c31f603
LS		 1248static const struct display_timing auo_g185han01_timings = {
1249 .pixelclock = { 120000000, 144000000, 175000000 },
1250 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 1251 .hfront_porch = { 36, 120, 148 },
1252 .hback_porch = { 24, 88, 108 },
1253 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 1254 .vactive = { 1080, 1080, 1080 },
1255 .vfront_porch = { 6, 10, 40 },
1256 .vback_porch = { 2, 5, 20 },
1257 .vsync_len = { 2, 5, 20 },
1258};
1259
1260static const struct panel_desc auo_g185han01 = {
1261 .timings = &auo_g185han01_timings,
1262 .num_timings = 1,
1263 .bpc = 8,
1264 .size = {
1265 .width = 409,
1266 .height = 230,
1267 },
1268 .delay = {
1269 .prepare = 50,
1270 .enable = 200,
1271 .disable = 110,
1272 .unprepare = 1000,
1273 },
1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 1276};
1277
2f7b832f
SR		 1278static const struct display_timing auo_g190ean01_timings = {
1279 .pixelclock = { 90000000, 108000000, 135000000 },
1280 .hactive = { 1280, 1280, 1280 },
1281 .hfront_porch = { 126, 184, 1266 },
1282 .hback_porch = { 84, 122, 844 },
1283 .hsync_len = { 70, 102, 704 },
1284 .vactive = { 1024, 1024, 1024 },
1285 .vfront_porch = { 4, 26, 76 },
1286 .vback_porch = { 2, 8, 25 },
1287 .vsync_len = { 2, 8, 25 },
1288};
1289
1290static const struct panel_desc auo_g190ean01 = {
1291 .timings = &auo_g190ean01_timings,
1292 .num_timings = 1,
1293 .bpc = 8,
1294 .size = {
1295 .width = 376,
1296 .height = 301,
1297 },
1298 .delay = {
1299 .prepare = 50,
1300 .enable = 200,
1301 .disable = 110,
1302 .unprepare = 1000,
1303 },
1304 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1305 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1306};
1307
8a45632e
MW		 1308static const struct display_timing auo_p238han01_timings = {
1309 .pixelclock = { 107400000, 142400000, 180000000 },
1310 .hactive = { 1920, 1920, 1920 },
1311 .hfront_porch = { 30, 70, 650 },
1312 .hback_porch = { 30, 70, 650 },
1313 .hsync_len = { 20, 40, 136 },
1314 .vactive = { 1080, 1080, 1080 },
1315 .vfront_porch = { 5, 19, 318 },
1316 .vback_porch = { 5, 19, 318 },
1317 .vsync_len = { 4, 12, 120 },
1318};
1319
1320static const struct panel_desc auo_p238han01 = {
1321 .timings = &auo_p238han01_timings,
1322 .num_timings = 1,
1323 .bpc = 8,
1324 .size = {
1325 .width = 527,
1326 .height = 296,
1327 },
1328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1329 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1330};
1331
70c0d5b7
LS		 1332static const struct display_timing auo_p320hvn03_timings = {
1333 .pixelclock = { 106000000, 148500000, 164000000 },
1334 .hactive = { 1920, 1920, 1920 },
1335 .hfront_porch = { 25, 50, 130 },
1336 .hback_porch = { 25, 50, 130 },
1337 .hsync_len = { 20, 40, 105 },
1338 .vactive = { 1080, 1080, 1080 },
1339 .vfront_porch = { 8, 17, 150 },
1340 .vback_porch = { 8, 17, 150 },
1341 .vsync_len = { 4, 11, 100 },
1342};
1343
1344static const struct panel_desc auo_p320hvn03 = {
1345 .timings = &auo_p320hvn03_timings,
1346 .num_timings = 1,
1347 .bpc = 8,
1348 .size = {
1349 .width = 698,
1350 .height = 393,
1351 },
1352 .delay = {
1353 .prepare = 1,
1354 .enable = 450,
1355 .unprepare = 500,
1356 },
2554f154 1357 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1358 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 1359};
1360
7ee933a1
HS		 1361static const struct drm_display_mode auo_t215hvn01_mode = {
1362 .clock = 148800,
1363 .hdisplay = 1920,
1364 .hsync_start = 1920 + 88,
1365 .hsync_end = 1920 + 88 + 44,
1366 .htotal = 1920 + 88 + 44 + 148,
1367 .vdisplay = 1080,
1368 .vsync_start = 1080 + 4,
1369 .vsync_end = 1080 + 4 + 5,
1370 .vtotal = 1080 + 4 + 5 + 36,
7ee933a1
HS		 1371};
1372
1373static const struct panel_desc auo_t215hvn01 = {
1374 .modes = &auo_t215hvn01_mode,
1375 .num_modes = 1,
1376 .bpc = 8,
1377 .size = {
1378 .width = 430,
1379 .height = 270,
1380 },
1381 .delay = {
1382 .disable = 5,
1383 .unprepare = 1000,
7a675a8f
MV		 1384 },
1385 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1386 .connector_type = DRM_MODE_CONNECTOR_LVDS,
7ee933a1
HS		 1387};
1388
d47df633
PZ		 1389static const struct drm_display_mode avic_tm070ddh03_mode = {
1390 .clock = 51200,
1391 .hdisplay = 1024,
1392 .hsync_start = 1024 + 160,
1393 .hsync_end = 1024 + 160 + 4,
1394 .htotal = 1024 + 160 + 4 + 156,
1395 .vdisplay = 600,
1396 .vsync_start = 600 + 17,
1397 .vsync_end = 600 + 17 + 1,
1398 .vtotal = 600 + 17 + 1 + 17,
d47df633
PZ		 1399};
1400
1401static const struct panel_desc avic_tm070ddh03 = {
1402 .modes = &avic_tm070ddh03_mode,
1403 .num_modes = 1,
1404 .bpc = 8,
1405 .size = {
1406 .width = 154,
1407 .height = 90,
1408 },
1409 .delay = {
1410 .prepare = 20,
1411 .enable = 200,
1412 .disable = 200,
1413 },
1414};
1415
7ad8b41c
CYT		 1416static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1417 .clock = 30000,
1418 .hdisplay = 800,
1419 .hsync_start = 800 + 40,
1420 .hsync_end = 800 + 40 + 48,
1421 .htotal = 800 + 40 + 48 + 40,
1422 .vdisplay = 480,
1423 .vsync_start = 480 + 13,
1424 .vsync_end = 480 + 13 + 3,
1425 .vtotal = 480 + 13 + 3 + 29,
1426};
1427
1428static const struct panel_desc bananapi_s070wv20_ct16 = {
1429 .modes = &bananapi_s070wv20_ct16_mode,
1430 .num_modes = 1,
1431 .bpc = 6,
1432 .size = {
1433 .width = 154,
1434 .height = 86,
1435 },
1436};
1437
b554c009
MS		 1438static const struct display_timing boe_av101hdt_a10_timing = {
1439 .pixelclock = { 74210000, 75330000, 76780000, },
1440 .hactive = { 1280, 1280, 1280, },
1441 .hfront_porch = { 10, 42, 33, },
1442 .hback_porch = { 10, 18, 33, },
1443 .hsync_len = { 30, 10, 30, },
1444 .vactive = { 720, 720, 720, },
1445 .vfront_porch = { 200, 183, 200, },
1446 .vback_porch = { 8, 8, 8, },
1447 .vsync_len = { 2, 19, 2, },
1448 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1449};
1450
1451static const struct panel_desc boe_av101hdt_a10 = {
1452 .timings = &boe_av101hdt_a10_timing,
1453 .num_timings = 1,
1454 .bpc = 8,
1455 .size = {
1456 .width = 224,
1457 .height = 126,
1458 },
1459 .delay = {
1460 .enable = 50,
1461 .disable = 50,
1462 },
1463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1464 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1465};
1466
d34bd3c7
MS		 1467static const struct display_timing boe_av123z7m_n17_timing = {
1468 .pixelclock = { 86600000, 88000000, 90800000, },
1469 .hactive = { 1920, 1920, 1920, },
1470 .hfront_porch = { 10, 10, 10, },
1471 .hback_porch = { 10, 10, 10, },
1472 .hsync_len = { 9, 12, 25, },
1473 .vactive = { 720, 720, 720, },
1474 .vfront_porch = { 7, 10, 13, },
1475 .vback_porch = { 7, 10, 13, },
1476 .vsync_len = { 7, 11, 14, },
1477 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1478};
1479
1480static const struct panel_desc boe_av123z7m_n17 = {
1481 .timings = &boe_av123z7m_n17_timing,
1482 .bpc = 8,
1483 .num_timings = 1,
1484 .size = {
1485 .width = 292,
1486 .height = 110,
1487 },
1488 .delay = {
1489 .prepare = 50,
1490 .disable = 50,
1491 },
1492 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1493 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1494};
1495
eeaddab4
TL		 1496static const struct drm_display_mode boe_bp101wx1_100_mode = {
1497 .clock = 78945,
1498 .hdisplay = 1280,
1499 .hsync_start = 1280 + 0,
1500 .hsync_end = 1280 + 0 + 2,
1501 .htotal = 1280 + 62 + 0 + 2,
1502 .vdisplay = 800,
1503 .vsync_start = 800 + 8,
1504 .vsync_end = 800 + 8 + 2,
1505 .vtotal = 800 + 6 + 8 + 2,
1506};
1507
dc90214f
TL		 1508static const struct panel_desc boe_bp082wx1_100 = {
1509 .modes = &boe_bp101wx1_100_mode,
1510 .num_modes = 1,
1511 .bpc = 8,
1512 .size = {
1513 .width = 177,
1514 .height = 110,
1515 },
1516 .delay = {
1517 .enable = 50,
1518 .disable = 50,
1519 },
1520 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1521 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1522 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1523};
1524
eeaddab4
TL		 1525static const struct panel_desc boe_bp101wx1_100 = {
1526 .modes = &boe_bp101wx1_100_mode,
1527 .num_modes = 1,
1528 .bpc = 8,
1529 .size = {
1530 .width = 217,
1531 .height = 136,
1532 },
1533 .delay = {
1534 .enable = 50,
1535 .disable = 50,
1536 },
1537 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1538 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1539 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1540};
1541
8bb7c7bc
LY		 1542static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1543 .pixelclock = { 69922000, 71000000, 72293000 },
1544 .hactive = { 1280, 1280, 1280 },
1545 .hfront_porch = { 48, 48, 48 },
1546 .hback_porch = { 80, 80, 80 },
1547 .hsync_len = { 32, 32, 32 },
1548 .vactive = { 800, 800, 800 },
1549 .vfront_porch = { 3, 3, 3 },
1550 .vback_porch = { 14, 14, 14 },
1551 .vsync_len = { 6, 6, 6 },
1552};
1553
1554static const struct panel_desc boe_ev121wxm_n10_1850 = {
1555 .timings = &boe_ev121wxm_n10_1850_timing,
1556 .num_timings = 1,
1557 .bpc = 8,
1558 .size = {
1559 .width = 261,
1560 .height = 163,
1561 },
1562 .delay = {
1563 .prepare = 9,
1564 .enable = 300,
1565 .unprepare = 300,
1566 .disable = 560,
1567 },
1568 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1569 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1570 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1571};
1572
ae8cf41b 1573static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 1574 .clock = 42105,
ae8cf41b 1575 .hdisplay = 1024,
e077e2f5
AH		 1576 .hsync_start = 1024 + 30,
1577 .hsync_end = 1024 + 30 + 30,
1578 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 1579 .vdisplay = 600,
e077e2f5
AH		 1580 .vsync_start = 600 + 10,
1581 .vsync_end = 600 + 10 + 10,
1582 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 1583};
1584
1585static const struct panel_desc boe_hv070wsa = {
1586 .modes = &boe_hv070wsa_mode,
1587 .num_modes = 1,
2a5c2ff5 1588 .bpc = 8,
ae8cf41b
AH		 1589 .size = {
1590 .width = 154,
1591 .height = 90,
1592 },
2a5c2ff5
SR		 1593 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1594 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1595 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ae8cf41b
AH		 1596};
1597
751b5841
JD		 1598static const struct display_timing cct_cmt430b19n00_timing = {
1599 .pixelclock = { 8000000, 9000000, 12000000 },
1600 .hactive = { 480, 480, 480 },
1601 .hfront_porch = { 2, 8, 75 },
1602 .hback_porch = { 3, 43, 43 },
1603 .hsync_len = { 2, 4, 75 },
1604 .vactive = { 272, 272, 272 },
1605 .vfront_porch = { 2, 8, 37 },
1606 .vback_porch = { 2, 12, 12 },
1607 .vsync_len = { 2, 4, 37 },
1608 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW
1609};
1610
1611static const struct panel_desc cct_cmt430b19n00 = {
1612 .timings = &cct_cmt430b19n00_timing,
1613 .num_timings = 1,
1614 .bpc = 8,
1615 .size = {
1616 .width = 95,
1617 .height = 53,
1618 },
1619 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1620 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1621 .connector_type = DRM_MODE_CONNECTOR_DPI,
1622};
1623
e58edce6
GB		 1624static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1625 .clock = 9000,
1626 .hdisplay = 480,
1627 .hsync_start = 480 + 5,
1628 .hsync_end = 480 + 5 + 5,
1629 .htotal = 480 + 5 + 5 + 40,
1630 .vdisplay = 272,
1631 .vsync_start = 272 + 8,
1632 .vsync_end = 272 + 8 + 8,
1633 .vtotal = 272 + 8 + 8 + 8,
e58edce6
GB		 1634 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1635};
1636
1637static const struct panel_desc cdtech_s043wq26h_ct7 = {
1638 .modes = &cdtech_s043wq26h_ct7_mode,
1639 .num_modes = 1,
1640 .bpc = 8,
1641 .size = {
1642 .width = 95,
1643 .height = 54,
1644 },
88bc4178 1645 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1646};
1647
0e3b67f6
MK		 1648/* S070PWS19HP-FC21 2017/04/22 */
1649static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1650 .clock = 51200,
1651 .hdisplay = 1024,
1652 .hsync_start = 1024 + 160,
1653 .hsync_end = 1024 + 160 + 20,
1654 .htotal = 1024 + 160 + 20 + 140,
1655 .vdisplay = 600,
1656 .vsync_start = 600 + 12,
1657 .vsync_end = 600 + 12 + 3,
1658 .vtotal = 600 + 12 + 3 + 20,
1659 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1660};
1661
1662static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1663 .modes = &cdtech_s070pws19hp_fc21_mode,
1664 .num_modes = 1,
1665 .bpc = 6,
1666 .size = {
1667 .width = 154,
1668 .height = 86,
1669 },
1670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1672 .connector_type = DRM_MODE_CONNECTOR_DPI,
1673};
1674
1675/* S070SWV29HG-DC44 2017/09/21 */
1676static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1677 .clock = 33300,
1678 .hdisplay = 800,
1679 .hsync_start = 800 + 210,
1680 .hsync_end = 800 + 210 + 2,
1681 .htotal = 800 + 210 + 2 + 44,
1682 .vdisplay = 480,
1683 .vsync_start = 480 + 22,
1684 .vsync_end = 480 + 22 + 2,
1685 .vtotal = 480 + 22 + 2 + 21,
1686 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1687};
1688
1689static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1690 .modes = &cdtech_s070swv29hg_dc44_mode,
1691 .num_modes = 1,
1692 .bpc = 6,
1693 .size = {
1694 .width = 154,
1695 .height = 86,
1696 },
1697 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1699 .connector_type = DRM_MODE_CONNECTOR_DPI,
1700};
1701
982f944e
GB		 1702static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1703 .clock = 35000,
1704 .hdisplay = 800,
1705 .hsync_start = 800 + 40,
1706 .hsync_end = 800 + 40 + 40,
1707 .htotal = 800 + 40 + 40 + 48,
1708 .vdisplay = 480,
1709 .vsync_start = 480 + 29,
1710 .vsync_end = 480 + 29 + 13,
1711 .vtotal = 480 + 29 + 13 + 3,
982f944e
GB		 1712 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1713};
1714
1715static const struct panel_desc cdtech_s070wv95_ct16 = {
1716 .modes = &cdtech_s070wv95_ct16_mode,
1717 .num_modes = 1,
1718 .bpc = 8,
1719 .size = {
1720 .width = 154,
1721 .height = 85,
1722 },
1723};
1724
07c913c4
MV		 1725static const struct display_timing chefree_ch101olhlwh_002_timing = {
1726 .pixelclock = { 68900000, 71100000, 73400000 },
1727 .hactive = { 1280, 1280, 1280 },
1728 .hfront_porch = { 65, 80, 95 },
1729 .hback_porch = { 64, 79, 94 },
1730 .hsync_len = { 1, 1, 1 },
1731 .vactive = { 800, 800, 800 },
1732 .vfront_porch = { 7, 11, 14 },
1733 .vback_porch = { 7, 11, 14 },
1734 .vsync_len = { 1, 1, 1 },
1735 .flags = DISPLAY_FLAGS_DE_HIGH,
1736};
1737
1738static const struct panel_desc chefree_ch101olhlwh_002 = {
1739 .timings = &chefree_ch101olhlwh_002_timing,
1740 .num_timings = 1,
1741 .bpc = 8,
1742 .size = {
1743 .width = 217,
1744 .height = 135,
1745 },
1746 .delay = {
1747 .enable = 200,
1748 .disable = 200,
1749 },
1750 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1751 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1752 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1753};
1754
2cb35c80
RL		 1755static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1756 .clock = 66770,
1757 .hdisplay = 800,
1758 .hsync_start = 800 + 49,
1759 .hsync_end = 800 + 49 + 33,
1760 .htotal = 800 + 49 + 33 + 17,
1761 .vdisplay = 1280,
1762 .vsync_start = 1280 + 1,
1763 .vsync_end = 1280 + 1 + 7,
1764 .vtotal = 1280 + 1 + 7 + 15,
2cb35c80
RL		 1765 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1766};
1767
1768static const struct panel_desc chunghwa_claa070wp03xg = {
1769 .modes = &chunghwa_claa070wp03xg_mode,
1770 .num_modes = 1,
1771 .bpc = 6,
1772 .size = {
1773 .width = 94,
1774 .height = 150,
1775 },
85560829 1776 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1777 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2cb35c80
RL		 1779};
1780
4c930757
SW		 1781static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1782 .clock = 72070,
1783 .hdisplay = 1366,
1784 .hsync_start = 1366 + 58,
1785 .hsync_end = 1366 + 58 + 58,
1786 .htotal = 1366 + 58 + 58 + 58,
1787 .vdisplay = 768,
1788 .vsync_start = 768 + 4,
1789 .vsync_end = 768 + 4 + 4,
1790 .vtotal = 768 + 4 + 4 + 4,
4c930757
SW		 1791};
1792
1793static const struct panel_desc chunghwa_claa101wa01a = {
1794 .modes = &chunghwa_claa101wa01a_mode,
1795 .num_modes = 1,
0208d511 1796 .bpc = 6,
4c930757
SW		 1797 .size = {
1798 .width = 220,
1799 .height = 120,
1800 },
85560829 1801 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1802 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1803 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4c930757
SW		 1804};
1805
280921de
TR		 1806static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1807 .clock = 69300,
1808 .hdisplay = 1366,
1809 .hsync_start = 1366 + 48,
1810 .hsync_end = 1366 + 48 + 32,
1811 .htotal = 1366 + 48 + 32 + 20,
1812 .vdisplay = 768,
1813 .vsync_start = 768 + 16,
1814 .vsync_end = 768 + 16 + 8,
1815 .vtotal = 768 + 16 + 8 + 16,
280921de
TR		 1816};
1817
1818static const struct panel_desc chunghwa_claa101wb01 = {
1819 .modes = &chunghwa_claa101wb01_mode,
1820 .num_modes = 1,
0208d511 1821 .bpc = 6,
280921de
TR		 1822 .size = {
1823 .width = 223,
1824 .height = 125,
1825 },
85560829 1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1828 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 1829};
1830
4dd024d4
MV		 1831static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1832 .pixelclock = { 5000000, 9000000, 12000000 },
1833 .hactive = { 480, 480, 480 },
1834 .hfront_porch = { 12, 12, 12 },
1835 .hback_porch = { 12, 12, 12 },
1836 .hsync_len = { 21, 21, 21 },
1837 .vactive = { 272, 272, 272 },
1838 .vfront_porch = { 4, 4, 4 },
1839 .vback_porch = { 4, 4, 4 },
1840 .vsync_len = { 8, 8, 8 },
1841};
1842
1843static const struct panel_desc dataimage_fg040346dsswbg04 = {
1844 .timings = &dataimage_fg040346dsswbg04_timing,
1845 .num_timings = 1,
1846 .bpc = 8,
1847 .size = {
1848 .width = 95,
1849 .height = 54,
1850 },
1851 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1852 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1853 .connector_type = DRM_MODE_CONNECTOR_DPI,
1854};
1855
803481d8
PO		 1856static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1857 .pixelclock = { 68900000, 71110000, 73400000 },
1858 .hactive = { 1280, 1280, 1280 },
1859 .vactive = { 800, 800, 800 },
1860 .hback_porch = { 100, 100, 100 },
1861 .hfront_porch = { 100, 100, 100 },
1862 .vback_porch = { 5, 5, 5 },
1863 .vfront_porch = { 5, 5, 5 },
1864 .hsync_len = { 24, 24, 24 },
1865 .vsync_len = { 3, 3, 3 },
1866 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1867 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1868};
1869
1870static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1871 .timings = &dataimage_fg1001l0dsswmg01_timing,
1872 .num_timings = 1,
1873 .bpc = 8,
1874 .size = {
1875 .width = 217,
1876 .height = 136,
1877 },
1878};
1879
97ceb1fb
MV		 1880static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1881 .clock = 33260,
1882 .hdisplay = 800,
1883 .hsync_start = 800 + 40,
1884 .hsync_end = 800 + 40 + 128,
1885 .htotal = 800 + 40 + 128 + 88,
1886 .vdisplay = 480,
1887 .vsync_start = 480 + 10,
1888 .vsync_end = 480 + 10 + 2,
1889 .vtotal = 480 + 10 + 2 + 33,
97ceb1fb
MV		 1890 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1891};
1892
1893static const struct panel_desc dataimage_scf0700c48ggu18 = {
1894 .modes = &dataimage_scf0700c48ggu18_mode,
1895 .num_modes = 1,
1896 .bpc = 8,
1897 .size = {
1898 .width = 152,
1899 .height = 91,
1900 },
1901 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1902 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1903};
1904
0ca0c827
PZ		 1905static const struct display_timing dlc_dlc0700yzg_1_timing = {
1906 .pixelclock = { 45000000, 51200000, 57000000 },
1907 .hactive = { 1024, 1024, 1024 },
1908 .hfront_porch = { 100, 106, 113 },
1909 .hback_porch = { 100, 106, 113 },
1910 .hsync_len = { 100, 108, 114 },
1911 .vactive = { 600, 600, 600 },
1912 .vfront_porch = { 8, 11, 15 },
1913 .vback_porch = { 8, 11, 15 },
1914 .vsync_len = { 9, 13, 15 },
1915 .flags = DISPLAY_FLAGS_DE_HIGH,
1916};
1917
1918static const struct panel_desc dlc_dlc0700yzg_1 = {
1919 .timings = &dlc_dlc0700yzg_1_timing,
1920 .num_timings = 1,
1921 .bpc = 6,
1922 .size = {
1923 .width = 154,
1924 .height = 86,
1925 },
1926 .delay = {
1927 .prepare = 30,
1928 .enable = 200,
1929 .disable = 200,
1930 },
1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1933};
1934
6cbe7cd1
MF		 1935static const struct display_timing dlc_dlc1010gig_timing = {
1936 .pixelclock = { 68900000, 71100000, 73400000 },
1937 .hactive = { 1280, 1280, 1280 },
1938 .hfront_porch = { 43, 53, 63 },
1939 .hback_porch = { 43, 53, 63 },
1940 .hsync_len = { 44, 54, 64 },
1941 .vactive = { 800, 800, 800 },
1942 .vfront_porch = { 5, 8, 11 },
1943 .vback_porch = { 5, 8, 11 },
1944 .vsync_len = { 5, 7, 11 },
1945 .flags = DISPLAY_FLAGS_DE_HIGH,
1946};
1947
1948static const struct panel_desc dlc_dlc1010gig = {
1949 .timings = &dlc_dlc1010gig_timing,
1950 .num_timings = 1,
1951 .bpc = 8,
1952 .size = {
1953 .width = 216,
1954 .height = 135,
1955 },
1956 .delay = {
1957 .prepare = 60,
1958 .enable = 150,
1959 .disable = 100,
1960 .unprepare = 60,
1961 },
1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1964};
1965
c2d24af6
AP		 1966static const struct drm_display_mode edt_et035012dm6_mode = {
1967 .clock = 6500,
1968 .hdisplay = 320,
1969 .hsync_start = 320 + 20,
1970 .hsync_end = 320 + 20 + 30,
1971 .htotal = 320 + 20 + 68,
1972 .vdisplay = 240,
1973 .vsync_start = 240 + 4,
1974 .vsync_end = 240 + 4 + 4,
1975 .vtotal = 240 + 4 + 4 + 14,
c2d24af6
AP		 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1977};
1978
1979static const struct panel_desc edt_et035012dm6 = {
1980 .modes = &edt_et035012dm6_mode,
1981 .num_modes = 1,
1982 .bpc = 8,
1983 .size = {
1984 .width = 70,
1985 .height = 52,
1986 },
1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
c2d24af6
AP		 1989};
1990
f08a2a1e
SR		 1991static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1992 .clock = 6520,
1993 .hdisplay = 320,
1994 .hsync_start = 320 + 20,
1995 .hsync_end = 320 + 20 + 68,
1996 .htotal = 320 + 20 + 68,
1997 .vdisplay = 240,
1998 .vsync_start = 240 + 4,
1999 .vsync_end = 240 + 4 + 18,
2000 .vtotal = 240 + 4 + 18,
2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2002};
2003
2004static const struct panel_desc edt_etm0350g0dh6 = {
2005 .modes = &edt_etm0350g0dh6_mode,
2006 .num_modes = 1,
2007 .bpc = 6,
2008 .size = {
2009 .width = 70,
2010 .height = 53,
2011 },
2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2014 .connector_type = DRM_MODE_CONNECTOR_DPI,
2015};
2016
82d57a59
MCR		 2017static const struct drm_display_mode edt_etm043080dh6gp_mode = {
2018 .clock = 10870,
2019 .hdisplay = 480,
2020 .hsync_start = 480 + 8,
2021 .hsync_end = 480 + 8 + 4,
2022 .htotal = 480 + 8 + 4 + 41,
2023
2024 /*
2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
2026 * fb_align
2027 */
2028
2029 .vdisplay = 288,
2030 .vsync_start = 288 + 2,
2031 .vsync_end = 288 + 2 + 4,
2032 .vtotal = 288 + 2 + 4 + 10,
82d57a59
MCR		 2033};
2034
2035static const struct panel_desc edt_etm043080dh6gp = {
2036 .modes = &edt_etm043080dh6gp_mode,
2037 .num_modes = 1,
2038 .bpc = 8,
2039 .size = {
2040 .width = 100,
2041 .height = 65,
2042 },
2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2044 .connector_type = DRM_MODE_CONNECTOR_DPI,
2045};
2046
fd819bff
MV		 2047static const struct drm_display_mode edt_etm0430g0dh6_mode = {
2048 .clock = 9000,
2049 .hdisplay = 480,
2050 .hsync_start = 480 + 2,
2051 .hsync_end = 480 + 2 + 41,
2052 .htotal = 480 + 2 + 41 + 2,
2053 .vdisplay = 272,
2054 .vsync_start = 272 + 2,
2055 .vsync_end = 272 + 2 + 10,
2056 .vtotal = 272 + 2 + 10 + 2,
fd819bff
MV		 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2058};
2059
2060static const struct panel_desc edt_etm0430g0dh6 = {
2061 .modes = &edt_etm0430g0dh6_mode,
2062 .num_modes = 1,
2063 .bpc = 6,
2064 .size = {
2065 .width = 95,
2066 .height = 54,
2067 },
4824a5f7
SR		 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d112e10f 2070 .connector_type = DRM_MODE_CONNECTOR_DPI,
fd819bff
MV		 2071};
2072
26ab0065
SA		 2073static const struct drm_display_mode edt_et057090dhu_mode = {
2074 .clock = 25175,
2075 .hdisplay = 640,
2076 .hsync_start = 640 + 16,
2077 .hsync_end = 640 + 16 + 30,
2078 .htotal = 640 + 16 + 30 + 114,
2079 .vdisplay = 480,
2080 .vsync_start = 480 + 10,
2081 .vsync_end = 480 + 10 + 3,
2082 .vtotal = 480 + 10 + 3 + 32,
26ab0065
SA		 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2084};
2085
2086static const struct panel_desc edt_et057090dhu = {
2087 .modes = &edt_et057090dhu_mode,
2088 .num_modes = 1,
0208d511 2089 .bpc = 6,
26ab0065
SA		 2090 .size = {
2091 .width = 115,
2092 .height = 86,
2093 },
eaeebffa 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
75e73224 2096 .connector_type = DRM_MODE_CONNECTOR_DPI,
26ab0065
SA		 2097};
2098
fff5de45
PZ		 2099static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2100 .clock = 33260,
2101 .hdisplay = 800,
2102 .hsync_start = 800 + 40,
2103 .hsync_end = 800 + 40 + 128,
2104 .htotal = 800 + 40 + 128 + 88,
2105 .vdisplay = 480,
2106 .vsync_start = 480 + 10,
2107 .vsync_end = 480 + 10 + 2,
2108 .vtotal = 480 + 10 + 2 + 33,
fff5de45
PZ		 2109 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2110};
2111
2112static const struct panel_desc edt_etm0700g0dh6 = {
2113 .modes = &edt_etm0700g0dh6_mode,
2114 .num_modes = 1,
0208d511 2115 .bpc = 6,
fff5de45
PZ		 2116 .size = {
2117 .width = 152,
2118 .height = 91,
2119 },
eaeebffa 2120 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 2121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
281edb9f 2122 .connector_type = DRM_MODE_CONNECTOR_DPI,
fff5de45
PZ		 2123};
2124
aa7e6455
JT		 2125static const struct panel_desc edt_etm0700g0bdh6 = {
2126 .modes = &edt_etm0700g0dh6_mode,
2127 .num_modes = 1,
2128 .bpc = 6,
2129 .size = {
2130 .width = 152,
2131 .height = 91,
2132 },
2133 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 2134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
d112e10f 2135 .connector_type = DRM_MODE_CONNECTOR_DPI,
aa7e6455
JT		 2136};
2137
a6cc3c72
MF		 2138static const struct display_timing edt_etml0700y5dha_timing = {
2139 .pixelclock = { 40800000, 51200000, 67200000 },
2140 .hactive = { 1024, 1024, 1024 },
2141 .hfront_porch = { 30, 106, 125 },
2142 .hback_porch = { 30, 106, 125 },
2143 .hsync_len = { 30, 108, 126 },
2144 .vactive = { 600, 600, 600 },
2145 .vfront_porch = { 3, 12, 67},
2146 .vback_porch = { 3, 12, 67 },
2147 .vsync_len = { 4, 11, 66 },
2148 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2149 DISPLAY_FLAGS_DE_HIGH,
2150};
2151
2152static const struct panel_desc edt_etml0700y5dha = {
2153 .timings = &edt_etml0700y5dha_timing,
2154 .num_timings = 1,
2155 .bpc = 8,
2156 .size = {
2157 .width = 155,
2158 .height = 86,
2159 },
2160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2161 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2162};
2163
aeb262c3
PF		 2164static const struct display_timing edt_etml1010g3dra_timing = {
2165 .pixelclock = { 66300000, 72400000, 78900000 },
2166 .hactive = { 1280, 1280, 1280 },
2167 .hfront_porch = { 12, 72, 132 },
2168 .hback_porch = { 86, 86, 86 },
2169 .hsync_len = { 2, 2, 2 },
2170 .vactive = { 800, 800, 800 },
2171 .vfront_porch = { 1, 15, 49 },
2172 .vback_porch = { 21, 21, 21 },
2173 .vsync_len = { 2, 2, 2 },
2174 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
2175 DISPLAY_FLAGS_DE_HIGH,
2176};
2177
2178static const struct panel_desc edt_etml1010g3dra = {
2179 .timings = &edt_etml1010g3dra_timing,
2180 .num_timings = 1,
2181 .bpc = 8,
2182 .size = {
2183 .width = 216,
2184 .height = 135,
2185 },
2186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2187 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2188 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2189};
2190
e46f73fb
SR		 2191static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2192 .clock = 25175,
2193 .hdisplay = 640,
2194 .hsync_start = 640,
2195 .hsync_end = 640 + 16,
2196 .htotal = 640 + 16 + 30 + 114,
2197 .vdisplay = 480,
2198 .vsync_start = 480 + 10,
2199 .vsync_end = 480 + 10 + 3,
2200 .vtotal = 480 + 10 + 3 + 35,
2201 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2202};
2203
2204static const struct panel_desc edt_etmv570g2dhu = {
2205 .modes = &edt_etmv570g2dhu_mode,
2206 .num_modes = 1,
2207 .bpc = 6,
2208 .size = {
2209 .width = 115,
2210 .height = 86,
2211 },
2212 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2213 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2214 .connector_type = DRM_MODE_CONNECTOR_DPI,
2215};
2216
9746f5fe
AF		 2217static const struct display_timing eink_vb3300_kca_timing = {
2218 .pixelclock = { 40000000, 40000000, 40000000 },
2219 .hactive = { 334, 334, 334 },
2220 .hfront_porch = { 1, 1, 1 },
2221 .hback_porch = { 1, 1, 1 },
2222 .hsync_len = { 1, 1, 1 },
2223 .vactive = { 1405, 1405, 1405 },
2224 .vfront_porch = { 1, 1, 1 },
2225 .vback_porch = { 1, 1, 1 },
2226 .vsync_len = { 1, 1, 1 },
2227 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2228 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
2229};
2230
2231static const struct panel_desc eink_vb3300_kca = {
2232 .timings = &eink_vb3300_kca_timing,
2233 .num_timings = 1,
2234 .bpc = 6,
2235 .size = {
2236 .width = 157,
2237 .height = 209,
2238 },
2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2240 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2241 .connector_type = DRM_MODE_CONNECTOR_DPI,
2242};
2243
1319f217
MW		 2244static const struct display_timing evervision_vgg644804_timing = {
2245 .pixelclock = { 25175000, 25175000, 25175000 },
2246 .hactive = { 640, 640, 640 },
2247 .hfront_porch = { 16, 16, 16 },
2248 .hback_porch = { 82, 114, 170 },
2249 .hsync_len = { 5, 30, 30 },
2250 .vactive = { 480, 480, 480 },
2251 .vfront_porch = { 10, 10, 10 },
2252 .vback_porch = { 30, 32, 34 },
2253 .vsync_len = { 1, 3, 5 },
2254 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2255 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2256 DISPLAY_FLAGS_SYNC_POSEDGE,
2257};
2258
2259static const struct panel_desc evervision_vgg644804 = {
2260 .timings = &evervision_vgg644804_timing,
2261 .num_timings = 1,
5dc1ea90 2262 .bpc = 6,
1319f217
MW		 2263 .size = {
2264 .width = 115,
2265 .height = 86,
2266 },
2267 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
5dc1ea90
MW		 2268 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2269 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1319f217
MW		 2270};
2271
9158e3c3
MF		 2272static const struct display_timing evervision_vgg804821_timing = {
2273 .pixelclock = { 27600000, 33300000, 50000000 },
2274 .hactive = { 800, 800, 800 },
2275 .hfront_porch = { 40, 66, 70 },
2276 .hback_porch = { 40, 67, 70 },
2277 .hsync_len = { 40, 67, 70 },
2278 .vactive = { 480, 480, 480 },
2279 .vfront_porch = { 6, 10, 10 },
2280 .vback_porch = { 7, 11, 11 },
2281 .vsync_len = { 7, 11, 11 },
2282 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2283 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2284 DISPLAY_FLAGS_SYNC_NEGEDGE,
2285};
2286
2287static const struct panel_desc evervision_vgg804821 = {
2288 .timings = &evervision_vgg804821_timing,
2289 .num_timings = 1,
2290 .bpc = 8,
2291 .size = {
2292 .width = 108,
2293 .height = 64,
2294 },
2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
9158e3c3
MF		 2297};
2298
102932b0
BB		 2299static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2300 .clock = 32260,
2301 .hdisplay = 800,
2302 .hsync_start = 800 + 168,
2303 .hsync_end = 800 + 168 + 64,
2304 .htotal = 800 + 168 + 64 + 88,
2305 .vdisplay = 480,
2306 .vsync_start = 480 + 37,
2307 .vsync_end = 480 + 37 + 2,
2308 .vtotal = 480 + 37 + 2 + 8,
102932b0
BB		 2309};
2310
2311static const struct panel_desc foxlink_fl500wvr00_a0t = {
2312 .modes = &foxlink_fl500wvr00_a0t_mode,
2313 .num_modes = 1,
d7a839cd 2314 .bpc = 8,
102932b0
BB		 2315 .size = {
2316 .width = 108,
2317 .height = 65,
2318 },
bb276cb3 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 2320};
2321
795db2af
PC		 2322static const struct drm_display_mode frida_frd350h54004_modes[] = {
2323 { /* 60 Hz */
2324 .clock = 6000,
2325 .hdisplay = 320,
2326 .hsync_start = 320 + 44,
2327 .hsync_end = 320 + 44 + 16,
2328 .htotal = 320 + 44 + 16 + 20,
2329 .vdisplay = 240,
2330 .vsync_start = 240 + 2,
2331 .vsync_end = 240 + 2 + 6,
2332 .vtotal = 240 + 2 + 6 + 2,
2333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2334 },
2335 { /* 50 Hz */
2336 .clock = 5400,
2337 .hdisplay = 320,
2338 .hsync_start = 320 + 56,
2339 .hsync_end = 320 + 56 + 16,
2340 .htotal = 320 + 56 + 16 + 40,
2341 .vdisplay = 240,
2342 .vsync_start = 240 + 2,
2343 .vsync_end = 240 + 2 + 6,
2344 .vtotal = 240 + 2 + 6 + 2,
2345 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2346 },
7b6bd843
PC		 2347};
2348
2349static const struct panel_desc frida_frd350h54004 = {
795db2af
PC		 2350 .modes = frida_frd350h54004_modes,
2351 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
7b6bd843
PC		 2352 .bpc = 8,
2353 .size = {
2354 .width = 77,
2355 .height = 64,
2356 },
2357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
7b6bd843
PC		 2359 .connector_type = DRM_MODE_CONNECTOR_DPI,
2360};
2361
3be20710
JT		 2362static const struct drm_display_mode friendlyarm_hd702e_mode = {
2363 .clock = 67185,
2364 .hdisplay = 800,
2365 .hsync_start = 800 + 20,
2366 .hsync_end = 800 + 20 + 24,
2367 .htotal = 800 + 20 + 24 + 20,
2368 .vdisplay = 1280,
2369 .vsync_start = 1280 + 4,
2370 .vsync_end = 1280 + 4 + 8,
2371 .vtotal = 1280 + 4 + 8 + 4,
3be20710
JT		 2372 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2373};
2374
2375static const struct panel_desc friendlyarm_hd702e = {
2376 .modes = &friendlyarm_hd702e_mode,
2377 .num_modes = 1,
2378 .size = {
2379 .width = 94,
2380 .height = 151,
2381 },
2382};
2383
d435a2af
PZ		 2384static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2385 .clock = 9000,
2386 .hdisplay = 480,
2387 .hsync_start = 480 + 5,
2388 .hsync_end = 480 + 5 + 1,
2389 .htotal = 480 + 5 + 1 + 40,
2390 .vdisplay = 272,
2391 .vsync_start = 272 + 8,
2392 .vsync_end = 272 + 8 + 1,
2393 .vtotal = 272 + 8 + 1 + 8,
d435a2af
PZ		 2394};
2395
2396static const struct panel_desc giantplus_gpg482739qs5 = {
2397 .modes = &giantplus_gpg482739qs5_mode,
2398 .num_modes = 1,
2399 .bpc = 8,
2400 .size = {
2401 .width = 95,
2402 .height = 54,
2403 },
33536a09 2404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 2405};
2406
2c6574a9
PC		 2407static const struct display_timing giantplus_gpm940b0_timing = {
2408 .pixelclock = { 13500000, 27000000, 27500000 },
2409 .hactive = { 320, 320, 320 },
2410 .hfront_porch = { 14, 686, 718 },
2411 .hback_porch = { 50, 70, 255 },
2412 .hsync_len = { 1, 1, 1 },
2413 .vactive = { 240, 240, 240 },
2414 .vfront_porch = { 1, 1, 179 },
2415 .vback_porch = { 1, 21, 31 },
2416 .vsync_len = { 1, 1, 6 },
2417 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2418};
2419
2420static const struct panel_desc giantplus_gpm940b0 = {
2421 .timings = &giantplus_gpm940b0_timing,
2422 .num_timings = 1,
2423 .bpc = 8,
2424 .size = {
2425 .width = 60,
2426 .height = 45,
2427 },
2428 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
f5436f77 2429 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2c6574a9
PC		 2430};
2431
ab07725a
PZ		 2432static const struct display_timing hannstar_hsd070pww1_timing = {
2433 .pixelclock = { 64300000, 71100000, 82000000 },
2434 .hactive = { 1280, 1280, 1280 },
2435 .hfront_porch = { 1, 1, 10 },
2436 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 2437 /*
2438 * According to the data sheet, the minimum horizontal blanking interval
2439 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2440 * minimum working horizontal blanking interval to be 60 clocks.
2441 */
2442 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 2443 .vactive = { 800, 800, 800 },
2444 .vfront_porch = { 1, 1, 10 },
2445 .vback_porch = { 1, 1, 10 },
2446 .vsync_len = { 1, 21, 203 },
2447 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 2448};
2449
2450static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 2451 .timings = &hannstar_hsd070pww1_timing,
2452 .num_timings = 1,
a853205e
PZ		 2453 .bpc = 6,
2454 .size = {
2455 .width = 151,
2456 .height = 94,
2457 },
58d6a7bc 2458 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2459 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 2460};
2461
c0d607e5
EN		 2462static const struct display_timing hannstar_hsd100pxn1_timing = {
2463 .pixelclock = { 55000000, 65000000, 75000000 },
2464 .hactive = { 1024, 1024, 1024 },
2465 .hfront_porch = { 40, 40, 40 },
2466 .hback_porch = { 220, 220, 220 },
2467 .hsync_len = { 20, 60, 100 },
2468 .vactive = { 768, 768, 768 },
2469 .vfront_porch = { 7, 7, 7 },
2470 .vback_porch = { 21, 21, 21 },
2471 .vsync_len = { 10, 10, 10 },
2472 .flags = DISPLAY_FLAGS_DE_HIGH,
2473};
2474
2475static const struct panel_desc hannstar_hsd100pxn1 = {
2476 .timings = &hannstar_hsd100pxn1_timing,
2477 .num_timings = 1,
2478 .bpc = 6,
2479 .size = {
2480 .width = 203,
2481 .height = 152,
2482 },
4946b043 2483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2484 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 2485};
2486
170a41e9
SR		 2487static const struct display_timing hannstar_hsd101pww2_timing = {
2488 .pixelclock = { 64300000, 71100000, 82000000 },
2489 .hactive = { 1280, 1280, 1280 },
2490 .hfront_porch = { 1, 1, 10 },
2491 .hback_porch = { 1, 1, 10 },
2492 .hsync_len = { 58, 158, 661 },
2493 .vactive = { 800, 800, 800 },
2494 .vfront_porch = { 1, 1, 10 },
2495 .vback_porch = { 1, 1, 10 },
2496 .vsync_len = { 1, 21, 203 },
2497 .flags = DISPLAY_FLAGS_DE_HIGH,
2498};
2499
2500static const struct panel_desc hannstar_hsd101pww2 = {
2501 .timings = &hannstar_hsd101pww2_timing,
2502 .num_timings = 1,
2503 .bpc = 8,
2504 .size = {
2505 .width = 217,
2506 .height = 136,
2507 },
2508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2509 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2510};
2511
61ac0bf8
LS		 2512static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2513 .clock = 33333,
2514 .hdisplay = 800,
2515 .hsync_start = 800 + 85,
2516 .hsync_end = 800 + 85 + 86,
2517 .htotal = 800 + 85 + 86 + 85,
2518 .vdisplay = 480,
2519 .vsync_start = 480 + 16,
2520 .vsync_end = 480 + 16 + 13,
2521 .vtotal = 480 + 16 + 13 + 16,
61ac0bf8
LS		 2522};
2523
2524static const struct panel_desc hitachi_tx23d38vm0caa = {
2525 .modes = &hitachi_tx23d38vm0caa_mode,
2526 .num_modes = 1,
2527 .bpc = 6,
2528 .size = {
2529 .width = 195,
2530 .height = 117,
2531 },
6c684e3b
PZ		 2532 .delay = {
2533 .enable = 160,
2534 .disable = 160,
2535 },
61ac0bf8
LS		 2536};
2537
41bcceb4
NF		 2538static const struct drm_display_mode innolux_at043tn24_mode = {
2539 .clock = 9000,
2540 .hdisplay = 480,
2541 .hsync_start = 480 + 2,
2542 .hsync_end = 480 + 2 + 41,
2543 .htotal = 480 + 2 + 41 + 2,
2544 .vdisplay = 272,
2545 .vsync_start = 272 + 2,
a483159d
PZ		 2546 .vsync_end = 272 + 2 + 10,
2547 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 2548 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2549};
2550
2551static const struct panel_desc innolux_at043tn24 = {
2552 .modes = &innolux_at043tn24_mode,
2553 .num_modes = 1,
2554 .bpc = 8,
2555 .size = {
2556 .width = 95,
2557 .height = 54,
2558 },
2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2c56a751 2560 .connector_type = DRM_MODE_CONNECTOR_DPI,
88bc4178 2561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 2562};
2563
4fc24ab3
RB		 2564static const struct drm_display_mode innolux_at070tn92_mode = {
2565 .clock = 33333,
2566 .hdisplay = 800,
2567 .hsync_start = 800 + 210,
2568 .hsync_end = 800 + 210 + 20,
2569 .htotal = 800 + 210 + 20 + 46,
2570 .vdisplay = 480,
2571 .vsync_start = 480 + 22,
2572 .vsync_end = 480 + 22 + 10,
2573 .vtotal = 480 + 22 + 23 + 10,
4fc24ab3
RB		 2574};
2575
2576static const struct panel_desc innolux_at070tn92 = {
2577 .modes = &innolux_at070tn92_mode,
2578 .num_modes = 1,
2579 .size = {
2580 .width = 154,
2581 .height = 86,
2582 },
2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2584};
2585
1993f598
RL		 2586static const struct display_timing innolux_g070ace_l01_timing = {
2587 .pixelclock = { 25200000, 35000000, 35700000 },
2588 .hactive = { 800, 800, 800 },
2589 .hfront_porch = { 30, 32, 87 },
2590 .hback_porch = { 30, 32, 87 },
2591 .hsync_len = { 1, 1, 1 },
2592 .vactive = { 480, 480, 480 },
2593 .vfront_porch = { 3, 3, 3 },
2594 .vback_porch = { 13, 13, 13 },
2595 .vsync_len = { 1, 1, 4 },
2596 .flags = DISPLAY_FLAGS_DE_HIGH,
2597};
2598
2599static const struct panel_desc innolux_g070ace_l01 = {
2600 .timings = &innolux_g070ace_l01_timing,
2601 .num_timings = 1,
2602 .bpc = 8,
2603 .size = {
2604 .width = 152,
2605 .height = 91,
2606 },
2607 .delay = {
2608 .prepare = 10,
2609 .enable = 50,
2610 .disable = 50,
2611 .unprepare = 500,
2612 },
2613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2614 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2615 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2616};
2617
a5d2ade6
CF		 2618static const struct display_timing innolux_g070y2_l01_timing = {
2619 .pixelclock = { 28000000, 29500000, 32000000 },
2620 .hactive = { 800, 800, 800 },
2621 .hfront_porch = { 61, 91, 141 },
2622 .hback_porch = { 60, 90, 140 },
2623 .hsync_len = { 12, 12, 12 },
2624 .vactive = { 480, 480, 480 },
2625 .vfront_porch = { 4, 9, 30 },
2626 .vback_porch = { 4, 8, 28 },
2627 .vsync_len = { 2, 2, 2 },
2628 .flags = DISPLAY_FLAGS_DE_HIGH,
2629};
2630
2631static const struct panel_desc innolux_g070y2_l01 = {
2632 .timings = &innolux_g070y2_l01_timing,
2633 .num_timings = 1,
fc1b6ef7 2634 .bpc = 8,
a5d2ade6
CF		 2635 .size = {
2636 .width = 152,
2637 .height = 91,
2638 },
2639 .delay = {
2640 .prepare = 10,
2641 .enable = 100,
2642 .disable = 100,
2643 .unprepare = 800,
2644 },
2645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
0f73a559 2646 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 2647 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 2648};
2649
b9d228a5
ST		 2650static const struct display_timing innolux_g070ace_lh3_timing = {
2651 .pixelclock = { 25200000, 25400000, 35700000 },
2652 .hactive = { 800, 800, 800 },
2653 .hfront_porch = { 30, 32, 87 },
2654 .hback_porch = { 29, 31, 86 },
2655 .hsync_len = { 1, 1, 1 },
2656 .vactive = { 480, 480, 480 },
2657 .vfront_porch = { 4, 5, 65 },
2658 .vback_porch = { 3, 4, 65 },
2659 .vsync_len = { 1, 1, 1 },
2660 .flags = DISPLAY_FLAGS_DE_HIGH,
2661};
2662
2663static const struct panel_desc innolux_g070ace_lh3 = {
2664 .timings = &innolux_g070ace_lh3_timing,
2665 .num_timings = 1,
2666 .bpc = 8,
2667 .size = {
2668 .width = 152,
2669 .height = 91,
2670 },
2671 .delay = {
2672 .prepare = 10,
2673 .enable = 450,
2674 .disable = 200,
2675 .unprepare = 510,
2676 },
2677 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2678 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2679 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2680};
2681
57a06e90
OR		 2682static const struct drm_display_mode innolux_g070y2_t02_mode = {
2683 .clock = 33333,
2684 .hdisplay = 800,
2685 .hsync_start = 800 + 210,
2686 .hsync_end = 800 + 210 + 20,
2687 .htotal = 800 + 210 + 20 + 46,
2688 .vdisplay = 480,
2689 .vsync_start = 480 + 22,
2690 .vsync_end = 480 + 22 + 10,
2691 .vtotal = 480 + 22 + 23 + 10,
2692};
2693
2694static const struct panel_desc innolux_g070y2_t02 = {
2695 .modes = &innolux_g070y2_t02_mode,
2696 .num_modes = 1,
2697 .bpc = 8,
2698 .size = {
2699 .width = 152,
2700 .height = 92,
2701 },
2702 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2703 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2704 .connector_type = DRM_MODE_CONNECTOR_DPI,
2705};
2706
1e29b840
MO		 2707static const struct display_timing innolux_g101ice_l01_timing = {
2708 .pixelclock = { 60400000, 71100000, 74700000 },
2709 .hactive = { 1280, 1280, 1280 },
3f9a91b6
MV		 2710 .hfront_porch = { 30, 60, 70 },
2711 .hback_porch = { 30, 60, 70 },
2712 .hsync_len = { 22, 40, 60 },
1e29b840 2713 .vactive = { 800, 800, 800 },
3f9a91b6
MV		 2714 .vfront_porch = { 3, 8, 14 },
2715 .vback_porch = { 3, 8, 14 },
2716 .vsync_len = { 4, 7, 12 },
1e29b840
MO		 2717 .flags = DISPLAY_FLAGS_DE_HIGH,
2718};
2719
2720static const struct panel_desc innolux_g101ice_l01 = {
2721 .timings = &innolux_g101ice_l01_timing,
2722 .num_timings = 1,
2723 .bpc = 8,
2724 .size = {
2725 .width = 217,
2726 .height = 135,
2727 },
2728 .delay = {
2729 .enable = 200,
2730 .disable = 200,
2731 },
2732 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
06fc41b0 2733 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 2734 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 2735};
2736
4ae13e48
LS		 2737static const struct display_timing innolux_g121i1_l01_timing = {
2738 .pixelclock = { 67450000, 71000000, 74550000 },
2739 .hactive = { 1280, 1280, 1280 },
2740 .hfront_porch = { 40, 80, 160 },
2741 .hback_porch = { 39, 79, 159 },
2742 .hsync_len = { 1, 1, 1 },
2743 .vactive = { 800, 800, 800 },
2744 .vfront_porch = { 5, 11, 100 },
2745 .vback_porch = { 4, 11, 99 },
2746 .vsync_len = { 1, 1, 1 },
d731f661
LS		 2747};
2748
2749static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 2750 .timings = &innolux_g121i1_l01_timing,
2751 .num_timings = 1,
d731f661
LS		 2752 .bpc = 6,
2753 .size = {
2754 .width = 261,
2755 .height = 163,
2756 },
4ae13e48
LS		 2757 .delay = {
2758 .enable = 200,
2759 .disable = 20,
2760 },
a7c48a0a 2761 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2762 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 2763};
2764
90c53f2b
MV		 2765static const struct display_timing innolux_g121x1_l03_timings = {
2766 .pixelclock = { 57500000, 64900000, 74400000 },
2767 .hactive = { 1024, 1024, 1024 },
2768 .hfront_porch = { 90, 140, 190 },
2769 .hback_porch = { 90, 140, 190 },
2770 .hsync_len = { 36, 40, 60 },
2771 .vactive = { 768, 768, 768 },
2772 .vfront_porch = { 2, 15, 30 },
2773 .vback_porch = { 2, 15, 30 },
2774 .vsync_len = { 2, 8, 20 },
2775 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
f8fa17ba
AB		 2776};
2777
2778static const struct panel_desc innolux_g121x1_l03 = {
90c53f2b
MV		 2779 .timings = &innolux_g121x1_l03_timings,
2780 .num_timings = 1,
f8fa17ba
AB		 2781 .bpc = 6,
2782 .size = {
2783 .width = 246,
2784 .height = 185,
2785 },
2786 .delay = {
2787 .enable = 200,
2788 .unprepare = 200,
2789 .disable = 400,
2790 },
11ac72d0
MV		 2791 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2792 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2793 .connector_type = DRM_MODE_CONNECTOR_LVDS,
f8fa17ba
AB		 2794};
2795
f7ad2ce5
MV		 2796static const struct panel_desc innolux_g121xce_l01 = {
2797 .timings = &innolux_g121x1_l03_timings,
2798 .num_timings = 1,
2799 .bpc = 8,
2800 .size = {
2801 .width = 246,
2802 .height = 185,
2803 },
2804 .delay = {
2805 .enable = 200,
2806 .unprepare = 200,
2807 .disable = 400,
2808 },
2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2810 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2811 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2812};
2813
eae74888 2814static const struct display_timing innolux_g156hce_l01_timings = {
438cf327 2815 .pixelclock = { 120000000, 141860000, 150000000 },
eae74888
MV		 2816 .hactive = { 1920, 1920, 1920 },
2817 .hfront_porch = { 80, 90, 100 },
2818 .hback_porch = { 80, 90, 100 },
2819 .hsync_len = { 20, 30, 30 },
2820 .vactive = { 1080, 1080, 1080 },
2821 .vfront_porch = { 3, 10, 20 },
2822 .vback_porch = { 3, 10, 20 },
2823 .vsync_len = { 4, 10, 10 },
2824};
2825
2826static const struct panel_desc innolux_g156hce_l01 = {
2827 .timings = &innolux_g156hce_l01_timings,
2828 .num_timings = 1,
2829 .bpc = 8,
2830 .size = {
2831 .width = 344,
2832 .height = 194,
2833 },
2834 .delay = {
2835 .prepare = 1, /* T1+T2 */
2836 .enable = 450, /* T5 */
2837 .disable = 200, /* T6 */
2838 .unprepare = 10, /* T3+T7 */
2839 },
2840 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2841 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2842 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2843};
2844
ea44739d
AB		 2845static const struct drm_display_mode innolux_n156bge_l21_mode = {
2846 .clock = 69300,
2847 .hdisplay = 1366,
2848 .hsync_start = 1366 + 16,
2849 .hsync_end = 1366 + 16 + 34,
2850 .htotal = 1366 + 16 + 34 + 50,
2851 .vdisplay = 768,
2852 .vsync_start = 768 + 2,
2853 .vsync_end = 768 + 2 + 6,
2854 .vtotal = 768 + 2 + 6 + 12,
ea44739d
AB		 2855};
2856
2857static const struct panel_desc innolux_n156bge_l21 = {
2858 .modes = &innolux_n156bge_l21_mode,
2859 .num_modes = 1,
0208d511 2860 .bpc = 6,
ea44739d
AB		 2861 .size = {
2862 .width = 344,
2863 .height = 193,
2864 },
85560829 2865 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 2866 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 2867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ea44739d
AB		 2868};
2869
bccac3f1
MG		 2870static const struct drm_display_mode innolux_zj070na_01p_mode = {
2871 .clock = 51501,
2872 .hdisplay = 1024,
2873 .hsync_start = 1024 + 128,
2874 .hsync_end = 1024 + 128 + 64,
2875 .htotal = 1024 + 128 + 64 + 128,
2876 .vdisplay = 600,
2877 .vsync_start = 600 + 16,
2878 .vsync_end = 600 + 16 + 4,
2879 .vtotal = 600 + 16 + 4 + 16,
bccac3f1
MG		 2880};
2881
2882static const struct panel_desc innolux_zj070na_01p = {
2883 .modes = &innolux_zj070na_01p_mode,
2884 .num_modes = 1,
2885 .bpc = 6,
2886 .size = {
81598846
TR		 2887 .width = 154,
2888 .height = 90,
bccac3f1
MG		 2889 },
2890};
2891
14bf60c4
LM		 2892static const struct display_timing koe_tx14d24vm1bpa_timing = {
2893 .pixelclock = { 5580000, 5850000, 6200000 },
2894 .hactive = { 320, 320, 320 },
2895 .hfront_porch = { 30, 30, 30 },
2896 .hback_porch = { 30, 30, 30 },
2897 .hsync_len = { 1, 5, 17 },
2898 .vactive = { 240, 240, 240 },
2899 .vfront_porch = { 6, 6, 6 },
2900 .vback_porch = { 5, 5, 5 },
2901 .vsync_len = { 1, 2, 11 },
2902 .flags = DISPLAY_FLAGS_DE_HIGH,
2903};
2904
2905static const struct panel_desc koe_tx14d24vm1bpa = {
2906 .timings = &koe_tx14d24vm1bpa_timing,
2907 .num_timings = 1,
2908 .bpc = 6,
2909 .size = {
2910 .width = 115,
2911 .height = 86,
2912 },
2913};
2914
8a070524
LY		 2915static const struct display_timing koe_tx26d202vm0bwa_timing = {
2916 .pixelclock = { 151820000, 156720000, 159780000 },
2917 .hactive = { 1920, 1920, 1920 },
2918 .hfront_porch = { 105, 130, 142 },
2919 .hback_porch = { 45, 70, 82 },
2920 .hsync_len = { 30, 30, 30 },
2921 .vactive = { 1200, 1200, 1200},
2922 .vfront_porch = { 3, 5, 10 },
2923 .vback_porch = { 2, 5, 10 },
2924 .vsync_len = { 5, 5, 5 },
37ce99b7 2925 .flags = DISPLAY_FLAGS_DE_HIGH,
8a070524
LY		 2926};
2927
2928static const struct panel_desc koe_tx26d202vm0bwa = {
2929 .timings = &koe_tx26d202vm0bwa_timing,
2930 .num_timings = 1,
2931 .bpc = 8,
2932 .size = {
2933 .width = 217,
2934 .height = 136,
2935 },
2936 .delay = {
2937 .prepare = 1000,
2938 .enable = 1000,
2939 .unprepare = 1000,
2940 .disable = 1000,
2941 },
2942 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2943 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
8a070524
LY		 2944 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2945};
2946
8cfe8341
JT		 2947static const struct display_timing koe_tx31d200vm0baa_timing = {
2948 .pixelclock = { 39600000, 43200000, 48000000 },
2949 .hactive = { 1280, 1280, 1280 },
2950 .hfront_porch = { 16, 36, 56 },
2951 .hback_porch = { 16, 36, 56 },
2952 .hsync_len = { 8, 8, 8 },
2953 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 2954 .vfront_porch = { 6, 21, 33 },
2955 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 2956 .vsync_len = { 8, 8, 8 },
2957 .flags = DISPLAY_FLAGS_DE_HIGH,
2958};
2959
2960static const struct panel_desc koe_tx31d200vm0baa = {
2961 .timings = &koe_tx31d200vm0baa_timing,
2962 .num_timings = 1,
2963 .bpc = 6,
2964 .size = {
2965 .width = 292,
2966 .height = 109,
2967 },
2968 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2969 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 2970};
2971
8def22e5
LS		 2972static const struct display_timing kyo_tcg121xglp_timing = {
2973 .pixelclock = { 52000000, 65000000, 71000000 },
2974 .hactive = { 1024, 1024, 1024 },
2975 .hfront_porch = { 2, 2, 2 },
2976 .hback_porch = { 2, 2, 2 },
2977 .hsync_len = { 86, 124, 244 },
2978 .vactive = { 768, 768, 768 },
2979 .vfront_porch = { 2, 2, 2 },
2980 .vback_porch = { 2, 2, 2 },
2981 .vsync_len = { 6, 34, 73 },
2982 .flags = DISPLAY_FLAGS_DE_HIGH,
2983};
2984
2985static const struct panel_desc kyo_tcg121xglp = {
2986 .timings = &kyo_tcg121xglp_timing,
2987 .num_timings = 1,
2988 .bpc = 8,
2989 .size = {
2990 .width = 246,
2991 .height = 184,
2992 },
2993 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2994 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 2995};
2996
27abdd83
PK		 2997static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2998 .clock = 7000,
2999 .hdisplay = 320,
3000 .hsync_start = 320 + 20,
3001 .hsync_end = 320 + 20 + 30,
3002 .htotal = 320 + 20 + 30 + 38,
3003 .vdisplay = 240,
3004 .vsync_start = 240 + 4,
3005 .vsync_end = 240 + 4 + 3,
3006 .vtotal = 240 + 4 + 3 + 15,
27abdd83
PK		 3007};
3008
3009static const struct panel_desc lemaker_bl035_rgb_002 = {
3010 .modes = &lemaker_bl035_rgb_002_mode,
3011 .num_modes = 1,
3012 .size = {
3013 .width = 70,
3014 .height = 52,
3015 },
3016 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3017 .bus_flags = DRM_BUS_FLAG_DE_LOW,
3018};
3019
c3ba13a0
AS		 3020static const struct display_timing lg_lb070wv8_timing = {
3021 .pixelclock = { 31950000, 33260000, 34600000 },
3022 .hactive = { 800, 800, 800 },
3023 .hfront_porch = { 88, 88, 88 },
3024 .hback_porch = { 88, 88, 88 },
3025 .hsync_len = { 80, 80, 80 },
3026 .vactive = { 480, 480, 480 },
3027 .vfront_porch = { 10, 10, 10 },
3028 .vback_porch = { 10, 10, 10 },
3029 .vsync_len = { 25, 25, 25 },
dd015002
HS		 3030};
3031
3032static const struct panel_desc lg_lb070wv8 = {
c3ba13a0
AS		 3033 .timings = &lg_lb070wv8_timing,
3034 .num_timings = 1,
a6ae2fe5 3035 .bpc = 8,
dd015002
HS		 3036 .size = {
3037 .width = 151,
3038 .height = 91,
3039 },
3040 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3041 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 3042};
3043
ac9b8b7f
AB		 3044static const struct drm_display_mode lincolntech_lcd185_101ct_mode = {
3045 .clock = 155127,
3046 .hdisplay = 1920,
3047 .hsync_start = 1920 + 128,
3048 .hsync_end = 1920 + 128 + 20,
3049 .htotal = 1920 + 128 + 20 + 12,
3050 .vdisplay = 1200,
3051 .vsync_start = 1200 + 19,
3052 .vsync_end = 1200 + 19 + 4,
3053 .vtotal = 1200 + 19 + 4 + 20,
3054};
3055
3056static const struct panel_desc lincolntech_lcd185_101ct = {
3057 .modes = &lincolntech_lcd185_101ct_mode,
3058 .bpc = 8,
3059 .num_modes = 1,
3060 .size = {
3061 .width = 217,
3062 .height = 136,
3063 },
3064 .delay = {
3065 .prepare = 50,
3066 .disable = 50,
3067 },
3068 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3069 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3070 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3071};
3072
5728fe7f
MZ		 3073static const struct display_timing logictechno_lt161010_2nh_timing = {
3074 .pixelclock = { 26400000, 33300000, 46800000 },
3075 .hactive = { 800, 800, 800 },
3076 .hfront_porch = { 16, 210, 354 },
3077 .hback_porch = { 46, 46, 46 },
3078 .hsync_len = { 1, 20, 40 },
3079 .vactive = { 480, 480, 480 },
3080 .vfront_porch = { 7, 22, 147 },
3081 .vback_porch = { 23, 23, 23 },
3082 .vsync_len = { 1, 10, 20 },
3083 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3084 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3085 DISPLAY_FLAGS_SYNC_POSEDGE,
3086};
3087
3088static const struct panel_desc logictechno_lt161010_2nh = {
3089 .timings = &logictechno_lt161010_2nh_timing,
3090 .num_timings = 1,
876153ab 3091 .bpc = 6,
5728fe7f
MZ		 3092 .size = {
3093 .width = 154,
3094 .height = 86,
3095 },
3096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3097 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3098 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3099 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3100 .connector_type = DRM_MODE_CONNECTOR_DPI,
3101};
3102
3103static const struct display_timing logictechno_lt170410_2whc_timing = {
3104 .pixelclock = { 68900000, 71100000, 73400000 },
3105 .hactive = { 1280, 1280, 1280 },
3106 .hfront_porch = { 23, 60, 71 },
3107 .hback_porch = { 23, 60, 71 },
3108 .hsync_len = { 15, 40, 47 },
3109 .vactive = { 800, 800, 800 },
3110 .vfront_porch = { 5, 7, 10 },
3111 .vback_porch = { 5, 7, 10 },
3112 .vsync_len = { 6, 9, 12 },
3113 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3114 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3115 DISPLAY_FLAGS_SYNC_POSEDGE,
3116};
3117
3118static const struct panel_desc logictechno_lt170410_2whc = {
3119 .timings = &logictechno_lt170410_2whc_timing,
3120 .num_timings = 1,
876153ab 3121 .bpc = 8,
5728fe7f
MZ		 3122 .size = {
3123 .width = 217,
3124 .height = 136,
3125 },
3126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 3127 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
5728fe7f
MZ		 3128 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3129};
3130
19f036ea
SA		 3131static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
3132 .clock = 33000,
3133 .hdisplay = 800,
3134 .hsync_start = 800 + 112,
3135 .hsync_end = 800 + 112 + 3,
3136 .htotal = 800 + 112 + 3 + 85,
3137 .vdisplay = 480,
3138 .vsync_start = 480 + 38,
3139 .vsync_end = 480 + 38 + 3,
3140 .vtotal = 480 + 38 + 3 + 29,
3141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3142};
3143
3144static const struct panel_desc logictechno_lttd800480070_l2rt = {
3145 .modes = &logictechno_lttd800480070_l2rt_mode,
3146 .num_modes = 1,
3147 .bpc = 8,
3148 .size = {
3149 .width = 154,
3150 .height = 86,
3151 },
3152 .delay = {
3153 .prepare = 45,
3154 .enable = 100,
3155 .disable = 100,
3156 .unprepare = 45
3157 },
3158 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3159 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3160 .connector_type = DRM_MODE_CONNECTOR_DPI,
3161};
3162
0c044f7d
SA		 3163static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
3164 .clock = 33000,
3165 .hdisplay = 800,
3166 .hsync_start = 800 + 154,
3167 .hsync_end = 800 + 154 + 3,
3168 .htotal = 800 + 154 + 3 + 43,
3169 .vdisplay = 480,
3170 .vsync_start = 480 + 47,
3171 .vsync_end = 480 + 47 + 3,
3172 .vtotal = 480 + 47 + 3 + 20,
3173 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3174};
3175
3176static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
3177 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
3178 .num_modes = 1,
3179 .bpc = 8,
3180 .size = {
3181 .width = 154,
3182 .height = 86,
3183 },
3184 .delay = {
3185 .prepare = 45,
3186 .enable = 100,
3187 .disable = 100,
3188 .unprepare = 45
3189 },
3190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3191 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3192 .connector_type = DRM_MODE_CONNECTOR_DPI,
3193};
3194
0d35408a 3195static const struct drm_display_mode logicpd_type_28_mode = {
f873c5d8 3196 .clock = 9107,
0d35408a
AF		 3197 .hdisplay = 480,
3198 .hsync_start = 480 + 3,
3199 .hsync_end = 480 + 3 + 42,
3200 .htotal = 480 + 3 + 42 + 2,
3201
3202 .vdisplay = 272,
3203 .vsync_start = 272 + 2,
3204 .vsync_end = 272 + 2 + 11,
3205 .vtotal = 272 + 2 + 11 + 3,
0d35408a
AF		 3206 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3207};
3208
3209static const struct panel_desc logicpd_type_28 = {
3210 .modes = &logicpd_type_28_mode,
3211 .num_modes = 1,
3212 .bpc = 8,
3213 .size = {
3214 .width = 105,
3215 .height = 67,
3216 },
3217 .delay = {
3218 .prepare = 200,
3219 .enable = 200,
3220 .unprepare = 200,
3221 .disable = 200,
3222 },
3223 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3225 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
efb94790 3226 .connector_type = DRM_MODE_CONNECTOR_DPI,
0d35408a
AF		 3227};
3228
f558d676
AB		 3229static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = {
3230 .clock = 150275,
3231 .hdisplay = 1920,
3232 .hsync_start = 1920 + 32,
3233 .hsync_end = 1920 + 32 + 52,
3234 .htotal = 1920 + 32 + 52 + 24,
3235 .vdisplay = 1200,
3236 .vsync_start = 1200 + 24,
3237 .vsync_end = 1200 + 24 + 8,
3238 .vtotal = 1200 + 24 + 8 + 3,
3239};
3240
3241static const struct panel_desc microtips_mf_101hiebcaf0_c = {
3242 .modes = &microtips_mf_101hiebcaf0_c_mode,
3243 .bpc = 8,
3244 .num_modes = 1,
3245 .size = {
3246 .width = 217,
3247 .height = 136,
3248 },
3249 .delay = {
3250 .prepare = 50,
3251 .disable = 50,
3252 },
3253 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3254 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3255 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3256};
3257
2c3d1bd2
AB		 3258static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = {
3259 .clock = 93301,
3260 .hdisplay = 1920,
3261 .hsync_start = 1920 + 72,
3262 .hsync_end = 1920 + 72 + 72,
3263 .htotal = 1920 + 72 + 72 + 72,
3264 .vdisplay = 720,
3265 .vsync_start = 720 + 3,
3266 .vsync_end = 720 + 3 + 3,
3267 .vtotal = 720 + 3 + 3 + 2,
3268};
3269
3270static const struct panel_desc microtips_mf_103hieb0ga0 = {
3271 .modes = &microtips_mf_103hieb0ga0_mode,
3272 .bpc = 8,
3273 .num_modes = 1,
3274 .size = {
3275 .width = 244,
3276 .height = 92,
3277 },
3278 .delay = {
3279 .prepare = 50,
3280 .disable = 50,
3281 },
3282 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3283 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3284 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3285};
3286
c8527b9a
DA		 3287static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3288 .clock = 30400,
3289 .hdisplay = 800,
3290 .hsync_start = 800 + 0,
3291 .hsync_end = 800 + 1,
3292 .htotal = 800 + 0 + 1 + 160,
3293 .vdisplay = 480,
3294 .vsync_start = 480 + 0,
3295 .vsync_end = 480 + 48 + 1,
3296 .vtotal = 480 + 48 + 1 + 0,
3297 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3298};
3299
65c766ca
LM		 3300static const struct panel_desc mitsubishi_aa070mc01 = {
3301 .modes = &mitsubishi_aa070mc01_mode,
3302 .num_modes = 1,
3303 .bpc = 8,
3304 .size = {
3305 .width = 152,
3306 .height = 91,
3307 },
3308
3309 .delay = {
3310 .enable = 200,
3311 .unprepare = 200,
3312 .disable = 400,
3313 },
3314 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3315 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 3316 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3317};
3318
637d3fdc
TW		 3319static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
3320 .clock = 56234,
3321 .hdisplay = 1024,
3322 .hsync_start = 1024 + 24,
3323 .hsync_end = 1024 + 24 + 63,
3324 .htotal = 1024 + 24 + 63 + 1,
3325 .vdisplay = 768,
3326 .vsync_start = 768 + 3,
3327 .vsync_end = 768 + 3 + 6,
3328 .vtotal = 768 + 3 + 6 + 1,
3329 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3330};
3331
3332static const struct panel_desc mitsubishi_aa084xe01 = {
3333 .modes = &mitsubishi_aa084xe01_mode,
3334 .num_modes = 1,
3335 .bpc = 8,
3336 .size = {
3337 .width = 1024,
3338 .height = 768,
3339 },
3340 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3341 .connector_type = DRM_MODE_CONNECTOR_DPI,
3342 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3343};
3344
ba68e690
MV		 3345static const struct display_timing multi_inno_mi0700a2t_30_timing = {
3346 .pixelclock = { 26400000, 33000000, 46800000 },
3347 .hactive = { 800, 800, 800 },
3348 .hfront_porch = { 16, 204, 354 },
3349 .hback_porch = { 46, 46, 46 },
3350 .hsync_len = { 1, 6, 40 },
3351 .vactive = { 480, 480, 480 },
3352 .vfront_porch = { 7, 22, 147 },
3353 .vback_porch = { 23, 23, 23 },
3354 .vsync_len = { 1, 3, 20 },
3355 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3356 DISPLAY_FLAGS_DE_HIGH,
3357};
3358
3359static const struct panel_desc multi_inno_mi0700a2t_30 = {
3360 .timings = &multi_inno_mi0700a2t_30_timing,
3361 .num_timings = 1,
3362 .bpc = 6,
3363 .size = {
3364 .width = 153,
3365 .height = 92,
3366 },
3367 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3368 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3369 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3370};
3371
a5d092d3
MV		 3372static const struct display_timing multi_inno_mi0700s4t_6_timing = {
3373 .pixelclock = { 29000000, 33000000, 38000000 },
3374 .hactive = { 800, 800, 800 },
3375 .hfront_porch = { 180, 210, 240 },
3376 .hback_porch = { 16, 16, 16 },
3377 .hsync_len = { 30, 30, 30 },
3378 .vactive = { 480, 480, 480 },
3379 .vfront_porch = { 12, 22, 32 },
3380 .vback_porch = { 10, 10, 10 },
3381 .vsync_len = { 13, 13, 13 },
3382 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3383 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3384 DISPLAY_FLAGS_SYNC_POSEDGE,
3385};
3386
3387static const struct panel_desc multi_inno_mi0700s4t_6 = {
3388 .timings = &multi_inno_mi0700s4t_6_timing,
3389 .num_timings = 1,
3390 .bpc = 8,
3391 .size = {
3392 .width = 154,
3393 .height = 86,
3394 },
3395 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3396 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3397 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3398 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3399 .connector_type = DRM_MODE_CONNECTOR_DPI,
3400};
3401
b55002b9
CN		 3402static const struct display_timing multi_inno_mi0800ft_9_timing = {
3403 .pixelclock = { 32000000, 40000000, 50000000 },
3404 .hactive = { 800, 800, 800 },
3405 .hfront_porch = { 16, 210, 354 },
3406 .hback_porch = { 6, 26, 45 },
3407 .hsync_len = { 1, 20, 40 },
3408 .vactive = { 600, 600, 600 },
3409 .vfront_porch = { 1, 12, 77 },
3410 .vback_porch = { 3, 13, 22 },
3411 .vsync_len = { 1, 10, 20 },
3412 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3413 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3414 DISPLAY_FLAGS_SYNC_POSEDGE,
3415};
3416
3417static const struct panel_desc multi_inno_mi0800ft_9 = {
3418 .timings = &multi_inno_mi0800ft_9_timing,
3419 .num_timings = 1,
3420 .bpc = 8,
3421 .size = {
3422 .width = 162,
3423 .height = 122,
3424 },
3425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3426 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3427 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3428 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3429 .connector_type = DRM_MODE_CONNECTOR_DPI,
3430};
3431
81162f4b
SR		 3432static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
3433 .pixelclock = { 68900000, 70000000, 73400000 },
3434 .hactive = { 1280, 1280, 1280 },
3435 .hfront_porch = { 30, 60, 71 },
3436 .hback_porch = { 30, 60, 71 },
3437 .hsync_len = { 10, 10, 48 },
3438 .vactive = { 800, 800, 800 },
3439 .vfront_porch = { 5, 10, 10 },
3440 .vback_porch = { 5, 10, 10 },
3441 .vsync_len = { 5, 6, 13 },
3442 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3443 DISPLAY_FLAGS_DE_HIGH,
3444};
3445
3446static const struct panel_desc multi_inno_mi1010ait_1cp = {
3447 .timings = &multi_inno_mi1010ait_1cp_timing,
3448 .num_timings = 1,
3449 .bpc = 8,
3450 .size = {
3451 .width = 217,
3452 .height = 136,
3453 },
3454 .delay = {
3455 .enable = 50,
3456 .disable = 50,
3457 },
3458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3459 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3460 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3461};
3462
958473e7
MV		 3463static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = {
3464 .pixelclock = { 40800000, 51200000, 67200000 },
3465 .hactive = { 1024, 1024, 1024 },
3466 .hfront_porch = { 30, 110, 130 },
3467 .hback_porch = { 30, 110, 130 },
3468 .hsync_len = { 30, 100, 116 },
3469 .vactive = { 600, 600, 600 },
3470 .vfront_porch = { 4, 13, 80 },
3471 .vback_porch = { 4, 13, 80 },
3472 .vsync_len = { 2, 9, 40 },
3473 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3474 DISPLAY_FLAGS_DE_HIGH,
3475};
3476
3477static const struct panel_desc multi_inno_mi1010z1t_1cp11 = {
3478 .timings = &multi_inno_mi1010z1t_1cp11_timing,
3479 .num_timings = 1,
3480 .bpc = 6,
3481 .size = {
3482 .width = 260,
3483 .height = 162,
3484 },
3485 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3486 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3487 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3488};
3489
01bacc13
LS		 3490static const struct display_timing nec_nl12880bc20_05_timing = {
3491 .pixelclock = { 67000000, 71000000, 75000000 },
3492 .hactive = { 1280, 1280, 1280 },
3493 .hfront_porch = { 2, 30, 30 },
3494 .hback_porch = { 6, 100, 100 },
3495 .hsync_len = { 2, 30, 30 },
3496 .vactive = { 800, 800, 800 },
3497 .vfront_porch = { 5, 5, 5 },
3498 .vback_porch = { 11, 11, 11 },
3499 .vsync_len = { 7, 7, 7 },
3500};
3501
3502static const struct panel_desc nec_nl12880bc20_05 = {
3503 .timings = &nec_nl12880bc20_05_timing,
3504 .num_timings = 1,
3505 .bpc = 8,
3506 .size = {
3507 .width = 261,
3508 .height = 163,
3509 },
3510 .delay = {
3511 .enable = 50,
3512 .disable = 50,
3513 },
3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3515 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 3516};
3517
c6e87f91 3518static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3519 .clock = 10870,
3520 .hdisplay = 480,
3521 .hsync_start = 480 + 2,
3522 .hsync_end = 480 + 2 + 41,
3523 .htotal = 480 + 2 + 41 + 2,
3524 .vdisplay = 272,
3525 .vsync_start = 272 + 2,
3526 .vsync_end = 272 + 2 + 4,
3527 .vtotal = 272 + 2 + 4 + 2,
4bc390c6 3528 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 3529};
3530
3531static const struct panel_desc nec_nl4827hc19_05b = {
3532 .modes = &nec_nl4827hc19_05b_mode,
3533 .num_modes = 1,
3534 .bpc = 8,
3535 .size = {
3536 .width = 95,
3537 .height = 54,
3538 },
2c80661d 3539 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 3540 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 3541};
3542
e6c2f066
MR		 3543static const struct drm_display_mode netron_dy_e231732_mode = {
3544 .clock = 66000,
3545 .hdisplay = 1024,
3546 .hsync_start = 1024 + 160,
3547 .hsync_end = 1024 + 160 + 70,
3548 .htotal = 1024 + 160 + 70 + 90,
3549 .vdisplay = 600,
3550 .vsync_start = 600 + 127,
3551 .vsync_end = 600 + 127 + 20,
3552 .vtotal = 600 + 127 + 20 + 3,
e6c2f066
MR		 3553};
3554
3555static const struct panel_desc netron_dy_e231732 = {
3556 .modes = &netron_dy_e231732_mode,
3557 .num_modes = 1,
3558 .size = {
3559 .width = 154,
3560 .height = 87,
3561 },
3562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3563};
3564
3b39ad7a
TV		 3565static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3566 .clock = 9000,
3567 .hdisplay = 480,
3568 .hsync_start = 480 + 2,
3569 .hsync_end = 480 + 2 + 41,
3570 .htotal = 480 + 2 + 41 + 2,
3571 .vdisplay = 272,
3572 .vsync_start = 272 + 2,
3573 .vsync_end = 272 + 2 + 10,
3574 .vtotal = 272 + 2 + 10 + 2,
3b39ad7a
TV		 3575 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3576};
3577
3578static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3579 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3580 .num_modes = 1,
3581 .bpc = 8,
3582 .size = {
3583 .width = 95,
3584 .height = 54,
3585 },
3586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 3587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3588 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
8a4f5e11 3589 .connector_type = DRM_MODE_CONNECTOR_DPI,
3b39ad7a
TV		 3590};
3591
c180b003
AG		 3592static const struct drm_display_mode nlt_nl13676bc25_03f_mode = {
3593 .clock = 75400,
3594 .hdisplay = 1366,
3595 .hsync_start = 1366 + 14,
3596 .hsync_end = 1366 + 14 + 56,
3597 .htotal = 1366 + 14 + 56 + 64,
3598 .vdisplay = 768,
3599 .vsync_start = 768 + 1,
3600 .vsync_end = 768 + 1 + 3,
3601 .vtotal = 768 + 1 + 3 + 22,
3602};
3603
3604static const struct panel_desc nlt_nl13676bc25_03f = {
3605 .modes = &nlt_nl13676bc25_03f_mode,
3606 .num_modes = 1,
3607 .bpc = 8,
3608 .size = {
3609 .width = 363,
3610 .height = 215,
3611 },
3612 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3613 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3614};
3615
4177fa66
LS		 3616static const struct display_timing nlt_nl192108ac18_02d_timing = {
3617 .pixelclock = { 130000000, 148350000, 163000000 },
3618 .hactive = { 1920, 1920, 1920 },
3619 .hfront_porch = { 80, 100, 100 },
3620 .hback_porch = { 100, 120, 120 },
3621 .hsync_len = { 50, 60, 60 },
3622 .vactive = { 1080, 1080, 1080 },
3623 .vfront_porch = { 12, 30, 30 },
3624 .vback_porch = { 4, 10, 10 },
3625 .vsync_len = { 4, 5, 5 },
3626};
3627
3628static const struct panel_desc nlt_nl192108ac18_02d = {
3629 .timings = &nlt_nl192108ac18_02d_timing,
3630 .num_timings = 1,
3631 .bpc = 8,
3632 .size = {
3633 .width = 344,
3634 .height = 194,
3635 },
3636 .delay = {
3637 .unprepare = 500,
3638 },
3639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3640 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 3641};
3642
05ec0e45
FL		 3643static const struct drm_display_mode nvd_9128_mode = {
3644 .clock = 29500,
3645 .hdisplay = 800,
3646 .hsync_start = 800 + 130,
3647 .hsync_end = 800 + 130 + 98,
3648 .htotal = 800 + 0 + 130 + 98,
3649 .vdisplay = 480,
3650 .vsync_start = 480 + 10,
3651 .vsync_end = 480 + 10 + 50,
3652 .vtotal = 480 + 0 + 10 + 50,
3653};
3654
3655static const struct panel_desc nvd_9128 = {
3656 .modes = &nvd_9128_mode,
3657 .num_modes = 1,
3658 .bpc = 8,
3659 .size = {
3660 .width = 156,
3661 .height = 88,
3662 },
3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3664 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 3665};
3666
a99fb626
GB		 3667static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3668 .pixelclock = { 30000000, 30000000, 40000000 },
3669 .hactive = { 800, 800, 800 },
3670 .hfront_porch = { 40, 40, 40 },
3671 .hback_porch = { 40, 40, 40 },
3672 .hsync_len = { 1, 48, 48 },
3673 .vactive = { 480, 480, 480 },
3674 .vfront_porch = { 13, 13, 13 },
3675 .vback_porch = { 29, 29, 29 },
3676 .vsync_len = { 3, 3, 3 },
3677 .flags = DISPLAY_FLAGS_DE_HIGH,
3678};
3679
3680static const struct panel_desc okaya_rs800480t_7x0gp = {
3681 .timings = &okaya_rs800480t_7x0gp_timing,
3682 .num_timings = 1,
3683 .bpc = 6,
3684 .size = {
3685 .width = 154,
3686 .height = 87,
3687 },
3688 .delay = {
3689 .prepare = 41,
3690 .enable = 50,
3691 .unprepare = 41,
3692 .disable = 50,
3693 },
3694 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3695};
3696
cf5c9e6d
MR		 3697static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3698 .clock = 9000,
3699 .hdisplay = 480,
3700 .hsync_start = 480 + 5,
3701 .hsync_end = 480 + 5 + 30,
3702 .htotal = 480 + 5 + 30 + 10,
3703 .vdisplay = 272,
3704 .vsync_start = 272 + 8,
3705 .vsync_end = 272 + 8 + 5,
3706 .vtotal = 272 + 8 + 5 + 3,
cf5c9e6d
MR		 3707};
3708
3709static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3710 .modes = &olimex_lcd_olinuxino_43ts_mode,
3711 .num_modes = 1,
3712 .size = {
30c6d7ab
JL		 3713 .width = 95,
3714 .height = 54,
cf5c9e6d 3715 },
5c2a7c6b 3716 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 3717};
3718
91a759d4
LY		 3719static const struct display_timing ontat_kd50g21_40nt_a1_timing = {
3720 .pixelclock = { 30000000, 30000000, 50000000 },
3721 .hactive = { 800, 800, 800 },
3722 .hfront_porch = { 1, 40, 255 },
3723 .hback_porch = { 1, 40, 87 },
3724 .hsync_len = { 1, 48, 87 },
3725 .vactive = { 480, 480, 480 },
3726 .vfront_porch = { 1, 13, 255 },
3727 .vback_porch = { 1, 29, 29 },
3728 .vsync_len = { 3, 3, 31 },
3729 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3730 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3731};
3732
3733static const struct panel_desc ontat_kd50g21_40nt_a1 = {
3734 .timings = &ontat_kd50g21_40nt_a1_timing,
3735 .num_timings = 1,
3736 .bpc = 8,
3737 .size = {
3738 .width = 108,
3739 .height = 65,
3740 },
3741 .delay = {
3742 .prepare = 147, /* 5 VSDs */
3743 .enable = 147, /* 5 VSDs */
3744 .disable = 88, /* 3 VSDs */
3745 .unprepare = 117, /* 4 VSDs */
3746 },
3747 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3748 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3749 .connector_type = DRM_MODE_CONNECTOR_DPI,
3750};
3751
e8b6f561
EA		 3752/*
3753 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3754 * pixel clocks, but this is the timing that was being used in the Adafruit
3755 * installation instructions.
3756 */
3757static const struct drm_display_mode ontat_yx700wv03_mode = {
3758 .clock = 29500,
3759 .hdisplay = 800,
3760 .hsync_start = 824,
3761 .hsync_end = 896,
3762 .htotal = 992,
3763 .vdisplay = 480,
3764 .vsync_start = 483,
3765 .vsync_end = 493,
3766 .vtotal = 500,
e8b6f561
EA		 3767 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3768};
3769
3770/*
3771 * Specification at:
3772 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3773 */
3774static const struct panel_desc ontat_yx700wv03 = {
3775 .modes = &ontat_yx700wv03_mode,
3776 .num_modes = 1,
3777 .bpc = 8,
3778 .size = {
3779 .width = 154,
3780 .height = 83,
3781 },
5651e5e0 3782 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 3783};
3784
9c31dcb6 3785static const struct drm_display_mode ortustech_com37h3m_mode = {
855e764d 3786 .clock = 22230,
9c31dcb6 3787 .hdisplay = 480,
855e764d
NS		 3788 .hsync_start = 480 + 40,
3789 .hsync_end = 480 + 40 + 10,
3790 .htotal = 480 + 40 + 10 + 40,
9c31dcb6
NS		 3791 .vdisplay = 640,
3792 .vsync_start = 640 + 4,
855e764d
NS		 3793 .vsync_end = 640 + 4 + 2,
3794 .vtotal = 640 + 4 + 2 + 4,
9c31dcb6
NS		 3795 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3796};
3797
3798static const struct panel_desc ortustech_com37h3m = {
3799 .modes = &ortustech_com37h3m_mode,
3800 .num_modes = 1,
3801 .bpc = 8,
3802 .size = {
3803 .width = 56, /* 56.16mm */
3804 .height = 75, /* 74.88mm */
3805 },
3806 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3807 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
9c31dcb6
NS		 3808 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3809};
3810
725c9d40
PZ		 3811static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3812 .clock = 25000,
3813 .hdisplay = 480,
3814 .hsync_start = 480 + 10,
3815 .hsync_end = 480 + 10 + 10,
3816 .htotal = 480 + 10 + 10 + 15,
3817 .vdisplay = 800,
3818 .vsync_start = 800 + 3,
3819 .vsync_end = 800 + 3 + 3,
3820 .vtotal = 800 + 3 + 3 + 3,
725c9d40
PZ		 3821};
3822
3823static const struct panel_desc ortustech_com43h4m85ulc = {
3824 .modes = &ortustech_com43h4m85ulc_mode,
3825 .num_modes = 1,
3b809516 3826 .bpc = 6,
725c9d40
PZ		 3827 .size = {
3828 .width = 56,
3829 .height = 93,
3830 },
f098f168 3831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 3832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2ccedf46 3833 .connector_type = DRM_MODE_CONNECTOR_DPI,
725c9d40
PZ		 3834};
3835
163f7a35
LP		 3836static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3837 .clock = 33000,
3838 .hdisplay = 800,
3839 .hsync_start = 800 + 210,
3840 .hsync_end = 800 + 210 + 30,
3841 .htotal = 800 + 210 + 30 + 16,
3842 .vdisplay = 480,
3843 .vsync_start = 480 + 22,
3844 .vsync_end = 480 + 22 + 13,
3845 .vtotal = 480 + 22 + 13 + 10,
163f7a35
LP		 3846 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3847};
3848
3849static const struct panel_desc osddisplays_osd070t1718_19ts = {
3850 .modes = &osddisplays_osd070t1718_19ts_mode,
3851 .num_modes = 1,
3852 .bpc = 8,
3853 .size = {
3854 .width = 152,
3855 .height = 91,
3856 },
3857 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
fb0629ee
TV		 3858 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3859 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
a793f0ee 3860 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 3861};
3862
4ba3e563
EH		 3863static const struct drm_display_mode pda_91_00156_a0_mode = {
3864 .clock = 33300,
3865 .hdisplay = 800,
3866 .hsync_start = 800 + 1,
3867 .hsync_end = 800 + 1 + 64,
3868 .htotal = 800 + 1 + 64 + 64,
3869 .vdisplay = 480,
3870 .vsync_start = 480 + 1,
3871 .vsync_end = 480 + 1 + 23,
3872 .vtotal = 480 + 1 + 23 + 22,
4ba3e563
EH		 3873};
3874
3875static const struct panel_desc pda_91_00156_a0 = {
3876 .modes = &pda_91_00156_a0_mode,
3877 .num_modes = 1,
3878 .size = {
3879 .width = 152,
3880 .height = 91,
3881 },
3882 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3883};
3884
6374a100
AG		 3885static const struct drm_display_mode powertip_ph128800t004_zza01_mode = {
3886 .clock = 71150,
3887 .hdisplay = 1280,
3888 .hsync_start = 1280 + 48,
3889 .hsync_end = 1280 + 48 + 32,
3890 .htotal = 1280 + 48 + 32 + 80,
3891 .vdisplay = 800,
3892 .vsync_start = 800 + 9,
3893 .vsync_end = 800 + 9 + 8,
3894 .vtotal = 800 + 9 + 8 + 6,
3895 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3896};
3897
3898static const struct panel_desc powertip_ph128800t004_zza01 = {
3899 .modes = &powertip_ph128800t004_zza01_mode,
3900 .num_modes = 1,
3901 .bpc = 8,
3902 .size = {
3903 .width = 216,
3904 .height = 135,
3905 },
3906 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3907 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3908 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3909};
3910
fd6aa8f2
NM		 3911static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = {
3912 .clock = 66500,
3913 .hdisplay = 1280,
3914 .hsync_start = 1280 + 12,
3915 .hsync_end = 1280 + 12 + 20,
3916 .htotal = 1280 + 12 + 20 + 56,
3917 .vdisplay = 800,
3918 .vsync_start = 800 + 1,
3919 .vsync_end = 800 + 1 + 3,
3920 .vtotal = 800 + 1 + 3 + 20,
3921 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3922};
3923
3924static const struct panel_desc powertip_ph128800t006_zhc01 = {
3925 .modes = &powertip_ph128800t006_zhc01_mode,
3926 .num_modes = 1,
3927 .bpc = 8,
3928 .size = {
3929 .width = 216,
3930 .height = 135,
3931 },
3932 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3933 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3934 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3935};
3936
d69de69f
MV		 3937static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3938 .clock = 24750,
3939 .hdisplay = 800,
3940 .hsync_start = 800 + 54,
3941 .hsync_end = 800 + 54 + 2,
3942 .htotal = 800 + 54 + 2 + 44,
3943 .vdisplay = 480,
3944 .vsync_start = 480 + 49,
3945 .vsync_end = 480 + 49 + 2,
3946 .vtotal = 480 + 49 + 2 + 22,
1c519980 3947 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
d69de69f
MV		 3948};
3949
3950static const struct panel_desc powertip_ph800480t013_idf02 = {
3951 .modes = &powertip_ph800480t013_idf02_mode,
3952 .num_modes = 1,
65f4937f 3953 .bpc = 8,
d69de69f
MV		 3954 .size = {
3955 .width = 152,
3956 .height = 91,
3957 },
3958 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3959 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3960 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3961 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3962 .connector_type = DRM_MODE_CONNECTOR_DPI,
3963};
4ba3e563 3964
8d1330d2
PF		 3965static const struct drm_display_mode primeview_pm070wl4_mode = {
3966 .clock = 32000,
3967 .hdisplay = 800,
3968 .hsync_start = 800 + 42,
3969 .hsync_end = 800 + 42 + 128,
3970 .htotal = 800 + 42 + 128 + 86,
3971 .vdisplay = 480,
3972 .vsync_start = 480 + 10,
3973 .vsync_end = 480 + 10 + 2,
3974 .vtotal = 480 + 10 + 2 + 33,
3975 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3976};
3977
3978static const struct panel_desc primeview_pm070wl4 = {
3979 .modes = &primeview_pm070wl4_mode,
3980 .num_modes = 1,
3981 .bpc = 6,
3982 .size = {
3983 .width = 152,
3984 .height = 91,
3985 },
3986 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3987 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3988 .connector_type = DRM_MODE_CONNECTOR_DPI,
3989};
3990
d2a6f0f5
JW		 3991static const struct drm_display_mode qd43003c0_40_mode = {
3992 .clock = 9000,
3993 .hdisplay = 480,
3994 .hsync_start = 480 + 8,
3995 .hsync_end = 480 + 8 + 4,
3996 .htotal = 480 + 8 + 4 + 39,
3997 .vdisplay = 272,
3998 .vsync_start = 272 + 4,
3999 .vsync_end = 272 + 4 + 10,
4000 .vtotal = 272 + 4 + 10 + 2,
d2a6f0f5
JW		 4001};
4002
4003static const struct panel_desc qd43003c0_40 = {
4004 .modes = &qd43003c0_40_mode,
4005 .num_modes = 1,
4006 .bpc = 8,
4007 .size = {
4008 .width = 95,
4009 .height = 53,
4010 },
4011 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4012};
4013
49179e66
AV		 4014static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
4015 { /* 60 Hz */
4016 .clock = 10800,
4017 .hdisplay = 480,
4018 .hsync_start = 480 + 77,
4019 .hsync_end = 480 + 77 + 41,
4020 .htotal = 480 + 77 + 41 + 2,
4021 .vdisplay = 272,
4022 .vsync_start = 272 + 16,
4023 .vsync_end = 272 + 16 + 10,
4024 .vtotal = 272 + 16 + 10 + 2,
4025 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4026 },
4027 { /* 50 Hz */
4028 .clock = 10800,
4029 .hdisplay = 480,
4030 .hsync_start = 480 + 17,
4031 .hsync_end = 480 + 17 + 41,
4032 .htotal = 480 + 17 + 41 + 2,
4033 .vdisplay = 272,
4034 .vsync_start = 272 + 116,
4035 .vsync_end = 272 + 116 + 10,
4036 .vtotal = 272 + 116 + 10 + 2,
4037 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4038 },
4039};
4040
4041static const struct panel_desc qishenglong_gopher2b_lcd = {
4042 .modes = qishenglong_gopher2b_lcd_modes,
4043 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
4044 .bpc = 8,
4045 .size = {
4046 .width = 95,
4047 .height = 54,
4048 },
4049 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4050 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4051 .connector_type = DRM_MODE_CONNECTOR_DPI,
4052};
4053
13cdd12a
DB		 4054static const struct display_timing rocktech_rk043fn48h_timing = {
4055 .pixelclock = { 6000000, 9000000, 12000000 },
4056 .hactive = { 480, 480, 480 },
4057 .hback_porch = { 8, 43, 43 },
c9424076 4058 .hfront_porch = { 2, 8, 10 },
13cdd12a
DB		 4059 .hsync_len = { 1, 1, 1 },
4060 .vactive = { 272, 272, 272 },
c9424076 4061 .vback_porch = { 2, 12, 26 },
13cdd12a
DB		 4062 .vfront_porch = { 1, 4, 4 },
4063 .vsync_len = { 1, 10, 10 },
4064 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
536090b6
RGP		 4065 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
4066 DISPLAY_FLAGS_SYNC_POSEDGE,
13cdd12a
DB		 4067};
4068
4069static const struct panel_desc rocktech_rk043fn48h = {
4070 .timings = &rocktech_rk043fn48h_timing,
4071 .num_timings = 1,
4072 .bpc = 8,
4073 .size = {
4074 .width = 95,
4075 .height = 54,
4076 },
4077 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4078 .connector_type = DRM_MODE_CONNECTOR_DPI,
4079};
4080
23167fa9
JT		 4081static const struct display_timing rocktech_rk070er9427_timing = {
4082 .pixelclock = { 26400000, 33300000, 46800000 },
4083 .hactive = { 800, 800, 800 },
4084 .hfront_porch = { 16, 210, 354 },
4085 .hback_porch = { 46, 46, 46 },
4086 .hsync_len = { 1, 1, 1 },
4087 .vactive = { 480, 480, 480 },
4088 .vfront_porch = { 7, 22, 147 },
4089 .vback_porch = { 23, 23, 23 },
4090 .vsync_len = { 1, 1, 1 },
4091 .flags = DISPLAY_FLAGS_DE_HIGH,
4092};
4093
4094static const struct panel_desc rocktech_rk070er9427 = {
4095 .timings = &rocktech_rk070er9427_timing,
4096 .num_timings = 1,
4097 .bpc = 6,
4098 .size = {
4099 .width = 154,
4100 .height = 86,
4101 },
4102 .delay = {
4103 .prepare = 41,
4104 .enable = 50,
4105 .unprepare = 41,
4106 .disable = 50,
4107 },
4108 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4109};
4110
f305047b
JS		 4111static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
4112 .clock = 71100,
4113 .hdisplay = 1280,
4114 .hsync_start = 1280 + 48,
4115 .hsync_end = 1280 + 48 + 32,
4116 .htotal = 1280 + 48 + 32 + 80,
4117 .vdisplay = 800,
4118 .vsync_start = 800 + 2,
4119 .vsync_end = 800 + 2 + 5,
4120 .vtotal = 800 + 2 + 5 + 16,
f305047b
JS		 4121};
4122
4123static const struct panel_desc rocktech_rk101ii01d_ct = {
4124 .modes = &rocktech_rk101ii01d_ct_mode,
f85b3f80 4125 .bpc = 8,
f305047b
JS		 4126 .num_modes = 1,
4127 .size = {
4128 .width = 217,
4129 .height = 136,
4130 },
4131 .delay = {
4132 .prepare = 50,
4133 .disable = 50,
4134 },
4135 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4138};
4139
a6aa679a
MJ		 4140static const struct display_timing samsung_ltl101al01_timing = {
4141 .pixelclock = { 66663000, 66663000, 66663000 },
4142 .hactive = { 1280, 1280, 1280 },
4143 .hfront_porch = { 18, 18, 18 },
4144 .hback_porch = { 36, 36, 36 },
4145 .hsync_len = { 16, 16, 16 },
4146 .vactive = { 800, 800, 800 },
4147 .vfront_porch = { 4, 4, 4 },
4148 .vback_porch = { 16, 16, 16 },
4149 .vsync_len = { 3, 3, 3 },
4150 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4151};
4152
4153static const struct panel_desc samsung_ltl101al01 = {
4154 .timings = &samsung_ltl101al01_timing,
4155 .num_timings = 1,
4156 .bpc = 8,
4157 .size = {
4158 .width = 217,
4159 .height = 135,
4160 },
4161 .delay = {
4162 .prepare = 40,
4163 .enable = 300,
4164 .disable = 200,
4165 .unprepare = 600,
4166 },
4167 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4168 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4169};
4170
6d54e3d2
MD		 4171static const struct drm_display_mode samsung_ltn101nt05_mode = {
4172 .clock = 54030,
4173 .hdisplay = 1024,
4174 .hsync_start = 1024 + 24,
4175 .hsync_end = 1024 + 24 + 136,
4176 .htotal = 1024 + 24 + 136 + 160,
4177 .vdisplay = 600,
4178 .vsync_start = 600 + 3,
4179 .vsync_end = 600 + 3 + 6,
4180 .vtotal = 600 + 3 + 6 + 61,
6d54e3d2
MD		 4181};
4182
4183static const struct panel_desc samsung_ltn101nt05 = {
4184 .modes = &samsung_ltn101nt05_mode,
4185 .num_modes = 1,
0208d511 4186 .bpc = 6,
6d54e3d2 4187 .size = {
81598846
TR		 4188 .width = 223,
4189 .height = 125,
6d54e3d2 4190 },
85560829 4191 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 4192 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 4193 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6d54e3d2
MD		 4194};
4195
44c58c52
MR		 4196static const struct display_timing satoz_sat050at40h12r2_timing = {
4197 .pixelclock = {33300000, 33300000, 50000000},
4198 .hactive = {800, 800, 800},
4199 .hfront_porch = {16, 210, 354},
4200 .hback_porch = {46, 46, 46},
4201 .hsync_len = {1, 1, 40},
4202 .vactive = {480, 480, 480},
4203 .vfront_porch = {7, 22, 147},
4204 .vback_porch = {23, 23, 23},
4205 .vsync_len = {1, 1, 20},
4206};
4207
4208static const struct panel_desc satoz_sat050at40h12r2 = {
4209 .timings = &satoz_sat050at40h12r2_timing,
4210 .num_timings = 1,
4211 .bpc = 8,
4212 .size = {
4213 .width = 108,
4214 .height = 65,
4215 },
34ca6b53 4216 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
44c58c52
MR		 4217 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4218};
4219
dda0e4bd
NS		 4220static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
4221 .clock = 33260,
4222 .hdisplay = 800,
4223 .hsync_start = 800 + 64,
4224 .hsync_end = 800 + 64 + 128,
4225 .htotal = 800 + 64 + 128 + 64,
4226 .vdisplay = 480,
4227 .vsync_start = 480 + 8,
4228 .vsync_end = 480 + 8 + 2,
4229 .vtotal = 480 + 8 + 2 + 35,
dda0e4bd
NS		 4230 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4231};
4232
4233static const struct panel_desc sharp_lq070y3dg3b = {
4234 .modes = &sharp_lq070y3dg3b_mode,
4235 .num_modes = 1,
4236 .bpc = 8,
4237 .size = {
4238 .width = 152, /* 152.4mm */
4239 .height = 91, /* 91.4mm */
4240 },
4241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4242 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
dda0e4bd
NS		 4243 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
4244};
4245
03e3ec9a
VZ		 4246static const struct drm_display_mode sharp_lq035q7db03_mode = {
4247 .clock = 5500,
4248 .hdisplay = 240,
4249 .hsync_start = 240 + 16,
4250 .hsync_end = 240 + 16 + 7,
4251 .htotal = 240 + 16 + 7 + 5,
4252 .vdisplay = 320,
4253 .vsync_start = 320 + 9,
4254 .vsync_end = 320 + 9 + 1,
4255 .vtotal = 320 + 9 + 1 + 7,
03e3ec9a
VZ		 4256};
4257
4258static const struct panel_desc sharp_lq035q7db03 = {
4259 .modes = &sharp_lq035q7db03_mode,
4260 .num_modes = 1,
4261 .bpc = 6,
4262 .size = {
4263 .width = 54,
4264 .height = 72,
4265 },
4266 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4267};
4268
592aa02b
JC		 4269static const struct display_timing sharp_lq101k1ly04_timing = {
4270 .pixelclock = { 60000000, 65000000, 80000000 },
4271 .hactive = { 1280, 1280, 1280 },
4272 .hfront_porch = { 20, 20, 20 },
4273 .hback_porch = { 20, 20, 20 },
4274 .hsync_len = { 10, 10, 10 },
4275 .vactive = { 800, 800, 800 },
4276 .vfront_porch = { 4, 4, 4 },
4277 .vback_porch = { 4, 4, 4 },
4278 .vsync_len = { 4, 4, 4 },
4279 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
4280};
4281
4282static const struct panel_desc sharp_lq101k1ly04 = {
4283 .timings = &sharp_lq101k1ly04_timing,
4284 .num_timings = 1,
4285 .bpc = 8,
4286 .size = {
4287 .width = 217,
4288 .height = 136,
4289 },
4290 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 4291 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 4292};
4293
656b7596 4294static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
e6c21e6f
PC		 4295 { /* 50 Hz */
4296 .clock = 3000,
4297 .hdisplay = 240,
4298 .hsync_start = 240 + 58,
4299 .hsync_end = 240 + 58 + 1,
4300 .htotal = 240 + 58 + 1 + 1,
4301 .vdisplay = 160,
4302 .vsync_start = 160 + 24,
4303 .vsync_end = 160 + 24 + 10,
4304 .vtotal = 160 + 24 + 10 + 6,
4305 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4306 },
656b7596 4307 { /* 60 Hz */
c1bd32b5 4308 .clock = 3000,
656b7596 4309 .hdisplay = 240,
c1bd32b5
PC		 4310 .hsync_start = 240 + 8,
4311 .hsync_end = 240 + 8 + 1,
4312 .htotal = 240 + 8 + 1 + 1,
656b7596 4313 .vdisplay = 160,
c1bd32b5
PC		 4314 .vsync_start = 160 + 24,
4315 .vsync_end = 160 + 24 + 10,
4316 .vtotal = 160 + 24 + 10 + 6,
656b7596
PC		 4317 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
4318 },
f1bd37f3
PC		 4319};
4320
4321static const struct panel_desc sharp_ls020b1dd01d = {
656b7596
PC		 4322 .modes = sharp_ls020b1dd01d_modes,
4323 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
f1bd37f3
PC		 4324 .bpc = 6,
4325 .size = {
4326 .width = 42,
4327 .height = 28,
4328 },
4329 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
4330 .bus_flags = DRM_BUS_FLAG_DE_HIGH
f5436f77 4331 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
f1bd37f3
PC		 4332 | DRM_BUS_FLAG_SHARP_SIGNALS,
4333};
4334
9c6615bc
BB		 4335static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
4336 .clock = 33300,
4337 .hdisplay = 800,
4338 .hsync_start = 800 + 1,
4339 .hsync_end = 800 + 1 + 64,
4340 .htotal = 800 + 1 + 64 + 64,
4341 .vdisplay = 480,
4342 .vsync_start = 480 + 1,
4343 .vsync_end = 480 + 1 + 23,
4344 .vtotal = 480 + 1 + 23 + 22,
9c6615bc
BB		 4345};
4346
4347static const struct panel_desc shelly_sca07010_bfn_lnn = {
4348 .modes = &shelly_sca07010_bfn_lnn_mode,
4349 .num_modes = 1,
4350 .size = {
4351 .width = 152,
4352 .height = 91,
4353 },
4354 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4355};
4356
105235e4
PR		 4357static const struct drm_display_mode starry_kr070pe2t_mode = {
4358 .clock = 33000,
4359 .hdisplay = 800,
4360 .hsync_start = 800 + 209,
4361 .hsync_end = 800 + 209 + 1,
4362 .htotal = 800 + 209 + 1 + 45,
4363 .vdisplay = 480,
4364 .vsync_start = 480 + 22,
4365 .vsync_end = 480 + 22 + 1,
4366 .vtotal = 480 + 22 + 1 + 22,
105235e4
PR		 4367};
4368
4369static const struct panel_desc starry_kr070pe2t = {
4370 .modes = &starry_kr070pe2t_mode,
4371 .num_modes = 1,
4372 .bpc = 8,
4373 .size = {
4374 .width = 152,
4375 .height = 86,
4376 },
4377 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4378 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
41fad307 4379 .connector_type = DRM_MODE_CONNECTOR_DPI,
105235e4
PR		 4380};
4381
9ff92363
HS		 4382static const struct display_timing startek_kd070wvfpa_mode = {
4383 .pixelclock = { 25200000, 27200000, 30500000 },
4384 .hactive = { 800, 800, 800 },
4385 .hfront_porch = { 19, 44, 115 },
4386 .hback_porch = { 5, 16, 101 },
4387 .hsync_len = { 1, 2, 100 },
4388 .vactive = { 480, 480, 480 },
4389 .vfront_porch = { 5, 43, 67 },
4390 .vback_porch = { 5, 5, 67 },
4391 .vsync_len = { 1, 2, 66 },
4392 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4393 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
4394 DISPLAY_FLAGS_SYNC_POSEDGE,
4395};
4396
4397static const struct panel_desc startek_kd070wvfpa = {
4398 .timings = &startek_kd070wvfpa_mode,
4399 .num_timings = 1,
4400 .bpc = 8,
4401 .size = {
4402 .width = 152,
4403 .height = 91,
4404 },
4405 .delay = {
4406 .prepare = 20,
4407 .enable = 200,
4408 .disable = 200,
4409 },
4410 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4411 .connector_type = DRM_MODE_CONNECTOR_DPI,
4412 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
4413 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
4414 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
4415};
4416
938db276
MV		 4417static const struct display_timing tsd_tst043015cmhx_timing = {
4418 .pixelclock = { 5000000, 9000000, 12000000 },
4419 .hactive = { 480, 480, 480 },
4420 .hfront_porch = { 4, 5, 65 },
4421 .hback_porch = { 36, 40, 255 },
4422 .hsync_len = { 1, 1, 1 },
4423 .vactive = { 272, 272, 272 },
4424 .vfront_porch = { 2, 8, 97 },
4425 .vback_porch = { 3, 8, 31 },
4426 .vsync_len = { 1, 1, 1 },
4427
4428 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
4429 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
4430};
4431
4432static const struct panel_desc tsd_tst043015cmhx = {
4433 .timings = &tsd_tst043015cmhx_timing,
4434 .num_timings = 1,
4435 .bpc = 8,
4436 .size = {
4437 .width = 105,
4438 .height = 67,
4439 },
4440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4442};
4443
42161531
JS		 4444static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4445 .clock = 30000,
4446 .hdisplay = 800,
4447 .hsync_start = 800 + 39,
4448 .hsync_end = 800 + 39 + 47,
4449 .htotal = 800 + 39 + 47 + 39,
4450 .vdisplay = 480,
4451 .vsync_start = 480 + 13,
4452 .vsync_end = 480 + 13 + 2,
4453 .vtotal = 480 + 13 + 2 + 29,
42161531
JS		 4454};
4455
4456static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4457 .modes = &tfc_s9700rtwv43tr_01b_mode,
4458 .num_modes = 1,
4459 .bpc = 8,
4460 .size = {
4461 .width = 155,
4462 .height = 90,
4463 },
4464 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4465 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
42161531
JS		 4466};
4467
adb973ef
GB		 4468static const struct display_timing tianma_tm070jdhg30_timing = {
4469 .pixelclock = { 62600000, 68200000, 78100000 },
4470 .hactive = { 1280, 1280, 1280 },
4471 .hfront_porch = { 15, 64, 159 },
4472 .hback_porch = { 5, 5, 5 },
4473 .hsync_len = { 1, 1, 256 },
4474 .vactive = { 800, 800, 800 },
4475 .vfront_porch = { 3, 40, 99 },
4476 .vback_porch = { 2, 2, 2 },
4477 .vsync_len = { 1, 1, 128 },
4478 .flags = DISPLAY_FLAGS_DE_HIGH,
4479};
4480
4481static const struct panel_desc tianma_tm070jdhg30 = {
4482 .timings = &tianma_tm070jdhg30_timing,
4483 .num_timings = 1,
4484 .bpc = 8,
4485 .size = {
4486 .width = 151,
4487 .height = 95,
4488 },
4489 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 4490 .connector_type = DRM_MODE_CONNECTOR_LVDS,
45dd7df2 4491 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
adb973ef
GB		 4492};
4493
b3bfcdf8
MM		 4494static const struct panel_desc tianma_tm070jvhg33 = {
4495 .timings = &tianma_tm070jdhg30_timing,
4496 .num_timings = 1,
4497 .bpc = 8,
4498 .size = {
4499 .width = 150,
4500 .height = 94,
4501 },
4502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4503 .connector_type = DRM_MODE_CONNECTOR_LVDS,
45dd7df2 4504 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
b3bfcdf8
MM		 4505};
4506
bf6daaa2 4507/*
178ac975
LC		 4508 * The TM070JDHG34-00 datasheet computes total blanking as back porch +
4509 * front porch, not including sync pulse width. This is for both H and
4510 * V. To make the total blanking and period correct, subtract the pulse
4511 * width from the front porch.
bf6daaa2
LC		 4512 *
4513 * This works well for the Min and Typ values, but for Max values the sync
4514 * pulse width is higher than back porch + front porch, so work around that
4515 * by reducing the Max sync length value to 1 and then treating the Max
4516 * porches as in the Min and Typ cases.
4517 *
4518 * Exact datasheet values are added as a comment where they differ from the
4519 * ones implemented for the above reason.
178ac975
LC		 4520 *
4521 * The P0700WXF1MBAA datasheet is even less detailed, only listing period
4522 * and total blanking time, however the resulting values are the same as
4523 * the TM070JDHG34-00.
bf6daaa2
LC		 4524 */
4525static const struct display_timing tianma_tm070jdhg34_00_timing = {
4526 .pixelclock = { 68400000, 71900000, 78100000 },
4527 .hactive = { 1280, 1280, 1280 },
4528 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */
4529 .hback_porch = { 5, 5, 5 },
4530 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */
4531 .vactive = { 800, 800, 800 },
4532 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */
4533 .vback_porch = { 2, 2, 2 },
4534 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */
4535 .flags = DISPLAY_FLAGS_DE_HIGH,
4536};
4537
4538static const struct panel_desc tianma_tm070jdhg34_00 = {
4539 .timings = &tianma_tm070jdhg34_00_timing,
4540 .num_timings = 1,
4541 .bpc = 8,
4542 .size = {
4543 .width = 150, /* 149.76 */
4544 .height = 94, /* 93.60 */
4545 },
716c75af
LC		 4546 .delay = {
4547 .prepare = 15, /* Tp1 */
4548 .enable = 150, /* Tp2 */
4549 .disable = 150, /* Tp4 */
4550 .unprepare = 120, /* Tp3 */
4551 },
bf6daaa2
LC		 4552 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4553 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4554};
4555
178ac975
LC		 4556static const struct panel_desc tianma_p0700wxf1mbaa = {
4557 .timings = &tianma_tm070jdhg34_00_timing,
4558 .num_timings = 1,
4559 .bpc = 8,
4560 .size = {
4561 .width = 150, /* 149.76 */
4562 .height = 94, /* 93.60 */
4563 },
4564 .delay = {
4565 .prepare = 18, /* Tr + Tp1 */
4566 .enable = 152, /* Tp2 + Tp5 */
4567 .disable = 152, /* Tp6 + Tp4 */
4568 .unprepare = 120, /* Tp3 */
4569 },
4570 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4571 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4572};
4573
870a0b12
LM		 4574static const struct display_timing tianma_tm070rvhg71_timing = {
4575 .pixelclock = { 27700000, 29200000, 39600000 },
4576 .hactive = { 800, 800, 800 },
4577 .hfront_porch = { 12, 40, 212 },
4578 .hback_porch = { 88, 88, 88 },
4579 .hsync_len = { 1, 1, 40 },
4580 .vactive = { 480, 480, 480 },
4581 .vfront_porch = { 1, 13, 88 },
4582 .vback_porch = { 32, 32, 32 },
4583 .vsync_len = { 1, 1, 3 },
4584 .flags = DISPLAY_FLAGS_DE_HIGH,
4585};
4586
4587static const struct panel_desc tianma_tm070rvhg71 = {
4588 .timings = &tianma_tm070rvhg71_timing,
4589 .num_timings = 1,
4590 .bpc = 8,
4591 .size = {
4592 .width = 154,
4593 .height = 86,
4594 },
4595 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 4596 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 4597};
4598
d8a0d6a3
LW		 4599static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4600 {
4601 .clock = 10000,
4602 .hdisplay = 320,
4603 .hsync_start = 320 + 50,
4604 .hsync_end = 320 + 50 + 6,
4605 .htotal = 320 + 50 + 6 + 38,
4606 .vdisplay = 240,
4607 .vsync_start = 240 + 3,
4608 .vsync_end = 240 + 3 + 1,
4609 .vtotal = 240 + 3 + 1 + 17,
d8a0d6a3
LW		 4610 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4611 },
4612};
4613
4614static const struct panel_desc ti_nspire_cx_lcd_panel = {
4615 .modes = ti_nspire_cx_lcd_mode,
4616 .num_modes = 1,
4617 .bpc = 8,
4618 .size = {
4619 .width = 65,
4620 .height = 49,
4621 },
4622 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4623 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d8a0d6a3
LW		 4624};
4625
4626static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4627 {
4628 .clock = 10000,
4629 .hdisplay = 320,
4630 .hsync_start = 320 + 6,
4631 .hsync_end = 320 + 6 + 6,
4632 .htotal = 320 + 6 + 6 + 6,
4633 .vdisplay = 240,
4634 .vsync_start = 240 + 0,
4635 .vsync_end = 240 + 0 + 1,
4636 .vtotal = 240 + 0 + 1 + 0,
d8a0d6a3
LW		 4637 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4638 },
4639};
4640
4641static const struct panel_desc ti_nspire_classic_lcd_panel = {
4642 .modes = ti_nspire_classic_lcd_mode,
4643 .num_modes = 1,
4644 /* The grayscale panel has 8 bit for the color .. Y (black) */
4645 .bpc = 8,
4646 .size = {
4647 .width = 71,
4648 .height = 53,
4649 },
4650 /* This is the grayscale bus format */
4651 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
f5436f77 4652 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
d8a0d6a3
LW		 4653};
4654
652be03b
AF		 4655static const struct display_timing topland_tian_g07017_01_timing = {
4656 .pixelclock = { 44900000, 51200000, 63000000 },
4657 .hactive = { 1024, 1024, 1024 },
4658 .hfront_porch = { 16, 160, 216 },
4659 .hback_porch = { 160, 160, 160 },
4660 .hsync_len = { 1, 1, 140 },
4661 .vactive = { 600, 600, 600 },
4662 .vfront_porch = { 1, 12, 127 },
4663 .vback_porch = { 23, 23, 23 },
4664 .vsync_len = { 1, 1, 20 },
4665};
4666
4667static const struct panel_desc topland_tian_g07017_01 = {
4668 .timings = &topland_tian_g07017_01_timing,
4669 .num_timings = 1,
4670 .bpc = 8,
4671 .size = {
4672 .width = 154,
4673 .height = 86,
4674 },
4675 .delay = {
4676 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */
4677 .enable = 100, /* 6.4 - Power on: 6 VSyncs */
4678 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */
4679 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */
4680 },
4681 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4682 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4683 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4684};
4685
06e733e4
LS		 4686static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4687 .clock = 79500,
4688 .hdisplay = 1280,
4689 .hsync_start = 1280 + 192,
4690 .hsync_end = 1280 + 192 + 128,
4691 .htotal = 1280 + 192 + 128 + 64,
4692 .vdisplay = 768,
4693 .vsync_start = 768 + 20,
4694 .vsync_end = 768 + 20 + 7,
4695 .vtotal = 768 + 20 + 7 + 3,
06e733e4
LS		 4696};
4697
4698static const struct panel_desc toshiba_lt089ac29000 = {
4699 .modes = &toshiba_lt089ac29000_mode,
4700 .num_modes = 1,
4701 .size = {
4702 .width = 194,
4703 .height = 116,
4704 },
9781bd1d 4705 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
c4715837 4706 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 4707 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 4708};
4709
227e4f40
BD		 4710static const struct drm_display_mode tpk_f07a_0102_mode = {
4711 .clock = 33260,
4712 .hdisplay = 800,
4713 .hsync_start = 800 + 40,
4714 .hsync_end = 800 + 40 + 128,
4715 .htotal = 800 + 40 + 128 + 88,
4716 .vdisplay = 480,
4717 .vsync_start = 480 + 10,
4718 .vsync_end = 480 + 10 + 2,
4719 .vtotal = 480 + 10 + 2 + 33,
227e4f40
BD		 4720};
4721
4722static const struct panel_desc tpk_f07a_0102 = {
4723 .modes = &tpk_f07a_0102_mode,
4724 .num_modes = 1,
4725 .size = {
4726 .width = 152,
4727 .height = 91,
4728 },
88bc4178 4729 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 4730};
4731
4732static const struct drm_display_mode tpk_f10a_0102_mode = {
4733 .clock = 45000,
4734 .hdisplay = 1024,
4735 .hsync_start = 1024 + 176,
4736 .hsync_end = 1024 + 176 + 5,
4737 .htotal = 1024 + 176 + 5 + 88,
4738 .vdisplay = 600,
4739 .vsync_start = 600 + 20,
4740 .vsync_end = 600 + 20 + 5,
4741 .vtotal = 600 + 20 + 5 + 25,
227e4f40
BD		 4742};
4743
4744static const struct panel_desc tpk_f10a_0102 = {
4745 .modes = &tpk_f10a_0102_mode,
4746 .num_modes = 1,
4747 .size = {
4748 .width = 223,
4749 .height = 125,
4750 },
4751};
4752
06a9dc65
MS		 4753static const struct display_timing urt_umsh_8596md_timing = {
4754 .pixelclock = { 33260000, 33260000, 33260000 },
4755 .hactive = { 800, 800, 800 },
4756 .hfront_porch = { 41, 41, 41 },
4757 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4758 .hsync_len = { 71, 128, 128 },
4759 .vactive = { 480, 480, 480 },
4760 .vfront_porch = { 10, 10, 10 },
4761 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4762 .vsync_len = { 2, 2, 2 },
4763 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4764 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4765};
4766
4767static const struct panel_desc urt_umsh_8596md_lvds = {
4768 .timings = &urt_umsh_8596md_timing,
4769 .num_timings = 1,
4770 .bpc = 6,
4771 .size = {
4772 .width = 152,
4773 .height = 91,
4774 },
4775 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 4776 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 4777};
4778
4779static const struct panel_desc urt_umsh_8596md_parallel = {
4780 .timings = &urt_umsh_8596md_timing,
4781 .num_timings = 1,
4782 .bpc = 6,
4783 .size = {
4784 .width = 152,
4785 .height = 91,
4786 },
4787 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4788};
4789
1a84a308
NP		 4790static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4791 .clock = 60000,
4792 .hdisplay = 1024,
4793 .hsync_start = 1024 + 160,
4794 .hsync_end = 1024 + 160 + 100,
4795 .htotal = 1024 + 160 + 100 + 60,
4796 .vdisplay = 600,
4797 .vsync_start = 600 + 12,
4798 .vsync_end = 600 + 12 + 10,
4799 .vtotal = 600 + 12 + 10 + 13,
4800};
4801
4802static const struct panel_desc vivax_tpc9150_panel = {
4803 .modes = &vivax_tpc9150_panel_mode,
4804 .num_modes = 1,
4805 .bpc = 6,
4806 .size = {
4807 .width = 200,
4808 .height = 115,
4809 },
4810 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4811 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4812 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4813};
4814
04206185
FE		 4815static const struct drm_display_mode vl050_8048nt_c01_mode = {
4816 .clock = 33333,
4817 .hdisplay = 800,
4818 .hsync_start = 800 + 210,
4819 .hsync_end = 800 + 210 + 20,
4820 .htotal = 800 + 210 + 20 + 46,
4821 .vdisplay = 480,
4822 .vsync_start = 480 + 22,
4823 .vsync_end = 480 + 22 + 10,
4824 .vtotal = 480 + 22 + 10 + 23,
04206185
FE		 4825 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4826};
4827
4828static const struct panel_desc vl050_8048nt_c01 = {
4829 .modes = &vl050_8048nt_c01_mode,
4830 .num_modes = 1,
4831 .bpc = 8,
4832 .size = {
4833 .width = 120,
4834 .height = 76,
4835 },
4836 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4837 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
04206185
FE		 4838};
4839
e4bac408
RG		 4840static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4841 .clock = 6410,
4842 .hdisplay = 320,
4843 .hsync_start = 320 + 20,
4844 .hsync_end = 320 + 20 + 30,
4845 .htotal = 320 + 20 + 30 + 38,
4846 .vdisplay = 240,
4847 .vsync_start = 240 + 4,
4848 .vsync_end = 240 + 4 + 3,
4849 .vtotal = 240 + 4 + 3 + 15,
e4bac408
RG		 4850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4851};
4852
4853static const struct panel_desc winstar_wf35ltiacd = {
4854 .modes = &winstar_wf35ltiacd_mode,
4855 .num_modes = 1,
4856 .bpc = 8,
4857 .size = {
4858 .width = 70,
4859 .height = 53,
4860 },
4861 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4862};
4863
7a1f4fa4
JT		 4864static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4865 .clock = 51200,
4866 .hdisplay = 1024,
4867 .hsync_start = 1024 + 100,
4868 .hsync_end = 1024 + 100 + 100,
4869 .htotal = 1024 + 100 + 100 + 120,
4870 .vdisplay = 600,
4871 .vsync_start = 600 + 10,
4872 .vsync_end = 600 + 10 + 10,
4873 .vtotal = 600 + 10 + 10 + 15,
4874 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4875};
4876
4877static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4878 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4879 .num_modes = 1,
44379b98 4880 .bpc = 8,
7a1f4fa4
JT		 4881 .size = {
4882 .width = 154,
4883 .height = 90,
4884 },
4885 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4886 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4887 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4888};
4889
40da1463
MM		 4890static const struct drm_display_mode mchp_ac69t88a_mode = {
4891 .clock = 25000,
4892 .hdisplay = 800,
4893 .hsync_start = 800 + 88,
4894 .hsync_end = 800 + 88 + 5,
4895 .htotal = 800 + 88 + 5 + 40,
4896 .vdisplay = 480,
4897 .vsync_start = 480 + 23,
4898 .vsync_end = 480 + 23 + 5,
4899 .vtotal = 480 + 23 + 5 + 1,
4900};
4901
4902static const struct panel_desc mchp_ac69t88a = {
4903 .modes = &mchp_ac69t88a_mode,
4904 .num_modes = 1,
4905 .bpc = 8,
4906 .size = {
4907 .width = 108,
4908 .height = 65,
4909 },
4910 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4911 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
4912 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4913};
4914
fcec4163
LW		 4915static const struct drm_display_mode arm_rtsm_mode[] = {
4916 {
4917 .clock = 65000,
4918 .hdisplay = 1024,
4919 .hsync_start = 1024 + 24,
4920 .hsync_end = 1024 + 24 + 136,
4921 .htotal = 1024 + 24 + 136 + 160,
4922 .vdisplay = 768,
4923 .vsync_start = 768 + 3,
4924 .vsync_end = 768 + 3 + 6,
4925 .vtotal = 768 + 3 + 6 + 29,
fcec4163
LW		 4926 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4927 },
4928};
4929
4930static const struct panel_desc arm_rtsm = {
4931 .modes = arm_rtsm_mode,
4932 .num_modes = 1,
4933 .bpc = 8,
4934 .size = {
4935 .width = 400,
4936 .height = 300,
4937 },
4938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4939};
4940
280921de
TR		 4941static const struct of_device_id platform_of_match[] = {
4942 {
bca684e6
JT		 4943 .compatible = "ampire,am-1280800n3tzqw-t00h",
4944 .data = &ampire_am_1280800n3tzqw_t00h,
4945 }, {
966fea78
YF		 4946 .compatible = "ampire,am-480272h3tmqw-t01h",
4947 .data = &ampire_am_480272h3tmqw_t01h,
410bb213
GU		 4948 }, {
4949 .compatible = "ampire,am-800480l1tmqw-t00h",
4950 .data = &ampire_am_800480l1tmqw_t00h,
966fea78 4951 }, {
1c550fa1
PZ		 4952 .compatible = "ampire,am800480r3tmqwa1h",
4953 .data = &ampire_am800480r3tmqwa1h,
103f06fd
BK		 4954 }, {
4955 .compatible = "ampire,am800600p5tmqw-tb8h",
4956 .data = &ampire_am800600p5tmqwtb8h,
fcec4163
LW		 4957 }, {
4958 .compatible = "arm,rtsm-display",
4959 .data = &arm_rtsm,
c479450f
SS		 4960 }, {
4961 .compatible = "armadeus,st0700-adapt",
4962 .data = &armadeus_st0700_adapt,
1c550fa1 4963 }, {
280921de
TR		 4964 .compatible = "auo,b101aw03",
4965 .data = &auo_b101aw03,
dac746e0
RC		 4966 }, {
4967 .compatible = "auo,b101xtn01",
4968 .data = &auo_b101xtn01,
ad3e33fe
DA		 4969 }, {
4970 .compatible = "auo,b116xw03",
4971 .data = &auo_b116xw03,
bccfaffb
LM		 4972 }, {
4973 .compatible = "auo,g070vvn01",
4974 .data = &auo_g070vvn01,
4fb86404
AG		 4975 }, {
4976 .compatible = "auo,g101evn010",
4977 .data = &auo_g101evn010,
4451c287
CF		 4978 }, {
4979 .compatible = "auo,g104sn02",
4980 .data = &auo_g104sn02,
6c2b2cd3
PG		 4981 }, {
4982 .compatible = "auo,g104stn01",
4983 .data = &auo_g104stn01,
03e909ac
SR		 4984 }, {
4985 .compatible = "auo,g121ean01",
4986 .data = &auo_g121ean01,
697035c6
LS		 4987 }, {
4988 .compatible = "auo,g133han01",
4989 .data = &auo_g133han01,
9e52d5c8
EA		 4990 }, {
4991 .compatible = "auo,g156han04",
4992 .data = &auo_g156han04,
d9ccd1f2
SR		 4993 }, {
4994 .compatible = "auo,g156xtn01",
4995 .data = &auo_g156xtn01,
8c31f603
LS		 4996 }, {
4997 .compatible = "auo,g185han01",
4998 .data = &auo_g185han01,
2f7b832f
SR		 4999 }, {
5000 .compatible = "auo,g190ean01",
5001 .data = &auo_g190ean01,
8a45632e
MW		 5002 }, {
5003 .compatible = "auo,p238han01",
5004 .data = &auo_p238han01,
70c0d5b7
LS		 5005 }, {
5006 .compatible = "auo,p320hvn03",
5007 .data = &auo_p320hvn03,
7ee933a1
HS		 5008 }, {
5009 .compatible = "auo,t215hvn01",
5010 .data = &auo_t215hvn01,
d47df633
PZ		 5011 }, {
5012 .compatible = "avic,tm070ddh03",
5013 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 5014 }, {
5015 .compatible = "bananapi,s070wv20-ct16",
5016 .data = &bananapi_s070wv20_ct16,
b554c009
MS		 5017 }, {
5018 .compatible = "boe,av101hdt-a10",
5019 .data = &boe_av101hdt_a10,
d34bd3c7
MS		 5020 }, {
5021 .compatible = "boe,av123z7m-n17",
5022 .data = &boe_av123z7m_n17,
dc90214f
TL		 5023 }, {
5024 .compatible = "boe,bp082wx1-100",
5025 .data = &boe_bp082wx1_100,
eeaddab4
TL		 5026 }, {
5027 .compatible = "boe,bp101wx1-100",
5028 .data = &boe_bp101wx1_100,
8bb7c7bc
LY		 5029 }, {
5030 .compatible = "boe,ev121wxm-n10-1850",
5031 .data = &boe_ev121wxm_n10_1850,
ae8cf41b
AH		 5032 }, {
5033 .compatible = "boe,hv070wsa-100",
5034 .data = &boe_hv070wsa
751b5841
JD		 5035 }, {
5036 .compatible = "cct,cmt430b19n00",
5037 .data = &cct_cmt430b19n00,
e58edce6
GB		 5038 }, {
5039 .compatible = "cdtech,s043wq26h-ct7",
5040 .data = &cdtech_s043wq26h_ct7,
0e3b67f6
MK		 5041 }, {
5042 .compatible = "cdtech,s070pws19hp-fc21",
5043 .data = &cdtech_s070pws19hp_fc21,
5044 }, {
5045 .compatible = "cdtech,s070swv29hg-dc44",
5046 .data = &cdtech_s070swv29hg_dc44,
982f944e
GB		 5047 }, {
5048 .compatible = "cdtech,s070wv95-ct16",
5049 .data = &cdtech_s070wv95_ct16,
07c913c4
MV		 5050 }, {
5051 .compatible = "chefree,ch101olhlwh-002",
5052 .data = &chefree_ch101olhlwh_002,
2cb35c80
RL		 5053 }, {
5054 .compatible = "chunghwa,claa070wp03xg",
5055 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 5056 }, {
5057 .compatible = "chunghwa,claa101wa01a",
5058 .data = &chunghwa_claa101wa01a
280921de
TR		 5059 }, {
5060 .compatible = "chunghwa,claa101wb01",
5061 .data = &chunghwa_claa101wb01
4dd024d4
MV		 5062 }, {
5063 .compatible = "dataimage,fg040346dsswbg04",
5064 .data = &dataimage_fg040346dsswbg04,
803481d8
PO		 5065 }, {
5066 .compatible = "dataimage,fg1001l0dsswmg01",
5067 .data = &dataimage_fg1001l0dsswmg01,
97ceb1fb
MV		 5068 }, {
5069 .compatible = "dataimage,scf0700c48ggu18",
5070 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 5071 }, {
5072 .compatible = "dlc,dlc0700yzg-1",
5073 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 5074 }, {
5075 .compatible = "dlc,dlc1010gig",
5076 .data = &dlc_dlc1010gig,
c2d24af6
AP		 5077 }, {
5078 .compatible = "edt,et035012dm6",
5079 .data = &edt_et035012dm6,
f08a2a1e
SR		 5080 }, {
5081 .compatible = "edt,etm0350g0dh6",
5082 .data = &edt_etm0350g0dh6,
82d57a59
MCR		 5083 }, {
5084 .compatible = "edt,etm043080dh6gp",
5085 .data = &edt_etm043080dh6gp,
fd819bff
MV		 5086 }, {
5087 .compatible = "edt,etm0430g0dh6",
5088 .data = &edt_etm0430g0dh6,
26ab0065
SA		 5089 }, {
5090 .compatible = "edt,et057090dhu",
5091 .data = &edt_et057090dhu,
fff5de45
PZ		 5092 }, {
5093 .compatible = "edt,et070080dh6",
5094 .data = &edt_etm0700g0dh6,
5095 }, {
5096 .compatible = "edt,etm0700g0dh6",
5097 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 5098 }, {
5099 .compatible = "edt,etm0700g0bdh6",
5100 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 5101 }, {
5102 .compatible = "edt,etm0700g0edh6",
5103 .data = &edt_etm0700g0bdh6,
a6cc3c72
MF		 5104 }, {
5105 .compatible = "edt,etml0700y5dha",
5106 .data = &edt_etml0700y5dha,
aeb262c3
PF		 5107 }, {
5108 .compatible = "edt,etml1010g3dra",
5109 .data = &edt_etml1010g3dra,
e46f73fb
SR		 5110 }, {
5111 .compatible = "edt,etmv570g2dhu",
5112 .data = &edt_etmv570g2dhu,
9746f5fe
AF		 5113 }, {
5114 .compatible = "eink,vb3300-kca",
5115 .data = &eink_vb3300_kca,
1319f217
MW		 5116 }, {
5117 .compatible = "evervision,vgg644804",
5118 .data = &evervision_vgg644804,
9158e3c3
MF		 5119 }, {
5120 .compatible = "evervision,vgg804821",
5121 .data = &evervision_vgg804821,
102932b0
BB		 5122 }, {
5123 .compatible = "foxlink,fl500wvr00-a0t",
5124 .data = &foxlink_fl500wvr00_a0t,
7b6bd843
PC		 5125 }, {
5126 .compatible = "frida,frd350h54004",
5127 .data = &frida_frd350h54004,
3be20710
JT		 5128 }, {
5129 .compatible = "friendlyarm,hd702e",
5130 .data = &friendlyarm_hd702e,
d435a2af
PZ		 5131 }, {
5132 .compatible = "giantplus,gpg482739qs5",
5133 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 5134 }, {
5135 .compatible = "giantplus,gpm940b0",
5136 .data = &giantplus_gpm940b0,
a853205e
PZ		 5137 }, {
5138 .compatible = "hannstar,hsd070pww1",
5139 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 5140 }, {
5141 .compatible = "hannstar,hsd100pxn1",
5142 .data = &hannstar_hsd100pxn1,
170a41e9
SR		 5143 }, {
5144 .compatible = "hannstar,hsd101pww2",
5145 .data = &hannstar_hsd101pww2,
61ac0bf8
LS		 5146 }, {
5147 .compatible = "hit,tx23d38vm0caa",
5148 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 5149 }, {
5150 .compatible = "innolux,at043tn24",
5151 .data = &innolux_at043tn24,
4fc24ab3
RB		 5152 }, {
5153 .compatible = "innolux,at070tn92",
5154 .data = &innolux_at070tn92,
1993f598
RL		 5155 }, {
5156 .compatible = "innolux,g070ace-l01",
5157 .data = &innolux_g070ace_l01,
b9d228a5
ST		 5158 }, {
5159 .compatible = "innolux,g070ace-lh3",
5160 .data = &innolux_g070ace_lh3,
1e29b840 5161 }, {
a5d2ade6
CF		 5162 .compatible = "innolux,g070y2-l01",
5163 .data = &innolux_g070y2_l01,
57a06e90
OR		 5164 }, {
5165 .compatible = "innolux,g070y2-t02",
5166 .data = &innolux_g070y2_t02,
a5d2ade6
CF		 5167 }, {
5168 .compatible = "innolux,g101ice-l01",
1e29b840 5169 .data = &innolux_g101ice_l01
d731f661 5170 }, {
a5d2ade6 5171 .compatible = "innolux,g121i1-l01",
d731f661 5172 .data = &innolux_g121i1_l01
f8fa17ba
AB		 5173 }, {
5174 .compatible = "innolux,g121x1-l03",
5175 .data = &innolux_g121x1_l03,
f7ad2ce5
MV		 5176 }, {
5177 .compatible = "innolux,g121xce-l01",
5178 .data = &innolux_g121xce_l01,
eae74888
MV		 5179 }, {
5180 .compatible = "innolux,g156hce-l01",
5181 .data = &innolux_g156hce_l01,
ea44739d
AB		 5182 }, {
5183 .compatible = "innolux,n156bge-l21",
5184 .data = &innolux_n156bge_l21,
bccac3f1
MG		 5185 }, {
5186 .compatible = "innolux,zj070na-01p",
5187 .data = &innolux_zj070na_01p,
14bf60c4
LM		 5188 }, {
5189 .compatible = "koe,tx14d24vm1bpa",
5190 .data = &koe_tx14d24vm1bpa,
8a070524
LY		 5191 }, {
5192 .compatible = "koe,tx26d202vm0bwa",
5193 .data = &koe_tx26d202vm0bwa,
8cfe8341
JT		 5194 }, {
5195 .compatible = "koe,tx31d200vm0baa",
5196 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 5197 }, {
5198 .compatible = "kyo,tcg121xglp",
5199 .data = &kyo_tcg121xglp,
27abdd83
PK		 5200 }, {
5201 .compatible = "lemaker,bl035-rgb-002",
5202 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 5203 }, {
5204 .compatible = "lg,lb070wv8",
5205 .data = &lg_lb070wv8,
ac9b8b7f
AB		 5206 }, {
5207 .compatible = "lincolntech,lcd185-101ct",
5208 .data = &lincolntech_lcd185_101ct,
0d35408a
AF		 5209 }, {
5210 .compatible = "logicpd,type28",
5211 .data = &logicpd_type_28,
5728fe7f
MZ		 5212 }, {
5213 .compatible = "logictechno,lt161010-2nhc",
5214 .data = &logictechno_lt161010_2nh,
5215 }, {
5216 .compatible = "logictechno,lt161010-2nhr",
5217 .data = &logictechno_lt161010_2nh,
5218 }, {
5219 .compatible = "logictechno,lt170410-2whc",
5220 .data = &logictechno_lt170410_2whc,
19f036ea
SA		 5221 }, {
5222 .compatible = "logictechno,lttd800480070-l2rt",
5223 .data = &logictechno_lttd800480070_l2rt,
0c044f7d
SA		 5224 }, {
5225 .compatible = "logictechno,lttd800480070-l6wh-rt",
5226 .data = &logictechno_lttd800480070_l6wh_rt,
f558d676
AB		 5227 }, {
5228 .compatible = "microtips,mf-101hiebcaf0",
5229 .data = &microtips_mf_101hiebcaf0_c,
2c3d1bd2
AB		 5230 }, {
5231 .compatible = "microtips,mf-103hieb0ga0",
5232 .data = &microtips_mf_103hieb0ga0,
65c766ca
LM		 5233 }, {
5234 .compatible = "mitsubishi,aa070mc01-ca1",
5235 .data = &mitsubishi_aa070mc01,
637d3fdc
TW		 5236 }, {
5237 .compatible = "mitsubishi,aa084xe01",
5238 .data = &mitsubishi_aa084xe01,
ba68e690
MV		 5239 }, {
5240 .compatible = "multi-inno,mi0700a2t-30",
5241 .data = &multi_inno_mi0700a2t_30,
a5d092d3
MV		 5242 }, {
5243 .compatible = "multi-inno,mi0700s4t-6",
5244 .data = &multi_inno_mi0700s4t_6,
b55002b9
CN		 5245 }, {
5246 .compatible = "multi-inno,mi0800ft-9",
5247 .data = &multi_inno_mi0800ft_9,
81162f4b
SR		 5248 }, {
5249 .compatible = "multi-inno,mi1010ait-1cp",
5250 .data = &multi_inno_mi1010ait_1cp,
958473e7
MV		 5251 }, {
5252 .compatible = "multi-inno,mi1010z1t-1cp11",
5253 .data = &multi_inno_mi1010z1t_1cp11,
01bacc13
LS		 5254 }, {
5255 .compatible = "nec,nl12880bc20-05",
5256 .data = &nec_nl12880bc20_05,
c6e87f91 5257 }, {
5258 .compatible = "nec,nl4827hc19-05b",
5259 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 5260 }, {
5261 .compatible = "netron-dy,e231732",
5262 .data = &netron_dy_e231732,
3b39ad7a
TV		 5263 }, {
5264 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
5265 .data = &newhaven_nhd_43_480272ef_atxl,
c180b003
AG		 5266 }, {
5267 .compatible = "nlt,nl13676bc25-03f",
5268 .data = &nlt_nl13676bc25_03f,
4177fa66
LS		 5269 }, {
5270 .compatible = "nlt,nl192108ac18-02d",
5271 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 5272 }, {
5273 .compatible = "nvd,9128",
5274 .data = &nvd_9128,
a99fb626
GB		 5275 }, {
5276 .compatible = "okaya,rs800480t-7x0gp",
5277 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 5278 }, {
5279 .compatible = "olimex,lcd-olinuxino-43-ts",
5280 .data = &olimex_lcd_olinuxino_43ts,
91a759d4
LY		 5281 }, {
5282 .compatible = "ontat,kd50g21-40nt-a1",
5283 .data = &ontat_kd50g21_40nt_a1,
e8b6f561
EA		 5284 }, {
5285 .compatible = "ontat,yx700wv03",
5286 .data = &ontat_yx700wv03,
9c31dcb6
NS		 5287 }, {
5288 .compatible = "ortustech,com37h3m05dtc",
5289 .data = &ortustech_com37h3m,
5290 }, {
5291 .compatible = "ortustech,com37h3m99dtc",
5292 .data = &ortustech_com37h3m,
725c9d40
PZ		 5293 }, {
5294 .compatible = "ortustech,com43h4m85ulc",
5295 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 5296 }, {
5297 .compatible = "osddisplays,osd070t1718-19ts",
5298 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 5299 }, {
5300 .compatible = "pda,91-00156-a0",
5301 .data = &pda_91_00156_a0,
6374a100
AG		 5302 }, {
5303 .compatible = "powertip,ph128800t004-zza01",
5304 .data = &powertip_ph128800t004_zza01,
fd6aa8f2
NM		 5305 }, {
5306 .compatible = "powertip,ph128800t006-zhc01",
5307 .data = &powertip_ph128800t006_zhc01,
d69de69f
MV		 5308 }, {
5309 .compatible = "powertip,ph800480t013-idf02",
5310 .data = &powertip_ph800480t013_idf02,
8d1330d2
PF		 5311 }, {
5312 .compatible = "primeview,pm070wl4",
5313 .data = &primeview_pm070wl4,
d2a6f0f5
JW		 5314 }, {
5315 .compatible = "qiaodian,qd43003c0-40",
5316 .data = &qd43003c0_40,
49179e66
AV		 5317 }, {
5318 .compatible = "qishenglong,gopher2b-lcd",
5319 .data = &qishenglong_gopher2b_lcd,
13cdd12a
DB		 5320 }, {
5321 .compatible = "rocktech,rk043fn48h",
5322 .data = &rocktech_rk043fn48h,
23167fa9
JT		 5323 }, {
5324 .compatible = "rocktech,rk070er9427",
5325 .data = &rocktech_rk070er9427,
f305047b
JS		 5326 }, {
5327 .compatible = "rocktech,rk101ii01d-ct",
5328 .data = &rocktech_rk101ii01d_ct,
a6aa679a
MJ		 5329 }, {
5330 .compatible = "samsung,ltl101al01",
5331 .data = &samsung_ltl101al01,
6d54e3d2
MD		 5332 }, {
5333 .compatible = "samsung,ltn101nt05",
5334 .data = &samsung_ltn101nt05,
44c58c52
MR		 5335 }, {
5336 .compatible = "satoz,sat050at40h12r2",
5337 .data = &satoz_sat050at40h12r2,
03e3ec9a
VZ		 5338 }, {
5339 .compatible = "sharp,lq035q7db03",
5340 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 5341 }, {
5342 .compatible = "sharp,lq070y3dg3b",
5343 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 5344 }, {
5345 .compatible = "sharp,lq101k1ly04",
5346 .data = &sharp_lq101k1ly04,
f1bd37f3
PC		 5347 }, {
5348 .compatible = "sharp,ls020b1dd01d",
5349 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 5350 }, {
5351 .compatible = "shelly,sca07010-bfn-lnn",
5352 .data = &shelly_sca07010_bfn_lnn,
105235e4
PR		 5353 }, {
5354 .compatible = "starry,kr070pe2t",
5355 .data = &starry_kr070pe2t,
9ff92363
HS		 5356 }, {
5357 .compatible = "startek,kd070wvfpa",
5358 .data = &startek_kd070wvfpa,
938db276
MV		 5359 }, {
5360 .compatible = "team-source-display,tst043015cmhx",
5361 .data = &tsd_tst043015cmhx,
42161531
JS		 5362 }, {
5363 .compatible = "tfc,s9700rtwv43tr-01b",
5364 .data = &tfc_s9700rtwv43tr_01b,
178ac975
LC		 5365 }, {
5366 .compatible = "tianma,p0700wxf1mbaa",
5367 .data = &tianma_p0700wxf1mbaa,
adb973ef
GB		 5368 }, {
5369 .compatible = "tianma,tm070jdhg30",
5370 .data = &tianma_tm070jdhg30,
bf6daaa2
LC		 5371 }, {
5372 .compatible = "tianma,tm070jdhg34-00",
5373 .data = &tianma_tm070jdhg34_00,
b3bfcdf8
MM		 5374 }, {
5375 .compatible = "tianma,tm070jvhg33",
5376 .data = &tianma_tm070jvhg33,
870a0b12
LM		 5377 }, {
5378 .compatible = "tianma,tm070rvhg71",
5379 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 5380 }, {
5381 .compatible = "ti,nspire-cx-lcd-panel",
5382 .data = &ti_nspire_cx_lcd_panel,
5383 }, {
5384 .compatible = "ti,nspire-classic-lcd-panel",
5385 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 5386 }, {
5387 .compatible = "toshiba,lt089ac29000",
5388 .data = &toshiba_lt089ac29000,
652be03b
AF		 5389 }, {
5390 .compatible = "topland,tian-g07017-01",
5391 .data = &topland_tian_g07017_01,
227e4f40
BD		 5392 }, {
5393 .compatible = "tpk,f07a-0102",
5394 .data = &tpk_f07a_0102,
5395 }, {
5396 .compatible = "tpk,f10a-0102",
5397 .data = &tpk_f10a_0102,
06a9dc65
MS		 5398 }, {
5399 .compatible = "urt,umsh-8596md-t",
5400 .data = &urt_umsh_8596md_parallel,
5401 }, {
5402 .compatible = "urt,umsh-8596md-1t",
5403 .data = &urt_umsh_8596md_parallel,
5404 }, {
5405 .compatible = "urt,umsh-8596md-7t",
5406 .data = &urt_umsh_8596md_parallel,
5407 }, {
5408 .compatible = "urt,umsh-8596md-11t",
5409 .data = &urt_umsh_8596md_lvds,
5410 }, {
5411 .compatible = "urt,umsh-8596md-19t",
5412 .data = &urt_umsh_8596md_lvds,
5413 }, {
5414 .compatible = "urt,umsh-8596md-20t",
5415 .data = &urt_umsh_8596md_parallel,
1a84a308
NP		 5416 }, {
5417 .compatible = "vivax,tpc9150-panel",
5418 .data = &vivax_tpc9150_panel,
04206185
FE		 5419 }, {
5420 .compatible = "vxt,vl050-8048nt-c01",
5421 .data = &vl050_8048nt_c01,
e4bac408
RG		 5422 }, {
5423 .compatible = "winstar,wf35ltiacd",
5424 .data = &winstar_wf35ltiacd,
7a1f4fa4
JT		 5425 }, {
5426 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
5427 .data = &yes_optoelectronics_ytc700tlag_05_201c,
40da1463
MM		 5428 }, {
5429 .compatible = "microchip,ac69t88a",
5430 .data = &mchp_ac69t88a,
4a1d0dbc
SR		 5431 }, {
5432 /* Must be the last entry */
5433 .compatible = "panel-dpi",
f6faebc1
MR		 5434
5435 /*
5436 * Explicitly NULL, the panel_desc structure will be
5437 * allocated by panel_dpi_probe().
5438 */
5439 .data = NULL,
280921de
TR		 5440 }, {
5441 /* sentinel */
5442 }
5443};
5444MODULE_DEVICE_TABLE(of, platform_of_match);
5445
5446static int panel_simple_platform_probe(struct platform_device *pdev)
5447{
921c41e5 5448 struct panel_simple *panel;
280921de 5449
47c08262 5450 panel = panel_simple_probe(&pdev->dev);
921c41e5
MR		 5451 if (IS_ERR(panel))
5452 return PTR_ERR(panel);
5453
5454 return 0;
280921de
TR		 5455}
5456
cef3776d 5457static void panel_simple_platform_remove(struct platform_device *pdev)
280921de 5458{
d72ac4bb 5459 panel_simple_remove(&pdev->dev);
280921de
TR		 5460}
5461
d02fd93e
TR		 5462static void panel_simple_platform_shutdown(struct platform_device *pdev)
5463{
5464 panel_simple_shutdown(&pdev->dev);
5465}
5466
3235b0f2
DA		 5467static const struct dev_pm_ops panel_simple_pm_ops = {
5468 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
5469 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5470 pm_runtime_force_resume)
5471};
5472
280921de
TR		 5473static struct platform_driver panel_simple_platform_driver = {
5474 .driver = {
5475 .name = "panel-simple",
280921de 5476 .of_match_table = platform_of_match,
3235b0f2 5477 .pm = &panel_simple_pm_ops,
280921de
TR		 5478 },
5479 .probe = panel_simple_platform_probe,
e70140ba 5480 .remove = panel_simple_platform_remove,
d02fd93e 5481 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 5482};
5483
d718d79e
TR		 5484static const struct drm_display_mode auo_b080uan01_mode = {
5485 .clock = 154500,
5486 .hdisplay = 1200,
5487 .hsync_start = 1200 + 62,
5488 .hsync_end = 1200 + 62 + 4,
5489 .htotal = 1200 + 62 + 4 + 62,
5490 .vdisplay = 1920,
5491 .vsync_start = 1920 + 9,
5492 .vsync_end = 1920 + 9 + 2,
5493 .vtotal = 1920 + 9 + 2 + 8,
d718d79e
TR		 5494};
5495
5496static const struct panel_desc_dsi auo_b080uan01 = {
5497 .desc = {
5498 .modes = &auo_b080uan01_mode,
5499 .num_modes = 1,
5500 .bpc = 8,
5501 .size = {
5502 .width = 108,
5503 .height = 272,
5504 },
cb62cdec 5505 .connector_type = DRM_MODE_CONNECTOR_DSI,
d718d79e
TR		 5506 },
5507 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
5508 .format = MIPI_DSI_FMT_RGB888,
5509 .lanes = 4,
5510};
5511
c8521969
CZ		 5512static const struct drm_display_mode boe_tv080wum_nl0_mode = {
5513 .clock = 160000,
5514 .hdisplay = 1200,
5515 .hsync_start = 1200 + 120,
5516 .hsync_end = 1200 + 120 + 20,
5517 .htotal = 1200 + 120 + 20 + 21,
5518 .vdisplay = 1920,
5519 .vsync_start = 1920 + 21,
5520 .vsync_end = 1920 + 21 + 3,
5521 .vtotal = 1920 + 21 + 3 + 18,
c8521969
CZ		 5522 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
5523};
5524
5525static const struct panel_desc_dsi boe_tv080wum_nl0 = {
5526 .desc = {
5527 .modes = &boe_tv080wum_nl0_mode,
5528 .num_modes = 1,
5529 .size = {
5530 .width = 107,
5531 .height = 172,
5532 },
cb62cdec 5533 .connector_type = DRM_MODE_CONNECTOR_DSI,
c8521969
CZ		 5534 },
5535 .flags = MIPI_DSI_MODE_VIDEO |
5536 MIPI_DSI_MODE_VIDEO_BURST |
5537 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
5538 .format = MIPI_DSI_FMT_RGB888,
5539 .lanes = 4,
5540};
5541
712ac1ba
AC		 5542static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
5543 .clock = 71000,
5544 .hdisplay = 800,
5545 .hsync_start = 800 + 32,
5546 .hsync_end = 800 + 32 + 1,
5547 .htotal = 800 + 32 + 1 + 57,
5548 .vdisplay = 1280,
5549 .vsync_start = 1280 + 28,
5550 .vsync_end = 1280 + 28 + 1,
5551 .vtotal = 1280 + 28 + 1 + 14,
712ac1ba
AC		 5552};
5553
5554static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
5555 .desc = {
5556 .modes = &lg_ld070wx3_sl01_mode,
5557 .num_modes = 1,
d7a839cd 5558 .bpc = 8,
712ac1ba
AC		 5559 .size = {
5560 .width = 94,
5561 .height = 151,
5562 },
cb62cdec 5563 .connector_type = DRM_MODE_CONNECTOR_DSI,
712ac1ba 5564 },
5e4cc278 5565 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 5566 .format = MIPI_DSI_FMT_RGB888,
5567 .lanes = 4,
5568};
5569
499ce85a
AC		 5570static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
5571 .clock = 67000,
5572 .hdisplay = 720,
5573 .hsync_start = 720 + 12,
5574 .hsync_end = 720 + 12 + 4,
5575 .htotal = 720 + 12 + 4 + 112,
5576 .vdisplay = 1280,
5577 .vsync_start = 1280 + 8,
5578 .vsync_end = 1280 + 8 + 4,
5579 .vtotal = 1280 + 8 + 4 + 12,
499ce85a
AC		 5580};
5581
5582static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
5583 .desc = {
5584 .modes = &lg_lh500wx1_sd03_mode,
5585 .num_modes = 1,
d7a839cd 5586 .bpc = 8,
499ce85a
AC		 5587 .size = {
5588 .width = 62,
5589 .height = 110,
5590 },
cb62cdec 5591 .connector_type = DRM_MODE_CONNECTOR_DSI,
499ce85a
AC		 5592 },
5593 .flags = MIPI_DSI_MODE_VIDEO,
5594 .format = MIPI_DSI_FMT_RGB888,
5595 .lanes = 4,
5596};
5597
280921de
TR		 5598static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
5599 .clock = 157200,
5600 .hdisplay = 1920,
5601 .hsync_start = 1920 + 154,
5602 .hsync_end = 1920 + 154 + 16,
5603 .htotal = 1920 + 154 + 16 + 32,
5604 .vdisplay = 1200,
5605 .vsync_start = 1200 + 17,
5606 .vsync_end = 1200 + 17 + 2,
5607 .vtotal = 1200 + 17 + 2 + 16,
280921de
TR		 5608};
5609
210fcd9d
TR		 5610static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5611 .desc = {
5612 .modes = &panasonic_vvx10f004b00_mode,
5613 .num_modes = 1,
d7a839cd 5614 .bpc = 8,
210fcd9d
TR		 5615 .size = {
5616 .width = 217,
5617 .height = 136,
5618 },
cb62cdec 5619 .connector_type = DRM_MODE_CONNECTOR_DSI,
280921de 5620 },
5e4cc278
AC		 5621 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5622 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 5623 .format = MIPI_DSI_FMT_RGB888,
5624 .lanes = 4,
5625};
5626
debcd8f9
JM		 5627static const struct drm_display_mode lg_acx467akm_7_mode = {
5628 .clock = 150000,
5629 .hdisplay = 1080,
5630 .hsync_start = 1080 + 2,
5631 .hsync_end = 1080 + 2 + 2,
5632 .htotal = 1080 + 2 + 2 + 2,
5633 .vdisplay = 1920,
5634 .vsync_start = 1920 + 2,
5635 .vsync_end = 1920 + 2 + 2,
5636 .vtotal = 1920 + 2 + 2 + 2,
debcd8f9
JM		 5637};
5638
5639static const struct panel_desc_dsi lg_acx467akm_7 = {
5640 .desc = {
5641 .modes = &lg_acx467akm_7_mode,
5642 .num_modes = 1,
5643 .bpc = 8,
5644 .size = {
5645 .width = 62,
5646 .height = 110,
5647 },
cb62cdec 5648 .connector_type = DRM_MODE_CONNECTOR_DSI,
debcd8f9
JM		 5649 },
5650 .flags = 0,
5651 .format = MIPI_DSI_FMT_RGB888,
5652 .lanes = 4,
5653};
5654
62967232
PU		 5655static const struct drm_display_mode osd101t2045_53ts_mode = {
5656 .clock = 154500,
5657 .hdisplay = 1920,
5658 .hsync_start = 1920 + 112,
5659 .hsync_end = 1920 + 112 + 16,
5660 .htotal = 1920 + 112 + 16 + 32,
5661 .vdisplay = 1200,
5662 .vsync_start = 1200 + 16,
5663 .vsync_end = 1200 + 16 + 2,
5664 .vtotal = 1200 + 16 + 2 + 16,
62967232
PU		 5665 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5666};
5667
5668static const struct panel_desc_dsi osd101t2045_53ts = {
5669 .desc = {
5670 .modes = &osd101t2045_53ts_mode,
5671 .num_modes = 1,
5672 .bpc = 8,
5673 .size = {
5674 .width = 217,
5675 .height = 136,
5676 },
cb62cdec 5677 .connector_type = DRM_MODE_CONNECTOR_DSI,
62967232
PU		 5678 },
5679 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5680 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
0f3b68b6 5681 MIPI_DSI_MODE_NO_EOT_PACKET,
62967232
PU		 5682 .format = MIPI_DSI_FMT_RGB888,
5683 .lanes = 4,
5684};
5685
210fcd9d
TR		 5686static const struct of_device_id dsi_of_match[] = {
5687 {
d718d79e
TR		 5688 .compatible = "auo,b080uan01",
5689 .data = &auo_b080uan01
c8521969
CZ		 5690 }, {
5691 .compatible = "boe,tv080wum-nl0",
5692 .data = &boe_tv080wum_nl0
d718d79e 5693 }, {
712ac1ba
AC		 5694 .compatible = "lg,ld070wx3-sl01",
5695 .data = &lg_ld070wx3_sl01
5696 }, {
499ce85a
AC		 5697 .compatible = "lg,lh500wx1-sd03",
5698 .data = &lg_lh500wx1_sd03
5699 }, {
210fcd9d
TR		 5700 .compatible = "panasonic,vvx10f004b00",
5701 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 5702 }, {
5703 .compatible = "lg,acx467akm-7",
5704 .data = &lg_acx467akm_7
62967232
PU		 5705 }, {
5706 .compatible = "osddisplays,osd101t2045-53ts",
5707 .data = &osd101t2045_53ts
210fcd9d
TR		 5708 }, {
5709 /* sentinel */
5710 }
5711};
5712MODULE_DEVICE_TABLE(of, dsi_of_match);
5713
5714static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5715{
5716 const struct panel_desc_dsi *desc;
921c41e5 5717 struct panel_simple *panel;
210fcd9d
TR		 5718 int err;
5719
47c08262 5720 panel = panel_simple_probe(&dsi->dev);
921c41e5
MR		 5721 if (IS_ERR(panel))
5722 return PTR_ERR(panel);
210fcd9d 5723
921c41e5 5724 desc = container_of(panel->desc, struct panel_desc_dsi, desc);
462658b8 5725 dsi->mode_flags = desc->flags;
210fcd9d
TR		 5726 dsi->format = desc->format;
5727 dsi->lanes = desc->lanes;
5728
7ad9db66
PU		 5729 err = mipi_dsi_attach(dsi);
5730 if (err) {
5dd331d4 5731 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
7ad9db66
PU		 5732
5733 drm_panel_remove(&panel->base);
5734 }
5735
5736 return err;
210fcd9d
TR		 5737}
5738
79abca2b 5739static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
210fcd9d
TR		 5740{
5741 int err;
5742
5743 err = mipi_dsi_detach(dsi);
5744 if (err < 0)
5745 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5746
d72ac4bb 5747 panel_simple_remove(&dsi->dev);
210fcd9d
TR		 5748}
5749
d02fd93e
TR		 5750static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5751{
5752 panel_simple_shutdown(&dsi->dev);
5753}
5754
210fcd9d
TR		 5755static struct mipi_dsi_driver panel_simple_dsi_driver = {
5756 .driver = {
5757 .name = "panel-simple-dsi",
210fcd9d 5758 .of_match_table = dsi_of_match,
3235b0f2 5759 .pm = &panel_simple_pm_ops,
210fcd9d
TR		 5760 },
5761 .probe = panel_simple_dsi_probe,
5762 .remove = panel_simple_dsi_remove,
d02fd93e 5763 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 5764};
5765
5766static int __init panel_simple_init(void)
5767{
210fcd9d
TR		 5768 int err;
5769
5770 err = platform_driver_register(&panel_simple_platform_driver);
5771 if (err < 0)
5772 return err;
5773
5774 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5775 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
74c06c28 5776 if (err < 0)
5f04e7ce 5777 goto err_did_platform_register;
210fcd9d
TR		 5778 }
5779
5780 return 0;
74c06c28 5781
74c06c28
DA		 5782err_did_platform_register:
5783 platform_driver_unregister(&panel_simple_platform_driver);
5784
5785 return err;
280921de
TR		 5786}
5787module_init(panel_simple_init);
5788
5789static void __exit panel_simple_exit(void)
5790{
210fcd9d
TR		 5791 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5792 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5793
280921de
TR		 5794 platform_driver_unregister(&panel_simple_platform_driver);
5795}
5796module_exit(panel_simple_exit);
5797
5798MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5799MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5800MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)