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drm/kmb: Remove an unnecessary NULL check
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
48834e60 26#include <linux/iopoll.h>
280921de 27#include <linux/module.h>
280921de
TR		 28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
cb23eae3 32#include <video/display_timing.h>
b8a2948f 33#include <video/of_display_timing.h>
cb23eae3
SR		 34#include <video/videomode.h>
35
280921de 36#include <drm/drm_crtc.h>
cb23eae3 37#include <drm/drm_device.h>
210fcd9d 38#include <drm/drm_mipi_dsi.h>
280921de
TR		 39#include <drm/drm_panel.h>
40
e362cc6a 41/**
084ee219 42 * struct panel_desc
e362cc6a
DA		 43 * @modes: Pointer to array of fixed modes appropriate for this panel. If
44 * only one mode then this can just be the address of this the mode.
45 * NOTE: cannot be used with "timings" and also if this is specified
46 * then you cannot override the mode in the device tree.
47 * @num_modes: Number of elements in modes array.
48 * @timings: Pointer to array of display timings. NOTE: cannot be used with
49 * "modes" and also these will be used to validate a device tree
50 * override if one is present.
51 * @num_timings: Number of elements in timings array.
52 * @bpc: Bits per color.
53 * @size: Structure containing the physical size of this panel.
54 * @delay: Structure containing various delay values for this panel.
55 * @bus_format: See MEDIA_BUS_FMT_... defines.
56 * @bus_flags: See DRM_BUS_FLAG_... defines.
084ee219 57 * @connector_type: LVDS, eDP, DSI, DPI, etc.
e362cc6a 58 */
280921de
TR		 59struct panel_desc {
60 const struct drm_display_mode *modes;
61 unsigned int num_modes;
a5d3e625
PZ		 62 const struct display_timing *timings;
63 unsigned int num_timings;
280921de 64
0208d511
SM		 65 unsigned int bpc;
66
85533e3b
UÖ		 67 /**
68 * @width: width (in millimeters) of the panel's active display area
69 * @height: height (in millimeters) of the panel's active display area
70 */
280921de
TR		 71 struct {
72 unsigned int width;
73 unsigned int height;
74 } size;
f673c37e
AK		 75
76 /**
77 * @prepare: the time (in milliseconds) that it takes for the panel to
78 * become ready and start receiving video data
2ed3e951
DA		 79 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
80 * Plug Detect isn't used.
f673c37e
AK		 81 * @enable: the time (in milliseconds) that it takes for the panel to
82 * display the first valid frame after starting to receive
83 * video data
84 * @disable: the time (in milliseconds) that it takes for the panel to
85 * turn the display off (no content is visible)
86 * @unprepare: the time (in milliseconds) that it takes for the panel
87 * to power itself down completely
88 */
89 struct {
90 unsigned int prepare;
2ed3e951 91 unsigned int hpd_absent_delay;
f673c37e
AK		 92 unsigned int enable;
93 unsigned int disable;
94 unsigned int unprepare;
95 } delay;
795f7ab3
BB		 96
97 u32 bus_format;
f0aa0838 98 u32 bus_flags;
9a2654c0 99 int connector_type;
280921de
TR		 100};
101
280921de
TR		 102struct panel_simple {
103 struct drm_panel base;
613a633e 104 bool prepared;
280921de 105 bool enabled;
2ed3e951 106 bool no_hpd;
280921de
TR		 107
108 const struct panel_desc *desc;
109
280921de
TR		 110 struct regulator *supply;
111 struct i2c_adapter *ddc;
112
cfdf0549 113 struct gpio_desc *enable_gpio;
48834e60 114 struct gpio_desc *hpd_gpio;
b8a2948f
SP		 115
116 struct drm_display_mode override_mode;
5759c967
DO		 117
118 enum drm_panel_orientation orientation;
280921de
TR		 119};
120
121static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
122{
123 return container_of(panel, struct panel_simple, base);
124}
125
0ce8ddd8
SR		 126static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
127 struct drm_connector *connector)
280921de 128{
280921de
TR		 129 struct drm_display_mode *mode;
130 unsigned int i, num = 0;
131
a5d3e625
PZ		 132 for (i = 0; i < panel->desc->num_timings; i++) {
133 const struct display_timing *dt = &panel->desc->timings[i];
134 struct videomode vm;
135
136 videomode_from_timing(dt, &vm);
aa6c4364 137 mode = drm_mode_create(connector->dev);
a5d3e625 138 if (!mode) {
aa6c4364 139 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 140 dt->hactive.typ, dt->vactive.typ);
141 continue;
142 }
143
144 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 145
146 mode->type |= DRM_MODE_TYPE_DRIVER;
147
230c5b44 148 if (panel->desc->num_timings == 1)
cda55372
BB		 149 mode->type |= DRM_MODE_TYPE_PREFERRED;
150
a5d3e625
PZ		 151 drm_mode_probed_add(connector, mode);
152 num++;
153 }
154
b8a2948f
SP		 155 return num;
156}
157
0ce8ddd8
SR		 158static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
159 struct drm_connector *connector)
b8a2948f 160{
b8a2948f
SP		 161 struct drm_display_mode *mode;
162 unsigned int i, num = 0;
163
280921de
TR		 164 for (i = 0; i < panel->desc->num_modes; i++) {
165 const struct drm_display_mode *m = &panel->desc->modes[i];
166
aa6c4364 167 mode = drm_mode_duplicate(connector->dev, m);
280921de 168 if (!mode) {
aa6c4364 169 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
0425662f
VS		 170 m->hdisplay, m->vdisplay,
171 drm_mode_vrefresh(m));
280921de
TR		 172 continue;
173 }
174
cda55372
BB		 175 mode->type |= DRM_MODE_TYPE_DRIVER;
176
177 if (panel->desc->num_modes == 1)
178 mode->type |= DRM_MODE_TYPE_PREFERRED;
179
280921de
TR		 180 drm_mode_set_name(mode);
181
182 drm_mode_probed_add(connector, mode);
183 num++;
184 }
185
b8a2948f
SP		 186 return num;
187}
188
0ce8ddd8
SR		 189static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
190 struct drm_connector *connector)
b8a2948f 191{
b8a2948f
SP		 192 struct drm_display_mode *mode;
193 bool has_override = panel->override_mode.type;
194 unsigned int num = 0;
195
196 if (!panel->desc)
197 return 0;
198
199 if (has_override) {
aa6c4364
SR		 200 mode = drm_mode_duplicate(connector->dev,
201 &panel->override_mode);
b8a2948f
SP		 202 if (mode) {
203 drm_mode_probed_add(connector, mode);
204 num = 1;
205 } else {
aa6c4364 206 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 207 }
208 }
209
210 /* Only add timings if override was not there or failed to validate */
211 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 212 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 213
214 /*
215 * Only add fixed modes if timings/override added no mode.
216 *
217 * We should only ever have either the display timings specified
218 * or a fixed mode. Anything else is rather bogus.
219 */
220 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
221 if (num == 0)
0ce8ddd8 222 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 223
0208d511 224 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 225 connector->display_info.width_mm = panel->desc->size.width;
226 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 227 if (panel->desc->bus_format)
228 drm_display_info_set_bus_formats(&connector->display_info,
229 &panel->desc->bus_format, 1);
f0aa0838 230 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 231
232 return num;
233}
234
235static int panel_simple_disable(struct drm_panel *panel)
236{
237 struct panel_simple *p = to_panel_simple(panel);
238
239 if (!p->enabled)
240 return 0;
241
f673c37e
AK		 242 if (p->desc->delay.disable)
243 msleep(p->desc->delay.disable);
244
280921de
TR		 245 p->enabled = false;
246
247 return 0;
248}
249
c0e1d170
AK		 250static int panel_simple_unprepare(struct drm_panel *panel)
251{
613a633e
AK		 252 struct panel_simple *p = to_panel_simple(panel);
253
254 if (!p->prepared)
255 return 0;
256
756b918d 257 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 258
259 regulator_disable(p->supply);
260
f673c37e
AK		 261 if (p->desc->delay.unprepare)
262 msleep(p->desc->delay.unprepare);
263
613a633e 264 p->prepared = false;
c0e1d170 265
c0e1d170
AK		 266 return 0;
267}
268
48834e60
DA		 269static int panel_simple_get_hpd_gpio(struct device *dev,
270 struct panel_simple *p, bool from_probe)
271{
272 int err;
273
274 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
275 if (IS_ERR(p->hpd_gpio)) {
276 err = PTR_ERR(p->hpd_gpio);
277
278 /*
279 * If we're called from probe we won't consider '-EPROBE_DEFER'
280 * to be an error--we'll leave the error code in "hpd_gpio".
281 * When we try to use it we'll try again. This allows for
282 * circular dependencies where the component providing the
283 * hpd gpio needs the panel to init before probing.
284 */
285 if (err != -EPROBE_DEFER || !from_probe) {
286 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
287 return err;
288 }
289 }
290
291 return 0;
292}
293
613a633e 294static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 295{
296 struct panel_simple *p = to_panel_simple(panel);
2ed3e951 297 unsigned int delay;
280921de 298 int err;
48834e60 299 int hpd_asserted;
280921de 300
613a633e 301 if (p->prepared)
280921de
TR		 302 return 0;
303
304 err = regulator_enable(p->supply);
305 if (err < 0) {
306 dev_err(panel->dev, "failed to enable supply: %d\n", err);
307 return err;
308 }
309
756b918d 310 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 311
2ed3e951
DA		 312 delay = p->desc->delay.prepare;
313 if (p->no_hpd)
314 delay += p->desc->delay.hpd_absent_delay;
315 if (delay)
316 msleep(delay);
f673c37e 317
48834e60
DA		 318 if (p->hpd_gpio) {
319 if (IS_ERR(p->hpd_gpio)) {
320 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
321 if (err)
322 return err;
323 }
324
325 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
326 hpd_asserted, hpd_asserted,
327 1000, 2000000);
328 if (hpd_asserted < 0)
329 err = hpd_asserted;
330
331 if (err) {
332 dev_err(panel->dev,
333 "error waiting for hpd GPIO: %d\n", err);
334 return err;
335 }
336 }
337
613a633e
AK		 338 p->prepared = true;
339
340 return 0;
341}
342
343static int panel_simple_enable(struct drm_panel *panel)
344{
345 struct panel_simple *p = to_panel_simple(panel);
346
347 if (p->enabled)
348 return 0;
349
f673c37e
AK		 350 if (p->desc->delay.enable)
351 msleep(p->desc->delay.enable);
352
280921de
TR		 353 p->enabled = true;
354
355 return 0;
356}
357
0ce8ddd8
SR		 358static int panel_simple_get_modes(struct drm_panel *panel,
359 struct drm_connector *connector)
280921de
TR		 360{
361 struct panel_simple *p = to_panel_simple(panel);
362 int num = 0;
363
364 /* probe EDID if a DDC bus is available */
365 if (p->ddc) {
0ce8ddd8
SR		 366 struct edid *edid = drm_get_edid(connector, p->ddc);
367
368 drm_connector_update_edid_property(connector, edid);
280921de 369 if (edid) {
0ce8ddd8 370 num += drm_add_edid_modes(connector, edid);
280921de
TR		 371 kfree(edid);
372 }
373 }
374
375 /* add hard-coded panel modes */
0ce8ddd8 376 num += panel_simple_get_non_edid_modes(p, connector);
280921de 377
5759c967
DO		 378 /* set up connector's "panel orientation" property */
379 drm_connector_set_panel_orientation(connector, p->orientation);
380
280921de
TR		 381 return num;
382}
383
a5d3e625
PZ		 384static int panel_simple_get_timings(struct drm_panel *panel,
385 unsigned int num_timings,
386 struct display_timing *timings)
387{
388 struct panel_simple *p = to_panel_simple(panel);
389 unsigned int i;
390
391 if (p->desc->num_timings < num_timings)
392 num_timings = p->desc->num_timings;
393
394 if (timings)
395 for (i = 0; i < num_timings; i++)
396 timings[i] = p->desc->timings[i];
397
398 return p->desc->num_timings;
399}
400
280921de
TR		 401static const struct drm_panel_funcs panel_simple_funcs = {
402 .disable = panel_simple_disable,
c0e1d170
AK		 403 .unprepare = panel_simple_unprepare,
404 .prepare = panel_simple_prepare,
280921de
TR		 405 .enable = panel_simple_enable,
406 .get_modes = panel_simple_get_modes,
a5d3e625 407 .get_timings = panel_simple_get_timings,
280921de
TR		 408};
409
4a1d0dbc
SR		 410static struct panel_desc panel_dpi;
411
412static int panel_dpi_probe(struct device *dev,
413 struct panel_simple *panel)
414{
415 struct display_timing *timing;
416 const struct device_node *np;
417 struct panel_desc *desc;
418 unsigned int bus_flags;
419 struct videomode vm;
4a1d0dbc
SR		 420 int ret;
421
422 np = dev->of_node;
423 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
424 if (!desc)
425 return -ENOMEM;
426
427 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
428 if (!timing)
429 return -ENOMEM;
430
431 ret = of_get_display_timing(np, "panel-timing", timing);
432 if (ret < 0) {
433 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
434 np);
435 return ret;
436 }
437
438 desc->timings = timing;
439 desc->num_timings = 1;
440
441 of_property_read_u32(np, "width-mm", &desc->size.width);
442 of_property_read_u32(np, "height-mm", &desc->size.height);
443
4a1d0dbc
SR		 444 /* Extract bus_flags from display_timing */
445 bus_flags = 0;
446 vm.flags = timing->flags;
447 drm_bus_flags_from_videomode(&vm, &bus_flags);
448 desc->bus_flags = bus_flags;
449
450 /* We do not know the connector for the DT node, so guess it */
451 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
452
453 panel->desc = desc;
454
455 return 0;
456}
457
b8a2948f
SP		 458#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
459 (to_check->field.typ >= bounds->field.min && \
460 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 461static void panel_simple_parse_panel_timing_node(struct device *dev,
462 struct panel_simple *panel,
463 const struct display_timing *ot)
b8a2948f
SP		 464{
465 const struct panel_desc *desc = panel->desc;
466 struct videomode vm;
467 unsigned int i;
468
469 if (WARN_ON(desc->num_modes)) {
470 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
471 return;
472 }
473 if (WARN_ON(!desc->num_timings)) {
474 dev_err(dev, "Reject override mode: no timings specified\n");
475 return;
476 }
477
478 for (i = 0; i < panel->desc->num_timings; i++) {
479 const struct display_timing *dt = &panel->desc->timings[i];
480
481 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
482 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
483 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
484 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
485 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
486 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
487 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
488 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
489 continue;
490
491 if (ot->flags != dt->flags)
492 continue;
493
494 videomode_from_timing(ot, &vm);
495 drm_display_mode_from_videomode(&vm, &panel->override_mode);
496 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
497 DRM_MODE_TYPE_PREFERRED;
498 break;
499 }
500
501 if (WARN_ON(!panel->override_mode.type))
502 dev_err(dev, "Reject override mode: No display_timing found\n");
503}
504
280921de
TR		 505static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
506{
280921de 507 struct panel_simple *panel;
b8a2948f 508 struct display_timing dt;
0fe1564b 509 struct device_node *ddc;
9f069c6f 510 int connector_type;
ddb8e853 511 u32 bus_flags;
280921de
TR		 512 int err;
513
514 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
515 if (!panel)
516 return -ENOMEM;
517
518 panel->enabled = false;
613a633e 519 panel->prepared = false;
280921de
TR		 520 panel->desc = desc;
521
2ed3e951 522 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
48834e60
DA		 523 if (!panel->no_hpd) {
524 err = panel_simple_get_hpd_gpio(dev, panel, true);
525 if (err)
526 return err;
527 }
2ed3e951 528
280921de
TR		 529 panel->supply = devm_regulator_get(dev, "power");
530 if (IS_ERR(panel->supply))
531 return PTR_ERR(panel->supply);
532
a61400d8
AC		 533 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
534 GPIOD_OUT_LOW);
cfdf0549
AC		 535 if (IS_ERR(panel->enable_gpio)) {
536 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 537 if (err != -EPROBE_DEFER)
538 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 539 return err;
540 }
280921de 541
5759c967
DO		 542 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
543 if (err) {
544 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
545 return err;
546 }
547
280921de
TR		 548 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
549 if (ddc) {
550 panel->ddc = of_find_i2c_adapter_by_node(ddc);
551 of_node_put(ddc);
552
0fe1564b
SR		 553 if (!panel->ddc)
554 return -EPROBE_DEFER;
280921de
TR		 555 }
556
4a1d0dbc
SR		 557 if (desc == &panel_dpi) {
558 /* Handle the generic panel-dpi binding */
559 err = panel_dpi_probe(dev, panel);
560 if (err)
561 goto free_ddc;
562 } else {
563 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
564 panel_simple_parse_panel_timing_node(dev, panel, &dt);
565 }
b8a2948f 566
9f069c6f 567 connector_type = desc->connector_type;
ddb8e853 568 /* Catch common mistakes for panels. */
9f069c6f 569 switch (connector_type) {
ddb8e853
SR		 570 case 0:
571 dev_warn(dev, "Specify missing connector_type\n");
9f069c6f 572 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853
SR		 573 break;
574 case DRM_MODE_CONNECTOR_LVDS:
c4715837
LP		 575 WARN_ON(desc->bus_flags &
576 ~(DRM_BUS_FLAG_DE_LOW |
577 DRM_BUS_FLAG_DE_HIGH |
578 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
579 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
1185c406
LP		 580 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
581 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
582 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
583 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
584 desc->bpc != 6);
585 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
586 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
587 desc->bpc != 8);
ddb8e853
SR		 588 break;
589 case DRM_MODE_CONNECTOR_eDP:
590 if (desc->bus_format == 0)
591 dev_warn(dev, "Specify missing bus_format\n");
592 if (desc->bpc != 6 && desc->bpc != 8)
593 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
594 break;
595 case DRM_MODE_CONNECTOR_DSI:
596 if (desc->bpc != 6 && desc->bpc != 8)
597 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
598 break;
599 case DRM_MODE_CONNECTOR_DPI:
600 bus_flags = DRM_BUS_FLAG_DE_LOW |
601 DRM_BUS_FLAG_DE_HIGH |
602 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
603 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
604 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
605 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
606 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
607 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
608 if (desc->bus_flags & ~bus_flags)
609 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
610 if (!(desc->bus_flags & bus_flags))
611 dev_warn(dev, "Specify missing bus_flags\n");
612 if (desc->bus_format == 0)
613 dev_warn(dev, "Specify missing bus_format\n");
614 if (desc->bpc != 6 && desc->bpc != 8)
615 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
616 break;
617 default:
618 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
9f069c6f 619 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853 620 break;
1185c406 621 }
c4715837 622
9f069c6f 623 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
280921de 624
0fe1564b
SR		 625 err = drm_panel_of_backlight(&panel->base);
626 if (err)
627 goto free_ddc;
628
c3ee8c65 629 drm_panel_add(&panel->base);
280921de
TR		 630
631 dev_set_drvdata(dev, panel);
632
633 return 0;
634
635free_ddc:
636 if (panel->ddc)
637 put_device(&panel->ddc->dev);
280921de
TR		 638
639 return err;
640}
641
642static int panel_simple_remove(struct device *dev)
643{
644 struct panel_simple *panel = dev_get_drvdata(dev);
645
280921de 646 drm_panel_remove(&panel->base);
0fe1564b
SR		 647 drm_panel_disable(&panel->base);
648 drm_panel_unprepare(&panel->base);
280921de
TR		 649
650 if (panel->ddc)
651 put_device(&panel->ddc->dev);
652
280921de
TR		 653 return 0;
654}
655
d02fd93e
TR		 656static void panel_simple_shutdown(struct device *dev)
657{
658 struct panel_simple *panel = dev_get_drvdata(dev);
659
0fe1564b
SR		 660 drm_panel_disable(&panel->base);
661 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 662}
663
bca684e6
JT		 664static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
665 .clock = 71100,
666 .hdisplay = 1280,
667 .hsync_start = 1280 + 40,
668 .hsync_end = 1280 + 40 + 80,
669 .htotal = 1280 + 40 + 80 + 40,
670 .vdisplay = 800,
671 .vsync_start = 800 + 3,
672 .vsync_end = 800 + 3 + 10,
673 .vtotal = 800 + 3 + 10 + 10,
674 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
675};
676
677static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
678 .modes = &ampire_am_1280800n3tzqw_t00h_mode,
679 .num_modes = 1,
680 .bpc = 6,
681 .size = {
682 .width = 217,
683 .height = 136,
684 },
685 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
686 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
687 .connector_type = DRM_MODE_CONNECTOR_LVDS,
688};
689
966fea78
YF		 690static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
691 .clock = 9000,
692 .hdisplay = 480,
693 .hsync_start = 480 + 2,
694 .hsync_end = 480 + 2 + 41,
695 .htotal = 480 + 2 + 41 + 2,
696 .vdisplay = 272,
697 .vsync_start = 272 + 2,
698 .vsync_end = 272 + 2 + 10,
699 .vtotal = 272 + 2 + 10 + 2,
966fea78
YF		 700 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
701};
702
703static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
704 .modes = &ampire_am_480272h3tmqw_t01h_mode,
705 .num_modes = 1,
706 .bpc = 8,
707 .size = {
708 .width = 105,
709 .height = 67,
710 },
711 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
712};
713
1c550fa1
PZ		 714static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
715 .clock = 33333,
716 .hdisplay = 800,
717 .hsync_start = 800 + 0,
718 .hsync_end = 800 + 0 + 255,
719 .htotal = 800 + 0 + 255 + 0,
720 .vdisplay = 480,
721 .vsync_start = 480 + 2,
722 .vsync_end = 480 + 2 + 45,
723 .vtotal = 480 + 2 + 45 + 0,
1c550fa1
PZ		 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
725};
726
727static const struct panel_desc ampire_am800480r3tmqwa1h = {
728 .modes = &ampire_am800480r3tmqwa1h_mode,
729 .num_modes = 1,
730 .bpc = 6,
731 .size = {
732 .width = 152,
733 .height = 91,
734 },
735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
736};
737
c479450f
SS		 738static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
739 .pixelclock = { 26400000, 33300000, 46800000 },
740 .hactive = { 800, 800, 800 },
741 .hfront_porch = { 16, 210, 354 },
742 .hback_porch = { 45, 36, 6 },
743 .hsync_len = { 1, 10, 40 },
744 .vactive = { 480, 480, 480 },
745 .vfront_porch = { 7, 22, 147 },
746 .vback_porch = { 22, 13, 3 },
747 .vsync_len = { 1, 10, 20 },
748 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
749 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
750};
751
752static const struct panel_desc armadeus_st0700_adapt = {
753 .timings = &santek_st0700i5y_rbslw_f_timing,
754 .num_timings = 1,
755 .bpc = 6,
756 .size = {
757 .width = 154,
758 .height = 86,
759 },
760 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 761 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
c479450f
SS		 762};
763
280921de
TR		 764static const struct drm_display_mode auo_b101aw03_mode = {
765 .clock = 51450,
766 .hdisplay = 1024,
767 .hsync_start = 1024 + 156,
768 .hsync_end = 1024 + 156 + 8,
769 .htotal = 1024 + 156 + 8 + 156,
770 .vdisplay = 600,
771 .vsync_start = 600 + 16,
772 .vsync_end = 600 + 16 + 6,
773 .vtotal = 600 + 16 + 6 + 16,
280921de
TR		 774};
775
776static const struct panel_desc auo_b101aw03 = {
777 .modes = &auo_b101aw03_mode,
778 .num_modes = 1,
0208d511 779 .bpc = 6,
280921de
TR		 780 .size = {
781 .width = 223,
782 .height = 125,
783 },
85560829 784 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 785 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 786 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 787};
788
374bf825
DA		 789static const struct display_timing auo_b101ean01_timing = {
790 .pixelclock = { 65300000, 72500000, 75000000 },
791 .hactive = { 1280, 1280, 1280 },
792 .hfront_porch = { 18, 119, 119 },
793 .hback_porch = { 21, 21, 21 },
794 .hsync_len = { 32, 32, 32 },
795 .vactive = { 800, 800, 800 },
796 .vfront_porch = { 4, 4, 4 },
797 .vback_porch = { 8, 8, 8 },
798 .vsync_len = { 18, 20, 20 },
a531bc3d
HL		 799};
800
801static const struct panel_desc auo_b101ean01 = {
374bf825
DA		 802 .timings = &auo_b101ean01_timing,
803 .num_timings = 1,
a531bc3d
HL		 804 .bpc = 6,
805 .size = {
806 .width = 217,
807 .height = 136,
808 },
809};
810
dac746e0
RC		 811static const struct drm_display_mode auo_b101xtn01_mode = {
812 .clock = 72000,
813 .hdisplay = 1366,
814 .hsync_start = 1366 + 20,
815 .hsync_end = 1366 + 20 + 70,
816 .htotal = 1366 + 20 + 70,
817 .vdisplay = 768,
818 .vsync_start = 768 + 14,
819 .vsync_end = 768 + 14 + 42,
820 .vtotal = 768 + 14 + 42,
dac746e0
RC		 821 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
822};
823
824static const struct panel_desc auo_b101xtn01 = {
825 .modes = &auo_b101xtn01_mode,
826 .num_modes = 1,
827 .bpc = 6,
828 .size = {
829 .width = 223,
830 .height = 125,
831 },
832};
833
da458286
RC		 834static const struct drm_display_mode auo_b116xak01_mode = {
835 .clock = 69300,
836 .hdisplay = 1366,
837 .hsync_start = 1366 + 48,
838 .hsync_end = 1366 + 48 + 32,
839 .htotal = 1366 + 48 + 32 + 10,
840 .vdisplay = 768,
841 .vsync_start = 768 + 4,
842 .vsync_end = 768 + 4 + 6,
843 .vtotal = 768 + 4 + 6 + 15,
da458286
RC		 844 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
845};
846
847static const struct panel_desc auo_b116xak01 = {
848 .modes = &auo_b116xak01_mode,
849 .num_modes = 1,
850 .bpc = 6,
851 .size = {
852 .width = 256,
853 .height = 144,
854 },
855 .delay = {
856 .hpd_absent_delay = 200,
857 },
858 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
859 .connector_type = DRM_MODE_CONNECTOR_eDP,
860};
861
e35e305e
AK		 862static const struct drm_display_mode auo_b116xw03_mode = {
863 .clock = 70589,
864 .hdisplay = 1366,
865 .hsync_start = 1366 + 40,
866 .hsync_end = 1366 + 40 + 40,
867 .htotal = 1366 + 40 + 40 + 32,
868 .vdisplay = 768,
869 .vsync_start = 768 + 10,
870 .vsync_end = 768 + 10 + 12,
871 .vtotal = 768 + 10 + 12 + 6,
88d3457c 872 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
e35e305e
AK		 873};
874
875static const struct panel_desc auo_b116xw03 = {
876 .modes = &auo_b116xw03_mode,
877 .num_modes = 1,
878 .bpc = 6,
879 .size = {
880 .width = 256,
881 .height = 144,
882 },
88d3457c
JS		 883 .delay = {
884 .enable = 400,
885 },
886 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
888 .connector_type = DRM_MODE_CONNECTOR_eDP,
e35e305e
AK		 889};
890
a333f7ad
SM		 891static const struct drm_display_mode auo_b133xtn01_mode = {
892 .clock = 69500,
893 .hdisplay = 1366,
894 .hsync_start = 1366 + 48,
895 .hsync_end = 1366 + 48 + 32,
896 .htotal = 1366 + 48 + 32 + 20,
897 .vdisplay = 768,
898 .vsync_start = 768 + 3,
899 .vsync_end = 768 + 3 + 6,
900 .vtotal = 768 + 3 + 6 + 13,
a333f7ad
SM		 901};
902
903static const struct panel_desc auo_b133xtn01 = {
904 .modes = &auo_b133xtn01_mode,
905 .num_modes = 1,
0208d511 906 .bpc = 6,
a333f7ad
SM		 907 .size = {
908 .width = 293,
909 .height = 165,
910 },
911};
912
3e51d609
AK		 913static const struct drm_display_mode auo_b133htn01_mode = {
914 .clock = 150660,
915 .hdisplay = 1920,
916 .hsync_start = 1920 + 172,
917 .hsync_end = 1920 + 172 + 80,
918 .htotal = 1920 + 172 + 80 + 60,
919 .vdisplay = 1080,
920 .vsync_start = 1080 + 25,
921 .vsync_end = 1080 + 25 + 10,
922 .vtotal = 1080 + 25 + 10 + 10,
3e51d609
AK		 923};
924
925static const struct panel_desc auo_b133htn01 = {
926 .modes = &auo_b133htn01_mode,
927 .num_modes = 1,
d7a839cd 928 .bpc = 6,
3e51d609
AK		 929 .size = {
930 .width = 293,
931 .height = 165,
932 },
933 .delay = {
934 .prepare = 105,
935 .enable = 20,
936 .unprepare = 50,
937 },
938};
939
bccfaffb
LM		 940static const struct display_timing auo_g070vvn01_timings = {
941 .pixelclock = { 33300000, 34209000, 45000000 },
942 .hactive = { 800, 800, 800 },
943 .hfront_porch = { 20, 40, 200 },
944 .hback_porch = { 87, 40, 1 },
945 .hsync_len = { 1, 48, 87 },
946 .vactive = { 480, 480, 480 },
947 .vfront_porch = { 5, 13, 200 },
948 .vback_porch = { 31, 31, 29 },
949 .vsync_len = { 1, 1, 3 },
950};
951
952static const struct panel_desc auo_g070vvn01 = {
953 .timings = &auo_g070vvn01_timings,
954 .num_timings = 1,
955 .bpc = 8,
956 .size = {
957 .width = 152,
958 .height = 91,
959 },
960 .delay = {
961 .prepare = 200,
962 .enable = 50,
963 .disable = 50,
964 .unprepare = 1000,
965 },
966};
967
4fb86404
AG		 968static const struct drm_display_mode auo_g101evn010_mode = {
969 .clock = 68930,
970 .hdisplay = 1280,
971 .hsync_start = 1280 + 82,
972 .hsync_end = 1280 + 82 + 2,
973 .htotal = 1280 + 82 + 2 + 84,
974 .vdisplay = 800,
975 .vsync_start = 800 + 8,
976 .vsync_end = 800 + 8 + 2,
977 .vtotal = 800 + 8 + 2 + 6,
4fb86404
AG		 978};
979
980static const struct panel_desc auo_g101evn010 = {
981 .modes = &auo_g101evn010_mode,
982 .num_modes = 1,
983 .bpc = 6,
984 .size = {
985 .width = 216,
986 .height = 135,
987 },
27a46fb7
TV		 988 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
989 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4fb86404
AG		 990};
991
4451c287
CF		 992static const struct drm_display_mode auo_g104sn02_mode = {
993 .clock = 40000,
994 .hdisplay = 800,
995 .hsync_start = 800 + 40,
996 .hsync_end = 800 + 40 + 216,
997 .htotal = 800 + 40 + 216 + 128,
998 .vdisplay = 600,
999 .vsync_start = 600 + 10,
1000 .vsync_end = 600 + 10 + 35,
1001 .vtotal = 600 + 10 + 35 + 2,
4451c287
CF		 1002};
1003
1004static const struct panel_desc auo_g104sn02 = {
1005 .modes = &auo_g104sn02_mode,
1006 .num_modes = 1,
1007 .bpc = 8,
1008 .size = {
1009 .width = 211,
1010 .height = 158,
1011 },
1012};
1013
03e909ac
SR		 1014static const struct drm_display_mode auo_g121ean01_mode = {
1015 .clock = 66700,
1016 .hdisplay = 1280,
1017 .hsync_start = 1280 + 58,
1018 .hsync_end = 1280 + 58 + 8,
1019 .htotal = 1280 + 58 + 8 + 70,
1020 .vdisplay = 800,
1021 .vsync_start = 800 + 6,
1022 .vsync_end = 800 + 6 + 4,
1023 .vtotal = 800 + 6 + 4 + 10,
03e909ac
SR		 1024};
1025
1026static const struct panel_desc auo_g121ean01 = {
1027 .modes = &auo_g121ean01_mode,
1028 .num_modes = 1,
1029 .bpc = 8,
1030 .size = {
1031 .width = 261,
1032 .height = 163,
1033 },
1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1035 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1036};
1037
697035c6
LS		 1038static const struct display_timing auo_g133han01_timings = {
1039 .pixelclock = { 134000000, 141200000, 149000000 },
1040 .hactive = { 1920, 1920, 1920 },
1041 .hfront_porch = { 39, 58, 77 },
1042 .hback_porch = { 59, 88, 117 },
1043 .hsync_len = { 28, 42, 56 },
1044 .vactive = { 1080, 1080, 1080 },
1045 .vfront_porch = { 3, 8, 11 },
1046 .vback_porch = { 5, 14, 19 },
1047 .vsync_len = { 4, 14, 19 },
1048};
1049
1050static const struct panel_desc auo_g133han01 = {
1051 .timings = &auo_g133han01_timings,
1052 .num_timings = 1,
1053 .bpc = 8,
1054 .size = {
1055 .width = 293,
1056 .height = 165,
1057 },
1058 .delay = {
1059 .prepare = 200,
1060 .enable = 50,
1061 .disable = 50,
1062 .unprepare = 1000,
1063 },
1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 1065 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 1066};
1067
d9ccd1f2
SR		 1068static const struct drm_display_mode auo_g156xtn01_mode = {
1069 .clock = 76000,
1070 .hdisplay = 1366,
1071 .hsync_start = 1366 + 33,
1072 .hsync_end = 1366 + 33 + 67,
1073 .htotal = 1560,
1074 .vdisplay = 768,
1075 .vsync_start = 768 + 4,
1076 .vsync_end = 768 + 4 + 4,
1077 .vtotal = 806,
d9ccd1f2
SR		 1078};
1079
1080static const struct panel_desc auo_g156xtn01 = {
1081 .modes = &auo_g156xtn01_mode,
1082 .num_modes = 1,
1083 .bpc = 8,
1084 .size = {
1085 .width = 344,
1086 .height = 194,
1087 },
1088 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1089 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1090};
1091
8c31f603
LS		 1092static const struct display_timing auo_g185han01_timings = {
1093 .pixelclock = { 120000000, 144000000, 175000000 },
1094 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 1095 .hfront_porch = { 36, 120, 148 },
1096 .hback_porch = { 24, 88, 108 },
1097 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 1098 .vactive = { 1080, 1080, 1080 },
1099 .vfront_porch = { 6, 10, 40 },
1100 .vback_porch = { 2, 5, 20 },
1101 .vsync_len = { 2, 5, 20 },
1102};
1103
1104static const struct panel_desc auo_g185han01 = {
1105 .timings = &auo_g185han01_timings,
1106 .num_timings = 1,
1107 .bpc = 8,
1108 .size = {
1109 .width = 409,
1110 .height = 230,
1111 },
1112 .delay = {
1113 .prepare = 50,
1114 .enable = 200,
1115 .disable = 110,
1116 .unprepare = 1000,
1117 },
1118 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1119 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 1120};
1121
2f7b832f
SR		 1122static const struct display_timing auo_g190ean01_timings = {
1123 .pixelclock = { 90000000, 108000000, 135000000 },
1124 .hactive = { 1280, 1280, 1280 },
1125 .hfront_porch = { 126, 184, 1266 },
1126 .hback_porch = { 84, 122, 844 },
1127 .hsync_len = { 70, 102, 704 },
1128 .vactive = { 1024, 1024, 1024 },
1129 .vfront_porch = { 4, 26, 76 },
1130 .vback_porch = { 2, 8, 25 },
1131 .vsync_len = { 2, 8, 25 },
1132};
1133
1134static const struct panel_desc auo_g190ean01 = {
1135 .timings = &auo_g190ean01_timings,
1136 .num_timings = 1,
1137 .bpc = 8,
1138 .size = {
1139 .width = 376,
1140 .height = 301,
1141 },
1142 .delay = {
1143 .prepare = 50,
1144 .enable = 200,
1145 .disable = 110,
1146 .unprepare = 1000,
1147 },
1148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1149 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1150};
1151
70c0d5b7
LS		 1152static const struct display_timing auo_p320hvn03_timings = {
1153 .pixelclock = { 106000000, 148500000, 164000000 },
1154 .hactive = { 1920, 1920, 1920 },
1155 .hfront_porch = { 25, 50, 130 },
1156 .hback_porch = { 25, 50, 130 },
1157 .hsync_len = { 20, 40, 105 },
1158 .vactive = { 1080, 1080, 1080 },
1159 .vfront_porch = { 8, 17, 150 },
1160 .vback_porch = { 8, 17, 150 },
1161 .vsync_len = { 4, 11, 100 },
1162};
1163
1164static const struct panel_desc auo_p320hvn03 = {
1165 .timings = &auo_p320hvn03_timings,
1166 .num_timings = 1,
1167 .bpc = 8,
1168 .size = {
1169 .width = 698,
1170 .height = 393,
1171 },
1172 .delay = {
1173 .prepare = 1,
1174 .enable = 450,
1175 .unprepare = 500,
1176 },
2554f154 1177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1178 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 1179};
1180
7ee933a1
HS		 1181static const struct drm_display_mode auo_t215hvn01_mode = {
1182 .clock = 148800,
1183 .hdisplay = 1920,
1184 .hsync_start = 1920 + 88,
1185 .hsync_end = 1920 + 88 + 44,
1186 .htotal = 1920 + 88 + 44 + 148,
1187 .vdisplay = 1080,
1188 .vsync_start = 1080 + 4,
1189 .vsync_end = 1080 + 4 + 5,
1190 .vtotal = 1080 + 4 + 5 + 36,
7ee933a1
HS		 1191};
1192
1193static const struct panel_desc auo_t215hvn01 = {
1194 .modes = &auo_t215hvn01_mode,
1195 .num_modes = 1,
1196 .bpc = 8,
1197 .size = {
1198 .width = 430,
1199 .height = 270,
1200 },
1201 .delay = {
1202 .disable = 5,
1203 .unprepare = 1000,
1204 }
1205};
1206
d47df633
PZ		 1207static const struct drm_display_mode avic_tm070ddh03_mode = {
1208 .clock = 51200,
1209 .hdisplay = 1024,
1210 .hsync_start = 1024 + 160,
1211 .hsync_end = 1024 + 160 + 4,
1212 .htotal = 1024 + 160 + 4 + 156,
1213 .vdisplay = 600,
1214 .vsync_start = 600 + 17,
1215 .vsync_end = 600 + 17 + 1,
1216 .vtotal = 600 + 17 + 1 + 17,
d47df633
PZ		 1217};
1218
1219static const struct panel_desc avic_tm070ddh03 = {
1220 .modes = &avic_tm070ddh03_mode,
1221 .num_modes = 1,
1222 .bpc = 8,
1223 .size = {
1224 .width = 154,
1225 .height = 90,
1226 },
1227 .delay = {
1228 .prepare = 20,
1229 .enable = 200,
1230 .disable = 200,
1231 },
1232};
1233
7ad8b41c
CYT		 1234static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1235 .clock = 30000,
1236 .hdisplay = 800,
1237 .hsync_start = 800 + 40,
1238 .hsync_end = 800 + 40 + 48,
1239 .htotal = 800 + 40 + 48 + 40,
1240 .vdisplay = 480,
1241 .vsync_start = 480 + 13,
1242 .vsync_end = 480 + 13 + 3,
1243 .vtotal = 480 + 13 + 3 + 29,
1244};
1245
1246static const struct panel_desc bananapi_s070wv20_ct16 = {
1247 .modes = &bananapi_s070wv20_ct16_mode,
1248 .num_modes = 1,
1249 .bpc = 6,
1250 .size = {
1251 .width = 154,
1252 .height = 86,
1253 },
1254};
1255
ae8cf41b 1256static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 1257 .clock = 42105,
ae8cf41b 1258 .hdisplay = 1024,
e077e2f5
AH		 1259 .hsync_start = 1024 + 30,
1260 .hsync_end = 1024 + 30 + 30,
1261 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 1262 .vdisplay = 600,
e077e2f5
AH		 1263 .vsync_start = 600 + 10,
1264 .vsync_end = 600 + 10 + 10,
1265 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 1266};
1267
1268static const struct panel_desc boe_hv070wsa = {
1269 .modes = &boe_hv070wsa_mode,
1270 .num_modes = 1,
2a5c2ff5 1271 .bpc = 8,
ae8cf41b
AH		 1272 .size = {
1273 .width = 154,
1274 .height = 90,
1275 },
2a5c2ff5
SR		 1276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1277 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1278 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ae8cf41b
AH		 1279};
1280
cac1a411
CW		 1281static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1282 {
1283 .clock = 71900,
1284 .hdisplay = 1280,
1285 .hsync_start = 1280 + 48,
1286 .hsync_end = 1280 + 48 + 32,
1287 .htotal = 1280 + 48 + 32 + 80,
1288 .vdisplay = 800,
1289 .vsync_start = 800 + 3,
1290 .vsync_end = 800 + 3 + 5,
1291 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1292 },
1293 {
1294 .clock = 57500,
1295 .hdisplay = 1280,
1296 .hsync_start = 1280 + 48,
1297 .hsync_end = 1280 + 48 + 32,
1298 .htotal = 1280 + 48 + 32 + 80,
1299 .vdisplay = 800,
1300 .vsync_start = 800 + 3,
1301 .vsync_end = 800 + 3 + 5,
1302 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1303 },
1304};
1305
1306static const struct panel_desc boe_nv101wxmn51 = {
1307 .modes = boe_nv101wxmn51_modes,
1308 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1309 .bpc = 8,
1310 .size = {
1311 .width = 217,
1312 .height = 136,
1313 },
1314 .delay = {
1315 .prepare = 210,
1316 .enable = 50,
1317 .unprepare = 160,
1318 },
1319};
1320
cfe40d02 1321/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1322static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1323 .clock = 147840,
1324 .hdisplay = 1920,
1325 .hsync_start = 1920 + 48,
1326 .hsync_end = 1920 + 48 + 32,
1327 .htotal = 1920 + 48 + 32 + 200,
1328 .vdisplay = 1080,
1329 .vsync_start = 1080 + 3,
1330 .vsync_end = 1080 + 3 + 6,
1331 .vtotal = 1080 + 3 + 6 + 31,
ab6fd5d4 1332 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
b0c664cc
BA		 1333};
1334
cfe40d02 1335/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1336static const struct panel_desc boe_nv133fhm_n61 = {
1337 .modes = &boe_nv133fhm_n61_modes,
1338 .num_modes = 1,
9694d9c3 1339 .bpc = 6,
b0c664cc 1340 .size = {
9694d9c3
DA		 1341 .width = 294,
1342 .height = 165,
b0c664cc
BA		 1343 },
1344 .delay = {
667d73d7
DA		 1345 /*
1346 * When power is first given to the panel there's a short
1347 * spike on the HPD line. It was explained that this spike
1348 * was until the TCON data download was complete. On
1349 * one system this was measured at 8 ms. We'll put 15 ms
1350 * in the prepare delay just to be safe and take it away
1351 * from the hpd_absent_delay (which would otherwise be 200 ms)
1352 * to handle this. That means:
1353 * - If HPD isn't hooked up you still have 200 ms delay.
1354 * - If HPD is hooked up we won't try to look at it for the
1355 * first 15 ms.
1356 */
1357 .prepare = 15,
1358 .hpd_absent_delay = 185,
1359
b0c664cc
BA		 1360 .unprepare = 500,
1361 },
1362 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1363 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1364 .connector_type = DRM_MODE_CONNECTOR_eDP,
1365};
1366
a5119818
TS		 1367static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1368 {
1369 .clock = 148500,
1370 .hdisplay = 1920,
1371 .hsync_start = 1920 + 48,
1372 .hsync_end = 1920 + 48 + 32,
1373 .htotal = 2200,
1374 .vdisplay = 1080,
1375 .vsync_start = 1080 + 3,
1376 .vsync_end = 1080 + 3 + 5,
1377 .vtotal = 1125,
a5119818
TS		 1378 },
1379};
1380
1381static const struct panel_desc boe_nv140fhmn49 = {
1382 .modes = boe_nv140fhmn49_modes,
1383 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1384 .bpc = 6,
1385 .size = {
1386 .width = 309,
1387 .height = 174,
1388 },
1389 .delay = {
1390 .prepare = 210,
1391 .enable = 50,
1392 .unprepare = 160,
1393 },
1394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1395 .connector_type = DRM_MODE_CONNECTOR_eDP,
1396};
1397
e58edce6
GB		 1398static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1399 .clock = 9000,
1400 .hdisplay = 480,
1401 .hsync_start = 480 + 5,
1402 .hsync_end = 480 + 5 + 5,
1403 .htotal = 480 + 5 + 5 + 40,
1404 .vdisplay = 272,
1405 .vsync_start = 272 + 8,
1406 .vsync_end = 272 + 8 + 8,
1407 .vtotal = 272 + 8 + 8 + 8,
e58edce6
GB		 1408 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1409};
1410
1411static const struct panel_desc cdtech_s043wq26h_ct7 = {
1412 .modes = &cdtech_s043wq26h_ct7_mode,
1413 .num_modes = 1,
1414 .bpc = 8,
1415 .size = {
1416 .width = 95,
1417 .height = 54,
1418 },
88bc4178 1419 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1420};
1421
0e3b67f6
MK		 1422/* S070PWS19HP-FC21 2017/04/22 */
1423static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1424 .clock = 51200,
1425 .hdisplay = 1024,
1426 .hsync_start = 1024 + 160,
1427 .hsync_end = 1024 + 160 + 20,
1428 .htotal = 1024 + 160 + 20 + 140,
1429 .vdisplay = 600,
1430 .vsync_start = 600 + 12,
1431 .vsync_end = 600 + 12 + 3,
1432 .vtotal = 600 + 12 + 3 + 20,
1433 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1434};
1435
1436static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1437 .modes = &cdtech_s070pws19hp_fc21_mode,
1438 .num_modes = 1,
1439 .bpc = 6,
1440 .size = {
1441 .width = 154,
1442 .height = 86,
1443 },
1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1446 .connector_type = DRM_MODE_CONNECTOR_DPI,
1447};
1448
1449/* S070SWV29HG-DC44 2017/09/21 */
1450static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1451 .clock = 33300,
1452 .hdisplay = 800,
1453 .hsync_start = 800 + 210,
1454 .hsync_end = 800 + 210 + 2,
1455 .htotal = 800 + 210 + 2 + 44,
1456 .vdisplay = 480,
1457 .vsync_start = 480 + 22,
1458 .vsync_end = 480 + 22 + 2,
1459 .vtotal = 480 + 22 + 2 + 21,
1460 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1461};
1462
1463static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1464 .modes = &cdtech_s070swv29hg_dc44_mode,
1465 .num_modes = 1,
1466 .bpc = 6,
1467 .size = {
1468 .width = 154,
1469 .height = 86,
1470 },
1471 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1473 .connector_type = DRM_MODE_CONNECTOR_DPI,
1474};
1475
982f944e
GB		 1476static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1477 .clock = 35000,
1478 .hdisplay = 800,
1479 .hsync_start = 800 + 40,
1480 .hsync_end = 800 + 40 + 40,
1481 .htotal = 800 + 40 + 40 + 48,
1482 .vdisplay = 480,
1483 .vsync_start = 480 + 29,
1484 .vsync_end = 480 + 29 + 13,
1485 .vtotal = 480 + 29 + 13 + 3,
982f944e
GB		 1486 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1487};
1488
1489static const struct panel_desc cdtech_s070wv95_ct16 = {
1490 .modes = &cdtech_s070wv95_ct16_mode,
1491 .num_modes = 1,
1492 .bpc = 8,
1493 .size = {
1494 .width = 154,
1495 .height = 85,
1496 },
1497};
1498
07c913c4
MV		 1499static const struct display_timing chefree_ch101olhlwh_002_timing = {
1500 .pixelclock = { 68900000, 71100000, 73400000 },
1501 .hactive = { 1280, 1280, 1280 },
1502 .hfront_porch = { 65, 80, 95 },
1503 .hback_porch = { 64, 79, 94 },
1504 .hsync_len = { 1, 1, 1 },
1505 .vactive = { 800, 800, 800 },
1506 .vfront_porch = { 7, 11, 14 },
1507 .vback_porch = { 7, 11, 14 },
1508 .vsync_len = { 1, 1, 1 },
1509 .flags = DISPLAY_FLAGS_DE_HIGH,
1510};
1511
1512static const struct panel_desc chefree_ch101olhlwh_002 = {
1513 .timings = &chefree_ch101olhlwh_002_timing,
1514 .num_timings = 1,
1515 .bpc = 8,
1516 .size = {
1517 .width = 217,
1518 .height = 135,
1519 },
1520 .delay = {
1521 .enable = 200,
1522 .disable = 200,
1523 },
1524 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1525 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1526 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1527};
1528
2cb35c80
RL		 1529static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1530 .clock = 66770,
1531 .hdisplay = 800,
1532 .hsync_start = 800 + 49,
1533 .hsync_end = 800 + 49 + 33,
1534 .htotal = 800 + 49 + 33 + 17,
1535 .vdisplay = 1280,
1536 .vsync_start = 1280 + 1,
1537 .vsync_end = 1280 + 1 + 7,
1538 .vtotal = 1280 + 1 + 7 + 15,
2cb35c80
RL		 1539 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1540};
1541
1542static const struct panel_desc chunghwa_claa070wp03xg = {
1543 .modes = &chunghwa_claa070wp03xg_mode,
1544 .num_modes = 1,
1545 .bpc = 6,
1546 .size = {
1547 .width = 94,
1548 .height = 150,
1549 },
85560829 1550 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1551 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1552 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2cb35c80
RL		 1553};
1554
4c930757
SW		 1555static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1556 .clock = 72070,
1557 .hdisplay = 1366,
1558 .hsync_start = 1366 + 58,
1559 .hsync_end = 1366 + 58 + 58,
1560 .htotal = 1366 + 58 + 58 + 58,
1561 .vdisplay = 768,
1562 .vsync_start = 768 + 4,
1563 .vsync_end = 768 + 4 + 4,
1564 .vtotal = 768 + 4 + 4 + 4,
4c930757
SW		 1565};
1566
1567static const struct panel_desc chunghwa_claa101wa01a = {
1568 .modes = &chunghwa_claa101wa01a_mode,
1569 .num_modes = 1,
0208d511 1570 .bpc = 6,
4c930757
SW		 1571 .size = {
1572 .width = 220,
1573 .height = 120,
1574 },
85560829 1575 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1576 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1577 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4c930757
SW		 1578};
1579
280921de
TR		 1580static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1581 .clock = 69300,
1582 .hdisplay = 1366,
1583 .hsync_start = 1366 + 48,
1584 .hsync_end = 1366 + 48 + 32,
1585 .htotal = 1366 + 48 + 32 + 20,
1586 .vdisplay = 768,
1587 .vsync_start = 768 + 16,
1588 .vsync_end = 768 + 16 + 8,
1589 .vtotal = 768 + 16 + 8 + 16,
280921de
TR		 1590};
1591
1592static const struct panel_desc chunghwa_claa101wb01 = {
1593 .modes = &chunghwa_claa101wb01_mode,
1594 .num_modes = 1,
0208d511 1595 .bpc = 6,
280921de
TR		 1596 .size = {
1597 .width = 223,
1598 .height = 125,
1599 },
85560829 1600 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1601 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1602 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 1603};
1604
97ceb1fb
MV		 1605static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1606 .clock = 33260,
1607 .hdisplay = 800,
1608 .hsync_start = 800 + 40,
1609 .hsync_end = 800 + 40 + 128,
1610 .htotal = 800 + 40 + 128 + 88,
1611 .vdisplay = 480,
1612 .vsync_start = 480 + 10,
1613 .vsync_end = 480 + 10 + 2,
1614 .vtotal = 480 + 10 + 2 + 33,
97ceb1fb
MV		 1615 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1616};
1617
1618static const struct panel_desc dataimage_scf0700c48ggu18 = {
1619 .modes = &dataimage_scf0700c48ggu18_mode,
1620 .num_modes = 1,
1621 .bpc = 8,
1622 .size = {
1623 .width = 152,
1624 .height = 91,
1625 },
1626 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1627 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1628};
1629
0ca0c827
PZ		 1630static const struct display_timing dlc_dlc0700yzg_1_timing = {
1631 .pixelclock = { 45000000, 51200000, 57000000 },
1632 .hactive = { 1024, 1024, 1024 },
1633 .hfront_porch = { 100, 106, 113 },
1634 .hback_porch = { 100, 106, 113 },
1635 .hsync_len = { 100, 108, 114 },
1636 .vactive = { 600, 600, 600 },
1637 .vfront_porch = { 8, 11, 15 },
1638 .vback_porch = { 8, 11, 15 },
1639 .vsync_len = { 9, 13, 15 },
1640 .flags = DISPLAY_FLAGS_DE_HIGH,
1641};
1642
1643static const struct panel_desc dlc_dlc0700yzg_1 = {
1644 .timings = &dlc_dlc0700yzg_1_timing,
1645 .num_timings = 1,
1646 .bpc = 6,
1647 .size = {
1648 .width = 154,
1649 .height = 86,
1650 },
1651 .delay = {
1652 .prepare = 30,
1653 .enable = 200,
1654 .disable = 200,
1655 },
1656 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1657 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1658};
1659
6cbe7cd1
MF		 1660static const struct display_timing dlc_dlc1010gig_timing = {
1661 .pixelclock = { 68900000, 71100000, 73400000 },
1662 .hactive = { 1280, 1280, 1280 },
1663 .hfront_porch = { 43, 53, 63 },
1664 .hback_porch = { 43, 53, 63 },
1665 .hsync_len = { 44, 54, 64 },
1666 .vactive = { 800, 800, 800 },
1667 .vfront_porch = { 5, 8, 11 },
1668 .vback_porch = { 5, 8, 11 },
1669 .vsync_len = { 5, 7, 11 },
1670 .flags = DISPLAY_FLAGS_DE_HIGH,
1671};
1672
1673static const struct panel_desc dlc_dlc1010gig = {
1674 .timings = &dlc_dlc1010gig_timing,
1675 .num_timings = 1,
1676 .bpc = 8,
1677 .size = {
1678 .width = 216,
1679 .height = 135,
1680 },
1681 .delay = {
1682 .prepare = 60,
1683 .enable = 150,
1684 .disable = 100,
1685 .unprepare = 60,
1686 },
1687 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1688 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1689};
1690
c2d24af6
AP		 1691static const struct drm_display_mode edt_et035012dm6_mode = {
1692 .clock = 6500,
1693 .hdisplay = 320,
1694 .hsync_start = 320 + 20,
1695 .hsync_end = 320 + 20 + 30,
1696 .htotal = 320 + 20 + 68,
1697 .vdisplay = 240,
1698 .vsync_start = 240 + 4,
1699 .vsync_end = 240 + 4 + 4,
1700 .vtotal = 240 + 4 + 4 + 14,
c2d24af6
AP		 1701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1702};
1703
1704static const struct panel_desc edt_et035012dm6 = {
1705 .modes = &edt_et035012dm6_mode,
1706 .num_modes = 1,
1707 .bpc = 8,
1708 .size = {
1709 .width = 70,
1710 .height = 52,
1711 },
1712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1713 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
c2d24af6
AP		 1714};
1715
82d57a59
MCR		 1716static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1717 .clock = 10870,
1718 .hdisplay = 480,
1719 .hsync_start = 480 + 8,
1720 .hsync_end = 480 + 8 + 4,
1721 .htotal = 480 + 8 + 4 + 41,
1722
1723 /*
1724 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1725 * fb_align
1726 */
1727
1728 .vdisplay = 288,
1729 .vsync_start = 288 + 2,
1730 .vsync_end = 288 + 2 + 4,
1731 .vtotal = 288 + 2 + 4 + 10,
82d57a59
MCR		 1732};
1733
1734static const struct panel_desc edt_etm043080dh6gp = {
1735 .modes = &edt_etm043080dh6gp_mode,
1736 .num_modes = 1,
1737 .bpc = 8,
1738 .size = {
1739 .width = 100,
1740 .height = 65,
1741 },
1742 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1743 .connector_type = DRM_MODE_CONNECTOR_DPI,
1744};
1745
fd819bff
MV		 1746static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1747 .clock = 9000,
1748 .hdisplay = 480,
1749 .hsync_start = 480 + 2,
1750 .hsync_end = 480 + 2 + 41,
1751 .htotal = 480 + 2 + 41 + 2,
1752 .vdisplay = 272,
1753 .vsync_start = 272 + 2,
1754 .vsync_end = 272 + 2 + 10,
1755 .vtotal = 272 + 2 + 10 + 2,
fd819bff
MV		 1756 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1757};
1758
1759static const struct panel_desc edt_etm0430g0dh6 = {
1760 .modes = &edt_etm0430g0dh6_mode,
1761 .num_modes = 1,
1762 .bpc = 6,
1763 .size = {
1764 .width = 95,
1765 .height = 54,
1766 },
1767};
1768
26ab0065
SA		 1769static const struct drm_display_mode edt_et057090dhu_mode = {
1770 .clock = 25175,
1771 .hdisplay = 640,
1772 .hsync_start = 640 + 16,
1773 .hsync_end = 640 + 16 + 30,
1774 .htotal = 640 + 16 + 30 + 114,
1775 .vdisplay = 480,
1776 .vsync_start = 480 + 10,
1777 .vsync_end = 480 + 10 + 3,
1778 .vtotal = 480 + 10 + 3 + 32,
26ab0065
SA		 1779 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1780};
1781
1782static const struct panel_desc edt_et057090dhu = {
1783 .modes = &edt_et057090dhu_mode,
1784 .num_modes = 1,
0208d511 1785 .bpc = 6,
26ab0065
SA		 1786 .size = {
1787 .width = 115,
1788 .height = 86,
1789 },
eaeebffa 1790 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
75e73224 1792 .connector_type = DRM_MODE_CONNECTOR_DPI,
26ab0065
SA		 1793};
1794
fff5de45
PZ		 1795static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1796 .clock = 33260,
1797 .hdisplay = 800,
1798 .hsync_start = 800 + 40,
1799 .hsync_end = 800 + 40 + 128,
1800 .htotal = 800 + 40 + 128 + 88,
1801 .vdisplay = 480,
1802 .vsync_start = 480 + 10,
1803 .vsync_end = 480 + 10 + 2,
1804 .vtotal = 480 + 10 + 2 + 33,
fff5de45
PZ		 1805 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1806};
1807
1808static const struct panel_desc edt_etm0700g0dh6 = {
1809 .modes = &edt_etm0700g0dh6_mode,
1810 .num_modes = 1,
0208d511 1811 .bpc = 6,
fff5de45
PZ		 1812 .size = {
1813 .width = 152,
1814 .height = 91,
1815 },
eaeebffa 1816 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1817 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
281edb9f 1818 .connector_type = DRM_MODE_CONNECTOR_DPI,
fff5de45
PZ		 1819};
1820
aa7e6455
JT		 1821static const struct panel_desc edt_etm0700g0bdh6 = {
1822 .modes = &edt_etm0700g0dh6_mode,
1823 .num_modes = 1,
1824 .bpc = 6,
1825 .size = {
1826 .width = 152,
1827 .height = 91,
1828 },
1829 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1830 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
aa7e6455
JT		 1831};
1832
9158e3c3
MF		 1833static const struct display_timing evervision_vgg804821_timing = {
1834 .pixelclock = { 27600000, 33300000, 50000000 },
1835 .hactive = { 800, 800, 800 },
1836 .hfront_porch = { 40, 66, 70 },
1837 .hback_porch = { 40, 67, 70 },
1838 .hsync_len = { 40, 67, 70 },
1839 .vactive = { 480, 480, 480 },
1840 .vfront_porch = { 6, 10, 10 },
1841 .vback_porch = { 7, 11, 11 },
1842 .vsync_len = { 7, 11, 11 },
1843 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1844 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1845 DISPLAY_FLAGS_SYNC_NEGEDGE,
1846};
1847
1848static const struct panel_desc evervision_vgg804821 = {
1849 .timings = &evervision_vgg804821_timing,
1850 .num_timings = 1,
1851 .bpc = 8,
1852 .size = {
1853 .width = 108,
1854 .height = 64,
1855 },
1856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
9158e3c3
MF		 1858};
1859
102932b0
BB		 1860static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1861 .clock = 32260,
1862 .hdisplay = 800,
1863 .hsync_start = 800 + 168,
1864 .hsync_end = 800 + 168 + 64,
1865 .htotal = 800 + 168 + 64 + 88,
1866 .vdisplay = 480,
1867 .vsync_start = 480 + 37,
1868 .vsync_end = 480 + 37 + 2,
1869 .vtotal = 480 + 37 + 2 + 8,
102932b0
BB		 1870};
1871
1872static const struct panel_desc foxlink_fl500wvr00_a0t = {
1873 .modes = &foxlink_fl500wvr00_a0t_mode,
1874 .num_modes = 1,
d7a839cd 1875 .bpc = 8,
102932b0
BB		 1876 .size = {
1877 .width = 108,
1878 .height = 65,
1879 },
bb276cb3 1880 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1881};
1882
795db2af
PC		 1883static const struct drm_display_mode frida_frd350h54004_modes[] = {
1884 { /* 60 Hz */
1885 .clock = 6000,
1886 .hdisplay = 320,
1887 .hsync_start = 320 + 44,
1888 .hsync_end = 320 + 44 + 16,
1889 .htotal = 320 + 44 + 16 + 20,
1890 .vdisplay = 240,
1891 .vsync_start = 240 + 2,
1892 .vsync_end = 240 + 2 + 6,
1893 .vtotal = 240 + 2 + 6 + 2,
1894 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1895 },
1896 { /* 50 Hz */
1897 .clock = 5400,
1898 .hdisplay = 320,
1899 .hsync_start = 320 + 56,
1900 .hsync_end = 320 + 56 + 16,
1901 .htotal = 320 + 56 + 16 + 40,
1902 .vdisplay = 240,
1903 .vsync_start = 240 + 2,
1904 .vsync_end = 240 + 2 + 6,
1905 .vtotal = 240 + 2 + 6 + 2,
1906 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1907 },
7b6bd843
PC		 1908};
1909
1910static const struct panel_desc frida_frd350h54004 = {
795db2af
PC		 1911 .modes = frida_frd350h54004_modes,
1912 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
7b6bd843
PC		 1913 .bpc = 8,
1914 .size = {
1915 .width = 77,
1916 .height = 64,
1917 },
1918 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
7b6bd843
PC		 1920 .connector_type = DRM_MODE_CONNECTOR_DPI,
1921};
1922
3be20710
JT		 1923static const struct drm_display_mode friendlyarm_hd702e_mode = {
1924 .clock = 67185,
1925 .hdisplay = 800,
1926 .hsync_start = 800 + 20,
1927 .hsync_end = 800 + 20 + 24,
1928 .htotal = 800 + 20 + 24 + 20,
1929 .vdisplay = 1280,
1930 .vsync_start = 1280 + 4,
1931 .vsync_end = 1280 + 4 + 8,
1932 .vtotal = 1280 + 4 + 8 + 4,
3be20710
JT		 1933 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1934};
1935
1936static const struct panel_desc friendlyarm_hd702e = {
1937 .modes = &friendlyarm_hd702e_mode,
1938 .num_modes = 1,
1939 .size = {
1940 .width = 94,
1941 .height = 151,
1942 },
1943};
1944
d435a2af
PZ		 1945static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1946 .clock = 9000,
1947 .hdisplay = 480,
1948 .hsync_start = 480 + 5,
1949 .hsync_end = 480 + 5 + 1,
1950 .htotal = 480 + 5 + 1 + 40,
1951 .vdisplay = 272,
1952 .vsync_start = 272 + 8,
1953 .vsync_end = 272 + 8 + 1,
1954 .vtotal = 272 + 8 + 1 + 8,
d435a2af
PZ		 1955};
1956
1957static const struct panel_desc giantplus_gpg482739qs5 = {
1958 .modes = &giantplus_gpg482739qs5_mode,
1959 .num_modes = 1,
1960 .bpc = 8,
1961 .size = {
1962 .width = 95,
1963 .height = 54,
1964 },
33536a09 1965 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1966};
1967
2c6574a9
PC		 1968static const struct display_timing giantplus_gpm940b0_timing = {
1969 .pixelclock = { 13500000, 27000000, 27500000 },
1970 .hactive = { 320, 320, 320 },
1971 .hfront_porch = { 14, 686, 718 },
1972 .hback_porch = { 50, 70, 255 },
1973 .hsync_len = { 1, 1, 1 },
1974 .vactive = { 240, 240, 240 },
1975 .vfront_porch = { 1, 1, 179 },
1976 .vback_porch = { 1, 21, 31 },
1977 .vsync_len = { 1, 1, 6 },
1978 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1979};
1980
1981static const struct panel_desc giantplus_gpm940b0 = {
1982 .timings = &giantplus_gpm940b0_timing,
1983 .num_timings = 1,
1984 .bpc = 8,
1985 .size = {
1986 .width = 60,
1987 .height = 45,
1988 },
1989 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
f5436f77 1990 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2c6574a9
PC		 1991};
1992
ab07725a
PZ		 1993static const struct display_timing hannstar_hsd070pww1_timing = {
1994 .pixelclock = { 64300000, 71100000, 82000000 },
1995 .hactive = { 1280, 1280, 1280 },
1996 .hfront_porch = { 1, 1, 10 },
1997 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1998 /*
1999 * According to the data sheet, the minimum horizontal blanking interval
2000 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2001 * minimum working horizontal blanking interval to be 60 clocks.
2002 */
2003 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 2004 .vactive = { 800, 800, 800 },
2005 .vfront_porch = { 1, 1, 10 },
2006 .vback_porch = { 1, 1, 10 },
2007 .vsync_len = { 1, 21, 203 },
2008 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 2009};
2010
2011static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 2012 .timings = &hannstar_hsd070pww1_timing,
2013 .num_timings = 1,
a853205e
PZ		 2014 .bpc = 6,
2015 .size = {
2016 .width = 151,
2017 .height = 94,
2018 },
58d6a7bc 2019 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2020 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 2021};
2022
c0d607e5
EN		 2023static const struct display_timing hannstar_hsd100pxn1_timing = {
2024 .pixelclock = { 55000000, 65000000, 75000000 },
2025 .hactive = { 1024, 1024, 1024 },
2026 .hfront_porch = { 40, 40, 40 },
2027 .hback_porch = { 220, 220, 220 },
2028 .hsync_len = { 20, 60, 100 },
2029 .vactive = { 768, 768, 768 },
2030 .vfront_porch = { 7, 7, 7 },
2031 .vback_porch = { 21, 21, 21 },
2032 .vsync_len = { 10, 10, 10 },
2033 .flags = DISPLAY_FLAGS_DE_HIGH,
2034};
2035
2036static const struct panel_desc hannstar_hsd100pxn1 = {
2037 .timings = &hannstar_hsd100pxn1_timing,
2038 .num_timings = 1,
2039 .bpc = 6,
2040 .size = {
2041 .width = 203,
2042 .height = 152,
2043 },
4946b043 2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2045 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 2046};
2047
61ac0bf8
LS		 2048static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2049 .clock = 33333,
2050 .hdisplay = 800,
2051 .hsync_start = 800 + 85,
2052 .hsync_end = 800 + 85 + 86,
2053 .htotal = 800 + 85 + 86 + 85,
2054 .vdisplay = 480,
2055 .vsync_start = 480 + 16,
2056 .vsync_end = 480 + 16 + 13,
2057 .vtotal = 480 + 16 + 13 + 16,
61ac0bf8
LS		 2058};
2059
2060static const struct panel_desc hitachi_tx23d38vm0caa = {
2061 .modes = &hitachi_tx23d38vm0caa_mode,
2062 .num_modes = 1,
2063 .bpc = 6,
2064 .size = {
2065 .width = 195,
2066 .height = 117,
2067 },
6c684e3b
PZ		 2068 .delay = {
2069 .enable = 160,
2070 .disable = 160,
2071 },
61ac0bf8
LS		 2072};
2073
41bcceb4
NF		 2074static const struct drm_display_mode innolux_at043tn24_mode = {
2075 .clock = 9000,
2076 .hdisplay = 480,
2077 .hsync_start = 480 + 2,
2078 .hsync_end = 480 + 2 + 41,
2079 .htotal = 480 + 2 + 41 + 2,
2080 .vdisplay = 272,
2081 .vsync_start = 272 + 2,
a483159d
PZ		 2082 .vsync_end = 272 + 2 + 10,
2083 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 2084 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2085};
2086
2087static const struct panel_desc innolux_at043tn24 = {
2088 .modes = &innolux_at043tn24_mode,
2089 .num_modes = 1,
2090 .bpc = 8,
2091 .size = {
2092 .width = 95,
2093 .height = 54,
2094 },
2095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2096 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 2097};
2098
4fc24ab3
RB		 2099static const struct drm_display_mode innolux_at070tn92_mode = {
2100 .clock = 33333,
2101 .hdisplay = 800,
2102 .hsync_start = 800 + 210,
2103 .hsync_end = 800 + 210 + 20,
2104 .htotal = 800 + 210 + 20 + 46,
2105 .vdisplay = 480,
2106 .vsync_start = 480 + 22,
2107 .vsync_end = 480 + 22 + 10,
2108 .vtotal = 480 + 22 + 23 + 10,
4fc24ab3
RB		 2109};
2110
2111static const struct panel_desc innolux_at070tn92 = {
2112 .modes = &innolux_at070tn92_mode,
2113 .num_modes = 1,
2114 .size = {
2115 .width = 154,
2116 .height = 86,
2117 },
2118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2119};
2120
a5d2ade6
CF		 2121static const struct display_timing innolux_g070y2_l01_timing = {
2122 .pixelclock = { 28000000, 29500000, 32000000 },
2123 .hactive = { 800, 800, 800 },
2124 .hfront_porch = { 61, 91, 141 },
2125 .hback_porch = { 60, 90, 140 },
2126 .hsync_len = { 12, 12, 12 },
2127 .vactive = { 480, 480, 480 },
2128 .vfront_porch = { 4, 9, 30 },
2129 .vback_porch = { 4, 8, 28 },
2130 .vsync_len = { 2, 2, 2 },
2131 .flags = DISPLAY_FLAGS_DE_HIGH,
2132};
2133
2134static const struct panel_desc innolux_g070y2_l01 = {
2135 .timings = &innolux_g070y2_l01_timing,
2136 .num_timings = 1,
2137 .bpc = 6,
2138 .size = {
2139 .width = 152,
2140 .height = 91,
2141 },
2142 .delay = {
2143 .prepare = 10,
2144 .enable = 100,
2145 .disable = 100,
2146 .unprepare = 800,
2147 },
2148 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2149 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 2150};
2151
1e29b840
MO		 2152static const struct display_timing innolux_g101ice_l01_timing = {
2153 .pixelclock = { 60400000, 71100000, 74700000 },
2154 .hactive = { 1280, 1280, 1280 },
2155 .hfront_porch = { 41, 80, 100 },
2156 .hback_porch = { 40, 79, 99 },
2157 .hsync_len = { 1, 1, 1 },
2158 .vactive = { 800, 800, 800 },
2159 .vfront_porch = { 5, 11, 14 },
2160 .vback_porch = { 4, 11, 14 },
2161 .vsync_len = { 1, 1, 1 },
2162 .flags = DISPLAY_FLAGS_DE_HIGH,
2163};
2164
2165static const struct panel_desc innolux_g101ice_l01 = {
2166 .timings = &innolux_g101ice_l01_timing,
2167 .num_timings = 1,
2168 .bpc = 8,
2169 .size = {
2170 .width = 217,
2171 .height = 135,
2172 },
2173 .delay = {
2174 .enable = 200,
2175 .disable = 200,
2176 },
2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2178 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 2179};
2180
4ae13e48
LS		 2181static const struct display_timing innolux_g121i1_l01_timing = {
2182 .pixelclock = { 67450000, 71000000, 74550000 },
2183 .hactive = { 1280, 1280, 1280 },
2184 .hfront_porch = { 40, 80, 160 },
2185 .hback_porch = { 39, 79, 159 },
2186 .hsync_len = { 1, 1, 1 },
2187 .vactive = { 800, 800, 800 },
2188 .vfront_porch = { 5, 11, 100 },
2189 .vback_porch = { 4, 11, 99 },
2190 .vsync_len = { 1, 1, 1 },
d731f661
LS		 2191};
2192
2193static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 2194 .timings = &innolux_g121i1_l01_timing,
2195 .num_timings = 1,
d731f661
LS		 2196 .bpc = 6,
2197 .size = {
2198 .width = 261,
2199 .height = 163,
2200 },
4ae13e48
LS		 2201 .delay = {
2202 .enable = 200,
2203 .disable = 20,
2204 },
2205 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2206 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 2207};
2208
f8fa17ba
AB		 2209static const struct drm_display_mode innolux_g121x1_l03_mode = {
2210 .clock = 65000,
2211 .hdisplay = 1024,
2212 .hsync_start = 1024 + 0,
2213 .hsync_end = 1024 + 1,
2214 .htotal = 1024 + 0 + 1 + 320,
2215 .vdisplay = 768,
2216 .vsync_start = 768 + 38,
2217 .vsync_end = 768 + 38 + 1,
2218 .vtotal = 768 + 38 + 1 + 0,
2e8c5eb9 2219 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 2220};
2221
2222static const struct panel_desc innolux_g121x1_l03 = {
2223 .modes = &innolux_g121x1_l03_mode,
2224 .num_modes = 1,
2225 .bpc = 6,
2226 .size = {
2227 .width = 246,
2228 .height = 185,
2229 },
2230 .delay = {
2231 .enable = 200,
2232 .unprepare = 200,
2233 .disable = 400,
2234 },
2235};
2236
d719cbe9
DA		 2237/*
2238 * Datasheet specifies that at 60 Hz refresh rate:
2239 * - total horizontal time: { 1506, 1592, 1716 }
2240 * - total vertical time: { 788, 800, 868 }
2241 *
2242 * ...but doesn't go into exactly how that should be split into a front
2243 * porch, back porch, or sync length. For now we'll leave a single setting
2244 * here which allows a bit of tweaking of the pixel clock at the expense of
2245 * refresh rate.
2246 */
2247static const struct display_timing innolux_n116bge_timing = {
2248 .pixelclock = { 72600000, 76420000, 80240000 },
2249 .hactive = { 1366, 1366, 1366 },
2250 .hfront_porch = { 136, 136, 136 },
2251 .hback_porch = { 60, 60, 60 },
2252 .hsync_len = { 30, 30, 30 },
2253 .vactive = { 768, 768, 768 },
2254 .vfront_porch = { 8, 8, 8 },
2255 .vback_porch = { 12, 12, 12 },
2256 .vsync_len = { 12, 12, 12 },
2257 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
0a2288c0
TR		 2258};
2259
2260static const struct panel_desc innolux_n116bge = {
d719cbe9
DA		 2261 .timings = &innolux_n116bge_timing,
2262 .num_timings = 1,
0a2288c0
TR		 2263 .bpc = 6,
2264 .size = {
2265 .width = 256,
2266 .height = 144,
2267 },
2268};
2269
a14c6b0e
LH		 2270static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2271 .clock = 162000,
2272 .hdisplay = 1920,
2273 .hsync_start = 1920 + 40,
2274 .hsync_end = 1920 + 40 + 40,
2275 .htotal = 1920 + 40 + 40 + 80,
2276 .vdisplay = 1080,
2277 .vsync_start = 1080 + 4,
2278 .vsync_end = 1080 + 4 + 4,
2279 .vtotal = 1080 + 4 + 4 + 24,
2280};
2281
2282static const struct panel_desc innolux_n125hce_gn1 = {
2283 .modes = &innolux_n125hce_gn1_mode,
2284 .num_modes = 1,
2285 .bpc = 8,
2286 .size = {
2287 .width = 276,
2288 .height = 155,
2289 },
2290 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2291 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2292 .connector_type = DRM_MODE_CONNECTOR_eDP,
2293};
2294
ea44739d
AB		 2295static const struct drm_display_mode innolux_n156bge_l21_mode = {
2296 .clock = 69300,
2297 .hdisplay = 1366,
2298 .hsync_start = 1366 + 16,
2299 .hsync_end = 1366 + 16 + 34,
2300 .htotal = 1366 + 16 + 34 + 50,
2301 .vdisplay = 768,
2302 .vsync_start = 768 + 2,
2303 .vsync_end = 768 + 2 + 6,
2304 .vtotal = 768 + 2 + 6 + 12,
ea44739d
AB		 2305};
2306
2307static const struct panel_desc innolux_n156bge_l21 = {
2308 .modes = &innolux_n156bge_l21_mode,
2309 .num_modes = 1,
0208d511 2310 .bpc = 6,
ea44739d
AB		 2311 .size = {
2312 .width = 344,
2313 .height = 193,
2314 },
85560829 2315 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 2316 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 2317 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ea44739d
AB		 2318};
2319
8f054b6f 2320static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 2321 .clock = 206016,
2322 .hdisplay = 2160,
2323 .hsync_start = 2160 + 48,
2324 .hsync_end = 2160 + 48 + 32,
2325 .htotal = 2160 + 48 + 32 + 80,
2326 .vdisplay = 1440,
2327 .vsync_start = 1440 + 3,
2328 .vsync_end = 1440 + 3 + 10,
2329 .vtotal = 1440 + 3 + 10 + 27,
da50bd42 2330 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2331};
2332
8f054b6f
DA		 2333static const struct panel_desc innolux_p120zdg_bf1 = {
2334 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 2335 .num_modes = 1,
2336 .bpc = 8,
2337 .size = {
8f054b6f
DA		 2338 .width = 254,
2339 .height = 169,
da50bd42 2340 },
22fd99e9 2341 .delay = {
625d3b5c 2342 .hpd_absent_delay = 200,
22fd99e9
SP		 2343 .unprepare = 500,
2344 },
da50bd42 2345};
2346
bccac3f1
MG		 2347static const struct drm_display_mode innolux_zj070na_01p_mode = {
2348 .clock = 51501,
2349 .hdisplay = 1024,
2350 .hsync_start = 1024 + 128,
2351 .hsync_end = 1024 + 128 + 64,
2352 .htotal = 1024 + 128 + 64 + 128,
2353 .vdisplay = 600,
2354 .vsync_start = 600 + 16,
2355 .vsync_end = 600 + 16 + 4,
2356 .vtotal = 600 + 16 + 4 + 16,
bccac3f1
MG		 2357};
2358
2359static const struct panel_desc innolux_zj070na_01p = {
2360 .modes = &innolux_zj070na_01p_mode,
2361 .num_modes = 1,
2362 .bpc = 6,
2363 .size = {
81598846
TR		 2364 .width = 154,
2365 .height = 90,
bccac3f1
MG		 2366 },
2367};
2368
e1ca5184
BA		 2369static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2370 .clock = 138778,
2371 .hdisplay = 1920,
2372 .hsync_start = 1920 + 24,
2373 .hsync_end = 1920 + 24 + 48,
2374 .htotal = 1920 + 24 + 48 + 88,
2375 .vdisplay = 1080,
2376 .vsync_start = 1080 + 3,
2377 .vsync_end = 1080 + 3 + 12,
2378 .vtotal = 1080 + 3 + 12 + 17,
e1ca5184
BA		 2379 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2380};
2381
2382static const struct panel_desc ivo_m133nwf4_r0 = {
2383 .modes = &ivo_m133nwf4_r0_mode,
2384 .num_modes = 1,
2385 .bpc = 8,
2386 .size = {
2387 .width = 294,
2388 .height = 165,
2389 },
2390 .delay = {
2391 .hpd_absent_delay = 200,
2392 .unprepare = 500,
2393 },
2394 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2395 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2396 .connector_type = DRM_MODE_CONNECTOR_eDP,
2397};
2398
fc26a375
DA		 2399static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2400 .clock = 81000,
2401 .hdisplay = 1366,
2402 .hsync_start = 1366 + 40,
2403 .hsync_end = 1366 + 40 + 32,
2404 .htotal = 1366 + 40 + 32 + 62,
2405 .vdisplay = 768,
2406 .vsync_start = 768 + 5,
2407 .vsync_end = 768 + 5 + 5,
2408 .vtotal = 768 + 5 + 5 + 122,
2409 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2410};
2411
2412static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2413 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2414 .num_modes = 1,
2415 .bpc = 6,
2416 .size = {
2417 .width = 256,
2418 .height = 144,
2419 },
2420 .delay = {
2421 .hpd_absent_delay = 200,
2422 },
2423 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2424 .connector_type = DRM_MODE_CONNECTOR_eDP,
2425};
2426
14bf60c4
LM		 2427static const struct display_timing koe_tx14d24vm1bpa_timing = {
2428 .pixelclock = { 5580000, 5850000, 6200000 },
2429 .hactive = { 320, 320, 320 },
2430 .hfront_porch = { 30, 30, 30 },
2431 .hback_porch = { 30, 30, 30 },
2432 .hsync_len = { 1, 5, 17 },
2433 .vactive = { 240, 240, 240 },
2434 .vfront_porch = { 6, 6, 6 },
2435 .vback_porch = { 5, 5, 5 },
2436 .vsync_len = { 1, 2, 11 },
2437 .flags = DISPLAY_FLAGS_DE_HIGH,
2438};
2439
2440static const struct panel_desc koe_tx14d24vm1bpa = {
2441 .timings = &koe_tx14d24vm1bpa_timing,
2442 .num_timings = 1,
2443 .bpc = 6,
2444 .size = {
2445 .width = 115,
2446 .height = 86,
2447 },
2448};
2449
8a070524
LY		 2450static const struct display_timing koe_tx26d202vm0bwa_timing = {
2451 .pixelclock = { 151820000, 156720000, 159780000 },
2452 .hactive = { 1920, 1920, 1920 },
2453 .hfront_porch = { 105, 130, 142 },
2454 .hback_porch = { 45, 70, 82 },
2455 .hsync_len = { 30, 30, 30 },
2456 .vactive = { 1200, 1200, 1200},
2457 .vfront_porch = { 3, 5, 10 },
2458 .vback_porch = { 2, 5, 10 },
2459 .vsync_len = { 5, 5, 5 },
2460};
2461
2462static const struct panel_desc koe_tx26d202vm0bwa = {
2463 .timings = &koe_tx26d202vm0bwa_timing,
2464 .num_timings = 1,
2465 .bpc = 8,
2466 .size = {
2467 .width = 217,
2468 .height = 136,
2469 },
2470 .delay = {
2471 .prepare = 1000,
2472 .enable = 1000,
2473 .unprepare = 1000,
2474 .disable = 1000,
2475 },
2476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2477 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
8a070524
LY		 2478 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2479};
2480
8cfe8341
JT		 2481static const struct display_timing koe_tx31d200vm0baa_timing = {
2482 .pixelclock = { 39600000, 43200000, 48000000 },
2483 .hactive = { 1280, 1280, 1280 },
2484 .hfront_porch = { 16, 36, 56 },
2485 .hback_porch = { 16, 36, 56 },
2486 .hsync_len = { 8, 8, 8 },
2487 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 2488 .vfront_porch = { 6, 21, 33 },
2489 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 2490 .vsync_len = { 8, 8, 8 },
2491 .flags = DISPLAY_FLAGS_DE_HIGH,
2492};
2493
2494static const struct panel_desc koe_tx31d200vm0baa = {
2495 .timings = &koe_tx31d200vm0baa_timing,
2496 .num_timings = 1,
2497 .bpc = 6,
2498 .size = {
2499 .width = 292,
2500 .height = 109,
2501 },
2502 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2503 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 2504};
2505
8def22e5
LS		 2506static const struct display_timing kyo_tcg121xglp_timing = {
2507 .pixelclock = { 52000000, 65000000, 71000000 },
2508 .hactive = { 1024, 1024, 1024 },
2509 .hfront_porch = { 2, 2, 2 },
2510 .hback_porch = { 2, 2, 2 },
2511 .hsync_len = { 86, 124, 244 },
2512 .vactive = { 768, 768, 768 },
2513 .vfront_porch = { 2, 2, 2 },
2514 .vback_porch = { 2, 2, 2 },
2515 .vsync_len = { 6, 34, 73 },
2516 .flags = DISPLAY_FLAGS_DE_HIGH,
2517};
2518
2519static const struct panel_desc kyo_tcg121xglp = {
2520 .timings = &kyo_tcg121xglp_timing,
2521 .num_timings = 1,
2522 .bpc = 8,
2523 .size = {
2524 .width = 246,
2525 .height = 184,
2526 },
2527 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2528 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 2529};
2530
27abdd83
PK		 2531static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2532 .clock = 7000,
2533 .hdisplay = 320,
2534 .hsync_start = 320 + 20,
2535 .hsync_end = 320 + 20 + 30,
2536 .htotal = 320 + 20 + 30 + 38,
2537 .vdisplay = 240,
2538 .vsync_start = 240 + 4,
2539 .vsync_end = 240 + 4 + 3,
2540 .vtotal = 240 + 4 + 3 + 15,
27abdd83
PK		 2541};
2542
2543static const struct panel_desc lemaker_bl035_rgb_002 = {
2544 .modes = &lemaker_bl035_rgb_002_mode,
2545 .num_modes = 1,
2546 .size = {
2547 .width = 70,
2548 .height = 52,
2549 },
2550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2551 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2552};
2553
dd015002
HS		 2554static const struct drm_display_mode lg_lb070wv8_mode = {
2555 .clock = 33246,
2556 .hdisplay = 800,
2557 .hsync_start = 800 + 88,
2558 .hsync_end = 800 + 88 + 80,
2559 .htotal = 800 + 88 + 80 + 88,
2560 .vdisplay = 480,
2561 .vsync_start = 480 + 10,
2562 .vsync_end = 480 + 10 + 25,
2563 .vtotal = 480 + 10 + 25 + 10,
dd015002
HS		 2564};
2565
2566static const struct panel_desc lg_lb070wv8 = {
2567 .modes = &lg_lb070wv8_mode,
2568 .num_modes = 1,
a6ae2fe5 2569 .bpc = 8,
dd015002
HS		 2570 .size = {
2571 .width = 151,
2572 .height = 91,
2573 },
2574 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2575 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 2576};
2577
c5ece402
YY		 2578static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2579 .clock = 200000,
2580 .hdisplay = 1536,
2581 .hsync_start = 1536 + 12,
2582 .hsync_end = 1536 + 12 + 16,
2583 .htotal = 1536 + 12 + 16 + 48,
2584 .vdisplay = 2048,
2585 .vsync_start = 2048 + 8,
2586 .vsync_end = 2048 + 8 + 4,
2587 .vtotal = 2048 + 8 + 4 + 8,
c5ece402
YY		 2588 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2589};
2590
2591static const struct panel_desc lg_lp079qx1_sp0v = {
2592 .modes = &lg_lp079qx1_sp0v_mode,
2593 .num_modes = 1,
2594 .size = {
2595 .width = 129,
2596 .height = 171,
2597 },
2598};
2599
0355dde2
YY		 2600static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2601 .clock = 205210,
2602 .hdisplay = 2048,
2603 .hsync_start = 2048 + 150,
2604 .hsync_end = 2048 + 150 + 5,
2605 .htotal = 2048 + 150 + 5 + 5,
2606 .vdisplay = 1536,
2607 .vsync_start = 1536 + 3,
2608 .vsync_end = 1536 + 3 + 1,
2609 .vtotal = 1536 + 3 + 1 + 9,
0355dde2
YY		 2610};
2611
2612static const struct panel_desc lg_lp097qx1_spa1 = {
2613 .modes = &lg_lp097qx1_spa1_mode,
2614 .num_modes = 1,
2615 .size = {
2616 .width = 208,
2617 .height = 147,
2618 },
2619};
2620
690d8fa7
JS		 2621static const struct drm_display_mode lg_lp120up1_mode = {
2622 .clock = 162300,
2623 .hdisplay = 1920,
2624 .hsync_start = 1920 + 40,
2625 .hsync_end = 1920 + 40 + 40,
2626 .htotal = 1920 + 40 + 40+ 80,
2627 .vdisplay = 1280,
2628 .vsync_start = 1280 + 4,
2629 .vsync_end = 1280 + 4 + 4,
2630 .vtotal = 1280 + 4 + 4 + 12,
690d8fa7
JS		 2631};
2632
2633static const struct panel_desc lg_lp120up1 = {
2634 .modes = &lg_lp120up1_mode,
2635 .num_modes = 1,
2636 .bpc = 8,
2637 .size = {
2638 .width = 267,
2639 .height = 183,
2640 },
d53139b3 2641 .connector_type = DRM_MODE_CONNECTOR_eDP,
690d8fa7
JS		 2642};
2643
ec7c5653
TR		 2644static const struct drm_display_mode lg_lp129qe_mode = {
2645 .clock = 285250,
2646 .hdisplay = 2560,
2647 .hsync_start = 2560 + 48,
2648 .hsync_end = 2560 + 48 + 32,
2649 .htotal = 2560 + 48 + 32 + 80,
2650 .vdisplay = 1700,
2651 .vsync_start = 1700 + 3,
2652 .vsync_end = 1700 + 3 + 10,
2653 .vtotal = 1700 + 3 + 10 + 36,
ec7c5653
TR		 2654};
2655
2656static const struct panel_desc lg_lp129qe = {
2657 .modes = &lg_lp129qe_mode,
2658 .num_modes = 1,
0208d511 2659 .bpc = 8,
ec7c5653
TR		 2660 .size = {
2661 .width = 272,
2662 .height = 181,
2663 },
2664};
2665
5728fe7f
MZ		 2666static const struct display_timing logictechno_lt161010_2nh_timing = {
2667 .pixelclock = { 26400000, 33300000, 46800000 },
2668 .hactive = { 800, 800, 800 },
2669 .hfront_porch = { 16, 210, 354 },
2670 .hback_porch = { 46, 46, 46 },
2671 .hsync_len = { 1, 20, 40 },
2672 .vactive = { 480, 480, 480 },
2673 .vfront_porch = { 7, 22, 147 },
2674 .vback_porch = { 23, 23, 23 },
2675 .vsync_len = { 1, 10, 20 },
2676 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2677 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2678 DISPLAY_FLAGS_SYNC_POSEDGE,
2679};
2680
2681static const struct panel_desc logictechno_lt161010_2nh = {
2682 .timings = &logictechno_lt161010_2nh_timing,
2683 .num_timings = 1,
2684 .size = {
2685 .width = 154,
2686 .height = 86,
2687 },
2688 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2689 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2690 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2691 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2692 .connector_type = DRM_MODE_CONNECTOR_DPI,
2693};
2694
2695static const struct display_timing logictechno_lt170410_2whc_timing = {
2696 .pixelclock = { 68900000, 71100000, 73400000 },
2697 .hactive = { 1280, 1280, 1280 },
2698 .hfront_porch = { 23, 60, 71 },
2699 .hback_porch = { 23, 60, 71 },
2700 .hsync_len = { 15, 40, 47 },
2701 .vactive = { 800, 800, 800 },
2702 .vfront_porch = { 5, 7, 10 },
2703 .vback_porch = { 5, 7, 10 },
2704 .vsync_len = { 6, 9, 12 },
2705 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2706 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2707 DISPLAY_FLAGS_SYNC_POSEDGE,
2708};
2709
2710static const struct panel_desc logictechno_lt170410_2whc = {
2711 .timings = &logictechno_lt170410_2whc_timing,
2712 .num_timings = 1,
2713 .size = {
2714 .width = 217,
2715 .height = 136,
2716 },
2717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2718 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
5728fe7f
MZ		 2719 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2720};
2721
65c766ca
LM		 2722static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2723 .clock = 30400,
2724 .hdisplay = 800,
2725 .hsync_start = 800 + 0,
2726 .hsync_end = 800 + 1,
2727 .htotal = 800 + 0 + 1 + 160,
2728 .vdisplay = 480,
2729 .vsync_start = 480 + 0,
2730 .vsync_end = 480 + 48 + 1,
2731 .vtotal = 480 + 48 + 1 + 0,
65c766ca
LM		 2732 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2733};
2734
0d35408a 2735static const struct drm_display_mode logicpd_type_28_mode = {
f873c5d8 2736 .clock = 9107,
0d35408a
AF		 2737 .hdisplay = 480,
2738 .hsync_start = 480 + 3,
2739 .hsync_end = 480 + 3 + 42,
2740 .htotal = 480 + 3 + 42 + 2,
2741
2742 .vdisplay = 272,
2743 .vsync_start = 272 + 2,
2744 .vsync_end = 272 + 2 + 11,
2745 .vtotal = 272 + 2 + 11 + 3,
0d35408a
AF		 2746 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2747};
2748
2749static const struct panel_desc logicpd_type_28 = {
2750 .modes = &logicpd_type_28_mode,
2751 .num_modes = 1,
2752 .bpc = 8,
2753 .size = {
2754 .width = 105,
2755 .height = 67,
2756 },
2757 .delay = {
2758 .prepare = 200,
2759 .enable = 200,
2760 .unprepare = 200,
2761 .disable = 200,
2762 },
2763 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2765 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
efb94790 2766 .connector_type = DRM_MODE_CONNECTOR_DPI,
0d35408a
AF		 2767};
2768
65c766ca
LM		 2769static const struct panel_desc mitsubishi_aa070mc01 = {
2770 .modes = &mitsubishi_aa070mc01_mode,
2771 .num_modes = 1,
2772 .bpc = 8,
2773 .size = {
2774 .width = 152,
2775 .height = 91,
2776 },
2777
2778 .delay = {
2779 .enable = 200,
2780 .unprepare = 200,
2781 .disable = 400,
2782 },
2783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2784 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 2785 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2786};
2787
01bacc13
LS		 2788static const struct display_timing nec_nl12880bc20_05_timing = {
2789 .pixelclock = { 67000000, 71000000, 75000000 },
2790 .hactive = { 1280, 1280, 1280 },
2791 .hfront_porch = { 2, 30, 30 },
2792 .hback_porch = { 6, 100, 100 },
2793 .hsync_len = { 2, 30, 30 },
2794 .vactive = { 800, 800, 800 },
2795 .vfront_porch = { 5, 5, 5 },
2796 .vback_porch = { 11, 11, 11 },
2797 .vsync_len = { 7, 7, 7 },
2798};
2799
2800static const struct panel_desc nec_nl12880bc20_05 = {
2801 .timings = &nec_nl12880bc20_05_timing,
2802 .num_timings = 1,
2803 .bpc = 8,
2804 .size = {
2805 .width = 261,
2806 .height = 163,
2807 },
2808 .delay = {
2809 .enable = 50,
2810 .disable = 50,
2811 },
2812 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2813 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 2814};
2815
c6e87f91 2816static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2817 .clock = 10870,
2818 .hdisplay = 480,
2819 .hsync_start = 480 + 2,
2820 .hsync_end = 480 + 2 + 41,
2821 .htotal = 480 + 2 + 41 + 2,
2822 .vdisplay = 272,
2823 .vsync_start = 272 + 2,
2824 .vsync_end = 272 + 2 + 4,
2825 .vtotal = 272 + 2 + 4 + 2,
4bc390c6 2826 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 2827};
2828
2829static const struct panel_desc nec_nl4827hc19_05b = {
2830 .modes = &nec_nl4827hc19_05b_mode,
2831 .num_modes = 1,
2832 .bpc = 8,
2833 .size = {
2834 .width = 95,
2835 .height = 54,
2836 },
2c80661d 2837 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2838 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 2839};
2840
e6c2f066
MR		 2841static const struct drm_display_mode netron_dy_e231732_mode = {
2842 .clock = 66000,
2843 .hdisplay = 1024,
2844 .hsync_start = 1024 + 160,
2845 .hsync_end = 1024 + 160 + 70,
2846 .htotal = 1024 + 160 + 70 + 90,
2847 .vdisplay = 600,
2848 .vsync_start = 600 + 127,
2849 .vsync_end = 600 + 127 + 20,
2850 .vtotal = 600 + 127 + 20 + 3,
e6c2f066
MR		 2851};
2852
2853static const struct panel_desc netron_dy_e231732 = {
2854 .modes = &netron_dy_e231732_mode,
2855 .num_modes = 1,
2856 .size = {
2857 .width = 154,
2858 .height = 87,
2859 },
2860 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2861};
2862
258145ea
VK		 2863static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2864 {
2865 .clock = 138500,
2866 .hdisplay = 1920,
2867 .hsync_start = 1920 + 48,
2868 .hsync_end = 1920 + 48 + 32,
2869 .htotal = 1920 + 48 + 32 + 80,
2870 .vdisplay = 1080,
2871 .vsync_start = 1080 + 3,
2872 .vsync_end = 1080 + 3 + 5,
2873 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 2874 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2875 }, {
2876 .clock = 110920,
2877 .hdisplay = 1920,
2878 .hsync_start = 1920 + 48,
2879 .hsync_end = 1920 + 48 + 32,
2880 .htotal = 1920 + 48 + 32 + 80,
2881 .vdisplay = 1080,
2882 .vsync_start = 1080 + 3,
2883 .vsync_end = 1080 + 3 + 5,
2884 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 2885 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2886 }
2887};
2888
2889static const struct panel_desc neweast_wjfh116008a = {
2890 .modes = neweast_wjfh116008a_modes,
2891 .num_modes = 2,
2892 .bpc = 6,
2893 .size = {
2894 .width = 260,
2895 .height = 150,
2896 },
2897 .delay = {
2898 .prepare = 110,
2899 .enable = 20,
2900 .unprepare = 500,
2901 },
2902 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2903 .connector_type = DRM_MODE_CONNECTOR_eDP,
2904};
2905
3b39ad7a
TV		 2906static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2907 .clock = 9000,
2908 .hdisplay = 480,
2909 .hsync_start = 480 + 2,
2910 .hsync_end = 480 + 2 + 41,
2911 .htotal = 480 + 2 + 41 + 2,
2912 .vdisplay = 272,
2913 .vsync_start = 272 + 2,
2914 .vsync_end = 272 + 2 + 10,
2915 .vtotal = 272 + 2 + 10 + 2,
3b39ad7a
TV		 2916 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2917};
2918
2919static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2920 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2921 .num_modes = 1,
2922 .bpc = 8,
2923 .size = {
2924 .width = 95,
2925 .height = 54,
2926 },
2927 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 2928 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2929 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
8a4f5e11 2930 .connector_type = DRM_MODE_CONNECTOR_DPI,
3b39ad7a
TV		 2931};
2932
4177fa66
LS		 2933static const struct display_timing nlt_nl192108ac18_02d_timing = {
2934 .pixelclock = { 130000000, 148350000, 163000000 },
2935 .hactive = { 1920, 1920, 1920 },
2936 .hfront_porch = { 80, 100, 100 },
2937 .hback_porch = { 100, 120, 120 },
2938 .hsync_len = { 50, 60, 60 },
2939 .vactive = { 1080, 1080, 1080 },
2940 .vfront_porch = { 12, 30, 30 },
2941 .vback_porch = { 4, 10, 10 },
2942 .vsync_len = { 4, 5, 5 },
2943};
2944
2945static const struct panel_desc nlt_nl192108ac18_02d = {
2946 .timings = &nlt_nl192108ac18_02d_timing,
2947 .num_timings = 1,
2948 .bpc = 8,
2949 .size = {
2950 .width = 344,
2951 .height = 194,
2952 },
2953 .delay = {
2954 .unprepare = 500,
2955 },
2956 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2957 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 2958};
2959
05ec0e45
FL		 2960static const struct drm_display_mode nvd_9128_mode = {
2961 .clock = 29500,
2962 .hdisplay = 800,
2963 .hsync_start = 800 + 130,
2964 .hsync_end = 800 + 130 + 98,
2965 .htotal = 800 + 0 + 130 + 98,
2966 .vdisplay = 480,
2967 .vsync_start = 480 + 10,
2968 .vsync_end = 480 + 10 + 50,
2969 .vtotal = 480 + 0 + 10 + 50,
2970};
2971
2972static const struct panel_desc nvd_9128 = {
2973 .modes = &nvd_9128_mode,
2974 .num_modes = 1,
2975 .bpc = 8,
2976 .size = {
2977 .width = 156,
2978 .height = 88,
2979 },
2980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2981 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 2982};
2983
a99fb626
GB		 2984static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2985 .pixelclock = { 30000000, 30000000, 40000000 },
2986 .hactive = { 800, 800, 800 },
2987 .hfront_porch = { 40, 40, 40 },
2988 .hback_porch = { 40, 40, 40 },
2989 .hsync_len = { 1, 48, 48 },
2990 .vactive = { 480, 480, 480 },
2991 .vfront_porch = { 13, 13, 13 },
2992 .vback_porch = { 29, 29, 29 },
2993 .vsync_len = { 3, 3, 3 },
2994 .flags = DISPLAY_FLAGS_DE_HIGH,
2995};
2996
2997static const struct panel_desc okaya_rs800480t_7x0gp = {
2998 .timings = &okaya_rs800480t_7x0gp_timing,
2999 .num_timings = 1,
3000 .bpc = 6,
3001 .size = {
3002 .width = 154,
3003 .height = 87,
3004 },
3005 .delay = {
3006 .prepare = 41,
3007 .enable = 50,
3008 .unprepare = 41,
3009 .disable = 50,
3010 },
3011 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3012};
3013
cf5c9e6d
MR		 3014static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3015 .clock = 9000,
3016 .hdisplay = 480,
3017 .hsync_start = 480 + 5,
3018 .hsync_end = 480 + 5 + 30,
3019 .htotal = 480 + 5 + 30 + 10,
3020 .vdisplay = 272,
3021 .vsync_start = 272 + 8,
3022 .vsync_end = 272 + 8 + 5,
3023 .vtotal = 272 + 8 + 5 + 3,
cf5c9e6d
MR		 3024};
3025
3026static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3027 .modes = &olimex_lcd_olinuxino_43ts_mode,
3028 .num_modes = 1,
3029 .size = {
30c6d7ab
JL		 3030 .width = 95,
3031 .height = 54,
cf5c9e6d 3032 },
5c2a7c6b 3033 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 3034};
3035
e8b6f561
EA		 3036/*
3037 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3038 * pixel clocks, but this is the timing that was being used in the Adafruit
3039 * installation instructions.
3040 */
3041static const struct drm_display_mode ontat_yx700wv03_mode = {
3042 .clock = 29500,
3043 .hdisplay = 800,
3044 .hsync_start = 824,
3045 .hsync_end = 896,
3046 .htotal = 992,
3047 .vdisplay = 480,
3048 .vsync_start = 483,
3049 .vsync_end = 493,
3050 .vtotal = 500,
e8b6f561
EA		 3051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3052};
3053
3054/*
3055 * Specification at:
3056 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3057 */
3058static const struct panel_desc ontat_yx700wv03 = {
3059 .modes = &ontat_yx700wv03_mode,
3060 .num_modes = 1,
3061 .bpc = 8,
3062 .size = {
3063 .width = 154,
3064 .height = 83,
3065 },
5651e5e0 3066 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 3067};
3068
9c31dcb6 3069static const struct drm_display_mode ortustech_com37h3m_mode = {
855e764d 3070 .clock = 22230,
9c31dcb6 3071 .hdisplay = 480,
855e764d
NS		 3072 .hsync_start = 480 + 40,
3073 .hsync_end = 480 + 40 + 10,
3074 .htotal = 480 + 40 + 10 + 40,
9c31dcb6
NS		 3075 .vdisplay = 640,
3076 .vsync_start = 640 + 4,
855e764d
NS		 3077 .vsync_end = 640 + 4 + 2,
3078 .vtotal = 640 + 4 + 2 + 4,
9c31dcb6
NS		 3079 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3080};
3081
3082static const struct panel_desc ortustech_com37h3m = {
3083 .modes = &ortustech_com37h3m_mode,
3084 .num_modes = 1,
3085 .bpc = 8,
3086 .size = {
3087 .width = 56, /* 56.16mm */
3088 .height = 75, /* 74.88mm */
3089 },
3090 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3091 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
9c31dcb6
NS		 3092 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3093};
3094
725c9d40
PZ		 3095static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3096 .clock = 25000,
3097 .hdisplay = 480,
3098 .hsync_start = 480 + 10,
3099 .hsync_end = 480 + 10 + 10,
3100 .htotal = 480 + 10 + 10 + 15,
3101 .vdisplay = 800,
3102 .vsync_start = 800 + 3,
3103 .vsync_end = 800 + 3 + 3,
3104 .vtotal = 800 + 3 + 3 + 3,
725c9d40
PZ		 3105};
3106
3107static const struct panel_desc ortustech_com43h4m85ulc = {
3108 .modes = &ortustech_com43h4m85ulc_mode,
3109 .num_modes = 1,
3b809516 3110 .bpc = 6,
725c9d40
PZ		 3111 .size = {
3112 .width = 56,
3113 .height = 93,
3114 },
f098f168 3115 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 3116 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2ccedf46 3117 .connector_type = DRM_MODE_CONNECTOR_DPI,
725c9d40
PZ		 3118};
3119
163f7a35
LP		 3120static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3121 .clock = 33000,
3122 .hdisplay = 800,
3123 .hsync_start = 800 + 210,
3124 .hsync_end = 800 + 210 + 30,
3125 .htotal = 800 + 210 + 30 + 16,
3126 .vdisplay = 480,
3127 .vsync_start = 480 + 22,
3128 .vsync_end = 480 + 22 + 13,
3129 .vtotal = 480 + 22 + 13 + 10,
163f7a35
LP		 3130 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3131};
3132
3133static const struct panel_desc osddisplays_osd070t1718_19ts = {
3134 .modes = &osddisplays_osd070t1718_19ts_mode,
3135 .num_modes = 1,
3136 .bpc = 8,
3137 .size = {
3138 .width = 152,
3139 .height = 91,
3140 },
3141 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
fb0629ee
TV		 3142 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3143 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
a793f0ee 3144 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 3145};
3146
4ba3e563
EH		 3147static const struct drm_display_mode pda_91_00156_a0_mode = {
3148 .clock = 33300,
3149 .hdisplay = 800,
3150 .hsync_start = 800 + 1,
3151 .hsync_end = 800 + 1 + 64,
3152 .htotal = 800 + 1 + 64 + 64,
3153 .vdisplay = 480,
3154 .vsync_start = 480 + 1,
3155 .vsync_end = 480 + 1 + 23,
3156 .vtotal = 480 + 1 + 23 + 22,
4ba3e563
EH		 3157};
3158
3159static const struct panel_desc pda_91_00156_a0 = {
3160 .modes = &pda_91_00156_a0_mode,
3161 .num_modes = 1,
3162 .size = {
3163 .width = 152,
3164 .height = 91,
3165 },
3166 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3167};
3168
d69de69f
MV		 3169static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3170 .clock = 24750,
3171 .hdisplay = 800,
3172 .hsync_start = 800 + 54,
3173 .hsync_end = 800 + 54 + 2,
3174 .htotal = 800 + 54 + 2 + 44,
3175 .vdisplay = 480,
3176 .vsync_start = 480 + 49,
3177 .vsync_end = 480 + 49 + 2,
3178 .vtotal = 480 + 49 + 2 + 22,
3179};
3180
3181static const struct panel_desc powertip_ph800480t013_idf02 = {
3182 .modes = &powertip_ph800480t013_idf02_mode,
3183 .num_modes = 1,
3184 .size = {
3185 .width = 152,
3186 .height = 91,
3187 },
3188 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3189 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3190 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3192 .connector_type = DRM_MODE_CONNECTOR_DPI,
3193};
4ba3e563 3194
d2a6f0f5
JW		 3195static const struct drm_display_mode qd43003c0_40_mode = {
3196 .clock = 9000,
3197 .hdisplay = 480,
3198 .hsync_start = 480 + 8,
3199 .hsync_end = 480 + 8 + 4,
3200 .htotal = 480 + 8 + 4 + 39,
3201 .vdisplay = 272,
3202 .vsync_start = 272 + 4,
3203 .vsync_end = 272 + 4 + 10,
3204 .vtotal = 272 + 4 + 10 + 2,
d2a6f0f5
JW		 3205};
3206
3207static const struct panel_desc qd43003c0_40 = {
3208 .modes = &qd43003c0_40_mode,
3209 .num_modes = 1,
3210 .bpc = 8,
3211 .size = {
3212 .width = 95,
3213 .height = 53,
3214 },
3215 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3216};
3217
23167fa9
JT		 3218static const struct display_timing rocktech_rk070er9427_timing = {
3219 .pixelclock = { 26400000, 33300000, 46800000 },
3220 .hactive = { 800, 800, 800 },
3221 .hfront_porch = { 16, 210, 354 },
3222 .hback_porch = { 46, 46, 46 },
3223 .hsync_len = { 1, 1, 1 },
3224 .vactive = { 480, 480, 480 },
3225 .vfront_porch = { 7, 22, 147 },
3226 .vback_porch = { 23, 23, 23 },
3227 .vsync_len = { 1, 1, 1 },
3228 .flags = DISPLAY_FLAGS_DE_HIGH,
3229};
3230
3231static const struct panel_desc rocktech_rk070er9427 = {
3232 .timings = &rocktech_rk070er9427_timing,
3233 .num_timings = 1,
3234 .bpc = 6,
3235 .size = {
3236 .width = 154,
3237 .height = 86,
3238 },
3239 .delay = {
3240 .prepare = 41,
3241 .enable = 50,
3242 .unprepare = 41,
3243 .disable = 50,
3244 },
3245 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3246};
3247
f305047b
JS		 3248static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3249 .clock = 71100,
3250 .hdisplay = 1280,
3251 .hsync_start = 1280 + 48,
3252 .hsync_end = 1280 + 48 + 32,
3253 .htotal = 1280 + 48 + 32 + 80,
3254 .vdisplay = 800,
3255 .vsync_start = 800 + 2,
3256 .vsync_end = 800 + 2 + 5,
3257 .vtotal = 800 + 2 + 5 + 16,
f305047b
JS		 3258};
3259
3260static const struct panel_desc rocktech_rk101ii01d_ct = {
3261 .modes = &rocktech_rk101ii01d_ct_mode,
3262 .num_modes = 1,
3263 .size = {
3264 .width = 217,
3265 .height = 136,
3266 },
3267 .delay = {
3268 .prepare = 50,
3269 .disable = 50,
3270 },
3271 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3272 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3273 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3274};
3275
0330eaf3
YY		 3276static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3277 .clock = 271560,
3278 .hdisplay = 2560,
3279 .hsync_start = 2560 + 48,
3280 .hsync_end = 2560 + 48 + 32,
3281 .htotal = 2560 + 48 + 32 + 80,
3282 .vdisplay = 1600,
3283 .vsync_start = 1600 + 2,
3284 .vsync_end = 1600 + 2 + 5,
3285 .vtotal = 1600 + 2 + 5 + 57,
0330eaf3
YY		 3286};
3287
3288static const struct panel_desc samsung_lsn122dl01_c01 = {
3289 .modes = &samsung_lsn122dl01_c01_mode,
3290 .num_modes = 1,
3291 .size = {
3292 .width = 263,
3293 .height = 164,
3294 },
3295};
3296
6d54e3d2
MD		 3297static const struct drm_display_mode samsung_ltn101nt05_mode = {
3298 .clock = 54030,
3299 .hdisplay = 1024,
3300 .hsync_start = 1024 + 24,
3301 .hsync_end = 1024 + 24 + 136,
3302 .htotal = 1024 + 24 + 136 + 160,
3303 .vdisplay = 600,
3304 .vsync_start = 600 + 3,
3305 .vsync_end = 600 + 3 + 6,
3306 .vtotal = 600 + 3 + 6 + 61,
6d54e3d2
MD		 3307};
3308
3309static const struct panel_desc samsung_ltn101nt05 = {
3310 .modes = &samsung_ltn101nt05_mode,
3311 .num_modes = 1,
0208d511 3312 .bpc = 6,
6d54e3d2 3313 .size = {
81598846
TR		 3314 .width = 223,
3315 .height = 125,
6d54e3d2 3316 },
85560829 3317 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 3318 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 3319 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6d54e3d2
MD		 3320};
3321
0c934306
SM		 3322static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3323 .clock = 76300,
3324 .hdisplay = 1366,
3325 .hsync_start = 1366 + 64,
3326 .hsync_end = 1366 + 64 + 48,
3327 .htotal = 1366 + 64 + 48 + 128,
3328 .vdisplay = 768,
3329 .vsync_start = 768 + 2,
3330 .vsync_end = 768 + 2 + 5,
3331 .vtotal = 768 + 2 + 5 + 17,
0c934306
SM		 3332};
3333
3334static const struct panel_desc samsung_ltn140at29_301 = {
3335 .modes = &samsung_ltn140at29_301_mode,
3336 .num_modes = 1,
3337 .bpc = 6,
3338 .size = {
3339 .width = 320,
3340 .height = 187,
3341 },
3342};
3343
44c58c52
MR		 3344static const struct display_timing satoz_sat050at40h12r2_timing = {
3345 .pixelclock = {33300000, 33300000, 50000000},
3346 .hactive = {800, 800, 800},
3347 .hfront_porch = {16, 210, 354},
3348 .hback_porch = {46, 46, 46},
3349 .hsync_len = {1, 1, 40},
3350 .vactive = {480, 480, 480},
3351 .vfront_porch = {7, 22, 147},
3352 .vback_porch = {23, 23, 23},
3353 .vsync_len = {1, 1, 20},
3354};
3355
3356static const struct panel_desc satoz_sat050at40h12r2 = {
3357 .timings = &satoz_sat050at40h12r2_timing,
3358 .num_timings = 1,
3359 .bpc = 8,
3360 .size = {
3361 .width = 108,
3362 .height = 65,
3363 },
34ca6b53 3364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
44c58c52
MR		 3365 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3366};
3367
cd5e1cbe
JH		 3368static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3369 .clock = 168480,
3370 .hdisplay = 1920,
3371 .hsync_start = 1920 + 48,
3372 .hsync_end = 1920 + 48 + 32,
3373 .htotal = 1920 + 48 + 32 + 80,
3374 .vdisplay = 1280,
3375 .vsync_start = 1280 + 3,
3376 .vsync_end = 1280 + 3 + 10,
3377 .vtotal = 1280 + 3 + 10 + 57,
cd5e1cbe
JH		 3378 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3379};
3380
3381static const struct panel_desc sharp_ld_d5116z01b = {
3382 .modes = &sharp_ld_d5116z01b_mode,
3383 .num_modes = 1,
3384 .bpc = 8,
3385 .size = {
3386 .width = 260,
3387 .height = 120,
3388 },
3389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3390 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3391};
3392
dda0e4bd
NS		 3393static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3394 .clock = 33260,
3395 .hdisplay = 800,
3396 .hsync_start = 800 + 64,
3397 .hsync_end = 800 + 64 + 128,
3398 .htotal = 800 + 64 + 128 + 64,
3399 .vdisplay = 480,
3400 .vsync_start = 480 + 8,
3401 .vsync_end = 480 + 8 + 2,
3402 .vtotal = 480 + 8 + 2 + 35,
dda0e4bd
NS		 3403 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3404};
3405
3406static const struct panel_desc sharp_lq070y3dg3b = {
3407 .modes = &sharp_lq070y3dg3b_mode,
3408 .num_modes = 1,
3409 .bpc = 8,
3410 .size = {
3411 .width = 152, /* 152.4mm */
3412 .height = 91, /* 91.4mm */
3413 },
3414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
dda0e4bd
NS		 3416 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3417};
3418
03e3ec9a
VZ		 3419static const struct drm_display_mode sharp_lq035q7db03_mode = {
3420 .clock = 5500,
3421 .hdisplay = 240,
3422 .hsync_start = 240 + 16,
3423 .hsync_end = 240 + 16 + 7,
3424 .htotal = 240 + 16 + 7 + 5,
3425 .vdisplay = 320,
3426 .vsync_start = 320 + 9,
3427 .vsync_end = 320 + 9 + 1,
3428 .vtotal = 320 + 9 + 1 + 7,
03e3ec9a
VZ		 3429};
3430
3431static const struct panel_desc sharp_lq035q7db03 = {
3432 .modes = &sharp_lq035q7db03_mode,
3433 .num_modes = 1,
3434 .bpc = 6,
3435 .size = {
3436 .width = 54,
3437 .height = 72,
3438 },
3439 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3440};
3441
592aa02b
JC		 3442static const struct display_timing sharp_lq101k1ly04_timing = {
3443 .pixelclock = { 60000000, 65000000, 80000000 },
3444 .hactive = { 1280, 1280, 1280 },
3445 .hfront_porch = { 20, 20, 20 },
3446 .hback_porch = { 20, 20, 20 },
3447 .hsync_len = { 10, 10, 10 },
3448 .vactive = { 800, 800, 800 },
3449 .vfront_porch = { 4, 4, 4 },
3450 .vback_porch = { 4, 4, 4 },
3451 .vsync_len = { 4, 4, 4 },
3452 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3453};
3454
3455static const struct panel_desc sharp_lq101k1ly04 = {
3456 .timings = &sharp_lq101k1ly04_timing,
3457 .num_timings = 1,
3458 .bpc = 8,
3459 .size = {
3460 .width = 217,
3461 .height = 136,
3462 },
3463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 3464 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 3465};
3466
9f7bae2d
SP		 3467static const struct display_timing sharp_lq123p1jx31_timing = {
3468 .pixelclock = { 252750000, 252750000, 266604720 },
3469 .hactive = { 2400, 2400, 2400 },
3470 .hfront_porch = { 48, 48, 48 },
3471 .hback_porch = { 80, 80, 84 },
3472 .hsync_len = { 32, 32, 32 },
3473 .vactive = { 1600, 1600, 1600 },
3474 .vfront_porch = { 3, 3, 3 },
3475 .vback_porch = { 33, 33, 120 },
3476 .vsync_len = { 10, 10, 10 },
3477 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 3478};
3479
3480static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 3481 .timings = &sharp_lq123p1jx31_timing,
3482 .num_timings = 1,
5466a631 3483 .bpc = 8,
739c7de9
YY		 3484 .size = {
3485 .width = 259,
3486 .height = 173,
3487 },
a42f6e3f
YY		 3488 .delay = {
3489 .prepare = 110,
3490 .enable = 50,
3491 .unprepare = 550,
3492 },
739c7de9
YY		 3493};
3494
656b7596 3495static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
e6c21e6f
PC		 3496 { /* 50 Hz */
3497 .clock = 3000,
3498 .hdisplay = 240,
3499 .hsync_start = 240 + 58,
3500 .hsync_end = 240 + 58 + 1,
3501 .htotal = 240 + 58 + 1 + 1,
3502 .vdisplay = 160,
3503 .vsync_start = 160 + 24,
3504 .vsync_end = 160 + 24 + 10,
3505 .vtotal = 160 + 24 + 10 + 6,
3506 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3507 },
656b7596 3508 { /* 60 Hz */
c1bd32b5 3509 .clock = 3000,
656b7596 3510 .hdisplay = 240,
c1bd32b5
PC		 3511 .hsync_start = 240 + 8,
3512 .hsync_end = 240 + 8 + 1,
3513 .htotal = 240 + 8 + 1 + 1,
656b7596 3514 .vdisplay = 160,
c1bd32b5
PC		 3515 .vsync_start = 160 + 24,
3516 .vsync_end = 160 + 24 + 10,
3517 .vtotal = 160 + 24 + 10 + 6,
656b7596
PC		 3518 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3519 },
f1bd37f3
PC		 3520};
3521
3522static const struct panel_desc sharp_ls020b1dd01d = {
656b7596
PC		 3523 .modes = sharp_ls020b1dd01d_modes,
3524 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
f1bd37f3
PC		 3525 .bpc = 6,
3526 .size = {
3527 .width = 42,
3528 .height = 28,
3529 },
3530 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3531 .bus_flags = DRM_BUS_FLAG_DE_HIGH
f5436f77 3532 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
f1bd37f3
PC		 3533 | DRM_BUS_FLAG_SHARP_SIGNALS,
3534};
3535
9c6615bc
BB		 3536static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3537 .clock = 33300,
3538 .hdisplay = 800,
3539 .hsync_start = 800 + 1,
3540 .hsync_end = 800 + 1 + 64,
3541 .htotal = 800 + 1 + 64 + 64,
3542 .vdisplay = 480,
3543 .vsync_start = 480 + 1,
3544 .vsync_end = 480 + 1 + 23,
3545 .vtotal = 480 + 1 + 23 + 22,
9c6615bc
BB		 3546};
3547
3548static const struct panel_desc shelly_sca07010_bfn_lnn = {
3549 .modes = &shelly_sca07010_bfn_lnn_mode,
3550 .num_modes = 1,
3551 .size = {
3552 .width = 152,
3553 .height = 91,
3554 },
3555 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3556};
3557
105235e4
PR		 3558static const struct drm_display_mode starry_kr070pe2t_mode = {
3559 .clock = 33000,
3560 .hdisplay = 800,
3561 .hsync_start = 800 + 209,
3562 .hsync_end = 800 + 209 + 1,
3563 .htotal = 800 + 209 + 1 + 45,
3564 .vdisplay = 480,
3565 .vsync_start = 480 + 22,
3566 .vsync_end = 480 + 22 + 1,
3567 .vtotal = 480 + 22 + 1 + 22,
105235e4
PR		 3568};
3569
3570static const struct panel_desc starry_kr070pe2t = {
3571 .modes = &starry_kr070pe2t_mode,
3572 .num_modes = 1,
3573 .bpc = 8,
3574 .size = {
3575 .width = 152,
3576 .height = 86,
3577 },
3578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3579 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
41fad307 3580 .connector_type = DRM_MODE_CONNECTOR_DPI,
105235e4
PR		 3581};
3582
9bb34c4c
DA		 3583static const struct drm_display_mode starry_kr122ea0sra_mode = {
3584 .clock = 147000,
3585 .hdisplay = 1920,
3586 .hsync_start = 1920 + 16,
3587 .hsync_end = 1920 + 16 + 16,
3588 .htotal = 1920 + 16 + 16 + 32,
3589 .vdisplay = 1200,
3590 .vsync_start = 1200 + 15,
3591 .vsync_end = 1200 + 15 + 2,
3592 .vtotal = 1200 + 15 + 2 + 18,
9bb34c4c
DA		 3593 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3594};
3595
3596static const struct panel_desc starry_kr122ea0sra = {
3597 .modes = &starry_kr122ea0sra_mode,
3598 .num_modes = 1,
3599 .size = {
3600 .width = 263,
3601 .height = 164,
3602 },
c46b924b
BN		 3603 .delay = {
3604 .prepare = 10 + 200,
3605 .enable = 50,
3606 .unprepare = 10 + 500,
3607 },
9bb34c4c
DA		 3608};
3609
42161531
JS		 3610static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3611 .clock = 30000,
3612 .hdisplay = 800,
3613 .hsync_start = 800 + 39,
3614 .hsync_end = 800 + 39 + 47,
3615 .htotal = 800 + 39 + 47 + 39,
3616 .vdisplay = 480,
3617 .vsync_start = 480 + 13,
3618 .vsync_end = 480 + 13 + 2,
3619 .vtotal = 480 + 13 + 2 + 29,
42161531
JS		 3620};
3621
3622static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3623 .modes = &tfc_s9700rtwv43tr_01b_mode,
3624 .num_modes = 1,
3625 .bpc = 8,
3626 .size = {
3627 .width = 155,
3628 .height = 90,
3629 },
3630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3631 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
42161531
JS		 3632};
3633
adb973ef
GB		 3634static const struct display_timing tianma_tm070jdhg30_timing = {
3635 .pixelclock = { 62600000, 68200000, 78100000 },
3636 .hactive = { 1280, 1280, 1280 },
3637 .hfront_porch = { 15, 64, 159 },
3638 .hback_porch = { 5, 5, 5 },
3639 .hsync_len = { 1, 1, 256 },
3640 .vactive = { 800, 800, 800 },
3641 .vfront_porch = { 3, 40, 99 },
3642 .vback_porch = { 2, 2, 2 },
3643 .vsync_len = { 1, 1, 128 },
3644 .flags = DISPLAY_FLAGS_DE_HIGH,
3645};
3646
3647static const struct panel_desc tianma_tm070jdhg30 = {
3648 .timings = &tianma_tm070jdhg30_timing,
3649 .num_timings = 1,
3650 .bpc = 8,
3651 .size = {
3652 .width = 151,
3653 .height = 95,
3654 },
3655 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3656 .connector_type = DRM_MODE_CONNECTOR_LVDS,
adb973ef
GB		 3657};
3658
b3bfcdf8
MM		 3659static const struct panel_desc tianma_tm070jvhg33 = {
3660 .timings = &tianma_tm070jdhg30_timing,
3661 .num_timings = 1,
3662 .bpc = 8,
3663 .size = {
3664 .width = 150,
3665 .height = 94,
3666 },
3667 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3668 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3669};
3670
870a0b12
LM		 3671static const struct display_timing tianma_tm070rvhg71_timing = {
3672 .pixelclock = { 27700000, 29200000, 39600000 },
3673 .hactive = { 800, 800, 800 },
3674 .hfront_porch = { 12, 40, 212 },
3675 .hback_porch = { 88, 88, 88 },
3676 .hsync_len = { 1, 1, 40 },
3677 .vactive = { 480, 480, 480 },
3678 .vfront_porch = { 1, 13, 88 },
3679 .vback_porch = { 32, 32, 32 },
3680 .vsync_len = { 1, 1, 3 },
3681 .flags = DISPLAY_FLAGS_DE_HIGH,
3682};
3683
3684static const struct panel_desc tianma_tm070rvhg71 = {
3685 .timings = &tianma_tm070rvhg71_timing,
3686 .num_timings = 1,
3687 .bpc = 8,
3688 .size = {
3689 .width = 154,
3690 .height = 86,
3691 },
3692 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3693 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 3694};
3695
d8a0d6a3
LW		 3696static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3697 {
3698 .clock = 10000,
3699 .hdisplay = 320,
3700 .hsync_start = 320 + 50,
3701 .hsync_end = 320 + 50 + 6,
3702 .htotal = 320 + 50 + 6 + 38,
3703 .vdisplay = 240,
3704 .vsync_start = 240 + 3,
3705 .vsync_end = 240 + 3 + 1,
3706 .vtotal = 240 + 3 + 1 + 17,
d8a0d6a3
LW		 3707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3708 },
3709};
3710
3711static const struct panel_desc ti_nspire_cx_lcd_panel = {
3712 .modes = ti_nspire_cx_lcd_mode,
3713 .num_modes = 1,
3714 .bpc = 8,
3715 .size = {
3716 .width = 65,
3717 .height = 49,
3718 },
3719 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3720 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d8a0d6a3
LW		 3721};
3722
3723static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3724 {
3725 .clock = 10000,
3726 .hdisplay = 320,
3727 .hsync_start = 320 + 6,
3728 .hsync_end = 320 + 6 + 6,
3729 .htotal = 320 + 6 + 6 + 6,
3730 .vdisplay = 240,
3731 .vsync_start = 240 + 0,
3732 .vsync_end = 240 + 0 + 1,
3733 .vtotal = 240 + 0 + 1 + 0,
d8a0d6a3
LW		 3734 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3735 },
3736};
3737
3738static const struct panel_desc ti_nspire_classic_lcd_panel = {
3739 .modes = ti_nspire_classic_lcd_mode,
3740 .num_modes = 1,
3741 /* The grayscale panel has 8 bit for the color .. Y (black) */
3742 .bpc = 8,
3743 .size = {
3744 .width = 71,
3745 .height = 53,
3746 },
3747 /* This is the grayscale bus format */
3748 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
f5436f77 3749 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
d8a0d6a3
LW		 3750};
3751
06e733e4
LS		 3752static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3753 .clock = 79500,
3754 .hdisplay = 1280,
3755 .hsync_start = 1280 + 192,
3756 .hsync_end = 1280 + 192 + 128,
3757 .htotal = 1280 + 192 + 128 + 64,
3758 .vdisplay = 768,
3759 .vsync_start = 768 + 20,
3760 .vsync_end = 768 + 20 + 7,
3761 .vtotal = 768 + 20 + 7 + 3,
06e733e4
LS		 3762};
3763
3764static const struct panel_desc toshiba_lt089ac29000 = {
3765 .modes = &toshiba_lt089ac29000_mode,
3766 .num_modes = 1,
3767 .size = {
3768 .width = 194,
3769 .height = 116,
3770 },
9781bd1d 3771 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
c4715837 3772 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 3773 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 3774};
3775
227e4f40
BD		 3776static const struct drm_display_mode tpk_f07a_0102_mode = {
3777 .clock = 33260,
3778 .hdisplay = 800,
3779 .hsync_start = 800 + 40,
3780 .hsync_end = 800 + 40 + 128,
3781 .htotal = 800 + 40 + 128 + 88,
3782 .vdisplay = 480,
3783 .vsync_start = 480 + 10,
3784 .vsync_end = 480 + 10 + 2,
3785 .vtotal = 480 + 10 + 2 + 33,
227e4f40
BD		 3786};
3787
3788static const struct panel_desc tpk_f07a_0102 = {
3789 .modes = &tpk_f07a_0102_mode,
3790 .num_modes = 1,
3791 .size = {
3792 .width = 152,
3793 .height = 91,
3794 },
88bc4178 3795 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 3796};
3797
3798static const struct drm_display_mode tpk_f10a_0102_mode = {
3799 .clock = 45000,
3800 .hdisplay = 1024,
3801 .hsync_start = 1024 + 176,
3802 .hsync_end = 1024 + 176 + 5,
3803 .htotal = 1024 + 176 + 5 + 88,
3804 .vdisplay = 600,
3805 .vsync_start = 600 + 20,
3806 .vsync_end = 600 + 20 + 5,
3807 .vtotal = 600 + 20 + 5 + 25,
227e4f40
BD		 3808};
3809
3810static const struct panel_desc tpk_f10a_0102 = {
3811 .modes = &tpk_f10a_0102_mode,
3812 .num_modes = 1,
3813 .size = {
3814 .width = 223,
3815 .height = 125,
3816 },
3817};
3818
06a9dc65
MS		 3819static const struct display_timing urt_umsh_8596md_timing = {
3820 .pixelclock = { 33260000, 33260000, 33260000 },
3821 .hactive = { 800, 800, 800 },
3822 .hfront_porch = { 41, 41, 41 },
3823 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3824 .hsync_len = { 71, 128, 128 },
3825 .vactive = { 480, 480, 480 },
3826 .vfront_porch = { 10, 10, 10 },
3827 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3828 .vsync_len = { 2, 2, 2 },
3829 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3830 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3831};
3832
3833static const struct panel_desc urt_umsh_8596md_lvds = {
3834 .timings = &urt_umsh_8596md_timing,
3835 .num_timings = 1,
3836 .bpc = 6,
3837 .size = {
3838 .width = 152,
3839 .height = 91,
3840 },
3841 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 3842 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 3843};
3844
3845static const struct panel_desc urt_umsh_8596md_parallel = {
3846 .timings = &urt_umsh_8596md_timing,
3847 .num_timings = 1,
3848 .bpc = 6,
3849 .size = {
3850 .width = 152,
3851 .height = 91,
3852 },
3853 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3854};
3855
04206185
FE		 3856static const struct drm_display_mode vl050_8048nt_c01_mode = {
3857 .clock = 33333,
3858 .hdisplay = 800,
3859 .hsync_start = 800 + 210,
3860 .hsync_end = 800 + 210 + 20,
3861 .htotal = 800 + 210 + 20 + 46,
3862 .vdisplay = 480,
3863 .vsync_start = 480 + 22,
3864 .vsync_end = 480 + 22 + 10,
3865 .vtotal = 480 + 22 + 10 + 23,
04206185
FE		 3866 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3867};
3868
3869static const struct panel_desc vl050_8048nt_c01 = {
3870 .modes = &vl050_8048nt_c01_mode,
3871 .num_modes = 1,
3872 .bpc = 8,
3873 .size = {
3874 .width = 120,
3875 .height = 76,
3876 },
3877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3878 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
04206185
FE		 3879};
3880
e4bac408
RG		 3881static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3882 .clock = 6410,
3883 .hdisplay = 320,
3884 .hsync_start = 320 + 20,
3885 .hsync_end = 320 + 20 + 30,
3886 .htotal = 320 + 20 + 30 + 38,
3887 .vdisplay = 240,
3888 .vsync_start = 240 + 4,
3889 .vsync_end = 240 + 4 + 3,
3890 .vtotal = 240 + 4 + 3 + 15,
e4bac408
RG		 3891 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3892};
3893
3894static const struct panel_desc winstar_wf35ltiacd = {
3895 .modes = &winstar_wf35ltiacd_mode,
3896 .num_modes = 1,
3897 .bpc = 8,
3898 .size = {
3899 .width = 70,
3900 .height = 53,
3901 },
3902 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3903};
3904
7a1f4fa4
JT		 3905static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3906 .clock = 51200,
3907 .hdisplay = 1024,
3908 .hsync_start = 1024 + 100,
3909 .hsync_end = 1024 + 100 + 100,
3910 .htotal = 1024 + 100 + 100 + 120,
3911 .vdisplay = 600,
3912 .vsync_start = 600 + 10,
3913 .vsync_end = 600 + 10 + 10,
3914 .vtotal = 600 + 10 + 10 + 15,
3915 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3916};
3917
3918static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3919 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3920 .num_modes = 1,
3921 .bpc = 6,
3922 .size = {
3923 .width = 154,
3924 .height = 90,
3925 },
3926 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3929};
3930
fcec4163
LW		 3931static const struct drm_display_mode arm_rtsm_mode[] = {
3932 {
3933 .clock = 65000,
3934 .hdisplay = 1024,
3935 .hsync_start = 1024 + 24,
3936 .hsync_end = 1024 + 24 + 136,
3937 .htotal = 1024 + 24 + 136 + 160,
3938 .vdisplay = 768,
3939 .vsync_start = 768 + 3,
3940 .vsync_end = 768 + 3 + 6,
3941 .vtotal = 768 + 3 + 6 + 29,
fcec4163
LW		 3942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3943 },
3944};
3945
3946static const struct panel_desc arm_rtsm = {
3947 .modes = arm_rtsm_mode,
3948 .num_modes = 1,
3949 .bpc = 8,
3950 .size = {
3951 .width = 400,
3952 .height = 300,
3953 },
3954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3955};
3956
280921de
TR		 3957static const struct of_device_id platform_of_match[] = {
3958 {
bca684e6
JT		 3959 .compatible = "ampire,am-1280800n3tzqw-t00h",
3960 .data = &ampire_am_1280800n3tzqw_t00h,
3961 }, {
966fea78
YF		 3962 .compatible = "ampire,am-480272h3tmqw-t01h",
3963 .data = &ampire_am_480272h3tmqw_t01h,
3964 }, {
1c550fa1
PZ		 3965 .compatible = "ampire,am800480r3tmqwa1h",
3966 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 3967 }, {
3968 .compatible = "arm,rtsm-display",
3969 .data = &arm_rtsm,
c479450f
SS		 3970 }, {
3971 .compatible = "armadeus,st0700-adapt",
3972 .data = &armadeus_st0700_adapt,
1c550fa1 3973 }, {
280921de
TR		 3974 .compatible = "auo,b101aw03",
3975 .data = &auo_b101aw03,
a531bc3d
HL		 3976 }, {
3977 .compatible = "auo,b101ean01",
3978 .data = &auo_b101ean01,
dac746e0
RC		 3979 }, {
3980 .compatible = "auo,b101xtn01",
3981 .data = &auo_b101xtn01,
da458286
RC		 3982 }, {
3983 .compatible = "auo,b116xa01",
3984 .data = &auo_b116xak01,
e35e305e
AK		 3985 }, {
3986 .compatible = "auo,b116xw03",
3987 .data = &auo_b116xw03,
3e51d609
AK		 3988 }, {
3989 .compatible = "auo,b133htn01",
3990 .data = &auo_b133htn01,
a333f7ad
SM		 3991 }, {
3992 .compatible = "auo,b133xtn01",
3993 .data = &auo_b133xtn01,
bccfaffb
LM		 3994 }, {
3995 .compatible = "auo,g070vvn01",
3996 .data = &auo_g070vvn01,
4fb86404
AG		 3997 }, {
3998 .compatible = "auo,g101evn010",
3999 .data = &auo_g101evn010,
4451c287
CF		 4000 }, {
4001 .compatible = "auo,g104sn02",
4002 .data = &auo_g104sn02,
03e909ac
SR		 4003 }, {
4004 .compatible = "auo,g121ean01",
4005 .data = &auo_g121ean01,
697035c6
LS		 4006 }, {
4007 .compatible = "auo,g133han01",
4008 .data = &auo_g133han01,
d9ccd1f2
SR		 4009 }, {
4010 .compatible = "auo,g156xtn01",
4011 .data = &auo_g156xtn01,
8c31f603
LS		 4012 }, {
4013 .compatible = "auo,g185han01",
4014 .data = &auo_g185han01,
2f7b832f
SR		 4015 }, {
4016 .compatible = "auo,g190ean01",
4017 .data = &auo_g190ean01,
70c0d5b7
LS		 4018 }, {
4019 .compatible = "auo,p320hvn03",
4020 .data = &auo_p320hvn03,
7ee933a1
HS		 4021 }, {
4022 .compatible = "auo,t215hvn01",
4023 .data = &auo_t215hvn01,
d47df633
PZ		 4024 }, {
4025 .compatible = "avic,tm070ddh03",
4026 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 4027 }, {
4028 .compatible = "bananapi,s070wv20-ct16",
4029 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 4030 }, {
4031 .compatible = "boe,hv070wsa-100",
4032 .data = &boe_hv070wsa
cac1a411
CW		 4033 }, {
4034 .compatible = "boe,nv101wxmn51",
4035 .data = &boe_nv101wxmn51,
b0c664cc
BA		 4036 }, {
4037 .compatible = "boe,nv133fhm-n61",
4038 .data = &boe_nv133fhm_n61,
cfe40d02
DA		 4039 }, {
4040 .compatible = "boe,nv133fhm-n62",
4041 .data = &boe_nv133fhm_n61,
a5119818
TS		 4042 }, {
4043 .compatible = "boe,nv140fhmn49",
4044 .data = &boe_nv140fhmn49,
e58edce6
GB		 4045 }, {
4046 .compatible = "cdtech,s043wq26h-ct7",
4047 .data = &cdtech_s043wq26h_ct7,
0e3b67f6
MK		 4048 }, {
4049 .compatible = "cdtech,s070pws19hp-fc21",
4050 .data = &cdtech_s070pws19hp_fc21,
4051 }, {
4052 .compatible = "cdtech,s070swv29hg-dc44",
4053 .data = &cdtech_s070swv29hg_dc44,
982f944e
GB		 4054 }, {
4055 .compatible = "cdtech,s070wv95-ct16",
4056 .data = &cdtech_s070wv95_ct16,
07c913c4
MV		 4057 }, {
4058 .compatible = "chefree,ch101olhlwh-002",
4059 .data = &chefree_ch101olhlwh_002,
2cb35c80
RL		 4060 }, {
4061 .compatible = "chunghwa,claa070wp03xg",
4062 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 4063 }, {
4064 .compatible = "chunghwa,claa101wa01a",
4065 .data = &chunghwa_claa101wa01a
280921de
TR		 4066 }, {
4067 .compatible = "chunghwa,claa101wb01",
4068 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 4069 }, {
4070 .compatible = "dataimage,scf0700c48ggu18",
4071 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 4072 }, {
4073 .compatible = "dlc,dlc0700yzg-1",
4074 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 4075 }, {
4076 .compatible = "dlc,dlc1010gig",
4077 .data = &dlc_dlc1010gig,
c2d24af6
AP		 4078 }, {
4079 .compatible = "edt,et035012dm6",
4080 .data = &edt_et035012dm6,
82d57a59
MCR		 4081 }, {
4082 .compatible = "edt,etm043080dh6gp",
4083 .data = &edt_etm043080dh6gp,
fd819bff
MV		 4084 }, {
4085 .compatible = "edt,etm0430g0dh6",
4086 .data = &edt_etm0430g0dh6,
26ab0065
SA		 4087 }, {
4088 .compatible = "edt,et057090dhu",
4089 .data = &edt_et057090dhu,
fff5de45
PZ		 4090 }, {
4091 .compatible = "edt,et070080dh6",
4092 .data = &edt_etm0700g0dh6,
4093 }, {
4094 .compatible = "edt,etm0700g0dh6",
4095 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 4096 }, {
4097 .compatible = "edt,etm0700g0bdh6",
4098 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 4099 }, {
4100 .compatible = "edt,etm0700g0edh6",
4101 .data = &edt_etm0700g0bdh6,
9158e3c3
MF		 4102 }, {
4103 .compatible = "evervision,vgg804821",
4104 .data = &evervision_vgg804821,
102932b0
BB		 4105 }, {
4106 .compatible = "foxlink,fl500wvr00-a0t",
4107 .data = &foxlink_fl500wvr00_a0t,
7b6bd843
PC		 4108 }, {
4109 .compatible = "frida,frd350h54004",
4110 .data = &frida_frd350h54004,
3be20710
JT		 4111 }, {
4112 .compatible = "friendlyarm,hd702e",
4113 .data = &friendlyarm_hd702e,
d435a2af
PZ		 4114 }, {
4115 .compatible = "giantplus,gpg482739qs5",
4116 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 4117 }, {
4118 .compatible = "giantplus,gpm940b0",
4119 .data = &giantplus_gpm940b0,
a853205e
PZ		 4120 }, {
4121 .compatible = "hannstar,hsd070pww1",
4122 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 4123 }, {
4124 .compatible = "hannstar,hsd100pxn1",
4125 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 4126 }, {
4127 .compatible = "hit,tx23d38vm0caa",
4128 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 4129 }, {
4130 .compatible = "innolux,at043tn24",
4131 .data = &innolux_at043tn24,
4fc24ab3
RB		 4132 }, {
4133 .compatible = "innolux,at070tn92",
4134 .data = &innolux_at070tn92,
1e29b840 4135 }, {
a5d2ade6
CF		 4136 .compatible = "innolux,g070y2-l01",
4137 .data = &innolux_g070y2_l01,
4138 }, {
4139 .compatible = "innolux,g101ice-l01",
1e29b840 4140 .data = &innolux_g101ice_l01
d731f661 4141 }, {
a5d2ade6 4142 .compatible = "innolux,g121i1-l01",
d731f661 4143 .data = &innolux_g121i1_l01
f8fa17ba
AB		 4144 }, {
4145 .compatible = "innolux,g121x1-l03",
4146 .data = &innolux_g121x1_l03,
0a2288c0
TR		 4147 }, {
4148 .compatible = "innolux,n116bge",
4149 .data = &innolux_n116bge,
a14c6b0e
LH		 4150 }, {
4151 .compatible = "innolux,n125hce-gn1",
4152 .data = &innolux_n125hce_gn1,
ea44739d
AB		 4153 }, {
4154 .compatible = "innolux,n156bge-l21",
4155 .data = &innolux_n156bge_l21,
da50bd42 4156 }, {
8f054b6f
DA		 4157 .compatible = "innolux,p120zdg-bf1",
4158 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 4159 }, {
4160 .compatible = "innolux,zj070na-01p",
4161 .data = &innolux_zj070na_01p,
e1ca5184
BA		 4162 }, {
4163 .compatible = "ivo,m133nwf4-r0",
4164 .data = &ivo_m133nwf4_r0,
fc26a375
DA		 4165 }, {
4166 .compatible = "kingdisplay,kd116n21-30nv-a010",
4167 .data = &kingdisplay_kd116n21_30nv_a010,
14bf60c4
LM		 4168 }, {
4169 .compatible = "koe,tx14d24vm1bpa",
4170 .data = &koe_tx14d24vm1bpa,
8a070524
LY		 4171 }, {
4172 .compatible = "koe,tx26d202vm0bwa",
4173 .data = &koe_tx26d202vm0bwa,
8cfe8341
JT		 4174 }, {
4175 .compatible = "koe,tx31d200vm0baa",
4176 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 4177 }, {
4178 .compatible = "kyo,tcg121xglp",
4179 .data = &kyo_tcg121xglp,
27abdd83
PK		 4180 }, {
4181 .compatible = "lemaker,bl035-rgb-002",
4182 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 4183 }, {
4184 .compatible = "lg,lb070wv8",
4185 .data = &lg_lb070wv8,
c5ece402
YY		 4186 }, {
4187 .compatible = "lg,lp079qx1-sp0v",
4188 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 4189 }, {
4190 .compatible = "lg,lp097qx1-spa1",
4191 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 4192 }, {
4193 .compatible = "lg,lp120up1",
4194 .data = &lg_lp120up1,
ec7c5653
TR		 4195 }, {
4196 .compatible = "lg,lp129qe",
4197 .data = &lg_lp129qe,
0d35408a
AF		 4198 }, {
4199 .compatible = "logicpd,type28",
4200 .data = &logicpd_type_28,
5728fe7f
MZ		 4201 }, {
4202 .compatible = "logictechno,lt161010-2nhc",
4203 .data = &logictechno_lt161010_2nh,
4204 }, {
4205 .compatible = "logictechno,lt161010-2nhr",
4206 .data = &logictechno_lt161010_2nh,
4207 }, {
4208 .compatible = "logictechno,lt170410-2whc",
4209 .data = &logictechno_lt170410_2whc,
65c766ca
LM		 4210 }, {
4211 .compatible = "mitsubishi,aa070mc01-ca1",
4212 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 4213 }, {
4214 .compatible = "nec,nl12880bc20-05",
4215 .data = &nec_nl12880bc20_05,
c6e87f91 4216 }, {
4217 .compatible = "nec,nl4827hc19-05b",
4218 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 4219 }, {
4220 .compatible = "netron-dy,e231732",
4221 .data = &netron_dy_e231732,
258145ea
VK		 4222 }, {
4223 .compatible = "neweast,wjfh116008a",
4224 .data = &neweast_wjfh116008a,
3b39ad7a
TV		 4225 }, {
4226 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4227 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 4228 }, {
4229 .compatible = "nlt,nl192108ac18-02d",
4230 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 4231 }, {
4232 .compatible = "nvd,9128",
4233 .data = &nvd_9128,
a99fb626
GB		 4234 }, {
4235 .compatible = "okaya,rs800480t-7x0gp",
4236 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 4237 }, {
4238 .compatible = "olimex,lcd-olinuxino-43-ts",
4239 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 4240 }, {
4241 .compatible = "ontat,yx700wv03",
4242 .data = &ontat_yx700wv03,
9c31dcb6
NS		 4243 }, {
4244 .compatible = "ortustech,com37h3m05dtc",
4245 .data = &ortustech_com37h3m,
4246 }, {
4247 .compatible = "ortustech,com37h3m99dtc",
4248 .data = &ortustech_com37h3m,
725c9d40
PZ		 4249 }, {
4250 .compatible = "ortustech,com43h4m85ulc",
4251 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 4252 }, {
4253 .compatible = "osddisplays,osd070t1718-19ts",
4254 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 4255 }, {
4256 .compatible = "pda,91-00156-a0",
4257 .data = &pda_91_00156_a0,
d69de69f
MV		 4258 }, {
4259 .compatible = "powertip,ph800480t013-idf02",
4260 .data = &powertip_ph800480t013_idf02,
d2a6f0f5
JW		 4261 }, {
4262 .compatible = "qiaodian,qd43003c0-40",
4263 .data = &qd43003c0_40,
23167fa9
JT		 4264 }, {
4265 .compatible = "rocktech,rk070er9427",
4266 .data = &rocktech_rk070er9427,
f305047b
JS		 4267 }, {
4268 .compatible = "rocktech,rk101ii01d-ct",
4269 .data = &rocktech_rk101ii01d_ct,
0330eaf3
YY		 4270 }, {
4271 .compatible = "samsung,lsn122dl01-c01",
4272 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 4273 }, {
4274 .compatible = "samsung,ltn101nt05",
4275 .data = &samsung_ltn101nt05,
0c934306
SM		 4276 }, {
4277 .compatible = "samsung,ltn140at29-301",
4278 .data = &samsung_ltn140at29_301,
44c58c52
MR		 4279 }, {
4280 .compatible = "satoz,sat050at40h12r2",
4281 .data = &satoz_sat050at40h12r2,
cd5e1cbe
JH		 4282 }, {
4283 .compatible = "sharp,ld-d5116z01b",
4284 .data = &sharp_ld_d5116z01b,
03e3ec9a
VZ		 4285 }, {
4286 .compatible = "sharp,lq035q7db03",
4287 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 4288 }, {
4289 .compatible = "sharp,lq070y3dg3b",
4290 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 4291 }, {
4292 .compatible = "sharp,lq101k1ly04",
4293 .data = &sharp_lq101k1ly04,
739c7de9
YY		 4294 }, {
4295 .compatible = "sharp,lq123p1jx31",
4296 .data = &sharp_lq123p1jx31,
f1bd37f3
PC		 4297 }, {
4298 .compatible = "sharp,ls020b1dd01d",
4299 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 4300 }, {
4301 .compatible = "shelly,sca07010-bfn-lnn",
4302 .data = &shelly_sca07010_bfn_lnn,
105235e4
PR		 4303 }, {
4304 .compatible = "starry,kr070pe2t",
4305 .data = &starry_kr070pe2t,
9bb34c4c
DA		 4306 }, {
4307 .compatible = "starry,kr122ea0sra",
4308 .data = &starry_kr122ea0sra,
42161531
JS		 4309 }, {
4310 .compatible = "tfc,s9700rtwv43tr-01b",
4311 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 4312 }, {
4313 .compatible = "tianma,tm070jdhg30",
4314 .data = &tianma_tm070jdhg30,
b3bfcdf8
MM		 4315 }, {
4316 .compatible = "tianma,tm070jvhg33",
4317 .data = &tianma_tm070jvhg33,
870a0b12
LM		 4318 }, {
4319 .compatible = "tianma,tm070rvhg71",
4320 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 4321 }, {
4322 .compatible = "ti,nspire-cx-lcd-panel",
4323 .data = &ti_nspire_cx_lcd_panel,
4324 }, {
4325 .compatible = "ti,nspire-classic-lcd-panel",
4326 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 4327 }, {
4328 .compatible = "toshiba,lt089ac29000",
4329 .data = &toshiba_lt089ac29000,
227e4f40
BD		 4330 }, {
4331 .compatible = "tpk,f07a-0102",
4332 .data = &tpk_f07a_0102,
4333 }, {
4334 .compatible = "tpk,f10a-0102",
4335 .data = &tpk_f10a_0102,
06a9dc65
MS		 4336 }, {
4337 .compatible = "urt,umsh-8596md-t",
4338 .data = &urt_umsh_8596md_parallel,
4339 }, {
4340 .compatible = "urt,umsh-8596md-1t",
4341 .data = &urt_umsh_8596md_parallel,
4342 }, {
4343 .compatible = "urt,umsh-8596md-7t",
4344 .data = &urt_umsh_8596md_parallel,
4345 }, {
4346 .compatible = "urt,umsh-8596md-11t",
4347 .data = &urt_umsh_8596md_lvds,
4348 }, {
4349 .compatible = "urt,umsh-8596md-19t",
4350 .data = &urt_umsh_8596md_lvds,
4351 }, {
4352 .compatible = "urt,umsh-8596md-20t",
4353 .data = &urt_umsh_8596md_parallel,
04206185
FE		 4354 }, {
4355 .compatible = "vxt,vl050-8048nt-c01",
4356 .data = &vl050_8048nt_c01,
e4bac408
RG		 4357 }, {
4358 .compatible = "winstar,wf35ltiacd",
4359 .data = &winstar_wf35ltiacd,
7a1f4fa4
JT		 4360 }, {
4361 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4362 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4a1d0dbc
SR		 4363 }, {
4364 /* Must be the last entry */
4365 .compatible = "panel-dpi",
4366 .data = &panel_dpi,
280921de
TR		 4367 }, {
4368 /* sentinel */
4369 }
4370};
4371MODULE_DEVICE_TABLE(of, platform_of_match);
4372
4373static int panel_simple_platform_probe(struct platform_device *pdev)
4374{
4375 const struct of_device_id *id;
4376
4377 id = of_match_node(platform_of_match, pdev->dev.of_node);
4378 if (!id)
4379 return -ENODEV;
4380
4381 return panel_simple_probe(&pdev->dev, id->data);
4382}
4383
4384static int panel_simple_platform_remove(struct platform_device *pdev)
4385{
4386 return panel_simple_remove(&pdev->dev);
4387}
4388
d02fd93e
TR		 4389static void panel_simple_platform_shutdown(struct platform_device *pdev)
4390{
4391 panel_simple_shutdown(&pdev->dev);
4392}
4393
280921de
TR		 4394static struct platform_driver panel_simple_platform_driver = {
4395 .driver = {
4396 .name = "panel-simple",
280921de
TR		 4397 .of_match_table = platform_of_match,
4398 },
4399 .probe = panel_simple_platform_probe,
4400 .remove = panel_simple_platform_remove,
d02fd93e 4401 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 4402};
4403
210fcd9d
TR		 4404struct panel_desc_dsi {
4405 struct panel_desc desc;
4406
462658b8 4407 unsigned long flags;
210fcd9d
TR		 4408 enum mipi_dsi_pixel_format format;
4409 unsigned int lanes;
4410};
4411
d718d79e
TR		 4412static const struct drm_display_mode auo_b080uan01_mode = {
4413 .clock = 154500,
4414 .hdisplay = 1200,
4415 .hsync_start = 1200 + 62,
4416 .hsync_end = 1200 + 62 + 4,
4417 .htotal = 1200 + 62 + 4 + 62,
4418 .vdisplay = 1920,
4419 .vsync_start = 1920 + 9,
4420 .vsync_end = 1920 + 9 + 2,
4421 .vtotal = 1920 + 9 + 2 + 8,
d718d79e
TR		 4422};
4423
4424static const struct panel_desc_dsi auo_b080uan01 = {
4425 .desc = {
4426 .modes = &auo_b080uan01_mode,
4427 .num_modes = 1,
4428 .bpc = 8,
4429 .size = {
4430 .width = 108,
4431 .height = 272,
4432 },
cb62cdec 4433 .connector_type = DRM_MODE_CONNECTOR_DSI,
d718d79e
TR		 4434 },
4435 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4436 .format = MIPI_DSI_FMT_RGB888,
4437 .lanes = 4,
4438};
4439
c8521969
CZ		 4440static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4441 .clock = 160000,
4442 .hdisplay = 1200,
4443 .hsync_start = 1200 + 120,
4444 .hsync_end = 1200 + 120 + 20,
4445 .htotal = 1200 + 120 + 20 + 21,
4446 .vdisplay = 1920,
4447 .vsync_start = 1920 + 21,
4448 .vsync_end = 1920 + 21 + 3,
4449 .vtotal = 1920 + 21 + 3 + 18,
c8521969
CZ		 4450 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4451};
4452
4453static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4454 .desc = {
4455 .modes = &boe_tv080wum_nl0_mode,
4456 .num_modes = 1,
4457 .size = {
4458 .width = 107,
4459 .height = 172,
4460 },
cb62cdec 4461 .connector_type = DRM_MODE_CONNECTOR_DSI,
c8521969
CZ		 4462 },
4463 .flags = MIPI_DSI_MODE_VIDEO |
4464 MIPI_DSI_MODE_VIDEO_BURST |
4465 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4466 .format = MIPI_DSI_FMT_RGB888,
4467 .lanes = 4,
4468};
4469
712ac1ba
AC		 4470static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4471 .clock = 71000,
4472 .hdisplay = 800,
4473 .hsync_start = 800 + 32,
4474 .hsync_end = 800 + 32 + 1,
4475 .htotal = 800 + 32 + 1 + 57,
4476 .vdisplay = 1280,
4477 .vsync_start = 1280 + 28,
4478 .vsync_end = 1280 + 28 + 1,
4479 .vtotal = 1280 + 28 + 1 + 14,
712ac1ba
AC		 4480};
4481
4482static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4483 .desc = {
4484 .modes = &lg_ld070wx3_sl01_mode,
4485 .num_modes = 1,
d7a839cd 4486 .bpc = 8,
712ac1ba
AC		 4487 .size = {
4488 .width = 94,
4489 .height = 151,
4490 },
cb62cdec 4491 .connector_type = DRM_MODE_CONNECTOR_DSI,
712ac1ba 4492 },
5e4cc278 4493 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 4494 .format = MIPI_DSI_FMT_RGB888,
4495 .lanes = 4,
4496};
4497
499ce85a
AC		 4498static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4499 .clock = 67000,
4500 .hdisplay = 720,
4501 .hsync_start = 720 + 12,
4502 .hsync_end = 720 + 12 + 4,
4503 .htotal = 720 + 12 + 4 + 112,
4504 .vdisplay = 1280,
4505 .vsync_start = 1280 + 8,
4506 .vsync_end = 1280 + 8 + 4,
4507 .vtotal = 1280 + 8 + 4 + 12,
499ce85a
AC		 4508};
4509
4510static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4511 .desc = {
4512 .modes = &lg_lh500wx1_sd03_mode,
4513 .num_modes = 1,
d7a839cd 4514 .bpc = 8,
499ce85a
AC		 4515 .size = {
4516 .width = 62,
4517 .height = 110,
4518 },
cb62cdec 4519 .connector_type = DRM_MODE_CONNECTOR_DSI,
499ce85a
AC		 4520 },
4521 .flags = MIPI_DSI_MODE_VIDEO,
4522 .format = MIPI_DSI_FMT_RGB888,
4523 .lanes = 4,
4524};
4525
280921de
TR		 4526static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4527 .clock = 157200,
4528 .hdisplay = 1920,
4529 .hsync_start = 1920 + 154,
4530 .hsync_end = 1920 + 154 + 16,
4531 .htotal = 1920 + 154 + 16 + 32,
4532 .vdisplay = 1200,
4533 .vsync_start = 1200 + 17,
4534 .vsync_end = 1200 + 17 + 2,
4535 .vtotal = 1200 + 17 + 2 + 16,
280921de
TR		 4536};
4537
210fcd9d
TR		 4538static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4539 .desc = {
4540 .modes = &panasonic_vvx10f004b00_mode,
4541 .num_modes = 1,
d7a839cd 4542 .bpc = 8,
210fcd9d
TR		 4543 .size = {
4544 .width = 217,
4545 .height = 136,
4546 },
cb62cdec 4547 .connector_type = DRM_MODE_CONNECTOR_DSI,
280921de 4548 },
5e4cc278
AC		 4549 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4550 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 4551 .format = MIPI_DSI_FMT_RGB888,
4552 .lanes = 4,
4553};
4554
debcd8f9
JM		 4555static const struct drm_display_mode lg_acx467akm_7_mode = {
4556 .clock = 150000,
4557 .hdisplay = 1080,
4558 .hsync_start = 1080 + 2,
4559 .hsync_end = 1080 + 2 + 2,
4560 .htotal = 1080 + 2 + 2 + 2,
4561 .vdisplay = 1920,
4562 .vsync_start = 1920 + 2,
4563 .vsync_end = 1920 + 2 + 2,
4564 .vtotal = 1920 + 2 + 2 + 2,
debcd8f9
JM		 4565};
4566
4567static const struct panel_desc_dsi lg_acx467akm_7 = {
4568 .desc = {
4569 .modes = &lg_acx467akm_7_mode,
4570 .num_modes = 1,
4571 .bpc = 8,
4572 .size = {
4573 .width = 62,
4574 .height = 110,
4575 },
cb62cdec 4576 .connector_type = DRM_MODE_CONNECTOR_DSI,
debcd8f9
JM		 4577 },
4578 .flags = 0,
4579 .format = MIPI_DSI_FMT_RGB888,
4580 .lanes = 4,
4581};
4582
62967232
PU		 4583static const struct drm_display_mode osd101t2045_53ts_mode = {
4584 .clock = 154500,
4585 .hdisplay = 1920,
4586 .hsync_start = 1920 + 112,
4587 .hsync_end = 1920 + 112 + 16,
4588 .htotal = 1920 + 112 + 16 + 32,
4589 .vdisplay = 1200,
4590 .vsync_start = 1200 + 16,
4591 .vsync_end = 1200 + 16 + 2,
4592 .vtotal = 1200 + 16 + 2 + 16,
62967232
PU		 4593 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4594};
4595
4596static const struct panel_desc_dsi osd101t2045_53ts = {
4597 .desc = {
4598 .modes = &osd101t2045_53ts_mode,
4599 .num_modes = 1,
4600 .bpc = 8,
4601 .size = {
4602 .width = 217,
4603 .height = 136,
4604 },
cb62cdec 4605 .connector_type = DRM_MODE_CONNECTOR_DSI,
62967232
PU		 4606 },
4607 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4608 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4609 MIPI_DSI_MODE_EOT_PACKET,
4610 .format = MIPI_DSI_FMT_RGB888,
4611 .lanes = 4,
4612};
4613
210fcd9d
TR		 4614static const struct of_device_id dsi_of_match[] = {
4615 {
d718d79e
TR		 4616 .compatible = "auo,b080uan01",
4617 .data = &auo_b080uan01
c8521969
CZ		 4618 }, {
4619 .compatible = "boe,tv080wum-nl0",
4620 .data = &boe_tv080wum_nl0
d718d79e 4621 }, {
712ac1ba
AC		 4622 .compatible = "lg,ld070wx3-sl01",
4623 .data = &lg_ld070wx3_sl01
4624 }, {
499ce85a
AC		 4625 .compatible = "lg,lh500wx1-sd03",
4626 .data = &lg_lh500wx1_sd03
4627 }, {
210fcd9d
TR		 4628 .compatible = "panasonic,vvx10f004b00",
4629 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 4630 }, {
4631 .compatible = "lg,acx467akm-7",
4632 .data = &lg_acx467akm_7
62967232
PU		 4633 }, {
4634 .compatible = "osddisplays,osd101t2045-53ts",
4635 .data = &osd101t2045_53ts
210fcd9d
TR		 4636 }, {
4637 /* sentinel */
4638 }
4639};
4640MODULE_DEVICE_TABLE(of, dsi_of_match);
4641
4642static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4643{
4644 const struct panel_desc_dsi *desc;
4645 const struct of_device_id *id;
4646 int err;
4647
4648 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4649 if (!id)
4650 return -ENODEV;
4651
4652 desc = id->data;
4653
4654 err = panel_simple_probe(&dsi->dev, &desc->desc);
4655 if (err < 0)
4656 return err;
4657
462658b8 4658 dsi->mode_flags = desc->flags;
210fcd9d
TR		 4659 dsi->format = desc->format;
4660 dsi->lanes = desc->lanes;
4661
7ad9db66
PU		 4662 err = mipi_dsi_attach(dsi);
4663 if (err) {
4664 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4665
4666 drm_panel_remove(&panel->base);
4667 }
4668
4669 return err;
210fcd9d
TR		 4670}
4671
4672static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4673{
4674 int err;
4675
4676 err = mipi_dsi_detach(dsi);
4677 if (err < 0)
4678 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4679
4680 return panel_simple_remove(&dsi->dev);
4681}
4682
d02fd93e
TR		 4683static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4684{
4685 panel_simple_shutdown(&dsi->dev);
4686}
4687
210fcd9d
TR		 4688static struct mipi_dsi_driver panel_simple_dsi_driver = {
4689 .driver = {
4690 .name = "panel-simple-dsi",
210fcd9d
TR		 4691 .of_match_table = dsi_of_match,
4692 },
4693 .probe = panel_simple_dsi_probe,
4694 .remove = panel_simple_dsi_remove,
d02fd93e 4695 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 4696};
4697
4698static int __init panel_simple_init(void)
4699{
210fcd9d
TR		 4700 int err;
4701
4702 err = platform_driver_register(&panel_simple_platform_driver);
4703 if (err < 0)
4704 return err;
4705
4706 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4707 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
f2e66f21
QM		 4708 if (err < 0) {
4709 platform_driver_unregister(&panel_simple_platform_driver);
210fcd9d 4710 return err;
f2e66f21 4711 }
210fcd9d
TR		 4712 }
4713
4714 return 0;
280921de
TR		 4715}
4716module_init(panel_simple_init);
4717
4718static void __exit panel_simple_exit(void)
4719{
210fcd9d
TR		 4720 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4721 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4722
280921de
TR		 4723 platform_driver_unregister(&panel_simple_platform_driver);
4724}
4725module_exit(panel_simple_exit);
4726
4727MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4728MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4729MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)