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dt-bindings: display: panel: Add AUO B116XAK01 panel bindings
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
cb23eae3 31#include <video/display_timing.h>
b8a2948f 32#include <video/of_display_timing.h>
cb23eae3
SR		 33#include <video/videomode.h>
34
280921de 35#include <drm/drm_crtc.h>
cb23eae3 36#include <drm/drm_device.h>
210fcd9d 37#include <drm/drm_mipi_dsi.h>
280921de
TR		 38#include <drm/drm_panel.h>
39
e362cc6a
DA		 40/**
41 * @modes: Pointer to array of fixed modes appropriate for this panel. If
42 * only one mode then this can just be the address of this the mode.
43 * NOTE: cannot be used with "timings" and also if this is specified
44 * then you cannot override the mode in the device tree.
45 * @num_modes: Number of elements in modes array.
46 * @timings: Pointer to array of display timings. NOTE: cannot be used with
47 * "modes" and also these will be used to validate a device tree
48 * override if one is present.
49 * @num_timings: Number of elements in timings array.
50 * @bpc: Bits per color.
51 * @size: Structure containing the physical size of this panel.
52 * @delay: Structure containing various delay values for this panel.
53 * @bus_format: See MEDIA_BUS_FMT_... defines.
54 * @bus_flags: See DRM_BUS_FLAG_... defines.
55 */
280921de
TR		 56struct panel_desc {
57 const struct drm_display_mode *modes;
58 unsigned int num_modes;
a5d3e625
PZ		 59 const struct display_timing *timings;
60 unsigned int num_timings;
280921de 61
0208d511
SM		 62 unsigned int bpc;
63
85533e3b
UÖ		 64 /**
65 * @width: width (in millimeters) of the panel's active display area
66 * @height: height (in millimeters) of the panel's active display area
67 */
280921de
TR		 68 struct {
69 unsigned int width;
70 unsigned int height;
71 } size;
f673c37e
AK		 72
73 /**
74 * @prepare: the time (in milliseconds) that it takes for the panel to
75 * become ready and start receiving video data
2ed3e951
DA		 76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
77 * Plug Detect isn't used.
f673c37e
AK		 78 * @enable: the time (in milliseconds) that it takes for the panel to
79 * display the first valid frame after starting to receive
80 * video data
81 * @disable: the time (in milliseconds) that it takes for the panel to
82 * turn the display off (no content is visible)
83 * @unprepare: the time (in milliseconds) that it takes for the panel
84 * to power itself down completely
85 */
86 struct {
87 unsigned int prepare;
2ed3e951 88 unsigned int hpd_absent_delay;
f673c37e
AK		 89 unsigned int enable;
90 unsigned int disable;
91 unsigned int unprepare;
92 } delay;
795f7ab3
BB		 93
94 u32 bus_format;
f0aa0838 95 u32 bus_flags;
9a2654c0 96 int connector_type;
280921de
TR		 97};
98
280921de
TR		 99struct panel_simple {
100 struct drm_panel base;
613a633e 101 bool prepared;
280921de 102 bool enabled;
2ed3e951 103 bool no_hpd;
280921de
TR		 104
105 const struct panel_desc *desc;
106
280921de
TR		 107 struct regulator *supply;
108 struct i2c_adapter *ddc;
109
cfdf0549 110 struct gpio_desc *enable_gpio;
b8a2948f
SP		 111
112 struct drm_display_mode override_mode;
280921de
TR		 113};
114
115static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
116{
117 return container_of(panel, struct panel_simple, base);
118}
119
0ce8ddd8
SR		 120static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
121 struct drm_connector *connector)
280921de 122{
280921de
TR		 123 struct drm_display_mode *mode;
124 unsigned int i, num = 0;
125
a5d3e625
PZ		 126 for (i = 0; i < panel->desc->num_timings; i++) {
127 const struct display_timing *dt = &panel->desc->timings[i];
128 struct videomode vm;
129
130 videomode_from_timing(dt, &vm);
aa6c4364 131 mode = drm_mode_create(connector->dev);
a5d3e625 132 if (!mode) {
aa6c4364 133 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 134 dt->hactive.typ, dt->vactive.typ);
135 continue;
136 }
137
138 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 139
140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
230c5b44 142 if (panel->desc->num_timings == 1)
cda55372
BB		 143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
a5d3e625
PZ		 145 drm_mode_probed_add(connector, mode);
146 num++;
147 }
148
b8a2948f
SP		 149 return num;
150}
151
0ce8ddd8
SR		 152static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
153 struct drm_connector *connector)
b8a2948f 154{
b8a2948f
SP		 155 struct drm_display_mode *mode;
156 unsigned int i, num = 0;
157
280921de
TR		 158 for (i = 0; i < panel->desc->num_modes; i++) {
159 const struct drm_display_mode *m = &panel->desc->modes[i];
160
aa6c4364 161 mode = drm_mode_duplicate(connector->dev, m);
280921de 162 if (!mode) {
aa6c4364 163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
280921de
TR		 164 m->hdisplay, m->vdisplay, m->vrefresh);
165 continue;
166 }
167
cda55372
BB		 168 mode->type |= DRM_MODE_TYPE_DRIVER;
169
170 if (panel->desc->num_modes == 1)
171 mode->type |= DRM_MODE_TYPE_PREFERRED;
172
280921de
TR		 173 drm_mode_set_name(mode);
174
175 drm_mode_probed_add(connector, mode);
176 num++;
177 }
178
b8a2948f
SP		 179 return num;
180}
181
0ce8ddd8
SR		 182static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
183 struct drm_connector *connector)
b8a2948f 184{
b8a2948f
SP		 185 struct drm_display_mode *mode;
186 bool has_override = panel->override_mode.type;
187 unsigned int num = 0;
188
189 if (!panel->desc)
190 return 0;
191
192 if (has_override) {
aa6c4364
SR		 193 mode = drm_mode_duplicate(connector->dev,
194 &panel->override_mode);
b8a2948f
SP		 195 if (mode) {
196 drm_mode_probed_add(connector, mode);
197 num = 1;
198 } else {
aa6c4364 199 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 200 }
201 }
202
203 /* Only add timings if override was not there or failed to validate */
204 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 205 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 206
207 /*
208 * Only add fixed modes if timings/override added no mode.
209 *
210 * We should only ever have either the display timings specified
211 * or a fixed mode. Anything else is rather bogus.
212 */
213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
214 if (num == 0)
0ce8ddd8 215 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 216
0208d511 217 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 218 connector->display_info.width_mm = panel->desc->size.width;
219 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 220 if (panel->desc->bus_format)
221 drm_display_info_set_bus_formats(&connector->display_info,
222 &panel->desc->bus_format, 1);
f0aa0838 223 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 224
225 return num;
226}
227
228static int panel_simple_disable(struct drm_panel *panel)
229{
230 struct panel_simple *p = to_panel_simple(panel);
231
232 if (!p->enabled)
233 return 0;
234
f673c37e
AK		 235 if (p->desc->delay.disable)
236 msleep(p->desc->delay.disable);
237
280921de
TR		 238 p->enabled = false;
239
240 return 0;
241}
242
c0e1d170
AK		 243static int panel_simple_unprepare(struct drm_panel *panel)
244{
613a633e
AK		 245 struct panel_simple *p = to_panel_simple(panel);
246
247 if (!p->prepared)
248 return 0;
249
756b918d 250 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 251
252 regulator_disable(p->supply);
253
f673c37e
AK		 254 if (p->desc->delay.unprepare)
255 msleep(p->desc->delay.unprepare);
256
613a633e 257 p->prepared = false;
c0e1d170 258
c0e1d170
AK		 259 return 0;
260}
261
613a633e 262static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 263{
264 struct panel_simple *p = to_panel_simple(panel);
2ed3e951 265 unsigned int delay;
280921de
TR		 266 int err;
267
613a633e 268 if (p->prepared)
280921de
TR		 269 return 0;
270
271 err = regulator_enable(p->supply);
272 if (err < 0) {
273 dev_err(panel->dev, "failed to enable supply: %d\n", err);
274 return err;
275 }
276
756b918d 277 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 278
2ed3e951
DA		 279 delay = p->desc->delay.prepare;
280 if (p->no_hpd)
281 delay += p->desc->delay.hpd_absent_delay;
282 if (delay)
283 msleep(delay);
f673c37e 284
613a633e
AK		 285 p->prepared = true;
286
287 return 0;
288}
289
290static int panel_simple_enable(struct drm_panel *panel)
291{
292 struct panel_simple *p = to_panel_simple(panel);
293
294 if (p->enabled)
295 return 0;
296
f673c37e
AK		 297 if (p->desc->delay.enable)
298 msleep(p->desc->delay.enable);
299
280921de
TR		 300 p->enabled = true;
301
302 return 0;
303}
304
0ce8ddd8
SR		 305static int panel_simple_get_modes(struct drm_panel *panel,
306 struct drm_connector *connector)
280921de
TR		 307{
308 struct panel_simple *p = to_panel_simple(panel);
309 int num = 0;
310
311 /* probe EDID if a DDC bus is available */
312 if (p->ddc) {
0ce8ddd8
SR		 313 struct edid *edid = drm_get_edid(connector, p->ddc);
314
315 drm_connector_update_edid_property(connector, edid);
280921de 316 if (edid) {
0ce8ddd8 317 num += drm_add_edid_modes(connector, edid);
280921de
TR		 318 kfree(edid);
319 }
320 }
321
322 /* add hard-coded panel modes */
0ce8ddd8 323 num += panel_simple_get_non_edid_modes(p, connector);
280921de
TR		 324
325 return num;
326}
327
a5d3e625
PZ		 328static int panel_simple_get_timings(struct drm_panel *panel,
329 unsigned int num_timings,
330 struct display_timing *timings)
331{
332 struct panel_simple *p = to_panel_simple(panel);
333 unsigned int i;
334
335 if (p->desc->num_timings < num_timings)
336 num_timings = p->desc->num_timings;
337
338 if (timings)
339 for (i = 0; i < num_timings; i++)
340 timings[i] = p->desc->timings[i];
341
342 return p->desc->num_timings;
343}
344
280921de
TR		 345static const struct drm_panel_funcs panel_simple_funcs = {
346 .disable = panel_simple_disable,
c0e1d170
AK		 347 .unprepare = panel_simple_unprepare,
348 .prepare = panel_simple_prepare,
280921de
TR		 349 .enable = panel_simple_enable,
350 .get_modes = panel_simple_get_modes,
a5d3e625 351 .get_timings = panel_simple_get_timings,
280921de
TR		 352};
353
b8a2948f
SP		 354#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
355 (to_check->field.typ >= bounds->field.min && \
356 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 357static void panel_simple_parse_panel_timing_node(struct device *dev,
358 struct panel_simple *panel,
359 const struct display_timing *ot)
b8a2948f
SP		 360{
361 const struct panel_desc *desc = panel->desc;
362 struct videomode vm;
363 unsigned int i;
364
365 if (WARN_ON(desc->num_modes)) {
366 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
367 return;
368 }
369 if (WARN_ON(!desc->num_timings)) {
370 dev_err(dev, "Reject override mode: no timings specified\n");
371 return;
372 }
373
374 for (i = 0; i < panel->desc->num_timings; i++) {
375 const struct display_timing *dt = &panel->desc->timings[i];
376
377 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
378 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
379 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
380 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
381 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
382 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
383 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
384 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
385 continue;
386
387 if (ot->flags != dt->flags)
388 continue;
389
390 videomode_from_timing(ot, &vm);
391 drm_display_mode_from_videomode(&vm, &panel->override_mode);
392 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
393 DRM_MODE_TYPE_PREFERRED;
394 break;
395 }
396
397 if (WARN_ON(!panel->override_mode.type))
398 dev_err(dev, "Reject override mode: No display_timing found\n");
399}
400
280921de
TR		 401static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
402{
280921de 403 struct panel_simple *panel;
b8a2948f 404 struct display_timing dt;
0fe1564b 405 struct device_node *ddc;
280921de
TR		 406 int err;
407
408 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
409 if (!panel)
410 return -ENOMEM;
411
412 panel->enabled = false;
613a633e 413 panel->prepared = false;
280921de
TR		 414 panel->desc = desc;
415
2ed3e951
DA		 416 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
417
280921de
TR		 418 panel->supply = devm_regulator_get(dev, "power");
419 if (IS_ERR(panel->supply))
420 return PTR_ERR(panel->supply);
421
a61400d8
AC		 422 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
423 GPIOD_OUT_LOW);
cfdf0549
AC		 424 if (IS_ERR(panel->enable_gpio)) {
425 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 426 if (err != -EPROBE_DEFER)
427 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 428 return err;
429 }
280921de 430
280921de
TR		 431 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
432 if (ddc) {
433 panel->ddc = of_find_i2c_adapter_by_node(ddc);
434 of_node_put(ddc);
435
0fe1564b
SR		 436 if (!panel->ddc)
437 return -EPROBE_DEFER;
280921de
TR		 438 }
439
b8a2948f 440 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
e362cc6a 441 panel_simple_parse_panel_timing_node(dev, panel, &dt);
b8a2948f 442
9a2654c0
LP		 443 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
444 desc->connector_type);
280921de 445
0fe1564b
SR		 446 err = drm_panel_of_backlight(&panel->base);
447 if (err)
448 goto free_ddc;
449
280921de
TR		 450 err = drm_panel_add(&panel->base);
451 if (err < 0)
452 goto free_ddc;
453
454 dev_set_drvdata(dev, panel);
455
456 return 0;
457
458free_ddc:
459 if (panel->ddc)
460 put_device(&panel->ddc->dev);
280921de
TR		 461
462 return err;
463}
464
465static int panel_simple_remove(struct device *dev)
466{
467 struct panel_simple *panel = dev_get_drvdata(dev);
468
280921de 469 drm_panel_remove(&panel->base);
0fe1564b
SR		 470 drm_panel_disable(&panel->base);
471 drm_panel_unprepare(&panel->base);
280921de
TR		 472
473 if (panel->ddc)
474 put_device(&panel->ddc->dev);
475
280921de
TR		 476 return 0;
477}
478
d02fd93e
TR		 479static void panel_simple_shutdown(struct device *dev)
480{
481 struct panel_simple *panel = dev_get_drvdata(dev);
482
0fe1564b
SR		 483 drm_panel_disable(&panel->base);
484 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 485}
486
966fea78
YF		 487static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
488 .clock = 9000,
489 .hdisplay = 480,
490 .hsync_start = 480 + 2,
491 .hsync_end = 480 + 2 + 41,
492 .htotal = 480 + 2 + 41 + 2,
493 .vdisplay = 272,
494 .vsync_start = 272 + 2,
495 .vsync_end = 272 + 2 + 10,
496 .vtotal = 272 + 2 + 10 + 2,
497 .vrefresh = 60,
498 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
499};
500
501static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
502 .modes = &ampire_am_480272h3tmqw_t01h_mode,
503 .num_modes = 1,
504 .bpc = 8,
505 .size = {
506 .width = 105,
507 .height = 67,
508 },
509 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
510};
511
1c550fa1
PZ		 512static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
513 .clock = 33333,
514 .hdisplay = 800,
515 .hsync_start = 800 + 0,
516 .hsync_end = 800 + 0 + 255,
517 .htotal = 800 + 0 + 255 + 0,
518 .vdisplay = 480,
519 .vsync_start = 480 + 2,
520 .vsync_end = 480 + 2 + 45,
521 .vtotal = 480 + 2 + 45 + 0,
522 .vrefresh = 60,
523 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
524};
525
526static const struct panel_desc ampire_am800480r3tmqwa1h = {
527 .modes = &ampire_am800480r3tmqwa1h_mode,
528 .num_modes = 1,
529 .bpc = 6,
530 .size = {
531 .width = 152,
532 .height = 91,
533 },
534 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
535};
536
c479450f
SS		 537static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
538 .pixelclock = { 26400000, 33300000, 46800000 },
539 .hactive = { 800, 800, 800 },
540 .hfront_porch = { 16, 210, 354 },
541 .hback_porch = { 45, 36, 6 },
542 .hsync_len = { 1, 10, 40 },
543 .vactive = { 480, 480, 480 },
544 .vfront_porch = { 7, 22, 147 },
545 .vback_porch = { 22, 13, 3 },
546 .vsync_len = { 1, 10, 20 },
547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
548 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
549};
550
551static const struct panel_desc armadeus_st0700_adapt = {
552 .timings = &santek_st0700i5y_rbslw_f_timing,
553 .num_timings = 1,
554 .bpc = 6,
555 .size = {
556 .width = 154,
557 .height = 86,
558 },
559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
561};
562
280921de
TR		 563static const struct drm_display_mode auo_b101aw03_mode = {
564 .clock = 51450,
565 .hdisplay = 1024,
566 .hsync_start = 1024 + 156,
567 .hsync_end = 1024 + 156 + 8,
568 .htotal = 1024 + 156 + 8 + 156,
569 .vdisplay = 600,
570 .vsync_start = 600 + 16,
571 .vsync_end = 600 + 16 + 6,
572 .vtotal = 600 + 16 + 6 + 16,
573 .vrefresh = 60,
574};
575
576static const struct panel_desc auo_b101aw03 = {
577 .modes = &auo_b101aw03_mode,
578 .num_modes = 1,
0208d511 579 .bpc = 6,
280921de
TR		 580 .size = {
581 .width = 223,
582 .height = 125,
583 },
584};
585
374bf825
DA		 586static const struct display_timing auo_b101ean01_timing = {
587 .pixelclock = { 65300000, 72500000, 75000000 },
588 .hactive = { 1280, 1280, 1280 },
589 .hfront_porch = { 18, 119, 119 },
590 .hback_porch = { 21, 21, 21 },
591 .hsync_len = { 32, 32, 32 },
592 .vactive = { 800, 800, 800 },
593 .vfront_porch = { 4, 4, 4 },
594 .vback_porch = { 8, 8, 8 },
595 .vsync_len = { 18, 20, 20 },
a531bc3d
HL		 596};
597
598static const struct panel_desc auo_b101ean01 = {
374bf825
DA		 599 .timings = &auo_b101ean01_timing,
600 .num_timings = 1,
a531bc3d
HL		 601 .bpc = 6,
602 .size = {
603 .width = 217,
604 .height = 136,
605 },
606};
607
dac746e0
RC		 608static const struct drm_display_mode auo_b101xtn01_mode = {
609 .clock = 72000,
610 .hdisplay = 1366,
611 .hsync_start = 1366 + 20,
612 .hsync_end = 1366 + 20 + 70,
613 .htotal = 1366 + 20 + 70,
614 .vdisplay = 768,
615 .vsync_start = 768 + 14,
616 .vsync_end = 768 + 14 + 42,
617 .vtotal = 768 + 14 + 42,
618 .vrefresh = 60,
619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
620};
621
622static const struct panel_desc auo_b101xtn01 = {
623 .modes = &auo_b101xtn01_mode,
624 .num_modes = 1,
625 .bpc = 6,
626 .size = {
627 .width = 223,
628 .height = 125,
629 },
630};
631
e35e305e
AK		 632static const struct drm_display_mode auo_b116xw03_mode = {
633 .clock = 70589,
634 .hdisplay = 1366,
635 .hsync_start = 1366 + 40,
636 .hsync_end = 1366 + 40 + 40,
637 .htotal = 1366 + 40 + 40 + 32,
638 .vdisplay = 768,
639 .vsync_start = 768 + 10,
640 .vsync_end = 768 + 10 + 12,
641 .vtotal = 768 + 10 + 12 + 6,
642 .vrefresh = 60,
643};
644
645static const struct panel_desc auo_b116xw03 = {
646 .modes = &auo_b116xw03_mode,
647 .num_modes = 1,
648 .bpc = 6,
649 .size = {
650 .width = 256,
651 .height = 144,
652 },
653};
654
a333f7ad
SM		 655static const struct drm_display_mode auo_b133xtn01_mode = {
656 .clock = 69500,
657 .hdisplay = 1366,
658 .hsync_start = 1366 + 48,
659 .hsync_end = 1366 + 48 + 32,
660 .htotal = 1366 + 48 + 32 + 20,
661 .vdisplay = 768,
662 .vsync_start = 768 + 3,
663 .vsync_end = 768 + 3 + 6,
664 .vtotal = 768 + 3 + 6 + 13,
665 .vrefresh = 60,
666};
667
668static const struct panel_desc auo_b133xtn01 = {
669 .modes = &auo_b133xtn01_mode,
670 .num_modes = 1,
0208d511 671 .bpc = 6,
a333f7ad
SM		 672 .size = {
673 .width = 293,
674 .height = 165,
675 },
676};
677
3e51d609
AK		 678static const struct drm_display_mode auo_b133htn01_mode = {
679 .clock = 150660,
680 .hdisplay = 1920,
681 .hsync_start = 1920 + 172,
682 .hsync_end = 1920 + 172 + 80,
683 .htotal = 1920 + 172 + 80 + 60,
684 .vdisplay = 1080,
685 .vsync_start = 1080 + 25,
686 .vsync_end = 1080 + 25 + 10,
687 .vtotal = 1080 + 25 + 10 + 10,
688 .vrefresh = 60,
689};
690
691static const struct panel_desc auo_b133htn01 = {
692 .modes = &auo_b133htn01_mode,
693 .num_modes = 1,
d7a839cd 694 .bpc = 6,
3e51d609
AK		 695 .size = {
696 .width = 293,
697 .height = 165,
698 },
699 .delay = {
700 .prepare = 105,
701 .enable = 20,
702 .unprepare = 50,
703 },
704};
705
bccfaffb
LM		 706static const struct display_timing auo_g070vvn01_timings = {
707 .pixelclock = { 33300000, 34209000, 45000000 },
708 .hactive = { 800, 800, 800 },
709 .hfront_porch = { 20, 40, 200 },
710 .hback_porch = { 87, 40, 1 },
711 .hsync_len = { 1, 48, 87 },
712 .vactive = { 480, 480, 480 },
713 .vfront_porch = { 5, 13, 200 },
714 .vback_porch = { 31, 31, 29 },
715 .vsync_len = { 1, 1, 3 },
716};
717
718static const struct panel_desc auo_g070vvn01 = {
719 .timings = &auo_g070vvn01_timings,
720 .num_timings = 1,
721 .bpc = 8,
722 .size = {
723 .width = 152,
724 .height = 91,
725 },
726 .delay = {
727 .prepare = 200,
728 .enable = 50,
729 .disable = 50,
730 .unprepare = 1000,
731 },
732};
733
4fb86404
AG		 734static const struct drm_display_mode auo_g101evn010_mode = {
735 .clock = 68930,
736 .hdisplay = 1280,
737 .hsync_start = 1280 + 82,
738 .hsync_end = 1280 + 82 + 2,
739 .htotal = 1280 + 82 + 2 + 84,
740 .vdisplay = 800,
741 .vsync_start = 800 + 8,
742 .vsync_end = 800 + 8 + 2,
743 .vtotal = 800 + 8 + 2 + 6,
744 .vrefresh = 60,
745};
746
747static const struct panel_desc auo_g101evn010 = {
748 .modes = &auo_g101evn010_mode,
749 .num_modes = 1,
750 .bpc = 6,
751 .size = {
752 .width = 216,
753 .height = 135,
754 },
755 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
756};
757
4451c287
CF		 758static const struct drm_display_mode auo_g104sn02_mode = {
759 .clock = 40000,
760 .hdisplay = 800,
761 .hsync_start = 800 + 40,
762 .hsync_end = 800 + 40 + 216,
763 .htotal = 800 + 40 + 216 + 128,
764 .vdisplay = 600,
765 .vsync_start = 600 + 10,
766 .vsync_end = 600 + 10 + 35,
767 .vtotal = 600 + 10 + 35 + 2,
768 .vrefresh = 60,
769};
770
771static const struct panel_desc auo_g104sn02 = {
772 .modes = &auo_g104sn02_mode,
773 .num_modes = 1,
774 .bpc = 8,
775 .size = {
776 .width = 211,
777 .height = 158,
778 },
779};
780
697035c6
LS		 781static const struct display_timing auo_g133han01_timings = {
782 .pixelclock = { 134000000, 141200000, 149000000 },
783 .hactive = { 1920, 1920, 1920 },
784 .hfront_porch = { 39, 58, 77 },
785 .hback_porch = { 59, 88, 117 },
786 .hsync_len = { 28, 42, 56 },
787 .vactive = { 1080, 1080, 1080 },
788 .vfront_porch = { 3, 8, 11 },
789 .vback_porch = { 5, 14, 19 },
790 .vsync_len = { 4, 14, 19 },
791};
792
793static const struct panel_desc auo_g133han01 = {
794 .timings = &auo_g133han01_timings,
795 .num_timings = 1,
796 .bpc = 8,
797 .size = {
798 .width = 293,
799 .height = 165,
800 },
801 .delay = {
802 .prepare = 200,
803 .enable = 50,
804 .disable = 50,
805 .unprepare = 1000,
806 },
807 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 808 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 809};
810
8c31f603
LS		 811static const struct display_timing auo_g185han01_timings = {
812 .pixelclock = { 120000000, 144000000, 175000000 },
813 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 814 .hfront_porch = { 36, 120, 148 },
815 .hback_porch = { 24, 88, 108 },
816 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 817 .vactive = { 1080, 1080, 1080 },
818 .vfront_porch = { 6, 10, 40 },
819 .vback_porch = { 2, 5, 20 },
820 .vsync_len = { 2, 5, 20 },
821};
822
823static const struct panel_desc auo_g185han01 = {
824 .timings = &auo_g185han01_timings,
825 .num_timings = 1,
826 .bpc = 8,
827 .size = {
828 .width = 409,
829 .height = 230,
830 },
831 .delay = {
832 .prepare = 50,
833 .enable = 200,
834 .disable = 110,
835 .unprepare = 1000,
836 },
837 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 838 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 839};
840
70c0d5b7
LS		 841static const struct display_timing auo_p320hvn03_timings = {
842 .pixelclock = { 106000000, 148500000, 164000000 },
843 .hactive = { 1920, 1920, 1920 },
844 .hfront_porch = { 25, 50, 130 },
845 .hback_porch = { 25, 50, 130 },
846 .hsync_len = { 20, 40, 105 },
847 .vactive = { 1080, 1080, 1080 },
848 .vfront_porch = { 8, 17, 150 },
849 .vback_porch = { 8, 17, 150 },
850 .vsync_len = { 4, 11, 100 },
851};
852
853static const struct panel_desc auo_p320hvn03 = {
854 .timings = &auo_p320hvn03_timings,
855 .num_timings = 1,
856 .bpc = 8,
857 .size = {
858 .width = 698,
859 .height = 393,
860 },
861 .delay = {
862 .prepare = 1,
863 .enable = 450,
864 .unprepare = 500,
865 },
2554f154 866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 868};
869
7ee933a1
HS		 870static const struct drm_display_mode auo_t215hvn01_mode = {
871 .clock = 148800,
872 .hdisplay = 1920,
873 .hsync_start = 1920 + 88,
874 .hsync_end = 1920 + 88 + 44,
875 .htotal = 1920 + 88 + 44 + 148,
876 .vdisplay = 1080,
877 .vsync_start = 1080 + 4,
878 .vsync_end = 1080 + 4 + 5,
879 .vtotal = 1080 + 4 + 5 + 36,
880 .vrefresh = 60,
881};
882
883static const struct panel_desc auo_t215hvn01 = {
884 .modes = &auo_t215hvn01_mode,
885 .num_modes = 1,
886 .bpc = 8,
887 .size = {
888 .width = 430,
889 .height = 270,
890 },
891 .delay = {
892 .disable = 5,
893 .unprepare = 1000,
894 }
895};
896
d47df633
PZ		 897static const struct drm_display_mode avic_tm070ddh03_mode = {
898 .clock = 51200,
899 .hdisplay = 1024,
900 .hsync_start = 1024 + 160,
901 .hsync_end = 1024 + 160 + 4,
902 .htotal = 1024 + 160 + 4 + 156,
903 .vdisplay = 600,
904 .vsync_start = 600 + 17,
905 .vsync_end = 600 + 17 + 1,
906 .vtotal = 600 + 17 + 1 + 17,
907 .vrefresh = 60,
908};
909
910static const struct panel_desc avic_tm070ddh03 = {
911 .modes = &avic_tm070ddh03_mode,
912 .num_modes = 1,
913 .bpc = 8,
914 .size = {
915 .width = 154,
916 .height = 90,
917 },
918 .delay = {
919 .prepare = 20,
920 .enable = 200,
921 .disable = 200,
922 },
923};
924
7ad8b41c
CYT		 925static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
926 .clock = 30000,
927 .hdisplay = 800,
928 .hsync_start = 800 + 40,
929 .hsync_end = 800 + 40 + 48,
930 .htotal = 800 + 40 + 48 + 40,
931 .vdisplay = 480,
932 .vsync_start = 480 + 13,
933 .vsync_end = 480 + 13 + 3,
934 .vtotal = 480 + 13 + 3 + 29,
935};
936
937static const struct panel_desc bananapi_s070wv20_ct16 = {
938 .modes = &bananapi_s070wv20_ct16_mode,
939 .num_modes = 1,
940 .bpc = 6,
941 .size = {
942 .width = 154,
943 .height = 86,
944 },
945};
946
ae8cf41b 947static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 948 .clock = 42105,
ae8cf41b 949 .hdisplay = 1024,
e077e2f5
AH		 950 .hsync_start = 1024 + 30,
951 .hsync_end = 1024 + 30 + 30,
952 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 953 .vdisplay = 600,
e077e2f5
AH		 954 .vsync_start = 600 + 10,
955 .vsync_end = 600 + 10 + 10,
956 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 957 .vrefresh = 60,
958};
959
960static const struct panel_desc boe_hv070wsa = {
961 .modes = &boe_hv070wsa_mode,
962 .num_modes = 1,
963 .size = {
964 .width = 154,
965 .height = 90,
966 },
967};
968
cac1a411
CW		 969static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
970 {
971 .clock = 71900,
972 .hdisplay = 1280,
973 .hsync_start = 1280 + 48,
974 .hsync_end = 1280 + 48 + 32,
975 .htotal = 1280 + 48 + 32 + 80,
976 .vdisplay = 800,
977 .vsync_start = 800 + 3,
978 .vsync_end = 800 + 3 + 5,
979 .vtotal = 800 + 3 + 5 + 24,
980 .vrefresh = 60,
981 },
982 {
983 .clock = 57500,
984 .hdisplay = 1280,
985 .hsync_start = 1280 + 48,
986 .hsync_end = 1280 + 48 + 32,
987 .htotal = 1280 + 48 + 32 + 80,
988 .vdisplay = 800,
989 .vsync_start = 800 + 3,
990 .vsync_end = 800 + 3 + 5,
991 .vtotal = 800 + 3 + 5 + 24,
992 .vrefresh = 48,
993 },
994};
995
996static const struct panel_desc boe_nv101wxmn51 = {
997 .modes = boe_nv101wxmn51_modes,
998 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
999 .bpc = 8,
1000 .size = {
1001 .width = 217,
1002 .height = 136,
1003 },
1004 .delay = {
1005 .prepare = 210,
1006 .enable = 50,
1007 .unprepare = 160,
1008 },
1009};
1010
e58edce6
GB		 1011static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1012 .clock = 9000,
1013 .hdisplay = 480,
1014 .hsync_start = 480 + 5,
1015 .hsync_end = 480 + 5 + 5,
1016 .htotal = 480 + 5 + 5 + 40,
1017 .vdisplay = 272,
1018 .vsync_start = 272 + 8,
1019 .vsync_end = 272 + 8 + 8,
1020 .vtotal = 272 + 8 + 8 + 8,
1021 .vrefresh = 60,
1022 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1023};
1024
1025static const struct panel_desc cdtech_s043wq26h_ct7 = {
1026 .modes = &cdtech_s043wq26h_ct7_mode,
1027 .num_modes = 1,
1028 .bpc = 8,
1029 .size = {
1030 .width = 95,
1031 .height = 54,
1032 },
88bc4178 1033 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1034};
1035
982f944e
GB		 1036static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1037 .clock = 35000,
1038 .hdisplay = 800,
1039 .hsync_start = 800 + 40,
1040 .hsync_end = 800 + 40 + 40,
1041 .htotal = 800 + 40 + 40 + 48,
1042 .vdisplay = 480,
1043 .vsync_start = 480 + 29,
1044 .vsync_end = 480 + 29 + 13,
1045 .vtotal = 480 + 29 + 13 + 3,
1046 .vrefresh = 60,
1047 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1048};
1049
1050static const struct panel_desc cdtech_s070wv95_ct16 = {
1051 .modes = &cdtech_s070wv95_ct16_mode,
1052 .num_modes = 1,
1053 .bpc = 8,
1054 .size = {
1055 .width = 154,
1056 .height = 85,
1057 },
1058};
1059
2cb35c80
RL		 1060static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1061 .clock = 66770,
1062 .hdisplay = 800,
1063 .hsync_start = 800 + 49,
1064 .hsync_end = 800 + 49 + 33,
1065 .htotal = 800 + 49 + 33 + 17,
1066 .vdisplay = 1280,
1067 .vsync_start = 1280 + 1,
1068 .vsync_end = 1280 + 1 + 7,
1069 .vtotal = 1280 + 1 + 7 + 15,
1070 .vrefresh = 60,
1071 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1072};
1073
1074static const struct panel_desc chunghwa_claa070wp03xg = {
1075 .modes = &chunghwa_claa070wp03xg_mode,
1076 .num_modes = 1,
1077 .bpc = 6,
1078 .size = {
1079 .width = 94,
1080 .height = 150,
1081 },
1082};
1083
4c930757
SW		 1084static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1085 .clock = 72070,
1086 .hdisplay = 1366,
1087 .hsync_start = 1366 + 58,
1088 .hsync_end = 1366 + 58 + 58,
1089 .htotal = 1366 + 58 + 58 + 58,
1090 .vdisplay = 768,
1091 .vsync_start = 768 + 4,
1092 .vsync_end = 768 + 4 + 4,
1093 .vtotal = 768 + 4 + 4 + 4,
1094 .vrefresh = 60,
1095};
1096
1097static const struct panel_desc chunghwa_claa101wa01a = {
1098 .modes = &chunghwa_claa101wa01a_mode,
1099 .num_modes = 1,
0208d511 1100 .bpc = 6,
4c930757
SW		 1101 .size = {
1102 .width = 220,
1103 .height = 120,
1104 },
1105};
1106
280921de
TR		 1107static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1108 .clock = 69300,
1109 .hdisplay = 1366,
1110 .hsync_start = 1366 + 48,
1111 .hsync_end = 1366 + 48 + 32,
1112 .htotal = 1366 + 48 + 32 + 20,
1113 .vdisplay = 768,
1114 .vsync_start = 768 + 16,
1115 .vsync_end = 768 + 16 + 8,
1116 .vtotal = 768 + 16 + 8 + 16,
1117 .vrefresh = 60,
1118};
1119
1120static const struct panel_desc chunghwa_claa101wb01 = {
1121 .modes = &chunghwa_claa101wb01_mode,
1122 .num_modes = 1,
0208d511 1123 .bpc = 6,
280921de
TR		 1124 .size = {
1125 .width = 223,
1126 .height = 125,
1127 },
1128};
1129
97ceb1fb
MV		 1130static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1131 .clock = 33260,
1132 .hdisplay = 800,
1133 .hsync_start = 800 + 40,
1134 .hsync_end = 800 + 40 + 128,
1135 .htotal = 800 + 40 + 128 + 88,
1136 .vdisplay = 480,
1137 .vsync_start = 480 + 10,
1138 .vsync_end = 480 + 10 + 2,
1139 .vtotal = 480 + 10 + 2 + 33,
1140 .vrefresh = 60,
1141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1142};
1143
1144static const struct panel_desc dataimage_scf0700c48ggu18 = {
1145 .modes = &dataimage_scf0700c48ggu18_mode,
1146 .num_modes = 1,
1147 .bpc = 8,
1148 .size = {
1149 .width = 152,
1150 .height = 91,
1151 },
1152 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1153 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1154};
1155
0ca0c827
PZ		 1156static const struct display_timing dlc_dlc0700yzg_1_timing = {
1157 .pixelclock = { 45000000, 51200000, 57000000 },
1158 .hactive = { 1024, 1024, 1024 },
1159 .hfront_porch = { 100, 106, 113 },
1160 .hback_porch = { 100, 106, 113 },
1161 .hsync_len = { 100, 108, 114 },
1162 .vactive = { 600, 600, 600 },
1163 .vfront_porch = { 8, 11, 15 },
1164 .vback_porch = { 8, 11, 15 },
1165 .vsync_len = { 9, 13, 15 },
1166 .flags = DISPLAY_FLAGS_DE_HIGH,
1167};
1168
1169static const struct panel_desc dlc_dlc0700yzg_1 = {
1170 .timings = &dlc_dlc0700yzg_1_timing,
1171 .num_timings = 1,
1172 .bpc = 6,
1173 .size = {
1174 .width = 154,
1175 .height = 86,
1176 },
1177 .delay = {
1178 .prepare = 30,
1179 .enable = 200,
1180 .disable = 200,
1181 },
1182 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1183 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1184};
1185
6cbe7cd1
MF		 1186static const struct display_timing dlc_dlc1010gig_timing = {
1187 .pixelclock = { 68900000, 71100000, 73400000 },
1188 .hactive = { 1280, 1280, 1280 },
1189 .hfront_porch = { 43, 53, 63 },
1190 .hback_porch = { 43, 53, 63 },
1191 .hsync_len = { 44, 54, 64 },
1192 .vactive = { 800, 800, 800 },
1193 .vfront_porch = { 5, 8, 11 },
1194 .vback_porch = { 5, 8, 11 },
1195 .vsync_len = { 5, 7, 11 },
1196 .flags = DISPLAY_FLAGS_DE_HIGH,
1197};
1198
1199static const struct panel_desc dlc_dlc1010gig = {
1200 .timings = &dlc_dlc1010gig_timing,
1201 .num_timings = 1,
1202 .bpc = 8,
1203 .size = {
1204 .width = 216,
1205 .height = 135,
1206 },
1207 .delay = {
1208 .prepare = 60,
1209 .enable = 150,
1210 .disable = 100,
1211 .unprepare = 60,
1212 },
1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1214 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1215};
1216
c2d24af6
AP		 1217static const struct drm_display_mode edt_et035012dm6_mode = {
1218 .clock = 6500,
1219 .hdisplay = 320,
1220 .hsync_start = 320 + 20,
1221 .hsync_end = 320 + 20 + 30,
1222 .htotal = 320 + 20 + 68,
1223 .vdisplay = 240,
1224 .vsync_start = 240 + 4,
1225 .vsync_end = 240 + 4 + 4,
1226 .vtotal = 240 + 4 + 4 + 14,
1227 .vrefresh = 60,
1228 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1229};
1230
1231static const struct panel_desc edt_et035012dm6 = {
1232 .modes = &edt_et035012dm6_mode,
1233 .num_modes = 1,
1234 .bpc = 8,
1235 .size = {
1236 .width = 70,
1237 .height = 52,
1238 },
1239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1240 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1241};
1242
fd819bff
MV		 1243static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1244 .clock = 9000,
1245 .hdisplay = 480,
1246 .hsync_start = 480 + 2,
1247 .hsync_end = 480 + 2 + 41,
1248 .htotal = 480 + 2 + 41 + 2,
1249 .vdisplay = 272,
1250 .vsync_start = 272 + 2,
1251 .vsync_end = 272 + 2 + 10,
1252 .vtotal = 272 + 2 + 10 + 2,
1253 .vrefresh = 60,
1254 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1255};
1256
1257static const struct panel_desc edt_etm0430g0dh6 = {
1258 .modes = &edt_etm0430g0dh6_mode,
1259 .num_modes = 1,
1260 .bpc = 6,
1261 .size = {
1262 .width = 95,
1263 .height = 54,
1264 },
1265};
1266
26ab0065
SA		 1267static const struct drm_display_mode edt_et057090dhu_mode = {
1268 .clock = 25175,
1269 .hdisplay = 640,
1270 .hsync_start = 640 + 16,
1271 .hsync_end = 640 + 16 + 30,
1272 .htotal = 640 + 16 + 30 + 114,
1273 .vdisplay = 480,
1274 .vsync_start = 480 + 10,
1275 .vsync_end = 480 + 10 + 3,
1276 .vtotal = 480 + 10 + 3 + 32,
1277 .vrefresh = 60,
1278 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1279};
1280
1281static const struct panel_desc edt_et057090dhu = {
1282 .modes = &edt_et057090dhu_mode,
1283 .num_modes = 1,
0208d511 1284 .bpc = 6,
26ab0065
SA		 1285 .size = {
1286 .width = 115,
1287 .height = 86,
1288 },
eaeebffa 1289 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
26ab0065
SA		 1291};
1292
fff5de45
PZ		 1293static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1294 .clock = 33260,
1295 .hdisplay = 800,
1296 .hsync_start = 800 + 40,
1297 .hsync_end = 800 + 40 + 128,
1298 .htotal = 800 + 40 + 128 + 88,
1299 .vdisplay = 480,
1300 .vsync_start = 480 + 10,
1301 .vsync_end = 480 + 10 + 2,
1302 .vtotal = 480 + 10 + 2 + 33,
1303 .vrefresh = 60,
1304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1305};
1306
1307static const struct panel_desc edt_etm0700g0dh6 = {
1308 .modes = &edt_etm0700g0dh6_mode,
1309 .num_modes = 1,
0208d511 1310 .bpc = 6,
fff5de45
PZ		 1311 .size = {
1312 .width = 152,
1313 .height = 91,
1314 },
eaeebffa 1315 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
fff5de45
PZ		 1317};
1318
aa7e6455
JT		 1319static const struct panel_desc edt_etm0700g0bdh6 = {
1320 .modes = &edt_etm0700g0dh6_mode,
1321 .num_modes = 1,
1322 .bpc = 6,
1323 .size = {
1324 .width = 152,
1325 .height = 91,
1326 },
1327 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1328 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
aa7e6455
JT		 1329};
1330
9158e3c3
MF		 1331static const struct display_timing evervision_vgg804821_timing = {
1332 .pixelclock = { 27600000, 33300000, 50000000 },
1333 .hactive = { 800, 800, 800 },
1334 .hfront_porch = { 40, 66, 70 },
1335 .hback_porch = { 40, 67, 70 },
1336 .hsync_len = { 40, 67, 70 },
1337 .vactive = { 480, 480, 480 },
1338 .vfront_porch = { 6, 10, 10 },
1339 .vback_porch = { 7, 11, 11 },
1340 .vsync_len = { 7, 11, 11 },
1341 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1342 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1343 DISPLAY_FLAGS_SYNC_NEGEDGE,
1344};
1345
1346static const struct panel_desc evervision_vgg804821 = {
1347 .timings = &evervision_vgg804821_timing,
1348 .num_timings = 1,
1349 .bpc = 8,
1350 .size = {
1351 .width = 108,
1352 .height = 64,
1353 },
1354 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1355 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1356};
1357
102932b0
BB		 1358static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1359 .clock = 32260,
1360 .hdisplay = 800,
1361 .hsync_start = 800 + 168,
1362 .hsync_end = 800 + 168 + 64,
1363 .htotal = 800 + 168 + 64 + 88,
1364 .vdisplay = 480,
1365 .vsync_start = 480 + 37,
1366 .vsync_end = 480 + 37 + 2,
1367 .vtotal = 480 + 37 + 2 + 8,
1368 .vrefresh = 60,
1369};
1370
1371static const struct panel_desc foxlink_fl500wvr00_a0t = {
1372 .modes = &foxlink_fl500wvr00_a0t_mode,
1373 .num_modes = 1,
d7a839cd 1374 .bpc = 8,
102932b0
BB		 1375 .size = {
1376 .width = 108,
1377 .height = 65,
1378 },
bb276cb3 1379 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1380};
1381
3be20710
JT		 1382static const struct drm_display_mode friendlyarm_hd702e_mode = {
1383 .clock = 67185,
1384 .hdisplay = 800,
1385 .hsync_start = 800 + 20,
1386 .hsync_end = 800 + 20 + 24,
1387 .htotal = 800 + 20 + 24 + 20,
1388 .vdisplay = 1280,
1389 .vsync_start = 1280 + 4,
1390 .vsync_end = 1280 + 4 + 8,
1391 .vtotal = 1280 + 4 + 8 + 4,
1392 .vrefresh = 60,
1393 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1394};
1395
1396static const struct panel_desc friendlyarm_hd702e = {
1397 .modes = &friendlyarm_hd702e_mode,
1398 .num_modes = 1,
1399 .size = {
1400 .width = 94,
1401 .height = 151,
1402 },
1403};
1404
d435a2af
PZ		 1405static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1406 .clock = 9000,
1407 .hdisplay = 480,
1408 .hsync_start = 480 + 5,
1409 .hsync_end = 480 + 5 + 1,
1410 .htotal = 480 + 5 + 1 + 40,
1411 .vdisplay = 272,
1412 .vsync_start = 272 + 8,
1413 .vsync_end = 272 + 8 + 1,
1414 .vtotal = 272 + 8 + 1 + 8,
1415 .vrefresh = 60,
1416};
1417
1418static const struct panel_desc giantplus_gpg482739qs5 = {
1419 .modes = &giantplus_gpg482739qs5_mode,
1420 .num_modes = 1,
1421 .bpc = 8,
1422 .size = {
1423 .width = 95,
1424 .height = 54,
1425 },
33536a09 1426 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1427};
1428
2c6574a9
PC		 1429static const struct display_timing giantplus_gpm940b0_timing = {
1430 .pixelclock = { 13500000, 27000000, 27500000 },
1431 .hactive = { 320, 320, 320 },
1432 .hfront_porch = { 14, 686, 718 },
1433 .hback_porch = { 50, 70, 255 },
1434 .hsync_len = { 1, 1, 1 },
1435 .vactive = { 240, 240, 240 },
1436 .vfront_porch = { 1, 1, 179 },
1437 .vback_porch = { 1, 21, 31 },
1438 .vsync_len = { 1, 1, 6 },
1439 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1440};
1441
1442static const struct panel_desc giantplus_gpm940b0 = {
1443 .timings = &giantplus_gpm940b0_timing,
1444 .num_timings = 1,
1445 .bpc = 8,
1446 .size = {
1447 .width = 60,
1448 .height = 45,
1449 },
1450 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1451 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1452};
1453
ab07725a
PZ		 1454static const struct display_timing hannstar_hsd070pww1_timing = {
1455 .pixelclock = { 64300000, 71100000, 82000000 },
1456 .hactive = { 1280, 1280, 1280 },
1457 .hfront_porch = { 1, 1, 10 },
1458 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1459 /*
1460 * According to the data sheet, the minimum horizontal blanking interval
1461 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1462 * minimum working horizontal blanking interval to be 60 clocks.
1463 */
1464 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 1465 .vactive = { 800, 800, 800 },
1466 .vfront_porch = { 1, 1, 10 },
1467 .vback_porch = { 1, 1, 10 },
1468 .vsync_len = { 1, 21, 203 },
1469 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1470};
1471
1472static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1473 .timings = &hannstar_hsd070pww1_timing,
1474 .num_timings = 1,
a853205e
PZ		 1475 .bpc = 6,
1476 .size = {
1477 .width = 151,
1478 .height = 94,
1479 },
58d6a7bc 1480 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1481 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 1482};
1483
c0d607e5
EN		 1484static const struct display_timing hannstar_hsd100pxn1_timing = {
1485 .pixelclock = { 55000000, 65000000, 75000000 },
1486 .hactive = { 1024, 1024, 1024 },
1487 .hfront_porch = { 40, 40, 40 },
1488 .hback_porch = { 220, 220, 220 },
1489 .hsync_len = { 20, 60, 100 },
1490 .vactive = { 768, 768, 768 },
1491 .vfront_porch = { 7, 7, 7 },
1492 .vback_porch = { 21, 21, 21 },
1493 .vsync_len = { 10, 10, 10 },
1494 .flags = DISPLAY_FLAGS_DE_HIGH,
1495};
1496
1497static const struct panel_desc hannstar_hsd100pxn1 = {
1498 .timings = &hannstar_hsd100pxn1_timing,
1499 .num_timings = 1,
1500 .bpc = 6,
1501 .size = {
1502 .width = 203,
1503 .height = 152,
1504 },
4946b043 1505 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1506 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 1507};
1508
61ac0bf8
LS		 1509static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1510 .clock = 33333,
1511 .hdisplay = 800,
1512 .hsync_start = 800 + 85,
1513 .hsync_end = 800 + 85 + 86,
1514 .htotal = 800 + 85 + 86 + 85,
1515 .vdisplay = 480,
1516 .vsync_start = 480 + 16,
1517 .vsync_end = 480 + 16 + 13,
1518 .vtotal = 480 + 16 + 13 + 16,
1519 .vrefresh = 60,
1520};
1521
1522static const struct panel_desc hitachi_tx23d38vm0caa = {
1523 .modes = &hitachi_tx23d38vm0caa_mode,
1524 .num_modes = 1,
1525 .bpc = 6,
1526 .size = {
1527 .width = 195,
1528 .height = 117,
1529 },
6c684e3b
PZ		 1530 .delay = {
1531 .enable = 160,
1532 .disable = 160,
1533 },
61ac0bf8
LS		 1534};
1535
41bcceb4
NF		 1536static const struct drm_display_mode innolux_at043tn24_mode = {
1537 .clock = 9000,
1538 .hdisplay = 480,
1539 .hsync_start = 480 + 2,
1540 .hsync_end = 480 + 2 + 41,
1541 .htotal = 480 + 2 + 41 + 2,
1542 .vdisplay = 272,
1543 .vsync_start = 272 + 2,
a483159d
PZ		 1544 .vsync_end = 272 + 2 + 10,
1545 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 1546 .vrefresh = 60,
1547 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1548};
1549
1550static const struct panel_desc innolux_at043tn24 = {
1551 .modes = &innolux_at043tn24_mode,
1552 .num_modes = 1,
1553 .bpc = 8,
1554 .size = {
1555 .width = 95,
1556 .height = 54,
1557 },
1558 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1559 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 1560};
1561
4fc24ab3
RB		 1562static const struct drm_display_mode innolux_at070tn92_mode = {
1563 .clock = 33333,
1564 .hdisplay = 800,
1565 .hsync_start = 800 + 210,
1566 .hsync_end = 800 + 210 + 20,
1567 .htotal = 800 + 210 + 20 + 46,
1568 .vdisplay = 480,
1569 .vsync_start = 480 + 22,
1570 .vsync_end = 480 + 22 + 10,
1571 .vtotal = 480 + 22 + 23 + 10,
1572 .vrefresh = 60,
1573};
1574
1575static const struct panel_desc innolux_at070tn92 = {
1576 .modes = &innolux_at070tn92_mode,
1577 .num_modes = 1,
1578 .size = {
1579 .width = 154,
1580 .height = 86,
1581 },
1582 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1583};
1584
a5d2ade6
CF		 1585static const struct display_timing innolux_g070y2_l01_timing = {
1586 .pixelclock = { 28000000, 29500000, 32000000 },
1587 .hactive = { 800, 800, 800 },
1588 .hfront_porch = { 61, 91, 141 },
1589 .hback_porch = { 60, 90, 140 },
1590 .hsync_len = { 12, 12, 12 },
1591 .vactive = { 480, 480, 480 },
1592 .vfront_porch = { 4, 9, 30 },
1593 .vback_porch = { 4, 8, 28 },
1594 .vsync_len = { 2, 2, 2 },
1595 .flags = DISPLAY_FLAGS_DE_HIGH,
1596};
1597
1598static const struct panel_desc innolux_g070y2_l01 = {
1599 .timings = &innolux_g070y2_l01_timing,
1600 .num_timings = 1,
1601 .bpc = 6,
1602 .size = {
1603 .width = 152,
1604 .height = 91,
1605 },
1606 .delay = {
1607 .prepare = 10,
1608 .enable = 100,
1609 .disable = 100,
1610 .unprepare = 800,
1611 },
1612 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1613 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 1614};
1615
1e29b840
MO		 1616static const struct display_timing innolux_g101ice_l01_timing = {
1617 .pixelclock = { 60400000, 71100000, 74700000 },
1618 .hactive = { 1280, 1280, 1280 },
1619 .hfront_porch = { 41, 80, 100 },
1620 .hback_porch = { 40, 79, 99 },
1621 .hsync_len = { 1, 1, 1 },
1622 .vactive = { 800, 800, 800 },
1623 .vfront_porch = { 5, 11, 14 },
1624 .vback_porch = { 4, 11, 14 },
1625 .vsync_len = { 1, 1, 1 },
1626 .flags = DISPLAY_FLAGS_DE_HIGH,
1627};
1628
1629static const struct panel_desc innolux_g101ice_l01 = {
1630 .timings = &innolux_g101ice_l01_timing,
1631 .num_timings = 1,
1632 .bpc = 8,
1633 .size = {
1634 .width = 217,
1635 .height = 135,
1636 },
1637 .delay = {
1638 .enable = 200,
1639 .disable = 200,
1640 },
1641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1642 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 1643};
1644
4ae13e48
LS		 1645static const struct display_timing innolux_g121i1_l01_timing = {
1646 .pixelclock = { 67450000, 71000000, 74550000 },
1647 .hactive = { 1280, 1280, 1280 },
1648 .hfront_porch = { 40, 80, 160 },
1649 .hback_porch = { 39, 79, 159 },
1650 .hsync_len = { 1, 1, 1 },
1651 .vactive = { 800, 800, 800 },
1652 .vfront_porch = { 5, 11, 100 },
1653 .vback_porch = { 4, 11, 99 },
1654 .vsync_len = { 1, 1, 1 },
d731f661
LS		 1655};
1656
1657static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 1658 .timings = &innolux_g121i1_l01_timing,
1659 .num_timings = 1,
d731f661
LS		 1660 .bpc = 6,
1661 .size = {
1662 .width = 261,
1663 .height = 163,
1664 },
4ae13e48
LS		 1665 .delay = {
1666 .enable = 200,
1667 .disable = 20,
1668 },
1669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1670 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 1671};
1672
f8fa17ba
AB		 1673static const struct drm_display_mode innolux_g121x1_l03_mode = {
1674 .clock = 65000,
1675 .hdisplay = 1024,
1676 .hsync_start = 1024 + 0,
1677 .hsync_end = 1024 + 1,
1678 .htotal = 1024 + 0 + 1 + 320,
1679 .vdisplay = 768,
1680 .vsync_start = 768 + 38,
1681 .vsync_end = 768 + 38 + 1,
1682 .vtotal = 768 + 38 + 1 + 0,
1683 .vrefresh = 60,
2e8c5eb9 1684 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 1685};
1686
1687static const struct panel_desc innolux_g121x1_l03 = {
1688 .modes = &innolux_g121x1_l03_mode,
1689 .num_modes = 1,
1690 .bpc = 6,
1691 .size = {
1692 .width = 246,
1693 .height = 185,
1694 },
1695 .delay = {
1696 .enable = 200,
1697 .unprepare = 200,
1698 .disable = 400,
1699 },
1700};
1701
d719cbe9
DA		 1702/*
1703 * Datasheet specifies that at 60 Hz refresh rate:
1704 * - total horizontal time: { 1506, 1592, 1716 }
1705 * - total vertical time: { 788, 800, 868 }
1706 *
1707 * ...but doesn't go into exactly how that should be split into a front
1708 * porch, back porch, or sync length. For now we'll leave a single setting
1709 * here which allows a bit of tweaking of the pixel clock at the expense of
1710 * refresh rate.
1711 */
1712static const struct display_timing innolux_n116bge_timing = {
1713 .pixelclock = { 72600000, 76420000, 80240000 },
1714 .hactive = { 1366, 1366, 1366 },
1715 .hfront_porch = { 136, 136, 136 },
1716 .hback_porch = { 60, 60, 60 },
1717 .hsync_len = { 30, 30, 30 },
1718 .vactive = { 768, 768, 768 },
1719 .vfront_porch = { 8, 8, 8 },
1720 .vback_porch = { 12, 12, 12 },
1721 .vsync_len = { 12, 12, 12 },
1722 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
0a2288c0
TR		 1723};
1724
1725static const struct panel_desc innolux_n116bge = {
d719cbe9
DA		 1726 .timings = &innolux_n116bge_timing,
1727 .num_timings = 1,
0a2288c0
TR		 1728 .bpc = 6,
1729 .size = {
1730 .width = 256,
1731 .height = 144,
1732 },
1733};
1734
ea44739d
AB		 1735static const struct drm_display_mode innolux_n156bge_l21_mode = {
1736 .clock = 69300,
1737 .hdisplay = 1366,
1738 .hsync_start = 1366 + 16,
1739 .hsync_end = 1366 + 16 + 34,
1740 .htotal = 1366 + 16 + 34 + 50,
1741 .vdisplay = 768,
1742 .vsync_start = 768 + 2,
1743 .vsync_end = 768 + 2 + 6,
1744 .vtotal = 768 + 2 + 6 + 12,
1745 .vrefresh = 60,
1746};
1747
1748static const struct panel_desc innolux_n156bge_l21 = {
1749 .modes = &innolux_n156bge_l21_mode,
1750 .num_modes = 1,
0208d511 1751 .bpc = 6,
ea44739d
AB		 1752 .size = {
1753 .width = 344,
1754 .height = 193,
1755 },
1756};
1757
8f054b6f 1758static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 1759 .clock = 206016,
1760 .hdisplay = 2160,
1761 .hsync_start = 2160 + 48,
1762 .hsync_end = 2160 + 48 + 32,
1763 .htotal = 2160 + 48 + 32 + 80,
1764 .vdisplay = 1440,
1765 .vsync_start = 1440 + 3,
1766 .vsync_end = 1440 + 3 + 10,
1767 .vtotal = 1440 + 3 + 10 + 27,
1768 .vrefresh = 60,
1769 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1770};
1771
8f054b6f
DA		 1772static const struct panel_desc innolux_p120zdg_bf1 = {
1773 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 1774 .num_modes = 1,
1775 .bpc = 8,
1776 .size = {
8f054b6f
DA		 1777 .width = 254,
1778 .height = 169,
da50bd42 1779 },
22fd99e9 1780 .delay = {
625d3b5c 1781 .hpd_absent_delay = 200,
22fd99e9
SP		 1782 .unprepare = 500,
1783 },
da50bd42 1784};
1785
bccac3f1
MG		 1786static const struct drm_display_mode innolux_zj070na_01p_mode = {
1787 .clock = 51501,
1788 .hdisplay = 1024,
1789 .hsync_start = 1024 + 128,
1790 .hsync_end = 1024 + 128 + 64,
1791 .htotal = 1024 + 128 + 64 + 128,
1792 .vdisplay = 600,
1793 .vsync_start = 600 + 16,
1794 .vsync_end = 600 + 16 + 4,
1795 .vtotal = 600 + 16 + 4 + 16,
1796 .vrefresh = 60,
1797};
1798
1799static const struct panel_desc innolux_zj070na_01p = {
1800 .modes = &innolux_zj070na_01p_mode,
1801 .num_modes = 1,
1802 .bpc = 6,
1803 .size = {
81598846
TR		 1804 .width = 154,
1805 .height = 90,
bccac3f1
MG		 1806 },
1807};
1808
14bf60c4
LM		 1809static const struct display_timing koe_tx14d24vm1bpa_timing = {
1810 .pixelclock = { 5580000, 5850000, 6200000 },
1811 .hactive = { 320, 320, 320 },
1812 .hfront_porch = { 30, 30, 30 },
1813 .hback_porch = { 30, 30, 30 },
1814 .hsync_len = { 1, 5, 17 },
1815 .vactive = { 240, 240, 240 },
1816 .vfront_porch = { 6, 6, 6 },
1817 .vback_porch = { 5, 5, 5 },
1818 .vsync_len = { 1, 2, 11 },
1819 .flags = DISPLAY_FLAGS_DE_HIGH,
1820};
1821
1822static const struct panel_desc koe_tx14d24vm1bpa = {
1823 .timings = &koe_tx14d24vm1bpa_timing,
1824 .num_timings = 1,
1825 .bpc = 6,
1826 .size = {
1827 .width = 115,
1828 .height = 86,
1829 },
1830};
1831
8cfe8341
JT		 1832static const struct display_timing koe_tx31d200vm0baa_timing = {
1833 .pixelclock = { 39600000, 43200000, 48000000 },
1834 .hactive = { 1280, 1280, 1280 },
1835 .hfront_porch = { 16, 36, 56 },
1836 .hback_porch = { 16, 36, 56 },
1837 .hsync_len = { 8, 8, 8 },
1838 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 1839 .vfront_porch = { 6, 21, 33 },
1840 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 1841 .vsync_len = { 8, 8, 8 },
1842 .flags = DISPLAY_FLAGS_DE_HIGH,
1843};
1844
1845static const struct panel_desc koe_tx31d200vm0baa = {
1846 .timings = &koe_tx31d200vm0baa_timing,
1847 .num_timings = 1,
1848 .bpc = 6,
1849 .size = {
1850 .width = 292,
1851 .height = 109,
1852 },
1853 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1854 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 1855};
1856
8def22e5
LS		 1857static const struct display_timing kyo_tcg121xglp_timing = {
1858 .pixelclock = { 52000000, 65000000, 71000000 },
1859 .hactive = { 1024, 1024, 1024 },
1860 .hfront_porch = { 2, 2, 2 },
1861 .hback_porch = { 2, 2, 2 },
1862 .hsync_len = { 86, 124, 244 },
1863 .vactive = { 768, 768, 768 },
1864 .vfront_porch = { 2, 2, 2 },
1865 .vback_porch = { 2, 2, 2 },
1866 .vsync_len = { 6, 34, 73 },
1867 .flags = DISPLAY_FLAGS_DE_HIGH,
1868};
1869
1870static const struct panel_desc kyo_tcg121xglp = {
1871 .timings = &kyo_tcg121xglp_timing,
1872 .num_timings = 1,
1873 .bpc = 8,
1874 .size = {
1875 .width = 246,
1876 .height = 184,
1877 },
1878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1879 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 1880};
1881
27abdd83
PK		 1882static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1883 .clock = 7000,
1884 .hdisplay = 320,
1885 .hsync_start = 320 + 20,
1886 .hsync_end = 320 + 20 + 30,
1887 .htotal = 320 + 20 + 30 + 38,
1888 .vdisplay = 240,
1889 .vsync_start = 240 + 4,
1890 .vsync_end = 240 + 4 + 3,
1891 .vtotal = 240 + 4 + 3 + 15,
1892 .vrefresh = 60,
1893};
1894
1895static const struct panel_desc lemaker_bl035_rgb_002 = {
1896 .modes = &lemaker_bl035_rgb_002_mode,
1897 .num_modes = 1,
1898 .size = {
1899 .width = 70,
1900 .height = 52,
1901 },
1902 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1903 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1904};
1905
dd015002
HS		 1906static const struct drm_display_mode lg_lb070wv8_mode = {
1907 .clock = 33246,
1908 .hdisplay = 800,
1909 .hsync_start = 800 + 88,
1910 .hsync_end = 800 + 88 + 80,
1911 .htotal = 800 + 88 + 80 + 88,
1912 .vdisplay = 480,
1913 .vsync_start = 480 + 10,
1914 .vsync_end = 480 + 10 + 25,
1915 .vtotal = 480 + 10 + 25 + 10,
1916 .vrefresh = 60,
1917};
1918
1919static const struct panel_desc lg_lb070wv8 = {
1920 .modes = &lg_lb070wv8_mode,
1921 .num_modes = 1,
1922 .bpc = 16,
1923 .size = {
1924 .width = 151,
1925 .height = 91,
1926 },
1927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 1929};
1930
c5ece402
YY		 1931static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1932 .clock = 200000,
1933 .hdisplay = 1536,
1934 .hsync_start = 1536 + 12,
1935 .hsync_end = 1536 + 12 + 16,
1936 .htotal = 1536 + 12 + 16 + 48,
1937 .vdisplay = 2048,
1938 .vsync_start = 2048 + 8,
1939 .vsync_end = 2048 + 8 + 4,
1940 .vtotal = 2048 + 8 + 4 + 8,
1941 .vrefresh = 60,
1942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1943};
1944
1945static const struct panel_desc lg_lp079qx1_sp0v = {
1946 .modes = &lg_lp079qx1_sp0v_mode,
1947 .num_modes = 1,
1948 .size = {
1949 .width = 129,
1950 .height = 171,
1951 },
1952};
1953
0355dde2
YY		 1954static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1955 .clock = 205210,
1956 .hdisplay = 2048,
1957 .hsync_start = 2048 + 150,
1958 .hsync_end = 2048 + 150 + 5,
1959 .htotal = 2048 + 150 + 5 + 5,
1960 .vdisplay = 1536,
1961 .vsync_start = 1536 + 3,
1962 .vsync_end = 1536 + 3 + 1,
1963 .vtotal = 1536 + 3 + 1 + 9,
1964 .vrefresh = 60,
1965};
1966
1967static const struct panel_desc lg_lp097qx1_spa1 = {
1968 .modes = &lg_lp097qx1_spa1_mode,
1969 .num_modes = 1,
1970 .size = {
1971 .width = 208,
1972 .height = 147,
1973 },
1974};
1975
690d8fa7
JS		 1976static const struct drm_display_mode lg_lp120up1_mode = {
1977 .clock = 162300,
1978 .hdisplay = 1920,
1979 .hsync_start = 1920 + 40,
1980 .hsync_end = 1920 + 40 + 40,
1981 .htotal = 1920 + 40 + 40+ 80,
1982 .vdisplay = 1280,
1983 .vsync_start = 1280 + 4,
1984 .vsync_end = 1280 + 4 + 4,
1985 .vtotal = 1280 + 4 + 4 + 12,
1986 .vrefresh = 60,
1987};
1988
1989static const struct panel_desc lg_lp120up1 = {
1990 .modes = &lg_lp120up1_mode,
1991 .num_modes = 1,
1992 .bpc = 8,
1993 .size = {
1994 .width = 267,
1995 .height = 183,
1996 },
1997};
1998
ec7c5653
TR		 1999static const struct drm_display_mode lg_lp129qe_mode = {
2000 .clock = 285250,
2001 .hdisplay = 2560,
2002 .hsync_start = 2560 + 48,
2003 .hsync_end = 2560 + 48 + 32,
2004 .htotal = 2560 + 48 + 32 + 80,
2005 .vdisplay = 1700,
2006 .vsync_start = 1700 + 3,
2007 .vsync_end = 1700 + 3 + 10,
2008 .vtotal = 1700 + 3 + 10 + 36,
2009 .vrefresh = 60,
2010};
2011
2012static const struct panel_desc lg_lp129qe = {
2013 .modes = &lg_lp129qe_mode,
2014 .num_modes = 1,
0208d511 2015 .bpc = 8,
ec7c5653
TR		 2016 .size = {
2017 .width = 272,
2018 .height = 181,
2019 },
2020};
2021
65c766ca
LM		 2022static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2023 .clock = 30400,
2024 .hdisplay = 800,
2025 .hsync_start = 800 + 0,
2026 .hsync_end = 800 + 1,
2027 .htotal = 800 + 0 + 1 + 160,
2028 .vdisplay = 480,
2029 .vsync_start = 480 + 0,
2030 .vsync_end = 480 + 48 + 1,
2031 .vtotal = 480 + 48 + 1 + 0,
2032 .vrefresh = 60,
2033 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2034};
2035
0d35408a
AF		 2036static const struct drm_display_mode logicpd_type_28_mode = {
2037 .clock = 9000,
2038 .hdisplay = 480,
2039 .hsync_start = 480 + 3,
2040 .hsync_end = 480 + 3 + 42,
2041 .htotal = 480 + 3 + 42 + 2,
2042
2043 .vdisplay = 272,
2044 .vsync_start = 272 + 2,
2045 .vsync_end = 272 + 2 + 11,
2046 .vtotal = 272 + 2 + 11 + 3,
2047 .vrefresh = 60,
2048 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2049};
2050
2051static const struct panel_desc logicpd_type_28 = {
2052 .modes = &logicpd_type_28_mode,
2053 .num_modes = 1,
2054 .bpc = 8,
2055 .size = {
2056 .width = 105,
2057 .height = 67,
2058 },
2059 .delay = {
2060 .prepare = 200,
2061 .enable = 200,
2062 .unprepare = 200,
2063 .disable = 200,
2064 },
2065 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2066 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2067 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2068};
2069
65c766ca
LM		 2070static const struct panel_desc mitsubishi_aa070mc01 = {
2071 .modes = &mitsubishi_aa070mc01_mode,
2072 .num_modes = 1,
2073 .bpc = 8,
2074 .size = {
2075 .width = 152,
2076 .height = 91,
2077 },
2078
2079 .delay = {
2080 .enable = 200,
2081 .unprepare = 200,
2082 .disable = 400,
2083 },
2084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2085 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 2086 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2087};
2088
01bacc13
LS		 2089static const struct display_timing nec_nl12880bc20_05_timing = {
2090 .pixelclock = { 67000000, 71000000, 75000000 },
2091 .hactive = { 1280, 1280, 1280 },
2092 .hfront_porch = { 2, 30, 30 },
2093 .hback_porch = { 6, 100, 100 },
2094 .hsync_len = { 2, 30, 30 },
2095 .vactive = { 800, 800, 800 },
2096 .vfront_porch = { 5, 5, 5 },
2097 .vback_porch = { 11, 11, 11 },
2098 .vsync_len = { 7, 7, 7 },
2099};
2100
2101static const struct panel_desc nec_nl12880bc20_05 = {
2102 .timings = &nec_nl12880bc20_05_timing,
2103 .num_timings = 1,
2104 .bpc = 8,
2105 .size = {
2106 .width = 261,
2107 .height = 163,
2108 },
2109 .delay = {
2110 .enable = 50,
2111 .disable = 50,
2112 },
2113 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2114 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 2115};
2116
c6e87f91 2117static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2118 .clock = 10870,
2119 .hdisplay = 480,
2120 .hsync_start = 480 + 2,
2121 .hsync_end = 480 + 2 + 41,
2122 .htotal = 480 + 2 + 41 + 2,
2123 .vdisplay = 272,
2124 .vsync_start = 272 + 2,
2125 .vsync_end = 272 + 2 + 4,
2126 .vtotal = 272 + 2 + 4 + 2,
2127 .vrefresh = 74,
4bc390c6 2128 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 2129};
2130
2131static const struct panel_desc nec_nl4827hc19_05b = {
2132 .modes = &nec_nl4827hc19_05b_mode,
2133 .num_modes = 1,
2134 .bpc = 8,
2135 .size = {
2136 .width = 95,
2137 .height = 54,
2138 },
2c80661d 2139 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2140 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 2141};
2142
e6c2f066
MR		 2143static const struct drm_display_mode netron_dy_e231732_mode = {
2144 .clock = 66000,
2145 .hdisplay = 1024,
2146 .hsync_start = 1024 + 160,
2147 .hsync_end = 1024 + 160 + 70,
2148 .htotal = 1024 + 160 + 70 + 90,
2149 .vdisplay = 600,
2150 .vsync_start = 600 + 127,
2151 .vsync_end = 600 + 127 + 20,
2152 .vtotal = 600 + 127 + 20 + 3,
2153 .vrefresh = 60,
2154};
2155
2156static const struct panel_desc netron_dy_e231732 = {
2157 .modes = &netron_dy_e231732_mode,
2158 .num_modes = 1,
2159 .size = {
2160 .width = 154,
2161 .height = 87,
2162 },
2163 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2164};
2165
3b39ad7a
TV		 2166static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2167 .clock = 9000,
2168 .hdisplay = 480,
2169 .hsync_start = 480 + 2,
2170 .hsync_end = 480 + 2 + 41,
2171 .htotal = 480 + 2 + 41 + 2,
2172 .vdisplay = 272,
2173 .vsync_start = 272 + 2,
2174 .vsync_end = 272 + 2 + 10,
2175 .vtotal = 272 + 2 + 10 + 2,
2176 .vrefresh = 60,
2177 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2178};
2179
2180static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2181 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2182 .num_modes = 1,
2183 .bpc = 8,
2184 .size = {
2185 .width = 95,
2186 .height = 54,
2187 },
2188 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 2189 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2190 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3b39ad7a
TV		 2191};
2192
4177fa66
LS		 2193static const struct display_timing nlt_nl192108ac18_02d_timing = {
2194 .pixelclock = { 130000000, 148350000, 163000000 },
2195 .hactive = { 1920, 1920, 1920 },
2196 .hfront_porch = { 80, 100, 100 },
2197 .hback_porch = { 100, 120, 120 },
2198 .hsync_len = { 50, 60, 60 },
2199 .vactive = { 1080, 1080, 1080 },
2200 .vfront_porch = { 12, 30, 30 },
2201 .vback_porch = { 4, 10, 10 },
2202 .vsync_len = { 4, 5, 5 },
2203};
2204
2205static const struct panel_desc nlt_nl192108ac18_02d = {
2206 .timings = &nlt_nl192108ac18_02d_timing,
2207 .num_timings = 1,
2208 .bpc = 8,
2209 .size = {
2210 .width = 344,
2211 .height = 194,
2212 },
2213 .delay = {
2214 .unprepare = 500,
2215 },
2216 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2217 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 2218};
2219
05ec0e45
FL		 2220static const struct drm_display_mode nvd_9128_mode = {
2221 .clock = 29500,
2222 .hdisplay = 800,
2223 .hsync_start = 800 + 130,
2224 .hsync_end = 800 + 130 + 98,
2225 .htotal = 800 + 0 + 130 + 98,
2226 .vdisplay = 480,
2227 .vsync_start = 480 + 10,
2228 .vsync_end = 480 + 10 + 50,
2229 .vtotal = 480 + 0 + 10 + 50,
2230};
2231
2232static const struct panel_desc nvd_9128 = {
2233 .modes = &nvd_9128_mode,
2234 .num_modes = 1,
2235 .bpc = 8,
2236 .size = {
2237 .width = 156,
2238 .height = 88,
2239 },
2240 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2241 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 2242};
2243
a99fb626
GB		 2244static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2245 .pixelclock = { 30000000, 30000000, 40000000 },
2246 .hactive = { 800, 800, 800 },
2247 .hfront_porch = { 40, 40, 40 },
2248 .hback_porch = { 40, 40, 40 },
2249 .hsync_len = { 1, 48, 48 },
2250 .vactive = { 480, 480, 480 },
2251 .vfront_porch = { 13, 13, 13 },
2252 .vback_porch = { 29, 29, 29 },
2253 .vsync_len = { 3, 3, 3 },
2254 .flags = DISPLAY_FLAGS_DE_HIGH,
2255};
2256
2257static const struct panel_desc okaya_rs800480t_7x0gp = {
2258 .timings = &okaya_rs800480t_7x0gp_timing,
2259 .num_timings = 1,
2260 .bpc = 6,
2261 .size = {
2262 .width = 154,
2263 .height = 87,
2264 },
2265 .delay = {
2266 .prepare = 41,
2267 .enable = 50,
2268 .unprepare = 41,
2269 .disable = 50,
2270 },
2271 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2272};
2273
cf5c9e6d
MR		 2274static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2275 .clock = 9000,
2276 .hdisplay = 480,
2277 .hsync_start = 480 + 5,
2278 .hsync_end = 480 + 5 + 30,
2279 .htotal = 480 + 5 + 30 + 10,
2280 .vdisplay = 272,
2281 .vsync_start = 272 + 8,
2282 .vsync_end = 272 + 8 + 5,
2283 .vtotal = 272 + 8 + 5 + 3,
2284 .vrefresh = 60,
2285};
2286
2287static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2288 .modes = &olimex_lcd_olinuxino_43ts_mode,
2289 .num_modes = 1,
2290 .size = {
30c6d7ab
JL		 2291 .width = 95,
2292 .height = 54,
cf5c9e6d 2293 },
5c2a7c6b 2294 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 2295};
2296
e8b6f561
EA		 2297/*
2298 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2299 * pixel clocks, but this is the timing that was being used in the Adafruit
2300 * installation instructions.
2301 */
2302static const struct drm_display_mode ontat_yx700wv03_mode = {
2303 .clock = 29500,
2304 .hdisplay = 800,
2305 .hsync_start = 824,
2306 .hsync_end = 896,
2307 .htotal = 992,
2308 .vdisplay = 480,
2309 .vsync_start = 483,
2310 .vsync_end = 493,
2311 .vtotal = 500,
2312 .vrefresh = 60,
2313 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2314};
2315
2316/*
2317 * Specification at:
2318 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2319 */
2320static const struct panel_desc ontat_yx700wv03 = {
2321 .modes = &ontat_yx700wv03_mode,
2322 .num_modes = 1,
2323 .bpc = 8,
2324 .size = {
2325 .width = 154,
2326 .height = 83,
2327 },
5651e5e0 2328 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 2329};
2330
9c31dcb6
NS		 2331static const struct drm_display_mode ortustech_com37h3m_mode = {
2332 .clock = 22153,
2333 .hdisplay = 480,
2334 .hsync_start = 480 + 8,
2335 .hsync_end = 480 + 8 + 10,
2336 .htotal = 480 + 8 + 10 + 10,
2337 .vdisplay = 640,
2338 .vsync_start = 640 + 4,
2339 .vsync_end = 640 + 4 + 3,
2340 .vtotal = 640 + 4 + 3 + 4,
2341 .vrefresh = 60,
2342 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2343};
2344
2345static const struct panel_desc ortustech_com37h3m = {
2346 .modes = &ortustech_com37h3m_mode,
2347 .num_modes = 1,
2348 .bpc = 8,
2349 .size = {
2350 .width = 56, /* 56.16mm */
2351 .height = 75, /* 74.88mm */
2352 },
2353 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2354 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2355 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2356};
2357
725c9d40
PZ		 2358static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2359 .clock = 25000,
2360 .hdisplay = 480,
2361 .hsync_start = 480 + 10,
2362 .hsync_end = 480 + 10 + 10,
2363 .htotal = 480 + 10 + 10 + 15,
2364 .vdisplay = 800,
2365 .vsync_start = 800 + 3,
2366 .vsync_end = 800 + 3 + 3,
2367 .vtotal = 800 + 3 + 3 + 3,
2368 .vrefresh = 60,
2369};
2370
2371static const struct panel_desc ortustech_com43h4m85ulc = {
2372 .modes = &ortustech_com43h4m85ulc_mode,
2373 .num_modes = 1,
2374 .bpc = 8,
2375 .size = {
2376 .width = 56,
2377 .height = 93,
2378 },
2379 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2380 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
725c9d40
PZ		 2381};
2382
163f7a35
LP		 2383static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2384 .clock = 33000,
2385 .hdisplay = 800,
2386 .hsync_start = 800 + 210,
2387 .hsync_end = 800 + 210 + 30,
2388 .htotal = 800 + 210 + 30 + 16,
2389 .vdisplay = 480,
2390 .vsync_start = 480 + 22,
2391 .vsync_end = 480 + 22 + 13,
2392 .vtotal = 480 + 22 + 13 + 10,
2393 .vrefresh = 60,
2394 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2395};
2396
2397static const struct panel_desc osddisplays_osd070t1718_19ts = {
2398 .modes = &osddisplays_osd070t1718_19ts_mode,
2399 .num_modes = 1,
2400 .bpc = 8,
2401 .size = {
2402 .width = 152,
2403 .height = 91,
2404 },
2405 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2406 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
a793f0ee 2407 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 2408};
2409
4ba3e563
EH		 2410static const struct drm_display_mode pda_91_00156_a0_mode = {
2411 .clock = 33300,
2412 .hdisplay = 800,
2413 .hsync_start = 800 + 1,
2414 .hsync_end = 800 + 1 + 64,
2415 .htotal = 800 + 1 + 64 + 64,
2416 .vdisplay = 480,
2417 .vsync_start = 480 + 1,
2418 .vsync_end = 480 + 1 + 23,
2419 .vtotal = 480 + 1 + 23 + 22,
2420 .vrefresh = 60,
2421};
2422
2423static const struct panel_desc pda_91_00156_a0 = {
2424 .modes = &pda_91_00156_a0_mode,
2425 .num_modes = 1,
2426 .size = {
2427 .width = 152,
2428 .height = 91,
2429 },
2430 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2431};
2432
2433
d2a6f0f5
JW		 2434static const struct drm_display_mode qd43003c0_40_mode = {
2435 .clock = 9000,
2436 .hdisplay = 480,
2437 .hsync_start = 480 + 8,
2438 .hsync_end = 480 + 8 + 4,
2439 .htotal = 480 + 8 + 4 + 39,
2440 .vdisplay = 272,
2441 .vsync_start = 272 + 4,
2442 .vsync_end = 272 + 4 + 10,
2443 .vtotal = 272 + 4 + 10 + 2,
2444 .vrefresh = 60,
2445};
2446
2447static const struct panel_desc qd43003c0_40 = {
2448 .modes = &qd43003c0_40_mode,
2449 .num_modes = 1,
2450 .bpc = 8,
2451 .size = {
2452 .width = 95,
2453 .height = 53,
2454 },
2455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2456};
2457
23167fa9
JT		 2458static const struct display_timing rocktech_rk070er9427_timing = {
2459 .pixelclock = { 26400000, 33300000, 46800000 },
2460 .hactive = { 800, 800, 800 },
2461 .hfront_porch = { 16, 210, 354 },
2462 .hback_porch = { 46, 46, 46 },
2463 .hsync_len = { 1, 1, 1 },
2464 .vactive = { 480, 480, 480 },
2465 .vfront_porch = { 7, 22, 147 },
2466 .vback_porch = { 23, 23, 23 },
2467 .vsync_len = { 1, 1, 1 },
2468 .flags = DISPLAY_FLAGS_DE_HIGH,
2469};
2470
2471static const struct panel_desc rocktech_rk070er9427 = {
2472 .timings = &rocktech_rk070er9427_timing,
2473 .num_timings = 1,
2474 .bpc = 6,
2475 .size = {
2476 .width = 154,
2477 .height = 86,
2478 },
2479 .delay = {
2480 .prepare = 41,
2481 .enable = 50,
2482 .unprepare = 41,
2483 .disable = 50,
2484 },
2485 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2486};
2487
0330eaf3
YY		 2488static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2489 .clock = 271560,
2490 .hdisplay = 2560,
2491 .hsync_start = 2560 + 48,
2492 .hsync_end = 2560 + 48 + 32,
2493 .htotal = 2560 + 48 + 32 + 80,
2494 .vdisplay = 1600,
2495 .vsync_start = 1600 + 2,
2496 .vsync_end = 1600 + 2 + 5,
2497 .vtotal = 1600 + 2 + 5 + 57,
2498 .vrefresh = 60,
2499};
2500
2501static const struct panel_desc samsung_lsn122dl01_c01 = {
2502 .modes = &samsung_lsn122dl01_c01_mode,
2503 .num_modes = 1,
2504 .size = {
2505 .width = 263,
2506 .height = 164,
2507 },
2508};
2509
6d54e3d2
MD		 2510static const struct drm_display_mode samsung_ltn101nt05_mode = {
2511 .clock = 54030,
2512 .hdisplay = 1024,
2513 .hsync_start = 1024 + 24,
2514 .hsync_end = 1024 + 24 + 136,
2515 .htotal = 1024 + 24 + 136 + 160,
2516 .vdisplay = 600,
2517 .vsync_start = 600 + 3,
2518 .vsync_end = 600 + 3 + 6,
2519 .vtotal = 600 + 3 + 6 + 61,
2520 .vrefresh = 60,
2521};
2522
2523static const struct panel_desc samsung_ltn101nt05 = {
2524 .modes = &samsung_ltn101nt05_mode,
2525 .num_modes = 1,
0208d511 2526 .bpc = 6,
6d54e3d2 2527 .size = {
81598846
TR		 2528 .width = 223,
2529 .height = 125,
6d54e3d2
MD		 2530 },
2531};
2532
0c934306
SM		 2533static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2534 .clock = 76300,
2535 .hdisplay = 1366,
2536 .hsync_start = 1366 + 64,
2537 .hsync_end = 1366 + 64 + 48,
2538 .htotal = 1366 + 64 + 48 + 128,
2539 .vdisplay = 768,
2540 .vsync_start = 768 + 2,
2541 .vsync_end = 768 + 2 + 5,
2542 .vtotal = 768 + 2 + 5 + 17,
2543 .vrefresh = 60,
2544};
2545
2546static const struct panel_desc samsung_ltn140at29_301 = {
2547 .modes = &samsung_ltn140at29_301_mode,
2548 .num_modes = 1,
2549 .bpc = 6,
2550 .size = {
2551 .width = 320,
2552 .height = 187,
2553 },
2554};
2555
cd5e1cbe
JH		 2556static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2557 .clock = 168480,
2558 .hdisplay = 1920,
2559 .hsync_start = 1920 + 48,
2560 .hsync_end = 1920 + 48 + 32,
2561 .htotal = 1920 + 48 + 32 + 80,
2562 .vdisplay = 1280,
2563 .vsync_start = 1280 + 3,
2564 .vsync_end = 1280 + 3 + 10,
2565 .vtotal = 1280 + 3 + 10 + 57,
2566 .vrefresh = 60,
2567 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2568};
2569
2570static const struct panel_desc sharp_ld_d5116z01b = {
2571 .modes = &sharp_ld_d5116z01b_mode,
2572 .num_modes = 1,
2573 .bpc = 8,
2574 .size = {
2575 .width = 260,
2576 .height = 120,
2577 },
2578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2579 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2580};
2581
dda0e4bd
NS		 2582static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2583 .clock = 33260,
2584 .hdisplay = 800,
2585 .hsync_start = 800 + 64,
2586 .hsync_end = 800 + 64 + 128,
2587 .htotal = 800 + 64 + 128 + 64,
2588 .vdisplay = 480,
2589 .vsync_start = 480 + 8,
2590 .vsync_end = 480 + 8 + 2,
2591 .vtotal = 480 + 8 + 2 + 35,
2592 .vrefresh = 60,
2593 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2594};
2595
2596static const struct panel_desc sharp_lq070y3dg3b = {
2597 .modes = &sharp_lq070y3dg3b_mode,
2598 .num_modes = 1,
2599 .bpc = 8,
2600 .size = {
2601 .width = 152, /* 152.4mm */
2602 .height = 91, /* 91.4mm */
2603 },
2604 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2605 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2606 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2607};
2608
03e3ec9a
VZ		 2609static const struct drm_display_mode sharp_lq035q7db03_mode = {
2610 .clock = 5500,
2611 .hdisplay = 240,
2612 .hsync_start = 240 + 16,
2613 .hsync_end = 240 + 16 + 7,
2614 .htotal = 240 + 16 + 7 + 5,
2615 .vdisplay = 320,
2616 .vsync_start = 320 + 9,
2617 .vsync_end = 320 + 9 + 1,
2618 .vtotal = 320 + 9 + 1 + 7,
2619 .vrefresh = 60,
2620};
2621
2622static const struct panel_desc sharp_lq035q7db03 = {
2623 .modes = &sharp_lq035q7db03_mode,
2624 .num_modes = 1,
2625 .bpc = 6,
2626 .size = {
2627 .width = 54,
2628 .height = 72,
2629 },
2630 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2631};
2632
592aa02b
JC		 2633static const struct display_timing sharp_lq101k1ly04_timing = {
2634 .pixelclock = { 60000000, 65000000, 80000000 },
2635 .hactive = { 1280, 1280, 1280 },
2636 .hfront_porch = { 20, 20, 20 },
2637 .hback_porch = { 20, 20, 20 },
2638 .hsync_len = { 10, 10, 10 },
2639 .vactive = { 800, 800, 800 },
2640 .vfront_porch = { 4, 4, 4 },
2641 .vback_porch = { 4, 4, 4 },
2642 .vsync_len = { 4, 4, 4 },
2643 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2644};
2645
2646static const struct panel_desc sharp_lq101k1ly04 = {
2647 .timings = &sharp_lq101k1ly04_timing,
2648 .num_timings = 1,
2649 .bpc = 8,
2650 .size = {
2651 .width = 217,
2652 .height = 136,
2653 },
2654 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 2655 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 2656};
2657
9f7bae2d
SP		 2658static const struct display_timing sharp_lq123p1jx31_timing = {
2659 .pixelclock = { 252750000, 252750000, 266604720 },
2660 .hactive = { 2400, 2400, 2400 },
2661 .hfront_porch = { 48, 48, 48 },
2662 .hback_porch = { 80, 80, 84 },
2663 .hsync_len = { 32, 32, 32 },
2664 .vactive = { 1600, 1600, 1600 },
2665 .vfront_porch = { 3, 3, 3 },
2666 .vback_porch = { 33, 33, 120 },
2667 .vsync_len = { 10, 10, 10 },
2668 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 2669};
2670
2671static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 2672 .timings = &sharp_lq123p1jx31_timing,
2673 .num_timings = 1,
5466a631 2674 .bpc = 8,
739c7de9
YY		 2675 .size = {
2676 .width = 259,
2677 .height = 173,
2678 },
a42f6e3f
YY		 2679 .delay = {
2680 .prepare = 110,
2681 .enable = 50,
2682 .unprepare = 550,
2683 },
739c7de9
YY		 2684};
2685
0f9cdd74
GL		 2686static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2687 .clock = 71100,
2688 .hdisplay = 1024,
2689 .hsync_start = 1024 + 168,
2690 .hsync_end = 1024 + 168 + 64,
2691 .htotal = 1024 + 168 + 64 + 88,
2692 .vdisplay = 768,
2693 .vsync_start = 768 + 37,
2694 .vsync_end = 768 + 37 + 2,
2695 .vtotal = 768 + 37 + 2 + 8,
2696 .vrefresh = 60,
2697};
2698
2699static const struct panel_desc sharp_lq150x1lg11 = {
2700 .modes = &sharp_lq150x1lg11_mode,
2701 .num_modes = 1,
2702 .bpc = 6,
2703 .size = {
2704 .width = 304,
2705 .height = 228,
2706 },
2707 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2708};
2709
f1bd37f3
PC		 2710static const struct display_timing sharp_ls020b1dd01d_timing = {
2711 .pixelclock = { 2000000, 4200000, 5000000 },
2712 .hactive = { 240, 240, 240 },
2713 .hfront_porch = { 66, 66, 66 },
2714 .hback_porch = { 1, 1, 1 },
2715 .hsync_len = { 1, 1, 1 },
2716 .vactive = { 160, 160, 160 },
2717 .vfront_porch = { 52, 52, 52 },
2718 .vback_porch = { 6, 6, 6 },
2719 .vsync_len = { 10, 10, 10 },
2720 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2721};
2722
2723static const struct panel_desc sharp_ls020b1dd01d = {
2724 .timings = &sharp_ls020b1dd01d_timing,
2725 .num_timings = 1,
2726 .bpc = 6,
2727 .size = {
2728 .width = 42,
2729 .height = 28,
2730 },
2731 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2732 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2733 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2734 | DRM_BUS_FLAG_SHARP_SIGNALS,
2735};
2736
9c6615bc
BB		 2737static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2738 .clock = 33300,
2739 .hdisplay = 800,
2740 .hsync_start = 800 + 1,
2741 .hsync_end = 800 + 1 + 64,
2742 .htotal = 800 + 1 + 64 + 64,
2743 .vdisplay = 480,
2744 .vsync_start = 480 + 1,
2745 .vsync_end = 480 + 1 + 23,
2746 .vtotal = 480 + 1 + 23 + 22,
2747 .vrefresh = 60,
2748};
2749
2750static const struct panel_desc shelly_sca07010_bfn_lnn = {
2751 .modes = &shelly_sca07010_bfn_lnn_mode,
2752 .num_modes = 1,
2753 .size = {
2754 .width = 152,
2755 .height = 91,
2756 },
2757 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2758};
2759
9bb34c4c
DA		 2760static const struct drm_display_mode starry_kr122ea0sra_mode = {
2761 .clock = 147000,
2762 .hdisplay = 1920,
2763 .hsync_start = 1920 + 16,
2764 .hsync_end = 1920 + 16 + 16,
2765 .htotal = 1920 + 16 + 16 + 32,
2766 .vdisplay = 1200,
2767 .vsync_start = 1200 + 15,
2768 .vsync_end = 1200 + 15 + 2,
2769 .vtotal = 1200 + 15 + 2 + 18,
2770 .vrefresh = 60,
2771 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2772};
2773
2774static const struct panel_desc starry_kr122ea0sra = {
2775 .modes = &starry_kr122ea0sra_mode,
2776 .num_modes = 1,
2777 .size = {
2778 .width = 263,
2779 .height = 164,
2780 },
c46b924b
BN		 2781 .delay = {
2782 .prepare = 10 + 200,
2783 .enable = 50,
2784 .unprepare = 10 + 500,
2785 },
9bb34c4c
DA		 2786};
2787
42161531
JS		 2788static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2789 .clock = 30000,
2790 .hdisplay = 800,
2791 .hsync_start = 800 + 39,
2792 .hsync_end = 800 + 39 + 47,
2793 .htotal = 800 + 39 + 47 + 39,
2794 .vdisplay = 480,
2795 .vsync_start = 480 + 13,
2796 .vsync_end = 480 + 13 + 2,
2797 .vtotal = 480 + 13 + 2 + 29,
2798 .vrefresh = 62,
2799};
2800
2801static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2802 .modes = &tfc_s9700rtwv43tr_01b_mode,
2803 .num_modes = 1,
2804 .bpc = 8,
2805 .size = {
2806 .width = 155,
2807 .height = 90,
2808 },
2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2810 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2811};
2812
adb973ef
GB		 2813static const struct display_timing tianma_tm070jdhg30_timing = {
2814 .pixelclock = { 62600000, 68200000, 78100000 },
2815 .hactive = { 1280, 1280, 1280 },
2816 .hfront_porch = { 15, 64, 159 },
2817 .hback_porch = { 5, 5, 5 },
2818 .hsync_len = { 1, 1, 256 },
2819 .vactive = { 800, 800, 800 },
2820 .vfront_porch = { 3, 40, 99 },
2821 .vback_porch = { 2, 2, 2 },
2822 .vsync_len = { 1, 1, 128 },
2823 .flags = DISPLAY_FLAGS_DE_HIGH,
2824};
2825
2826static const struct panel_desc tianma_tm070jdhg30 = {
2827 .timings = &tianma_tm070jdhg30_timing,
2828 .num_timings = 1,
2829 .bpc = 8,
2830 .size = {
2831 .width = 151,
2832 .height = 95,
2833 },
2834 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2835 .connector_type = DRM_MODE_CONNECTOR_LVDS,
adb973ef
GB		 2836};
2837
870a0b12
LM		 2838static const struct display_timing tianma_tm070rvhg71_timing = {
2839 .pixelclock = { 27700000, 29200000, 39600000 },
2840 .hactive = { 800, 800, 800 },
2841 .hfront_porch = { 12, 40, 212 },
2842 .hback_porch = { 88, 88, 88 },
2843 .hsync_len = { 1, 1, 40 },
2844 .vactive = { 480, 480, 480 },
2845 .vfront_porch = { 1, 13, 88 },
2846 .vback_porch = { 32, 32, 32 },
2847 .vsync_len = { 1, 1, 3 },
2848 .flags = DISPLAY_FLAGS_DE_HIGH,
2849};
2850
2851static const struct panel_desc tianma_tm070rvhg71 = {
2852 .timings = &tianma_tm070rvhg71_timing,
2853 .num_timings = 1,
2854 .bpc = 8,
2855 .size = {
2856 .width = 154,
2857 .height = 86,
2858 },
2859 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2860 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 2861};
2862
d8a0d6a3
LW		 2863static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2864 {
2865 .clock = 10000,
2866 .hdisplay = 320,
2867 .hsync_start = 320 + 50,
2868 .hsync_end = 320 + 50 + 6,
2869 .htotal = 320 + 50 + 6 + 38,
2870 .vdisplay = 240,
2871 .vsync_start = 240 + 3,
2872 .vsync_end = 240 + 3 + 1,
2873 .vtotal = 240 + 3 + 1 + 17,
2874 .vrefresh = 60,
2875 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2876 },
2877};
2878
2879static const struct panel_desc ti_nspire_cx_lcd_panel = {
2880 .modes = ti_nspire_cx_lcd_mode,
2881 .num_modes = 1,
2882 .bpc = 8,
2883 .size = {
2884 .width = 65,
2885 .height = 49,
2886 },
2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2888 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2889};
2890
2891static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2892 {
2893 .clock = 10000,
2894 .hdisplay = 320,
2895 .hsync_start = 320 + 6,
2896 .hsync_end = 320 + 6 + 6,
2897 .htotal = 320 + 6 + 6 + 6,
2898 .vdisplay = 240,
2899 .vsync_start = 240 + 0,
2900 .vsync_end = 240 + 0 + 1,
2901 .vtotal = 240 + 0 + 1 + 0,
2902 .vrefresh = 60,
2903 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2904 },
2905};
2906
2907static const struct panel_desc ti_nspire_classic_lcd_panel = {
2908 .modes = ti_nspire_classic_lcd_mode,
2909 .num_modes = 1,
2910 /* The grayscale panel has 8 bit for the color .. Y (black) */
2911 .bpc = 8,
2912 .size = {
2913 .width = 71,
2914 .height = 53,
2915 },
2916 /* This is the grayscale bus format */
2917 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2918 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2919};
2920
06e733e4
LS		 2921static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2922 .clock = 79500,
2923 .hdisplay = 1280,
2924 .hsync_start = 1280 + 192,
2925 .hsync_end = 1280 + 192 + 128,
2926 .htotal = 1280 + 192 + 128 + 64,
2927 .vdisplay = 768,
2928 .vsync_start = 768 + 20,
2929 .vsync_end = 768 + 20 + 7,
2930 .vtotal = 768 + 20 + 7 + 3,
2931 .vrefresh = 60,
2932};
2933
2934static const struct panel_desc toshiba_lt089ac29000 = {
2935 .modes = &toshiba_lt089ac29000_mode,
2936 .num_modes = 1,
2937 .size = {
2938 .width = 194,
2939 .height = 116,
2940 },
2941 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2942 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
9a2654c0 2943 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 2944};
2945
227e4f40
BD		 2946static const struct drm_display_mode tpk_f07a_0102_mode = {
2947 .clock = 33260,
2948 .hdisplay = 800,
2949 .hsync_start = 800 + 40,
2950 .hsync_end = 800 + 40 + 128,
2951 .htotal = 800 + 40 + 128 + 88,
2952 .vdisplay = 480,
2953 .vsync_start = 480 + 10,
2954 .vsync_end = 480 + 10 + 2,
2955 .vtotal = 480 + 10 + 2 + 33,
2956 .vrefresh = 60,
2957};
2958
2959static const struct panel_desc tpk_f07a_0102 = {
2960 .modes = &tpk_f07a_0102_mode,
2961 .num_modes = 1,
2962 .size = {
2963 .width = 152,
2964 .height = 91,
2965 },
88bc4178 2966 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 2967};
2968
2969static const struct drm_display_mode tpk_f10a_0102_mode = {
2970 .clock = 45000,
2971 .hdisplay = 1024,
2972 .hsync_start = 1024 + 176,
2973 .hsync_end = 1024 + 176 + 5,
2974 .htotal = 1024 + 176 + 5 + 88,
2975 .vdisplay = 600,
2976 .vsync_start = 600 + 20,
2977 .vsync_end = 600 + 20 + 5,
2978 .vtotal = 600 + 20 + 5 + 25,
2979 .vrefresh = 60,
2980};
2981
2982static const struct panel_desc tpk_f10a_0102 = {
2983 .modes = &tpk_f10a_0102_mode,
2984 .num_modes = 1,
2985 .size = {
2986 .width = 223,
2987 .height = 125,
2988 },
2989};
2990
06a9dc65
MS		 2991static const struct display_timing urt_umsh_8596md_timing = {
2992 .pixelclock = { 33260000, 33260000, 33260000 },
2993 .hactive = { 800, 800, 800 },
2994 .hfront_porch = { 41, 41, 41 },
2995 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2996 .hsync_len = { 71, 128, 128 },
2997 .vactive = { 480, 480, 480 },
2998 .vfront_porch = { 10, 10, 10 },
2999 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3000 .vsync_len = { 2, 2, 2 },
3001 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3002 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3003};
3004
3005static const struct panel_desc urt_umsh_8596md_lvds = {
3006 .timings = &urt_umsh_8596md_timing,
3007 .num_timings = 1,
3008 .bpc = 6,
3009 .size = {
3010 .width = 152,
3011 .height = 91,
3012 },
3013 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 3014 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 3015};
3016
3017static const struct panel_desc urt_umsh_8596md_parallel = {
3018 .timings = &urt_umsh_8596md_timing,
3019 .num_timings = 1,
3020 .bpc = 6,
3021 .size = {
3022 .width = 152,
3023 .height = 91,
3024 },
3025 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3026};
3027
04206185
FE		 3028static const struct drm_display_mode vl050_8048nt_c01_mode = {
3029 .clock = 33333,
3030 .hdisplay = 800,
3031 .hsync_start = 800 + 210,
3032 .hsync_end = 800 + 210 + 20,
3033 .htotal = 800 + 210 + 20 + 46,
3034 .vdisplay = 480,
3035 .vsync_start = 480 + 22,
3036 .vsync_end = 480 + 22 + 10,
3037 .vtotal = 480 + 22 + 10 + 23,
3038 .vrefresh = 60,
3039 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3040};
3041
3042static const struct panel_desc vl050_8048nt_c01 = {
3043 .modes = &vl050_8048nt_c01_mode,
3044 .num_modes = 1,
3045 .bpc = 8,
3046 .size = {
3047 .width = 120,
3048 .height = 76,
3049 },
3050 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3051 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3052};
3053
e4bac408
RG		 3054static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3055 .clock = 6410,
3056 .hdisplay = 320,
3057 .hsync_start = 320 + 20,
3058 .hsync_end = 320 + 20 + 30,
3059 .htotal = 320 + 20 + 30 + 38,
3060 .vdisplay = 240,
3061 .vsync_start = 240 + 4,
3062 .vsync_end = 240 + 4 + 3,
3063 .vtotal = 240 + 4 + 3 + 15,
3064 .vrefresh = 60,
3065 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3066};
3067
3068static const struct panel_desc winstar_wf35ltiacd = {
3069 .modes = &winstar_wf35ltiacd_mode,
3070 .num_modes = 1,
3071 .bpc = 8,
3072 .size = {
3073 .width = 70,
3074 .height = 53,
3075 },
3076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3077};
3078
fcec4163
LW		 3079static const struct drm_display_mode arm_rtsm_mode[] = {
3080 {
3081 .clock = 65000,
3082 .hdisplay = 1024,
3083 .hsync_start = 1024 + 24,
3084 .hsync_end = 1024 + 24 + 136,
3085 .htotal = 1024 + 24 + 136 + 160,
3086 .vdisplay = 768,
3087 .vsync_start = 768 + 3,
3088 .vsync_end = 768 + 3 + 6,
3089 .vtotal = 768 + 3 + 6 + 29,
3090 .vrefresh = 60,
3091 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3092 },
3093};
3094
3095static const struct panel_desc arm_rtsm = {
3096 .modes = arm_rtsm_mode,
3097 .num_modes = 1,
3098 .bpc = 8,
3099 .size = {
3100 .width = 400,
3101 .height = 300,
3102 },
3103 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3104};
3105
280921de
TR		 3106static const struct of_device_id platform_of_match[] = {
3107 {
966fea78
YF		 3108 .compatible = "ampire,am-480272h3tmqw-t01h",
3109 .data = &ampire_am_480272h3tmqw_t01h,
3110 }, {
1c550fa1
PZ		 3111 .compatible = "ampire,am800480r3tmqwa1h",
3112 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 3113 }, {
3114 .compatible = "arm,rtsm-display",
3115 .data = &arm_rtsm,
c479450f
SS		 3116 }, {
3117 .compatible = "armadeus,st0700-adapt",
3118 .data = &armadeus_st0700_adapt,
1c550fa1 3119 }, {
280921de
TR		 3120 .compatible = "auo,b101aw03",
3121 .data = &auo_b101aw03,
a531bc3d
HL		 3122 }, {
3123 .compatible = "auo,b101ean01",
3124 .data = &auo_b101ean01,
dac746e0
RC		 3125 }, {
3126 .compatible = "auo,b101xtn01",
3127 .data = &auo_b101xtn01,
e35e305e
AK		 3128 }, {
3129 .compatible = "auo,b116xw03",
3130 .data = &auo_b116xw03,
3e51d609
AK		 3131 }, {
3132 .compatible = "auo,b133htn01",
3133 .data = &auo_b133htn01,
a333f7ad
SM		 3134 }, {
3135 .compatible = "auo,b133xtn01",
3136 .data = &auo_b133xtn01,
bccfaffb
LM		 3137 }, {
3138 .compatible = "auo,g070vvn01",
3139 .data = &auo_g070vvn01,
4fb86404
AG		 3140 }, {
3141 .compatible = "auo,g101evn010",
3142 .data = &auo_g101evn010,
4451c287
CF		 3143 }, {
3144 .compatible = "auo,g104sn02",
3145 .data = &auo_g104sn02,
697035c6
LS		 3146 }, {
3147 .compatible = "auo,g133han01",
3148 .data = &auo_g133han01,
8c31f603
LS		 3149 }, {
3150 .compatible = "auo,g185han01",
3151 .data = &auo_g185han01,
70c0d5b7
LS		 3152 }, {
3153 .compatible = "auo,p320hvn03",
3154 .data = &auo_p320hvn03,
7ee933a1
HS		 3155 }, {
3156 .compatible = "auo,t215hvn01",
3157 .data = &auo_t215hvn01,
d47df633
PZ		 3158 }, {
3159 .compatible = "avic,tm070ddh03",
3160 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 3161 }, {
3162 .compatible = "bananapi,s070wv20-ct16",
3163 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 3164 }, {
3165 .compatible = "boe,hv070wsa-100",
3166 .data = &boe_hv070wsa
cac1a411
CW		 3167 }, {
3168 .compatible = "boe,nv101wxmn51",
3169 .data = &boe_nv101wxmn51,
e58edce6
GB		 3170 }, {
3171 .compatible = "cdtech,s043wq26h-ct7",
3172 .data = &cdtech_s043wq26h_ct7,
982f944e
GB		 3173 }, {
3174 .compatible = "cdtech,s070wv95-ct16",
3175 .data = &cdtech_s070wv95_ct16,
2cb35c80
RL		 3176 }, {
3177 .compatible = "chunghwa,claa070wp03xg",
3178 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 3179 }, {
3180 .compatible = "chunghwa,claa101wa01a",
3181 .data = &chunghwa_claa101wa01a
280921de
TR		 3182 }, {
3183 .compatible = "chunghwa,claa101wb01",
3184 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 3185 }, {
3186 .compatible = "dataimage,scf0700c48ggu18",
3187 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 3188 }, {
3189 .compatible = "dlc,dlc0700yzg-1",
3190 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 3191 }, {
3192 .compatible = "dlc,dlc1010gig",
3193 .data = &dlc_dlc1010gig,
c2d24af6
AP		 3194 }, {
3195 .compatible = "edt,et035012dm6",
3196 .data = &edt_et035012dm6,
fd819bff
MV		 3197 }, {
3198 .compatible = "edt,etm0430g0dh6",
3199 .data = &edt_etm0430g0dh6,
26ab0065
SA		 3200 }, {
3201 .compatible = "edt,et057090dhu",
3202 .data = &edt_et057090dhu,
fff5de45
PZ		 3203 }, {
3204 .compatible = "edt,et070080dh6",
3205 .data = &edt_etm0700g0dh6,
3206 }, {
3207 .compatible = "edt,etm0700g0dh6",
3208 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 3209 }, {
3210 .compatible = "edt,etm0700g0bdh6",
3211 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 3212 }, {
3213 .compatible = "edt,etm0700g0edh6",
3214 .data = &edt_etm0700g0bdh6,
9158e3c3
MF		 3215 }, {
3216 .compatible = "evervision,vgg804821",
3217 .data = &evervision_vgg804821,
102932b0
BB		 3218 }, {
3219 .compatible = "foxlink,fl500wvr00-a0t",
3220 .data = &foxlink_fl500wvr00_a0t,
3be20710
JT		 3221 }, {
3222 .compatible = "friendlyarm,hd702e",
3223 .data = &friendlyarm_hd702e,
d435a2af
PZ		 3224 }, {
3225 .compatible = "giantplus,gpg482739qs5",
3226 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 3227 }, {
3228 .compatible = "giantplus,gpm940b0",
3229 .data = &giantplus_gpm940b0,
a853205e
PZ		 3230 }, {
3231 .compatible = "hannstar,hsd070pww1",
3232 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 3233 }, {
3234 .compatible = "hannstar,hsd100pxn1",
3235 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 3236 }, {
3237 .compatible = "hit,tx23d38vm0caa",
3238 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 3239 }, {
3240 .compatible = "innolux,at043tn24",
3241 .data = &innolux_at043tn24,
4fc24ab3
RB		 3242 }, {
3243 .compatible = "innolux,at070tn92",
3244 .data = &innolux_at070tn92,
1e29b840 3245 }, {
a5d2ade6
CF		 3246 .compatible = "innolux,g070y2-l01",
3247 .data = &innolux_g070y2_l01,
3248 }, {
3249 .compatible = "innolux,g101ice-l01",
1e29b840 3250 .data = &innolux_g101ice_l01
d731f661 3251 }, {
a5d2ade6 3252 .compatible = "innolux,g121i1-l01",
d731f661 3253 .data = &innolux_g121i1_l01
f8fa17ba
AB		 3254 }, {
3255 .compatible = "innolux,g121x1-l03",
3256 .data = &innolux_g121x1_l03,
0a2288c0
TR		 3257 }, {
3258 .compatible = "innolux,n116bge",
3259 .data = &innolux_n116bge,
ea44739d
AB		 3260 }, {
3261 .compatible = "innolux,n156bge-l21",
3262 .data = &innolux_n156bge_l21,
da50bd42 3263 }, {
8f054b6f
DA		 3264 .compatible = "innolux,p120zdg-bf1",
3265 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 3266 }, {
3267 .compatible = "innolux,zj070na-01p",
3268 .data = &innolux_zj070na_01p,
14bf60c4
LM		 3269 }, {
3270 .compatible = "koe,tx14d24vm1bpa",
3271 .data = &koe_tx14d24vm1bpa,
8cfe8341
JT		 3272 }, {
3273 .compatible = "koe,tx31d200vm0baa",
3274 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 3275 }, {
3276 .compatible = "kyo,tcg121xglp",
3277 .data = &kyo_tcg121xglp,
27abdd83
PK		 3278 }, {
3279 .compatible = "lemaker,bl035-rgb-002",
3280 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 3281 }, {
3282 .compatible = "lg,lb070wv8",
3283 .data = &lg_lb070wv8,
c5ece402
YY		 3284 }, {
3285 .compatible = "lg,lp079qx1-sp0v",
3286 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 3287 }, {
3288 .compatible = "lg,lp097qx1-spa1",
3289 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 3290 }, {
3291 .compatible = "lg,lp120up1",
3292 .data = &lg_lp120up1,
ec7c5653
TR		 3293 }, {
3294 .compatible = "lg,lp129qe",
3295 .data = &lg_lp129qe,
0d35408a
AF		 3296 }, {
3297 .compatible = "logicpd,type28",
3298 .data = &logicpd_type_28,
65c766ca
LM		 3299 }, {
3300 .compatible = "mitsubishi,aa070mc01-ca1",
3301 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 3302 }, {
3303 .compatible = "nec,nl12880bc20-05",
3304 .data = &nec_nl12880bc20_05,
c6e87f91 3305 }, {
3306 .compatible = "nec,nl4827hc19-05b",
3307 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 3308 }, {
3309 .compatible = "netron-dy,e231732",
3310 .data = &netron_dy_e231732,
3b39ad7a
TV		 3311 }, {
3312 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3313 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 3314 }, {
3315 .compatible = "nlt,nl192108ac18-02d",
3316 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 3317 }, {
3318 .compatible = "nvd,9128",
3319 .data = &nvd_9128,
a99fb626
GB		 3320 }, {
3321 .compatible = "okaya,rs800480t-7x0gp",
3322 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 3323 }, {
3324 .compatible = "olimex,lcd-olinuxino-43-ts",
3325 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 3326 }, {
3327 .compatible = "ontat,yx700wv03",
3328 .data = &ontat_yx700wv03,
9c31dcb6
NS		 3329 }, {
3330 .compatible = "ortustech,com37h3m05dtc",
3331 .data = &ortustech_com37h3m,
3332 }, {
3333 .compatible = "ortustech,com37h3m99dtc",
3334 .data = &ortustech_com37h3m,
725c9d40
PZ		 3335 }, {
3336 .compatible = "ortustech,com43h4m85ulc",
3337 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 3338 }, {
3339 .compatible = "osddisplays,osd070t1718-19ts",
3340 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 3341 }, {
3342 .compatible = "pda,91-00156-a0",
3343 .data = &pda_91_00156_a0,
d2a6f0f5
JW		 3344 }, {
3345 .compatible = "qiaodian,qd43003c0-40",
3346 .data = &qd43003c0_40,
23167fa9
JT		 3347 }, {
3348 .compatible = "rocktech,rk070er9427",
3349 .data = &rocktech_rk070er9427,
0330eaf3
YY		 3350 }, {
3351 .compatible = "samsung,lsn122dl01-c01",
3352 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 3353 }, {
3354 .compatible = "samsung,ltn101nt05",
3355 .data = &samsung_ltn101nt05,
0c934306
SM		 3356 }, {
3357 .compatible = "samsung,ltn140at29-301",
3358 .data = &samsung_ltn140at29_301,
cd5e1cbe
JH		 3359 }, {
3360 .compatible = "sharp,ld-d5116z01b",
3361 .data = &sharp_ld_d5116z01b,
03e3ec9a
VZ		 3362 }, {
3363 .compatible = "sharp,lq035q7db03",
3364 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 3365 }, {
3366 .compatible = "sharp,lq070y3dg3b",
3367 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 3368 }, {
3369 .compatible = "sharp,lq101k1ly04",
3370 .data = &sharp_lq101k1ly04,
739c7de9
YY		 3371 }, {
3372 .compatible = "sharp,lq123p1jx31",
3373 .data = &sharp_lq123p1jx31,
0f9cdd74
GL		 3374 }, {
3375 .compatible = "sharp,lq150x1lg11",
3376 .data = &sharp_lq150x1lg11,
f1bd37f3
PC		 3377 }, {
3378 .compatible = "sharp,ls020b1dd01d",
3379 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 3380 }, {
3381 .compatible = "shelly,sca07010-bfn-lnn",
3382 .data = &shelly_sca07010_bfn_lnn,
9bb34c4c
DA		 3383 }, {
3384 .compatible = "starry,kr122ea0sra",
3385 .data = &starry_kr122ea0sra,
42161531
JS		 3386 }, {
3387 .compatible = "tfc,s9700rtwv43tr-01b",
3388 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 3389 }, {
3390 .compatible = "tianma,tm070jdhg30",
3391 .data = &tianma_tm070jdhg30,
870a0b12
LM		 3392 }, {
3393 .compatible = "tianma,tm070rvhg71",
3394 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 3395 }, {
3396 .compatible = "ti,nspire-cx-lcd-panel",
3397 .data = &ti_nspire_cx_lcd_panel,
3398 }, {
3399 .compatible = "ti,nspire-classic-lcd-panel",
3400 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 3401 }, {
3402 .compatible = "toshiba,lt089ac29000",
3403 .data = &toshiba_lt089ac29000,
227e4f40
BD		 3404 }, {
3405 .compatible = "tpk,f07a-0102",
3406 .data = &tpk_f07a_0102,
3407 }, {
3408 .compatible = "tpk,f10a-0102",
3409 .data = &tpk_f10a_0102,
06a9dc65
MS		 3410 }, {
3411 .compatible = "urt,umsh-8596md-t",
3412 .data = &urt_umsh_8596md_parallel,
3413 }, {
3414 .compatible = "urt,umsh-8596md-1t",
3415 .data = &urt_umsh_8596md_parallel,
3416 }, {
3417 .compatible = "urt,umsh-8596md-7t",
3418 .data = &urt_umsh_8596md_parallel,
3419 }, {
3420 .compatible = "urt,umsh-8596md-11t",
3421 .data = &urt_umsh_8596md_lvds,
3422 }, {
3423 .compatible = "urt,umsh-8596md-19t",
3424 .data = &urt_umsh_8596md_lvds,
3425 }, {
3426 .compatible = "urt,umsh-8596md-20t",
3427 .data = &urt_umsh_8596md_parallel,
04206185
FE		 3428 }, {
3429 .compatible = "vxt,vl050-8048nt-c01",
3430 .data = &vl050_8048nt_c01,
e4bac408
RG		 3431 }, {
3432 .compatible = "winstar,wf35ltiacd",
3433 .data = &winstar_wf35ltiacd,
280921de
TR		 3434 }, {
3435 /* sentinel */
3436 }
3437};
3438MODULE_DEVICE_TABLE(of, platform_of_match);
3439
3440static int panel_simple_platform_probe(struct platform_device *pdev)
3441{
3442 const struct of_device_id *id;
3443
3444 id = of_match_node(platform_of_match, pdev->dev.of_node);
3445 if (!id)
3446 return -ENODEV;
3447
3448 return panel_simple_probe(&pdev->dev, id->data);
3449}
3450
3451static int panel_simple_platform_remove(struct platform_device *pdev)
3452{
3453 return panel_simple_remove(&pdev->dev);
3454}
3455
d02fd93e
TR		 3456static void panel_simple_platform_shutdown(struct platform_device *pdev)
3457{
3458 panel_simple_shutdown(&pdev->dev);
3459}
3460
280921de
TR		 3461static struct platform_driver panel_simple_platform_driver = {
3462 .driver = {
3463 .name = "panel-simple",
280921de
TR		 3464 .of_match_table = platform_of_match,
3465 },
3466 .probe = panel_simple_platform_probe,
3467 .remove = panel_simple_platform_remove,
d02fd93e 3468 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 3469};
3470
210fcd9d
TR		 3471struct panel_desc_dsi {
3472 struct panel_desc desc;
3473
462658b8 3474 unsigned long flags;
210fcd9d
TR		 3475 enum mipi_dsi_pixel_format format;
3476 unsigned int lanes;
3477};
3478
d718d79e
TR		 3479static const struct drm_display_mode auo_b080uan01_mode = {
3480 .clock = 154500,
3481 .hdisplay = 1200,
3482 .hsync_start = 1200 + 62,
3483 .hsync_end = 1200 + 62 + 4,
3484 .htotal = 1200 + 62 + 4 + 62,
3485 .vdisplay = 1920,
3486 .vsync_start = 1920 + 9,
3487 .vsync_end = 1920 + 9 + 2,
3488 .vtotal = 1920 + 9 + 2 + 8,
3489 .vrefresh = 60,
3490};
3491
3492static const struct panel_desc_dsi auo_b080uan01 = {
3493 .desc = {
3494 .modes = &auo_b080uan01_mode,
3495 .num_modes = 1,
3496 .bpc = 8,
3497 .size = {
3498 .width = 108,
3499 .height = 272,
3500 },
3501 },
3502 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3503 .format = MIPI_DSI_FMT_RGB888,
3504 .lanes = 4,
3505};
3506
c8521969
CZ		 3507static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3508 .clock = 160000,
3509 .hdisplay = 1200,
3510 .hsync_start = 1200 + 120,
3511 .hsync_end = 1200 + 120 + 20,
3512 .htotal = 1200 + 120 + 20 + 21,
3513 .vdisplay = 1920,
3514 .vsync_start = 1920 + 21,
3515 .vsync_end = 1920 + 21 + 3,
3516 .vtotal = 1920 + 21 + 3 + 18,
3517 .vrefresh = 60,
3518 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3519};
3520
3521static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3522 .desc = {
3523 .modes = &boe_tv080wum_nl0_mode,
3524 .num_modes = 1,
3525 .size = {
3526 .width = 107,
3527 .height = 172,
3528 },
3529 },
3530 .flags = MIPI_DSI_MODE_VIDEO |
3531 MIPI_DSI_MODE_VIDEO_BURST |
3532 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3533 .format = MIPI_DSI_FMT_RGB888,
3534 .lanes = 4,
3535};
3536
712ac1ba
AC		 3537static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3538 .clock = 71000,
3539 .hdisplay = 800,
3540 .hsync_start = 800 + 32,
3541 .hsync_end = 800 + 32 + 1,
3542 .htotal = 800 + 32 + 1 + 57,
3543 .vdisplay = 1280,
3544 .vsync_start = 1280 + 28,
3545 .vsync_end = 1280 + 28 + 1,
3546 .vtotal = 1280 + 28 + 1 + 14,
3547 .vrefresh = 60,
3548};
3549
3550static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3551 .desc = {
3552 .modes = &lg_ld070wx3_sl01_mode,
3553 .num_modes = 1,
d7a839cd 3554 .bpc = 8,
712ac1ba
AC		 3555 .size = {
3556 .width = 94,
3557 .height = 151,
3558 },
3559 },
5e4cc278 3560 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 3561 .format = MIPI_DSI_FMT_RGB888,
3562 .lanes = 4,
3563};
3564
499ce85a
AC		 3565static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3566 .clock = 67000,
3567 .hdisplay = 720,
3568 .hsync_start = 720 + 12,
3569 .hsync_end = 720 + 12 + 4,
3570 .htotal = 720 + 12 + 4 + 112,
3571 .vdisplay = 1280,
3572 .vsync_start = 1280 + 8,
3573 .vsync_end = 1280 + 8 + 4,
3574 .vtotal = 1280 + 8 + 4 + 12,
3575 .vrefresh = 60,
3576};
3577
3578static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3579 .desc = {
3580 .modes = &lg_lh500wx1_sd03_mode,
3581 .num_modes = 1,
d7a839cd 3582 .bpc = 8,
499ce85a
AC		 3583 .size = {
3584 .width = 62,
3585 .height = 110,
3586 },
3587 },
3588 .flags = MIPI_DSI_MODE_VIDEO,
3589 .format = MIPI_DSI_FMT_RGB888,
3590 .lanes = 4,
3591};
3592
280921de
TR		 3593static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3594 .clock = 157200,
3595 .hdisplay = 1920,
3596 .hsync_start = 1920 + 154,
3597 .hsync_end = 1920 + 154 + 16,
3598 .htotal = 1920 + 154 + 16 + 32,
3599 .vdisplay = 1200,
3600 .vsync_start = 1200 + 17,
3601 .vsync_end = 1200 + 17 + 2,
3602 .vtotal = 1200 + 17 + 2 + 16,
3603 .vrefresh = 60,
3604};
3605
210fcd9d
TR		 3606static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3607 .desc = {
3608 .modes = &panasonic_vvx10f004b00_mode,
3609 .num_modes = 1,
d7a839cd 3610 .bpc = 8,
210fcd9d
TR		 3611 .size = {
3612 .width = 217,
3613 .height = 136,
3614 },
280921de 3615 },
5e4cc278
AC		 3616 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3617 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 3618 .format = MIPI_DSI_FMT_RGB888,
3619 .lanes = 4,
3620};
3621
debcd8f9
JM		 3622static const struct drm_display_mode lg_acx467akm_7_mode = {
3623 .clock = 150000,
3624 .hdisplay = 1080,
3625 .hsync_start = 1080 + 2,
3626 .hsync_end = 1080 + 2 + 2,
3627 .htotal = 1080 + 2 + 2 + 2,
3628 .vdisplay = 1920,
3629 .vsync_start = 1920 + 2,
3630 .vsync_end = 1920 + 2 + 2,
3631 .vtotal = 1920 + 2 + 2 + 2,
3632 .vrefresh = 60,
3633};
3634
3635static const struct panel_desc_dsi lg_acx467akm_7 = {
3636 .desc = {
3637 .modes = &lg_acx467akm_7_mode,
3638 .num_modes = 1,
3639 .bpc = 8,
3640 .size = {
3641 .width = 62,
3642 .height = 110,
3643 },
3644 },
3645 .flags = 0,
3646 .format = MIPI_DSI_FMT_RGB888,
3647 .lanes = 4,
3648};
3649
62967232
PU		 3650static const struct drm_display_mode osd101t2045_53ts_mode = {
3651 .clock = 154500,
3652 .hdisplay = 1920,
3653 .hsync_start = 1920 + 112,
3654 .hsync_end = 1920 + 112 + 16,
3655 .htotal = 1920 + 112 + 16 + 32,
3656 .vdisplay = 1200,
3657 .vsync_start = 1200 + 16,
3658 .vsync_end = 1200 + 16 + 2,
3659 .vtotal = 1200 + 16 + 2 + 16,
3660 .vrefresh = 60,
3661 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3662};
3663
3664static const struct panel_desc_dsi osd101t2045_53ts = {
3665 .desc = {
3666 .modes = &osd101t2045_53ts_mode,
3667 .num_modes = 1,
3668 .bpc = 8,
3669 .size = {
3670 .width = 217,
3671 .height = 136,
3672 },
3673 },
3674 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3675 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3676 MIPI_DSI_MODE_EOT_PACKET,
3677 .format = MIPI_DSI_FMT_RGB888,
3678 .lanes = 4,
3679};
3680
210fcd9d
TR		 3681static const struct of_device_id dsi_of_match[] = {
3682 {
d718d79e
TR		 3683 .compatible = "auo,b080uan01",
3684 .data = &auo_b080uan01
c8521969
CZ		 3685 }, {
3686 .compatible = "boe,tv080wum-nl0",
3687 .data = &boe_tv080wum_nl0
d718d79e 3688 }, {
712ac1ba
AC		 3689 .compatible = "lg,ld070wx3-sl01",
3690 .data = &lg_ld070wx3_sl01
3691 }, {
499ce85a
AC		 3692 .compatible = "lg,lh500wx1-sd03",
3693 .data = &lg_lh500wx1_sd03
3694 }, {
210fcd9d
TR		 3695 .compatible = "panasonic,vvx10f004b00",
3696 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 3697 }, {
3698 .compatible = "lg,acx467akm-7",
3699 .data = &lg_acx467akm_7
62967232
PU		 3700 }, {
3701 .compatible = "osddisplays,osd101t2045-53ts",
3702 .data = &osd101t2045_53ts
210fcd9d
TR		 3703 }, {
3704 /* sentinel */
3705 }
3706};
3707MODULE_DEVICE_TABLE(of, dsi_of_match);
3708
3709static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3710{
3711 const struct panel_desc_dsi *desc;
3712 const struct of_device_id *id;
3713 int err;
3714
3715 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3716 if (!id)
3717 return -ENODEV;
3718
3719 desc = id->data;
3720
3721 err = panel_simple_probe(&dsi->dev, &desc->desc);
3722 if (err < 0)
3723 return err;
3724
462658b8 3725 dsi->mode_flags = desc->flags;
210fcd9d
TR		 3726 dsi->format = desc->format;
3727 dsi->lanes = desc->lanes;
3728
7ad9db66
PU		 3729 err = mipi_dsi_attach(dsi);
3730 if (err) {
3731 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3732
3733 drm_panel_remove(&panel->base);
3734 }
3735
3736 return err;
210fcd9d
TR		 3737}
3738
3739static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3740{
3741 int err;
3742
3743 err = mipi_dsi_detach(dsi);
3744 if (err < 0)
3745 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3746
3747 return panel_simple_remove(&dsi->dev);
3748}
3749
d02fd93e
TR		 3750static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3751{
3752 panel_simple_shutdown(&dsi->dev);
3753}
3754
210fcd9d
TR		 3755static struct mipi_dsi_driver panel_simple_dsi_driver = {
3756 .driver = {
3757 .name = "panel-simple-dsi",
210fcd9d
TR		 3758 .of_match_table = dsi_of_match,
3759 },
3760 .probe = panel_simple_dsi_probe,
3761 .remove = panel_simple_dsi_remove,
d02fd93e 3762 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 3763};
3764
3765static int __init panel_simple_init(void)
3766{
210fcd9d
TR		 3767 int err;
3768
3769 err = platform_driver_register(&panel_simple_platform_driver);
3770 if (err < 0)
3771 return err;
3772
3773 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3774 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3775 if (err < 0)
3776 return err;
3777 }
3778
3779 return 0;
280921de
TR		 3780}
3781module_init(panel_simple_init);
3782
3783static void __exit panel_simple_exit(void)
3784{
210fcd9d
TR		 3785 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3786 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3787
280921de
TR		 3788 platform_driver_unregister(&panel_simple_platform_driver);
3789}
3790module_exit(panel_simple_exit);
3791
3792MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3793MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3794MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)