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dt-bindings: drm/panel: simple: Add no-hpd property
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
85533e3b
UÖ		 47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
280921de
TR		 51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
f673c37e
AK		 55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
795f7ab3
BB		 73
74 u32 bus_format;
f0aa0838 75 u32 bus_flags;
280921de
TR		 76};
77
280921de
TR		 78struct panel_simple {
79 struct drm_panel base;
613a633e 80 bool prepared;
280921de
TR		 81 bool enabled;
82
83 const struct panel_desc *desc;
84
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
88
cfdf0549 89 struct gpio_desc *enable_gpio;
280921de
TR		 90};
91
92static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
93{
94 return container_of(panel, struct panel_simple, base);
95}
96
97static int panel_simple_get_fixed_modes(struct panel_simple *panel)
98{
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
103
104 if (!panel->desc)
105 return 0;
106
a5d3e625
PZ		 107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
109 struct videomode vm;
110
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
113 if (!mode) {
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
116 continue;
117 }
118
119 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
230c5b44 123 if (panel->desc->num_timings == 1)
cda55372
BB		 124 mode->type |= DRM_MODE_TYPE_PREFERRED;
125
a5d3e625
PZ		 126 drm_mode_probed_add(connector, mode);
127 num++;
128 }
129
280921de
TR		 130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
132
133 mode = drm_mode_duplicate(drm, m);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
137 continue;
138 }
139
cda55372
BB		 140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
280921de
TR		 145 drm_mode_set_name(mode);
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
0208d511 151 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
f0aa0838 157 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 158
159 return num;
160}
161
162static int panel_simple_disable(struct drm_panel *panel)
163{
164 struct panel_simple *p = to_panel_simple(panel);
165
166 if (!p->enabled)
167 return 0;
168
169 if (p->backlight) {
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
e4aa3428 171 p->backlight->props.state |= BL_CORE_FBBLANK;
280921de
TR		 172 backlight_update_status(p->backlight);
173 }
174
f673c37e
AK		 175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
177
280921de
TR		 178 p->enabled = false;
179
180 return 0;
181}
182
c0e1d170
AK		 183static int panel_simple_unprepare(struct drm_panel *panel)
184{
613a633e
AK		 185 struct panel_simple *p = to_panel_simple(panel);
186
187 if (!p->prepared)
188 return 0;
189
756b918d 190 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 191
192 regulator_disable(p->supply);
193
f673c37e
AK		 194 if (p->desc->delay.unprepare)
195 msleep(p->desc->delay.unprepare);
196
613a633e 197 p->prepared = false;
c0e1d170 198
c0e1d170
AK		 199 return 0;
200}
201
613a633e 202static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 203{
204 struct panel_simple *p = to_panel_simple(panel);
205 int err;
206
613a633e 207 if (p->prepared)
280921de
TR		 208 return 0;
209
210 err = regulator_enable(p->supply);
211 if (err < 0) {
212 dev_err(panel->dev, "failed to enable supply: %d\n", err);
213 return err;
214 }
215
756b918d 216 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 217
f673c37e
AK		 218 if (p->desc->delay.prepare)
219 msleep(p->desc->delay.prepare);
220
613a633e
AK		 221 p->prepared = true;
222
223 return 0;
224}
225
226static int panel_simple_enable(struct drm_panel *panel)
227{
228 struct panel_simple *p = to_panel_simple(panel);
229
230 if (p->enabled)
231 return 0;
232
f673c37e
AK		 233 if (p->desc->delay.enable)
234 msleep(p->desc->delay.enable);
235
280921de 236 if (p->backlight) {
e4aa3428 237 p->backlight->props.state &= ~BL_CORE_FBBLANK;
280921de
TR		 238 p->backlight->props.power = FB_BLANK_UNBLANK;
239 backlight_update_status(p->backlight);
240 }
241
242 p->enabled = true;
243
244 return 0;
245}
246
247static int panel_simple_get_modes(struct drm_panel *panel)
248{
249 struct panel_simple *p = to_panel_simple(panel);
250 int num = 0;
251
252 /* probe EDID if a DDC bus is available */
253 if (p->ddc) {
254 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
c555f023 255 drm_connector_update_edid_property(panel->connector, edid);
280921de
TR		 256 if (edid) {
257 num += drm_add_edid_modes(panel->connector, edid);
258 kfree(edid);
259 }
260 }
261
262 /* add hard-coded panel modes */
263 num += panel_simple_get_fixed_modes(p);
264
265 return num;
266}
267
a5d3e625
PZ		 268static int panel_simple_get_timings(struct drm_panel *panel,
269 unsigned int num_timings,
270 struct display_timing *timings)
271{
272 struct panel_simple *p = to_panel_simple(panel);
273 unsigned int i;
274
275 if (p->desc->num_timings < num_timings)
276 num_timings = p->desc->num_timings;
277
278 if (timings)
279 for (i = 0; i < num_timings; i++)
280 timings[i] = p->desc->timings[i];
281
282 return p->desc->num_timings;
283}
284
280921de
TR		 285static const struct drm_panel_funcs panel_simple_funcs = {
286 .disable = panel_simple_disable,
c0e1d170
AK		 287 .unprepare = panel_simple_unprepare,
288 .prepare = panel_simple_prepare,
280921de
TR		 289 .enable = panel_simple_enable,
290 .get_modes = panel_simple_get_modes,
a5d3e625 291 .get_timings = panel_simple_get_timings,
280921de
TR		 292};
293
294static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
295{
296 struct device_node *backlight, *ddc;
297 struct panel_simple *panel;
280921de
TR		 298 int err;
299
300 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
301 if (!panel)
302 return -ENOMEM;
303
304 panel->enabled = false;
613a633e 305 panel->prepared = false;
280921de
TR		 306 panel->desc = desc;
307
308 panel->supply = devm_regulator_get(dev, "power");
309 if (IS_ERR(panel->supply))
310 return PTR_ERR(panel->supply);
311
a61400d8
AC		 312 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
313 GPIOD_OUT_LOW);
cfdf0549
AC		 314 if (IS_ERR(panel->enable_gpio)) {
315 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 316 if (err != -EPROBE_DEFER)
317 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 318 return err;
319 }
280921de 320
280921de
TR		 321 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
322 if (backlight) {
323 panel->backlight = of_find_backlight_by_node(backlight);
324 of_node_put(backlight);
325
cfdf0549
AC		 326 if (!panel->backlight)
327 return -EPROBE_DEFER;
280921de
TR		 328 }
329
330 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
331 if (ddc) {
332 panel->ddc = of_find_i2c_adapter_by_node(ddc);
333 of_node_put(ddc);
334
335 if (!panel->ddc) {
336 err = -EPROBE_DEFER;
337 goto free_backlight;
338 }
339 }
340
341 drm_panel_init(&panel->base);
342 panel->base.dev = dev;
343 panel->base.funcs = &panel_simple_funcs;
344
345 err = drm_panel_add(&panel->base);
346 if (err < 0)
347 goto free_ddc;
348
349 dev_set_drvdata(dev, panel);
350
351 return 0;
352
353free_ddc:
354 if (panel->ddc)
355 put_device(&panel->ddc->dev);
356free_backlight:
357 if (panel->backlight)
358 put_device(&panel->backlight->dev);
280921de
TR		 359
360 return err;
361}
362
363static int panel_simple_remove(struct device *dev)
364{
365 struct panel_simple *panel = dev_get_drvdata(dev);
366
280921de
TR		 367 drm_panel_remove(&panel->base);
368
369 panel_simple_disable(&panel->base);
f3621a8e 370 panel_simple_unprepare(&panel->base);
280921de
TR		 371
372 if (panel->ddc)
373 put_device(&panel->ddc->dev);
374
375 if (panel->backlight)
376 put_device(&panel->backlight->dev);
377
280921de
TR		 378 return 0;
379}
380
d02fd93e
TR		 381static void panel_simple_shutdown(struct device *dev)
382{
383 struct panel_simple *panel = dev_get_drvdata(dev);
384
385 panel_simple_disable(&panel->base);
f3621a8e 386 panel_simple_unprepare(&panel->base);
d02fd93e
TR		 387}
388
966fea78
YF		 389static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
390 .clock = 9000,
391 .hdisplay = 480,
392 .hsync_start = 480 + 2,
393 .hsync_end = 480 + 2 + 41,
394 .htotal = 480 + 2 + 41 + 2,
395 .vdisplay = 272,
396 .vsync_start = 272 + 2,
397 .vsync_end = 272 + 2 + 10,
398 .vtotal = 272 + 2 + 10 + 2,
399 .vrefresh = 60,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
401};
402
403static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
404 .modes = &ampire_am_480272h3tmqw_t01h_mode,
405 .num_modes = 1,
406 .bpc = 8,
407 .size = {
408 .width = 105,
409 .height = 67,
410 },
411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
412};
413
1c550fa1
PZ		 414static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
415 .clock = 33333,
416 .hdisplay = 800,
417 .hsync_start = 800 + 0,
418 .hsync_end = 800 + 0 + 255,
419 .htotal = 800 + 0 + 255 + 0,
420 .vdisplay = 480,
421 .vsync_start = 480 + 2,
422 .vsync_end = 480 + 2 + 45,
423 .vtotal = 480 + 2 + 45 + 0,
424 .vrefresh = 60,
425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
426};
427
428static const struct panel_desc ampire_am800480r3tmqwa1h = {
429 .modes = &ampire_am800480r3tmqwa1h_mode,
430 .num_modes = 1,
431 .bpc = 6,
432 .size = {
433 .width = 152,
434 .height = 91,
435 },
436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
437};
438
280921de
TR		 439static const struct drm_display_mode auo_b101aw03_mode = {
440 .clock = 51450,
441 .hdisplay = 1024,
442 .hsync_start = 1024 + 156,
443 .hsync_end = 1024 + 156 + 8,
444 .htotal = 1024 + 156 + 8 + 156,
445 .vdisplay = 600,
446 .vsync_start = 600 + 16,
447 .vsync_end = 600 + 16 + 6,
448 .vtotal = 600 + 16 + 6 + 16,
449 .vrefresh = 60,
450};
451
452static const struct panel_desc auo_b101aw03 = {
453 .modes = &auo_b101aw03_mode,
454 .num_modes = 1,
0208d511 455 .bpc = 6,
280921de
TR		 456 .size = {
457 .width = 223,
458 .height = 125,
459 },
460};
461
a531bc3d
HL		 462static const struct drm_display_mode auo_b101ean01_mode = {
463 .clock = 72500,
464 .hdisplay = 1280,
465 .hsync_start = 1280 + 119,
466 .hsync_end = 1280 + 119 + 32,
467 .htotal = 1280 + 119 + 32 + 21,
468 .vdisplay = 800,
469 .vsync_start = 800 + 4,
470 .vsync_end = 800 + 4 + 20,
471 .vtotal = 800 + 4 + 20 + 8,
472 .vrefresh = 60,
473};
474
475static const struct panel_desc auo_b101ean01 = {
476 .modes = &auo_b101ean01_mode,
477 .num_modes = 1,
478 .bpc = 6,
479 .size = {
480 .width = 217,
481 .height = 136,
482 },
483};
484
dac746e0
RC		 485static const struct drm_display_mode auo_b101xtn01_mode = {
486 .clock = 72000,
487 .hdisplay = 1366,
488 .hsync_start = 1366 + 20,
489 .hsync_end = 1366 + 20 + 70,
490 .htotal = 1366 + 20 + 70,
491 .vdisplay = 768,
492 .vsync_start = 768 + 14,
493 .vsync_end = 768 + 14 + 42,
494 .vtotal = 768 + 14 + 42,
495 .vrefresh = 60,
496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
497};
498
499static const struct panel_desc auo_b101xtn01 = {
500 .modes = &auo_b101xtn01_mode,
501 .num_modes = 1,
502 .bpc = 6,
503 .size = {
504 .width = 223,
505 .height = 125,
506 },
507};
508
e35e305e
AK		 509static const struct drm_display_mode auo_b116xw03_mode = {
510 .clock = 70589,
511 .hdisplay = 1366,
512 .hsync_start = 1366 + 40,
513 .hsync_end = 1366 + 40 + 40,
514 .htotal = 1366 + 40 + 40 + 32,
515 .vdisplay = 768,
516 .vsync_start = 768 + 10,
517 .vsync_end = 768 + 10 + 12,
518 .vtotal = 768 + 10 + 12 + 6,
519 .vrefresh = 60,
520};
521
522static const struct panel_desc auo_b116xw03 = {
523 .modes = &auo_b116xw03_mode,
524 .num_modes = 1,
525 .bpc = 6,
526 .size = {
527 .width = 256,
528 .height = 144,
529 },
530};
531
a333f7ad
SM		 532static const struct drm_display_mode auo_b133xtn01_mode = {
533 .clock = 69500,
534 .hdisplay = 1366,
535 .hsync_start = 1366 + 48,
536 .hsync_end = 1366 + 48 + 32,
537 .htotal = 1366 + 48 + 32 + 20,
538 .vdisplay = 768,
539 .vsync_start = 768 + 3,
540 .vsync_end = 768 + 3 + 6,
541 .vtotal = 768 + 3 + 6 + 13,
542 .vrefresh = 60,
543};
544
545static const struct panel_desc auo_b133xtn01 = {
546 .modes = &auo_b133xtn01_mode,
547 .num_modes = 1,
0208d511 548 .bpc = 6,
a333f7ad
SM		 549 .size = {
550 .width = 293,
551 .height = 165,
552 },
553};
554
3e51d609
AK		 555static const struct drm_display_mode auo_b133htn01_mode = {
556 .clock = 150660,
557 .hdisplay = 1920,
558 .hsync_start = 1920 + 172,
559 .hsync_end = 1920 + 172 + 80,
560 .htotal = 1920 + 172 + 80 + 60,
561 .vdisplay = 1080,
562 .vsync_start = 1080 + 25,
563 .vsync_end = 1080 + 25 + 10,
564 .vtotal = 1080 + 25 + 10 + 10,
565 .vrefresh = 60,
566};
567
568static const struct panel_desc auo_b133htn01 = {
569 .modes = &auo_b133htn01_mode,
570 .num_modes = 1,
d7a839cd 571 .bpc = 6,
3e51d609
AK		 572 .size = {
573 .width = 293,
574 .height = 165,
575 },
576 .delay = {
577 .prepare = 105,
578 .enable = 20,
579 .unprepare = 50,
580 },
581};
582
bccfaffb
LM		 583static const struct display_timing auo_g070vvn01_timings = {
584 .pixelclock = { 33300000, 34209000, 45000000 },
585 .hactive = { 800, 800, 800 },
586 .hfront_porch = { 20, 40, 200 },
587 .hback_porch = { 87, 40, 1 },
588 .hsync_len = { 1, 48, 87 },
589 .vactive = { 480, 480, 480 },
590 .vfront_porch = { 5, 13, 200 },
591 .vback_porch = { 31, 31, 29 },
592 .vsync_len = { 1, 1, 3 },
593};
594
595static const struct panel_desc auo_g070vvn01 = {
596 .timings = &auo_g070vvn01_timings,
597 .num_timings = 1,
598 .bpc = 8,
599 .size = {
600 .width = 152,
601 .height = 91,
602 },
603 .delay = {
604 .prepare = 200,
605 .enable = 50,
606 .disable = 50,
607 .unprepare = 1000,
608 },
609};
610
4451c287
CF		 611static const struct drm_display_mode auo_g104sn02_mode = {
612 .clock = 40000,
613 .hdisplay = 800,
614 .hsync_start = 800 + 40,
615 .hsync_end = 800 + 40 + 216,
616 .htotal = 800 + 40 + 216 + 128,
617 .vdisplay = 600,
618 .vsync_start = 600 + 10,
619 .vsync_end = 600 + 10 + 35,
620 .vtotal = 600 + 10 + 35 + 2,
621 .vrefresh = 60,
622};
623
624static const struct panel_desc auo_g104sn02 = {
625 .modes = &auo_g104sn02_mode,
626 .num_modes = 1,
627 .bpc = 8,
628 .size = {
629 .width = 211,
630 .height = 158,
631 },
632};
633
697035c6
LS		 634static const struct display_timing auo_g133han01_timings = {
635 .pixelclock = { 134000000, 141200000, 149000000 },
636 .hactive = { 1920, 1920, 1920 },
637 .hfront_porch = { 39, 58, 77 },
638 .hback_porch = { 59, 88, 117 },
639 .hsync_len = { 28, 42, 56 },
640 .vactive = { 1080, 1080, 1080 },
641 .vfront_porch = { 3, 8, 11 },
642 .vback_porch = { 5, 14, 19 },
643 .vsync_len = { 4, 14, 19 },
644};
645
646static const struct panel_desc auo_g133han01 = {
647 .timings = &auo_g133han01_timings,
648 .num_timings = 1,
649 .bpc = 8,
650 .size = {
651 .width = 293,
652 .height = 165,
653 },
654 .delay = {
655 .prepare = 200,
656 .enable = 50,
657 .disable = 50,
658 .unprepare = 1000,
659 },
660 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
661};
662
8c31f603
LS		 663static const struct display_timing auo_g185han01_timings = {
664 .pixelclock = { 120000000, 144000000, 175000000 },
665 .hactive = { 1920, 1920, 1920 },
666 .hfront_porch = { 18, 60, 74 },
667 .hback_porch = { 12, 44, 54 },
668 .hsync_len = { 10, 24, 32 },
669 .vactive = { 1080, 1080, 1080 },
670 .vfront_porch = { 6, 10, 40 },
671 .vback_porch = { 2, 5, 20 },
672 .vsync_len = { 2, 5, 20 },
673};
674
675static const struct panel_desc auo_g185han01 = {
676 .timings = &auo_g185han01_timings,
677 .num_timings = 1,
678 .bpc = 8,
679 .size = {
680 .width = 409,
681 .height = 230,
682 },
683 .delay = {
684 .prepare = 50,
685 .enable = 200,
686 .disable = 110,
687 .unprepare = 1000,
688 },
689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
690};
691
70c0d5b7
LS		 692static const struct display_timing auo_p320hvn03_timings = {
693 .pixelclock = { 106000000, 148500000, 164000000 },
694 .hactive = { 1920, 1920, 1920 },
695 .hfront_porch = { 25, 50, 130 },
696 .hback_porch = { 25, 50, 130 },
697 .hsync_len = { 20, 40, 105 },
698 .vactive = { 1080, 1080, 1080 },
699 .vfront_porch = { 8, 17, 150 },
700 .vback_porch = { 8, 17, 150 },
701 .vsync_len = { 4, 11, 100 },
702};
703
704static const struct panel_desc auo_p320hvn03 = {
705 .timings = &auo_p320hvn03_timings,
706 .num_timings = 1,
707 .bpc = 8,
708 .size = {
709 .width = 698,
710 .height = 393,
711 },
712 .delay = {
713 .prepare = 1,
714 .enable = 450,
715 .unprepare = 500,
716 },
2554f154 717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
70c0d5b7
LS		 718};
719
7ee933a1
HS		 720static const struct drm_display_mode auo_t215hvn01_mode = {
721 .clock = 148800,
722 .hdisplay = 1920,
723 .hsync_start = 1920 + 88,
724 .hsync_end = 1920 + 88 + 44,
725 .htotal = 1920 + 88 + 44 + 148,
726 .vdisplay = 1080,
727 .vsync_start = 1080 + 4,
728 .vsync_end = 1080 + 4 + 5,
729 .vtotal = 1080 + 4 + 5 + 36,
730 .vrefresh = 60,
731};
732
733static const struct panel_desc auo_t215hvn01 = {
734 .modes = &auo_t215hvn01_mode,
735 .num_modes = 1,
736 .bpc = 8,
737 .size = {
738 .width = 430,
739 .height = 270,
740 },
741 .delay = {
742 .disable = 5,
743 .unprepare = 1000,
744 }
745};
746
d47df633
PZ		 747static const struct drm_display_mode avic_tm070ddh03_mode = {
748 .clock = 51200,
749 .hdisplay = 1024,
750 .hsync_start = 1024 + 160,
751 .hsync_end = 1024 + 160 + 4,
752 .htotal = 1024 + 160 + 4 + 156,
753 .vdisplay = 600,
754 .vsync_start = 600 + 17,
755 .vsync_end = 600 + 17 + 1,
756 .vtotal = 600 + 17 + 1 + 17,
757 .vrefresh = 60,
758};
759
760static const struct panel_desc avic_tm070ddh03 = {
761 .modes = &avic_tm070ddh03_mode,
762 .num_modes = 1,
763 .bpc = 8,
764 .size = {
765 .width = 154,
766 .height = 90,
767 },
768 .delay = {
769 .prepare = 20,
770 .enable = 200,
771 .disable = 200,
772 },
773};
774
ae8cf41b
AH		 775static const struct drm_display_mode boe_hv070wsa_mode = {
776 .clock = 40800,
777 .hdisplay = 1024,
778 .hsync_start = 1024 + 90,
779 .hsync_end = 1024 + 90 + 90,
780 .htotal = 1024 + 90 + 90 + 90,
781 .vdisplay = 600,
782 .vsync_start = 600 + 3,
783 .vsync_end = 600 + 3 + 4,
784 .vtotal = 600 + 3 + 4 + 3,
785 .vrefresh = 60,
786};
787
788static const struct panel_desc boe_hv070wsa = {
789 .modes = &boe_hv070wsa_mode,
790 .num_modes = 1,
791 .size = {
792 .width = 154,
793 .height = 90,
794 },
795};
796
cac1a411
CW		 797static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
798 {
799 .clock = 71900,
800 .hdisplay = 1280,
801 .hsync_start = 1280 + 48,
802 .hsync_end = 1280 + 48 + 32,
803 .htotal = 1280 + 48 + 32 + 80,
804 .vdisplay = 800,
805 .vsync_start = 800 + 3,
806 .vsync_end = 800 + 3 + 5,
807 .vtotal = 800 + 3 + 5 + 24,
808 .vrefresh = 60,
809 },
810 {
811 .clock = 57500,
812 .hdisplay = 1280,
813 .hsync_start = 1280 + 48,
814 .hsync_end = 1280 + 48 + 32,
815 .htotal = 1280 + 48 + 32 + 80,
816 .vdisplay = 800,
817 .vsync_start = 800 + 3,
818 .vsync_end = 800 + 3 + 5,
819 .vtotal = 800 + 3 + 5 + 24,
820 .vrefresh = 48,
821 },
822};
823
824static const struct panel_desc boe_nv101wxmn51 = {
825 .modes = boe_nv101wxmn51_modes,
826 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
827 .bpc = 8,
828 .size = {
829 .width = 217,
830 .height = 136,
831 },
832 .delay = {
833 .prepare = 210,
834 .enable = 50,
835 .unprepare = 160,
836 },
837};
838
2cb35c80
RL		 839static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
840 .clock = 66770,
841 .hdisplay = 800,
842 .hsync_start = 800 + 49,
843 .hsync_end = 800 + 49 + 33,
844 .htotal = 800 + 49 + 33 + 17,
845 .vdisplay = 1280,
846 .vsync_start = 1280 + 1,
847 .vsync_end = 1280 + 1 + 7,
848 .vtotal = 1280 + 1 + 7 + 15,
849 .vrefresh = 60,
850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
851};
852
853static const struct panel_desc chunghwa_claa070wp03xg = {
854 .modes = &chunghwa_claa070wp03xg_mode,
855 .num_modes = 1,
856 .bpc = 6,
857 .size = {
858 .width = 94,
859 .height = 150,
860 },
861};
862
4c930757
SW		 863static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
864 .clock = 72070,
865 .hdisplay = 1366,
866 .hsync_start = 1366 + 58,
867 .hsync_end = 1366 + 58 + 58,
868 .htotal = 1366 + 58 + 58 + 58,
869 .vdisplay = 768,
870 .vsync_start = 768 + 4,
871 .vsync_end = 768 + 4 + 4,
872 .vtotal = 768 + 4 + 4 + 4,
873 .vrefresh = 60,
874};
875
876static const struct panel_desc chunghwa_claa101wa01a = {
877 .modes = &chunghwa_claa101wa01a_mode,
878 .num_modes = 1,
0208d511 879 .bpc = 6,
4c930757
SW		 880 .size = {
881 .width = 220,
882 .height = 120,
883 },
884};
885
280921de
TR		 886static const struct drm_display_mode chunghwa_claa101wb01_mode = {
887 .clock = 69300,
888 .hdisplay = 1366,
889 .hsync_start = 1366 + 48,
890 .hsync_end = 1366 + 48 + 32,
891 .htotal = 1366 + 48 + 32 + 20,
892 .vdisplay = 768,
893 .vsync_start = 768 + 16,
894 .vsync_end = 768 + 16 + 8,
895 .vtotal = 768 + 16 + 8 + 16,
896 .vrefresh = 60,
897};
898
899static const struct panel_desc chunghwa_claa101wb01 = {
900 .modes = &chunghwa_claa101wb01_mode,
901 .num_modes = 1,
0208d511 902 .bpc = 6,
280921de
TR		 903 .size = {
904 .width = 223,
905 .height = 125,
906 },
907};
908
97ceb1fb
MV		 909static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
910 .clock = 33260,
911 .hdisplay = 800,
912 .hsync_start = 800 + 40,
913 .hsync_end = 800 + 40 + 128,
914 .htotal = 800 + 40 + 128 + 88,
915 .vdisplay = 480,
916 .vsync_start = 480 + 10,
917 .vsync_end = 480 + 10 + 2,
918 .vtotal = 480 + 10 + 2 + 33,
919 .vrefresh = 60,
920 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
921};
922
923static const struct panel_desc dataimage_scf0700c48ggu18 = {
924 .modes = &dataimage_scf0700c48ggu18_mode,
925 .num_modes = 1,
926 .bpc = 8,
927 .size = {
928 .width = 152,
929 .height = 91,
930 },
931 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
932 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
933};
934
0ca0c827
PZ		 935static const struct display_timing dlc_dlc0700yzg_1_timing = {
936 .pixelclock = { 45000000, 51200000, 57000000 },
937 .hactive = { 1024, 1024, 1024 },
938 .hfront_porch = { 100, 106, 113 },
939 .hback_porch = { 100, 106, 113 },
940 .hsync_len = { 100, 108, 114 },
941 .vactive = { 600, 600, 600 },
942 .vfront_porch = { 8, 11, 15 },
943 .vback_porch = { 8, 11, 15 },
944 .vsync_len = { 9, 13, 15 },
945 .flags = DISPLAY_FLAGS_DE_HIGH,
946};
947
948static const struct panel_desc dlc_dlc0700yzg_1 = {
949 .timings = &dlc_dlc0700yzg_1_timing,
950 .num_timings = 1,
951 .bpc = 6,
952 .size = {
953 .width = 154,
954 .height = 86,
955 },
956 .delay = {
957 .prepare = 30,
958 .enable = 200,
959 .disable = 200,
960 },
961 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
962};
963
26ab0065
SA		 964static const struct drm_display_mode edt_et057090dhu_mode = {
965 .clock = 25175,
966 .hdisplay = 640,
967 .hsync_start = 640 + 16,
968 .hsync_end = 640 + 16 + 30,
969 .htotal = 640 + 16 + 30 + 114,
970 .vdisplay = 480,
971 .vsync_start = 480 + 10,
972 .vsync_end = 480 + 10 + 3,
973 .vtotal = 480 + 10 + 3 + 32,
974 .vrefresh = 60,
975 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
976};
977
978static const struct panel_desc edt_et057090dhu = {
979 .modes = &edt_et057090dhu_mode,
980 .num_modes = 1,
0208d511 981 .bpc = 6,
26ab0065
SA		 982 .size = {
983 .width = 115,
984 .height = 86,
985 },
eaeebffa
SA		 986 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
987 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
26ab0065
SA		 988};
989
fff5de45
PZ		 990static const struct drm_display_mode edt_etm0700g0dh6_mode = {
991 .clock = 33260,
992 .hdisplay = 800,
993 .hsync_start = 800 + 40,
994 .hsync_end = 800 + 40 + 128,
995 .htotal = 800 + 40 + 128 + 88,
996 .vdisplay = 480,
997 .vsync_start = 480 + 10,
998 .vsync_end = 480 + 10 + 2,
999 .vtotal = 480 + 10 + 2 + 33,
1000 .vrefresh = 60,
1001 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1002};
1003
1004static const struct panel_desc edt_etm0700g0dh6 = {
1005 .modes = &edt_etm0700g0dh6_mode,
1006 .num_modes = 1,
0208d511 1007 .bpc = 6,
fff5de45
PZ		 1008 .size = {
1009 .width = 152,
1010 .height = 91,
1011 },
eaeebffa
SA		 1012 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
fff5de45
PZ		 1014};
1015
aa7e6455
JT		 1016static const struct panel_desc edt_etm0700g0bdh6 = {
1017 .modes = &edt_etm0700g0dh6_mode,
1018 .num_modes = 1,
1019 .bpc = 6,
1020 .size = {
1021 .width = 152,
1022 .height = 91,
1023 },
1024 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1025 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1026};
1027
102932b0
BB		 1028static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1029 .clock = 32260,
1030 .hdisplay = 800,
1031 .hsync_start = 800 + 168,
1032 .hsync_end = 800 + 168 + 64,
1033 .htotal = 800 + 168 + 64 + 88,
1034 .vdisplay = 480,
1035 .vsync_start = 480 + 37,
1036 .vsync_end = 480 + 37 + 2,
1037 .vtotal = 480 + 37 + 2 + 8,
1038 .vrefresh = 60,
1039};
1040
1041static const struct panel_desc foxlink_fl500wvr00_a0t = {
1042 .modes = &foxlink_fl500wvr00_a0t_mode,
1043 .num_modes = 1,
d7a839cd 1044 .bpc = 8,
102932b0
BB		 1045 .size = {
1046 .width = 108,
1047 .height = 65,
1048 },
bb276cb3 1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1050};
1051
d435a2af
PZ		 1052static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1053 .clock = 9000,
1054 .hdisplay = 480,
1055 .hsync_start = 480 + 5,
1056 .hsync_end = 480 + 5 + 1,
1057 .htotal = 480 + 5 + 1 + 40,
1058 .vdisplay = 272,
1059 .vsync_start = 272 + 8,
1060 .vsync_end = 272 + 8 + 1,
1061 .vtotal = 272 + 8 + 1 + 8,
1062 .vrefresh = 60,
1063};
1064
1065static const struct panel_desc giantplus_gpg482739qs5 = {
1066 .modes = &giantplus_gpg482739qs5_mode,
1067 .num_modes = 1,
1068 .bpc = 8,
1069 .size = {
1070 .width = 95,
1071 .height = 54,
1072 },
33536a09 1073 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1074};
1075
ab07725a
PZ		 1076static const struct display_timing hannstar_hsd070pww1_timing = {
1077 .pixelclock = { 64300000, 71100000, 82000000 },
1078 .hactive = { 1280, 1280, 1280 },
1079 .hfront_porch = { 1, 1, 10 },
1080 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1081 /*
1082 * According to the data sheet, the minimum horizontal blanking interval
1083 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1084 * minimum working horizontal blanking interval to be 60 clocks.
1085 */
1086 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 1087 .vactive = { 800, 800, 800 },
1088 .vfront_porch = { 1, 1, 10 },
1089 .vback_porch = { 1, 1, 10 },
1090 .vsync_len = { 1, 21, 203 },
1091 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1092};
1093
1094static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1095 .timings = &hannstar_hsd070pww1_timing,
1096 .num_timings = 1,
a853205e
PZ		 1097 .bpc = 6,
1098 .size = {
1099 .width = 151,
1100 .height = 94,
1101 },
58d6a7bc 1102 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 1103};
1104
c0d607e5
EN		 1105static const struct display_timing hannstar_hsd100pxn1_timing = {
1106 .pixelclock = { 55000000, 65000000, 75000000 },
1107 .hactive = { 1024, 1024, 1024 },
1108 .hfront_porch = { 40, 40, 40 },
1109 .hback_porch = { 220, 220, 220 },
1110 .hsync_len = { 20, 60, 100 },
1111 .vactive = { 768, 768, 768 },
1112 .vfront_porch = { 7, 7, 7 },
1113 .vback_porch = { 21, 21, 21 },
1114 .vsync_len = { 10, 10, 10 },
1115 .flags = DISPLAY_FLAGS_DE_HIGH,
1116};
1117
1118static const struct panel_desc hannstar_hsd100pxn1 = {
1119 .timings = &hannstar_hsd100pxn1_timing,
1120 .num_timings = 1,
1121 .bpc = 6,
1122 .size = {
1123 .width = 203,
1124 .height = 152,
1125 },
4946b043 1126 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 1127};
1128
61ac0bf8
LS		 1129static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1130 .clock = 33333,
1131 .hdisplay = 800,
1132 .hsync_start = 800 + 85,
1133 .hsync_end = 800 + 85 + 86,
1134 .htotal = 800 + 85 + 86 + 85,
1135 .vdisplay = 480,
1136 .vsync_start = 480 + 16,
1137 .vsync_end = 480 + 16 + 13,
1138 .vtotal = 480 + 16 + 13 + 16,
1139 .vrefresh = 60,
1140};
1141
1142static const struct panel_desc hitachi_tx23d38vm0caa = {
1143 .modes = &hitachi_tx23d38vm0caa_mode,
1144 .num_modes = 1,
1145 .bpc = 6,
1146 .size = {
1147 .width = 195,
1148 .height = 117,
1149 },
6c684e3b
PZ		 1150 .delay = {
1151 .enable = 160,
1152 .disable = 160,
1153 },
61ac0bf8
LS		 1154};
1155
41bcceb4
NF		 1156static const struct drm_display_mode innolux_at043tn24_mode = {
1157 .clock = 9000,
1158 .hdisplay = 480,
1159 .hsync_start = 480 + 2,
1160 .hsync_end = 480 + 2 + 41,
1161 .htotal = 480 + 2 + 41 + 2,
1162 .vdisplay = 272,
1163 .vsync_start = 272 + 2,
a483159d
PZ		 1164 .vsync_end = 272 + 2 + 10,
1165 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 1166 .vrefresh = 60,
1167 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1168};
1169
1170static const struct panel_desc innolux_at043tn24 = {
1171 .modes = &innolux_at043tn24_mode,
1172 .num_modes = 1,
1173 .bpc = 8,
1174 .size = {
1175 .width = 95,
1176 .height = 54,
1177 },
1178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
6560279c 1179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
41bcceb4
NF		 1180};
1181
4fc24ab3
RB		 1182static const struct drm_display_mode innolux_at070tn92_mode = {
1183 .clock = 33333,
1184 .hdisplay = 800,
1185 .hsync_start = 800 + 210,
1186 .hsync_end = 800 + 210 + 20,
1187 .htotal = 800 + 210 + 20 + 46,
1188 .vdisplay = 480,
1189 .vsync_start = 480 + 22,
1190 .vsync_end = 480 + 22 + 10,
1191 .vtotal = 480 + 22 + 23 + 10,
1192 .vrefresh = 60,
1193};
1194
1195static const struct panel_desc innolux_at070tn92 = {
1196 .modes = &innolux_at070tn92_mode,
1197 .num_modes = 1,
1198 .size = {
1199 .width = 154,
1200 .height = 86,
1201 },
1202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1203};
1204
a5d2ade6
CF		 1205static const struct display_timing innolux_g070y2_l01_timing = {
1206 .pixelclock = { 28000000, 29500000, 32000000 },
1207 .hactive = { 800, 800, 800 },
1208 .hfront_porch = { 61, 91, 141 },
1209 .hback_porch = { 60, 90, 140 },
1210 .hsync_len = { 12, 12, 12 },
1211 .vactive = { 480, 480, 480 },
1212 .vfront_porch = { 4, 9, 30 },
1213 .vback_porch = { 4, 8, 28 },
1214 .vsync_len = { 2, 2, 2 },
1215 .flags = DISPLAY_FLAGS_DE_HIGH,
1216};
1217
1218static const struct panel_desc innolux_g070y2_l01 = {
1219 .timings = &innolux_g070y2_l01_timing,
1220 .num_timings = 1,
1221 .bpc = 6,
1222 .size = {
1223 .width = 152,
1224 .height = 91,
1225 },
1226 .delay = {
1227 .prepare = 10,
1228 .enable = 100,
1229 .disable = 100,
1230 .unprepare = 800,
1231 },
1232 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1233};
1234
1e29b840
MO		 1235static const struct display_timing innolux_g101ice_l01_timing = {
1236 .pixelclock = { 60400000, 71100000, 74700000 },
1237 .hactive = { 1280, 1280, 1280 },
1238 .hfront_porch = { 41, 80, 100 },
1239 .hback_porch = { 40, 79, 99 },
1240 .hsync_len = { 1, 1, 1 },
1241 .vactive = { 800, 800, 800 },
1242 .vfront_porch = { 5, 11, 14 },
1243 .vback_porch = { 4, 11, 14 },
1244 .vsync_len = { 1, 1, 1 },
1245 .flags = DISPLAY_FLAGS_DE_HIGH,
1246};
1247
1248static const struct panel_desc innolux_g101ice_l01 = {
1249 .timings = &innolux_g101ice_l01_timing,
1250 .num_timings = 1,
1251 .bpc = 8,
1252 .size = {
1253 .width = 217,
1254 .height = 135,
1255 },
1256 .delay = {
1257 .enable = 200,
1258 .disable = 200,
1259 },
1260 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1261};
1262
4ae13e48
LS		 1263static const struct display_timing innolux_g121i1_l01_timing = {
1264 .pixelclock = { 67450000, 71000000, 74550000 },
1265 .hactive = { 1280, 1280, 1280 },
1266 .hfront_porch = { 40, 80, 160 },
1267 .hback_porch = { 39, 79, 159 },
1268 .hsync_len = { 1, 1, 1 },
1269 .vactive = { 800, 800, 800 },
1270 .vfront_porch = { 5, 11, 100 },
1271 .vback_porch = { 4, 11, 99 },
1272 .vsync_len = { 1, 1, 1 },
d731f661
LS		 1273};
1274
1275static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 1276 .timings = &innolux_g121i1_l01_timing,
1277 .num_timings = 1,
d731f661
LS		 1278 .bpc = 6,
1279 .size = {
1280 .width = 261,
1281 .height = 163,
1282 },
4ae13e48
LS		 1283 .delay = {
1284 .enable = 200,
1285 .disable = 20,
1286 },
1287 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
d731f661
LS		 1288};
1289
f8fa17ba
AB		 1290static const struct drm_display_mode innolux_g121x1_l03_mode = {
1291 .clock = 65000,
1292 .hdisplay = 1024,
1293 .hsync_start = 1024 + 0,
1294 .hsync_end = 1024 + 1,
1295 .htotal = 1024 + 0 + 1 + 320,
1296 .vdisplay = 768,
1297 .vsync_start = 768 + 38,
1298 .vsync_end = 768 + 38 + 1,
1299 .vtotal = 768 + 38 + 1 + 0,
1300 .vrefresh = 60,
2e8c5eb9 1301 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 1302};
1303
1304static const struct panel_desc innolux_g121x1_l03 = {
1305 .modes = &innolux_g121x1_l03_mode,
1306 .num_modes = 1,
1307 .bpc = 6,
1308 .size = {
1309 .width = 246,
1310 .height = 185,
1311 },
1312 .delay = {
1313 .enable = 200,
1314 .unprepare = 200,
1315 .disable = 400,
1316 },
1317};
1318
0a2288c0 1319static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 1320 .clock = 76420,
0a2288c0 1321 .hdisplay = 1366,
7fe8c777
DK		 1322 .hsync_start = 1366 + 136,
1323 .hsync_end = 1366 + 136 + 30,
1324 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 1325 .vdisplay = 768,
1326 .vsync_start = 768 + 8,
7fe8c777
DK		 1327 .vsync_end = 768 + 8 + 12,
1328 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 1329 .vrefresh = 60,
1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1331};
1332
1333static const struct panel_desc innolux_n116bge = {
1334 .modes = &innolux_n116bge_mode,
1335 .num_modes = 1,
1336 .bpc = 6,
1337 .size = {
1338 .width = 256,
1339 .height = 144,
1340 },
1341};
1342
ea44739d
AB		 1343static const struct drm_display_mode innolux_n156bge_l21_mode = {
1344 .clock = 69300,
1345 .hdisplay = 1366,
1346 .hsync_start = 1366 + 16,
1347 .hsync_end = 1366 + 16 + 34,
1348 .htotal = 1366 + 16 + 34 + 50,
1349 .vdisplay = 768,
1350 .vsync_start = 768 + 2,
1351 .vsync_end = 768 + 2 + 6,
1352 .vtotal = 768 + 2 + 6 + 12,
1353 .vrefresh = 60,
1354};
1355
1356static const struct panel_desc innolux_n156bge_l21 = {
1357 .modes = &innolux_n156bge_l21_mode,
1358 .num_modes = 1,
0208d511 1359 .bpc = 6,
ea44739d
AB		 1360 .size = {
1361 .width = 344,
1362 .height = 193,
1363 },
1364};
1365
da50bd42 1366static const struct drm_display_mode innolux_tv123wam_mode = {
1367 .clock = 206016,
1368 .hdisplay = 2160,
1369 .hsync_start = 2160 + 48,
1370 .hsync_end = 2160 + 48 + 32,
1371 .htotal = 2160 + 48 + 32 + 80,
1372 .vdisplay = 1440,
1373 .vsync_start = 1440 + 3,
1374 .vsync_end = 1440 + 3 + 10,
1375 .vtotal = 1440 + 3 + 10 + 27,
1376 .vrefresh = 60,
1377 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1378};
1379
1380static const struct panel_desc innolux_tv123wam = {
1381 .modes = &innolux_tv123wam_mode,
1382 .num_modes = 1,
1383 .bpc = 8,
1384 .size = {
1385 .width = 259,
1386 .height = 173,
1387 },
22fd99e9
SP		 1388 .delay = {
1389 .unprepare = 500,
1390 },
da50bd42 1391};
1392
bccac3f1
MG		 1393static const struct drm_display_mode innolux_zj070na_01p_mode = {
1394 .clock = 51501,
1395 .hdisplay = 1024,
1396 .hsync_start = 1024 + 128,
1397 .hsync_end = 1024 + 128 + 64,
1398 .htotal = 1024 + 128 + 64 + 128,
1399 .vdisplay = 600,
1400 .vsync_start = 600 + 16,
1401 .vsync_end = 600 + 16 + 4,
1402 .vtotal = 600 + 16 + 4 + 16,
1403 .vrefresh = 60,
1404};
1405
1406static const struct panel_desc innolux_zj070na_01p = {
1407 .modes = &innolux_zj070na_01p_mode,
1408 .num_modes = 1,
1409 .bpc = 6,
1410 .size = {
81598846
TR		 1411 .width = 154,
1412 .height = 90,
bccac3f1
MG		 1413 },
1414};
1415
8cfe8341
JT		 1416static const struct display_timing koe_tx31d200vm0baa_timing = {
1417 .pixelclock = { 39600000, 43200000, 48000000 },
1418 .hactive = { 1280, 1280, 1280 },
1419 .hfront_porch = { 16, 36, 56 },
1420 .hback_porch = { 16, 36, 56 },
1421 .hsync_len = { 8, 8, 8 },
1422 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 1423 .vfront_porch = { 6, 21, 33 },
1424 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 1425 .vsync_len = { 8, 8, 8 },
1426 .flags = DISPLAY_FLAGS_DE_HIGH,
1427};
1428
1429static const struct panel_desc koe_tx31d200vm0baa = {
1430 .timings = &koe_tx31d200vm0baa_timing,
1431 .num_timings = 1,
1432 .bpc = 6,
1433 .size = {
1434 .width = 292,
1435 .height = 109,
1436 },
1437 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1438};
1439
8def22e5
LS		 1440static const struct display_timing kyo_tcg121xglp_timing = {
1441 .pixelclock = { 52000000, 65000000, 71000000 },
1442 .hactive = { 1024, 1024, 1024 },
1443 .hfront_porch = { 2, 2, 2 },
1444 .hback_porch = { 2, 2, 2 },
1445 .hsync_len = { 86, 124, 244 },
1446 .vactive = { 768, 768, 768 },
1447 .vfront_porch = { 2, 2, 2 },
1448 .vback_porch = { 2, 2, 2 },
1449 .vsync_len = { 6, 34, 73 },
1450 .flags = DISPLAY_FLAGS_DE_HIGH,
1451};
1452
1453static const struct panel_desc kyo_tcg121xglp = {
1454 .timings = &kyo_tcg121xglp_timing,
1455 .num_timings = 1,
1456 .bpc = 8,
1457 .size = {
1458 .width = 246,
1459 .height = 184,
1460 },
1461 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1462};
1463
dd015002
HS		 1464static const struct drm_display_mode lg_lb070wv8_mode = {
1465 .clock = 33246,
1466 .hdisplay = 800,
1467 .hsync_start = 800 + 88,
1468 .hsync_end = 800 + 88 + 80,
1469 .htotal = 800 + 88 + 80 + 88,
1470 .vdisplay = 480,
1471 .vsync_start = 480 + 10,
1472 .vsync_end = 480 + 10 + 25,
1473 .vtotal = 480 + 10 + 25 + 10,
1474 .vrefresh = 60,
1475};
1476
1477static const struct panel_desc lg_lb070wv8 = {
1478 .modes = &lg_lb070wv8_mode,
1479 .num_modes = 1,
1480 .bpc = 16,
1481 .size = {
1482 .width = 151,
1483 .height = 91,
1484 },
1485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1486};
1487
c5ece402
YY		 1488static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1489 .clock = 200000,
1490 .hdisplay = 1536,
1491 .hsync_start = 1536 + 12,
1492 .hsync_end = 1536 + 12 + 16,
1493 .htotal = 1536 + 12 + 16 + 48,
1494 .vdisplay = 2048,
1495 .vsync_start = 2048 + 8,
1496 .vsync_end = 2048 + 8 + 4,
1497 .vtotal = 2048 + 8 + 4 + 8,
1498 .vrefresh = 60,
1499 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1500};
1501
1502static const struct panel_desc lg_lp079qx1_sp0v = {
1503 .modes = &lg_lp079qx1_sp0v_mode,
1504 .num_modes = 1,
1505 .size = {
1506 .width = 129,
1507 .height = 171,
1508 },
1509};
1510
0355dde2
YY		 1511static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1512 .clock = 205210,
1513 .hdisplay = 2048,
1514 .hsync_start = 2048 + 150,
1515 .hsync_end = 2048 + 150 + 5,
1516 .htotal = 2048 + 150 + 5 + 5,
1517 .vdisplay = 1536,
1518 .vsync_start = 1536 + 3,
1519 .vsync_end = 1536 + 3 + 1,
1520 .vtotal = 1536 + 3 + 1 + 9,
1521 .vrefresh = 60,
1522};
1523
1524static const struct panel_desc lg_lp097qx1_spa1 = {
1525 .modes = &lg_lp097qx1_spa1_mode,
1526 .num_modes = 1,
1527 .size = {
1528 .width = 208,
1529 .height = 147,
1530 },
1531};
1532
690d8fa7
JS		 1533static const struct drm_display_mode lg_lp120up1_mode = {
1534 .clock = 162300,
1535 .hdisplay = 1920,
1536 .hsync_start = 1920 + 40,
1537 .hsync_end = 1920 + 40 + 40,
1538 .htotal = 1920 + 40 + 40+ 80,
1539 .vdisplay = 1280,
1540 .vsync_start = 1280 + 4,
1541 .vsync_end = 1280 + 4 + 4,
1542 .vtotal = 1280 + 4 + 4 + 12,
1543 .vrefresh = 60,
1544};
1545
1546static const struct panel_desc lg_lp120up1 = {
1547 .modes = &lg_lp120up1_mode,
1548 .num_modes = 1,
1549 .bpc = 8,
1550 .size = {
1551 .width = 267,
1552 .height = 183,
1553 },
1554};
1555
ec7c5653
TR		 1556static const struct drm_display_mode lg_lp129qe_mode = {
1557 .clock = 285250,
1558 .hdisplay = 2560,
1559 .hsync_start = 2560 + 48,
1560 .hsync_end = 2560 + 48 + 32,
1561 .htotal = 2560 + 48 + 32 + 80,
1562 .vdisplay = 1700,
1563 .vsync_start = 1700 + 3,
1564 .vsync_end = 1700 + 3 + 10,
1565 .vtotal = 1700 + 3 + 10 + 36,
1566 .vrefresh = 60,
1567};
1568
1569static const struct panel_desc lg_lp129qe = {
1570 .modes = &lg_lp129qe_mode,
1571 .num_modes = 1,
0208d511 1572 .bpc = 8,
ec7c5653
TR		 1573 .size = {
1574 .width = 272,
1575 .height = 181,
1576 },
1577};
1578
65c766ca
LM		 1579static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
1580 .clock = 30400,
1581 .hdisplay = 800,
1582 .hsync_start = 800 + 0,
1583 .hsync_end = 800 + 1,
1584 .htotal = 800 + 0 + 1 + 160,
1585 .vdisplay = 480,
1586 .vsync_start = 480 + 0,
1587 .vsync_end = 480 + 48 + 1,
1588 .vtotal = 480 + 48 + 1 + 0,
1589 .vrefresh = 60,
1590 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1591};
1592
1593static const struct panel_desc mitsubishi_aa070mc01 = {
1594 .modes = &mitsubishi_aa070mc01_mode,
1595 .num_modes = 1,
1596 .bpc = 8,
1597 .size = {
1598 .width = 152,
1599 .height = 91,
1600 },
1601
1602 .delay = {
1603 .enable = 200,
1604 .unprepare = 200,
1605 .disable = 400,
1606 },
1607 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1608 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1609};
1610
01bacc13
LS		 1611static const struct display_timing nec_nl12880bc20_05_timing = {
1612 .pixelclock = { 67000000, 71000000, 75000000 },
1613 .hactive = { 1280, 1280, 1280 },
1614 .hfront_porch = { 2, 30, 30 },
1615 .hback_porch = { 6, 100, 100 },
1616 .hsync_len = { 2, 30, 30 },
1617 .vactive = { 800, 800, 800 },
1618 .vfront_porch = { 5, 5, 5 },
1619 .vback_porch = { 11, 11, 11 },
1620 .vsync_len = { 7, 7, 7 },
1621};
1622
1623static const struct panel_desc nec_nl12880bc20_05 = {
1624 .timings = &nec_nl12880bc20_05_timing,
1625 .num_timings = 1,
1626 .bpc = 8,
1627 .size = {
1628 .width = 261,
1629 .height = 163,
1630 },
1631 .delay = {
1632 .enable = 50,
1633 .disable = 50,
1634 },
1635 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1636};
1637
c6e87f91 1638static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1639 .clock = 10870,
1640 .hdisplay = 480,
1641 .hsync_start = 480 + 2,
1642 .hsync_end = 480 + 2 + 41,
1643 .htotal = 480 + 2 + 41 + 2,
1644 .vdisplay = 272,
1645 .vsync_start = 272 + 2,
1646 .vsync_end = 272 + 2 + 4,
1647 .vtotal = 272 + 2 + 4 + 2,
1648 .vrefresh = 74,
4bc390c6 1649 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 1650};
1651
1652static const struct panel_desc nec_nl4827hc19_05b = {
1653 .modes = &nec_nl4827hc19_05b_mode,
1654 .num_modes = 1,
1655 .bpc = 8,
1656 .size = {
1657 .width = 95,
1658 .height = 54,
1659 },
2c80661d
SA		 1660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1661 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
c6e87f91 1662};
1663
e6c2f066
MR		 1664static const struct drm_display_mode netron_dy_e231732_mode = {
1665 .clock = 66000,
1666 .hdisplay = 1024,
1667 .hsync_start = 1024 + 160,
1668 .hsync_end = 1024 + 160 + 70,
1669 .htotal = 1024 + 160 + 70 + 90,
1670 .vdisplay = 600,
1671 .vsync_start = 600 + 127,
1672 .vsync_end = 600 + 127 + 20,
1673 .vtotal = 600 + 127 + 20 + 3,
1674 .vrefresh = 60,
1675};
1676
1677static const struct panel_desc netron_dy_e231732 = {
1678 .modes = &netron_dy_e231732_mode,
1679 .num_modes = 1,
1680 .size = {
1681 .width = 154,
1682 .height = 87,
1683 },
1684 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1685};
1686
3b39ad7a
TV		 1687static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
1688 .clock = 9000,
1689 .hdisplay = 480,
1690 .hsync_start = 480 + 2,
1691 .hsync_end = 480 + 2 + 41,
1692 .htotal = 480 + 2 + 41 + 2,
1693 .vdisplay = 272,
1694 .vsync_start = 272 + 2,
1695 .vsync_end = 272 + 2 + 10,
1696 .vtotal = 272 + 2 + 10 + 2,
1697 .vrefresh = 60,
1698 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1699};
1700
1701static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
1702 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
1703 .num_modes = 1,
1704 .bpc = 8,
1705 .size = {
1706 .width = 95,
1707 .height = 54,
1708 },
1709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1710 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
1711 DRM_BUS_FLAG_SYNC_POSEDGE,
1712};
1713
4177fa66
LS		 1714static const struct display_timing nlt_nl192108ac18_02d_timing = {
1715 .pixelclock = { 130000000, 148350000, 163000000 },
1716 .hactive = { 1920, 1920, 1920 },
1717 .hfront_porch = { 80, 100, 100 },
1718 .hback_porch = { 100, 120, 120 },
1719 .hsync_len = { 50, 60, 60 },
1720 .vactive = { 1080, 1080, 1080 },
1721 .vfront_porch = { 12, 30, 30 },
1722 .vback_porch = { 4, 10, 10 },
1723 .vsync_len = { 4, 5, 5 },
1724};
1725
1726static const struct panel_desc nlt_nl192108ac18_02d = {
1727 .timings = &nlt_nl192108ac18_02d_timing,
1728 .num_timings = 1,
1729 .bpc = 8,
1730 .size = {
1731 .width = 344,
1732 .height = 194,
1733 },
1734 .delay = {
1735 .unprepare = 500,
1736 },
1737 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1738};
1739
05ec0e45
FL		 1740static const struct drm_display_mode nvd_9128_mode = {
1741 .clock = 29500,
1742 .hdisplay = 800,
1743 .hsync_start = 800 + 130,
1744 .hsync_end = 800 + 130 + 98,
1745 .htotal = 800 + 0 + 130 + 98,
1746 .vdisplay = 480,
1747 .vsync_start = 480 + 10,
1748 .vsync_end = 480 + 10 + 50,
1749 .vtotal = 480 + 0 + 10 + 50,
1750};
1751
1752static const struct panel_desc nvd_9128 = {
1753 .modes = &nvd_9128_mode,
1754 .num_modes = 1,
1755 .bpc = 8,
1756 .size = {
1757 .width = 156,
1758 .height = 88,
1759 },
1760 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1761};
1762
a99fb626
GB		 1763static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1764 .pixelclock = { 30000000, 30000000, 40000000 },
1765 .hactive = { 800, 800, 800 },
1766 .hfront_porch = { 40, 40, 40 },
1767 .hback_porch = { 40, 40, 40 },
1768 .hsync_len = { 1, 48, 48 },
1769 .vactive = { 480, 480, 480 },
1770 .vfront_porch = { 13, 13, 13 },
1771 .vback_porch = { 29, 29, 29 },
1772 .vsync_len = { 3, 3, 3 },
1773 .flags = DISPLAY_FLAGS_DE_HIGH,
1774};
1775
1776static const struct panel_desc okaya_rs800480t_7x0gp = {
1777 .timings = &okaya_rs800480t_7x0gp_timing,
1778 .num_timings = 1,
1779 .bpc = 6,
1780 .size = {
1781 .width = 154,
1782 .height = 87,
1783 },
1784 .delay = {
1785 .prepare = 41,
1786 .enable = 50,
1787 .unprepare = 41,
1788 .disable = 50,
1789 },
1790 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1791};
1792
cf5c9e6d
MR		 1793static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1794 .clock = 9000,
1795 .hdisplay = 480,
1796 .hsync_start = 480 + 5,
1797 .hsync_end = 480 + 5 + 30,
1798 .htotal = 480 + 5 + 30 + 10,
1799 .vdisplay = 272,
1800 .vsync_start = 272 + 8,
1801 .vsync_end = 272 + 8 + 5,
1802 .vtotal = 272 + 8 + 5 + 3,
1803 .vrefresh = 60,
1804};
1805
1806static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1807 .modes = &olimex_lcd_olinuxino_43ts_mode,
1808 .num_modes = 1,
1809 .size = {
30c6d7ab
JL		 1810 .width = 95,
1811 .height = 54,
cf5c9e6d 1812 },
5c2a7c6b 1813 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 1814};
1815
e8b6f561
EA		 1816/*
1817 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1818 * pixel clocks, but this is the timing that was being used in the Adafruit
1819 * installation instructions.
1820 */
1821static const struct drm_display_mode ontat_yx700wv03_mode = {
1822 .clock = 29500,
1823 .hdisplay = 800,
1824 .hsync_start = 824,
1825 .hsync_end = 896,
1826 .htotal = 992,
1827 .vdisplay = 480,
1828 .vsync_start = 483,
1829 .vsync_end = 493,
1830 .vtotal = 500,
1831 .vrefresh = 60,
1832 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1833};
1834
1835/*
1836 * Specification at:
1837 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1838 */
1839static const struct panel_desc ontat_yx700wv03 = {
1840 .modes = &ontat_yx700wv03_mode,
1841 .num_modes = 1,
1842 .bpc = 8,
1843 .size = {
1844 .width = 154,
1845 .height = 83,
1846 },
5651e5e0 1847 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 1848};
1849
725c9d40
PZ		 1850static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1851 .clock = 25000,
1852 .hdisplay = 480,
1853 .hsync_start = 480 + 10,
1854 .hsync_end = 480 + 10 + 10,
1855 .htotal = 480 + 10 + 10 + 15,
1856 .vdisplay = 800,
1857 .vsync_start = 800 + 3,
1858 .vsync_end = 800 + 3 + 3,
1859 .vtotal = 800 + 3 + 3 + 3,
1860 .vrefresh = 60,
1861};
1862
1863static const struct panel_desc ortustech_com43h4m85ulc = {
1864 .modes = &ortustech_com43h4m85ulc_mode,
1865 .num_modes = 1,
1866 .bpc = 8,
1867 .size = {
1868 .width = 56,
1869 .height = 93,
1870 },
1871 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
e0932f9d 1872 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
725c9d40
PZ		 1873};
1874
d2a6f0f5
JW		 1875static const struct drm_display_mode qd43003c0_40_mode = {
1876 .clock = 9000,
1877 .hdisplay = 480,
1878 .hsync_start = 480 + 8,
1879 .hsync_end = 480 + 8 + 4,
1880 .htotal = 480 + 8 + 4 + 39,
1881 .vdisplay = 272,
1882 .vsync_start = 272 + 4,
1883 .vsync_end = 272 + 4 + 10,
1884 .vtotal = 272 + 4 + 10 + 2,
1885 .vrefresh = 60,
1886};
1887
1888static const struct panel_desc qd43003c0_40 = {
1889 .modes = &qd43003c0_40_mode,
1890 .num_modes = 1,
1891 .bpc = 8,
1892 .size = {
1893 .width = 95,
1894 .height = 53,
1895 },
1896 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1897};
1898
23167fa9
JT		 1899static const struct display_timing rocktech_rk070er9427_timing = {
1900 .pixelclock = { 26400000, 33300000, 46800000 },
1901 .hactive = { 800, 800, 800 },
1902 .hfront_porch = { 16, 210, 354 },
1903 .hback_porch = { 46, 46, 46 },
1904 .hsync_len = { 1, 1, 1 },
1905 .vactive = { 480, 480, 480 },
1906 .vfront_porch = { 7, 22, 147 },
1907 .vback_porch = { 23, 23, 23 },
1908 .vsync_len = { 1, 1, 1 },
1909 .flags = DISPLAY_FLAGS_DE_HIGH,
1910};
1911
1912static const struct panel_desc rocktech_rk070er9427 = {
1913 .timings = &rocktech_rk070er9427_timing,
1914 .num_timings = 1,
1915 .bpc = 6,
1916 .size = {
1917 .width = 154,
1918 .height = 86,
1919 },
1920 .delay = {
1921 .prepare = 41,
1922 .enable = 50,
1923 .unprepare = 41,
1924 .disable = 50,
1925 },
1926 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1927};
1928
0330eaf3
YY		 1929static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1930 .clock = 271560,
1931 .hdisplay = 2560,
1932 .hsync_start = 2560 + 48,
1933 .hsync_end = 2560 + 48 + 32,
1934 .htotal = 2560 + 48 + 32 + 80,
1935 .vdisplay = 1600,
1936 .vsync_start = 1600 + 2,
1937 .vsync_end = 1600 + 2 + 5,
1938 .vtotal = 1600 + 2 + 5 + 57,
1939 .vrefresh = 60,
1940};
1941
1942static const struct panel_desc samsung_lsn122dl01_c01 = {
1943 .modes = &samsung_lsn122dl01_c01_mode,
1944 .num_modes = 1,
1945 .size = {
1946 .width = 263,
1947 .height = 164,
1948 },
1949};
1950
6d54e3d2
MD		 1951static const struct drm_display_mode samsung_ltn101nt05_mode = {
1952 .clock = 54030,
1953 .hdisplay = 1024,
1954 .hsync_start = 1024 + 24,
1955 .hsync_end = 1024 + 24 + 136,
1956 .htotal = 1024 + 24 + 136 + 160,
1957 .vdisplay = 600,
1958 .vsync_start = 600 + 3,
1959 .vsync_end = 600 + 3 + 6,
1960 .vtotal = 600 + 3 + 6 + 61,
1961 .vrefresh = 60,
1962};
1963
1964static const struct panel_desc samsung_ltn101nt05 = {
1965 .modes = &samsung_ltn101nt05_mode,
1966 .num_modes = 1,
0208d511 1967 .bpc = 6,
6d54e3d2 1968 .size = {
81598846
TR		 1969 .width = 223,
1970 .height = 125,
6d54e3d2
MD		 1971 },
1972};
1973
0c934306
SM		 1974static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1975 .clock = 76300,
1976 .hdisplay = 1366,
1977 .hsync_start = 1366 + 64,
1978 .hsync_end = 1366 + 64 + 48,
1979 .htotal = 1366 + 64 + 48 + 128,
1980 .vdisplay = 768,
1981 .vsync_start = 768 + 2,
1982 .vsync_end = 768 + 2 + 5,
1983 .vtotal = 768 + 2 + 5 + 17,
1984 .vrefresh = 60,
1985};
1986
1987static const struct panel_desc samsung_ltn140at29_301 = {
1988 .modes = &samsung_ltn140at29_301_mode,
1989 .num_modes = 1,
1990 .bpc = 6,
1991 .size = {
1992 .width = 320,
1993 .height = 187,
1994 },
1995};
1996
03e3ec9a
VZ		 1997static const struct drm_display_mode sharp_lq035q7db03_mode = {
1998 .clock = 5500,
1999 .hdisplay = 240,
2000 .hsync_start = 240 + 16,
2001 .hsync_end = 240 + 16 + 7,
2002 .htotal = 240 + 16 + 7 + 5,
2003 .vdisplay = 320,
2004 .vsync_start = 320 + 9,
2005 .vsync_end = 320 + 9 + 1,
2006 .vtotal = 320 + 9 + 1 + 7,
2007 .vrefresh = 60,
2008};
2009
2010static const struct panel_desc sharp_lq035q7db03 = {
2011 .modes = &sharp_lq035q7db03_mode,
2012 .num_modes = 1,
2013 .bpc = 6,
2014 .size = {
2015 .width = 54,
2016 .height = 72,
2017 },
2018 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2019};
2020
592aa02b
JC		 2021static const struct display_timing sharp_lq101k1ly04_timing = {
2022 .pixelclock = { 60000000, 65000000, 80000000 },
2023 .hactive = { 1280, 1280, 1280 },
2024 .hfront_porch = { 20, 20, 20 },
2025 .hback_porch = { 20, 20, 20 },
2026 .hsync_len = { 10, 10, 10 },
2027 .vactive = { 800, 800, 800 },
2028 .vfront_porch = { 4, 4, 4 },
2029 .vback_porch = { 4, 4, 4 },
2030 .vsync_len = { 4, 4, 4 },
2031 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2032};
2033
2034static const struct panel_desc sharp_lq101k1ly04 = {
2035 .timings = &sharp_lq101k1ly04_timing,
2036 .num_timings = 1,
2037 .bpc = 8,
2038 .size = {
2039 .width = 217,
2040 .height = 136,
2041 },
2042 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2043};
2044
9f7bae2d
SP		 2045static const struct display_timing sharp_lq123p1jx31_timing = {
2046 .pixelclock = { 252750000, 252750000, 266604720 },
2047 .hactive = { 2400, 2400, 2400 },
2048 .hfront_porch = { 48, 48, 48 },
2049 .hback_porch = { 80, 80, 84 },
2050 .hsync_len = { 32, 32, 32 },
2051 .vactive = { 1600, 1600, 1600 },
2052 .vfront_porch = { 3, 3, 3 },
2053 .vback_porch = { 33, 33, 120 },
2054 .vsync_len = { 10, 10, 10 },
2055 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 2056};
2057
2058static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 2059 .timings = &sharp_lq123p1jx31_timing,
2060 .num_timings = 1,
5466a631 2061 .bpc = 8,
739c7de9
YY		 2062 .size = {
2063 .width = 259,
2064 .height = 173,
2065 },
a42f6e3f
YY		 2066 .delay = {
2067 .prepare = 110,
2068 .enable = 50,
2069 .unprepare = 550,
2070 },
739c7de9
YY		 2071};
2072
0f9cdd74
GL		 2073static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2074 .clock = 71100,
2075 .hdisplay = 1024,
2076 .hsync_start = 1024 + 168,
2077 .hsync_end = 1024 + 168 + 64,
2078 .htotal = 1024 + 168 + 64 + 88,
2079 .vdisplay = 768,
2080 .vsync_start = 768 + 37,
2081 .vsync_end = 768 + 37 + 2,
2082 .vtotal = 768 + 37 + 2 + 8,
2083 .vrefresh = 60,
2084};
2085
2086static const struct panel_desc sharp_lq150x1lg11 = {
2087 .modes = &sharp_lq150x1lg11_mode,
2088 .num_modes = 1,
2089 .bpc = 6,
2090 .size = {
2091 .width = 304,
2092 .height = 228,
2093 },
2094 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2095};
2096
9c6615bc
BB		 2097static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2098 .clock = 33300,
2099 .hdisplay = 800,
2100 .hsync_start = 800 + 1,
2101 .hsync_end = 800 + 1 + 64,
2102 .htotal = 800 + 1 + 64 + 64,
2103 .vdisplay = 480,
2104 .vsync_start = 480 + 1,
2105 .vsync_end = 480 + 1 + 23,
2106 .vtotal = 480 + 1 + 23 + 22,
2107 .vrefresh = 60,
2108};
2109
2110static const struct panel_desc shelly_sca07010_bfn_lnn = {
2111 .modes = &shelly_sca07010_bfn_lnn_mode,
2112 .num_modes = 1,
2113 .size = {
2114 .width = 152,
2115 .height = 91,
2116 },
2117 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2118};
2119
9bb34c4c
DA		 2120static const struct drm_display_mode starry_kr122ea0sra_mode = {
2121 .clock = 147000,
2122 .hdisplay = 1920,
2123 .hsync_start = 1920 + 16,
2124 .hsync_end = 1920 + 16 + 16,
2125 .htotal = 1920 + 16 + 16 + 32,
2126 .vdisplay = 1200,
2127 .vsync_start = 1200 + 15,
2128 .vsync_end = 1200 + 15 + 2,
2129 .vtotal = 1200 + 15 + 2 + 18,
2130 .vrefresh = 60,
2131 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2132};
2133
2134static const struct panel_desc starry_kr122ea0sra = {
2135 .modes = &starry_kr122ea0sra_mode,
2136 .num_modes = 1,
2137 .size = {
2138 .width = 263,
2139 .height = 164,
2140 },
c46b924b
BN		 2141 .delay = {
2142 .prepare = 10 + 200,
2143 .enable = 50,
2144 .unprepare = 10 + 500,
2145 },
9bb34c4c
DA		 2146};
2147
adb973ef
GB		 2148static const struct display_timing tianma_tm070jdhg30_timing = {
2149 .pixelclock = { 62600000, 68200000, 78100000 },
2150 .hactive = { 1280, 1280, 1280 },
2151 .hfront_porch = { 15, 64, 159 },
2152 .hback_porch = { 5, 5, 5 },
2153 .hsync_len = { 1, 1, 256 },
2154 .vactive = { 800, 800, 800 },
2155 .vfront_porch = { 3, 40, 99 },
2156 .vback_porch = { 2, 2, 2 },
2157 .vsync_len = { 1, 1, 128 },
2158 .flags = DISPLAY_FLAGS_DE_HIGH,
2159};
2160
2161static const struct panel_desc tianma_tm070jdhg30 = {
2162 .timings = &tianma_tm070jdhg30_timing,
2163 .num_timings = 1,
2164 .bpc = 8,
2165 .size = {
2166 .width = 151,
2167 .height = 95,
2168 },
2169 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2170};
2171
870a0b12
LM		 2172static const struct display_timing tianma_tm070rvhg71_timing = {
2173 .pixelclock = { 27700000, 29200000, 39600000 },
2174 .hactive = { 800, 800, 800 },
2175 .hfront_porch = { 12, 40, 212 },
2176 .hback_porch = { 88, 88, 88 },
2177 .hsync_len = { 1, 1, 40 },
2178 .vactive = { 480, 480, 480 },
2179 .vfront_porch = { 1, 13, 88 },
2180 .vback_porch = { 32, 32, 32 },
2181 .vsync_len = { 1, 1, 3 },
2182 .flags = DISPLAY_FLAGS_DE_HIGH,
2183};
2184
2185static const struct panel_desc tianma_tm070rvhg71 = {
2186 .timings = &tianma_tm070rvhg71_timing,
2187 .num_timings = 1,
2188 .bpc = 8,
2189 .size = {
2190 .width = 154,
2191 .height = 86,
2192 },
2193 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2194};
2195
06e733e4
LS		 2196static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2197 .clock = 79500,
2198 .hdisplay = 1280,
2199 .hsync_start = 1280 + 192,
2200 .hsync_end = 1280 + 192 + 128,
2201 .htotal = 1280 + 192 + 128 + 64,
2202 .vdisplay = 768,
2203 .vsync_start = 768 + 20,
2204 .vsync_end = 768 + 20 + 7,
2205 .vtotal = 768 + 20 + 7 + 3,
2206 .vrefresh = 60,
2207};
2208
2209static const struct panel_desc toshiba_lt089ac29000 = {
2210 .modes = &toshiba_lt089ac29000_mode,
2211 .num_modes = 1,
2212 .size = {
2213 .width = 194,
2214 .height = 116,
2215 },
2216 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2217 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2218};
2219
227e4f40
BD		 2220static const struct drm_display_mode tpk_f07a_0102_mode = {
2221 .clock = 33260,
2222 .hdisplay = 800,
2223 .hsync_start = 800 + 40,
2224 .hsync_end = 800 + 40 + 128,
2225 .htotal = 800 + 40 + 128 + 88,
2226 .vdisplay = 480,
2227 .vsync_start = 480 + 10,
2228 .vsync_end = 480 + 10 + 2,
2229 .vtotal = 480 + 10 + 2 + 33,
2230 .vrefresh = 60,
2231};
2232
2233static const struct panel_desc tpk_f07a_0102 = {
2234 .modes = &tpk_f07a_0102_mode,
2235 .num_modes = 1,
2236 .size = {
2237 .width = 152,
2238 .height = 91,
2239 },
2240 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2241};
2242
2243static const struct drm_display_mode tpk_f10a_0102_mode = {
2244 .clock = 45000,
2245 .hdisplay = 1024,
2246 .hsync_start = 1024 + 176,
2247 .hsync_end = 1024 + 176 + 5,
2248 .htotal = 1024 + 176 + 5 + 88,
2249 .vdisplay = 600,
2250 .vsync_start = 600 + 20,
2251 .vsync_end = 600 + 20 + 5,
2252 .vtotal = 600 + 20 + 5 + 25,
2253 .vrefresh = 60,
2254};
2255
2256static const struct panel_desc tpk_f10a_0102 = {
2257 .modes = &tpk_f10a_0102_mode,
2258 .num_modes = 1,
2259 .size = {
2260 .width = 223,
2261 .height = 125,
2262 },
2263};
2264
06a9dc65
MS		 2265static const struct display_timing urt_umsh_8596md_timing = {
2266 .pixelclock = { 33260000, 33260000, 33260000 },
2267 .hactive = { 800, 800, 800 },
2268 .hfront_porch = { 41, 41, 41 },
2269 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2270 .hsync_len = { 71, 128, 128 },
2271 .vactive = { 480, 480, 480 },
2272 .vfront_porch = { 10, 10, 10 },
2273 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2274 .vsync_len = { 2, 2, 2 },
2275 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2276 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2277};
2278
2279static const struct panel_desc urt_umsh_8596md_lvds = {
2280 .timings = &urt_umsh_8596md_timing,
2281 .num_timings = 1,
2282 .bpc = 6,
2283 .size = {
2284 .width = 152,
2285 .height = 91,
2286 },
2287 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2288};
2289
2290static const struct panel_desc urt_umsh_8596md_parallel = {
2291 .timings = &urt_umsh_8596md_timing,
2292 .num_timings = 1,
2293 .bpc = 6,
2294 .size = {
2295 .width = 152,
2296 .height = 91,
2297 },
2298 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2299};
2300
e4bac408
RG		 2301static const struct drm_display_mode winstar_wf35ltiacd_mode = {
2302 .clock = 6410,
2303 .hdisplay = 320,
2304 .hsync_start = 320 + 20,
2305 .hsync_end = 320 + 20 + 30,
2306 .htotal = 320 + 20 + 30 + 38,
2307 .vdisplay = 240,
2308 .vsync_start = 240 + 4,
2309 .vsync_end = 240 + 4 + 3,
2310 .vtotal = 240 + 4 + 3 + 15,
2311 .vrefresh = 60,
2312 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2313};
2314
2315static const struct panel_desc winstar_wf35ltiacd = {
2316 .modes = &winstar_wf35ltiacd_mode,
2317 .num_modes = 1,
2318 .bpc = 8,
2319 .size = {
2320 .width = 70,
2321 .height = 53,
2322 },
2323 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2324};
2325
280921de
TR		 2326static const struct of_device_id platform_of_match[] = {
2327 {
966fea78
YF		 2328 .compatible = "ampire,am-480272h3tmqw-t01h",
2329 .data = &ampire_am_480272h3tmqw_t01h,
2330 }, {
1c550fa1
PZ		 2331 .compatible = "ampire,am800480r3tmqwa1h",
2332 .data = &ampire_am800480r3tmqwa1h,
2333 }, {
280921de
TR		 2334 .compatible = "auo,b101aw03",
2335 .data = &auo_b101aw03,
a531bc3d
HL		 2336 }, {
2337 .compatible = "auo,b101ean01",
2338 .data = &auo_b101ean01,
dac746e0
RC		 2339 }, {
2340 .compatible = "auo,b101xtn01",
2341 .data = &auo_b101xtn01,
e35e305e
AK		 2342 }, {
2343 .compatible = "auo,b116xw03",
2344 .data = &auo_b116xw03,
3e51d609
AK		 2345 }, {
2346 .compatible = "auo,b133htn01",
2347 .data = &auo_b133htn01,
a333f7ad
SM		 2348 }, {
2349 .compatible = "auo,b133xtn01",
2350 .data = &auo_b133xtn01,
bccfaffb
LM		 2351 }, {
2352 .compatible = "auo,g070vvn01",
2353 .data = &auo_g070vvn01,
4451c287
CF		 2354 }, {
2355 .compatible = "auo,g104sn02",
2356 .data = &auo_g104sn02,
697035c6
LS		 2357 }, {
2358 .compatible = "auo,g133han01",
2359 .data = &auo_g133han01,
8c31f603
LS		 2360 }, {
2361 .compatible = "auo,g185han01",
2362 .data = &auo_g185han01,
70c0d5b7
LS		 2363 }, {
2364 .compatible = "auo,p320hvn03",
2365 .data = &auo_p320hvn03,
7ee933a1
HS		 2366 }, {
2367 .compatible = "auo,t215hvn01",
2368 .data = &auo_t215hvn01,
d47df633
PZ		 2369 }, {
2370 .compatible = "avic,tm070ddh03",
2371 .data = &avic_tm070ddh03,
ae8cf41b
AH		 2372 }, {
2373 .compatible = "boe,hv070wsa-100",
2374 .data = &boe_hv070wsa
cac1a411
CW		 2375 }, {
2376 .compatible = "boe,nv101wxmn51",
2377 .data = &boe_nv101wxmn51,
2cb35c80
RL		 2378 }, {
2379 .compatible = "chunghwa,claa070wp03xg",
2380 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 2381 }, {
2382 .compatible = "chunghwa,claa101wa01a",
2383 .data = &chunghwa_claa101wa01a
280921de
TR		 2384 }, {
2385 .compatible = "chunghwa,claa101wb01",
2386 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 2387 }, {
2388 .compatible = "dataimage,scf0700c48ggu18",
2389 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 2390 }, {
2391 .compatible = "dlc,dlc0700yzg-1",
2392 .data = &dlc_dlc0700yzg_1,
26ab0065
SA		 2393 }, {
2394 .compatible = "edt,et057090dhu",
2395 .data = &edt_et057090dhu,
fff5de45
PZ		 2396 }, {
2397 .compatible = "edt,et070080dh6",
2398 .data = &edt_etm0700g0dh6,
2399 }, {
2400 .compatible = "edt,etm0700g0dh6",
2401 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 2402 }, {
2403 .compatible = "edt,etm0700g0bdh6",
2404 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 2405 }, {
2406 .compatible = "edt,etm0700g0edh6",
2407 .data = &edt_etm0700g0bdh6,
102932b0
BB		 2408 }, {
2409 .compatible = "foxlink,fl500wvr00-a0t",
2410 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 2411 }, {
2412 .compatible = "giantplus,gpg482739qs5",
2413 .data = &giantplus_gpg482739qs5
a853205e
PZ		 2414 }, {
2415 .compatible = "hannstar,hsd070pww1",
2416 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 2417 }, {
2418 .compatible = "hannstar,hsd100pxn1",
2419 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 2420 }, {
2421 .compatible = "hit,tx23d38vm0caa",
2422 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 2423 }, {
2424 .compatible = "innolux,at043tn24",
2425 .data = &innolux_at043tn24,
4fc24ab3
RB		 2426 }, {
2427 .compatible = "innolux,at070tn92",
2428 .data = &innolux_at070tn92,
1e29b840 2429 }, {
a5d2ade6
CF		 2430 .compatible = "innolux,g070y2-l01",
2431 .data = &innolux_g070y2_l01,
2432 }, {
2433 .compatible = "innolux,g101ice-l01",
1e29b840 2434 .data = &innolux_g101ice_l01
d731f661 2435 }, {
a5d2ade6 2436 .compatible = "innolux,g121i1-l01",
d731f661 2437 .data = &innolux_g121i1_l01
f8fa17ba
AB		 2438 }, {
2439 .compatible = "innolux,g121x1-l03",
2440 .data = &innolux_g121x1_l03,
0a2288c0
TR		 2441 }, {
2442 .compatible = "innolux,n116bge",
2443 .data = &innolux_n116bge,
ea44739d
AB		 2444 }, {
2445 .compatible = "innolux,n156bge-l21",
2446 .data = &innolux_n156bge_l21,
da50bd42 2447 }, {
2448 .compatible = "innolux,tv123wam",
2449 .data = &innolux_tv123wam,
bccac3f1
MG		 2450 }, {
2451 .compatible = "innolux,zj070na-01p",
2452 .data = &innolux_zj070na_01p,
8cfe8341
JT		 2453 }, {
2454 .compatible = "koe,tx31d200vm0baa",
2455 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 2456 }, {
2457 .compatible = "kyo,tcg121xglp",
2458 .data = &kyo_tcg121xglp,
dd015002
HS		 2459 }, {
2460 .compatible = "lg,lb070wv8",
2461 .data = &lg_lb070wv8,
c5ece402
YY		 2462 }, {
2463 .compatible = "lg,lp079qx1-sp0v",
2464 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 2465 }, {
2466 .compatible = "lg,lp097qx1-spa1",
2467 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 2468 }, {
2469 .compatible = "lg,lp120up1",
2470 .data = &lg_lp120up1,
ec7c5653
TR		 2471 }, {
2472 .compatible = "lg,lp129qe",
2473 .data = &lg_lp129qe,
65c766ca
LM		 2474 }, {
2475 .compatible = "mitsubishi,aa070mc01-ca1",
2476 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 2477 }, {
2478 .compatible = "nec,nl12880bc20-05",
2479 .data = &nec_nl12880bc20_05,
c6e87f91 2480 }, {
2481 .compatible = "nec,nl4827hc19-05b",
2482 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 2483 }, {
2484 .compatible = "netron-dy,e231732",
2485 .data = &netron_dy_e231732,
3b39ad7a
TV		 2486 }, {
2487 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
2488 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 2489 }, {
2490 .compatible = "nlt,nl192108ac18-02d",
2491 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 2492 }, {
2493 .compatible = "nvd,9128",
2494 .data = &nvd_9128,
a99fb626
GB		 2495 }, {
2496 .compatible = "okaya,rs800480t-7x0gp",
2497 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 2498 }, {
2499 .compatible = "olimex,lcd-olinuxino-43-ts",
2500 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 2501 }, {
2502 .compatible = "ontat,yx700wv03",
2503 .data = &ontat_yx700wv03,
725c9d40
PZ		 2504 }, {
2505 .compatible = "ortustech,com43h4m85ulc",
2506 .data = &ortustech_com43h4m85ulc,
d2a6f0f5
JW		 2507 }, {
2508 .compatible = "qiaodian,qd43003c0-40",
2509 .data = &qd43003c0_40,
23167fa9
JT		 2510 }, {
2511 .compatible = "rocktech,rk070er9427",
2512 .data = &rocktech_rk070er9427,
0330eaf3
YY		 2513 }, {
2514 .compatible = "samsung,lsn122dl01-c01",
2515 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 2516 }, {
2517 .compatible = "samsung,ltn101nt05",
2518 .data = &samsung_ltn101nt05,
0c934306
SM		 2519 }, {
2520 .compatible = "samsung,ltn140at29-301",
2521 .data = &samsung_ltn140at29_301,
03e3ec9a
VZ		 2522 }, {
2523 .compatible = "sharp,lq035q7db03",
2524 .data = &sharp_lq035q7db03,
592aa02b
JC		 2525 }, {
2526 .compatible = "sharp,lq101k1ly04",
2527 .data = &sharp_lq101k1ly04,
739c7de9
YY		 2528 }, {
2529 .compatible = "sharp,lq123p1jx31",
2530 .data = &sharp_lq123p1jx31,
0f9cdd74
GL		 2531 }, {
2532 .compatible = "sharp,lq150x1lg11",
2533 .data = &sharp_lq150x1lg11,
9c6615bc
BB		 2534 }, {
2535 .compatible = "shelly,sca07010-bfn-lnn",
2536 .data = &shelly_sca07010_bfn_lnn,
9bb34c4c
DA		 2537 }, {
2538 .compatible = "starry,kr122ea0sra",
2539 .data = &starry_kr122ea0sra,
adb973ef
GB		 2540 }, {
2541 .compatible = "tianma,tm070jdhg30",
2542 .data = &tianma_tm070jdhg30,
870a0b12
LM		 2543 }, {
2544 .compatible = "tianma,tm070rvhg71",
2545 .data = &tianma_tm070rvhg71,
06e733e4
LS		 2546 }, {
2547 .compatible = "toshiba,lt089ac29000",
2548 .data = &toshiba_lt089ac29000,
227e4f40
BD		 2549 }, {
2550 .compatible = "tpk,f07a-0102",
2551 .data = &tpk_f07a_0102,
2552 }, {
2553 .compatible = "tpk,f10a-0102",
2554 .data = &tpk_f10a_0102,
06a9dc65
MS		 2555 }, {
2556 .compatible = "urt,umsh-8596md-t",
2557 .data = &urt_umsh_8596md_parallel,
2558 }, {
2559 .compatible = "urt,umsh-8596md-1t",
2560 .data = &urt_umsh_8596md_parallel,
2561 }, {
2562 .compatible = "urt,umsh-8596md-7t",
2563 .data = &urt_umsh_8596md_parallel,
2564 }, {
2565 .compatible = "urt,umsh-8596md-11t",
2566 .data = &urt_umsh_8596md_lvds,
2567 }, {
2568 .compatible = "urt,umsh-8596md-19t",
2569 .data = &urt_umsh_8596md_lvds,
2570 }, {
2571 .compatible = "urt,umsh-8596md-20t",
2572 .data = &urt_umsh_8596md_parallel,
e4bac408
RG		 2573 }, {
2574 .compatible = "winstar,wf35ltiacd",
2575 .data = &winstar_wf35ltiacd,
280921de
TR		 2576 }, {
2577 /* sentinel */
2578 }
2579};
2580MODULE_DEVICE_TABLE(of, platform_of_match);
2581
2582static int panel_simple_platform_probe(struct platform_device *pdev)
2583{
2584 const struct of_device_id *id;
2585
2586 id = of_match_node(platform_of_match, pdev->dev.of_node);
2587 if (!id)
2588 return -ENODEV;
2589
2590 return panel_simple_probe(&pdev->dev, id->data);
2591}
2592
2593static int panel_simple_platform_remove(struct platform_device *pdev)
2594{
2595 return panel_simple_remove(&pdev->dev);
2596}
2597
d02fd93e
TR		 2598static void panel_simple_platform_shutdown(struct platform_device *pdev)
2599{
2600 panel_simple_shutdown(&pdev->dev);
2601}
2602
280921de
TR		 2603static struct platform_driver panel_simple_platform_driver = {
2604 .driver = {
2605 .name = "panel-simple",
280921de
TR		 2606 .of_match_table = platform_of_match,
2607 },
2608 .probe = panel_simple_platform_probe,
2609 .remove = panel_simple_platform_remove,
d02fd93e 2610 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 2611};
2612
210fcd9d
TR		 2613struct panel_desc_dsi {
2614 struct panel_desc desc;
2615
462658b8 2616 unsigned long flags;
210fcd9d
TR		 2617 enum mipi_dsi_pixel_format format;
2618 unsigned int lanes;
2619};
2620
d718d79e
TR		 2621static const struct drm_display_mode auo_b080uan01_mode = {
2622 .clock = 154500,
2623 .hdisplay = 1200,
2624 .hsync_start = 1200 + 62,
2625 .hsync_end = 1200 + 62 + 4,
2626 .htotal = 1200 + 62 + 4 + 62,
2627 .vdisplay = 1920,
2628 .vsync_start = 1920 + 9,
2629 .vsync_end = 1920 + 9 + 2,
2630 .vtotal = 1920 + 9 + 2 + 8,
2631 .vrefresh = 60,
2632};
2633
2634static const struct panel_desc_dsi auo_b080uan01 = {
2635 .desc = {
2636 .modes = &auo_b080uan01_mode,
2637 .num_modes = 1,
2638 .bpc = 8,
2639 .size = {
2640 .width = 108,
2641 .height = 272,
2642 },
2643 },
2644 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
2645 .format = MIPI_DSI_FMT_RGB888,
2646 .lanes = 4,
2647};
2648
c8521969
CZ		 2649static const struct drm_display_mode boe_tv080wum_nl0_mode = {
2650 .clock = 160000,
2651 .hdisplay = 1200,
2652 .hsync_start = 1200 + 120,
2653 .hsync_end = 1200 + 120 + 20,
2654 .htotal = 1200 + 120 + 20 + 21,
2655 .vdisplay = 1920,
2656 .vsync_start = 1920 + 21,
2657 .vsync_end = 1920 + 21 + 3,
2658 .vtotal = 1920 + 21 + 3 + 18,
2659 .vrefresh = 60,
2660 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2661};
2662
2663static const struct panel_desc_dsi boe_tv080wum_nl0 = {
2664 .desc = {
2665 .modes = &boe_tv080wum_nl0_mode,
2666 .num_modes = 1,
2667 .size = {
2668 .width = 107,
2669 .height = 172,
2670 },
2671 },
2672 .flags = MIPI_DSI_MODE_VIDEO |
2673 MIPI_DSI_MODE_VIDEO_BURST |
2674 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
2675 .format = MIPI_DSI_FMT_RGB888,
2676 .lanes = 4,
2677};
2678
712ac1ba
AC		 2679static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
2680 .clock = 71000,
2681 .hdisplay = 800,
2682 .hsync_start = 800 + 32,
2683 .hsync_end = 800 + 32 + 1,
2684 .htotal = 800 + 32 + 1 + 57,
2685 .vdisplay = 1280,
2686 .vsync_start = 1280 + 28,
2687 .vsync_end = 1280 + 28 + 1,
2688 .vtotal = 1280 + 28 + 1 + 14,
2689 .vrefresh = 60,
2690};
2691
2692static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
2693 .desc = {
2694 .modes = &lg_ld070wx3_sl01_mode,
2695 .num_modes = 1,
d7a839cd 2696 .bpc = 8,
712ac1ba
AC		 2697 .size = {
2698 .width = 94,
2699 .height = 151,
2700 },
2701 },
5e4cc278 2702 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 2703 .format = MIPI_DSI_FMT_RGB888,
2704 .lanes = 4,
2705};
2706
499ce85a
AC		 2707static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
2708 .clock = 67000,
2709 .hdisplay = 720,
2710 .hsync_start = 720 + 12,
2711 .hsync_end = 720 + 12 + 4,
2712 .htotal = 720 + 12 + 4 + 112,
2713 .vdisplay = 1280,
2714 .vsync_start = 1280 + 8,
2715 .vsync_end = 1280 + 8 + 4,
2716 .vtotal = 1280 + 8 + 4 + 12,
2717 .vrefresh = 60,
2718};
2719
2720static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
2721 .desc = {
2722 .modes = &lg_lh500wx1_sd03_mode,
2723 .num_modes = 1,
d7a839cd 2724 .bpc = 8,
499ce85a
AC		 2725 .size = {
2726 .width = 62,
2727 .height = 110,
2728 },
2729 },
2730 .flags = MIPI_DSI_MODE_VIDEO,
2731 .format = MIPI_DSI_FMT_RGB888,
2732 .lanes = 4,
2733};
2734
280921de
TR		 2735static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
2736 .clock = 157200,
2737 .hdisplay = 1920,
2738 .hsync_start = 1920 + 154,
2739 .hsync_end = 1920 + 154 + 16,
2740 .htotal = 1920 + 154 + 16 + 32,
2741 .vdisplay = 1200,
2742 .vsync_start = 1200 + 17,
2743 .vsync_end = 1200 + 17 + 2,
2744 .vtotal = 1200 + 17 + 2 + 16,
2745 .vrefresh = 60,
2746};
2747
210fcd9d
TR		 2748static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2749 .desc = {
2750 .modes = &panasonic_vvx10f004b00_mode,
2751 .num_modes = 1,
d7a839cd 2752 .bpc = 8,
210fcd9d
TR		 2753 .size = {
2754 .width = 217,
2755 .height = 136,
2756 },
280921de 2757 },
5e4cc278
AC		 2758 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2759 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 2760 .format = MIPI_DSI_FMT_RGB888,
2761 .lanes = 4,
2762};
2763
2764static const struct of_device_id dsi_of_match[] = {
2765 {
d718d79e
TR		 2766 .compatible = "auo,b080uan01",
2767 .data = &auo_b080uan01
c8521969
CZ		 2768 }, {
2769 .compatible = "boe,tv080wum-nl0",
2770 .data = &boe_tv080wum_nl0
d718d79e 2771 }, {
712ac1ba
AC		 2772 .compatible = "lg,ld070wx3-sl01",
2773 .data = &lg_ld070wx3_sl01
2774 }, {
499ce85a
AC		 2775 .compatible = "lg,lh500wx1-sd03",
2776 .data = &lg_lh500wx1_sd03
2777 }, {
210fcd9d
TR		 2778 .compatible = "panasonic,vvx10f004b00",
2779 .data = &panasonic_vvx10f004b00
2780 }, {
2781 /* sentinel */
2782 }
2783};
2784MODULE_DEVICE_TABLE(of, dsi_of_match);
2785
2786static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2787{
2788 const struct panel_desc_dsi *desc;
2789 const struct of_device_id *id;
2790 int err;
2791
2792 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2793 if (!id)
2794 return -ENODEV;
2795
2796 desc = id->data;
2797
2798 err = panel_simple_probe(&dsi->dev, &desc->desc);
2799 if (err < 0)
2800 return err;
2801
462658b8 2802 dsi->mode_flags = desc->flags;
210fcd9d
TR		 2803 dsi->format = desc->format;
2804 dsi->lanes = desc->lanes;
2805
2806 return mipi_dsi_attach(dsi);
2807}
2808
2809static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2810{
2811 int err;
2812
2813 err = mipi_dsi_detach(dsi);
2814 if (err < 0)
2815 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2816
2817 return panel_simple_remove(&dsi->dev);
2818}
2819
d02fd93e
TR		 2820static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2821{
2822 panel_simple_shutdown(&dsi->dev);
2823}
2824
210fcd9d
TR		 2825static struct mipi_dsi_driver panel_simple_dsi_driver = {
2826 .driver = {
2827 .name = "panel-simple-dsi",
210fcd9d
TR		 2828 .of_match_table = dsi_of_match,
2829 },
2830 .probe = panel_simple_dsi_probe,
2831 .remove = panel_simple_dsi_remove,
d02fd93e 2832 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 2833};
2834
2835static int __init panel_simple_init(void)
2836{
210fcd9d
TR		 2837 int err;
2838
2839 err = platform_driver_register(&panel_simple_platform_driver);
2840 if (err < 0)
2841 return err;
2842
2843 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2844 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2845 if (err < 0)
2846 return err;
2847 }
2848
2849 return 0;
280921de
TR		 2850}
2851module_init(panel_simple_init);
2852
2853static void __exit panel_simple_exit(void)
2854{
210fcd9d
TR		 2855 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2856 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2857
280921de
TR		 2858 platform_driver_unregister(&panel_simple_platform_driver);
2859}
2860module_exit(panel_simple_exit);
2861
2862MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2863MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2864MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)