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drm/panel: novatek,nt39016: Add missing CR to error messages
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
48834e60 26#include <linux/iopoll.h>
280921de 27#include <linux/module.h>
280921de
TR		 28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
cb23eae3 32#include <video/display_timing.h>
b8a2948f 33#include <video/of_display_timing.h>
cb23eae3
SR		 34#include <video/videomode.h>
35
280921de 36#include <drm/drm_crtc.h>
cb23eae3 37#include <drm/drm_device.h>
210fcd9d 38#include <drm/drm_mipi_dsi.h>
280921de
TR		 39#include <drm/drm_panel.h>
40
e362cc6a
DA		 41/**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
280921de
TR		 57struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
a5d3e625
PZ		 60 const struct display_timing *timings;
61 unsigned int num_timings;
280921de 62
0208d511
SM		 63 unsigned int bpc;
64
85533e3b
UÖ		 65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
280921de
TR		 69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
f673c37e
AK		 73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
2ed3e951
DA		 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
f673c37e
AK		 79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
2ed3e951 89 unsigned int hpd_absent_delay;
f673c37e
AK		 90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
795f7ab3
BB		 94
95 u32 bus_format;
f0aa0838 96 u32 bus_flags;
9a2654c0 97 int connector_type;
280921de
TR		 98};
99
280921de
TR		 100struct panel_simple {
101 struct drm_panel base;
613a633e 102 bool prepared;
280921de 103 bool enabled;
2ed3e951 104 bool no_hpd;
280921de
TR		 105
106 const struct panel_desc *desc;
107
280921de
TR		 108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
cfdf0549 111 struct gpio_desc *enable_gpio;
48834e60 112 struct gpio_desc *hpd_gpio;
b8a2948f
SP		 113
114 struct drm_display_mode override_mode;
280921de
TR		 115};
116
117static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
118{
119 return container_of(panel, struct panel_simple, base);
120}
121
0ce8ddd8
SR		 122static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
123 struct drm_connector *connector)
280921de 124{
280921de
TR		 125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
127
a5d3e625
PZ		 128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
130 struct videomode vm;
131
132 videomode_from_timing(dt, &vm);
aa6c4364 133 mode = drm_mode_create(connector->dev);
a5d3e625 134 if (!mode) {
aa6c4364 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 136 dt->hactive.typ, dt->vactive.typ);
137 continue;
138 }
139
140 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 141
142 mode->type |= DRM_MODE_TYPE_DRIVER;
143
230c5b44 144 if (panel->desc->num_timings == 1)
cda55372
BB		 145 mode->type |= DRM_MODE_TYPE_PREFERRED;
146
a5d3e625
PZ		 147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
b8a2948f
SP		 151 return num;
152}
153
0ce8ddd8
SR		 154static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
155 struct drm_connector *connector)
b8a2948f 156{
b8a2948f
SP		 157 struct drm_display_mode *mode;
158 unsigned int i, num = 0;
159
280921de
TR		 160 for (i = 0; i < panel->desc->num_modes; i++) {
161 const struct drm_display_mode *m = &panel->desc->modes[i];
162
aa6c4364 163 mode = drm_mode_duplicate(connector->dev, m);
280921de 164 if (!mode) {
aa6c4364 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
0425662f
VS		 166 m->hdisplay, m->vdisplay,
167 drm_mode_vrefresh(m));
280921de
TR		 168 continue;
169 }
170
cda55372
BB		 171 mode->type |= DRM_MODE_TYPE_DRIVER;
172
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
175
280921de
TR		 176 drm_mode_set_name(mode);
177
178 drm_mode_probed_add(connector, mode);
179 num++;
180 }
181
b8a2948f
SP		 182 return num;
183}
184
0ce8ddd8
SR		 185static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
186 struct drm_connector *connector)
b8a2948f 187{
b8a2948f
SP		 188 struct drm_display_mode *mode;
189 bool has_override = panel->override_mode.type;
190 unsigned int num = 0;
191
192 if (!panel->desc)
193 return 0;
194
195 if (has_override) {
aa6c4364
SR		 196 mode = drm_mode_duplicate(connector->dev,
197 &panel->override_mode);
b8a2948f
SP		 198 if (mode) {
199 drm_mode_probed_add(connector, mode);
200 num = 1;
201 } else {
aa6c4364 202 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 203 }
204 }
205
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 208 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 209
210 /*
211 * Only add fixed modes if timings/override added no mode.
212 *
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
215 */
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 if (num == 0)
0ce8ddd8 218 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 219
0208d511 220 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
f0aa0838 226 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 227
228 return num;
229}
230
231static int panel_simple_disable(struct drm_panel *panel)
232{
233 struct panel_simple *p = to_panel_simple(panel);
234
235 if (!p->enabled)
236 return 0;
237
f673c37e
AK		 238 if (p->desc->delay.disable)
239 msleep(p->desc->delay.disable);
240
280921de
TR		 241 p->enabled = false;
242
243 return 0;
244}
245
c0e1d170
AK		 246static int panel_simple_unprepare(struct drm_panel *panel)
247{
613a633e
AK		 248 struct panel_simple *p = to_panel_simple(panel);
249
250 if (!p->prepared)
251 return 0;
252
756b918d 253 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 254
255 regulator_disable(p->supply);
256
f673c37e
AK		 257 if (p->desc->delay.unprepare)
258 msleep(p->desc->delay.unprepare);
259
613a633e 260 p->prepared = false;
c0e1d170 261
c0e1d170
AK		 262 return 0;
263}
264
48834e60
DA		 265static int panel_simple_get_hpd_gpio(struct device *dev,
266 struct panel_simple *p, bool from_probe)
267{
268 int err;
269
270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
271 if (IS_ERR(p->hpd_gpio)) {
272 err = PTR_ERR(p->hpd_gpio);
273
274 /*
275 * If we're called from probe we won't consider '-EPROBE_DEFER'
276 * to be an error--we'll leave the error code in "hpd_gpio".
277 * When we try to use it we'll try again. This allows for
278 * circular dependencies where the component providing the
279 * hpd gpio needs the panel to init before probing.
280 */
281 if (err != -EPROBE_DEFER || !from_probe) {
282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
283 return err;
284 }
285 }
286
287 return 0;
288}
289
613a633e 290static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 291{
292 struct panel_simple *p = to_panel_simple(panel);
2ed3e951 293 unsigned int delay;
280921de 294 int err;
48834e60 295 int hpd_asserted;
280921de 296
613a633e 297 if (p->prepared)
280921de
TR		 298 return 0;
299
300 err = regulator_enable(p->supply);
301 if (err < 0) {
302 dev_err(panel->dev, "failed to enable supply: %d\n", err);
303 return err;
304 }
305
756b918d 306 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 307
2ed3e951
DA		 308 delay = p->desc->delay.prepare;
309 if (p->no_hpd)
310 delay += p->desc->delay.hpd_absent_delay;
311 if (delay)
312 msleep(delay);
f673c37e 313
48834e60
DA		 314 if (p->hpd_gpio) {
315 if (IS_ERR(p->hpd_gpio)) {
316 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
317 if (err)
318 return err;
319 }
320
321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
322 hpd_asserted, hpd_asserted,
323 1000, 2000000);
324 if (hpd_asserted < 0)
325 err = hpd_asserted;
326
327 if (err) {
328 dev_err(panel->dev,
329 "error waiting for hpd GPIO: %d\n", err);
330 return err;
331 }
332 }
333
613a633e
AK		 334 p->prepared = true;
335
336 return 0;
337}
338
339static int panel_simple_enable(struct drm_panel *panel)
340{
341 struct panel_simple *p = to_panel_simple(panel);
342
343 if (p->enabled)
344 return 0;
345
f673c37e
AK		 346 if (p->desc->delay.enable)
347 msleep(p->desc->delay.enable);
348
280921de
TR		 349 p->enabled = true;
350
351 return 0;
352}
353
0ce8ddd8
SR		 354static int panel_simple_get_modes(struct drm_panel *panel,
355 struct drm_connector *connector)
280921de
TR		 356{
357 struct panel_simple *p = to_panel_simple(panel);
358 int num = 0;
359
360 /* probe EDID if a DDC bus is available */
361 if (p->ddc) {
0ce8ddd8
SR		 362 struct edid *edid = drm_get_edid(connector, p->ddc);
363
364 drm_connector_update_edid_property(connector, edid);
280921de 365 if (edid) {
0ce8ddd8 366 num += drm_add_edid_modes(connector, edid);
280921de
TR		 367 kfree(edid);
368 }
369 }
370
371 /* add hard-coded panel modes */
0ce8ddd8 372 num += panel_simple_get_non_edid_modes(p, connector);
280921de
TR		 373
374 return num;
375}
376
a5d3e625
PZ		 377static int panel_simple_get_timings(struct drm_panel *panel,
378 unsigned int num_timings,
379 struct display_timing *timings)
380{
381 struct panel_simple *p = to_panel_simple(panel);
382 unsigned int i;
383
384 if (p->desc->num_timings < num_timings)
385 num_timings = p->desc->num_timings;
386
387 if (timings)
388 for (i = 0; i < num_timings; i++)
389 timings[i] = p->desc->timings[i];
390
391 return p->desc->num_timings;
392}
393
280921de
TR		 394static const struct drm_panel_funcs panel_simple_funcs = {
395 .disable = panel_simple_disable,
c0e1d170
AK		 396 .unprepare = panel_simple_unprepare,
397 .prepare = panel_simple_prepare,
280921de
TR		 398 .enable = panel_simple_enable,
399 .get_modes = panel_simple_get_modes,
a5d3e625 400 .get_timings = panel_simple_get_timings,
280921de
TR		 401};
402
4a1d0dbc
SR		 403static struct panel_desc panel_dpi;
404
405static int panel_dpi_probe(struct device *dev,
406 struct panel_simple *panel)
407{
408 struct display_timing *timing;
409 const struct device_node *np;
410 struct panel_desc *desc;
411 unsigned int bus_flags;
412 struct videomode vm;
4a1d0dbc
SR		 413 int ret;
414
415 np = dev->of_node;
416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
417 if (!desc)
418 return -ENOMEM;
419
420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
421 if (!timing)
422 return -ENOMEM;
423
424 ret = of_get_display_timing(np, "panel-timing", timing);
425 if (ret < 0) {
426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
427 np);
428 return ret;
429 }
430
431 desc->timings = timing;
432 desc->num_timings = 1;
433
434 of_property_read_u32(np, "width-mm", &desc->size.width);
435 of_property_read_u32(np, "height-mm", &desc->size.height);
436
4a1d0dbc
SR		 437 /* Extract bus_flags from display_timing */
438 bus_flags = 0;
439 vm.flags = timing->flags;
440 drm_bus_flags_from_videomode(&vm, &bus_flags);
441 desc->bus_flags = bus_flags;
442
443 /* We do not know the connector for the DT node, so guess it */
444 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
445
446 panel->desc = desc;
447
448 return 0;
449}
450
b8a2948f
SP		 451#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
452 (to_check->field.typ >= bounds->field.min && \
453 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 454static void panel_simple_parse_panel_timing_node(struct device *dev,
455 struct panel_simple *panel,
456 const struct display_timing *ot)
b8a2948f
SP		 457{
458 const struct panel_desc *desc = panel->desc;
459 struct videomode vm;
460 unsigned int i;
461
462 if (WARN_ON(desc->num_modes)) {
463 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
464 return;
465 }
466 if (WARN_ON(!desc->num_timings)) {
467 dev_err(dev, "Reject override mode: no timings specified\n");
468 return;
469 }
470
471 for (i = 0; i < panel->desc->num_timings; i++) {
472 const struct display_timing *dt = &panel->desc->timings[i];
473
474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
482 continue;
483
484 if (ot->flags != dt->flags)
485 continue;
486
487 videomode_from_timing(ot, &vm);
488 drm_display_mode_from_videomode(&vm, &panel->override_mode);
489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
490 DRM_MODE_TYPE_PREFERRED;
491 break;
492 }
493
494 if (WARN_ON(!panel->override_mode.type))
495 dev_err(dev, "Reject override mode: No display_timing found\n");
496}
497
280921de
TR		 498static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
499{
280921de 500 struct panel_simple *panel;
b8a2948f 501 struct display_timing dt;
0fe1564b 502 struct device_node *ddc;
9f069c6f 503 int connector_type;
ddb8e853 504 u32 bus_flags;
280921de
TR		 505 int err;
506
507 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
508 if (!panel)
509 return -ENOMEM;
510
511 panel->enabled = false;
613a633e 512 panel->prepared = false;
280921de
TR		 513 panel->desc = desc;
514
2ed3e951 515 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
48834e60
DA		 516 if (!panel->no_hpd) {
517 err = panel_simple_get_hpd_gpio(dev, panel, true);
518 if (err)
519 return err;
520 }
2ed3e951 521
280921de
TR		 522 panel->supply = devm_regulator_get(dev, "power");
523 if (IS_ERR(panel->supply))
524 return PTR_ERR(panel->supply);
525
a61400d8
AC		 526 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
527 GPIOD_OUT_LOW);
cfdf0549
AC		 528 if (IS_ERR(panel->enable_gpio)) {
529 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 530 if (err != -EPROBE_DEFER)
531 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 532 return err;
533 }
280921de 534
280921de
TR		 535 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
536 if (ddc) {
537 panel->ddc = of_find_i2c_adapter_by_node(ddc);
538 of_node_put(ddc);
539
0fe1564b
SR		 540 if (!panel->ddc)
541 return -EPROBE_DEFER;
280921de
TR		 542 }
543
4a1d0dbc
SR		 544 if (desc == &panel_dpi) {
545 /* Handle the generic panel-dpi binding */
546 err = panel_dpi_probe(dev, panel);
547 if (err)
548 goto free_ddc;
549 } else {
550 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
551 panel_simple_parse_panel_timing_node(dev, panel, &dt);
552 }
b8a2948f 553
9f069c6f 554 connector_type = desc->connector_type;
ddb8e853 555 /* Catch common mistakes for panels. */
9f069c6f 556 switch (connector_type) {
ddb8e853
SR		 557 case 0:
558 dev_warn(dev, "Specify missing connector_type\n");
9f069c6f 559 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853
SR		 560 break;
561 case DRM_MODE_CONNECTOR_LVDS:
c4715837
LP		 562 WARN_ON(desc->bus_flags &
563 ~(DRM_BUS_FLAG_DE_LOW |
564 DRM_BUS_FLAG_DE_HIGH |
565 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
566 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
1185c406
LP		 567 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
568 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
569 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
570 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
571 desc->bpc != 6);
572 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
573 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
574 desc->bpc != 8);
ddb8e853
SR		 575 break;
576 case DRM_MODE_CONNECTOR_eDP:
577 if (desc->bus_format == 0)
578 dev_warn(dev, "Specify missing bus_format\n");
579 if (desc->bpc != 6 && desc->bpc != 8)
580 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
581 break;
582 case DRM_MODE_CONNECTOR_DSI:
583 if (desc->bpc != 6 && desc->bpc != 8)
584 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
585 break;
586 case DRM_MODE_CONNECTOR_DPI:
587 bus_flags = DRM_BUS_FLAG_DE_LOW |
588 DRM_BUS_FLAG_DE_HIGH |
589 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
590 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
591 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
592 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
593 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
594 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
595 if (desc->bus_flags & ~bus_flags)
596 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
597 if (!(desc->bus_flags & bus_flags))
598 dev_warn(dev, "Specify missing bus_flags\n");
599 if (desc->bus_format == 0)
600 dev_warn(dev, "Specify missing bus_format\n");
601 if (desc->bpc != 6 && desc->bpc != 8)
602 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
603 break;
604 default:
605 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
9f069c6f 606 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853 607 break;
1185c406 608 }
c4715837 609
9f069c6f 610 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
280921de 611
0fe1564b
SR		 612 err = drm_panel_of_backlight(&panel->base);
613 if (err)
614 goto free_ddc;
615
c3ee8c65 616 drm_panel_add(&panel->base);
280921de
TR		 617
618 dev_set_drvdata(dev, panel);
619
620 return 0;
621
622free_ddc:
623 if (panel->ddc)
624 put_device(&panel->ddc->dev);
280921de
TR		 625
626 return err;
627}
628
629static int panel_simple_remove(struct device *dev)
630{
631 struct panel_simple *panel = dev_get_drvdata(dev);
632
280921de 633 drm_panel_remove(&panel->base);
0fe1564b
SR		 634 drm_panel_disable(&panel->base);
635 drm_panel_unprepare(&panel->base);
280921de
TR		 636
637 if (panel->ddc)
638 put_device(&panel->ddc->dev);
639
280921de
TR		 640 return 0;
641}
642
d02fd93e
TR		 643static void panel_simple_shutdown(struct device *dev)
644{
645 struct panel_simple *panel = dev_get_drvdata(dev);
646
0fe1564b
SR		 647 drm_panel_disable(&panel->base);
648 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 649}
650
966fea78
YF		 651static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
652 .clock = 9000,
653 .hdisplay = 480,
654 .hsync_start = 480 + 2,
655 .hsync_end = 480 + 2 + 41,
656 .htotal = 480 + 2 + 41 + 2,
657 .vdisplay = 272,
658 .vsync_start = 272 + 2,
659 .vsync_end = 272 + 2 + 10,
660 .vtotal = 272 + 2 + 10 + 2,
966fea78
YF		 661 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
662};
663
664static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
665 .modes = &ampire_am_480272h3tmqw_t01h_mode,
666 .num_modes = 1,
667 .bpc = 8,
668 .size = {
669 .width = 105,
670 .height = 67,
671 },
672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
673};
674
1c550fa1
PZ		 675static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
676 .clock = 33333,
677 .hdisplay = 800,
678 .hsync_start = 800 + 0,
679 .hsync_end = 800 + 0 + 255,
680 .htotal = 800 + 0 + 255 + 0,
681 .vdisplay = 480,
682 .vsync_start = 480 + 2,
683 .vsync_end = 480 + 2 + 45,
684 .vtotal = 480 + 2 + 45 + 0,
1c550fa1
PZ		 685 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
686};
687
688static const struct panel_desc ampire_am800480r3tmqwa1h = {
689 .modes = &ampire_am800480r3tmqwa1h_mode,
690 .num_modes = 1,
691 .bpc = 6,
692 .size = {
693 .width = 152,
694 .height = 91,
695 },
696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
697};
698
c479450f
SS		 699static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
700 .pixelclock = { 26400000, 33300000, 46800000 },
701 .hactive = { 800, 800, 800 },
702 .hfront_porch = { 16, 210, 354 },
703 .hback_porch = { 45, 36, 6 },
704 .hsync_len = { 1, 10, 40 },
705 .vactive = { 480, 480, 480 },
706 .vfront_porch = { 7, 22, 147 },
707 .vback_porch = { 22, 13, 3 },
708 .vsync_len = { 1, 10, 20 },
709 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
710 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
711};
712
713static const struct panel_desc armadeus_st0700_adapt = {
714 .timings = &santek_st0700i5y_rbslw_f_timing,
715 .num_timings = 1,
716 .bpc = 6,
717 .size = {
718 .width = 154,
719 .height = 86,
720 },
721 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 722 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
c479450f
SS		 723};
724
280921de
TR		 725static const struct drm_display_mode auo_b101aw03_mode = {
726 .clock = 51450,
727 .hdisplay = 1024,
728 .hsync_start = 1024 + 156,
729 .hsync_end = 1024 + 156 + 8,
730 .htotal = 1024 + 156 + 8 + 156,
731 .vdisplay = 600,
732 .vsync_start = 600 + 16,
733 .vsync_end = 600 + 16 + 6,
734 .vtotal = 600 + 16 + 6 + 16,
280921de
TR		 735};
736
737static const struct panel_desc auo_b101aw03 = {
738 .modes = &auo_b101aw03_mode,
739 .num_modes = 1,
0208d511 740 .bpc = 6,
280921de
TR		 741 .size = {
742 .width = 223,
743 .height = 125,
744 },
85560829 745 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 746 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 747 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 748};
749
374bf825
DA		 750static const struct display_timing auo_b101ean01_timing = {
751 .pixelclock = { 65300000, 72500000, 75000000 },
752 .hactive = { 1280, 1280, 1280 },
753 .hfront_porch = { 18, 119, 119 },
754 .hback_porch = { 21, 21, 21 },
755 .hsync_len = { 32, 32, 32 },
756 .vactive = { 800, 800, 800 },
757 .vfront_porch = { 4, 4, 4 },
758 .vback_porch = { 8, 8, 8 },
759 .vsync_len = { 18, 20, 20 },
a531bc3d
HL		 760};
761
762static const struct panel_desc auo_b101ean01 = {
374bf825
DA		 763 .timings = &auo_b101ean01_timing,
764 .num_timings = 1,
a531bc3d
HL		 765 .bpc = 6,
766 .size = {
767 .width = 217,
768 .height = 136,
769 },
770};
771
dac746e0
RC		 772static const struct drm_display_mode auo_b101xtn01_mode = {
773 .clock = 72000,
774 .hdisplay = 1366,
775 .hsync_start = 1366 + 20,
776 .hsync_end = 1366 + 20 + 70,
777 .htotal = 1366 + 20 + 70,
778 .vdisplay = 768,
779 .vsync_start = 768 + 14,
780 .vsync_end = 768 + 14 + 42,
781 .vtotal = 768 + 14 + 42,
dac746e0
RC		 782 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
783};
784
785static const struct panel_desc auo_b101xtn01 = {
786 .modes = &auo_b101xtn01_mode,
787 .num_modes = 1,
788 .bpc = 6,
789 .size = {
790 .width = 223,
791 .height = 125,
792 },
793};
794
da458286
RC		 795static const struct drm_display_mode auo_b116xak01_mode = {
796 .clock = 69300,
797 .hdisplay = 1366,
798 .hsync_start = 1366 + 48,
799 .hsync_end = 1366 + 48 + 32,
800 .htotal = 1366 + 48 + 32 + 10,
801 .vdisplay = 768,
802 .vsync_start = 768 + 4,
803 .vsync_end = 768 + 4 + 6,
804 .vtotal = 768 + 4 + 6 + 15,
da458286
RC		 805 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
806};
807
808static const struct panel_desc auo_b116xak01 = {
809 .modes = &auo_b116xak01_mode,
810 .num_modes = 1,
811 .bpc = 6,
812 .size = {
813 .width = 256,
814 .height = 144,
815 },
816 .delay = {
817 .hpd_absent_delay = 200,
818 },
819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
820 .connector_type = DRM_MODE_CONNECTOR_eDP,
821};
822
e35e305e
AK		 823static const struct drm_display_mode auo_b116xw03_mode = {
824 .clock = 70589,
825 .hdisplay = 1366,
826 .hsync_start = 1366 + 40,
827 .hsync_end = 1366 + 40 + 40,
828 .htotal = 1366 + 40 + 40 + 32,
829 .vdisplay = 768,
830 .vsync_start = 768 + 10,
831 .vsync_end = 768 + 10 + 12,
832 .vtotal = 768 + 10 + 12 + 6,
88d3457c 833 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
e35e305e
AK		 834};
835
836static const struct panel_desc auo_b116xw03 = {
837 .modes = &auo_b116xw03_mode,
838 .num_modes = 1,
839 .bpc = 6,
840 .size = {
841 .width = 256,
842 .height = 144,
843 },
88d3457c
JS		 844 .delay = {
845 .enable = 400,
846 },
847 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
848 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
849 .connector_type = DRM_MODE_CONNECTOR_eDP,
e35e305e
AK		 850};
851
a333f7ad
SM		 852static const struct drm_display_mode auo_b133xtn01_mode = {
853 .clock = 69500,
854 .hdisplay = 1366,
855 .hsync_start = 1366 + 48,
856 .hsync_end = 1366 + 48 + 32,
857 .htotal = 1366 + 48 + 32 + 20,
858 .vdisplay = 768,
859 .vsync_start = 768 + 3,
860 .vsync_end = 768 + 3 + 6,
861 .vtotal = 768 + 3 + 6 + 13,
a333f7ad
SM		 862};
863
864static const struct panel_desc auo_b133xtn01 = {
865 .modes = &auo_b133xtn01_mode,
866 .num_modes = 1,
0208d511 867 .bpc = 6,
a333f7ad
SM		 868 .size = {
869 .width = 293,
870 .height = 165,
871 },
872};
873
3e51d609
AK		 874static const struct drm_display_mode auo_b133htn01_mode = {
875 .clock = 150660,
876 .hdisplay = 1920,
877 .hsync_start = 1920 + 172,
878 .hsync_end = 1920 + 172 + 80,
879 .htotal = 1920 + 172 + 80 + 60,
880 .vdisplay = 1080,
881 .vsync_start = 1080 + 25,
882 .vsync_end = 1080 + 25 + 10,
883 .vtotal = 1080 + 25 + 10 + 10,
3e51d609
AK		 884};
885
886static const struct panel_desc auo_b133htn01 = {
887 .modes = &auo_b133htn01_mode,
888 .num_modes = 1,
d7a839cd 889 .bpc = 6,
3e51d609
AK		 890 .size = {
891 .width = 293,
892 .height = 165,
893 },
894 .delay = {
895 .prepare = 105,
896 .enable = 20,
897 .unprepare = 50,
898 },
899};
900
bccfaffb
LM		 901static const struct display_timing auo_g070vvn01_timings = {
902 .pixelclock = { 33300000, 34209000, 45000000 },
903 .hactive = { 800, 800, 800 },
904 .hfront_porch = { 20, 40, 200 },
905 .hback_porch = { 87, 40, 1 },
906 .hsync_len = { 1, 48, 87 },
907 .vactive = { 480, 480, 480 },
908 .vfront_porch = { 5, 13, 200 },
909 .vback_porch = { 31, 31, 29 },
910 .vsync_len = { 1, 1, 3 },
911};
912
913static const struct panel_desc auo_g070vvn01 = {
914 .timings = &auo_g070vvn01_timings,
915 .num_timings = 1,
916 .bpc = 8,
917 .size = {
918 .width = 152,
919 .height = 91,
920 },
921 .delay = {
922 .prepare = 200,
923 .enable = 50,
924 .disable = 50,
925 .unprepare = 1000,
926 },
927};
928
4fb86404
AG		 929static const struct drm_display_mode auo_g101evn010_mode = {
930 .clock = 68930,
931 .hdisplay = 1280,
932 .hsync_start = 1280 + 82,
933 .hsync_end = 1280 + 82 + 2,
934 .htotal = 1280 + 82 + 2 + 84,
935 .vdisplay = 800,
936 .vsync_start = 800 + 8,
937 .vsync_end = 800 + 8 + 2,
938 .vtotal = 800 + 8 + 2 + 6,
4fb86404
AG		 939};
940
941static const struct panel_desc auo_g101evn010 = {
942 .modes = &auo_g101evn010_mode,
943 .num_modes = 1,
944 .bpc = 6,
945 .size = {
946 .width = 216,
947 .height = 135,
948 },
27a46fb7
TV		 949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
950 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4fb86404
AG		 951};
952
4451c287
CF		 953static const struct drm_display_mode auo_g104sn02_mode = {
954 .clock = 40000,
955 .hdisplay = 800,
956 .hsync_start = 800 + 40,
957 .hsync_end = 800 + 40 + 216,
958 .htotal = 800 + 40 + 216 + 128,
959 .vdisplay = 600,
960 .vsync_start = 600 + 10,
961 .vsync_end = 600 + 10 + 35,
962 .vtotal = 600 + 10 + 35 + 2,
4451c287
CF		 963};
964
965static const struct panel_desc auo_g104sn02 = {
966 .modes = &auo_g104sn02_mode,
967 .num_modes = 1,
968 .bpc = 8,
969 .size = {
970 .width = 211,
971 .height = 158,
972 },
973};
974
03e909ac
SR		 975static const struct drm_display_mode auo_g121ean01_mode = {
976 .clock = 66700,
977 .hdisplay = 1280,
978 .hsync_start = 1280 + 58,
979 .hsync_end = 1280 + 58 + 8,
980 .htotal = 1280 + 58 + 8 + 70,
981 .vdisplay = 800,
982 .vsync_start = 800 + 6,
983 .vsync_end = 800 + 6 + 4,
984 .vtotal = 800 + 6 + 4 + 10,
03e909ac
SR		 985};
986
987static const struct panel_desc auo_g121ean01 = {
988 .modes = &auo_g121ean01_mode,
989 .num_modes = 1,
990 .bpc = 8,
991 .size = {
992 .width = 261,
993 .height = 163,
994 },
995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
996 .connector_type = DRM_MODE_CONNECTOR_LVDS,
997};
998
697035c6
LS		 999static const struct display_timing auo_g133han01_timings = {
1000 .pixelclock = { 134000000, 141200000, 149000000 },
1001 .hactive = { 1920, 1920, 1920 },
1002 .hfront_porch = { 39, 58, 77 },
1003 .hback_porch = { 59, 88, 117 },
1004 .hsync_len = { 28, 42, 56 },
1005 .vactive = { 1080, 1080, 1080 },
1006 .vfront_porch = { 3, 8, 11 },
1007 .vback_porch = { 5, 14, 19 },
1008 .vsync_len = { 4, 14, 19 },
1009};
1010
1011static const struct panel_desc auo_g133han01 = {
1012 .timings = &auo_g133han01_timings,
1013 .num_timings = 1,
1014 .bpc = 8,
1015 .size = {
1016 .width = 293,
1017 .height = 165,
1018 },
1019 .delay = {
1020 .prepare = 200,
1021 .enable = 50,
1022 .disable = 50,
1023 .unprepare = 1000,
1024 },
1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 1027};
1028
d9ccd1f2
SR		 1029static const struct drm_display_mode auo_g156xtn01_mode = {
1030 .clock = 76000,
1031 .hdisplay = 1366,
1032 .hsync_start = 1366 + 33,
1033 .hsync_end = 1366 + 33 + 67,
1034 .htotal = 1560,
1035 .vdisplay = 768,
1036 .vsync_start = 768 + 4,
1037 .vsync_end = 768 + 4 + 4,
1038 .vtotal = 806,
d9ccd1f2
SR		 1039};
1040
1041static const struct panel_desc auo_g156xtn01 = {
1042 .modes = &auo_g156xtn01_mode,
1043 .num_modes = 1,
1044 .bpc = 8,
1045 .size = {
1046 .width = 344,
1047 .height = 194,
1048 },
1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1050 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1051};
1052
8c31f603
LS		 1053static const struct display_timing auo_g185han01_timings = {
1054 .pixelclock = { 120000000, 144000000, 175000000 },
1055 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 1056 .hfront_porch = { 36, 120, 148 },
1057 .hback_porch = { 24, 88, 108 },
1058 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 1059 .vactive = { 1080, 1080, 1080 },
1060 .vfront_porch = { 6, 10, 40 },
1061 .vback_porch = { 2, 5, 20 },
1062 .vsync_len = { 2, 5, 20 },
1063};
1064
1065static const struct panel_desc auo_g185han01 = {
1066 .timings = &auo_g185han01_timings,
1067 .num_timings = 1,
1068 .bpc = 8,
1069 .size = {
1070 .width = 409,
1071 .height = 230,
1072 },
1073 .delay = {
1074 .prepare = 50,
1075 .enable = 200,
1076 .disable = 110,
1077 .unprepare = 1000,
1078 },
1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 1081};
1082
2f7b832f
SR		 1083static const struct display_timing auo_g190ean01_timings = {
1084 .pixelclock = { 90000000, 108000000, 135000000 },
1085 .hactive = { 1280, 1280, 1280 },
1086 .hfront_porch = { 126, 184, 1266 },
1087 .hback_porch = { 84, 122, 844 },
1088 .hsync_len = { 70, 102, 704 },
1089 .vactive = { 1024, 1024, 1024 },
1090 .vfront_porch = { 4, 26, 76 },
1091 .vback_porch = { 2, 8, 25 },
1092 .vsync_len = { 2, 8, 25 },
1093};
1094
1095static const struct panel_desc auo_g190ean01 = {
1096 .timings = &auo_g190ean01_timings,
1097 .num_timings = 1,
1098 .bpc = 8,
1099 .size = {
1100 .width = 376,
1101 .height = 301,
1102 },
1103 .delay = {
1104 .prepare = 50,
1105 .enable = 200,
1106 .disable = 110,
1107 .unprepare = 1000,
1108 },
1109 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1110 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1111};
1112
70c0d5b7
LS		 1113static const struct display_timing auo_p320hvn03_timings = {
1114 .pixelclock = { 106000000, 148500000, 164000000 },
1115 .hactive = { 1920, 1920, 1920 },
1116 .hfront_porch = { 25, 50, 130 },
1117 .hback_porch = { 25, 50, 130 },
1118 .hsync_len = { 20, 40, 105 },
1119 .vactive = { 1080, 1080, 1080 },
1120 .vfront_porch = { 8, 17, 150 },
1121 .vback_porch = { 8, 17, 150 },
1122 .vsync_len = { 4, 11, 100 },
1123};
1124
1125static const struct panel_desc auo_p320hvn03 = {
1126 .timings = &auo_p320hvn03_timings,
1127 .num_timings = 1,
1128 .bpc = 8,
1129 .size = {
1130 .width = 698,
1131 .height = 393,
1132 },
1133 .delay = {
1134 .prepare = 1,
1135 .enable = 450,
1136 .unprepare = 500,
1137 },
2554f154 1138 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1139 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 1140};
1141
7ee933a1
HS		 1142static const struct drm_display_mode auo_t215hvn01_mode = {
1143 .clock = 148800,
1144 .hdisplay = 1920,
1145 .hsync_start = 1920 + 88,
1146 .hsync_end = 1920 + 88 + 44,
1147 .htotal = 1920 + 88 + 44 + 148,
1148 .vdisplay = 1080,
1149 .vsync_start = 1080 + 4,
1150 .vsync_end = 1080 + 4 + 5,
1151 .vtotal = 1080 + 4 + 5 + 36,
7ee933a1
HS		 1152};
1153
1154static const struct panel_desc auo_t215hvn01 = {
1155 .modes = &auo_t215hvn01_mode,
1156 .num_modes = 1,
1157 .bpc = 8,
1158 .size = {
1159 .width = 430,
1160 .height = 270,
1161 },
1162 .delay = {
1163 .disable = 5,
1164 .unprepare = 1000,
1165 }
1166};
1167
d47df633
PZ		 1168static const struct drm_display_mode avic_tm070ddh03_mode = {
1169 .clock = 51200,
1170 .hdisplay = 1024,
1171 .hsync_start = 1024 + 160,
1172 .hsync_end = 1024 + 160 + 4,
1173 .htotal = 1024 + 160 + 4 + 156,
1174 .vdisplay = 600,
1175 .vsync_start = 600 + 17,
1176 .vsync_end = 600 + 17 + 1,
1177 .vtotal = 600 + 17 + 1 + 17,
d47df633
PZ		 1178};
1179
1180static const struct panel_desc avic_tm070ddh03 = {
1181 .modes = &avic_tm070ddh03_mode,
1182 .num_modes = 1,
1183 .bpc = 8,
1184 .size = {
1185 .width = 154,
1186 .height = 90,
1187 },
1188 .delay = {
1189 .prepare = 20,
1190 .enable = 200,
1191 .disable = 200,
1192 },
1193};
1194
7ad8b41c
CYT		 1195static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1196 .clock = 30000,
1197 .hdisplay = 800,
1198 .hsync_start = 800 + 40,
1199 .hsync_end = 800 + 40 + 48,
1200 .htotal = 800 + 40 + 48 + 40,
1201 .vdisplay = 480,
1202 .vsync_start = 480 + 13,
1203 .vsync_end = 480 + 13 + 3,
1204 .vtotal = 480 + 13 + 3 + 29,
1205};
1206
1207static const struct panel_desc bananapi_s070wv20_ct16 = {
1208 .modes = &bananapi_s070wv20_ct16_mode,
1209 .num_modes = 1,
1210 .bpc = 6,
1211 .size = {
1212 .width = 154,
1213 .height = 86,
1214 },
1215};
1216
ae8cf41b 1217static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 1218 .clock = 42105,
ae8cf41b 1219 .hdisplay = 1024,
e077e2f5
AH		 1220 .hsync_start = 1024 + 30,
1221 .hsync_end = 1024 + 30 + 30,
1222 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 1223 .vdisplay = 600,
e077e2f5
AH		 1224 .vsync_start = 600 + 10,
1225 .vsync_end = 600 + 10 + 10,
1226 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 1227};
1228
1229static const struct panel_desc boe_hv070wsa = {
1230 .modes = &boe_hv070wsa_mode,
1231 .num_modes = 1,
2a5c2ff5 1232 .bpc = 8,
ae8cf41b
AH		 1233 .size = {
1234 .width = 154,
1235 .height = 90,
1236 },
2a5c2ff5
SR		 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1238 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1239 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ae8cf41b
AH		 1240};
1241
cac1a411
CW		 1242static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1243 {
1244 .clock = 71900,
1245 .hdisplay = 1280,
1246 .hsync_start = 1280 + 48,
1247 .hsync_end = 1280 + 48 + 32,
1248 .htotal = 1280 + 48 + 32 + 80,
1249 .vdisplay = 800,
1250 .vsync_start = 800 + 3,
1251 .vsync_end = 800 + 3 + 5,
1252 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1253 },
1254 {
1255 .clock = 57500,
1256 .hdisplay = 1280,
1257 .hsync_start = 1280 + 48,
1258 .hsync_end = 1280 + 48 + 32,
1259 .htotal = 1280 + 48 + 32 + 80,
1260 .vdisplay = 800,
1261 .vsync_start = 800 + 3,
1262 .vsync_end = 800 + 3 + 5,
1263 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1264 },
1265};
1266
1267static const struct panel_desc boe_nv101wxmn51 = {
1268 .modes = boe_nv101wxmn51_modes,
1269 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1270 .bpc = 8,
1271 .size = {
1272 .width = 217,
1273 .height = 136,
1274 },
1275 .delay = {
1276 .prepare = 210,
1277 .enable = 50,
1278 .unprepare = 160,
1279 },
1280};
1281
cfe40d02 1282/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1283static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1284 .clock = 147840,
1285 .hdisplay = 1920,
1286 .hsync_start = 1920 + 48,
1287 .hsync_end = 1920 + 48 + 32,
1288 .htotal = 1920 + 48 + 32 + 200,
1289 .vdisplay = 1080,
1290 .vsync_start = 1080 + 3,
1291 .vsync_end = 1080 + 3 + 6,
1292 .vtotal = 1080 + 3 + 6 + 31,
b0c664cc
BA		 1293};
1294
cfe40d02 1295/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1296static const struct panel_desc boe_nv133fhm_n61 = {
1297 .modes = &boe_nv133fhm_n61_modes,
1298 .num_modes = 1,
9694d9c3 1299 .bpc = 6,
b0c664cc 1300 .size = {
9694d9c3
DA		 1301 .width = 294,
1302 .height = 165,
b0c664cc
BA		 1303 },
1304 .delay = {
667d73d7
DA		 1305 /*
1306 * When power is first given to the panel there's a short
1307 * spike on the HPD line. It was explained that this spike
1308 * was until the TCON data download was complete. On
1309 * one system this was measured at 8 ms. We'll put 15 ms
1310 * in the prepare delay just to be safe and take it away
1311 * from the hpd_absent_delay (which would otherwise be 200 ms)
1312 * to handle this. That means:
1313 * - If HPD isn't hooked up you still have 200 ms delay.
1314 * - If HPD is hooked up we won't try to look at it for the
1315 * first 15 ms.
1316 */
1317 .prepare = 15,
1318 .hpd_absent_delay = 185,
1319
b0c664cc
BA		 1320 .unprepare = 500,
1321 },
1322 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1323 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1324 .connector_type = DRM_MODE_CONNECTOR_eDP,
1325};
1326
a5119818
TS		 1327static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1328 {
1329 .clock = 148500,
1330 .hdisplay = 1920,
1331 .hsync_start = 1920 + 48,
1332 .hsync_end = 1920 + 48 + 32,
1333 .htotal = 2200,
1334 .vdisplay = 1080,
1335 .vsync_start = 1080 + 3,
1336 .vsync_end = 1080 + 3 + 5,
1337 .vtotal = 1125,
a5119818
TS		 1338 },
1339};
1340
1341static const struct panel_desc boe_nv140fhmn49 = {
1342 .modes = boe_nv140fhmn49_modes,
1343 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1344 .bpc = 6,
1345 .size = {
1346 .width = 309,
1347 .height = 174,
1348 },
1349 .delay = {
1350 .prepare = 210,
1351 .enable = 50,
1352 .unprepare = 160,
1353 },
1354 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1355 .connector_type = DRM_MODE_CONNECTOR_eDP,
1356};
1357
e58edce6
GB		 1358static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1359 .clock = 9000,
1360 .hdisplay = 480,
1361 .hsync_start = 480 + 5,
1362 .hsync_end = 480 + 5 + 5,
1363 .htotal = 480 + 5 + 5 + 40,
1364 .vdisplay = 272,
1365 .vsync_start = 272 + 8,
1366 .vsync_end = 272 + 8 + 8,
1367 .vtotal = 272 + 8 + 8 + 8,
e58edce6
GB		 1368 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1369};
1370
1371static const struct panel_desc cdtech_s043wq26h_ct7 = {
1372 .modes = &cdtech_s043wq26h_ct7_mode,
1373 .num_modes = 1,
1374 .bpc = 8,
1375 .size = {
1376 .width = 95,
1377 .height = 54,
1378 },
88bc4178 1379 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1380};
1381
0e3b67f6
MK		 1382/* S070PWS19HP-FC21 2017/04/22 */
1383static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1384 .clock = 51200,
1385 .hdisplay = 1024,
1386 .hsync_start = 1024 + 160,
1387 .hsync_end = 1024 + 160 + 20,
1388 .htotal = 1024 + 160 + 20 + 140,
1389 .vdisplay = 600,
1390 .vsync_start = 600 + 12,
1391 .vsync_end = 600 + 12 + 3,
1392 .vtotal = 600 + 12 + 3 + 20,
1393 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1394};
1395
1396static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1397 .modes = &cdtech_s070pws19hp_fc21_mode,
1398 .num_modes = 1,
1399 .bpc = 6,
1400 .size = {
1401 .width = 154,
1402 .height = 86,
1403 },
1404 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1405 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1406 .connector_type = DRM_MODE_CONNECTOR_DPI,
1407};
1408
1409/* S070SWV29HG-DC44 2017/09/21 */
1410static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1411 .clock = 33300,
1412 .hdisplay = 800,
1413 .hsync_start = 800 + 210,
1414 .hsync_end = 800 + 210 + 2,
1415 .htotal = 800 + 210 + 2 + 44,
1416 .vdisplay = 480,
1417 .vsync_start = 480 + 22,
1418 .vsync_end = 480 + 22 + 2,
1419 .vtotal = 480 + 22 + 2 + 21,
1420 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1421};
1422
1423static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1424 .modes = &cdtech_s070swv29hg_dc44_mode,
1425 .num_modes = 1,
1426 .bpc = 6,
1427 .size = {
1428 .width = 154,
1429 .height = 86,
1430 },
1431 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1432 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1433 .connector_type = DRM_MODE_CONNECTOR_DPI,
1434};
1435
982f944e
GB		 1436static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1437 .clock = 35000,
1438 .hdisplay = 800,
1439 .hsync_start = 800 + 40,
1440 .hsync_end = 800 + 40 + 40,
1441 .htotal = 800 + 40 + 40 + 48,
1442 .vdisplay = 480,
1443 .vsync_start = 480 + 29,
1444 .vsync_end = 480 + 29 + 13,
1445 .vtotal = 480 + 29 + 13 + 3,
982f944e
GB		 1446 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1447};
1448
1449static const struct panel_desc cdtech_s070wv95_ct16 = {
1450 .modes = &cdtech_s070wv95_ct16_mode,
1451 .num_modes = 1,
1452 .bpc = 8,
1453 .size = {
1454 .width = 154,
1455 .height = 85,
1456 },
1457};
1458
07c913c4
MV		 1459static const struct display_timing chefree_ch101olhlwh_002_timing = {
1460 .pixelclock = { 68900000, 71100000, 73400000 },
1461 .hactive = { 1280, 1280, 1280 },
1462 .hfront_porch = { 65, 80, 95 },
1463 .hback_porch = { 64, 79, 94 },
1464 .hsync_len = { 1, 1, 1 },
1465 .vactive = { 800, 800, 800 },
1466 .vfront_porch = { 7, 11, 14 },
1467 .vback_porch = { 7, 11, 14 },
1468 .vsync_len = { 1, 1, 1 },
1469 .flags = DISPLAY_FLAGS_DE_HIGH,
1470};
1471
1472static const struct panel_desc chefree_ch101olhlwh_002 = {
1473 .timings = &chefree_ch101olhlwh_002_timing,
1474 .num_timings = 1,
1475 .bpc = 8,
1476 .size = {
1477 .width = 217,
1478 .height = 135,
1479 },
1480 .delay = {
1481 .enable = 200,
1482 .disable = 200,
1483 },
1484 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1486 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1487};
1488
2cb35c80
RL		 1489static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1490 .clock = 66770,
1491 .hdisplay = 800,
1492 .hsync_start = 800 + 49,
1493 .hsync_end = 800 + 49 + 33,
1494 .htotal = 800 + 49 + 33 + 17,
1495 .vdisplay = 1280,
1496 .vsync_start = 1280 + 1,
1497 .vsync_end = 1280 + 1 + 7,
1498 .vtotal = 1280 + 1 + 7 + 15,
2cb35c80
RL		 1499 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1500};
1501
1502static const struct panel_desc chunghwa_claa070wp03xg = {
1503 .modes = &chunghwa_claa070wp03xg_mode,
1504 .num_modes = 1,
1505 .bpc = 6,
1506 .size = {
1507 .width = 94,
1508 .height = 150,
1509 },
85560829 1510 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1511 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1512 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2cb35c80
RL		 1513};
1514
4c930757
SW		 1515static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1516 .clock = 72070,
1517 .hdisplay = 1366,
1518 .hsync_start = 1366 + 58,
1519 .hsync_end = 1366 + 58 + 58,
1520 .htotal = 1366 + 58 + 58 + 58,
1521 .vdisplay = 768,
1522 .vsync_start = 768 + 4,
1523 .vsync_end = 768 + 4 + 4,
1524 .vtotal = 768 + 4 + 4 + 4,
4c930757
SW		 1525};
1526
1527static const struct panel_desc chunghwa_claa101wa01a = {
1528 .modes = &chunghwa_claa101wa01a_mode,
1529 .num_modes = 1,
0208d511 1530 .bpc = 6,
4c930757
SW		 1531 .size = {
1532 .width = 220,
1533 .height = 120,
1534 },
85560829 1535 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1536 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1537 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4c930757
SW		 1538};
1539
280921de
TR		 1540static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1541 .clock = 69300,
1542 .hdisplay = 1366,
1543 .hsync_start = 1366 + 48,
1544 .hsync_end = 1366 + 48 + 32,
1545 .htotal = 1366 + 48 + 32 + 20,
1546 .vdisplay = 768,
1547 .vsync_start = 768 + 16,
1548 .vsync_end = 768 + 16 + 8,
1549 .vtotal = 768 + 16 + 8 + 16,
280921de
TR		 1550};
1551
1552static const struct panel_desc chunghwa_claa101wb01 = {
1553 .modes = &chunghwa_claa101wb01_mode,
1554 .num_modes = 1,
0208d511 1555 .bpc = 6,
280921de
TR		 1556 .size = {
1557 .width = 223,
1558 .height = 125,
1559 },
85560829 1560 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1561 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1562 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 1563};
1564
97ceb1fb
MV		 1565static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1566 .clock = 33260,
1567 .hdisplay = 800,
1568 .hsync_start = 800 + 40,
1569 .hsync_end = 800 + 40 + 128,
1570 .htotal = 800 + 40 + 128 + 88,
1571 .vdisplay = 480,
1572 .vsync_start = 480 + 10,
1573 .vsync_end = 480 + 10 + 2,
1574 .vtotal = 480 + 10 + 2 + 33,
97ceb1fb
MV		 1575 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1576};
1577
1578static const struct panel_desc dataimage_scf0700c48ggu18 = {
1579 .modes = &dataimage_scf0700c48ggu18_mode,
1580 .num_modes = 1,
1581 .bpc = 8,
1582 .size = {
1583 .width = 152,
1584 .height = 91,
1585 },
1586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1588};
1589
0ca0c827
PZ		 1590static const struct display_timing dlc_dlc0700yzg_1_timing = {
1591 .pixelclock = { 45000000, 51200000, 57000000 },
1592 .hactive = { 1024, 1024, 1024 },
1593 .hfront_porch = { 100, 106, 113 },
1594 .hback_porch = { 100, 106, 113 },
1595 .hsync_len = { 100, 108, 114 },
1596 .vactive = { 600, 600, 600 },
1597 .vfront_porch = { 8, 11, 15 },
1598 .vback_porch = { 8, 11, 15 },
1599 .vsync_len = { 9, 13, 15 },
1600 .flags = DISPLAY_FLAGS_DE_HIGH,
1601};
1602
1603static const struct panel_desc dlc_dlc0700yzg_1 = {
1604 .timings = &dlc_dlc0700yzg_1_timing,
1605 .num_timings = 1,
1606 .bpc = 6,
1607 .size = {
1608 .width = 154,
1609 .height = 86,
1610 },
1611 .delay = {
1612 .prepare = 30,
1613 .enable = 200,
1614 .disable = 200,
1615 },
1616 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1617 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1618};
1619
6cbe7cd1
MF		 1620static const struct display_timing dlc_dlc1010gig_timing = {
1621 .pixelclock = { 68900000, 71100000, 73400000 },
1622 .hactive = { 1280, 1280, 1280 },
1623 .hfront_porch = { 43, 53, 63 },
1624 .hback_porch = { 43, 53, 63 },
1625 .hsync_len = { 44, 54, 64 },
1626 .vactive = { 800, 800, 800 },
1627 .vfront_porch = { 5, 8, 11 },
1628 .vback_porch = { 5, 8, 11 },
1629 .vsync_len = { 5, 7, 11 },
1630 .flags = DISPLAY_FLAGS_DE_HIGH,
1631};
1632
1633static const struct panel_desc dlc_dlc1010gig = {
1634 .timings = &dlc_dlc1010gig_timing,
1635 .num_timings = 1,
1636 .bpc = 8,
1637 .size = {
1638 .width = 216,
1639 .height = 135,
1640 },
1641 .delay = {
1642 .prepare = 60,
1643 .enable = 150,
1644 .disable = 100,
1645 .unprepare = 60,
1646 },
1647 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1648 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1649};
1650
c2d24af6
AP		 1651static const struct drm_display_mode edt_et035012dm6_mode = {
1652 .clock = 6500,
1653 .hdisplay = 320,
1654 .hsync_start = 320 + 20,
1655 .hsync_end = 320 + 20 + 30,
1656 .htotal = 320 + 20 + 68,
1657 .vdisplay = 240,
1658 .vsync_start = 240 + 4,
1659 .vsync_end = 240 + 4 + 4,
1660 .vtotal = 240 + 4 + 4 + 14,
c2d24af6
AP		 1661 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1662};
1663
1664static const struct panel_desc edt_et035012dm6 = {
1665 .modes = &edt_et035012dm6_mode,
1666 .num_modes = 1,
1667 .bpc = 8,
1668 .size = {
1669 .width = 70,
1670 .height = 52,
1671 },
1672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1673 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
c2d24af6
AP		 1674};
1675
82d57a59
MCR		 1676static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1677 .clock = 10870,
1678 .hdisplay = 480,
1679 .hsync_start = 480 + 8,
1680 .hsync_end = 480 + 8 + 4,
1681 .htotal = 480 + 8 + 4 + 41,
1682
1683 /*
1684 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1685 * fb_align
1686 */
1687
1688 .vdisplay = 288,
1689 .vsync_start = 288 + 2,
1690 .vsync_end = 288 + 2 + 4,
1691 .vtotal = 288 + 2 + 4 + 10,
82d57a59
MCR		 1692};
1693
1694static const struct panel_desc edt_etm043080dh6gp = {
1695 .modes = &edt_etm043080dh6gp_mode,
1696 .num_modes = 1,
1697 .bpc = 8,
1698 .size = {
1699 .width = 100,
1700 .height = 65,
1701 },
1702 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1703 .connector_type = DRM_MODE_CONNECTOR_DPI,
1704};
1705
fd819bff
MV		 1706static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1707 .clock = 9000,
1708 .hdisplay = 480,
1709 .hsync_start = 480 + 2,
1710 .hsync_end = 480 + 2 + 41,
1711 .htotal = 480 + 2 + 41 + 2,
1712 .vdisplay = 272,
1713 .vsync_start = 272 + 2,
1714 .vsync_end = 272 + 2 + 10,
1715 .vtotal = 272 + 2 + 10 + 2,
fd819bff
MV		 1716 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1717};
1718
1719static const struct panel_desc edt_etm0430g0dh6 = {
1720 .modes = &edt_etm0430g0dh6_mode,
1721 .num_modes = 1,
1722 .bpc = 6,
1723 .size = {
1724 .width = 95,
1725 .height = 54,
1726 },
1727};
1728
26ab0065
SA		 1729static const struct drm_display_mode edt_et057090dhu_mode = {
1730 .clock = 25175,
1731 .hdisplay = 640,
1732 .hsync_start = 640 + 16,
1733 .hsync_end = 640 + 16 + 30,
1734 .htotal = 640 + 16 + 30 + 114,
1735 .vdisplay = 480,
1736 .vsync_start = 480 + 10,
1737 .vsync_end = 480 + 10 + 3,
1738 .vtotal = 480 + 10 + 3 + 32,
26ab0065
SA		 1739 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1740};
1741
1742static const struct panel_desc edt_et057090dhu = {
1743 .modes = &edt_et057090dhu_mode,
1744 .num_modes = 1,
0208d511 1745 .bpc = 6,
26ab0065
SA		 1746 .size = {
1747 .width = 115,
1748 .height = 86,
1749 },
eaeebffa 1750 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1751 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
75e73224 1752 .connector_type = DRM_MODE_CONNECTOR_DPI,
26ab0065
SA		 1753};
1754
fff5de45
PZ		 1755static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1756 .clock = 33260,
1757 .hdisplay = 800,
1758 .hsync_start = 800 + 40,
1759 .hsync_end = 800 + 40 + 128,
1760 .htotal = 800 + 40 + 128 + 88,
1761 .vdisplay = 480,
1762 .vsync_start = 480 + 10,
1763 .vsync_end = 480 + 10 + 2,
1764 .vtotal = 480 + 10 + 2 + 33,
fff5de45
PZ		 1765 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1766};
1767
1768static const struct panel_desc edt_etm0700g0dh6 = {
1769 .modes = &edt_etm0700g0dh6_mode,
1770 .num_modes = 1,
0208d511 1771 .bpc = 6,
fff5de45
PZ		 1772 .size = {
1773 .width = 152,
1774 .height = 91,
1775 },
eaeebffa 1776 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1777 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
fff5de45
PZ		 1778};
1779
aa7e6455
JT		 1780static const struct panel_desc edt_etm0700g0bdh6 = {
1781 .modes = &edt_etm0700g0dh6_mode,
1782 .num_modes = 1,
1783 .bpc = 6,
1784 .size = {
1785 .width = 152,
1786 .height = 91,
1787 },
1788 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1789 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
aa7e6455
JT		 1790};
1791
9158e3c3
MF		 1792static const struct display_timing evervision_vgg804821_timing = {
1793 .pixelclock = { 27600000, 33300000, 50000000 },
1794 .hactive = { 800, 800, 800 },
1795 .hfront_porch = { 40, 66, 70 },
1796 .hback_porch = { 40, 67, 70 },
1797 .hsync_len = { 40, 67, 70 },
1798 .vactive = { 480, 480, 480 },
1799 .vfront_porch = { 6, 10, 10 },
1800 .vback_porch = { 7, 11, 11 },
1801 .vsync_len = { 7, 11, 11 },
1802 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1803 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1804 DISPLAY_FLAGS_SYNC_NEGEDGE,
1805};
1806
1807static const struct panel_desc evervision_vgg804821 = {
1808 .timings = &evervision_vgg804821_timing,
1809 .num_timings = 1,
1810 .bpc = 8,
1811 .size = {
1812 .width = 108,
1813 .height = 64,
1814 },
1815 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
9158e3c3
MF		 1817};
1818
102932b0
BB		 1819static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1820 .clock = 32260,
1821 .hdisplay = 800,
1822 .hsync_start = 800 + 168,
1823 .hsync_end = 800 + 168 + 64,
1824 .htotal = 800 + 168 + 64 + 88,
1825 .vdisplay = 480,
1826 .vsync_start = 480 + 37,
1827 .vsync_end = 480 + 37 + 2,
1828 .vtotal = 480 + 37 + 2 + 8,
102932b0
BB		 1829};
1830
1831static const struct panel_desc foxlink_fl500wvr00_a0t = {
1832 .modes = &foxlink_fl500wvr00_a0t_mode,
1833 .num_modes = 1,
d7a839cd 1834 .bpc = 8,
102932b0
BB		 1835 .size = {
1836 .width = 108,
1837 .height = 65,
1838 },
bb276cb3 1839 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1840};
1841
795db2af
PC		 1842static const struct drm_display_mode frida_frd350h54004_modes[] = {
1843 { /* 60 Hz */
1844 .clock = 6000,
1845 .hdisplay = 320,
1846 .hsync_start = 320 + 44,
1847 .hsync_end = 320 + 44 + 16,
1848 .htotal = 320 + 44 + 16 + 20,
1849 .vdisplay = 240,
1850 .vsync_start = 240 + 2,
1851 .vsync_end = 240 + 2 + 6,
1852 .vtotal = 240 + 2 + 6 + 2,
1853 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1854 },
1855 { /* 50 Hz */
1856 .clock = 5400,
1857 .hdisplay = 320,
1858 .hsync_start = 320 + 56,
1859 .hsync_end = 320 + 56 + 16,
1860 .htotal = 320 + 56 + 16 + 40,
1861 .vdisplay = 240,
1862 .vsync_start = 240 + 2,
1863 .vsync_end = 240 + 2 + 6,
1864 .vtotal = 240 + 2 + 6 + 2,
1865 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1866 },
7b6bd843
PC		 1867};
1868
1869static const struct panel_desc frida_frd350h54004 = {
795db2af
PC		 1870 .modes = frida_frd350h54004_modes,
1871 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
7b6bd843
PC		 1872 .bpc = 8,
1873 .size = {
1874 .width = 77,
1875 .height = 64,
1876 },
1877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 1878 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
7b6bd843
PC		 1879 .connector_type = DRM_MODE_CONNECTOR_DPI,
1880};
1881
3be20710
JT		 1882static const struct drm_display_mode friendlyarm_hd702e_mode = {
1883 .clock = 67185,
1884 .hdisplay = 800,
1885 .hsync_start = 800 + 20,
1886 .hsync_end = 800 + 20 + 24,
1887 .htotal = 800 + 20 + 24 + 20,
1888 .vdisplay = 1280,
1889 .vsync_start = 1280 + 4,
1890 .vsync_end = 1280 + 4 + 8,
1891 .vtotal = 1280 + 4 + 8 + 4,
3be20710
JT		 1892 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1893};
1894
1895static const struct panel_desc friendlyarm_hd702e = {
1896 .modes = &friendlyarm_hd702e_mode,
1897 .num_modes = 1,
1898 .size = {
1899 .width = 94,
1900 .height = 151,
1901 },
1902};
1903
d435a2af
PZ		 1904static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1905 .clock = 9000,
1906 .hdisplay = 480,
1907 .hsync_start = 480 + 5,
1908 .hsync_end = 480 + 5 + 1,
1909 .htotal = 480 + 5 + 1 + 40,
1910 .vdisplay = 272,
1911 .vsync_start = 272 + 8,
1912 .vsync_end = 272 + 8 + 1,
1913 .vtotal = 272 + 8 + 1 + 8,
d435a2af
PZ		 1914};
1915
1916static const struct panel_desc giantplus_gpg482739qs5 = {
1917 .modes = &giantplus_gpg482739qs5_mode,
1918 .num_modes = 1,
1919 .bpc = 8,
1920 .size = {
1921 .width = 95,
1922 .height = 54,
1923 },
33536a09 1924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1925};
1926
2c6574a9
PC		 1927static const struct display_timing giantplus_gpm940b0_timing = {
1928 .pixelclock = { 13500000, 27000000, 27500000 },
1929 .hactive = { 320, 320, 320 },
1930 .hfront_porch = { 14, 686, 718 },
1931 .hback_porch = { 50, 70, 255 },
1932 .hsync_len = { 1, 1, 1 },
1933 .vactive = { 240, 240, 240 },
1934 .vfront_porch = { 1, 1, 179 },
1935 .vback_porch = { 1, 21, 31 },
1936 .vsync_len = { 1, 1, 6 },
1937 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1938};
1939
1940static const struct panel_desc giantplus_gpm940b0 = {
1941 .timings = &giantplus_gpm940b0_timing,
1942 .num_timings = 1,
1943 .bpc = 8,
1944 .size = {
1945 .width = 60,
1946 .height = 45,
1947 },
1948 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
f5436f77 1949 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2c6574a9
PC		 1950};
1951
ab07725a
PZ		 1952static const struct display_timing hannstar_hsd070pww1_timing = {
1953 .pixelclock = { 64300000, 71100000, 82000000 },
1954 .hactive = { 1280, 1280, 1280 },
1955 .hfront_porch = { 1, 1, 10 },
1956 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1957 /*
1958 * According to the data sheet, the minimum horizontal blanking interval
1959 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1960 * minimum working horizontal blanking interval to be 60 clocks.
1961 */
1962 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 1963 .vactive = { 800, 800, 800 },
1964 .vfront_porch = { 1, 1, 10 },
1965 .vback_porch = { 1, 1, 10 },
1966 .vsync_len = { 1, 21, 203 },
1967 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1968};
1969
1970static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1971 .timings = &hannstar_hsd070pww1_timing,
1972 .num_timings = 1,
a853205e
PZ		 1973 .bpc = 6,
1974 .size = {
1975 .width = 151,
1976 .height = 94,
1977 },
58d6a7bc 1978 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1979 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 1980};
1981
c0d607e5
EN		 1982static const struct display_timing hannstar_hsd100pxn1_timing = {
1983 .pixelclock = { 55000000, 65000000, 75000000 },
1984 .hactive = { 1024, 1024, 1024 },
1985 .hfront_porch = { 40, 40, 40 },
1986 .hback_porch = { 220, 220, 220 },
1987 .hsync_len = { 20, 60, 100 },
1988 .vactive = { 768, 768, 768 },
1989 .vfront_porch = { 7, 7, 7 },
1990 .vback_porch = { 21, 21, 21 },
1991 .vsync_len = { 10, 10, 10 },
1992 .flags = DISPLAY_FLAGS_DE_HIGH,
1993};
1994
1995static const struct panel_desc hannstar_hsd100pxn1 = {
1996 .timings = &hannstar_hsd100pxn1_timing,
1997 .num_timings = 1,
1998 .bpc = 6,
1999 .size = {
2000 .width = 203,
2001 .height = 152,
2002 },
4946b043 2003 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 2005};
2006
61ac0bf8
LS		 2007static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2008 .clock = 33333,
2009 .hdisplay = 800,
2010 .hsync_start = 800 + 85,
2011 .hsync_end = 800 + 85 + 86,
2012 .htotal = 800 + 85 + 86 + 85,
2013 .vdisplay = 480,
2014 .vsync_start = 480 + 16,
2015 .vsync_end = 480 + 16 + 13,
2016 .vtotal = 480 + 16 + 13 + 16,
61ac0bf8
LS		 2017};
2018
2019static const struct panel_desc hitachi_tx23d38vm0caa = {
2020 .modes = &hitachi_tx23d38vm0caa_mode,
2021 .num_modes = 1,
2022 .bpc = 6,
2023 .size = {
2024 .width = 195,
2025 .height = 117,
2026 },
6c684e3b
PZ		 2027 .delay = {
2028 .enable = 160,
2029 .disable = 160,
2030 },
61ac0bf8
LS		 2031};
2032
41bcceb4
NF		 2033static const struct drm_display_mode innolux_at043tn24_mode = {
2034 .clock = 9000,
2035 .hdisplay = 480,
2036 .hsync_start = 480 + 2,
2037 .hsync_end = 480 + 2 + 41,
2038 .htotal = 480 + 2 + 41 + 2,
2039 .vdisplay = 272,
2040 .vsync_start = 272 + 2,
a483159d
PZ		 2041 .vsync_end = 272 + 2 + 10,
2042 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 2043 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2044};
2045
2046static const struct panel_desc innolux_at043tn24 = {
2047 .modes = &innolux_at043tn24_mode,
2048 .num_modes = 1,
2049 .bpc = 8,
2050 .size = {
2051 .width = 95,
2052 .height = 54,
2053 },
2054 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2055 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 2056};
2057
4fc24ab3
RB		 2058static const struct drm_display_mode innolux_at070tn92_mode = {
2059 .clock = 33333,
2060 .hdisplay = 800,
2061 .hsync_start = 800 + 210,
2062 .hsync_end = 800 + 210 + 20,
2063 .htotal = 800 + 210 + 20 + 46,
2064 .vdisplay = 480,
2065 .vsync_start = 480 + 22,
2066 .vsync_end = 480 + 22 + 10,
2067 .vtotal = 480 + 22 + 23 + 10,
4fc24ab3
RB		 2068};
2069
2070static const struct panel_desc innolux_at070tn92 = {
2071 .modes = &innolux_at070tn92_mode,
2072 .num_modes = 1,
2073 .size = {
2074 .width = 154,
2075 .height = 86,
2076 },
2077 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2078};
2079
a5d2ade6
CF		 2080static const struct display_timing innolux_g070y2_l01_timing = {
2081 .pixelclock = { 28000000, 29500000, 32000000 },
2082 .hactive = { 800, 800, 800 },
2083 .hfront_porch = { 61, 91, 141 },
2084 .hback_porch = { 60, 90, 140 },
2085 .hsync_len = { 12, 12, 12 },
2086 .vactive = { 480, 480, 480 },
2087 .vfront_porch = { 4, 9, 30 },
2088 .vback_porch = { 4, 8, 28 },
2089 .vsync_len = { 2, 2, 2 },
2090 .flags = DISPLAY_FLAGS_DE_HIGH,
2091};
2092
2093static const struct panel_desc innolux_g070y2_l01 = {
2094 .timings = &innolux_g070y2_l01_timing,
2095 .num_timings = 1,
2096 .bpc = 6,
2097 .size = {
2098 .width = 152,
2099 .height = 91,
2100 },
2101 .delay = {
2102 .prepare = 10,
2103 .enable = 100,
2104 .disable = 100,
2105 .unprepare = 800,
2106 },
2107 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2108 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 2109};
2110
1e29b840
MO		 2111static const struct display_timing innolux_g101ice_l01_timing = {
2112 .pixelclock = { 60400000, 71100000, 74700000 },
2113 .hactive = { 1280, 1280, 1280 },
2114 .hfront_porch = { 41, 80, 100 },
2115 .hback_porch = { 40, 79, 99 },
2116 .hsync_len = { 1, 1, 1 },
2117 .vactive = { 800, 800, 800 },
2118 .vfront_porch = { 5, 11, 14 },
2119 .vback_porch = { 4, 11, 14 },
2120 .vsync_len = { 1, 1, 1 },
2121 .flags = DISPLAY_FLAGS_DE_HIGH,
2122};
2123
2124static const struct panel_desc innolux_g101ice_l01 = {
2125 .timings = &innolux_g101ice_l01_timing,
2126 .num_timings = 1,
2127 .bpc = 8,
2128 .size = {
2129 .width = 217,
2130 .height = 135,
2131 },
2132 .delay = {
2133 .enable = 200,
2134 .disable = 200,
2135 },
2136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 2138};
2139
4ae13e48
LS		 2140static const struct display_timing innolux_g121i1_l01_timing = {
2141 .pixelclock = { 67450000, 71000000, 74550000 },
2142 .hactive = { 1280, 1280, 1280 },
2143 .hfront_porch = { 40, 80, 160 },
2144 .hback_porch = { 39, 79, 159 },
2145 .hsync_len = { 1, 1, 1 },
2146 .vactive = { 800, 800, 800 },
2147 .vfront_porch = { 5, 11, 100 },
2148 .vback_porch = { 4, 11, 99 },
2149 .vsync_len = { 1, 1, 1 },
d731f661
LS		 2150};
2151
2152static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 2153 .timings = &innolux_g121i1_l01_timing,
2154 .num_timings = 1,
d731f661
LS		 2155 .bpc = 6,
2156 .size = {
2157 .width = 261,
2158 .height = 163,
2159 },
4ae13e48
LS		 2160 .delay = {
2161 .enable = 200,
2162 .disable = 20,
2163 },
2164 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2165 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 2166};
2167
f8fa17ba
AB		 2168static const struct drm_display_mode innolux_g121x1_l03_mode = {
2169 .clock = 65000,
2170 .hdisplay = 1024,
2171 .hsync_start = 1024 + 0,
2172 .hsync_end = 1024 + 1,
2173 .htotal = 1024 + 0 + 1 + 320,
2174 .vdisplay = 768,
2175 .vsync_start = 768 + 38,
2176 .vsync_end = 768 + 38 + 1,
2177 .vtotal = 768 + 38 + 1 + 0,
2e8c5eb9 2178 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 2179};
2180
2181static const struct panel_desc innolux_g121x1_l03 = {
2182 .modes = &innolux_g121x1_l03_mode,
2183 .num_modes = 1,
2184 .bpc = 6,
2185 .size = {
2186 .width = 246,
2187 .height = 185,
2188 },
2189 .delay = {
2190 .enable = 200,
2191 .unprepare = 200,
2192 .disable = 400,
2193 },
2194};
2195
d719cbe9
DA		 2196/*
2197 * Datasheet specifies that at 60 Hz refresh rate:
2198 * - total horizontal time: { 1506, 1592, 1716 }
2199 * - total vertical time: { 788, 800, 868 }
2200 *
2201 * ...but doesn't go into exactly how that should be split into a front
2202 * porch, back porch, or sync length. For now we'll leave a single setting
2203 * here which allows a bit of tweaking of the pixel clock at the expense of
2204 * refresh rate.
2205 */
2206static const struct display_timing innolux_n116bge_timing = {
2207 .pixelclock = { 72600000, 76420000, 80240000 },
2208 .hactive = { 1366, 1366, 1366 },
2209 .hfront_porch = { 136, 136, 136 },
2210 .hback_porch = { 60, 60, 60 },
2211 .hsync_len = { 30, 30, 30 },
2212 .vactive = { 768, 768, 768 },
2213 .vfront_porch = { 8, 8, 8 },
2214 .vback_porch = { 12, 12, 12 },
2215 .vsync_len = { 12, 12, 12 },
2216 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
0a2288c0
TR		 2217};
2218
2219static const struct panel_desc innolux_n116bge = {
d719cbe9
DA		 2220 .timings = &innolux_n116bge_timing,
2221 .num_timings = 1,
0a2288c0
TR		 2222 .bpc = 6,
2223 .size = {
2224 .width = 256,
2225 .height = 144,
2226 },
2227};
2228
ea44739d
AB		 2229static const struct drm_display_mode innolux_n156bge_l21_mode = {
2230 .clock = 69300,
2231 .hdisplay = 1366,
2232 .hsync_start = 1366 + 16,
2233 .hsync_end = 1366 + 16 + 34,
2234 .htotal = 1366 + 16 + 34 + 50,
2235 .vdisplay = 768,
2236 .vsync_start = 768 + 2,
2237 .vsync_end = 768 + 2 + 6,
2238 .vtotal = 768 + 2 + 6 + 12,
ea44739d
AB		 2239};
2240
2241static const struct panel_desc innolux_n156bge_l21 = {
2242 .modes = &innolux_n156bge_l21_mode,
2243 .num_modes = 1,
0208d511 2244 .bpc = 6,
ea44739d
AB		 2245 .size = {
2246 .width = 344,
2247 .height = 193,
2248 },
85560829 2249 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 2250 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 2251 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ea44739d
AB		 2252};
2253
8f054b6f 2254static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 2255 .clock = 206016,
2256 .hdisplay = 2160,
2257 .hsync_start = 2160 + 48,
2258 .hsync_end = 2160 + 48 + 32,
2259 .htotal = 2160 + 48 + 32 + 80,
2260 .vdisplay = 1440,
2261 .vsync_start = 1440 + 3,
2262 .vsync_end = 1440 + 3 + 10,
2263 .vtotal = 1440 + 3 + 10 + 27,
da50bd42 2264 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2265};
2266
8f054b6f
DA		 2267static const struct panel_desc innolux_p120zdg_bf1 = {
2268 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 2269 .num_modes = 1,
2270 .bpc = 8,
2271 .size = {
8f054b6f
DA		 2272 .width = 254,
2273 .height = 169,
da50bd42 2274 },
22fd99e9 2275 .delay = {
625d3b5c 2276 .hpd_absent_delay = 200,
22fd99e9
SP		 2277 .unprepare = 500,
2278 },
da50bd42 2279};
2280
bccac3f1
MG		 2281static const struct drm_display_mode innolux_zj070na_01p_mode = {
2282 .clock = 51501,
2283 .hdisplay = 1024,
2284 .hsync_start = 1024 + 128,
2285 .hsync_end = 1024 + 128 + 64,
2286 .htotal = 1024 + 128 + 64 + 128,
2287 .vdisplay = 600,
2288 .vsync_start = 600 + 16,
2289 .vsync_end = 600 + 16 + 4,
2290 .vtotal = 600 + 16 + 4 + 16,
bccac3f1
MG		 2291};
2292
2293static const struct panel_desc innolux_zj070na_01p = {
2294 .modes = &innolux_zj070na_01p_mode,
2295 .num_modes = 1,
2296 .bpc = 6,
2297 .size = {
81598846
TR		 2298 .width = 154,
2299 .height = 90,
bccac3f1
MG		 2300 },
2301};
2302
e1ca5184
BA		 2303static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2304 .clock = 138778,
2305 .hdisplay = 1920,
2306 .hsync_start = 1920 + 24,
2307 .hsync_end = 1920 + 24 + 48,
2308 .htotal = 1920 + 24 + 48 + 88,
2309 .vdisplay = 1080,
2310 .vsync_start = 1080 + 3,
2311 .vsync_end = 1080 + 3 + 12,
2312 .vtotal = 1080 + 3 + 12 + 17,
e1ca5184
BA		 2313 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2314};
2315
2316static const struct panel_desc ivo_m133nwf4_r0 = {
2317 .modes = &ivo_m133nwf4_r0_mode,
2318 .num_modes = 1,
2319 .bpc = 8,
2320 .size = {
2321 .width = 294,
2322 .height = 165,
2323 },
2324 .delay = {
2325 .hpd_absent_delay = 200,
2326 .unprepare = 500,
2327 },
2328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2329 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2330 .connector_type = DRM_MODE_CONNECTOR_eDP,
2331};
2332
14bf60c4
LM		 2333static const struct display_timing koe_tx14d24vm1bpa_timing = {
2334 .pixelclock = { 5580000, 5850000, 6200000 },
2335 .hactive = { 320, 320, 320 },
2336 .hfront_porch = { 30, 30, 30 },
2337 .hback_porch = { 30, 30, 30 },
2338 .hsync_len = { 1, 5, 17 },
2339 .vactive = { 240, 240, 240 },
2340 .vfront_porch = { 6, 6, 6 },
2341 .vback_porch = { 5, 5, 5 },
2342 .vsync_len = { 1, 2, 11 },
2343 .flags = DISPLAY_FLAGS_DE_HIGH,
2344};
2345
2346static const struct panel_desc koe_tx14d24vm1bpa = {
2347 .timings = &koe_tx14d24vm1bpa_timing,
2348 .num_timings = 1,
2349 .bpc = 6,
2350 .size = {
2351 .width = 115,
2352 .height = 86,
2353 },
2354};
2355
8a070524
LY		 2356static const struct display_timing koe_tx26d202vm0bwa_timing = {
2357 .pixelclock = { 151820000, 156720000, 159780000 },
2358 .hactive = { 1920, 1920, 1920 },
2359 .hfront_porch = { 105, 130, 142 },
2360 .hback_porch = { 45, 70, 82 },
2361 .hsync_len = { 30, 30, 30 },
2362 .vactive = { 1200, 1200, 1200},
2363 .vfront_porch = { 3, 5, 10 },
2364 .vback_porch = { 2, 5, 10 },
2365 .vsync_len = { 5, 5, 5 },
2366};
2367
2368static const struct panel_desc koe_tx26d202vm0bwa = {
2369 .timings = &koe_tx26d202vm0bwa_timing,
2370 .num_timings = 1,
2371 .bpc = 8,
2372 .size = {
2373 .width = 217,
2374 .height = 136,
2375 },
2376 .delay = {
2377 .prepare = 1000,
2378 .enable = 1000,
2379 .unprepare = 1000,
2380 .disable = 1000,
2381 },
2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2383 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
8a070524
LY		 2384 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2385};
2386
8cfe8341
JT		 2387static const struct display_timing koe_tx31d200vm0baa_timing = {
2388 .pixelclock = { 39600000, 43200000, 48000000 },
2389 .hactive = { 1280, 1280, 1280 },
2390 .hfront_porch = { 16, 36, 56 },
2391 .hback_porch = { 16, 36, 56 },
2392 .hsync_len = { 8, 8, 8 },
2393 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 2394 .vfront_porch = { 6, 21, 33 },
2395 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 2396 .vsync_len = { 8, 8, 8 },
2397 .flags = DISPLAY_FLAGS_DE_HIGH,
2398};
2399
2400static const struct panel_desc koe_tx31d200vm0baa = {
2401 .timings = &koe_tx31d200vm0baa_timing,
2402 .num_timings = 1,
2403 .bpc = 6,
2404 .size = {
2405 .width = 292,
2406 .height = 109,
2407 },
2408 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2409 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 2410};
2411
8def22e5
LS		 2412static const struct display_timing kyo_tcg121xglp_timing = {
2413 .pixelclock = { 52000000, 65000000, 71000000 },
2414 .hactive = { 1024, 1024, 1024 },
2415 .hfront_porch = { 2, 2, 2 },
2416 .hback_porch = { 2, 2, 2 },
2417 .hsync_len = { 86, 124, 244 },
2418 .vactive = { 768, 768, 768 },
2419 .vfront_porch = { 2, 2, 2 },
2420 .vback_porch = { 2, 2, 2 },
2421 .vsync_len = { 6, 34, 73 },
2422 .flags = DISPLAY_FLAGS_DE_HIGH,
2423};
2424
2425static const struct panel_desc kyo_tcg121xglp = {
2426 .timings = &kyo_tcg121xglp_timing,
2427 .num_timings = 1,
2428 .bpc = 8,
2429 .size = {
2430 .width = 246,
2431 .height = 184,
2432 },
2433 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2434 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 2435};
2436
27abdd83
PK		 2437static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2438 .clock = 7000,
2439 .hdisplay = 320,
2440 .hsync_start = 320 + 20,
2441 .hsync_end = 320 + 20 + 30,
2442 .htotal = 320 + 20 + 30 + 38,
2443 .vdisplay = 240,
2444 .vsync_start = 240 + 4,
2445 .vsync_end = 240 + 4 + 3,
2446 .vtotal = 240 + 4 + 3 + 15,
27abdd83
PK		 2447};
2448
2449static const struct panel_desc lemaker_bl035_rgb_002 = {
2450 .modes = &lemaker_bl035_rgb_002_mode,
2451 .num_modes = 1,
2452 .size = {
2453 .width = 70,
2454 .height = 52,
2455 },
2456 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2457 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2458};
2459
dd015002
HS		 2460static const struct drm_display_mode lg_lb070wv8_mode = {
2461 .clock = 33246,
2462 .hdisplay = 800,
2463 .hsync_start = 800 + 88,
2464 .hsync_end = 800 + 88 + 80,
2465 .htotal = 800 + 88 + 80 + 88,
2466 .vdisplay = 480,
2467 .vsync_start = 480 + 10,
2468 .vsync_end = 480 + 10 + 25,
2469 .vtotal = 480 + 10 + 25 + 10,
dd015002
HS		 2470};
2471
2472static const struct panel_desc lg_lb070wv8 = {
2473 .modes = &lg_lb070wv8_mode,
2474 .num_modes = 1,
a6ae2fe5 2475 .bpc = 8,
dd015002
HS		 2476 .size = {
2477 .width = 151,
2478 .height = 91,
2479 },
2480 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2481 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 2482};
2483
c5ece402
YY		 2484static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2485 .clock = 200000,
2486 .hdisplay = 1536,
2487 .hsync_start = 1536 + 12,
2488 .hsync_end = 1536 + 12 + 16,
2489 .htotal = 1536 + 12 + 16 + 48,
2490 .vdisplay = 2048,
2491 .vsync_start = 2048 + 8,
2492 .vsync_end = 2048 + 8 + 4,
2493 .vtotal = 2048 + 8 + 4 + 8,
c5ece402
YY		 2494 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2495};
2496
2497static const struct panel_desc lg_lp079qx1_sp0v = {
2498 .modes = &lg_lp079qx1_sp0v_mode,
2499 .num_modes = 1,
2500 .size = {
2501 .width = 129,
2502 .height = 171,
2503 },
2504};
2505
0355dde2
YY		 2506static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2507 .clock = 205210,
2508 .hdisplay = 2048,
2509 .hsync_start = 2048 + 150,
2510 .hsync_end = 2048 + 150 + 5,
2511 .htotal = 2048 + 150 + 5 + 5,
2512 .vdisplay = 1536,
2513 .vsync_start = 1536 + 3,
2514 .vsync_end = 1536 + 3 + 1,
2515 .vtotal = 1536 + 3 + 1 + 9,
0355dde2
YY		 2516};
2517
2518static const struct panel_desc lg_lp097qx1_spa1 = {
2519 .modes = &lg_lp097qx1_spa1_mode,
2520 .num_modes = 1,
2521 .size = {
2522 .width = 208,
2523 .height = 147,
2524 },
2525};
2526
690d8fa7
JS		 2527static const struct drm_display_mode lg_lp120up1_mode = {
2528 .clock = 162300,
2529 .hdisplay = 1920,
2530 .hsync_start = 1920 + 40,
2531 .hsync_end = 1920 + 40 + 40,
2532 .htotal = 1920 + 40 + 40+ 80,
2533 .vdisplay = 1280,
2534 .vsync_start = 1280 + 4,
2535 .vsync_end = 1280 + 4 + 4,
2536 .vtotal = 1280 + 4 + 4 + 12,
690d8fa7
JS		 2537};
2538
2539static const struct panel_desc lg_lp120up1 = {
2540 .modes = &lg_lp120up1_mode,
2541 .num_modes = 1,
2542 .bpc = 8,
2543 .size = {
2544 .width = 267,
2545 .height = 183,
2546 },
d53139b3 2547 .connector_type = DRM_MODE_CONNECTOR_eDP,
690d8fa7
JS		 2548};
2549
ec7c5653
TR		 2550static const struct drm_display_mode lg_lp129qe_mode = {
2551 .clock = 285250,
2552 .hdisplay = 2560,
2553 .hsync_start = 2560 + 48,
2554 .hsync_end = 2560 + 48 + 32,
2555 .htotal = 2560 + 48 + 32 + 80,
2556 .vdisplay = 1700,
2557 .vsync_start = 1700 + 3,
2558 .vsync_end = 1700 + 3 + 10,
2559 .vtotal = 1700 + 3 + 10 + 36,
ec7c5653
TR		 2560};
2561
2562static const struct panel_desc lg_lp129qe = {
2563 .modes = &lg_lp129qe_mode,
2564 .num_modes = 1,
0208d511 2565 .bpc = 8,
ec7c5653
TR		 2566 .size = {
2567 .width = 272,
2568 .height = 181,
2569 },
2570};
2571
5728fe7f
MZ		 2572static const struct display_timing logictechno_lt161010_2nh_timing = {
2573 .pixelclock = { 26400000, 33300000, 46800000 },
2574 .hactive = { 800, 800, 800 },
2575 .hfront_porch = { 16, 210, 354 },
2576 .hback_porch = { 46, 46, 46 },
2577 .hsync_len = { 1, 20, 40 },
2578 .vactive = { 480, 480, 480 },
2579 .vfront_porch = { 7, 22, 147 },
2580 .vback_porch = { 23, 23, 23 },
2581 .vsync_len = { 1, 10, 20 },
2582 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2583 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2584 DISPLAY_FLAGS_SYNC_POSEDGE,
2585};
2586
2587static const struct panel_desc logictechno_lt161010_2nh = {
2588 .timings = &logictechno_lt161010_2nh_timing,
2589 .num_timings = 1,
2590 .size = {
2591 .width = 154,
2592 .height = 86,
2593 },
2594 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2595 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2596 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2597 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2598 .connector_type = DRM_MODE_CONNECTOR_DPI,
2599};
2600
2601static const struct display_timing logictechno_lt170410_2whc_timing = {
2602 .pixelclock = { 68900000, 71100000, 73400000 },
2603 .hactive = { 1280, 1280, 1280 },
2604 .hfront_porch = { 23, 60, 71 },
2605 .hback_porch = { 23, 60, 71 },
2606 .hsync_len = { 15, 40, 47 },
2607 .vactive = { 800, 800, 800 },
2608 .vfront_porch = { 5, 7, 10 },
2609 .vback_porch = { 5, 7, 10 },
2610 .vsync_len = { 6, 9, 12 },
2611 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2612 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2613 DISPLAY_FLAGS_SYNC_POSEDGE,
2614};
2615
2616static const struct panel_desc logictechno_lt170410_2whc = {
2617 .timings = &logictechno_lt170410_2whc_timing,
2618 .num_timings = 1,
2619 .size = {
2620 .width = 217,
2621 .height = 136,
2622 },
2623 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2624 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
5728fe7f
MZ		 2625 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2626};
2627
65c766ca
LM		 2628static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2629 .clock = 30400,
2630 .hdisplay = 800,
2631 .hsync_start = 800 + 0,
2632 .hsync_end = 800 + 1,
2633 .htotal = 800 + 0 + 1 + 160,
2634 .vdisplay = 480,
2635 .vsync_start = 480 + 0,
2636 .vsync_end = 480 + 48 + 1,
2637 .vtotal = 480 + 48 + 1 + 0,
65c766ca
LM		 2638 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2639};
2640
0d35408a 2641static const struct drm_display_mode logicpd_type_28_mode = {
f873c5d8 2642 .clock = 9107,
0d35408a
AF		 2643 .hdisplay = 480,
2644 .hsync_start = 480 + 3,
2645 .hsync_end = 480 + 3 + 42,
2646 .htotal = 480 + 3 + 42 + 2,
2647
2648 .vdisplay = 272,
2649 .vsync_start = 272 + 2,
2650 .vsync_end = 272 + 2 + 11,
2651 .vtotal = 272 + 2 + 11 + 3,
0d35408a
AF		 2652 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2653};
2654
2655static const struct panel_desc logicpd_type_28 = {
2656 .modes = &logicpd_type_28_mode,
2657 .num_modes = 1,
2658 .bpc = 8,
2659 .size = {
2660 .width = 105,
2661 .height = 67,
2662 },
2663 .delay = {
2664 .prepare = 200,
2665 .enable = 200,
2666 .unprepare = 200,
2667 .disable = 200,
2668 },
2669 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2671 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
efb94790 2672 .connector_type = DRM_MODE_CONNECTOR_DPI,
0d35408a
AF		 2673};
2674
65c766ca
LM		 2675static const struct panel_desc mitsubishi_aa070mc01 = {
2676 .modes = &mitsubishi_aa070mc01_mode,
2677 .num_modes = 1,
2678 .bpc = 8,
2679 .size = {
2680 .width = 152,
2681 .height = 91,
2682 },
2683
2684 .delay = {
2685 .enable = 200,
2686 .unprepare = 200,
2687 .disable = 400,
2688 },
2689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2690 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 2691 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2692};
2693
01bacc13
LS		 2694static const struct display_timing nec_nl12880bc20_05_timing = {
2695 .pixelclock = { 67000000, 71000000, 75000000 },
2696 .hactive = { 1280, 1280, 1280 },
2697 .hfront_porch = { 2, 30, 30 },
2698 .hback_porch = { 6, 100, 100 },
2699 .hsync_len = { 2, 30, 30 },
2700 .vactive = { 800, 800, 800 },
2701 .vfront_porch = { 5, 5, 5 },
2702 .vback_porch = { 11, 11, 11 },
2703 .vsync_len = { 7, 7, 7 },
2704};
2705
2706static const struct panel_desc nec_nl12880bc20_05 = {
2707 .timings = &nec_nl12880bc20_05_timing,
2708 .num_timings = 1,
2709 .bpc = 8,
2710 .size = {
2711 .width = 261,
2712 .height = 163,
2713 },
2714 .delay = {
2715 .enable = 50,
2716 .disable = 50,
2717 },
2718 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2719 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 2720};
2721
c6e87f91 2722static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2723 .clock = 10870,
2724 .hdisplay = 480,
2725 .hsync_start = 480 + 2,
2726 .hsync_end = 480 + 2 + 41,
2727 .htotal = 480 + 2 + 41 + 2,
2728 .vdisplay = 272,
2729 .vsync_start = 272 + 2,
2730 .vsync_end = 272 + 2 + 4,
2731 .vtotal = 272 + 2 + 4 + 2,
4bc390c6 2732 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 2733};
2734
2735static const struct panel_desc nec_nl4827hc19_05b = {
2736 .modes = &nec_nl4827hc19_05b_mode,
2737 .num_modes = 1,
2738 .bpc = 8,
2739 .size = {
2740 .width = 95,
2741 .height = 54,
2742 },
2c80661d 2743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2744 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 2745};
2746
e6c2f066
MR		 2747static const struct drm_display_mode netron_dy_e231732_mode = {
2748 .clock = 66000,
2749 .hdisplay = 1024,
2750 .hsync_start = 1024 + 160,
2751 .hsync_end = 1024 + 160 + 70,
2752 .htotal = 1024 + 160 + 70 + 90,
2753 .vdisplay = 600,
2754 .vsync_start = 600 + 127,
2755 .vsync_end = 600 + 127 + 20,
2756 .vtotal = 600 + 127 + 20 + 3,
e6c2f066
MR		 2757};
2758
2759static const struct panel_desc netron_dy_e231732 = {
2760 .modes = &netron_dy_e231732_mode,
2761 .num_modes = 1,
2762 .size = {
2763 .width = 154,
2764 .height = 87,
2765 },
2766 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2767};
2768
258145ea
VK		 2769static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2770 {
2771 .clock = 138500,
2772 .hdisplay = 1920,
2773 .hsync_start = 1920 + 48,
2774 .hsync_end = 1920 + 48 + 32,
2775 .htotal = 1920 + 48 + 32 + 80,
2776 .vdisplay = 1080,
2777 .vsync_start = 1080 + 3,
2778 .vsync_end = 1080 + 3 + 5,
2779 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 2780 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2781 }, {
2782 .clock = 110920,
2783 .hdisplay = 1920,
2784 .hsync_start = 1920 + 48,
2785 .hsync_end = 1920 + 48 + 32,
2786 .htotal = 1920 + 48 + 32 + 80,
2787 .vdisplay = 1080,
2788 .vsync_start = 1080 + 3,
2789 .vsync_end = 1080 + 3 + 5,
2790 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 2791 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2792 }
2793};
2794
2795static const struct panel_desc neweast_wjfh116008a = {
2796 .modes = neweast_wjfh116008a_modes,
2797 .num_modes = 2,
2798 .bpc = 6,
2799 .size = {
2800 .width = 260,
2801 .height = 150,
2802 },
2803 .delay = {
2804 .prepare = 110,
2805 .enable = 20,
2806 .unprepare = 500,
2807 },
2808 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2809 .connector_type = DRM_MODE_CONNECTOR_eDP,
2810};
2811
3b39ad7a
TV		 2812static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2813 .clock = 9000,
2814 .hdisplay = 480,
2815 .hsync_start = 480 + 2,
2816 .hsync_end = 480 + 2 + 41,
2817 .htotal = 480 + 2 + 41 + 2,
2818 .vdisplay = 272,
2819 .vsync_start = 272 + 2,
2820 .vsync_end = 272 + 2 + 10,
2821 .vtotal = 272 + 2 + 10 + 2,
3b39ad7a
TV		 2822 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2823};
2824
2825static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2826 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2827 .num_modes = 1,
2828 .bpc = 8,
2829 .size = {
2830 .width = 95,
2831 .height = 54,
2832 },
2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 2834 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2835 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
8a4f5e11 2836 .connector_type = DRM_MODE_CONNECTOR_DPI,
3b39ad7a
TV		 2837};
2838
4177fa66
LS		 2839static const struct display_timing nlt_nl192108ac18_02d_timing = {
2840 .pixelclock = { 130000000, 148350000, 163000000 },
2841 .hactive = { 1920, 1920, 1920 },
2842 .hfront_porch = { 80, 100, 100 },
2843 .hback_porch = { 100, 120, 120 },
2844 .hsync_len = { 50, 60, 60 },
2845 .vactive = { 1080, 1080, 1080 },
2846 .vfront_porch = { 12, 30, 30 },
2847 .vback_porch = { 4, 10, 10 },
2848 .vsync_len = { 4, 5, 5 },
2849};
2850
2851static const struct panel_desc nlt_nl192108ac18_02d = {
2852 .timings = &nlt_nl192108ac18_02d_timing,
2853 .num_timings = 1,
2854 .bpc = 8,
2855 .size = {
2856 .width = 344,
2857 .height = 194,
2858 },
2859 .delay = {
2860 .unprepare = 500,
2861 },
2862 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2863 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 2864};
2865
05ec0e45
FL		 2866static const struct drm_display_mode nvd_9128_mode = {
2867 .clock = 29500,
2868 .hdisplay = 800,
2869 .hsync_start = 800 + 130,
2870 .hsync_end = 800 + 130 + 98,
2871 .htotal = 800 + 0 + 130 + 98,
2872 .vdisplay = 480,
2873 .vsync_start = 480 + 10,
2874 .vsync_end = 480 + 10 + 50,
2875 .vtotal = 480 + 0 + 10 + 50,
2876};
2877
2878static const struct panel_desc nvd_9128 = {
2879 .modes = &nvd_9128_mode,
2880 .num_modes = 1,
2881 .bpc = 8,
2882 .size = {
2883 .width = 156,
2884 .height = 88,
2885 },
2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2887 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 2888};
2889
a99fb626
GB		 2890static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2891 .pixelclock = { 30000000, 30000000, 40000000 },
2892 .hactive = { 800, 800, 800 },
2893 .hfront_porch = { 40, 40, 40 },
2894 .hback_porch = { 40, 40, 40 },
2895 .hsync_len = { 1, 48, 48 },
2896 .vactive = { 480, 480, 480 },
2897 .vfront_porch = { 13, 13, 13 },
2898 .vback_porch = { 29, 29, 29 },
2899 .vsync_len = { 3, 3, 3 },
2900 .flags = DISPLAY_FLAGS_DE_HIGH,
2901};
2902
2903static const struct panel_desc okaya_rs800480t_7x0gp = {
2904 .timings = &okaya_rs800480t_7x0gp_timing,
2905 .num_timings = 1,
2906 .bpc = 6,
2907 .size = {
2908 .width = 154,
2909 .height = 87,
2910 },
2911 .delay = {
2912 .prepare = 41,
2913 .enable = 50,
2914 .unprepare = 41,
2915 .disable = 50,
2916 },
2917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2918};
2919
cf5c9e6d
MR		 2920static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2921 .clock = 9000,
2922 .hdisplay = 480,
2923 .hsync_start = 480 + 5,
2924 .hsync_end = 480 + 5 + 30,
2925 .htotal = 480 + 5 + 30 + 10,
2926 .vdisplay = 272,
2927 .vsync_start = 272 + 8,
2928 .vsync_end = 272 + 8 + 5,
2929 .vtotal = 272 + 8 + 5 + 3,
cf5c9e6d
MR		 2930};
2931
2932static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2933 .modes = &olimex_lcd_olinuxino_43ts_mode,
2934 .num_modes = 1,
2935 .size = {
30c6d7ab
JL		 2936 .width = 95,
2937 .height = 54,
cf5c9e6d 2938 },
5c2a7c6b 2939 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 2940};
2941
e8b6f561
EA		 2942/*
2943 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2944 * pixel clocks, but this is the timing that was being used in the Adafruit
2945 * installation instructions.
2946 */
2947static const struct drm_display_mode ontat_yx700wv03_mode = {
2948 .clock = 29500,
2949 .hdisplay = 800,
2950 .hsync_start = 824,
2951 .hsync_end = 896,
2952 .htotal = 992,
2953 .vdisplay = 480,
2954 .vsync_start = 483,
2955 .vsync_end = 493,
2956 .vtotal = 500,
e8b6f561
EA		 2957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2958};
2959
2960/*
2961 * Specification at:
2962 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2963 */
2964static const struct panel_desc ontat_yx700wv03 = {
2965 .modes = &ontat_yx700wv03_mode,
2966 .num_modes = 1,
2967 .bpc = 8,
2968 .size = {
2969 .width = 154,
2970 .height = 83,
2971 },
5651e5e0 2972 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 2973};
2974
9c31dcb6 2975static const struct drm_display_mode ortustech_com37h3m_mode = {
855e764d 2976 .clock = 22230,
9c31dcb6 2977 .hdisplay = 480,
855e764d
NS		 2978 .hsync_start = 480 + 40,
2979 .hsync_end = 480 + 40 + 10,
2980 .htotal = 480 + 40 + 10 + 40,
9c31dcb6
NS		 2981 .vdisplay = 640,
2982 .vsync_start = 640 + 4,
855e764d
NS		 2983 .vsync_end = 640 + 4 + 2,
2984 .vtotal = 640 + 4 + 2 + 4,
9c31dcb6
NS		 2985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2986};
2987
2988static const struct panel_desc ortustech_com37h3m = {
2989 .modes = &ortustech_com37h3m_mode,
2990 .num_modes = 1,
2991 .bpc = 8,
2992 .size = {
2993 .width = 56, /* 56.16mm */
2994 .height = 75, /* 74.88mm */
2995 },
2996 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2997 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
9c31dcb6
NS		 2998 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2999};
3000
725c9d40
PZ		 3001static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3002 .clock = 25000,
3003 .hdisplay = 480,
3004 .hsync_start = 480 + 10,
3005 .hsync_end = 480 + 10 + 10,
3006 .htotal = 480 + 10 + 10 + 15,
3007 .vdisplay = 800,
3008 .vsync_start = 800 + 3,
3009 .vsync_end = 800 + 3 + 3,
3010 .vtotal = 800 + 3 + 3 + 3,
725c9d40
PZ		 3011};
3012
3013static const struct panel_desc ortustech_com43h4m85ulc = {
3014 .modes = &ortustech_com43h4m85ulc_mode,
3015 .num_modes = 1,
3016 .bpc = 8,
3017 .size = {
3018 .width = 56,
3019 .height = 93,
3020 },
f098f168 3021 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 3022 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2ccedf46 3023 .connector_type = DRM_MODE_CONNECTOR_DPI,
725c9d40
PZ		 3024};
3025
163f7a35
LP		 3026static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3027 .clock = 33000,
3028 .hdisplay = 800,
3029 .hsync_start = 800 + 210,
3030 .hsync_end = 800 + 210 + 30,
3031 .htotal = 800 + 210 + 30 + 16,
3032 .vdisplay = 480,
3033 .vsync_start = 480 + 22,
3034 .vsync_end = 480 + 22 + 13,
3035 .vtotal = 480 + 22 + 13 + 10,
163f7a35
LP		 3036 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3037};
3038
3039static const struct panel_desc osddisplays_osd070t1718_19ts = {
3040 .modes = &osddisplays_osd070t1718_19ts_mode,
3041 .num_modes = 1,
3042 .bpc = 8,
3043 .size = {
3044 .width = 152,
3045 .height = 91,
3046 },
3047 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
fb0629ee
TV		 3048 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3049 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
a793f0ee 3050 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 3051};
3052
4ba3e563
EH		 3053static const struct drm_display_mode pda_91_00156_a0_mode = {
3054 .clock = 33300,
3055 .hdisplay = 800,
3056 .hsync_start = 800 + 1,
3057 .hsync_end = 800 + 1 + 64,
3058 .htotal = 800 + 1 + 64 + 64,
3059 .vdisplay = 480,
3060 .vsync_start = 480 + 1,
3061 .vsync_end = 480 + 1 + 23,
3062 .vtotal = 480 + 1 + 23 + 22,
4ba3e563
EH		 3063};
3064
3065static const struct panel_desc pda_91_00156_a0 = {
3066 .modes = &pda_91_00156_a0_mode,
3067 .num_modes = 1,
3068 .size = {
3069 .width = 152,
3070 .height = 91,
3071 },
3072 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3073};
3074
d69de69f
MV		 3075static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3076 .clock = 24750,
3077 .hdisplay = 800,
3078 .hsync_start = 800 + 54,
3079 .hsync_end = 800 + 54 + 2,
3080 .htotal = 800 + 54 + 2 + 44,
3081 .vdisplay = 480,
3082 .vsync_start = 480 + 49,
3083 .vsync_end = 480 + 49 + 2,
3084 .vtotal = 480 + 49 + 2 + 22,
3085};
3086
3087static const struct panel_desc powertip_ph800480t013_idf02 = {
3088 .modes = &powertip_ph800480t013_idf02_mode,
3089 .num_modes = 1,
3090 .size = {
3091 .width = 152,
3092 .height = 91,
3093 },
3094 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3095 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3096 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3098 .connector_type = DRM_MODE_CONNECTOR_DPI,
3099};
4ba3e563 3100
d2a6f0f5
JW		 3101static const struct drm_display_mode qd43003c0_40_mode = {
3102 .clock = 9000,
3103 .hdisplay = 480,
3104 .hsync_start = 480 + 8,
3105 .hsync_end = 480 + 8 + 4,
3106 .htotal = 480 + 8 + 4 + 39,
3107 .vdisplay = 272,
3108 .vsync_start = 272 + 4,
3109 .vsync_end = 272 + 4 + 10,
3110 .vtotal = 272 + 4 + 10 + 2,
d2a6f0f5
JW		 3111};
3112
3113static const struct panel_desc qd43003c0_40 = {
3114 .modes = &qd43003c0_40_mode,
3115 .num_modes = 1,
3116 .bpc = 8,
3117 .size = {
3118 .width = 95,
3119 .height = 53,
3120 },
3121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3122};
3123
23167fa9
JT		 3124static const struct display_timing rocktech_rk070er9427_timing = {
3125 .pixelclock = { 26400000, 33300000, 46800000 },
3126 .hactive = { 800, 800, 800 },
3127 .hfront_porch = { 16, 210, 354 },
3128 .hback_porch = { 46, 46, 46 },
3129 .hsync_len = { 1, 1, 1 },
3130 .vactive = { 480, 480, 480 },
3131 .vfront_porch = { 7, 22, 147 },
3132 .vback_porch = { 23, 23, 23 },
3133 .vsync_len = { 1, 1, 1 },
3134 .flags = DISPLAY_FLAGS_DE_HIGH,
3135};
3136
3137static const struct panel_desc rocktech_rk070er9427 = {
3138 .timings = &rocktech_rk070er9427_timing,
3139 .num_timings = 1,
3140 .bpc = 6,
3141 .size = {
3142 .width = 154,
3143 .height = 86,
3144 },
3145 .delay = {
3146 .prepare = 41,
3147 .enable = 50,
3148 .unprepare = 41,
3149 .disable = 50,
3150 },
3151 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3152};
3153
f305047b
JS		 3154static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3155 .clock = 71100,
3156 .hdisplay = 1280,
3157 .hsync_start = 1280 + 48,
3158 .hsync_end = 1280 + 48 + 32,
3159 .htotal = 1280 + 48 + 32 + 80,
3160 .vdisplay = 800,
3161 .vsync_start = 800 + 2,
3162 .vsync_end = 800 + 2 + 5,
3163 .vtotal = 800 + 2 + 5 + 16,
f305047b
JS		 3164};
3165
3166static const struct panel_desc rocktech_rk101ii01d_ct = {
3167 .modes = &rocktech_rk101ii01d_ct_mode,
3168 .num_modes = 1,
3169 .size = {
3170 .width = 217,
3171 .height = 136,
3172 },
3173 .delay = {
3174 .prepare = 50,
3175 .disable = 50,
3176 },
3177 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3178 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3179 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3180};
3181
0330eaf3
YY		 3182static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3183 .clock = 271560,
3184 .hdisplay = 2560,
3185 .hsync_start = 2560 + 48,
3186 .hsync_end = 2560 + 48 + 32,
3187 .htotal = 2560 + 48 + 32 + 80,
3188 .vdisplay = 1600,
3189 .vsync_start = 1600 + 2,
3190 .vsync_end = 1600 + 2 + 5,
3191 .vtotal = 1600 + 2 + 5 + 57,
0330eaf3
YY		 3192};
3193
3194static const struct panel_desc samsung_lsn122dl01_c01 = {
3195 .modes = &samsung_lsn122dl01_c01_mode,
3196 .num_modes = 1,
3197 .size = {
3198 .width = 263,
3199 .height = 164,
3200 },
3201};
3202
6d54e3d2
MD		 3203static const struct drm_display_mode samsung_ltn101nt05_mode = {
3204 .clock = 54030,
3205 .hdisplay = 1024,
3206 .hsync_start = 1024 + 24,
3207 .hsync_end = 1024 + 24 + 136,
3208 .htotal = 1024 + 24 + 136 + 160,
3209 .vdisplay = 600,
3210 .vsync_start = 600 + 3,
3211 .vsync_end = 600 + 3 + 6,
3212 .vtotal = 600 + 3 + 6 + 61,
6d54e3d2
MD		 3213};
3214
3215static const struct panel_desc samsung_ltn101nt05 = {
3216 .modes = &samsung_ltn101nt05_mode,
3217 .num_modes = 1,
0208d511 3218 .bpc = 6,
6d54e3d2 3219 .size = {
81598846
TR		 3220 .width = 223,
3221 .height = 125,
6d54e3d2 3222 },
85560829 3223 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 3224 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 3225 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6d54e3d2
MD		 3226};
3227
0c934306
SM		 3228static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3229 .clock = 76300,
3230 .hdisplay = 1366,
3231 .hsync_start = 1366 + 64,
3232 .hsync_end = 1366 + 64 + 48,
3233 .htotal = 1366 + 64 + 48 + 128,
3234 .vdisplay = 768,
3235 .vsync_start = 768 + 2,
3236 .vsync_end = 768 + 2 + 5,
3237 .vtotal = 768 + 2 + 5 + 17,
0c934306
SM		 3238};
3239
3240static const struct panel_desc samsung_ltn140at29_301 = {
3241 .modes = &samsung_ltn140at29_301_mode,
3242 .num_modes = 1,
3243 .bpc = 6,
3244 .size = {
3245 .width = 320,
3246 .height = 187,
3247 },
3248};
3249
44c58c52
MR		 3250static const struct display_timing satoz_sat050at40h12r2_timing = {
3251 .pixelclock = {33300000, 33300000, 50000000},
3252 .hactive = {800, 800, 800},
3253 .hfront_porch = {16, 210, 354},
3254 .hback_porch = {46, 46, 46},
3255 .hsync_len = {1, 1, 40},
3256 .vactive = {480, 480, 480},
3257 .vfront_porch = {7, 22, 147},
3258 .vback_porch = {23, 23, 23},
3259 .vsync_len = {1, 1, 20},
3260};
3261
3262static const struct panel_desc satoz_sat050at40h12r2 = {
3263 .timings = &satoz_sat050at40h12r2_timing,
3264 .num_timings = 1,
3265 .bpc = 8,
3266 .size = {
3267 .width = 108,
3268 .height = 65,
3269 },
34ca6b53 3270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
44c58c52
MR		 3271 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3272};
3273
cd5e1cbe
JH		 3274static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3275 .clock = 168480,
3276 .hdisplay = 1920,
3277 .hsync_start = 1920 + 48,
3278 .hsync_end = 1920 + 48 + 32,
3279 .htotal = 1920 + 48 + 32 + 80,
3280 .vdisplay = 1280,
3281 .vsync_start = 1280 + 3,
3282 .vsync_end = 1280 + 3 + 10,
3283 .vtotal = 1280 + 3 + 10 + 57,
cd5e1cbe
JH		 3284 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3285};
3286
3287static const struct panel_desc sharp_ld_d5116z01b = {
3288 .modes = &sharp_ld_d5116z01b_mode,
3289 .num_modes = 1,
3290 .bpc = 8,
3291 .size = {
3292 .width = 260,
3293 .height = 120,
3294 },
3295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3296 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3297};
3298
dda0e4bd
NS		 3299static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3300 .clock = 33260,
3301 .hdisplay = 800,
3302 .hsync_start = 800 + 64,
3303 .hsync_end = 800 + 64 + 128,
3304 .htotal = 800 + 64 + 128 + 64,
3305 .vdisplay = 480,
3306 .vsync_start = 480 + 8,
3307 .vsync_end = 480 + 8 + 2,
3308 .vtotal = 480 + 8 + 2 + 35,
dda0e4bd
NS		 3309 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3310};
3311
3312static const struct panel_desc sharp_lq070y3dg3b = {
3313 .modes = &sharp_lq070y3dg3b_mode,
3314 .num_modes = 1,
3315 .bpc = 8,
3316 .size = {
3317 .width = 152, /* 152.4mm */
3318 .height = 91, /* 91.4mm */
3319 },
3320 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3321 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
dda0e4bd
NS		 3322 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3323};
3324
03e3ec9a
VZ		 3325static const struct drm_display_mode sharp_lq035q7db03_mode = {
3326 .clock = 5500,
3327 .hdisplay = 240,
3328 .hsync_start = 240 + 16,
3329 .hsync_end = 240 + 16 + 7,
3330 .htotal = 240 + 16 + 7 + 5,
3331 .vdisplay = 320,
3332 .vsync_start = 320 + 9,
3333 .vsync_end = 320 + 9 + 1,
3334 .vtotal = 320 + 9 + 1 + 7,
03e3ec9a
VZ		 3335};
3336
3337static const struct panel_desc sharp_lq035q7db03 = {
3338 .modes = &sharp_lq035q7db03_mode,
3339 .num_modes = 1,
3340 .bpc = 6,
3341 .size = {
3342 .width = 54,
3343 .height = 72,
3344 },
3345 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3346};
3347
592aa02b
JC		 3348static const struct display_timing sharp_lq101k1ly04_timing = {
3349 .pixelclock = { 60000000, 65000000, 80000000 },
3350 .hactive = { 1280, 1280, 1280 },
3351 .hfront_porch = { 20, 20, 20 },
3352 .hback_porch = { 20, 20, 20 },
3353 .hsync_len = { 10, 10, 10 },
3354 .vactive = { 800, 800, 800 },
3355 .vfront_porch = { 4, 4, 4 },
3356 .vback_porch = { 4, 4, 4 },
3357 .vsync_len = { 4, 4, 4 },
3358 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3359};
3360
3361static const struct panel_desc sharp_lq101k1ly04 = {
3362 .timings = &sharp_lq101k1ly04_timing,
3363 .num_timings = 1,
3364 .bpc = 8,
3365 .size = {
3366 .width = 217,
3367 .height = 136,
3368 },
3369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 3370 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 3371};
3372
9f7bae2d
SP		 3373static const struct display_timing sharp_lq123p1jx31_timing = {
3374 .pixelclock = { 252750000, 252750000, 266604720 },
3375 .hactive = { 2400, 2400, 2400 },
3376 .hfront_porch = { 48, 48, 48 },
3377 .hback_porch = { 80, 80, 84 },
3378 .hsync_len = { 32, 32, 32 },
3379 .vactive = { 1600, 1600, 1600 },
3380 .vfront_porch = { 3, 3, 3 },
3381 .vback_porch = { 33, 33, 120 },
3382 .vsync_len = { 10, 10, 10 },
3383 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 3384};
3385
3386static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 3387 .timings = &sharp_lq123p1jx31_timing,
3388 .num_timings = 1,
5466a631 3389 .bpc = 8,
739c7de9
YY		 3390 .size = {
3391 .width = 259,
3392 .height = 173,
3393 },
a42f6e3f
YY		 3394 .delay = {
3395 .prepare = 110,
3396 .enable = 50,
3397 .unprepare = 550,
3398 },
739c7de9
YY		 3399};
3400
f1bd37f3
PC		 3401static const struct display_timing sharp_ls020b1dd01d_timing = {
3402 .pixelclock = { 2000000, 4200000, 5000000 },
3403 .hactive = { 240, 240, 240 },
3404 .hfront_porch = { 66, 66, 66 },
3405 .hback_porch = { 1, 1, 1 },
3406 .hsync_len = { 1, 1, 1 },
3407 .vactive = { 160, 160, 160 },
3408 .vfront_porch = { 52, 52, 52 },
3409 .vback_porch = { 6, 6, 6 },
3410 .vsync_len = { 10, 10, 10 },
3411 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
3412};
3413
3414static const struct panel_desc sharp_ls020b1dd01d = {
3415 .timings = &sharp_ls020b1dd01d_timing,
3416 .num_timings = 1,
3417 .bpc = 6,
3418 .size = {
3419 .width = 42,
3420 .height = 28,
3421 },
3422 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3423 .bus_flags = DRM_BUS_FLAG_DE_HIGH
f5436f77 3424 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
f1bd37f3
PC		 3425 | DRM_BUS_FLAG_SHARP_SIGNALS,
3426};
3427
9c6615bc
BB		 3428static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3429 .clock = 33300,
3430 .hdisplay = 800,
3431 .hsync_start = 800 + 1,
3432 .hsync_end = 800 + 1 + 64,
3433 .htotal = 800 + 1 + 64 + 64,
3434 .vdisplay = 480,
3435 .vsync_start = 480 + 1,
3436 .vsync_end = 480 + 1 + 23,
3437 .vtotal = 480 + 1 + 23 + 22,
9c6615bc
BB		 3438};
3439
3440static const struct panel_desc shelly_sca07010_bfn_lnn = {
3441 .modes = &shelly_sca07010_bfn_lnn_mode,
3442 .num_modes = 1,
3443 .size = {
3444 .width = 152,
3445 .height = 91,
3446 },
3447 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3448};
3449
105235e4
PR		 3450static const struct drm_display_mode starry_kr070pe2t_mode = {
3451 .clock = 33000,
3452 .hdisplay = 800,
3453 .hsync_start = 800 + 209,
3454 .hsync_end = 800 + 209 + 1,
3455 .htotal = 800 + 209 + 1 + 45,
3456 .vdisplay = 480,
3457 .vsync_start = 480 + 22,
3458 .vsync_end = 480 + 22 + 1,
3459 .vtotal = 480 + 22 + 1 + 22,
105235e4
PR		 3460};
3461
3462static const struct panel_desc starry_kr070pe2t = {
3463 .modes = &starry_kr070pe2t_mode,
3464 .num_modes = 1,
3465 .bpc = 8,
3466 .size = {
3467 .width = 152,
3468 .height = 86,
3469 },
3470 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3471 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
41fad307 3472 .connector_type = DRM_MODE_CONNECTOR_DPI,
105235e4
PR		 3473};
3474
9bb34c4c
DA		 3475static const struct drm_display_mode starry_kr122ea0sra_mode = {
3476 .clock = 147000,
3477 .hdisplay = 1920,
3478 .hsync_start = 1920 + 16,
3479 .hsync_end = 1920 + 16 + 16,
3480 .htotal = 1920 + 16 + 16 + 32,
3481 .vdisplay = 1200,
3482 .vsync_start = 1200 + 15,
3483 .vsync_end = 1200 + 15 + 2,
3484 .vtotal = 1200 + 15 + 2 + 18,
9bb34c4c
DA		 3485 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3486};
3487
3488static const struct panel_desc starry_kr122ea0sra = {
3489 .modes = &starry_kr122ea0sra_mode,
3490 .num_modes = 1,
3491 .size = {
3492 .width = 263,
3493 .height = 164,
3494 },
c46b924b
BN		 3495 .delay = {
3496 .prepare = 10 + 200,
3497 .enable = 50,
3498 .unprepare = 10 + 500,
3499 },
9bb34c4c
DA		 3500};
3501
42161531
JS		 3502static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3503 .clock = 30000,
3504 .hdisplay = 800,
3505 .hsync_start = 800 + 39,
3506 .hsync_end = 800 + 39 + 47,
3507 .htotal = 800 + 39 + 47 + 39,
3508 .vdisplay = 480,
3509 .vsync_start = 480 + 13,
3510 .vsync_end = 480 + 13 + 2,
3511 .vtotal = 480 + 13 + 2 + 29,
42161531
JS		 3512};
3513
3514static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3515 .modes = &tfc_s9700rtwv43tr_01b_mode,
3516 .num_modes = 1,
3517 .bpc = 8,
3518 .size = {
3519 .width = 155,
3520 .height = 90,
3521 },
3522 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3523 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
42161531
JS		 3524};
3525
adb973ef
GB		 3526static const struct display_timing tianma_tm070jdhg30_timing = {
3527 .pixelclock = { 62600000, 68200000, 78100000 },
3528 .hactive = { 1280, 1280, 1280 },
3529 .hfront_porch = { 15, 64, 159 },
3530 .hback_porch = { 5, 5, 5 },
3531 .hsync_len = { 1, 1, 256 },
3532 .vactive = { 800, 800, 800 },
3533 .vfront_porch = { 3, 40, 99 },
3534 .vback_porch = { 2, 2, 2 },
3535 .vsync_len = { 1, 1, 128 },
3536 .flags = DISPLAY_FLAGS_DE_HIGH,
3537};
3538
3539static const struct panel_desc tianma_tm070jdhg30 = {
3540 .timings = &tianma_tm070jdhg30_timing,
3541 .num_timings = 1,
3542 .bpc = 8,
3543 .size = {
3544 .width = 151,
3545 .height = 95,
3546 },
3547 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3548 .connector_type = DRM_MODE_CONNECTOR_LVDS,
adb973ef
GB		 3549};
3550
b3bfcdf8
MM		 3551static const struct panel_desc tianma_tm070jvhg33 = {
3552 .timings = &tianma_tm070jdhg30_timing,
3553 .num_timings = 1,
3554 .bpc = 8,
3555 .size = {
3556 .width = 150,
3557 .height = 94,
3558 },
3559 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3560 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3561};
3562
870a0b12
LM		 3563static const struct display_timing tianma_tm070rvhg71_timing = {
3564 .pixelclock = { 27700000, 29200000, 39600000 },
3565 .hactive = { 800, 800, 800 },
3566 .hfront_porch = { 12, 40, 212 },
3567 .hback_porch = { 88, 88, 88 },
3568 .hsync_len = { 1, 1, 40 },
3569 .vactive = { 480, 480, 480 },
3570 .vfront_porch = { 1, 13, 88 },
3571 .vback_porch = { 32, 32, 32 },
3572 .vsync_len = { 1, 1, 3 },
3573 .flags = DISPLAY_FLAGS_DE_HIGH,
3574};
3575
3576static const struct panel_desc tianma_tm070rvhg71 = {
3577 .timings = &tianma_tm070rvhg71_timing,
3578 .num_timings = 1,
3579 .bpc = 8,
3580 .size = {
3581 .width = 154,
3582 .height = 86,
3583 },
3584 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3585 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 3586};
3587
d8a0d6a3
LW		 3588static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3589 {
3590 .clock = 10000,
3591 .hdisplay = 320,
3592 .hsync_start = 320 + 50,
3593 .hsync_end = 320 + 50 + 6,
3594 .htotal = 320 + 50 + 6 + 38,
3595 .vdisplay = 240,
3596 .vsync_start = 240 + 3,
3597 .vsync_end = 240 + 3 + 1,
3598 .vtotal = 240 + 3 + 1 + 17,
d8a0d6a3
LW		 3599 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3600 },
3601};
3602
3603static const struct panel_desc ti_nspire_cx_lcd_panel = {
3604 .modes = ti_nspire_cx_lcd_mode,
3605 .num_modes = 1,
3606 .bpc = 8,
3607 .size = {
3608 .width = 65,
3609 .height = 49,
3610 },
3611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3612 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d8a0d6a3
LW		 3613};
3614
3615static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3616 {
3617 .clock = 10000,
3618 .hdisplay = 320,
3619 .hsync_start = 320 + 6,
3620 .hsync_end = 320 + 6 + 6,
3621 .htotal = 320 + 6 + 6 + 6,
3622 .vdisplay = 240,
3623 .vsync_start = 240 + 0,
3624 .vsync_end = 240 + 0 + 1,
3625 .vtotal = 240 + 0 + 1 + 0,
d8a0d6a3
LW		 3626 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3627 },
3628};
3629
3630static const struct panel_desc ti_nspire_classic_lcd_panel = {
3631 .modes = ti_nspire_classic_lcd_mode,
3632 .num_modes = 1,
3633 /* The grayscale panel has 8 bit for the color .. Y (black) */
3634 .bpc = 8,
3635 .size = {
3636 .width = 71,
3637 .height = 53,
3638 },
3639 /* This is the grayscale bus format */
3640 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
f5436f77 3641 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
d8a0d6a3
LW		 3642};
3643
06e733e4
LS		 3644static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3645 .clock = 79500,
3646 .hdisplay = 1280,
3647 .hsync_start = 1280 + 192,
3648 .hsync_end = 1280 + 192 + 128,
3649 .htotal = 1280 + 192 + 128 + 64,
3650 .vdisplay = 768,
3651 .vsync_start = 768 + 20,
3652 .vsync_end = 768 + 20 + 7,
3653 .vtotal = 768 + 20 + 7 + 3,
06e733e4
LS		 3654};
3655
3656static const struct panel_desc toshiba_lt089ac29000 = {
3657 .modes = &toshiba_lt089ac29000_mode,
3658 .num_modes = 1,
3659 .size = {
3660 .width = 194,
3661 .height = 116,
3662 },
9781bd1d 3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
c4715837 3664 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 3665 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 3666};
3667
227e4f40
BD		 3668static const struct drm_display_mode tpk_f07a_0102_mode = {
3669 .clock = 33260,
3670 .hdisplay = 800,
3671 .hsync_start = 800 + 40,
3672 .hsync_end = 800 + 40 + 128,
3673 .htotal = 800 + 40 + 128 + 88,
3674 .vdisplay = 480,
3675 .vsync_start = 480 + 10,
3676 .vsync_end = 480 + 10 + 2,
3677 .vtotal = 480 + 10 + 2 + 33,
227e4f40
BD		 3678};
3679
3680static const struct panel_desc tpk_f07a_0102 = {
3681 .modes = &tpk_f07a_0102_mode,
3682 .num_modes = 1,
3683 .size = {
3684 .width = 152,
3685 .height = 91,
3686 },
88bc4178 3687 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 3688};
3689
3690static const struct drm_display_mode tpk_f10a_0102_mode = {
3691 .clock = 45000,
3692 .hdisplay = 1024,
3693 .hsync_start = 1024 + 176,
3694 .hsync_end = 1024 + 176 + 5,
3695 .htotal = 1024 + 176 + 5 + 88,
3696 .vdisplay = 600,
3697 .vsync_start = 600 + 20,
3698 .vsync_end = 600 + 20 + 5,
3699 .vtotal = 600 + 20 + 5 + 25,
227e4f40
BD		 3700};
3701
3702static const struct panel_desc tpk_f10a_0102 = {
3703 .modes = &tpk_f10a_0102_mode,
3704 .num_modes = 1,
3705 .size = {
3706 .width = 223,
3707 .height = 125,
3708 },
3709};
3710
06a9dc65
MS		 3711static const struct display_timing urt_umsh_8596md_timing = {
3712 .pixelclock = { 33260000, 33260000, 33260000 },
3713 .hactive = { 800, 800, 800 },
3714 .hfront_porch = { 41, 41, 41 },
3715 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3716 .hsync_len = { 71, 128, 128 },
3717 .vactive = { 480, 480, 480 },
3718 .vfront_porch = { 10, 10, 10 },
3719 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3720 .vsync_len = { 2, 2, 2 },
3721 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3722 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3723};
3724
3725static const struct panel_desc urt_umsh_8596md_lvds = {
3726 .timings = &urt_umsh_8596md_timing,
3727 .num_timings = 1,
3728 .bpc = 6,
3729 .size = {
3730 .width = 152,
3731 .height = 91,
3732 },
3733 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 3734 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 3735};
3736
3737static const struct panel_desc urt_umsh_8596md_parallel = {
3738 .timings = &urt_umsh_8596md_timing,
3739 .num_timings = 1,
3740 .bpc = 6,
3741 .size = {
3742 .width = 152,
3743 .height = 91,
3744 },
3745 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3746};
3747
04206185
FE		 3748static const struct drm_display_mode vl050_8048nt_c01_mode = {
3749 .clock = 33333,
3750 .hdisplay = 800,
3751 .hsync_start = 800 + 210,
3752 .hsync_end = 800 + 210 + 20,
3753 .htotal = 800 + 210 + 20 + 46,
3754 .vdisplay = 480,
3755 .vsync_start = 480 + 22,
3756 .vsync_end = 480 + 22 + 10,
3757 .vtotal = 480 + 22 + 10 + 23,
04206185
FE		 3758 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3759};
3760
3761static const struct panel_desc vl050_8048nt_c01 = {
3762 .modes = &vl050_8048nt_c01_mode,
3763 .num_modes = 1,
3764 .bpc = 8,
3765 .size = {
3766 .width = 120,
3767 .height = 76,
3768 },
3769 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3770 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
04206185
FE		 3771};
3772
e4bac408
RG		 3773static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3774 .clock = 6410,
3775 .hdisplay = 320,
3776 .hsync_start = 320 + 20,
3777 .hsync_end = 320 + 20 + 30,
3778 .htotal = 320 + 20 + 30 + 38,
3779 .vdisplay = 240,
3780 .vsync_start = 240 + 4,
3781 .vsync_end = 240 + 4 + 3,
3782 .vtotal = 240 + 4 + 3 + 15,
e4bac408
RG		 3783 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3784};
3785
3786static const struct panel_desc winstar_wf35ltiacd = {
3787 .modes = &winstar_wf35ltiacd_mode,
3788 .num_modes = 1,
3789 .bpc = 8,
3790 .size = {
3791 .width = 70,
3792 .height = 53,
3793 },
3794 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3795};
3796
fcec4163
LW		 3797static const struct drm_display_mode arm_rtsm_mode[] = {
3798 {
3799 .clock = 65000,
3800 .hdisplay = 1024,
3801 .hsync_start = 1024 + 24,
3802 .hsync_end = 1024 + 24 + 136,
3803 .htotal = 1024 + 24 + 136 + 160,
3804 .vdisplay = 768,
3805 .vsync_start = 768 + 3,
3806 .vsync_end = 768 + 3 + 6,
3807 .vtotal = 768 + 3 + 6 + 29,
fcec4163
LW		 3808 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3809 },
3810};
3811
3812static const struct panel_desc arm_rtsm = {
3813 .modes = arm_rtsm_mode,
3814 .num_modes = 1,
3815 .bpc = 8,
3816 .size = {
3817 .width = 400,
3818 .height = 300,
3819 },
3820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3821};
3822
280921de
TR		 3823static const struct of_device_id platform_of_match[] = {
3824 {
966fea78
YF		 3825 .compatible = "ampire,am-480272h3tmqw-t01h",
3826 .data = &ampire_am_480272h3tmqw_t01h,
3827 }, {
1c550fa1
PZ		 3828 .compatible = "ampire,am800480r3tmqwa1h",
3829 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 3830 }, {
3831 .compatible = "arm,rtsm-display",
3832 .data = &arm_rtsm,
c479450f
SS		 3833 }, {
3834 .compatible = "armadeus,st0700-adapt",
3835 .data = &armadeus_st0700_adapt,
1c550fa1 3836 }, {
280921de
TR		 3837 .compatible = "auo,b101aw03",
3838 .data = &auo_b101aw03,
a531bc3d
HL		 3839 }, {
3840 .compatible = "auo,b101ean01",
3841 .data = &auo_b101ean01,
dac746e0
RC		 3842 }, {
3843 .compatible = "auo,b101xtn01",
3844 .data = &auo_b101xtn01,
da458286
RC		 3845 }, {
3846 .compatible = "auo,b116xa01",
3847 .data = &auo_b116xak01,
e35e305e
AK		 3848 }, {
3849 .compatible = "auo,b116xw03",
3850 .data = &auo_b116xw03,
3e51d609
AK		 3851 }, {
3852 .compatible = "auo,b133htn01",
3853 .data = &auo_b133htn01,
a333f7ad
SM		 3854 }, {
3855 .compatible = "auo,b133xtn01",
3856 .data = &auo_b133xtn01,
bccfaffb
LM		 3857 }, {
3858 .compatible = "auo,g070vvn01",
3859 .data = &auo_g070vvn01,
4fb86404
AG		 3860 }, {
3861 .compatible = "auo,g101evn010",
3862 .data = &auo_g101evn010,
4451c287
CF		 3863 }, {
3864 .compatible = "auo,g104sn02",
3865 .data = &auo_g104sn02,
03e909ac
SR		 3866 }, {
3867 .compatible = "auo,g121ean01",
3868 .data = &auo_g121ean01,
697035c6
LS		 3869 }, {
3870 .compatible = "auo,g133han01",
3871 .data = &auo_g133han01,
d9ccd1f2
SR		 3872 }, {
3873 .compatible = "auo,g156xtn01",
3874 .data = &auo_g156xtn01,
8c31f603
LS		 3875 }, {
3876 .compatible = "auo,g185han01",
3877 .data = &auo_g185han01,
2f7b832f
SR		 3878 }, {
3879 .compatible = "auo,g190ean01",
3880 .data = &auo_g190ean01,
70c0d5b7
LS		 3881 }, {
3882 .compatible = "auo,p320hvn03",
3883 .data = &auo_p320hvn03,
7ee933a1
HS		 3884 }, {
3885 .compatible = "auo,t215hvn01",
3886 .data = &auo_t215hvn01,
d47df633
PZ		 3887 }, {
3888 .compatible = "avic,tm070ddh03",
3889 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 3890 }, {
3891 .compatible = "bananapi,s070wv20-ct16",
3892 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 3893 }, {
3894 .compatible = "boe,hv070wsa-100",
3895 .data = &boe_hv070wsa
cac1a411
CW		 3896 }, {
3897 .compatible = "boe,nv101wxmn51",
3898 .data = &boe_nv101wxmn51,
b0c664cc
BA		 3899 }, {
3900 .compatible = "boe,nv133fhm-n61",
3901 .data = &boe_nv133fhm_n61,
cfe40d02
DA		 3902 }, {
3903 .compatible = "boe,nv133fhm-n62",
3904 .data = &boe_nv133fhm_n61,
a5119818
TS		 3905 }, {
3906 .compatible = "boe,nv140fhmn49",
3907 .data = &boe_nv140fhmn49,
e58edce6
GB		 3908 }, {
3909 .compatible = "cdtech,s043wq26h-ct7",
3910 .data = &cdtech_s043wq26h_ct7,
0e3b67f6
MK		 3911 }, {
3912 .compatible = "cdtech,s070pws19hp-fc21",
3913 .data = &cdtech_s070pws19hp_fc21,
3914 }, {
3915 .compatible = "cdtech,s070swv29hg-dc44",
3916 .data = &cdtech_s070swv29hg_dc44,
982f944e
GB		 3917 }, {
3918 .compatible = "cdtech,s070wv95-ct16",
3919 .data = &cdtech_s070wv95_ct16,
07c913c4
MV		 3920 }, {
3921 .compatible = "chefree,ch101olhlwh-002",
3922 .data = &chefree_ch101olhlwh_002,
2cb35c80
RL		 3923 }, {
3924 .compatible = "chunghwa,claa070wp03xg",
3925 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 3926 }, {
3927 .compatible = "chunghwa,claa101wa01a",
3928 .data = &chunghwa_claa101wa01a
280921de
TR		 3929 }, {
3930 .compatible = "chunghwa,claa101wb01",
3931 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 3932 }, {
3933 .compatible = "dataimage,scf0700c48ggu18",
3934 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 3935 }, {
3936 .compatible = "dlc,dlc0700yzg-1",
3937 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 3938 }, {
3939 .compatible = "dlc,dlc1010gig",
3940 .data = &dlc_dlc1010gig,
c2d24af6
AP		 3941 }, {
3942 .compatible = "edt,et035012dm6",
3943 .data = &edt_et035012dm6,
82d57a59
MCR		 3944 }, {
3945 .compatible = "edt,etm043080dh6gp",
3946 .data = &edt_etm043080dh6gp,
fd819bff
MV		 3947 }, {
3948 .compatible = "edt,etm0430g0dh6",
3949 .data = &edt_etm0430g0dh6,
26ab0065
SA		 3950 }, {
3951 .compatible = "edt,et057090dhu",
3952 .data = &edt_et057090dhu,
fff5de45
PZ		 3953 }, {
3954 .compatible = "edt,et070080dh6",
3955 .data = &edt_etm0700g0dh6,
3956 }, {
3957 .compatible = "edt,etm0700g0dh6",
3958 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 3959 }, {
3960 .compatible = "edt,etm0700g0bdh6",
3961 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 3962 }, {
3963 .compatible = "edt,etm0700g0edh6",
3964 .data = &edt_etm0700g0bdh6,
9158e3c3
MF		 3965 }, {
3966 .compatible = "evervision,vgg804821",
3967 .data = &evervision_vgg804821,
102932b0
BB		 3968 }, {
3969 .compatible = "foxlink,fl500wvr00-a0t",
3970 .data = &foxlink_fl500wvr00_a0t,
7b6bd843
PC		 3971 }, {
3972 .compatible = "frida,frd350h54004",
3973 .data = &frida_frd350h54004,
3be20710
JT		 3974 }, {
3975 .compatible = "friendlyarm,hd702e",
3976 .data = &friendlyarm_hd702e,
d435a2af
PZ		 3977 }, {
3978 .compatible = "giantplus,gpg482739qs5",
3979 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 3980 }, {
3981 .compatible = "giantplus,gpm940b0",
3982 .data = &giantplus_gpm940b0,
a853205e
PZ		 3983 }, {
3984 .compatible = "hannstar,hsd070pww1",
3985 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 3986 }, {
3987 .compatible = "hannstar,hsd100pxn1",
3988 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 3989 }, {
3990 .compatible = "hit,tx23d38vm0caa",
3991 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 3992 }, {
3993 .compatible = "innolux,at043tn24",
3994 .data = &innolux_at043tn24,
4fc24ab3
RB		 3995 }, {
3996 .compatible = "innolux,at070tn92",
3997 .data = &innolux_at070tn92,
1e29b840 3998 }, {
a5d2ade6
CF		 3999 .compatible = "innolux,g070y2-l01",
4000 .data = &innolux_g070y2_l01,
4001 }, {
4002 .compatible = "innolux,g101ice-l01",
1e29b840 4003 .data = &innolux_g101ice_l01
d731f661 4004 }, {
a5d2ade6 4005 .compatible = "innolux,g121i1-l01",
d731f661 4006 .data = &innolux_g121i1_l01
f8fa17ba
AB		 4007 }, {
4008 .compatible = "innolux,g121x1-l03",
4009 .data = &innolux_g121x1_l03,
0a2288c0
TR		 4010 }, {
4011 .compatible = "innolux,n116bge",
4012 .data = &innolux_n116bge,
ea44739d
AB		 4013 }, {
4014 .compatible = "innolux,n156bge-l21",
4015 .data = &innolux_n156bge_l21,
da50bd42 4016 }, {
8f054b6f
DA		 4017 .compatible = "innolux,p120zdg-bf1",
4018 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 4019 }, {
4020 .compatible = "innolux,zj070na-01p",
4021 .data = &innolux_zj070na_01p,
e1ca5184
BA		 4022 }, {
4023 .compatible = "ivo,m133nwf4-r0",
4024 .data = &ivo_m133nwf4_r0,
14bf60c4
LM		 4025 }, {
4026 .compatible = "koe,tx14d24vm1bpa",
4027 .data = &koe_tx14d24vm1bpa,
8a070524
LY		 4028 }, {
4029 .compatible = "koe,tx26d202vm0bwa",
4030 .data = &koe_tx26d202vm0bwa,
8cfe8341
JT		 4031 }, {
4032 .compatible = "koe,tx31d200vm0baa",
4033 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 4034 }, {
4035 .compatible = "kyo,tcg121xglp",
4036 .data = &kyo_tcg121xglp,
27abdd83
PK		 4037 }, {
4038 .compatible = "lemaker,bl035-rgb-002",
4039 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 4040 }, {
4041 .compatible = "lg,lb070wv8",
4042 .data = &lg_lb070wv8,
c5ece402
YY		 4043 }, {
4044 .compatible = "lg,lp079qx1-sp0v",
4045 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 4046 }, {
4047 .compatible = "lg,lp097qx1-spa1",
4048 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 4049 }, {
4050 .compatible = "lg,lp120up1",
4051 .data = &lg_lp120up1,
ec7c5653
TR		 4052 }, {
4053 .compatible = "lg,lp129qe",
4054 .data = &lg_lp129qe,
0d35408a
AF		 4055 }, {
4056 .compatible = "logicpd,type28",
4057 .data = &logicpd_type_28,
5728fe7f
MZ		 4058 }, {
4059 .compatible = "logictechno,lt161010-2nhc",
4060 .data = &logictechno_lt161010_2nh,
4061 }, {
4062 .compatible = "logictechno,lt161010-2nhr",
4063 .data = &logictechno_lt161010_2nh,
4064 }, {
4065 .compatible = "logictechno,lt170410-2whc",
4066 .data = &logictechno_lt170410_2whc,
65c766ca
LM		 4067 }, {
4068 .compatible = "mitsubishi,aa070mc01-ca1",
4069 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 4070 }, {
4071 .compatible = "nec,nl12880bc20-05",
4072 .data = &nec_nl12880bc20_05,
c6e87f91 4073 }, {
4074 .compatible = "nec,nl4827hc19-05b",
4075 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 4076 }, {
4077 .compatible = "netron-dy,e231732",
4078 .data = &netron_dy_e231732,
258145ea
VK		 4079 }, {
4080 .compatible = "neweast,wjfh116008a",
4081 .data = &neweast_wjfh116008a,
3b39ad7a
TV		 4082 }, {
4083 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4084 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 4085 }, {
4086 .compatible = "nlt,nl192108ac18-02d",
4087 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 4088 }, {
4089 .compatible = "nvd,9128",
4090 .data = &nvd_9128,
a99fb626
GB		 4091 }, {
4092 .compatible = "okaya,rs800480t-7x0gp",
4093 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 4094 }, {
4095 .compatible = "olimex,lcd-olinuxino-43-ts",
4096 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 4097 }, {
4098 .compatible = "ontat,yx700wv03",
4099 .data = &ontat_yx700wv03,
9c31dcb6
NS		 4100 }, {
4101 .compatible = "ortustech,com37h3m05dtc",
4102 .data = &ortustech_com37h3m,
4103 }, {
4104 .compatible = "ortustech,com37h3m99dtc",
4105 .data = &ortustech_com37h3m,
725c9d40
PZ		 4106 }, {
4107 .compatible = "ortustech,com43h4m85ulc",
4108 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 4109 }, {
4110 .compatible = "osddisplays,osd070t1718-19ts",
4111 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 4112 }, {
4113 .compatible = "pda,91-00156-a0",
4114 .data = &pda_91_00156_a0,
d69de69f
MV		 4115 }, {
4116 .compatible = "powertip,ph800480t013-idf02",
4117 .data = &powertip_ph800480t013_idf02,
d2a6f0f5
JW		 4118 }, {
4119 .compatible = "qiaodian,qd43003c0-40",
4120 .data = &qd43003c0_40,
23167fa9
JT		 4121 }, {
4122 .compatible = "rocktech,rk070er9427",
4123 .data = &rocktech_rk070er9427,
f305047b
JS		 4124 }, {
4125 .compatible = "rocktech,rk101ii01d-ct",
4126 .data = &rocktech_rk101ii01d_ct,
0330eaf3
YY		 4127 }, {
4128 .compatible = "samsung,lsn122dl01-c01",
4129 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 4130 }, {
4131 .compatible = "samsung,ltn101nt05",
4132 .data = &samsung_ltn101nt05,
0c934306
SM		 4133 }, {
4134 .compatible = "samsung,ltn140at29-301",
4135 .data = &samsung_ltn140at29_301,
44c58c52
MR		 4136 }, {
4137 .compatible = "satoz,sat050at40h12r2",
4138 .data = &satoz_sat050at40h12r2,
cd5e1cbe
JH		 4139 }, {
4140 .compatible = "sharp,ld-d5116z01b",
4141 .data = &sharp_ld_d5116z01b,
03e3ec9a
VZ		 4142 }, {
4143 .compatible = "sharp,lq035q7db03",
4144 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 4145 }, {
4146 .compatible = "sharp,lq070y3dg3b",
4147 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 4148 }, {
4149 .compatible = "sharp,lq101k1ly04",
4150 .data = &sharp_lq101k1ly04,
739c7de9
YY		 4151 }, {
4152 .compatible = "sharp,lq123p1jx31",
4153 .data = &sharp_lq123p1jx31,
f1bd37f3
PC		 4154 }, {
4155 .compatible = "sharp,ls020b1dd01d",
4156 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 4157 }, {
4158 .compatible = "shelly,sca07010-bfn-lnn",
4159 .data = &shelly_sca07010_bfn_lnn,
105235e4
PR		 4160 }, {
4161 .compatible = "starry,kr070pe2t",
4162 .data = &starry_kr070pe2t,
9bb34c4c
DA		 4163 }, {
4164 .compatible = "starry,kr122ea0sra",
4165 .data = &starry_kr122ea0sra,
42161531
JS		 4166 }, {
4167 .compatible = "tfc,s9700rtwv43tr-01b",
4168 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 4169 }, {
4170 .compatible = "tianma,tm070jdhg30",
4171 .data = &tianma_tm070jdhg30,
b3bfcdf8
MM		 4172 }, {
4173 .compatible = "tianma,tm070jvhg33",
4174 .data = &tianma_tm070jvhg33,
870a0b12
LM		 4175 }, {
4176 .compatible = "tianma,tm070rvhg71",
4177 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 4178 }, {
4179 .compatible = "ti,nspire-cx-lcd-panel",
4180 .data = &ti_nspire_cx_lcd_panel,
4181 }, {
4182 .compatible = "ti,nspire-classic-lcd-panel",
4183 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 4184 }, {
4185 .compatible = "toshiba,lt089ac29000",
4186 .data = &toshiba_lt089ac29000,
227e4f40
BD		 4187 }, {
4188 .compatible = "tpk,f07a-0102",
4189 .data = &tpk_f07a_0102,
4190 }, {
4191 .compatible = "tpk,f10a-0102",
4192 .data = &tpk_f10a_0102,
06a9dc65
MS		 4193 }, {
4194 .compatible = "urt,umsh-8596md-t",
4195 .data = &urt_umsh_8596md_parallel,
4196 }, {
4197 .compatible = "urt,umsh-8596md-1t",
4198 .data = &urt_umsh_8596md_parallel,
4199 }, {
4200 .compatible = "urt,umsh-8596md-7t",
4201 .data = &urt_umsh_8596md_parallel,
4202 }, {
4203 .compatible = "urt,umsh-8596md-11t",
4204 .data = &urt_umsh_8596md_lvds,
4205 }, {
4206 .compatible = "urt,umsh-8596md-19t",
4207 .data = &urt_umsh_8596md_lvds,
4208 }, {
4209 .compatible = "urt,umsh-8596md-20t",
4210 .data = &urt_umsh_8596md_parallel,
04206185
FE		 4211 }, {
4212 .compatible = "vxt,vl050-8048nt-c01",
4213 .data = &vl050_8048nt_c01,
e4bac408
RG		 4214 }, {
4215 .compatible = "winstar,wf35ltiacd",
4216 .data = &winstar_wf35ltiacd,
4a1d0dbc
SR		 4217 }, {
4218 /* Must be the last entry */
4219 .compatible = "panel-dpi",
4220 .data = &panel_dpi,
280921de
TR		 4221 }, {
4222 /* sentinel */
4223 }
4224};
4225MODULE_DEVICE_TABLE(of, platform_of_match);
4226
4227static int panel_simple_platform_probe(struct platform_device *pdev)
4228{
4229 const struct of_device_id *id;
4230
4231 id = of_match_node(platform_of_match, pdev->dev.of_node);
4232 if (!id)
4233 return -ENODEV;
4234
4235 return panel_simple_probe(&pdev->dev, id->data);
4236}
4237
4238static int panel_simple_platform_remove(struct platform_device *pdev)
4239{
4240 return panel_simple_remove(&pdev->dev);
4241}
4242
d02fd93e
TR		 4243static void panel_simple_platform_shutdown(struct platform_device *pdev)
4244{
4245 panel_simple_shutdown(&pdev->dev);
4246}
4247
280921de
TR		 4248static struct platform_driver panel_simple_platform_driver = {
4249 .driver = {
4250 .name = "panel-simple",
280921de
TR		 4251 .of_match_table = platform_of_match,
4252 },
4253 .probe = panel_simple_platform_probe,
4254 .remove = panel_simple_platform_remove,
d02fd93e 4255 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 4256};
4257
210fcd9d
TR		 4258struct panel_desc_dsi {
4259 struct panel_desc desc;
4260
462658b8 4261 unsigned long flags;
210fcd9d
TR		 4262 enum mipi_dsi_pixel_format format;
4263 unsigned int lanes;
4264};
4265
d718d79e
TR		 4266static const struct drm_display_mode auo_b080uan01_mode = {
4267 .clock = 154500,
4268 .hdisplay = 1200,
4269 .hsync_start = 1200 + 62,
4270 .hsync_end = 1200 + 62 + 4,
4271 .htotal = 1200 + 62 + 4 + 62,
4272 .vdisplay = 1920,
4273 .vsync_start = 1920 + 9,
4274 .vsync_end = 1920 + 9 + 2,
4275 .vtotal = 1920 + 9 + 2 + 8,
d718d79e
TR		 4276};
4277
4278static const struct panel_desc_dsi auo_b080uan01 = {
4279 .desc = {
4280 .modes = &auo_b080uan01_mode,
4281 .num_modes = 1,
4282 .bpc = 8,
4283 .size = {
4284 .width = 108,
4285 .height = 272,
4286 },
cb62cdec 4287 .connector_type = DRM_MODE_CONNECTOR_DSI,
d718d79e
TR		 4288 },
4289 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4290 .format = MIPI_DSI_FMT_RGB888,
4291 .lanes = 4,
4292};
4293
c8521969
CZ		 4294static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4295 .clock = 160000,
4296 .hdisplay = 1200,
4297 .hsync_start = 1200 + 120,
4298 .hsync_end = 1200 + 120 + 20,
4299 .htotal = 1200 + 120 + 20 + 21,
4300 .vdisplay = 1920,
4301 .vsync_start = 1920 + 21,
4302 .vsync_end = 1920 + 21 + 3,
4303 .vtotal = 1920 + 21 + 3 + 18,
c8521969
CZ		 4304 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4305};
4306
4307static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4308 .desc = {
4309 .modes = &boe_tv080wum_nl0_mode,
4310 .num_modes = 1,
4311 .size = {
4312 .width = 107,
4313 .height = 172,
4314 },
cb62cdec 4315 .connector_type = DRM_MODE_CONNECTOR_DSI,
c8521969
CZ		 4316 },
4317 .flags = MIPI_DSI_MODE_VIDEO |
4318 MIPI_DSI_MODE_VIDEO_BURST |
4319 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4320 .format = MIPI_DSI_FMT_RGB888,
4321 .lanes = 4,
4322};
4323
712ac1ba
AC		 4324static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4325 .clock = 71000,
4326 .hdisplay = 800,
4327 .hsync_start = 800 + 32,
4328 .hsync_end = 800 + 32 + 1,
4329 .htotal = 800 + 32 + 1 + 57,
4330 .vdisplay = 1280,
4331 .vsync_start = 1280 + 28,
4332 .vsync_end = 1280 + 28 + 1,
4333 .vtotal = 1280 + 28 + 1 + 14,
712ac1ba
AC		 4334};
4335
4336static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4337 .desc = {
4338 .modes = &lg_ld070wx3_sl01_mode,
4339 .num_modes = 1,
d7a839cd 4340 .bpc = 8,
712ac1ba
AC		 4341 .size = {
4342 .width = 94,
4343 .height = 151,
4344 },
cb62cdec 4345 .connector_type = DRM_MODE_CONNECTOR_DSI,
712ac1ba 4346 },
5e4cc278 4347 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 4348 .format = MIPI_DSI_FMT_RGB888,
4349 .lanes = 4,
4350};
4351
499ce85a
AC		 4352static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4353 .clock = 67000,
4354 .hdisplay = 720,
4355 .hsync_start = 720 + 12,
4356 .hsync_end = 720 + 12 + 4,
4357 .htotal = 720 + 12 + 4 + 112,
4358 .vdisplay = 1280,
4359 .vsync_start = 1280 + 8,
4360 .vsync_end = 1280 + 8 + 4,
4361 .vtotal = 1280 + 8 + 4 + 12,
499ce85a
AC		 4362};
4363
4364static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4365 .desc = {
4366 .modes = &lg_lh500wx1_sd03_mode,
4367 .num_modes = 1,
d7a839cd 4368 .bpc = 8,
499ce85a
AC		 4369 .size = {
4370 .width = 62,
4371 .height = 110,
4372 },
cb62cdec 4373 .connector_type = DRM_MODE_CONNECTOR_DSI,
499ce85a
AC		 4374 },
4375 .flags = MIPI_DSI_MODE_VIDEO,
4376 .format = MIPI_DSI_FMT_RGB888,
4377 .lanes = 4,
4378};
4379
280921de
TR		 4380static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4381 .clock = 157200,
4382 .hdisplay = 1920,
4383 .hsync_start = 1920 + 154,
4384 .hsync_end = 1920 + 154 + 16,
4385 .htotal = 1920 + 154 + 16 + 32,
4386 .vdisplay = 1200,
4387 .vsync_start = 1200 + 17,
4388 .vsync_end = 1200 + 17 + 2,
4389 .vtotal = 1200 + 17 + 2 + 16,
280921de
TR		 4390};
4391
210fcd9d
TR		 4392static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4393 .desc = {
4394 .modes = &panasonic_vvx10f004b00_mode,
4395 .num_modes = 1,
d7a839cd 4396 .bpc = 8,
210fcd9d
TR		 4397 .size = {
4398 .width = 217,
4399 .height = 136,
4400 },
cb62cdec 4401 .connector_type = DRM_MODE_CONNECTOR_DSI,
280921de 4402 },
5e4cc278
AC		 4403 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4404 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 4405 .format = MIPI_DSI_FMT_RGB888,
4406 .lanes = 4,
4407};
4408
debcd8f9
JM		 4409static const struct drm_display_mode lg_acx467akm_7_mode = {
4410 .clock = 150000,
4411 .hdisplay = 1080,
4412 .hsync_start = 1080 + 2,
4413 .hsync_end = 1080 + 2 + 2,
4414 .htotal = 1080 + 2 + 2 + 2,
4415 .vdisplay = 1920,
4416 .vsync_start = 1920 + 2,
4417 .vsync_end = 1920 + 2 + 2,
4418 .vtotal = 1920 + 2 + 2 + 2,
debcd8f9
JM		 4419};
4420
4421static const struct panel_desc_dsi lg_acx467akm_7 = {
4422 .desc = {
4423 .modes = &lg_acx467akm_7_mode,
4424 .num_modes = 1,
4425 .bpc = 8,
4426 .size = {
4427 .width = 62,
4428 .height = 110,
4429 },
cb62cdec 4430 .connector_type = DRM_MODE_CONNECTOR_DSI,
debcd8f9
JM		 4431 },
4432 .flags = 0,
4433 .format = MIPI_DSI_FMT_RGB888,
4434 .lanes = 4,
4435};
4436
62967232
PU		 4437static const struct drm_display_mode osd101t2045_53ts_mode = {
4438 .clock = 154500,
4439 .hdisplay = 1920,
4440 .hsync_start = 1920 + 112,
4441 .hsync_end = 1920 + 112 + 16,
4442 .htotal = 1920 + 112 + 16 + 32,
4443 .vdisplay = 1200,
4444 .vsync_start = 1200 + 16,
4445 .vsync_end = 1200 + 16 + 2,
4446 .vtotal = 1200 + 16 + 2 + 16,
62967232
PU		 4447 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4448};
4449
4450static const struct panel_desc_dsi osd101t2045_53ts = {
4451 .desc = {
4452 .modes = &osd101t2045_53ts_mode,
4453 .num_modes = 1,
4454 .bpc = 8,
4455 .size = {
4456 .width = 217,
4457 .height = 136,
4458 },
cb62cdec 4459 .connector_type = DRM_MODE_CONNECTOR_DSI,
62967232
PU		 4460 },
4461 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4462 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4463 MIPI_DSI_MODE_EOT_PACKET,
4464 .format = MIPI_DSI_FMT_RGB888,
4465 .lanes = 4,
4466};
4467
210fcd9d
TR		 4468static const struct of_device_id dsi_of_match[] = {
4469 {
d718d79e
TR		 4470 .compatible = "auo,b080uan01",
4471 .data = &auo_b080uan01
c8521969
CZ		 4472 }, {
4473 .compatible = "boe,tv080wum-nl0",
4474 .data = &boe_tv080wum_nl0
d718d79e 4475 }, {
712ac1ba
AC		 4476 .compatible = "lg,ld070wx3-sl01",
4477 .data = &lg_ld070wx3_sl01
4478 }, {
499ce85a
AC		 4479 .compatible = "lg,lh500wx1-sd03",
4480 .data = &lg_lh500wx1_sd03
4481 }, {
210fcd9d
TR		 4482 .compatible = "panasonic,vvx10f004b00",
4483 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 4484 }, {
4485 .compatible = "lg,acx467akm-7",
4486 .data = &lg_acx467akm_7
62967232
PU		 4487 }, {
4488 .compatible = "osddisplays,osd101t2045-53ts",
4489 .data = &osd101t2045_53ts
210fcd9d
TR		 4490 }, {
4491 /* sentinel */
4492 }
4493};
4494MODULE_DEVICE_TABLE(of, dsi_of_match);
4495
4496static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4497{
4498 const struct panel_desc_dsi *desc;
4499 const struct of_device_id *id;
4500 int err;
4501
4502 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4503 if (!id)
4504 return -ENODEV;
4505
4506 desc = id->data;
4507
4508 err = panel_simple_probe(&dsi->dev, &desc->desc);
4509 if (err < 0)
4510 return err;
4511
462658b8 4512 dsi->mode_flags = desc->flags;
210fcd9d
TR		 4513 dsi->format = desc->format;
4514 dsi->lanes = desc->lanes;
4515
7ad9db66
PU		 4516 err = mipi_dsi_attach(dsi);
4517 if (err) {
4518 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4519
4520 drm_panel_remove(&panel->base);
4521 }
4522
4523 return err;
210fcd9d
TR		 4524}
4525
4526static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4527{
4528 int err;
4529
4530 err = mipi_dsi_detach(dsi);
4531 if (err < 0)
4532 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4533
4534 return panel_simple_remove(&dsi->dev);
4535}
4536
d02fd93e
TR		 4537static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4538{
4539 panel_simple_shutdown(&dsi->dev);
4540}
4541
210fcd9d
TR		 4542static struct mipi_dsi_driver panel_simple_dsi_driver = {
4543 .driver = {
4544 .name = "panel-simple-dsi",
210fcd9d
TR		 4545 .of_match_table = dsi_of_match,
4546 },
4547 .probe = panel_simple_dsi_probe,
4548 .remove = panel_simple_dsi_remove,
d02fd93e 4549 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 4550};
4551
4552static int __init panel_simple_init(void)
4553{
210fcd9d
TR		 4554 int err;
4555
4556 err = platform_driver_register(&panel_simple_platform_driver);
4557 if (err < 0)
4558 return err;
4559
4560 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4561 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4562 if (err < 0)
4563 return err;
4564 }
4565
4566 return 0;
280921de
TR		 4567}
4568module_init(panel_simple_init);
4569
4570static void __exit panel_simple_exit(void)
4571{
210fcd9d
TR		 4572 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4573 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4574
280921de
TR		 4575 platform_driver_unregister(&panel_simple_platform_driver);
4576}
4577module_exit(panel_simple_exit);
4578
4579MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4580MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4581MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)