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drm/panel: novatek-nt39016: drop use of legacy drm_bus_flags
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
48834e60 26#include <linux/iopoll.h>
280921de 27#include <linux/module.h>
280921de
TR		 28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/regulator/consumer.h>
31
cb23eae3 32#include <video/display_timing.h>
b8a2948f 33#include <video/of_display_timing.h>
cb23eae3
SR		 34#include <video/videomode.h>
35
280921de 36#include <drm/drm_crtc.h>
cb23eae3 37#include <drm/drm_device.h>
210fcd9d 38#include <drm/drm_mipi_dsi.h>
280921de
TR		 39#include <drm/drm_panel.h>
40
e362cc6a
DA		 41/**
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
56 */
280921de
TR		 57struct panel_desc {
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
a5d3e625
PZ		 60 const struct display_timing *timings;
61 unsigned int num_timings;
280921de 62
0208d511
SM		 63 unsigned int bpc;
64
85533e3b
UÖ		 65 /**
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
68 */
280921de
TR		 69 struct {
70 unsigned int width;
71 unsigned int height;
72 } size;
f673c37e
AK		 73
74 /**
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
2ed3e951
DA		 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
f673c37e
AK		 79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
81 * video data
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
86 */
87 struct {
88 unsigned int prepare;
2ed3e951 89 unsigned int hpd_absent_delay;
f673c37e
AK		 90 unsigned int enable;
91 unsigned int disable;
92 unsigned int unprepare;
93 } delay;
795f7ab3
BB		 94
95 u32 bus_format;
f0aa0838 96 u32 bus_flags;
9a2654c0 97 int connector_type;
280921de
TR		 98};
99
280921de
TR		 100struct panel_simple {
101 struct drm_panel base;
613a633e 102 bool prepared;
280921de 103 bool enabled;
2ed3e951 104 bool no_hpd;
280921de
TR		 105
106 const struct panel_desc *desc;
107
280921de
TR		 108 struct regulator *supply;
109 struct i2c_adapter *ddc;
110
cfdf0549 111 struct gpio_desc *enable_gpio;
48834e60 112 struct gpio_desc *hpd_gpio;
b8a2948f
SP		 113
114 struct drm_display_mode override_mode;
280921de
TR		 115};
116
117static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
118{
119 return container_of(panel, struct panel_simple, base);
120}
121
0ce8ddd8
SR		 122static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
123 struct drm_connector *connector)
280921de 124{
280921de
TR		 125 struct drm_display_mode *mode;
126 unsigned int i, num = 0;
127
a5d3e625
PZ		 128 for (i = 0; i < panel->desc->num_timings; i++) {
129 const struct display_timing *dt = &panel->desc->timings[i];
130 struct videomode vm;
131
132 videomode_from_timing(dt, &vm);
aa6c4364 133 mode = drm_mode_create(connector->dev);
a5d3e625 134 if (!mode) {
aa6c4364 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 136 dt->hactive.typ, dt->vactive.typ);
137 continue;
138 }
139
140 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 141
142 mode->type |= DRM_MODE_TYPE_DRIVER;
143
230c5b44 144 if (panel->desc->num_timings == 1)
cda55372
BB		 145 mode->type |= DRM_MODE_TYPE_PREFERRED;
146
a5d3e625
PZ		 147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
b8a2948f
SP		 151 return num;
152}
153
0ce8ddd8
SR		 154static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
155 struct drm_connector *connector)
b8a2948f 156{
b8a2948f
SP		 157 struct drm_display_mode *mode;
158 unsigned int i, num = 0;
159
280921de
TR		 160 for (i = 0; i < panel->desc->num_modes; i++) {
161 const struct drm_display_mode *m = &panel->desc->modes[i];
162
aa6c4364 163 mode = drm_mode_duplicate(connector->dev, m);
280921de 164 if (!mode) {
aa6c4364 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
0425662f
VS		 166 m->hdisplay, m->vdisplay,
167 drm_mode_vrefresh(m));
280921de
TR		 168 continue;
169 }
170
cda55372
BB		 171 mode->type |= DRM_MODE_TYPE_DRIVER;
172
173 if (panel->desc->num_modes == 1)
174 mode->type |= DRM_MODE_TYPE_PREFERRED;
175
280921de
TR		 176 drm_mode_set_name(mode);
177
178 drm_mode_probed_add(connector, mode);
179 num++;
180 }
181
b8a2948f
SP		 182 return num;
183}
184
0ce8ddd8
SR		 185static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
186 struct drm_connector *connector)
b8a2948f 187{
b8a2948f
SP		 188 struct drm_display_mode *mode;
189 bool has_override = panel->override_mode.type;
190 unsigned int num = 0;
191
192 if (!panel->desc)
193 return 0;
194
195 if (has_override) {
aa6c4364
SR		 196 mode = drm_mode_duplicate(connector->dev,
197 &panel->override_mode);
b8a2948f
SP		 198 if (mode) {
199 drm_mode_probed_add(connector, mode);
200 num = 1;
201 } else {
aa6c4364 202 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 203 }
204 }
205
206 /* Only add timings if override was not there or failed to validate */
207 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 208 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 209
210 /*
211 * Only add fixed modes if timings/override added no mode.
212 *
213 * We should only ever have either the display timings specified
214 * or a fixed mode. Anything else is rather bogus.
215 */
216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 if (num == 0)
0ce8ddd8 218 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 219
0208d511 220 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 221 connector->display_info.width_mm = panel->desc->size.width;
222 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 223 if (panel->desc->bus_format)
224 drm_display_info_set_bus_formats(&connector->display_info,
225 &panel->desc->bus_format, 1);
f0aa0838 226 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 227
228 return num;
229}
230
231static int panel_simple_disable(struct drm_panel *panel)
232{
233 struct panel_simple *p = to_panel_simple(panel);
234
235 if (!p->enabled)
236 return 0;
237
f673c37e
AK		 238 if (p->desc->delay.disable)
239 msleep(p->desc->delay.disable);
240
280921de
TR		 241 p->enabled = false;
242
243 return 0;
244}
245
c0e1d170
AK		 246static int panel_simple_unprepare(struct drm_panel *panel)
247{
613a633e
AK		 248 struct panel_simple *p = to_panel_simple(panel);
249
250 if (!p->prepared)
251 return 0;
252
756b918d 253 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 254
255 regulator_disable(p->supply);
256
f673c37e
AK		 257 if (p->desc->delay.unprepare)
258 msleep(p->desc->delay.unprepare);
259
613a633e 260 p->prepared = false;
c0e1d170 261
c0e1d170
AK		 262 return 0;
263}
264
48834e60
DA		 265static int panel_simple_get_hpd_gpio(struct device *dev,
266 struct panel_simple *p, bool from_probe)
267{
268 int err;
269
270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
271 if (IS_ERR(p->hpd_gpio)) {
272 err = PTR_ERR(p->hpd_gpio);
273
274 /*
275 * If we're called from probe we won't consider '-EPROBE_DEFER'
276 * to be an error--we'll leave the error code in "hpd_gpio".
277 * When we try to use it we'll try again. This allows for
278 * circular dependencies where the component providing the
279 * hpd gpio needs the panel to init before probing.
280 */
281 if (err != -EPROBE_DEFER || !from_probe) {
282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
283 return err;
284 }
285 }
286
287 return 0;
288}
289
613a633e 290static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 291{
292 struct panel_simple *p = to_panel_simple(panel);
2ed3e951 293 unsigned int delay;
280921de 294 int err;
48834e60 295 int hpd_asserted;
280921de 296
613a633e 297 if (p->prepared)
280921de
TR		 298 return 0;
299
300 err = regulator_enable(p->supply);
301 if (err < 0) {
302 dev_err(panel->dev, "failed to enable supply: %d\n", err);
303 return err;
304 }
305
756b918d 306 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 307
2ed3e951
DA		 308 delay = p->desc->delay.prepare;
309 if (p->no_hpd)
310 delay += p->desc->delay.hpd_absent_delay;
311 if (delay)
312 msleep(delay);
f673c37e 313
48834e60
DA		 314 if (p->hpd_gpio) {
315 if (IS_ERR(p->hpd_gpio)) {
316 err = panel_simple_get_hpd_gpio(panel->dev, p, false);
317 if (err)
318 return err;
319 }
320
321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
322 hpd_asserted, hpd_asserted,
323 1000, 2000000);
324 if (hpd_asserted < 0)
325 err = hpd_asserted;
326
327 if (err) {
328 dev_err(panel->dev,
329 "error waiting for hpd GPIO: %d\n", err);
330 return err;
331 }
332 }
333
613a633e
AK		 334 p->prepared = true;
335
336 return 0;
337}
338
339static int panel_simple_enable(struct drm_panel *panel)
340{
341 struct panel_simple *p = to_panel_simple(panel);
342
343 if (p->enabled)
344 return 0;
345
f673c37e
AK		 346 if (p->desc->delay.enable)
347 msleep(p->desc->delay.enable);
348
280921de
TR		 349 p->enabled = true;
350
351 return 0;
352}
353
0ce8ddd8
SR		 354static int panel_simple_get_modes(struct drm_panel *panel,
355 struct drm_connector *connector)
280921de
TR		 356{
357 struct panel_simple *p = to_panel_simple(panel);
358 int num = 0;
359
360 /* probe EDID if a DDC bus is available */
361 if (p->ddc) {
0ce8ddd8
SR		 362 struct edid *edid = drm_get_edid(connector, p->ddc);
363
364 drm_connector_update_edid_property(connector, edid);
280921de 365 if (edid) {
0ce8ddd8 366 num += drm_add_edid_modes(connector, edid);
280921de
TR		 367 kfree(edid);
368 }
369 }
370
371 /* add hard-coded panel modes */
0ce8ddd8 372 num += panel_simple_get_non_edid_modes(p, connector);
280921de
TR		 373
374 return num;
375}
376
a5d3e625
PZ		 377static int panel_simple_get_timings(struct drm_panel *panel,
378 unsigned int num_timings,
379 struct display_timing *timings)
380{
381 struct panel_simple *p = to_panel_simple(panel);
382 unsigned int i;
383
384 if (p->desc->num_timings < num_timings)
385 num_timings = p->desc->num_timings;
386
387 if (timings)
388 for (i = 0; i < num_timings; i++)
389 timings[i] = p->desc->timings[i];
390
391 return p->desc->num_timings;
392}
393
280921de
TR		 394static const struct drm_panel_funcs panel_simple_funcs = {
395 .disable = panel_simple_disable,
c0e1d170
AK		 396 .unprepare = panel_simple_unprepare,
397 .prepare = panel_simple_prepare,
280921de
TR		 398 .enable = panel_simple_enable,
399 .get_modes = panel_simple_get_modes,
a5d3e625 400 .get_timings = panel_simple_get_timings,
280921de
TR		 401};
402
4a1d0dbc
SR		 403static struct panel_desc panel_dpi;
404
405static int panel_dpi_probe(struct device *dev,
406 struct panel_simple *panel)
407{
408 struct display_timing *timing;
409 const struct device_node *np;
410 struct panel_desc *desc;
411 unsigned int bus_flags;
412 struct videomode vm;
4a1d0dbc
SR		 413 int ret;
414
415 np = dev->of_node;
416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
417 if (!desc)
418 return -ENOMEM;
419
420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
421 if (!timing)
422 return -ENOMEM;
423
424 ret = of_get_display_timing(np, "panel-timing", timing);
425 if (ret < 0) {
426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
427 np);
428 return ret;
429 }
430
431 desc->timings = timing;
432 desc->num_timings = 1;
433
434 of_property_read_u32(np, "width-mm", &desc->size.width);
435 of_property_read_u32(np, "height-mm", &desc->size.height);
436
4a1d0dbc
SR		 437 /* Extract bus_flags from display_timing */
438 bus_flags = 0;
439 vm.flags = timing->flags;
440 drm_bus_flags_from_videomode(&vm, &bus_flags);
441 desc->bus_flags = bus_flags;
442
443 /* We do not know the connector for the DT node, so guess it */
444 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
445
446 panel->desc = desc;
447
448 return 0;
449}
450
b8a2948f
SP		 451#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
452 (to_check->field.typ >= bounds->field.min && \
453 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 454static void panel_simple_parse_panel_timing_node(struct device *dev,
455 struct panel_simple *panel,
456 const struct display_timing *ot)
b8a2948f
SP		 457{
458 const struct panel_desc *desc = panel->desc;
459 struct videomode vm;
460 unsigned int i;
461
462 if (WARN_ON(desc->num_modes)) {
463 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
464 return;
465 }
466 if (WARN_ON(!desc->num_timings)) {
467 dev_err(dev, "Reject override mode: no timings specified\n");
468 return;
469 }
470
471 for (i = 0; i < panel->desc->num_timings; i++) {
472 const struct display_timing *dt = &panel->desc->timings[i];
473
474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
482 continue;
483
484 if (ot->flags != dt->flags)
485 continue;
486
487 videomode_from_timing(ot, &vm);
488 drm_display_mode_from_videomode(&vm, &panel->override_mode);
489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
490 DRM_MODE_TYPE_PREFERRED;
491 break;
492 }
493
494 if (WARN_ON(!panel->override_mode.type))
495 dev_err(dev, "Reject override mode: No display_timing found\n");
496}
497
280921de
TR		 498static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
499{
280921de 500 struct panel_simple *panel;
b8a2948f 501 struct display_timing dt;
0fe1564b 502 struct device_node *ddc;
280921de
TR		 503 int err;
504
505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
506 if (!panel)
507 return -ENOMEM;
508
509 panel->enabled = false;
613a633e 510 panel->prepared = false;
280921de
TR		 511 panel->desc = desc;
512
2ed3e951 513 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
48834e60
DA		 514 if (!panel->no_hpd) {
515 err = panel_simple_get_hpd_gpio(dev, panel, true);
516 if (err)
517 return err;
518 }
2ed3e951 519
280921de
TR		 520 panel->supply = devm_regulator_get(dev, "power");
521 if (IS_ERR(panel->supply))
522 return PTR_ERR(panel->supply);
523
a61400d8
AC		 524 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
525 GPIOD_OUT_LOW);
cfdf0549
AC		 526 if (IS_ERR(panel->enable_gpio)) {
527 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 528 if (err != -EPROBE_DEFER)
529 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 530 return err;
531 }
280921de 532
280921de
TR		 533 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
534 if (ddc) {
535 panel->ddc = of_find_i2c_adapter_by_node(ddc);
536 of_node_put(ddc);
537
0fe1564b
SR		 538 if (!panel->ddc)
539 return -EPROBE_DEFER;
280921de
TR		 540 }
541
4a1d0dbc
SR		 542 if (desc == &panel_dpi) {
543 /* Handle the generic panel-dpi binding */
544 err = panel_dpi_probe(dev, panel);
545 if (err)
546 goto free_ddc;
547 } else {
548 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
549 panel_simple_parse_panel_timing_node(dev, panel, &dt);
550 }
b8a2948f 551
1185c406 552 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
c4715837
LP		 553 /* Catch common mistakes for LVDS panels. */
554 WARN_ON(desc->bus_flags &
555 ~(DRM_BUS_FLAG_DE_LOW |
556 DRM_BUS_FLAG_DE_HIGH |
557 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
558 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
1185c406
LP		 559 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
560 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
561 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
562 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
563 desc->bpc != 6);
564 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
565 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
566 desc->bpc != 8);
567 }
c4715837 568
9a2654c0
LP		 569 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
570 desc->connector_type);
280921de 571
0fe1564b
SR		 572 err = drm_panel_of_backlight(&panel->base);
573 if (err)
574 goto free_ddc;
575
280921de
TR		 576 err = drm_panel_add(&panel->base);
577 if (err < 0)
578 goto free_ddc;
579
580 dev_set_drvdata(dev, panel);
581
582 return 0;
583
584free_ddc:
585 if (panel->ddc)
586 put_device(&panel->ddc->dev);
280921de
TR		 587
588 return err;
589}
590
591static int panel_simple_remove(struct device *dev)
592{
593 struct panel_simple *panel = dev_get_drvdata(dev);
594
280921de 595 drm_panel_remove(&panel->base);
0fe1564b
SR		 596 drm_panel_disable(&panel->base);
597 drm_panel_unprepare(&panel->base);
280921de
TR		 598
599 if (panel->ddc)
600 put_device(&panel->ddc->dev);
601
280921de
TR		 602 return 0;
603}
604
d02fd93e
TR		 605static void panel_simple_shutdown(struct device *dev)
606{
607 struct panel_simple *panel = dev_get_drvdata(dev);
608
0fe1564b
SR		 609 drm_panel_disable(&panel->base);
610 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 611}
612
966fea78
YF		 613static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
614 .clock = 9000,
615 .hdisplay = 480,
616 .hsync_start = 480 + 2,
617 .hsync_end = 480 + 2 + 41,
618 .htotal = 480 + 2 + 41 + 2,
619 .vdisplay = 272,
620 .vsync_start = 272 + 2,
621 .vsync_end = 272 + 2 + 10,
622 .vtotal = 272 + 2 + 10 + 2,
966fea78
YF		 623 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
624};
625
626static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
627 .modes = &ampire_am_480272h3tmqw_t01h_mode,
628 .num_modes = 1,
629 .bpc = 8,
630 .size = {
631 .width = 105,
632 .height = 67,
633 },
634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
635};
636
1c550fa1
PZ		 637static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
638 .clock = 33333,
639 .hdisplay = 800,
640 .hsync_start = 800 + 0,
641 .hsync_end = 800 + 0 + 255,
642 .htotal = 800 + 0 + 255 + 0,
643 .vdisplay = 480,
644 .vsync_start = 480 + 2,
645 .vsync_end = 480 + 2 + 45,
646 .vtotal = 480 + 2 + 45 + 0,
1c550fa1
PZ		 647 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
648};
649
650static const struct panel_desc ampire_am800480r3tmqwa1h = {
651 .modes = &ampire_am800480r3tmqwa1h_mode,
652 .num_modes = 1,
653 .bpc = 6,
654 .size = {
655 .width = 152,
656 .height = 91,
657 },
658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
659};
660
c479450f
SS		 661static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
662 .pixelclock = { 26400000, 33300000, 46800000 },
663 .hactive = { 800, 800, 800 },
664 .hfront_porch = { 16, 210, 354 },
665 .hback_porch = { 45, 36, 6 },
666 .hsync_len = { 1, 10, 40 },
667 .vactive = { 480, 480, 480 },
668 .vfront_porch = { 7, 22, 147 },
669 .vback_porch = { 22, 13, 3 },
670 .vsync_len = { 1, 10, 20 },
671 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
672 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
673};
674
675static const struct panel_desc armadeus_st0700_adapt = {
676 .timings = &santek_st0700i5y_rbslw_f_timing,
677 .num_timings = 1,
678 .bpc = 6,
679 .size = {
680 .width = 154,
681 .height = 86,
682 },
683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
685};
686
280921de
TR		 687static const struct drm_display_mode auo_b101aw03_mode = {
688 .clock = 51450,
689 .hdisplay = 1024,
690 .hsync_start = 1024 + 156,
691 .hsync_end = 1024 + 156 + 8,
692 .htotal = 1024 + 156 + 8 + 156,
693 .vdisplay = 600,
694 .vsync_start = 600 + 16,
695 .vsync_end = 600 + 16 + 6,
696 .vtotal = 600 + 16 + 6 + 16,
280921de
TR		 697};
698
699static const struct panel_desc auo_b101aw03 = {
700 .modes = &auo_b101aw03_mode,
701 .num_modes = 1,
0208d511 702 .bpc = 6,
280921de
TR		 703 .size = {
704 .width = 223,
705 .height = 125,
706 },
85560829 707 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 708 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 709 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 710};
711
374bf825
DA		 712static const struct display_timing auo_b101ean01_timing = {
713 .pixelclock = { 65300000, 72500000, 75000000 },
714 .hactive = { 1280, 1280, 1280 },
715 .hfront_porch = { 18, 119, 119 },
716 .hback_porch = { 21, 21, 21 },
717 .hsync_len = { 32, 32, 32 },
718 .vactive = { 800, 800, 800 },
719 .vfront_porch = { 4, 4, 4 },
720 .vback_porch = { 8, 8, 8 },
721 .vsync_len = { 18, 20, 20 },
a531bc3d
HL		 722};
723
724static const struct panel_desc auo_b101ean01 = {
374bf825
DA		 725 .timings = &auo_b101ean01_timing,
726 .num_timings = 1,
a531bc3d
HL		 727 .bpc = 6,
728 .size = {
729 .width = 217,
730 .height = 136,
731 },
732};
733
dac746e0
RC		 734static const struct drm_display_mode auo_b101xtn01_mode = {
735 .clock = 72000,
736 .hdisplay = 1366,
737 .hsync_start = 1366 + 20,
738 .hsync_end = 1366 + 20 + 70,
739 .htotal = 1366 + 20 + 70,
740 .vdisplay = 768,
741 .vsync_start = 768 + 14,
742 .vsync_end = 768 + 14 + 42,
743 .vtotal = 768 + 14 + 42,
dac746e0
RC		 744 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
745};
746
747static const struct panel_desc auo_b101xtn01 = {
748 .modes = &auo_b101xtn01_mode,
749 .num_modes = 1,
750 .bpc = 6,
751 .size = {
752 .width = 223,
753 .height = 125,
754 },
755};
756
da458286
RC		 757static const struct drm_display_mode auo_b116xak01_mode = {
758 .clock = 69300,
759 .hdisplay = 1366,
760 .hsync_start = 1366 + 48,
761 .hsync_end = 1366 + 48 + 32,
762 .htotal = 1366 + 48 + 32 + 10,
763 .vdisplay = 768,
764 .vsync_start = 768 + 4,
765 .vsync_end = 768 + 4 + 6,
766 .vtotal = 768 + 4 + 6 + 15,
da458286
RC		 767 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
768};
769
770static const struct panel_desc auo_b116xak01 = {
771 .modes = &auo_b116xak01_mode,
772 .num_modes = 1,
773 .bpc = 6,
774 .size = {
775 .width = 256,
776 .height = 144,
777 },
778 .delay = {
779 .hpd_absent_delay = 200,
780 },
781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
782 .connector_type = DRM_MODE_CONNECTOR_eDP,
783};
784
e35e305e
AK		 785static const struct drm_display_mode auo_b116xw03_mode = {
786 .clock = 70589,
787 .hdisplay = 1366,
788 .hsync_start = 1366 + 40,
789 .hsync_end = 1366 + 40 + 40,
790 .htotal = 1366 + 40 + 40 + 32,
791 .vdisplay = 768,
792 .vsync_start = 768 + 10,
793 .vsync_end = 768 + 10 + 12,
794 .vtotal = 768 + 10 + 12 + 6,
e35e305e
AK		 795};
796
797static const struct panel_desc auo_b116xw03 = {
798 .modes = &auo_b116xw03_mode,
799 .num_modes = 1,
800 .bpc = 6,
801 .size = {
802 .width = 256,
803 .height = 144,
804 },
805};
806
a333f7ad
SM		 807static const struct drm_display_mode auo_b133xtn01_mode = {
808 .clock = 69500,
809 .hdisplay = 1366,
810 .hsync_start = 1366 + 48,
811 .hsync_end = 1366 + 48 + 32,
812 .htotal = 1366 + 48 + 32 + 20,
813 .vdisplay = 768,
814 .vsync_start = 768 + 3,
815 .vsync_end = 768 + 3 + 6,
816 .vtotal = 768 + 3 + 6 + 13,
a333f7ad
SM		 817};
818
819static const struct panel_desc auo_b133xtn01 = {
820 .modes = &auo_b133xtn01_mode,
821 .num_modes = 1,
0208d511 822 .bpc = 6,
a333f7ad
SM		 823 .size = {
824 .width = 293,
825 .height = 165,
826 },
827};
828
3e51d609
AK		 829static const struct drm_display_mode auo_b133htn01_mode = {
830 .clock = 150660,
831 .hdisplay = 1920,
832 .hsync_start = 1920 + 172,
833 .hsync_end = 1920 + 172 + 80,
834 .htotal = 1920 + 172 + 80 + 60,
835 .vdisplay = 1080,
836 .vsync_start = 1080 + 25,
837 .vsync_end = 1080 + 25 + 10,
838 .vtotal = 1080 + 25 + 10 + 10,
3e51d609
AK		 839};
840
841static const struct panel_desc auo_b133htn01 = {
842 .modes = &auo_b133htn01_mode,
843 .num_modes = 1,
d7a839cd 844 .bpc = 6,
3e51d609
AK		 845 .size = {
846 .width = 293,
847 .height = 165,
848 },
849 .delay = {
850 .prepare = 105,
851 .enable = 20,
852 .unprepare = 50,
853 },
854};
855
bccfaffb
LM		 856static const struct display_timing auo_g070vvn01_timings = {
857 .pixelclock = { 33300000, 34209000, 45000000 },
858 .hactive = { 800, 800, 800 },
859 .hfront_porch = { 20, 40, 200 },
860 .hback_porch = { 87, 40, 1 },
861 .hsync_len = { 1, 48, 87 },
862 .vactive = { 480, 480, 480 },
863 .vfront_porch = { 5, 13, 200 },
864 .vback_porch = { 31, 31, 29 },
865 .vsync_len = { 1, 1, 3 },
866};
867
868static const struct panel_desc auo_g070vvn01 = {
869 .timings = &auo_g070vvn01_timings,
870 .num_timings = 1,
871 .bpc = 8,
872 .size = {
873 .width = 152,
874 .height = 91,
875 },
876 .delay = {
877 .prepare = 200,
878 .enable = 50,
879 .disable = 50,
880 .unprepare = 1000,
881 },
882};
883
4fb86404
AG		 884static const struct drm_display_mode auo_g101evn010_mode = {
885 .clock = 68930,
886 .hdisplay = 1280,
887 .hsync_start = 1280 + 82,
888 .hsync_end = 1280 + 82 + 2,
889 .htotal = 1280 + 82 + 2 + 84,
890 .vdisplay = 800,
891 .vsync_start = 800 + 8,
892 .vsync_end = 800 + 8 + 2,
893 .vtotal = 800 + 8 + 2 + 6,
4fb86404
AG		 894};
895
896static const struct panel_desc auo_g101evn010 = {
897 .modes = &auo_g101evn010_mode,
898 .num_modes = 1,
899 .bpc = 6,
900 .size = {
901 .width = 216,
902 .height = 135,
903 },
27a46fb7
TV		 904 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
905 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4fb86404
AG		 906};
907
4451c287
CF		 908static const struct drm_display_mode auo_g104sn02_mode = {
909 .clock = 40000,
910 .hdisplay = 800,
911 .hsync_start = 800 + 40,
912 .hsync_end = 800 + 40 + 216,
913 .htotal = 800 + 40 + 216 + 128,
914 .vdisplay = 600,
915 .vsync_start = 600 + 10,
916 .vsync_end = 600 + 10 + 35,
917 .vtotal = 600 + 10 + 35 + 2,
4451c287
CF		 918};
919
920static const struct panel_desc auo_g104sn02 = {
921 .modes = &auo_g104sn02_mode,
922 .num_modes = 1,
923 .bpc = 8,
924 .size = {
925 .width = 211,
926 .height = 158,
927 },
928};
929
03e909ac
SR		 930static const struct drm_display_mode auo_g121ean01_mode = {
931 .clock = 66700,
932 .hdisplay = 1280,
933 .hsync_start = 1280 + 58,
934 .hsync_end = 1280 + 58 + 8,
935 .htotal = 1280 + 58 + 8 + 70,
936 .vdisplay = 800,
937 .vsync_start = 800 + 6,
938 .vsync_end = 800 + 6 + 4,
939 .vtotal = 800 + 6 + 4 + 10,
03e909ac
SR		 940};
941
942static const struct panel_desc auo_g121ean01 = {
943 .modes = &auo_g121ean01_mode,
944 .num_modes = 1,
945 .bpc = 8,
946 .size = {
947 .width = 261,
948 .height = 163,
949 },
950 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
951 .connector_type = DRM_MODE_CONNECTOR_LVDS,
952};
953
697035c6
LS		 954static const struct display_timing auo_g133han01_timings = {
955 .pixelclock = { 134000000, 141200000, 149000000 },
956 .hactive = { 1920, 1920, 1920 },
957 .hfront_porch = { 39, 58, 77 },
958 .hback_porch = { 59, 88, 117 },
959 .hsync_len = { 28, 42, 56 },
960 .vactive = { 1080, 1080, 1080 },
961 .vfront_porch = { 3, 8, 11 },
962 .vback_porch = { 5, 14, 19 },
963 .vsync_len = { 4, 14, 19 },
964};
965
966static const struct panel_desc auo_g133han01 = {
967 .timings = &auo_g133han01_timings,
968 .num_timings = 1,
969 .bpc = 8,
970 .size = {
971 .width = 293,
972 .height = 165,
973 },
974 .delay = {
975 .prepare = 200,
976 .enable = 50,
977 .disable = 50,
978 .unprepare = 1000,
979 },
980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 981 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 982};
983
d9ccd1f2
SR		 984static const struct drm_display_mode auo_g156xtn01_mode = {
985 .clock = 76000,
986 .hdisplay = 1366,
987 .hsync_start = 1366 + 33,
988 .hsync_end = 1366 + 33 + 67,
989 .htotal = 1560,
990 .vdisplay = 768,
991 .vsync_start = 768 + 4,
992 .vsync_end = 768 + 4 + 4,
993 .vtotal = 806,
d9ccd1f2
SR		 994};
995
996static const struct panel_desc auo_g156xtn01 = {
997 .modes = &auo_g156xtn01_mode,
998 .num_modes = 1,
999 .bpc = 8,
1000 .size = {
1001 .width = 344,
1002 .height = 194,
1003 },
1004 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1005 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1006};
1007
8c31f603
LS		 1008static const struct display_timing auo_g185han01_timings = {
1009 .pixelclock = { 120000000, 144000000, 175000000 },
1010 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 1011 .hfront_porch = { 36, 120, 148 },
1012 .hback_porch = { 24, 88, 108 },
1013 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 1014 .vactive = { 1080, 1080, 1080 },
1015 .vfront_porch = { 6, 10, 40 },
1016 .vback_porch = { 2, 5, 20 },
1017 .vsync_len = { 2, 5, 20 },
1018};
1019
1020static const struct panel_desc auo_g185han01 = {
1021 .timings = &auo_g185han01_timings,
1022 .num_timings = 1,
1023 .bpc = 8,
1024 .size = {
1025 .width = 409,
1026 .height = 230,
1027 },
1028 .delay = {
1029 .prepare = 50,
1030 .enable = 200,
1031 .disable = 110,
1032 .unprepare = 1000,
1033 },
1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 1036};
1037
2f7b832f
SR		 1038static const struct display_timing auo_g190ean01_timings = {
1039 .pixelclock = { 90000000, 108000000, 135000000 },
1040 .hactive = { 1280, 1280, 1280 },
1041 .hfront_porch = { 126, 184, 1266 },
1042 .hback_porch = { 84, 122, 844 },
1043 .hsync_len = { 70, 102, 704 },
1044 .vactive = { 1024, 1024, 1024 },
1045 .vfront_porch = { 4, 26, 76 },
1046 .vback_porch = { 2, 8, 25 },
1047 .vsync_len = { 2, 8, 25 },
1048};
1049
1050static const struct panel_desc auo_g190ean01 = {
1051 .timings = &auo_g190ean01_timings,
1052 .num_timings = 1,
1053 .bpc = 8,
1054 .size = {
1055 .width = 376,
1056 .height = 301,
1057 },
1058 .delay = {
1059 .prepare = 50,
1060 .enable = 200,
1061 .disable = 110,
1062 .unprepare = 1000,
1063 },
1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1065 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1066};
1067
70c0d5b7
LS		 1068static const struct display_timing auo_p320hvn03_timings = {
1069 .pixelclock = { 106000000, 148500000, 164000000 },
1070 .hactive = { 1920, 1920, 1920 },
1071 .hfront_porch = { 25, 50, 130 },
1072 .hback_porch = { 25, 50, 130 },
1073 .hsync_len = { 20, 40, 105 },
1074 .vactive = { 1080, 1080, 1080 },
1075 .vfront_porch = { 8, 17, 150 },
1076 .vback_porch = { 8, 17, 150 },
1077 .vsync_len = { 4, 11, 100 },
1078};
1079
1080static const struct panel_desc auo_p320hvn03 = {
1081 .timings = &auo_p320hvn03_timings,
1082 .num_timings = 1,
1083 .bpc = 8,
1084 .size = {
1085 .width = 698,
1086 .height = 393,
1087 },
1088 .delay = {
1089 .prepare = 1,
1090 .enable = 450,
1091 .unprepare = 500,
1092 },
2554f154 1093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1094 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 1095};
1096
7ee933a1
HS		 1097static const struct drm_display_mode auo_t215hvn01_mode = {
1098 .clock = 148800,
1099 .hdisplay = 1920,
1100 .hsync_start = 1920 + 88,
1101 .hsync_end = 1920 + 88 + 44,
1102 .htotal = 1920 + 88 + 44 + 148,
1103 .vdisplay = 1080,
1104 .vsync_start = 1080 + 4,
1105 .vsync_end = 1080 + 4 + 5,
1106 .vtotal = 1080 + 4 + 5 + 36,
7ee933a1
HS		 1107};
1108
1109static const struct panel_desc auo_t215hvn01 = {
1110 .modes = &auo_t215hvn01_mode,
1111 .num_modes = 1,
1112 .bpc = 8,
1113 .size = {
1114 .width = 430,
1115 .height = 270,
1116 },
1117 .delay = {
1118 .disable = 5,
1119 .unprepare = 1000,
1120 }
1121};
1122
d47df633
PZ		 1123static const struct drm_display_mode avic_tm070ddh03_mode = {
1124 .clock = 51200,
1125 .hdisplay = 1024,
1126 .hsync_start = 1024 + 160,
1127 .hsync_end = 1024 + 160 + 4,
1128 .htotal = 1024 + 160 + 4 + 156,
1129 .vdisplay = 600,
1130 .vsync_start = 600 + 17,
1131 .vsync_end = 600 + 17 + 1,
1132 .vtotal = 600 + 17 + 1 + 17,
d47df633
PZ		 1133};
1134
1135static const struct panel_desc avic_tm070ddh03 = {
1136 .modes = &avic_tm070ddh03_mode,
1137 .num_modes = 1,
1138 .bpc = 8,
1139 .size = {
1140 .width = 154,
1141 .height = 90,
1142 },
1143 .delay = {
1144 .prepare = 20,
1145 .enable = 200,
1146 .disable = 200,
1147 },
1148};
1149
7ad8b41c
CYT		 1150static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1151 .clock = 30000,
1152 .hdisplay = 800,
1153 .hsync_start = 800 + 40,
1154 .hsync_end = 800 + 40 + 48,
1155 .htotal = 800 + 40 + 48 + 40,
1156 .vdisplay = 480,
1157 .vsync_start = 480 + 13,
1158 .vsync_end = 480 + 13 + 3,
1159 .vtotal = 480 + 13 + 3 + 29,
1160};
1161
1162static const struct panel_desc bananapi_s070wv20_ct16 = {
1163 .modes = &bananapi_s070wv20_ct16_mode,
1164 .num_modes = 1,
1165 .bpc = 6,
1166 .size = {
1167 .width = 154,
1168 .height = 86,
1169 },
1170};
1171
ae8cf41b 1172static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 1173 .clock = 42105,
ae8cf41b 1174 .hdisplay = 1024,
e077e2f5
AH		 1175 .hsync_start = 1024 + 30,
1176 .hsync_end = 1024 + 30 + 30,
1177 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 1178 .vdisplay = 600,
e077e2f5
AH		 1179 .vsync_start = 600 + 10,
1180 .vsync_end = 600 + 10 + 10,
1181 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 1182};
1183
1184static const struct panel_desc boe_hv070wsa = {
1185 .modes = &boe_hv070wsa_mode,
1186 .num_modes = 1,
1187 .size = {
1188 .width = 154,
1189 .height = 90,
1190 },
1191};
1192
cac1a411
CW		 1193static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1194 {
1195 .clock = 71900,
1196 .hdisplay = 1280,
1197 .hsync_start = 1280 + 48,
1198 .hsync_end = 1280 + 48 + 32,
1199 .htotal = 1280 + 48 + 32 + 80,
1200 .vdisplay = 800,
1201 .vsync_start = 800 + 3,
1202 .vsync_end = 800 + 3 + 5,
1203 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1204 },
1205 {
1206 .clock = 57500,
1207 .hdisplay = 1280,
1208 .hsync_start = 1280 + 48,
1209 .hsync_end = 1280 + 48 + 32,
1210 .htotal = 1280 + 48 + 32 + 80,
1211 .vdisplay = 800,
1212 .vsync_start = 800 + 3,
1213 .vsync_end = 800 + 3 + 5,
1214 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1215 },
1216};
1217
1218static const struct panel_desc boe_nv101wxmn51 = {
1219 .modes = boe_nv101wxmn51_modes,
1220 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1221 .bpc = 8,
1222 .size = {
1223 .width = 217,
1224 .height = 136,
1225 },
1226 .delay = {
1227 .prepare = 210,
1228 .enable = 50,
1229 .unprepare = 160,
1230 },
1231};
1232
cfe40d02 1233/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1234static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1235 .clock = 147840,
1236 .hdisplay = 1920,
1237 .hsync_start = 1920 + 48,
1238 .hsync_end = 1920 + 48 + 32,
1239 .htotal = 1920 + 48 + 32 + 200,
1240 .vdisplay = 1080,
1241 .vsync_start = 1080 + 3,
1242 .vsync_end = 1080 + 3 + 6,
1243 .vtotal = 1080 + 3 + 6 + 31,
b0c664cc
BA		 1244};
1245
cfe40d02 1246/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1247static const struct panel_desc boe_nv133fhm_n61 = {
1248 .modes = &boe_nv133fhm_n61_modes,
1249 .num_modes = 1,
9694d9c3 1250 .bpc = 6,
b0c664cc 1251 .size = {
9694d9c3
DA		 1252 .width = 294,
1253 .height = 165,
b0c664cc
BA		 1254 },
1255 .delay = {
1256 .hpd_absent_delay = 200,
1257 .unprepare = 500,
1258 },
1259 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1260 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1261 .connector_type = DRM_MODE_CONNECTOR_eDP,
1262};
1263
a5119818
TS		 1264static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1265 {
1266 .clock = 148500,
1267 .hdisplay = 1920,
1268 .hsync_start = 1920 + 48,
1269 .hsync_end = 1920 + 48 + 32,
1270 .htotal = 2200,
1271 .vdisplay = 1080,
1272 .vsync_start = 1080 + 3,
1273 .vsync_end = 1080 + 3 + 5,
1274 .vtotal = 1125,
a5119818
TS		 1275 },
1276};
1277
1278static const struct panel_desc boe_nv140fhmn49 = {
1279 .modes = boe_nv140fhmn49_modes,
1280 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1281 .bpc = 6,
1282 .size = {
1283 .width = 309,
1284 .height = 174,
1285 },
1286 .delay = {
1287 .prepare = 210,
1288 .enable = 50,
1289 .unprepare = 160,
1290 },
1291 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1292 .connector_type = DRM_MODE_CONNECTOR_eDP,
1293};
1294
e58edce6
GB		 1295static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1296 .clock = 9000,
1297 .hdisplay = 480,
1298 .hsync_start = 480 + 5,
1299 .hsync_end = 480 + 5 + 5,
1300 .htotal = 480 + 5 + 5 + 40,
1301 .vdisplay = 272,
1302 .vsync_start = 272 + 8,
1303 .vsync_end = 272 + 8 + 8,
1304 .vtotal = 272 + 8 + 8 + 8,
e58edce6
GB		 1305 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1306};
1307
1308static const struct panel_desc cdtech_s043wq26h_ct7 = {
1309 .modes = &cdtech_s043wq26h_ct7_mode,
1310 .num_modes = 1,
1311 .bpc = 8,
1312 .size = {
1313 .width = 95,
1314 .height = 54,
1315 },
88bc4178 1316 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1317};
1318
0e3b67f6
MK		 1319/* S070PWS19HP-FC21 2017/04/22 */
1320static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1321 .clock = 51200,
1322 .hdisplay = 1024,
1323 .hsync_start = 1024 + 160,
1324 .hsync_end = 1024 + 160 + 20,
1325 .htotal = 1024 + 160 + 20 + 140,
1326 .vdisplay = 600,
1327 .vsync_start = 600 + 12,
1328 .vsync_end = 600 + 12 + 3,
1329 .vtotal = 600 + 12 + 3 + 20,
1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1331};
1332
1333static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1334 .modes = &cdtech_s070pws19hp_fc21_mode,
1335 .num_modes = 1,
1336 .bpc = 6,
1337 .size = {
1338 .width = 154,
1339 .height = 86,
1340 },
1341 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1342 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1343 .connector_type = DRM_MODE_CONNECTOR_DPI,
1344};
1345
1346/* S070SWV29HG-DC44 2017/09/21 */
1347static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1348 .clock = 33300,
1349 .hdisplay = 800,
1350 .hsync_start = 800 + 210,
1351 .hsync_end = 800 + 210 + 2,
1352 .htotal = 800 + 210 + 2 + 44,
1353 .vdisplay = 480,
1354 .vsync_start = 480 + 22,
1355 .vsync_end = 480 + 22 + 2,
1356 .vtotal = 480 + 22 + 2 + 21,
1357 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1358};
1359
1360static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1361 .modes = &cdtech_s070swv29hg_dc44_mode,
1362 .num_modes = 1,
1363 .bpc = 6,
1364 .size = {
1365 .width = 154,
1366 .height = 86,
1367 },
1368 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1369 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1370 .connector_type = DRM_MODE_CONNECTOR_DPI,
1371};
1372
982f944e
GB		 1373static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1374 .clock = 35000,
1375 .hdisplay = 800,
1376 .hsync_start = 800 + 40,
1377 .hsync_end = 800 + 40 + 40,
1378 .htotal = 800 + 40 + 40 + 48,
1379 .vdisplay = 480,
1380 .vsync_start = 480 + 29,
1381 .vsync_end = 480 + 29 + 13,
1382 .vtotal = 480 + 29 + 13 + 3,
982f944e
GB		 1383 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1384};
1385
1386static const struct panel_desc cdtech_s070wv95_ct16 = {
1387 .modes = &cdtech_s070wv95_ct16_mode,
1388 .num_modes = 1,
1389 .bpc = 8,
1390 .size = {
1391 .width = 154,
1392 .height = 85,
1393 },
1394};
1395
2cb35c80
RL		 1396static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1397 .clock = 66770,
1398 .hdisplay = 800,
1399 .hsync_start = 800 + 49,
1400 .hsync_end = 800 + 49 + 33,
1401 .htotal = 800 + 49 + 33 + 17,
1402 .vdisplay = 1280,
1403 .vsync_start = 1280 + 1,
1404 .vsync_end = 1280 + 1 + 7,
1405 .vtotal = 1280 + 1 + 7 + 15,
2cb35c80
RL		 1406 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1407};
1408
1409static const struct panel_desc chunghwa_claa070wp03xg = {
1410 .modes = &chunghwa_claa070wp03xg_mode,
1411 .num_modes = 1,
1412 .bpc = 6,
1413 .size = {
1414 .width = 94,
1415 .height = 150,
1416 },
85560829 1417 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1418 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1419 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2cb35c80
RL		 1420};
1421
4c930757
SW		 1422static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1423 .clock = 72070,
1424 .hdisplay = 1366,
1425 .hsync_start = 1366 + 58,
1426 .hsync_end = 1366 + 58 + 58,
1427 .htotal = 1366 + 58 + 58 + 58,
1428 .vdisplay = 768,
1429 .vsync_start = 768 + 4,
1430 .vsync_end = 768 + 4 + 4,
1431 .vtotal = 768 + 4 + 4 + 4,
4c930757
SW		 1432};
1433
1434static const struct panel_desc chunghwa_claa101wa01a = {
1435 .modes = &chunghwa_claa101wa01a_mode,
1436 .num_modes = 1,
0208d511 1437 .bpc = 6,
4c930757
SW		 1438 .size = {
1439 .width = 220,
1440 .height = 120,
1441 },
85560829 1442 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1443 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1444 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4c930757
SW		 1445};
1446
280921de
TR		 1447static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1448 .clock = 69300,
1449 .hdisplay = 1366,
1450 .hsync_start = 1366 + 48,
1451 .hsync_end = 1366 + 48 + 32,
1452 .htotal = 1366 + 48 + 32 + 20,
1453 .vdisplay = 768,
1454 .vsync_start = 768 + 16,
1455 .vsync_end = 768 + 16 + 8,
1456 .vtotal = 768 + 16 + 8 + 16,
280921de
TR		 1457};
1458
1459static const struct panel_desc chunghwa_claa101wb01 = {
1460 .modes = &chunghwa_claa101wb01_mode,
1461 .num_modes = 1,
0208d511 1462 .bpc = 6,
280921de
TR		 1463 .size = {
1464 .width = 223,
1465 .height = 125,
1466 },
85560829 1467 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1468 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1469 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 1470};
1471
97ceb1fb
MV		 1472static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1473 .clock = 33260,
1474 .hdisplay = 800,
1475 .hsync_start = 800 + 40,
1476 .hsync_end = 800 + 40 + 128,
1477 .htotal = 800 + 40 + 128 + 88,
1478 .vdisplay = 480,
1479 .vsync_start = 480 + 10,
1480 .vsync_end = 480 + 10 + 2,
1481 .vtotal = 480 + 10 + 2 + 33,
97ceb1fb
MV		 1482 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1483};
1484
1485static const struct panel_desc dataimage_scf0700c48ggu18 = {
1486 .modes = &dataimage_scf0700c48ggu18_mode,
1487 .num_modes = 1,
1488 .bpc = 8,
1489 .size = {
1490 .width = 152,
1491 .height = 91,
1492 },
1493 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1494 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1495};
1496
0ca0c827
PZ		 1497static const struct display_timing dlc_dlc0700yzg_1_timing = {
1498 .pixelclock = { 45000000, 51200000, 57000000 },
1499 .hactive = { 1024, 1024, 1024 },
1500 .hfront_porch = { 100, 106, 113 },
1501 .hback_porch = { 100, 106, 113 },
1502 .hsync_len = { 100, 108, 114 },
1503 .vactive = { 600, 600, 600 },
1504 .vfront_porch = { 8, 11, 15 },
1505 .vback_porch = { 8, 11, 15 },
1506 .vsync_len = { 9, 13, 15 },
1507 .flags = DISPLAY_FLAGS_DE_HIGH,
1508};
1509
1510static const struct panel_desc dlc_dlc0700yzg_1 = {
1511 .timings = &dlc_dlc0700yzg_1_timing,
1512 .num_timings = 1,
1513 .bpc = 6,
1514 .size = {
1515 .width = 154,
1516 .height = 86,
1517 },
1518 .delay = {
1519 .prepare = 30,
1520 .enable = 200,
1521 .disable = 200,
1522 },
1523 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1524 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1525};
1526
6cbe7cd1
MF		 1527static const struct display_timing dlc_dlc1010gig_timing = {
1528 .pixelclock = { 68900000, 71100000, 73400000 },
1529 .hactive = { 1280, 1280, 1280 },
1530 .hfront_porch = { 43, 53, 63 },
1531 .hback_porch = { 43, 53, 63 },
1532 .hsync_len = { 44, 54, 64 },
1533 .vactive = { 800, 800, 800 },
1534 .vfront_porch = { 5, 8, 11 },
1535 .vback_porch = { 5, 8, 11 },
1536 .vsync_len = { 5, 7, 11 },
1537 .flags = DISPLAY_FLAGS_DE_HIGH,
1538};
1539
1540static const struct panel_desc dlc_dlc1010gig = {
1541 .timings = &dlc_dlc1010gig_timing,
1542 .num_timings = 1,
1543 .bpc = 8,
1544 .size = {
1545 .width = 216,
1546 .height = 135,
1547 },
1548 .delay = {
1549 .prepare = 60,
1550 .enable = 150,
1551 .disable = 100,
1552 .unprepare = 60,
1553 },
1554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1555 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1556};
1557
c2d24af6
AP		 1558static const struct drm_display_mode edt_et035012dm6_mode = {
1559 .clock = 6500,
1560 .hdisplay = 320,
1561 .hsync_start = 320 + 20,
1562 .hsync_end = 320 + 20 + 30,
1563 .htotal = 320 + 20 + 68,
1564 .vdisplay = 240,
1565 .vsync_start = 240 + 4,
1566 .vsync_end = 240 + 4 + 4,
1567 .vtotal = 240 + 4 + 4 + 14,
c2d24af6
AP		 1568 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1569};
1570
1571static const struct panel_desc edt_et035012dm6 = {
1572 .modes = &edt_et035012dm6_mode,
1573 .num_modes = 1,
1574 .bpc = 8,
1575 .size = {
1576 .width = 70,
1577 .height = 52,
1578 },
1579 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1580 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1581};
1582
82d57a59
MCR		 1583static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1584 .clock = 10870,
1585 .hdisplay = 480,
1586 .hsync_start = 480 + 8,
1587 .hsync_end = 480 + 8 + 4,
1588 .htotal = 480 + 8 + 4 + 41,
1589
1590 /*
1591 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1592 * fb_align
1593 */
1594
1595 .vdisplay = 288,
1596 .vsync_start = 288 + 2,
1597 .vsync_end = 288 + 2 + 4,
1598 .vtotal = 288 + 2 + 4 + 10,
82d57a59
MCR		 1599};
1600
1601static const struct panel_desc edt_etm043080dh6gp = {
1602 .modes = &edt_etm043080dh6gp_mode,
1603 .num_modes = 1,
1604 .bpc = 8,
1605 .size = {
1606 .width = 100,
1607 .height = 65,
1608 },
1609 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1610 .connector_type = DRM_MODE_CONNECTOR_DPI,
1611};
1612
fd819bff
MV		 1613static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1614 .clock = 9000,
1615 .hdisplay = 480,
1616 .hsync_start = 480 + 2,
1617 .hsync_end = 480 + 2 + 41,
1618 .htotal = 480 + 2 + 41 + 2,
1619 .vdisplay = 272,
1620 .vsync_start = 272 + 2,
1621 .vsync_end = 272 + 2 + 10,
1622 .vtotal = 272 + 2 + 10 + 2,
fd819bff
MV		 1623 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1624};
1625
1626static const struct panel_desc edt_etm0430g0dh6 = {
1627 .modes = &edt_etm0430g0dh6_mode,
1628 .num_modes = 1,
1629 .bpc = 6,
1630 .size = {
1631 .width = 95,
1632 .height = 54,
1633 },
1634};
1635
26ab0065
SA		 1636static const struct drm_display_mode edt_et057090dhu_mode = {
1637 .clock = 25175,
1638 .hdisplay = 640,
1639 .hsync_start = 640 + 16,
1640 .hsync_end = 640 + 16 + 30,
1641 .htotal = 640 + 16 + 30 + 114,
1642 .vdisplay = 480,
1643 .vsync_start = 480 + 10,
1644 .vsync_end = 480 + 10 + 3,
1645 .vtotal = 480 + 10 + 3 + 32,
26ab0065
SA		 1646 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1647};
1648
1649static const struct panel_desc edt_et057090dhu = {
1650 .modes = &edt_et057090dhu_mode,
1651 .num_modes = 1,
0208d511 1652 .bpc = 6,
26ab0065
SA		 1653 .size = {
1654 .width = 115,
1655 .height = 86,
1656 },
eaeebffa 1657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1658 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
75e73224 1659 .connector_type = DRM_MODE_CONNECTOR_DPI,
26ab0065
SA		 1660};
1661
fff5de45
PZ		 1662static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1663 .clock = 33260,
1664 .hdisplay = 800,
1665 .hsync_start = 800 + 40,
1666 .hsync_end = 800 + 40 + 128,
1667 .htotal = 800 + 40 + 128 + 88,
1668 .vdisplay = 480,
1669 .vsync_start = 480 + 10,
1670 .vsync_end = 480 + 10 + 2,
1671 .vtotal = 480 + 10 + 2 + 33,
fff5de45
PZ		 1672 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1673};
1674
1675static const struct panel_desc edt_etm0700g0dh6 = {
1676 .modes = &edt_etm0700g0dh6_mode,
1677 .num_modes = 1,
0208d511 1678 .bpc = 6,
fff5de45
PZ		 1679 .size = {
1680 .width = 152,
1681 .height = 91,
1682 },
eaeebffa 1683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
fff5de45
PZ		 1685};
1686
aa7e6455
JT		 1687static const struct panel_desc edt_etm0700g0bdh6 = {
1688 .modes = &edt_etm0700g0dh6_mode,
1689 .num_modes = 1,
1690 .bpc = 6,
1691 .size = {
1692 .width = 152,
1693 .height = 91,
1694 },
1695 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1696 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
aa7e6455
JT		 1697};
1698
9158e3c3
MF		 1699static const struct display_timing evervision_vgg804821_timing = {
1700 .pixelclock = { 27600000, 33300000, 50000000 },
1701 .hactive = { 800, 800, 800 },
1702 .hfront_porch = { 40, 66, 70 },
1703 .hback_porch = { 40, 67, 70 },
1704 .hsync_len = { 40, 67, 70 },
1705 .vactive = { 480, 480, 480 },
1706 .vfront_porch = { 6, 10, 10 },
1707 .vback_porch = { 7, 11, 11 },
1708 .vsync_len = { 7, 11, 11 },
1709 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1710 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1711 DISPLAY_FLAGS_SYNC_NEGEDGE,
1712};
1713
1714static const struct panel_desc evervision_vgg804821 = {
1715 .timings = &evervision_vgg804821_timing,
1716 .num_timings = 1,
1717 .bpc = 8,
1718 .size = {
1719 .width = 108,
1720 .height = 64,
1721 },
1722 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1723 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1724};
1725
102932b0
BB		 1726static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1727 .clock = 32260,
1728 .hdisplay = 800,
1729 .hsync_start = 800 + 168,
1730 .hsync_end = 800 + 168 + 64,
1731 .htotal = 800 + 168 + 64 + 88,
1732 .vdisplay = 480,
1733 .vsync_start = 480 + 37,
1734 .vsync_end = 480 + 37 + 2,
1735 .vtotal = 480 + 37 + 2 + 8,
102932b0
BB		 1736};
1737
1738static const struct panel_desc foxlink_fl500wvr00_a0t = {
1739 .modes = &foxlink_fl500wvr00_a0t_mode,
1740 .num_modes = 1,
d7a839cd 1741 .bpc = 8,
102932b0
BB		 1742 .size = {
1743 .width = 108,
1744 .height = 65,
1745 },
bb276cb3 1746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1747};
1748
7b6bd843
PC		 1749static const struct drm_display_mode frida_frd350h54004_mode = {
1750 .clock = 6000,
1751 .hdisplay = 320,
1752 .hsync_start = 320 + 44,
1753 .hsync_end = 320 + 44 + 16,
1754 .htotal = 320 + 44 + 16 + 20,
1755 .vdisplay = 240,
1756 .vsync_start = 240 + 2,
1757 .vsync_end = 240 + 2 + 6,
1758 .vtotal = 240 + 2 + 6 + 2,
7b6bd843
PC		 1759 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1760};
1761
1762static const struct panel_desc frida_frd350h54004 = {
1763 .modes = &frida_frd350h54004_mode,
1764 .num_modes = 1,
1765 .bpc = 8,
1766 .size = {
1767 .width = 77,
1768 .height = 64,
1769 },
1770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1771 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
1772 .connector_type = DRM_MODE_CONNECTOR_DPI,
1773};
1774
3be20710
JT		 1775static const struct drm_display_mode friendlyarm_hd702e_mode = {
1776 .clock = 67185,
1777 .hdisplay = 800,
1778 .hsync_start = 800 + 20,
1779 .hsync_end = 800 + 20 + 24,
1780 .htotal = 800 + 20 + 24 + 20,
1781 .vdisplay = 1280,
1782 .vsync_start = 1280 + 4,
1783 .vsync_end = 1280 + 4 + 8,
1784 .vtotal = 1280 + 4 + 8 + 4,
3be20710
JT		 1785 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1786};
1787
1788static const struct panel_desc friendlyarm_hd702e = {
1789 .modes = &friendlyarm_hd702e_mode,
1790 .num_modes = 1,
1791 .size = {
1792 .width = 94,
1793 .height = 151,
1794 },
1795};
1796
d435a2af
PZ		 1797static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1798 .clock = 9000,
1799 .hdisplay = 480,
1800 .hsync_start = 480 + 5,
1801 .hsync_end = 480 + 5 + 1,
1802 .htotal = 480 + 5 + 1 + 40,
1803 .vdisplay = 272,
1804 .vsync_start = 272 + 8,
1805 .vsync_end = 272 + 8 + 1,
1806 .vtotal = 272 + 8 + 1 + 8,
d435a2af
PZ		 1807};
1808
1809static const struct panel_desc giantplus_gpg482739qs5 = {
1810 .modes = &giantplus_gpg482739qs5_mode,
1811 .num_modes = 1,
1812 .bpc = 8,
1813 .size = {
1814 .width = 95,
1815 .height = 54,
1816 },
33536a09 1817 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1818};
1819
2c6574a9
PC		 1820static const struct display_timing giantplus_gpm940b0_timing = {
1821 .pixelclock = { 13500000, 27000000, 27500000 },
1822 .hactive = { 320, 320, 320 },
1823 .hfront_porch = { 14, 686, 718 },
1824 .hback_porch = { 50, 70, 255 },
1825 .hsync_len = { 1, 1, 1 },
1826 .vactive = { 240, 240, 240 },
1827 .vfront_porch = { 1, 1, 179 },
1828 .vback_porch = { 1, 21, 31 },
1829 .vsync_len = { 1, 1, 6 },
1830 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1831};
1832
1833static const struct panel_desc giantplus_gpm940b0 = {
1834 .timings = &giantplus_gpm940b0_timing,
1835 .num_timings = 1,
1836 .bpc = 8,
1837 .size = {
1838 .width = 60,
1839 .height = 45,
1840 },
1841 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1843};
1844
ab07725a
PZ		 1845static const struct display_timing hannstar_hsd070pww1_timing = {
1846 .pixelclock = { 64300000, 71100000, 82000000 },
1847 .hactive = { 1280, 1280, 1280 },
1848 .hfront_porch = { 1, 1, 10 },
1849 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1850 /*
1851 * According to the data sheet, the minimum horizontal blanking interval
1852 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1853 * minimum working horizontal blanking interval to be 60 clocks.
1854 */
1855 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 1856 .vactive = { 800, 800, 800 },
1857 .vfront_porch = { 1, 1, 10 },
1858 .vback_porch = { 1, 1, 10 },
1859 .vsync_len = { 1, 21, 203 },
1860 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1861};
1862
1863static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1864 .timings = &hannstar_hsd070pww1_timing,
1865 .num_timings = 1,
a853205e
PZ		 1866 .bpc = 6,
1867 .size = {
1868 .width = 151,
1869 .height = 94,
1870 },
58d6a7bc 1871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1872 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 1873};
1874
c0d607e5
EN		 1875static const struct display_timing hannstar_hsd100pxn1_timing = {
1876 .pixelclock = { 55000000, 65000000, 75000000 },
1877 .hactive = { 1024, 1024, 1024 },
1878 .hfront_porch = { 40, 40, 40 },
1879 .hback_porch = { 220, 220, 220 },
1880 .hsync_len = { 20, 60, 100 },
1881 .vactive = { 768, 768, 768 },
1882 .vfront_porch = { 7, 7, 7 },
1883 .vback_porch = { 21, 21, 21 },
1884 .vsync_len = { 10, 10, 10 },
1885 .flags = DISPLAY_FLAGS_DE_HIGH,
1886};
1887
1888static const struct panel_desc hannstar_hsd100pxn1 = {
1889 .timings = &hannstar_hsd100pxn1_timing,
1890 .num_timings = 1,
1891 .bpc = 6,
1892 .size = {
1893 .width = 203,
1894 .height = 152,
1895 },
4946b043 1896 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1897 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 1898};
1899
61ac0bf8
LS		 1900static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1901 .clock = 33333,
1902 .hdisplay = 800,
1903 .hsync_start = 800 + 85,
1904 .hsync_end = 800 + 85 + 86,
1905 .htotal = 800 + 85 + 86 + 85,
1906 .vdisplay = 480,
1907 .vsync_start = 480 + 16,
1908 .vsync_end = 480 + 16 + 13,
1909 .vtotal = 480 + 16 + 13 + 16,
61ac0bf8
LS		 1910};
1911
1912static const struct panel_desc hitachi_tx23d38vm0caa = {
1913 .modes = &hitachi_tx23d38vm0caa_mode,
1914 .num_modes = 1,
1915 .bpc = 6,
1916 .size = {
1917 .width = 195,
1918 .height = 117,
1919 },
6c684e3b
PZ		 1920 .delay = {
1921 .enable = 160,
1922 .disable = 160,
1923 },
61ac0bf8
LS		 1924};
1925
41bcceb4
NF		 1926static const struct drm_display_mode innolux_at043tn24_mode = {
1927 .clock = 9000,
1928 .hdisplay = 480,
1929 .hsync_start = 480 + 2,
1930 .hsync_end = 480 + 2 + 41,
1931 .htotal = 480 + 2 + 41 + 2,
1932 .vdisplay = 272,
1933 .vsync_start = 272 + 2,
a483159d
PZ		 1934 .vsync_end = 272 + 2 + 10,
1935 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 1936 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1937};
1938
1939static const struct panel_desc innolux_at043tn24 = {
1940 .modes = &innolux_at043tn24_mode,
1941 .num_modes = 1,
1942 .bpc = 8,
1943 .size = {
1944 .width = 95,
1945 .height = 54,
1946 },
1947 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1948 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 1949};
1950
4fc24ab3
RB		 1951static const struct drm_display_mode innolux_at070tn92_mode = {
1952 .clock = 33333,
1953 .hdisplay = 800,
1954 .hsync_start = 800 + 210,
1955 .hsync_end = 800 + 210 + 20,
1956 .htotal = 800 + 210 + 20 + 46,
1957 .vdisplay = 480,
1958 .vsync_start = 480 + 22,
1959 .vsync_end = 480 + 22 + 10,
1960 .vtotal = 480 + 22 + 23 + 10,
4fc24ab3
RB		 1961};
1962
1963static const struct panel_desc innolux_at070tn92 = {
1964 .modes = &innolux_at070tn92_mode,
1965 .num_modes = 1,
1966 .size = {
1967 .width = 154,
1968 .height = 86,
1969 },
1970 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1971};
1972
a5d2ade6
CF		 1973static const struct display_timing innolux_g070y2_l01_timing = {
1974 .pixelclock = { 28000000, 29500000, 32000000 },
1975 .hactive = { 800, 800, 800 },
1976 .hfront_porch = { 61, 91, 141 },
1977 .hback_porch = { 60, 90, 140 },
1978 .hsync_len = { 12, 12, 12 },
1979 .vactive = { 480, 480, 480 },
1980 .vfront_porch = { 4, 9, 30 },
1981 .vback_porch = { 4, 8, 28 },
1982 .vsync_len = { 2, 2, 2 },
1983 .flags = DISPLAY_FLAGS_DE_HIGH,
1984};
1985
1986static const struct panel_desc innolux_g070y2_l01 = {
1987 .timings = &innolux_g070y2_l01_timing,
1988 .num_timings = 1,
1989 .bpc = 6,
1990 .size = {
1991 .width = 152,
1992 .height = 91,
1993 },
1994 .delay = {
1995 .prepare = 10,
1996 .enable = 100,
1997 .disable = 100,
1998 .unprepare = 800,
1999 },
2000 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2001 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 2002};
2003
1e29b840
MO		 2004static const struct display_timing innolux_g101ice_l01_timing = {
2005 .pixelclock = { 60400000, 71100000, 74700000 },
2006 .hactive = { 1280, 1280, 1280 },
2007 .hfront_porch = { 41, 80, 100 },
2008 .hback_porch = { 40, 79, 99 },
2009 .hsync_len = { 1, 1, 1 },
2010 .vactive = { 800, 800, 800 },
2011 .vfront_porch = { 5, 11, 14 },
2012 .vback_porch = { 4, 11, 14 },
2013 .vsync_len = { 1, 1, 1 },
2014 .flags = DISPLAY_FLAGS_DE_HIGH,
2015};
2016
2017static const struct panel_desc innolux_g101ice_l01 = {
2018 .timings = &innolux_g101ice_l01_timing,
2019 .num_timings = 1,
2020 .bpc = 8,
2021 .size = {
2022 .width = 217,
2023 .height = 135,
2024 },
2025 .delay = {
2026 .enable = 200,
2027 .disable = 200,
2028 },
2029 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2030 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 2031};
2032
4ae13e48
LS		 2033static const struct display_timing innolux_g121i1_l01_timing = {
2034 .pixelclock = { 67450000, 71000000, 74550000 },
2035 .hactive = { 1280, 1280, 1280 },
2036 .hfront_porch = { 40, 80, 160 },
2037 .hback_porch = { 39, 79, 159 },
2038 .hsync_len = { 1, 1, 1 },
2039 .vactive = { 800, 800, 800 },
2040 .vfront_porch = { 5, 11, 100 },
2041 .vback_porch = { 4, 11, 99 },
2042 .vsync_len = { 1, 1, 1 },
d731f661
LS		 2043};
2044
2045static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 2046 .timings = &innolux_g121i1_l01_timing,
2047 .num_timings = 1,
d731f661
LS		 2048 .bpc = 6,
2049 .size = {
2050 .width = 261,
2051 .height = 163,
2052 },
4ae13e48
LS		 2053 .delay = {
2054 .enable = 200,
2055 .disable = 20,
2056 },
2057 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2058 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 2059};
2060
f8fa17ba
AB		 2061static const struct drm_display_mode innolux_g121x1_l03_mode = {
2062 .clock = 65000,
2063 .hdisplay = 1024,
2064 .hsync_start = 1024 + 0,
2065 .hsync_end = 1024 + 1,
2066 .htotal = 1024 + 0 + 1 + 320,
2067 .vdisplay = 768,
2068 .vsync_start = 768 + 38,
2069 .vsync_end = 768 + 38 + 1,
2070 .vtotal = 768 + 38 + 1 + 0,
2e8c5eb9 2071 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 2072};
2073
2074static const struct panel_desc innolux_g121x1_l03 = {
2075 .modes = &innolux_g121x1_l03_mode,
2076 .num_modes = 1,
2077 .bpc = 6,
2078 .size = {
2079 .width = 246,
2080 .height = 185,
2081 },
2082 .delay = {
2083 .enable = 200,
2084 .unprepare = 200,
2085 .disable = 400,
2086 },
2087};
2088
d719cbe9
DA		 2089/*
2090 * Datasheet specifies that at 60 Hz refresh rate:
2091 * - total horizontal time: { 1506, 1592, 1716 }
2092 * - total vertical time: { 788, 800, 868 }
2093 *
2094 * ...but doesn't go into exactly how that should be split into a front
2095 * porch, back porch, or sync length. For now we'll leave a single setting
2096 * here which allows a bit of tweaking of the pixel clock at the expense of
2097 * refresh rate.
2098 */
2099static const struct display_timing innolux_n116bge_timing = {
2100 .pixelclock = { 72600000, 76420000, 80240000 },
2101 .hactive = { 1366, 1366, 1366 },
2102 .hfront_porch = { 136, 136, 136 },
2103 .hback_porch = { 60, 60, 60 },
2104 .hsync_len = { 30, 30, 30 },
2105 .vactive = { 768, 768, 768 },
2106 .vfront_porch = { 8, 8, 8 },
2107 .vback_porch = { 12, 12, 12 },
2108 .vsync_len = { 12, 12, 12 },
2109 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
0a2288c0
TR		 2110};
2111
2112static const struct panel_desc innolux_n116bge = {
d719cbe9
DA		 2113 .timings = &innolux_n116bge_timing,
2114 .num_timings = 1,
0a2288c0
TR		 2115 .bpc = 6,
2116 .size = {
2117 .width = 256,
2118 .height = 144,
2119 },
2120};
2121
ea44739d
AB		 2122static const struct drm_display_mode innolux_n156bge_l21_mode = {
2123 .clock = 69300,
2124 .hdisplay = 1366,
2125 .hsync_start = 1366 + 16,
2126 .hsync_end = 1366 + 16 + 34,
2127 .htotal = 1366 + 16 + 34 + 50,
2128 .vdisplay = 768,
2129 .vsync_start = 768 + 2,
2130 .vsync_end = 768 + 2 + 6,
2131 .vtotal = 768 + 2 + 6 + 12,
ea44739d
AB		 2132};
2133
2134static const struct panel_desc innolux_n156bge_l21 = {
2135 .modes = &innolux_n156bge_l21_mode,
2136 .num_modes = 1,
0208d511 2137 .bpc = 6,
ea44739d
AB		 2138 .size = {
2139 .width = 344,
2140 .height = 193,
2141 },
85560829 2142 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 2143 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 2144 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ea44739d
AB		 2145};
2146
8f054b6f 2147static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 2148 .clock = 206016,
2149 .hdisplay = 2160,
2150 .hsync_start = 2160 + 48,
2151 .hsync_end = 2160 + 48 + 32,
2152 .htotal = 2160 + 48 + 32 + 80,
2153 .vdisplay = 1440,
2154 .vsync_start = 1440 + 3,
2155 .vsync_end = 1440 + 3 + 10,
2156 .vtotal = 1440 + 3 + 10 + 27,
da50bd42 2157 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2158};
2159
8f054b6f
DA		 2160static const struct panel_desc innolux_p120zdg_bf1 = {
2161 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 2162 .num_modes = 1,
2163 .bpc = 8,
2164 .size = {
8f054b6f
DA		 2165 .width = 254,
2166 .height = 169,
da50bd42 2167 },
22fd99e9 2168 .delay = {
625d3b5c 2169 .hpd_absent_delay = 200,
22fd99e9
SP		 2170 .unprepare = 500,
2171 },
da50bd42 2172};
2173
bccac3f1
MG		 2174static const struct drm_display_mode innolux_zj070na_01p_mode = {
2175 .clock = 51501,
2176 .hdisplay = 1024,
2177 .hsync_start = 1024 + 128,
2178 .hsync_end = 1024 + 128 + 64,
2179 .htotal = 1024 + 128 + 64 + 128,
2180 .vdisplay = 600,
2181 .vsync_start = 600 + 16,
2182 .vsync_end = 600 + 16 + 4,
2183 .vtotal = 600 + 16 + 4 + 16,
bccac3f1
MG		 2184};
2185
2186static const struct panel_desc innolux_zj070na_01p = {
2187 .modes = &innolux_zj070na_01p_mode,
2188 .num_modes = 1,
2189 .bpc = 6,
2190 .size = {
81598846
TR		 2191 .width = 154,
2192 .height = 90,
bccac3f1
MG		 2193 },
2194};
2195
e1ca5184
BA		 2196static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2197 .clock = 138778,
2198 .hdisplay = 1920,
2199 .hsync_start = 1920 + 24,
2200 .hsync_end = 1920 + 24 + 48,
2201 .htotal = 1920 + 24 + 48 + 88,
2202 .vdisplay = 1080,
2203 .vsync_start = 1080 + 3,
2204 .vsync_end = 1080 + 3 + 12,
2205 .vtotal = 1080 + 3 + 12 + 17,
e1ca5184
BA		 2206 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2207};
2208
2209static const struct panel_desc ivo_m133nwf4_r0 = {
2210 .modes = &ivo_m133nwf4_r0_mode,
2211 .num_modes = 1,
2212 .bpc = 8,
2213 .size = {
2214 .width = 294,
2215 .height = 165,
2216 },
2217 .delay = {
2218 .hpd_absent_delay = 200,
2219 .unprepare = 500,
2220 },
2221 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2222 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2223 .connector_type = DRM_MODE_CONNECTOR_eDP,
2224};
2225
14bf60c4
LM		 2226static const struct display_timing koe_tx14d24vm1bpa_timing = {
2227 .pixelclock = { 5580000, 5850000, 6200000 },
2228 .hactive = { 320, 320, 320 },
2229 .hfront_porch = { 30, 30, 30 },
2230 .hback_porch = { 30, 30, 30 },
2231 .hsync_len = { 1, 5, 17 },
2232 .vactive = { 240, 240, 240 },
2233 .vfront_porch = { 6, 6, 6 },
2234 .vback_porch = { 5, 5, 5 },
2235 .vsync_len = { 1, 2, 11 },
2236 .flags = DISPLAY_FLAGS_DE_HIGH,
2237};
2238
2239static const struct panel_desc koe_tx14d24vm1bpa = {
2240 .timings = &koe_tx14d24vm1bpa_timing,
2241 .num_timings = 1,
2242 .bpc = 6,
2243 .size = {
2244 .width = 115,
2245 .height = 86,
2246 },
2247};
2248
8a070524
LY		 2249static const struct display_timing koe_tx26d202vm0bwa_timing = {
2250 .pixelclock = { 151820000, 156720000, 159780000 },
2251 .hactive = { 1920, 1920, 1920 },
2252 .hfront_porch = { 105, 130, 142 },
2253 .hback_porch = { 45, 70, 82 },
2254 .hsync_len = { 30, 30, 30 },
2255 .vactive = { 1200, 1200, 1200},
2256 .vfront_porch = { 3, 5, 10 },
2257 .vback_porch = { 2, 5, 10 },
2258 .vsync_len = { 5, 5, 5 },
2259};
2260
2261static const struct panel_desc koe_tx26d202vm0bwa = {
2262 .timings = &koe_tx26d202vm0bwa_timing,
2263 .num_timings = 1,
2264 .bpc = 8,
2265 .size = {
2266 .width = 217,
2267 .height = 136,
2268 },
2269 .delay = {
2270 .prepare = 1000,
2271 .enable = 1000,
2272 .unprepare = 1000,
2273 .disable = 1000,
2274 },
2275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2276 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
8a070524
LY		 2277 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2278};
2279
8cfe8341
JT		 2280static const struct display_timing koe_tx31d200vm0baa_timing = {
2281 .pixelclock = { 39600000, 43200000, 48000000 },
2282 .hactive = { 1280, 1280, 1280 },
2283 .hfront_porch = { 16, 36, 56 },
2284 .hback_porch = { 16, 36, 56 },
2285 .hsync_len = { 8, 8, 8 },
2286 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 2287 .vfront_porch = { 6, 21, 33 },
2288 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 2289 .vsync_len = { 8, 8, 8 },
2290 .flags = DISPLAY_FLAGS_DE_HIGH,
2291};
2292
2293static const struct panel_desc koe_tx31d200vm0baa = {
2294 .timings = &koe_tx31d200vm0baa_timing,
2295 .num_timings = 1,
2296 .bpc = 6,
2297 .size = {
2298 .width = 292,
2299 .height = 109,
2300 },
2301 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2302 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 2303};
2304
8def22e5
LS		 2305static const struct display_timing kyo_tcg121xglp_timing = {
2306 .pixelclock = { 52000000, 65000000, 71000000 },
2307 .hactive = { 1024, 1024, 1024 },
2308 .hfront_porch = { 2, 2, 2 },
2309 .hback_porch = { 2, 2, 2 },
2310 .hsync_len = { 86, 124, 244 },
2311 .vactive = { 768, 768, 768 },
2312 .vfront_porch = { 2, 2, 2 },
2313 .vback_porch = { 2, 2, 2 },
2314 .vsync_len = { 6, 34, 73 },
2315 .flags = DISPLAY_FLAGS_DE_HIGH,
2316};
2317
2318static const struct panel_desc kyo_tcg121xglp = {
2319 .timings = &kyo_tcg121xglp_timing,
2320 .num_timings = 1,
2321 .bpc = 8,
2322 .size = {
2323 .width = 246,
2324 .height = 184,
2325 },
2326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2327 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 2328};
2329
27abdd83
PK		 2330static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2331 .clock = 7000,
2332 .hdisplay = 320,
2333 .hsync_start = 320 + 20,
2334 .hsync_end = 320 + 20 + 30,
2335 .htotal = 320 + 20 + 30 + 38,
2336 .vdisplay = 240,
2337 .vsync_start = 240 + 4,
2338 .vsync_end = 240 + 4 + 3,
2339 .vtotal = 240 + 4 + 3 + 15,
27abdd83
PK		 2340};
2341
2342static const struct panel_desc lemaker_bl035_rgb_002 = {
2343 .modes = &lemaker_bl035_rgb_002_mode,
2344 .num_modes = 1,
2345 .size = {
2346 .width = 70,
2347 .height = 52,
2348 },
2349 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2350 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2351};
2352
dd015002
HS		 2353static const struct drm_display_mode lg_lb070wv8_mode = {
2354 .clock = 33246,
2355 .hdisplay = 800,
2356 .hsync_start = 800 + 88,
2357 .hsync_end = 800 + 88 + 80,
2358 .htotal = 800 + 88 + 80 + 88,
2359 .vdisplay = 480,
2360 .vsync_start = 480 + 10,
2361 .vsync_end = 480 + 10 + 25,
2362 .vtotal = 480 + 10 + 25 + 10,
dd015002
HS		 2363};
2364
2365static const struct panel_desc lg_lb070wv8 = {
2366 .modes = &lg_lb070wv8_mode,
2367 .num_modes = 1,
2368 .bpc = 16,
2369 .size = {
2370 .width = 151,
2371 .height = 91,
2372 },
2373 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2374 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 2375};
2376
c5ece402
YY		 2377static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2378 .clock = 200000,
2379 .hdisplay = 1536,
2380 .hsync_start = 1536 + 12,
2381 .hsync_end = 1536 + 12 + 16,
2382 .htotal = 1536 + 12 + 16 + 48,
2383 .vdisplay = 2048,
2384 .vsync_start = 2048 + 8,
2385 .vsync_end = 2048 + 8 + 4,
2386 .vtotal = 2048 + 8 + 4 + 8,
c5ece402
YY		 2387 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2388};
2389
2390static const struct panel_desc lg_lp079qx1_sp0v = {
2391 .modes = &lg_lp079qx1_sp0v_mode,
2392 .num_modes = 1,
2393 .size = {
2394 .width = 129,
2395 .height = 171,
2396 },
2397};
2398
0355dde2
YY		 2399static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2400 .clock = 205210,
2401 .hdisplay = 2048,
2402 .hsync_start = 2048 + 150,
2403 .hsync_end = 2048 + 150 + 5,
2404 .htotal = 2048 + 150 + 5 + 5,
2405 .vdisplay = 1536,
2406 .vsync_start = 1536 + 3,
2407 .vsync_end = 1536 + 3 + 1,
2408 .vtotal = 1536 + 3 + 1 + 9,
0355dde2
YY		 2409};
2410
2411static const struct panel_desc lg_lp097qx1_spa1 = {
2412 .modes = &lg_lp097qx1_spa1_mode,
2413 .num_modes = 1,
2414 .size = {
2415 .width = 208,
2416 .height = 147,
2417 },
2418};
2419
690d8fa7
JS		 2420static const struct drm_display_mode lg_lp120up1_mode = {
2421 .clock = 162300,
2422 .hdisplay = 1920,
2423 .hsync_start = 1920 + 40,
2424 .hsync_end = 1920 + 40 + 40,
2425 .htotal = 1920 + 40 + 40+ 80,
2426 .vdisplay = 1280,
2427 .vsync_start = 1280 + 4,
2428 .vsync_end = 1280 + 4 + 4,
2429 .vtotal = 1280 + 4 + 4 + 12,
690d8fa7
JS		 2430};
2431
2432static const struct panel_desc lg_lp120up1 = {
2433 .modes = &lg_lp120up1_mode,
2434 .num_modes = 1,
2435 .bpc = 8,
2436 .size = {
2437 .width = 267,
2438 .height = 183,
2439 },
d53139b3 2440 .connector_type = DRM_MODE_CONNECTOR_eDP,
690d8fa7
JS		 2441};
2442
ec7c5653
TR		 2443static const struct drm_display_mode lg_lp129qe_mode = {
2444 .clock = 285250,
2445 .hdisplay = 2560,
2446 .hsync_start = 2560 + 48,
2447 .hsync_end = 2560 + 48 + 32,
2448 .htotal = 2560 + 48 + 32 + 80,
2449 .vdisplay = 1700,
2450 .vsync_start = 1700 + 3,
2451 .vsync_end = 1700 + 3 + 10,
2452 .vtotal = 1700 + 3 + 10 + 36,
ec7c5653
TR		 2453};
2454
2455static const struct panel_desc lg_lp129qe = {
2456 .modes = &lg_lp129qe_mode,
2457 .num_modes = 1,
0208d511 2458 .bpc = 8,
ec7c5653
TR		 2459 .size = {
2460 .width = 272,
2461 .height = 181,
2462 },
2463};
2464
5728fe7f
MZ		 2465static const struct display_timing logictechno_lt161010_2nh_timing = {
2466 .pixelclock = { 26400000, 33300000, 46800000 },
2467 .hactive = { 800, 800, 800 },
2468 .hfront_porch = { 16, 210, 354 },
2469 .hback_porch = { 46, 46, 46 },
2470 .hsync_len = { 1, 20, 40 },
2471 .vactive = { 480, 480, 480 },
2472 .vfront_porch = { 7, 22, 147 },
2473 .vback_porch = { 23, 23, 23 },
2474 .vsync_len = { 1, 10, 20 },
2475 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2476 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2477 DISPLAY_FLAGS_SYNC_POSEDGE,
2478};
2479
2480static const struct panel_desc logictechno_lt161010_2nh = {
2481 .timings = &logictechno_lt161010_2nh_timing,
2482 .num_timings = 1,
2483 .size = {
2484 .width = 154,
2485 .height = 86,
2486 },
2487 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2488 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2489 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2490 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2491 .connector_type = DRM_MODE_CONNECTOR_DPI,
2492};
2493
2494static const struct display_timing logictechno_lt170410_2whc_timing = {
2495 .pixelclock = { 68900000, 71100000, 73400000 },
2496 .hactive = { 1280, 1280, 1280 },
2497 .hfront_porch = { 23, 60, 71 },
2498 .hback_porch = { 23, 60, 71 },
2499 .hsync_len = { 15, 40, 47 },
2500 .vactive = { 800, 800, 800 },
2501 .vfront_porch = { 5, 7, 10 },
2502 .vback_porch = { 5, 7, 10 },
2503 .vsync_len = { 6, 9, 12 },
2504 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2505 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2506 DISPLAY_FLAGS_SYNC_POSEDGE,
2507};
2508
2509static const struct panel_desc logictechno_lt170410_2whc = {
2510 .timings = &logictechno_lt170410_2whc_timing,
2511 .num_timings = 1,
2512 .size = {
2513 .width = 217,
2514 .height = 136,
2515 },
2516 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2517 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
5728fe7f
MZ		 2518 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2519};
2520
65c766ca
LM		 2521static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2522 .clock = 30400,
2523 .hdisplay = 800,
2524 .hsync_start = 800 + 0,
2525 .hsync_end = 800 + 1,
2526 .htotal = 800 + 0 + 1 + 160,
2527 .vdisplay = 480,
2528 .vsync_start = 480 + 0,
2529 .vsync_end = 480 + 48 + 1,
2530 .vtotal = 480 + 48 + 1 + 0,
65c766ca
LM		 2531 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2532};
2533
0d35408a 2534static const struct drm_display_mode logicpd_type_28_mode = {
f873c5d8 2535 .clock = 9107,
0d35408a
AF		 2536 .hdisplay = 480,
2537 .hsync_start = 480 + 3,
2538 .hsync_end = 480 + 3 + 42,
2539 .htotal = 480 + 3 + 42 + 2,
2540
2541 .vdisplay = 272,
2542 .vsync_start = 272 + 2,
2543 .vsync_end = 272 + 2 + 11,
2544 .vtotal = 272 + 2 + 11 + 3,
0d35408a
AF		 2545 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2546};
2547
2548static const struct panel_desc logicpd_type_28 = {
2549 .modes = &logicpd_type_28_mode,
2550 .num_modes = 1,
2551 .bpc = 8,
2552 .size = {
2553 .width = 105,
2554 .height = 67,
2555 },
2556 .delay = {
2557 .prepare = 200,
2558 .enable = 200,
2559 .unprepare = 200,
2560 .disable = 200,
2561 },
2562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2564 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2565};
2566
65c766ca
LM		 2567static const struct panel_desc mitsubishi_aa070mc01 = {
2568 .modes = &mitsubishi_aa070mc01_mode,
2569 .num_modes = 1,
2570 .bpc = 8,
2571 .size = {
2572 .width = 152,
2573 .height = 91,
2574 },
2575
2576 .delay = {
2577 .enable = 200,
2578 .unprepare = 200,
2579 .disable = 400,
2580 },
2581 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2582 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 2583 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2584};
2585
01bacc13
LS		 2586static const struct display_timing nec_nl12880bc20_05_timing = {
2587 .pixelclock = { 67000000, 71000000, 75000000 },
2588 .hactive = { 1280, 1280, 1280 },
2589 .hfront_porch = { 2, 30, 30 },
2590 .hback_porch = { 6, 100, 100 },
2591 .hsync_len = { 2, 30, 30 },
2592 .vactive = { 800, 800, 800 },
2593 .vfront_porch = { 5, 5, 5 },
2594 .vback_porch = { 11, 11, 11 },
2595 .vsync_len = { 7, 7, 7 },
2596};
2597
2598static const struct panel_desc nec_nl12880bc20_05 = {
2599 .timings = &nec_nl12880bc20_05_timing,
2600 .num_timings = 1,
2601 .bpc = 8,
2602 .size = {
2603 .width = 261,
2604 .height = 163,
2605 },
2606 .delay = {
2607 .enable = 50,
2608 .disable = 50,
2609 },
2610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2611 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 2612};
2613
c6e87f91 2614static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2615 .clock = 10870,
2616 .hdisplay = 480,
2617 .hsync_start = 480 + 2,
2618 .hsync_end = 480 + 2 + 41,
2619 .htotal = 480 + 2 + 41 + 2,
2620 .vdisplay = 272,
2621 .vsync_start = 272 + 2,
2622 .vsync_end = 272 + 2 + 4,
2623 .vtotal = 272 + 2 + 4 + 2,
4bc390c6 2624 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 2625};
2626
2627static const struct panel_desc nec_nl4827hc19_05b = {
2628 .modes = &nec_nl4827hc19_05b_mode,
2629 .num_modes = 1,
2630 .bpc = 8,
2631 .size = {
2632 .width = 95,
2633 .height = 54,
2634 },
2c80661d 2635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2636 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 2637};
2638
e6c2f066
MR		 2639static const struct drm_display_mode netron_dy_e231732_mode = {
2640 .clock = 66000,
2641 .hdisplay = 1024,
2642 .hsync_start = 1024 + 160,
2643 .hsync_end = 1024 + 160 + 70,
2644 .htotal = 1024 + 160 + 70 + 90,
2645 .vdisplay = 600,
2646 .vsync_start = 600 + 127,
2647 .vsync_end = 600 + 127 + 20,
2648 .vtotal = 600 + 127 + 20 + 3,
e6c2f066
MR		 2649};
2650
2651static const struct panel_desc netron_dy_e231732 = {
2652 .modes = &netron_dy_e231732_mode,
2653 .num_modes = 1,
2654 .size = {
2655 .width = 154,
2656 .height = 87,
2657 },
2658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2659};
2660
258145ea
VK		 2661static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
2662 {
2663 .clock = 138500,
2664 .hdisplay = 1920,
2665 .hsync_start = 1920 + 48,
2666 .hsync_end = 1920 + 48 + 32,
2667 .htotal = 1920 + 48 + 32 + 80,
2668 .vdisplay = 1080,
2669 .vsync_start = 1080 + 3,
2670 .vsync_end = 1080 + 3 + 5,
2671 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 2672 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2673 }, {
2674 .clock = 110920,
2675 .hdisplay = 1920,
2676 .hsync_start = 1920 + 48,
2677 .hsync_end = 1920 + 48 + 32,
2678 .htotal = 1920 + 48 + 32 + 80,
2679 .vdisplay = 1080,
2680 .vsync_start = 1080 + 3,
2681 .vsync_end = 1080 + 3 + 5,
2682 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 2683 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2684 }
2685};
2686
2687static const struct panel_desc neweast_wjfh116008a = {
2688 .modes = neweast_wjfh116008a_modes,
2689 .num_modes = 2,
2690 .bpc = 6,
2691 .size = {
2692 .width = 260,
2693 .height = 150,
2694 },
2695 .delay = {
2696 .prepare = 110,
2697 .enable = 20,
2698 .unprepare = 500,
2699 },
2700 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2701 .connector_type = DRM_MODE_CONNECTOR_eDP,
2702};
2703
3b39ad7a
TV		 2704static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2705 .clock = 9000,
2706 .hdisplay = 480,
2707 .hsync_start = 480 + 2,
2708 .hsync_end = 480 + 2 + 41,
2709 .htotal = 480 + 2 + 41 + 2,
2710 .vdisplay = 272,
2711 .vsync_start = 272 + 2,
2712 .vsync_end = 272 + 2 + 10,
2713 .vtotal = 272 + 2 + 10 + 2,
3b39ad7a
TV		 2714 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2715};
2716
2717static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2718 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2719 .num_modes = 1,
2720 .bpc = 8,
2721 .size = {
2722 .width = 95,
2723 .height = 54,
2724 },
2725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 2726 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2727 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3b39ad7a
TV		 2728};
2729
4177fa66
LS		 2730static const struct display_timing nlt_nl192108ac18_02d_timing = {
2731 .pixelclock = { 130000000, 148350000, 163000000 },
2732 .hactive = { 1920, 1920, 1920 },
2733 .hfront_porch = { 80, 100, 100 },
2734 .hback_porch = { 100, 120, 120 },
2735 .hsync_len = { 50, 60, 60 },
2736 .vactive = { 1080, 1080, 1080 },
2737 .vfront_porch = { 12, 30, 30 },
2738 .vback_porch = { 4, 10, 10 },
2739 .vsync_len = { 4, 5, 5 },
2740};
2741
2742static const struct panel_desc nlt_nl192108ac18_02d = {
2743 .timings = &nlt_nl192108ac18_02d_timing,
2744 .num_timings = 1,
2745 .bpc = 8,
2746 .size = {
2747 .width = 344,
2748 .height = 194,
2749 },
2750 .delay = {
2751 .unprepare = 500,
2752 },
2753 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2754 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 2755};
2756
05ec0e45
FL		 2757static const struct drm_display_mode nvd_9128_mode = {
2758 .clock = 29500,
2759 .hdisplay = 800,
2760 .hsync_start = 800 + 130,
2761 .hsync_end = 800 + 130 + 98,
2762 .htotal = 800 + 0 + 130 + 98,
2763 .vdisplay = 480,
2764 .vsync_start = 480 + 10,
2765 .vsync_end = 480 + 10 + 50,
2766 .vtotal = 480 + 0 + 10 + 50,
2767};
2768
2769static const struct panel_desc nvd_9128 = {
2770 .modes = &nvd_9128_mode,
2771 .num_modes = 1,
2772 .bpc = 8,
2773 .size = {
2774 .width = 156,
2775 .height = 88,
2776 },
2777 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2778 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 2779};
2780
a99fb626
GB		 2781static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2782 .pixelclock = { 30000000, 30000000, 40000000 },
2783 .hactive = { 800, 800, 800 },
2784 .hfront_porch = { 40, 40, 40 },
2785 .hback_porch = { 40, 40, 40 },
2786 .hsync_len = { 1, 48, 48 },
2787 .vactive = { 480, 480, 480 },
2788 .vfront_porch = { 13, 13, 13 },
2789 .vback_porch = { 29, 29, 29 },
2790 .vsync_len = { 3, 3, 3 },
2791 .flags = DISPLAY_FLAGS_DE_HIGH,
2792};
2793
2794static const struct panel_desc okaya_rs800480t_7x0gp = {
2795 .timings = &okaya_rs800480t_7x0gp_timing,
2796 .num_timings = 1,
2797 .bpc = 6,
2798 .size = {
2799 .width = 154,
2800 .height = 87,
2801 },
2802 .delay = {
2803 .prepare = 41,
2804 .enable = 50,
2805 .unprepare = 41,
2806 .disable = 50,
2807 },
2808 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2809};
2810
cf5c9e6d
MR		 2811static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2812 .clock = 9000,
2813 .hdisplay = 480,
2814 .hsync_start = 480 + 5,
2815 .hsync_end = 480 + 5 + 30,
2816 .htotal = 480 + 5 + 30 + 10,
2817 .vdisplay = 272,
2818 .vsync_start = 272 + 8,
2819 .vsync_end = 272 + 8 + 5,
2820 .vtotal = 272 + 8 + 5 + 3,
cf5c9e6d
MR		 2821};
2822
2823static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2824 .modes = &olimex_lcd_olinuxino_43ts_mode,
2825 .num_modes = 1,
2826 .size = {
30c6d7ab
JL		 2827 .width = 95,
2828 .height = 54,
cf5c9e6d 2829 },
5c2a7c6b 2830 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 2831};
2832
e8b6f561
EA		 2833/*
2834 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2835 * pixel clocks, but this is the timing that was being used in the Adafruit
2836 * installation instructions.
2837 */
2838static const struct drm_display_mode ontat_yx700wv03_mode = {
2839 .clock = 29500,
2840 .hdisplay = 800,
2841 .hsync_start = 824,
2842 .hsync_end = 896,
2843 .htotal = 992,
2844 .vdisplay = 480,
2845 .vsync_start = 483,
2846 .vsync_end = 493,
2847 .vtotal = 500,
e8b6f561
EA		 2848 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2849};
2850
2851/*
2852 * Specification at:
2853 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2854 */
2855static const struct panel_desc ontat_yx700wv03 = {
2856 .modes = &ontat_yx700wv03_mode,
2857 .num_modes = 1,
2858 .bpc = 8,
2859 .size = {
2860 .width = 154,
2861 .height = 83,
2862 },
5651e5e0 2863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 2864};
2865
9c31dcb6 2866static const struct drm_display_mode ortustech_com37h3m_mode = {
855e764d 2867 .clock = 22230,
9c31dcb6 2868 .hdisplay = 480,
855e764d
NS		 2869 .hsync_start = 480 + 40,
2870 .hsync_end = 480 + 40 + 10,
2871 .htotal = 480 + 40 + 10 + 40,
9c31dcb6
NS		 2872 .vdisplay = 640,
2873 .vsync_start = 640 + 4,
855e764d
NS		 2874 .vsync_end = 640 + 4 + 2,
2875 .vtotal = 640 + 4 + 2 + 4,
9c31dcb6
NS		 2876 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2877};
2878
2879static const struct panel_desc ortustech_com37h3m = {
2880 .modes = &ortustech_com37h3m_mode,
2881 .num_modes = 1,
2882 .bpc = 8,
2883 .size = {
2884 .width = 56, /* 56.16mm */
2885 .height = 75, /* 74.88mm */
2886 },
2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2888 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2889 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2890};
2891
725c9d40
PZ		 2892static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2893 .clock = 25000,
2894 .hdisplay = 480,
2895 .hsync_start = 480 + 10,
2896 .hsync_end = 480 + 10 + 10,
2897 .htotal = 480 + 10 + 10 + 15,
2898 .vdisplay = 800,
2899 .vsync_start = 800 + 3,
2900 .vsync_end = 800 + 3 + 3,
2901 .vtotal = 800 + 3 + 3 + 3,
725c9d40
PZ		 2902};
2903
2904static const struct panel_desc ortustech_com43h4m85ulc = {
2905 .modes = &ortustech_com43h4m85ulc_mode,
2906 .num_modes = 1,
2907 .bpc = 8,
2908 .size = {
2909 .width = 56,
2910 .height = 93,
2911 },
2912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2ccedf46 2914 .connector_type = DRM_MODE_CONNECTOR_DPI,
725c9d40
PZ		 2915};
2916
163f7a35
LP		 2917static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2918 .clock = 33000,
2919 .hdisplay = 800,
2920 .hsync_start = 800 + 210,
2921 .hsync_end = 800 + 210 + 30,
2922 .htotal = 800 + 210 + 30 + 16,
2923 .vdisplay = 480,
2924 .vsync_start = 480 + 22,
2925 .vsync_end = 480 + 22 + 13,
2926 .vtotal = 480 + 22 + 13 + 10,
163f7a35
LP		 2927 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2928};
2929
2930static const struct panel_desc osddisplays_osd070t1718_19ts = {
2931 .modes = &osddisplays_osd070t1718_19ts_mode,
2932 .num_modes = 1,
2933 .bpc = 8,
2934 .size = {
2935 .width = 152,
2936 .height = 91,
2937 },
2938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
fb0629ee
TV		 2939 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2940 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
a793f0ee 2941 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 2942};
2943
4ba3e563
EH		 2944static const struct drm_display_mode pda_91_00156_a0_mode = {
2945 .clock = 33300,
2946 .hdisplay = 800,
2947 .hsync_start = 800 + 1,
2948 .hsync_end = 800 + 1 + 64,
2949 .htotal = 800 + 1 + 64 + 64,
2950 .vdisplay = 480,
2951 .vsync_start = 480 + 1,
2952 .vsync_end = 480 + 1 + 23,
2953 .vtotal = 480 + 1 + 23 + 22,
4ba3e563
EH		 2954};
2955
2956static const struct panel_desc pda_91_00156_a0 = {
2957 .modes = &pda_91_00156_a0_mode,
2958 .num_modes = 1,
2959 .size = {
2960 .width = 152,
2961 .height = 91,
2962 },
2963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2964};
2965
2966
d2a6f0f5
JW		 2967static const struct drm_display_mode qd43003c0_40_mode = {
2968 .clock = 9000,
2969 .hdisplay = 480,
2970 .hsync_start = 480 + 8,
2971 .hsync_end = 480 + 8 + 4,
2972 .htotal = 480 + 8 + 4 + 39,
2973 .vdisplay = 272,
2974 .vsync_start = 272 + 4,
2975 .vsync_end = 272 + 4 + 10,
2976 .vtotal = 272 + 4 + 10 + 2,
d2a6f0f5
JW		 2977};
2978
2979static const struct panel_desc qd43003c0_40 = {
2980 .modes = &qd43003c0_40_mode,
2981 .num_modes = 1,
2982 .bpc = 8,
2983 .size = {
2984 .width = 95,
2985 .height = 53,
2986 },
2987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2988};
2989
23167fa9
JT		 2990static const struct display_timing rocktech_rk070er9427_timing = {
2991 .pixelclock = { 26400000, 33300000, 46800000 },
2992 .hactive = { 800, 800, 800 },
2993 .hfront_porch = { 16, 210, 354 },
2994 .hback_porch = { 46, 46, 46 },
2995 .hsync_len = { 1, 1, 1 },
2996 .vactive = { 480, 480, 480 },
2997 .vfront_porch = { 7, 22, 147 },
2998 .vback_porch = { 23, 23, 23 },
2999 .vsync_len = { 1, 1, 1 },
3000 .flags = DISPLAY_FLAGS_DE_HIGH,
3001};
3002
3003static const struct panel_desc rocktech_rk070er9427 = {
3004 .timings = &rocktech_rk070er9427_timing,
3005 .num_timings = 1,
3006 .bpc = 6,
3007 .size = {
3008 .width = 154,
3009 .height = 86,
3010 },
3011 .delay = {
3012 .prepare = 41,
3013 .enable = 50,
3014 .unprepare = 41,
3015 .disable = 50,
3016 },
3017 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3018};
3019
f305047b
JS		 3020static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3021 .clock = 71100,
3022 .hdisplay = 1280,
3023 .hsync_start = 1280 + 48,
3024 .hsync_end = 1280 + 48 + 32,
3025 .htotal = 1280 + 48 + 32 + 80,
3026 .vdisplay = 800,
3027 .vsync_start = 800 + 2,
3028 .vsync_end = 800 + 2 + 5,
3029 .vtotal = 800 + 2 + 5 + 16,
f305047b
JS		 3030};
3031
3032static const struct panel_desc rocktech_rk101ii01d_ct = {
3033 .modes = &rocktech_rk101ii01d_ct_mode,
3034 .num_modes = 1,
3035 .size = {
3036 .width = 217,
3037 .height = 136,
3038 },
3039 .delay = {
3040 .prepare = 50,
3041 .disable = 50,
3042 },
3043 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3044 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3045 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3046};
3047
0330eaf3
YY		 3048static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3049 .clock = 271560,
3050 .hdisplay = 2560,
3051 .hsync_start = 2560 + 48,
3052 .hsync_end = 2560 + 48 + 32,
3053 .htotal = 2560 + 48 + 32 + 80,
3054 .vdisplay = 1600,
3055 .vsync_start = 1600 + 2,
3056 .vsync_end = 1600 + 2 + 5,
3057 .vtotal = 1600 + 2 + 5 + 57,
0330eaf3
YY		 3058};
3059
3060static const struct panel_desc samsung_lsn122dl01_c01 = {
3061 .modes = &samsung_lsn122dl01_c01_mode,
3062 .num_modes = 1,
3063 .size = {
3064 .width = 263,
3065 .height = 164,
3066 },
3067};
3068
6d54e3d2
MD		 3069static const struct drm_display_mode samsung_ltn101nt05_mode = {
3070 .clock = 54030,
3071 .hdisplay = 1024,
3072 .hsync_start = 1024 + 24,
3073 .hsync_end = 1024 + 24 + 136,
3074 .htotal = 1024 + 24 + 136 + 160,
3075 .vdisplay = 600,
3076 .vsync_start = 600 + 3,
3077 .vsync_end = 600 + 3 + 6,
3078 .vtotal = 600 + 3 + 6 + 61,
6d54e3d2
MD		 3079};
3080
3081static const struct panel_desc samsung_ltn101nt05 = {
3082 .modes = &samsung_ltn101nt05_mode,
3083 .num_modes = 1,
0208d511 3084 .bpc = 6,
6d54e3d2 3085 .size = {
81598846
TR		 3086 .width = 223,
3087 .height = 125,
6d54e3d2 3088 },
85560829 3089 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 3090 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 3091 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6d54e3d2
MD		 3092};
3093
0c934306
SM		 3094static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3095 .clock = 76300,
3096 .hdisplay = 1366,
3097 .hsync_start = 1366 + 64,
3098 .hsync_end = 1366 + 64 + 48,
3099 .htotal = 1366 + 64 + 48 + 128,
3100 .vdisplay = 768,
3101 .vsync_start = 768 + 2,
3102 .vsync_end = 768 + 2 + 5,
3103 .vtotal = 768 + 2 + 5 + 17,
0c934306
SM		 3104};
3105
3106static const struct panel_desc samsung_ltn140at29_301 = {
3107 .modes = &samsung_ltn140at29_301_mode,
3108 .num_modes = 1,
3109 .bpc = 6,
3110 .size = {
3111 .width = 320,
3112 .height = 187,
3113 },
3114};
3115
44c58c52
MR		 3116static const struct display_timing satoz_sat050at40h12r2_timing = {
3117 .pixelclock = {33300000, 33300000, 50000000},
3118 .hactive = {800, 800, 800},
3119 .hfront_porch = {16, 210, 354},
3120 .hback_porch = {46, 46, 46},
3121 .hsync_len = {1, 1, 40},
3122 .vactive = {480, 480, 480},
3123 .vfront_porch = {7, 22, 147},
3124 .vback_porch = {23, 23, 23},
3125 .vsync_len = {1, 1, 20},
3126};
3127
3128static const struct panel_desc satoz_sat050at40h12r2 = {
3129 .timings = &satoz_sat050at40h12r2_timing,
3130 .num_timings = 1,
3131 .bpc = 8,
3132 .size = {
3133 .width = 108,
3134 .height = 65,
3135 },
34ca6b53 3136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
44c58c52
MR		 3137 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3138};
3139
cd5e1cbe
JH		 3140static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3141 .clock = 168480,
3142 .hdisplay = 1920,
3143 .hsync_start = 1920 + 48,
3144 .hsync_end = 1920 + 48 + 32,
3145 .htotal = 1920 + 48 + 32 + 80,
3146 .vdisplay = 1280,
3147 .vsync_start = 1280 + 3,
3148 .vsync_end = 1280 + 3 + 10,
3149 .vtotal = 1280 + 3 + 10 + 57,
cd5e1cbe
JH		 3150 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3151};
3152
3153static const struct panel_desc sharp_ld_d5116z01b = {
3154 .modes = &sharp_ld_d5116z01b_mode,
3155 .num_modes = 1,
3156 .bpc = 8,
3157 .size = {
3158 .width = 260,
3159 .height = 120,
3160 },
3161 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3162 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3163};
3164
dda0e4bd
NS		 3165static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3166 .clock = 33260,
3167 .hdisplay = 800,
3168 .hsync_start = 800 + 64,
3169 .hsync_end = 800 + 64 + 128,
3170 .htotal = 800 + 64 + 128 + 64,
3171 .vdisplay = 480,
3172 .vsync_start = 480 + 8,
3173 .vsync_end = 480 + 8 + 2,
3174 .vtotal = 480 + 8 + 2 + 35,
dda0e4bd
NS		 3175 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3176};
3177
3178static const struct panel_desc sharp_lq070y3dg3b = {
3179 .modes = &sharp_lq070y3dg3b_mode,
3180 .num_modes = 1,
3181 .bpc = 8,
3182 .size = {
3183 .width = 152, /* 152.4mm */
3184 .height = 91, /* 91.4mm */
3185 },
3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3187 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
3188 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3189};
3190
03e3ec9a
VZ		 3191static const struct drm_display_mode sharp_lq035q7db03_mode = {
3192 .clock = 5500,
3193 .hdisplay = 240,
3194 .hsync_start = 240 + 16,
3195 .hsync_end = 240 + 16 + 7,
3196 .htotal = 240 + 16 + 7 + 5,
3197 .vdisplay = 320,
3198 .vsync_start = 320 + 9,
3199 .vsync_end = 320 + 9 + 1,
3200 .vtotal = 320 + 9 + 1 + 7,
03e3ec9a
VZ		 3201};
3202
3203static const struct panel_desc sharp_lq035q7db03 = {
3204 .modes = &sharp_lq035q7db03_mode,
3205 .num_modes = 1,
3206 .bpc = 6,
3207 .size = {
3208 .width = 54,
3209 .height = 72,
3210 },
3211 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3212};
3213
592aa02b
JC		 3214static const struct display_timing sharp_lq101k1ly04_timing = {
3215 .pixelclock = { 60000000, 65000000, 80000000 },
3216 .hactive = { 1280, 1280, 1280 },
3217 .hfront_porch = { 20, 20, 20 },
3218 .hback_porch = { 20, 20, 20 },
3219 .hsync_len = { 10, 10, 10 },
3220 .vactive = { 800, 800, 800 },
3221 .vfront_porch = { 4, 4, 4 },
3222 .vback_porch = { 4, 4, 4 },
3223 .vsync_len = { 4, 4, 4 },
3224 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3225};
3226
3227static const struct panel_desc sharp_lq101k1ly04 = {
3228 .timings = &sharp_lq101k1ly04_timing,
3229 .num_timings = 1,
3230 .bpc = 8,
3231 .size = {
3232 .width = 217,
3233 .height = 136,
3234 },
3235 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 3236 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 3237};
3238
9f7bae2d
SP		 3239static const struct display_timing sharp_lq123p1jx31_timing = {
3240 .pixelclock = { 252750000, 252750000, 266604720 },
3241 .hactive = { 2400, 2400, 2400 },
3242 .hfront_porch = { 48, 48, 48 },
3243 .hback_porch = { 80, 80, 84 },
3244 .hsync_len = { 32, 32, 32 },
3245 .vactive = { 1600, 1600, 1600 },
3246 .vfront_porch = { 3, 3, 3 },
3247 .vback_porch = { 33, 33, 120 },
3248 .vsync_len = { 10, 10, 10 },
3249 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 3250};
3251
3252static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 3253 .timings = &sharp_lq123p1jx31_timing,
3254 .num_timings = 1,
5466a631 3255 .bpc = 8,
739c7de9
YY		 3256 .size = {
3257 .width = 259,
3258 .height = 173,
3259 },
a42f6e3f
YY		 3260 .delay = {
3261 .prepare = 110,
3262 .enable = 50,
3263 .unprepare = 550,
3264 },
739c7de9
YY		 3265};
3266
f1bd37f3
PC		 3267static const struct display_timing sharp_ls020b1dd01d_timing = {
3268 .pixelclock = { 2000000, 4200000, 5000000 },
3269 .hactive = { 240, 240, 240 },
3270 .hfront_porch = { 66, 66, 66 },
3271 .hback_porch = { 1, 1, 1 },
3272 .hsync_len = { 1, 1, 1 },
3273 .vactive = { 160, 160, 160 },
3274 .vfront_porch = { 52, 52, 52 },
3275 .vback_porch = { 6, 6, 6 },
3276 .vsync_len = { 10, 10, 10 },
3277 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
3278};
3279
3280static const struct panel_desc sharp_ls020b1dd01d = {
3281 .timings = &sharp_ls020b1dd01d_timing,
3282 .num_timings = 1,
3283 .bpc = 6,
3284 .size = {
3285 .width = 42,
3286 .height = 28,
3287 },
3288 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3289 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3290 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
3291 | DRM_BUS_FLAG_SHARP_SIGNALS,
3292};
3293
9c6615bc
BB		 3294static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3295 .clock = 33300,
3296 .hdisplay = 800,
3297 .hsync_start = 800 + 1,
3298 .hsync_end = 800 + 1 + 64,
3299 .htotal = 800 + 1 + 64 + 64,
3300 .vdisplay = 480,
3301 .vsync_start = 480 + 1,
3302 .vsync_end = 480 + 1 + 23,
3303 .vtotal = 480 + 1 + 23 + 22,
9c6615bc
BB		 3304};
3305
3306static const struct panel_desc shelly_sca07010_bfn_lnn = {
3307 .modes = &shelly_sca07010_bfn_lnn_mode,
3308 .num_modes = 1,
3309 .size = {
3310 .width = 152,
3311 .height = 91,
3312 },
3313 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3314};
3315
105235e4
PR		 3316static const struct drm_display_mode starry_kr070pe2t_mode = {
3317 .clock = 33000,
3318 .hdisplay = 800,
3319 .hsync_start = 800 + 209,
3320 .hsync_end = 800 + 209 + 1,
3321 .htotal = 800 + 209 + 1 + 45,
3322 .vdisplay = 480,
3323 .vsync_start = 480 + 22,
3324 .vsync_end = 480 + 22 + 1,
3325 .vtotal = 480 + 22 + 1 + 22,
105235e4
PR		 3326};
3327
3328static const struct panel_desc starry_kr070pe2t = {
3329 .modes = &starry_kr070pe2t_mode,
3330 .num_modes = 1,
3331 .bpc = 8,
3332 .size = {
3333 .width = 152,
3334 .height = 86,
3335 },
3336 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3337 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
41fad307 3338 .connector_type = DRM_MODE_CONNECTOR_DPI,
105235e4
PR		 3339};
3340
9bb34c4c
DA		 3341static const struct drm_display_mode starry_kr122ea0sra_mode = {
3342 .clock = 147000,
3343 .hdisplay = 1920,
3344 .hsync_start = 1920 + 16,
3345 .hsync_end = 1920 + 16 + 16,
3346 .htotal = 1920 + 16 + 16 + 32,
3347 .vdisplay = 1200,
3348 .vsync_start = 1200 + 15,
3349 .vsync_end = 1200 + 15 + 2,
3350 .vtotal = 1200 + 15 + 2 + 18,
9bb34c4c
DA		 3351 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3352};
3353
3354static const struct panel_desc starry_kr122ea0sra = {
3355 .modes = &starry_kr122ea0sra_mode,
3356 .num_modes = 1,
3357 .size = {
3358 .width = 263,
3359 .height = 164,
3360 },
c46b924b
BN		 3361 .delay = {
3362 .prepare = 10 + 200,
3363 .enable = 50,
3364 .unprepare = 10 + 500,
3365 },
9bb34c4c
DA		 3366};
3367
42161531
JS		 3368static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3369 .clock = 30000,
3370 .hdisplay = 800,
3371 .hsync_start = 800 + 39,
3372 .hsync_end = 800 + 39 + 47,
3373 .htotal = 800 + 39 + 47 + 39,
3374 .vdisplay = 480,
3375 .vsync_start = 480 + 13,
3376 .vsync_end = 480 + 13 + 2,
3377 .vtotal = 480 + 13 + 2 + 29,
42161531
JS		 3378};
3379
3380static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3381 .modes = &tfc_s9700rtwv43tr_01b_mode,
3382 .num_modes = 1,
3383 .bpc = 8,
3384 .size = {
3385 .width = 155,
3386 .height = 90,
3387 },
3388 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3389 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3390};
3391
adb973ef
GB		 3392static const struct display_timing tianma_tm070jdhg30_timing = {
3393 .pixelclock = { 62600000, 68200000, 78100000 },
3394 .hactive = { 1280, 1280, 1280 },
3395 .hfront_porch = { 15, 64, 159 },
3396 .hback_porch = { 5, 5, 5 },
3397 .hsync_len = { 1, 1, 256 },
3398 .vactive = { 800, 800, 800 },
3399 .vfront_porch = { 3, 40, 99 },
3400 .vback_porch = { 2, 2, 2 },
3401 .vsync_len = { 1, 1, 128 },
3402 .flags = DISPLAY_FLAGS_DE_HIGH,
3403};
3404
3405static const struct panel_desc tianma_tm070jdhg30 = {
3406 .timings = &tianma_tm070jdhg30_timing,
3407 .num_timings = 1,
3408 .bpc = 8,
3409 .size = {
3410 .width = 151,
3411 .height = 95,
3412 },
3413 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3414 .connector_type = DRM_MODE_CONNECTOR_LVDS,
adb973ef
GB		 3415};
3416
b3bfcdf8
MM		 3417static const struct panel_desc tianma_tm070jvhg33 = {
3418 .timings = &tianma_tm070jdhg30_timing,
3419 .num_timings = 1,
3420 .bpc = 8,
3421 .size = {
3422 .width = 150,
3423 .height = 94,
3424 },
3425 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3426 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3427};
3428
870a0b12
LM		 3429static const struct display_timing tianma_tm070rvhg71_timing = {
3430 .pixelclock = { 27700000, 29200000, 39600000 },
3431 .hactive = { 800, 800, 800 },
3432 .hfront_porch = { 12, 40, 212 },
3433 .hback_porch = { 88, 88, 88 },
3434 .hsync_len = { 1, 1, 40 },
3435 .vactive = { 480, 480, 480 },
3436 .vfront_porch = { 1, 13, 88 },
3437 .vback_porch = { 32, 32, 32 },
3438 .vsync_len = { 1, 1, 3 },
3439 .flags = DISPLAY_FLAGS_DE_HIGH,
3440};
3441
3442static const struct panel_desc tianma_tm070rvhg71 = {
3443 .timings = &tianma_tm070rvhg71_timing,
3444 .num_timings = 1,
3445 .bpc = 8,
3446 .size = {
3447 .width = 154,
3448 .height = 86,
3449 },
3450 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3451 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 3452};
3453
d8a0d6a3
LW		 3454static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3455 {
3456 .clock = 10000,
3457 .hdisplay = 320,
3458 .hsync_start = 320 + 50,
3459 .hsync_end = 320 + 50 + 6,
3460 .htotal = 320 + 50 + 6 + 38,
3461 .vdisplay = 240,
3462 .vsync_start = 240 + 3,
3463 .vsync_end = 240 + 3 + 1,
3464 .vtotal = 240 + 3 + 1 + 17,
d8a0d6a3
LW		 3465 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3466 },
3467};
3468
3469static const struct panel_desc ti_nspire_cx_lcd_panel = {
3470 .modes = ti_nspire_cx_lcd_mode,
3471 .num_modes = 1,
3472 .bpc = 8,
3473 .size = {
3474 .width = 65,
3475 .height = 49,
3476 },
3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3478 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
3479};
3480
3481static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3482 {
3483 .clock = 10000,
3484 .hdisplay = 320,
3485 .hsync_start = 320 + 6,
3486 .hsync_end = 320 + 6 + 6,
3487 .htotal = 320 + 6 + 6 + 6,
3488 .vdisplay = 240,
3489 .vsync_start = 240 + 0,
3490 .vsync_end = 240 + 0 + 1,
3491 .vtotal = 240 + 0 + 1 + 0,
d8a0d6a3
LW		 3492 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3493 },
3494};
3495
3496static const struct panel_desc ti_nspire_classic_lcd_panel = {
3497 .modes = ti_nspire_classic_lcd_mode,
3498 .num_modes = 1,
3499 /* The grayscale panel has 8 bit for the color .. Y (black) */
3500 .bpc = 8,
3501 .size = {
3502 .width = 71,
3503 .height = 53,
3504 },
3505 /* This is the grayscale bus format */
3506 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3507 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
3508};
3509
06e733e4
LS		 3510static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3511 .clock = 79500,
3512 .hdisplay = 1280,
3513 .hsync_start = 1280 + 192,
3514 .hsync_end = 1280 + 192 + 128,
3515 .htotal = 1280 + 192 + 128 + 64,
3516 .vdisplay = 768,
3517 .vsync_start = 768 + 20,
3518 .vsync_end = 768 + 20 + 7,
3519 .vtotal = 768 + 20 + 7 + 3,
06e733e4
LS		 3520};
3521
3522static const struct panel_desc toshiba_lt089ac29000 = {
3523 .modes = &toshiba_lt089ac29000_mode,
3524 .num_modes = 1,
3525 .size = {
3526 .width = 194,
3527 .height = 116,
3528 },
9781bd1d 3529 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
c4715837 3530 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 3531 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 3532};
3533
227e4f40
BD		 3534static const struct drm_display_mode tpk_f07a_0102_mode = {
3535 .clock = 33260,
3536 .hdisplay = 800,
3537 .hsync_start = 800 + 40,
3538 .hsync_end = 800 + 40 + 128,
3539 .htotal = 800 + 40 + 128 + 88,
3540 .vdisplay = 480,
3541 .vsync_start = 480 + 10,
3542 .vsync_end = 480 + 10 + 2,
3543 .vtotal = 480 + 10 + 2 + 33,
227e4f40
BD		 3544};
3545
3546static const struct panel_desc tpk_f07a_0102 = {
3547 .modes = &tpk_f07a_0102_mode,
3548 .num_modes = 1,
3549 .size = {
3550 .width = 152,
3551 .height = 91,
3552 },
88bc4178 3553 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 3554};
3555
3556static const struct drm_display_mode tpk_f10a_0102_mode = {
3557 .clock = 45000,
3558 .hdisplay = 1024,
3559 .hsync_start = 1024 + 176,
3560 .hsync_end = 1024 + 176 + 5,
3561 .htotal = 1024 + 176 + 5 + 88,
3562 .vdisplay = 600,
3563 .vsync_start = 600 + 20,
3564 .vsync_end = 600 + 20 + 5,
3565 .vtotal = 600 + 20 + 5 + 25,
227e4f40
BD		 3566};
3567
3568static const struct panel_desc tpk_f10a_0102 = {
3569 .modes = &tpk_f10a_0102_mode,
3570 .num_modes = 1,
3571 .size = {
3572 .width = 223,
3573 .height = 125,
3574 },
3575};
3576
06a9dc65
MS		 3577static const struct display_timing urt_umsh_8596md_timing = {
3578 .pixelclock = { 33260000, 33260000, 33260000 },
3579 .hactive = { 800, 800, 800 },
3580 .hfront_porch = { 41, 41, 41 },
3581 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3582 .hsync_len = { 71, 128, 128 },
3583 .vactive = { 480, 480, 480 },
3584 .vfront_porch = { 10, 10, 10 },
3585 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3586 .vsync_len = { 2, 2, 2 },
3587 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3588 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3589};
3590
3591static const struct panel_desc urt_umsh_8596md_lvds = {
3592 .timings = &urt_umsh_8596md_timing,
3593 .num_timings = 1,
3594 .bpc = 6,
3595 .size = {
3596 .width = 152,
3597 .height = 91,
3598 },
3599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 3600 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 3601};
3602
3603static const struct panel_desc urt_umsh_8596md_parallel = {
3604 .timings = &urt_umsh_8596md_timing,
3605 .num_timings = 1,
3606 .bpc = 6,
3607 .size = {
3608 .width = 152,
3609 .height = 91,
3610 },
3611 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3612};
3613
04206185
FE		 3614static const struct drm_display_mode vl050_8048nt_c01_mode = {
3615 .clock = 33333,
3616 .hdisplay = 800,
3617 .hsync_start = 800 + 210,
3618 .hsync_end = 800 + 210 + 20,
3619 .htotal = 800 + 210 + 20 + 46,
3620 .vdisplay = 480,
3621 .vsync_start = 480 + 22,
3622 .vsync_end = 480 + 22 + 10,
3623 .vtotal = 480 + 22 + 10 + 23,
04206185
FE		 3624 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3625};
3626
3627static const struct panel_desc vl050_8048nt_c01 = {
3628 .modes = &vl050_8048nt_c01_mode,
3629 .num_modes = 1,
3630 .bpc = 8,
3631 .size = {
3632 .width = 120,
3633 .height = 76,
3634 },
3635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3637};
3638
e4bac408
RG		 3639static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3640 .clock = 6410,
3641 .hdisplay = 320,
3642 .hsync_start = 320 + 20,
3643 .hsync_end = 320 + 20 + 30,
3644 .htotal = 320 + 20 + 30 + 38,
3645 .vdisplay = 240,
3646 .vsync_start = 240 + 4,
3647 .vsync_end = 240 + 4 + 3,
3648 .vtotal = 240 + 4 + 3 + 15,
e4bac408
RG		 3649 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3650};
3651
3652static const struct panel_desc winstar_wf35ltiacd = {
3653 .modes = &winstar_wf35ltiacd_mode,
3654 .num_modes = 1,
3655 .bpc = 8,
3656 .size = {
3657 .width = 70,
3658 .height = 53,
3659 },
3660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3661};
3662
fcec4163
LW		 3663static const struct drm_display_mode arm_rtsm_mode[] = {
3664 {
3665 .clock = 65000,
3666 .hdisplay = 1024,
3667 .hsync_start = 1024 + 24,
3668 .hsync_end = 1024 + 24 + 136,
3669 .htotal = 1024 + 24 + 136 + 160,
3670 .vdisplay = 768,
3671 .vsync_start = 768 + 3,
3672 .vsync_end = 768 + 3 + 6,
3673 .vtotal = 768 + 3 + 6 + 29,
fcec4163
LW		 3674 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3675 },
3676};
3677
3678static const struct panel_desc arm_rtsm = {
3679 .modes = arm_rtsm_mode,
3680 .num_modes = 1,
3681 .bpc = 8,
3682 .size = {
3683 .width = 400,
3684 .height = 300,
3685 },
3686 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3687};
3688
280921de
TR		 3689static const struct of_device_id platform_of_match[] = {
3690 {
966fea78
YF		 3691 .compatible = "ampire,am-480272h3tmqw-t01h",
3692 .data = &ampire_am_480272h3tmqw_t01h,
3693 }, {
1c550fa1
PZ		 3694 .compatible = "ampire,am800480r3tmqwa1h",
3695 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 3696 }, {
3697 .compatible = "arm,rtsm-display",
3698 .data = &arm_rtsm,
c479450f
SS		 3699 }, {
3700 .compatible = "armadeus,st0700-adapt",
3701 .data = &armadeus_st0700_adapt,
1c550fa1 3702 }, {
280921de
TR		 3703 .compatible = "auo,b101aw03",
3704 .data = &auo_b101aw03,
a531bc3d
HL		 3705 }, {
3706 .compatible = "auo,b101ean01",
3707 .data = &auo_b101ean01,
dac746e0
RC		 3708 }, {
3709 .compatible = "auo,b101xtn01",
3710 .data = &auo_b101xtn01,
da458286
RC		 3711 }, {
3712 .compatible = "auo,b116xa01",
3713 .data = &auo_b116xak01,
e35e305e
AK		 3714 }, {
3715 .compatible = "auo,b116xw03",
3716 .data = &auo_b116xw03,
3e51d609
AK		 3717 }, {
3718 .compatible = "auo,b133htn01",
3719 .data = &auo_b133htn01,
a333f7ad
SM		 3720 }, {
3721 .compatible = "auo,b133xtn01",
3722 .data = &auo_b133xtn01,
bccfaffb
LM		 3723 }, {
3724 .compatible = "auo,g070vvn01",
3725 .data = &auo_g070vvn01,
4fb86404
AG		 3726 }, {
3727 .compatible = "auo,g101evn010",
3728 .data = &auo_g101evn010,
4451c287
CF		 3729 }, {
3730 .compatible = "auo,g104sn02",
3731 .data = &auo_g104sn02,
03e909ac
SR		 3732 }, {
3733 .compatible = "auo,g121ean01",
3734 .data = &auo_g121ean01,
697035c6
LS		 3735 }, {
3736 .compatible = "auo,g133han01",
3737 .data = &auo_g133han01,
d9ccd1f2
SR		 3738 }, {
3739 .compatible = "auo,g156xtn01",
3740 .data = &auo_g156xtn01,
8c31f603
LS		 3741 }, {
3742 .compatible = "auo,g185han01",
3743 .data = &auo_g185han01,
2f7b832f
SR		 3744 }, {
3745 .compatible = "auo,g190ean01",
3746 .data = &auo_g190ean01,
70c0d5b7
LS		 3747 }, {
3748 .compatible = "auo,p320hvn03",
3749 .data = &auo_p320hvn03,
7ee933a1
HS		 3750 }, {
3751 .compatible = "auo,t215hvn01",
3752 .data = &auo_t215hvn01,
d47df633
PZ		 3753 }, {
3754 .compatible = "avic,tm070ddh03",
3755 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 3756 }, {
3757 .compatible = "bananapi,s070wv20-ct16",
3758 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 3759 }, {
3760 .compatible = "boe,hv070wsa-100",
3761 .data = &boe_hv070wsa
cac1a411
CW		 3762 }, {
3763 .compatible = "boe,nv101wxmn51",
3764 .data = &boe_nv101wxmn51,
b0c664cc
BA		 3765 }, {
3766 .compatible = "boe,nv133fhm-n61",
3767 .data = &boe_nv133fhm_n61,
cfe40d02
DA		 3768 }, {
3769 .compatible = "boe,nv133fhm-n62",
3770 .data = &boe_nv133fhm_n61,
a5119818
TS		 3771 }, {
3772 .compatible = "boe,nv140fhmn49",
3773 .data = &boe_nv140fhmn49,
e58edce6
GB		 3774 }, {
3775 .compatible = "cdtech,s043wq26h-ct7",
3776 .data = &cdtech_s043wq26h_ct7,
0e3b67f6
MK		 3777 }, {
3778 .compatible = "cdtech,s070pws19hp-fc21",
3779 .data = &cdtech_s070pws19hp_fc21,
3780 }, {
3781 .compatible = "cdtech,s070swv29hg-dc44",
3782 .data = &cdtech_s070swv29hg_dc44,
982f944e
GB		 3783 }, {
3784 .compatible = "cdtech,s070wv95-ct16",
3785 .data = &cdtech_s070wv95_ct16,
2cb35c80
RL		 3786 }, {
3787 .compatible = "chunghwa,claa070wp03xg",
3788 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 3789 }, {
3790 .compatible = "chunghwa,claa101wa01a",
3791 .data = &chunghwa_claa101wa01a
280921de
TR		 3792 }, {
3793 .compatible = "chunghwa,claa101wb01",
3794 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 3795 }, {
3796 .compatible = "dataimage,scf0700c48ggu18",
3797 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 3798 }, {
3799 .compatible = "dlc,dlc0700yzg-1",
3800 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 3801 }, {
3802 .compatible = "dlc,dlc1010gig",
3803 .data = &dlc_dlc1010gig,
c2d24af6
AP		 3804 }, {
3805 .compatible = "edt,et035012dm6",
3806 .data = &edt_et035012dm6,
82d57a59
MCR		 3807 }, {
3808 .compatible = "edt,etm043080dh6gp",
3809 .data = &edt_etm043080dh6gp,
fd819bff
MV		 3810 }, {
3811 .compatible = "edt,etm0430g0dh6",
3812 .data = &edt_etm0430g0dh6,
26ab0065
SA		 3813 }, {
3814 .compatible = "edt,et057090dhu",
3815 .data = &edt_et057090dhu,
fff5de45
PZ		 3816 }, {
3817 .compatible = "edt,et070080dh6",
3818 .data = &edt_etm0700g0dh6,
3819 }, {
3820 .compatible = "edt,etm0700g0dh6",
3821 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 3822 }, {
3823 .compatible = "edt,etm0700g0bdh6",
3824 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 3825 }, {
3826 .compatible = "edt,etm0700g0edh6",
3827 .data = &edt_etm0700g0bdh6,
9158e3c3
MF		 3828 }, {
3829 .compatible = "evervision,vgg804821",
3830 .data = &evervision_vgg804821,
102932b0
BB		 3831 }, {
3832 .compatible = "foxlink,fl500wvr00-a0t",
3833 .data = &foxlink_fl500wvr00_a0t,
7b6bd843
PC		 3834 }, {
3835 .compatible = "frida,frd350h54004",
3836 .data = &frida_frd350h54004,
3be20710
JT		 3837 }, {
3838 .compatible = "friendlyarm,hd702e",
3839 .data = &friendlyarm_hd702e,
d435a2af
PZ		 3840 }, {
3841 .compatible = "giantplus,gpg482739qs5",
3842 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 3843 }, {
3844 .compatible = "giantplus,gpm940b0",
3845 .data = &giantplus_gpm940b0,
a853205e
PZ		 3846 }, {
3847 .compatible = "hannstar,hsd070pww1",
3848 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 3849 }, {
3850 .compatible = "hannstar,hsd100pxn1",
3851 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 3852 }, {
3853 .compatible = "hit,tx23d38vm0caa",
3854 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 3855 }, {
3856 .compatible = "innolux,at043tn24",
3857 .data = &innolux_at043tn24,
4fc24ab3
RB		 3858 }, {
3859 .compatible = "innolux,at070tn92",
3860 .data = &innolux_at070tn92,
1e29b840 3861 }, {
a5d2ade6
CF		 3862 .compatible = "innolux,g070y2-l01",
3863 .data = &innolux_g070y2_l01,
3864 }, {
3865 .compatible = "innolux,g101ice-l01",
1e29b840 3866 .data = &innolux_g101ice_l01
d731f661 3867 }, {
a5d2ade6 3868 .compatible = "innolux,g121i1-l01",
d731f661 3869 .data = &innolux_g121i1_l01
f8fa17ba
AB		 3870 }, {
3871 .compatible = "innolux,g121x1-l03",
3872 .data = &innolux_g121x1_l03,
0a2288c0
TR		 3873 }, {
3874 .compatible = "innolux,n116bge",
3875 .data = &innolux_n116bge,
ea44739d
AB		 3876 }, {
3877 .compatible = "innolux,n156bge-l21",
3878 .data = &innolux_n156bge_l21,
da50bd42 3879 }, {
8f054b6f
DA		 3880 .compatible = "innolux,p120zdg-bf1",
3881 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 3882 }, {
3883 .compatible = "innolux,zj070na-01p",
3884 .data = &innolux_zj070na_01p,
e1ca5184
BA		 3885 }, {
3886 .compatible = "ivo,m133nwf4-r0",
3887 .data = &ivo_m133nwf4_r0,
14bf60c4
LM		 3888 }, {
3889 .compatible = "koe,tx14d24vm1bpa",
3890 .data = &koe_tx14d24vm1bpa,
8a070524
LY		 3891 }, {
3892 .compatible = "koe,tx26d202vm0bwa",
3893 .data = &koe_tx26d202vm0bwa,
8cfe8341
JT		 3894 }, {
3895 .compatible = "koe,tx31d200vm0baa",
3896 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 3897 }, {
3898 .compatible = "kyo,tcg121xglp",
3899 .data = &kyo_tcg121xglp,
27abdd83
PK		 3900 }, {
3901 .compatible = "lemaker,bl035-rgb-002",
3902 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 3903 }, {
3904 .compatible = "lg,lb070wv8",
3905 .data = &lg_lb070wv8,
c5ece402
YY		 3906 }, {
3907 .compatible = "lg,lp079qx1-sp0v",
3908 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 3909 }, {
3910 .compatible = "lg,lp097qx1-spa1",
3911 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 3912 }, {
3913 .compatible = "lg,lp120up1",
3914 .data = &lg_lp120up1,
ec7c5653
TR		 3915 }, {
3916 .compatible = "lg,lp129qe",
3917 .data = &lg_lp129qe,
0d35408a
AF		 3918 }, {
3919 .compatible = "logicpd,type28",
3920 .data = &logicpd_type_28,
5728fe7f
MZ		 3921 }, {
3922 .compatible = "logictechno,lt161010-2nhc",
3923 .data = &logictechno_lt161010_2nh,
3924 }, {
3925 .compatible = "logictechno,lt161010-2nhr",
3926 .data = &logictechno_lt161010_2nh,
3927 }, {
3928 .compatible = "logictechno,lt170410-2whc",
3929 .data = &logictechno_lt170410_2whc,
65c766ca
LM		 3930 }, {
3931 .compatible = "mitsubishi,aa070mc01-ca1",
3932 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 3933 }, {
3934 .compatible = "nec,nl12880bc20-05",
3935 .data = &nec_nl12880bc20_05,
c6e87f91 3936 }, {
3937 .compatible = "nec,nl4827hc19-05b",
3938 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 3939 }, {
3940 .compatible = "netron-dy,e231732",
3941 .data = &netron_dy_e231732,
258145ea
VK		 3942 }, {
3943 .compatible = "neweast,wjfh116008a",
3944 .data = &neweast_wjfh116008a,
3b39ad7a
TV		 3945 }, {
3946 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3947 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 3948 }, {
3949 .compatible = "nlt,nl192108ac18-02d",
3950 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 3951 }, {
3952 .compatible = "nvd,9128",
3953 .data = &nvd_9128,
a99fb626
GB		 3954 }, {
3955 .compatible = "okaya,rs800480t-7x0gp",
3956 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 3957 }, {
3958 .compatible = "olimex,lcd-olinuxino-43-ts",
3959 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 3960 }, {
3961 .compatible = "ontat,yx700wv03",
3962 .data = &ontat_yx700wv03,
9c31dcb6
NS		 3963 }, {
3964 .compatible = "ortustech,com37h3m05dtc",
3965 .data = &ortustech_com37h3m,
3966 }, {
3967 .compatible = "ortustech,com37h3m99dtc",
3968 .data = &ortustech_com37h3m,
725c9d40
PZ		 3969 }, {
3970 .compatible = "ortustech,com43h4m85ulc",
3971 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 3972 }, {
3973 .compatible = "osddisplays,osd070t1718-19ts",
3974 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 3975 }, {
3976 .compatible = "pda,91-00156-a0",
3977 .data = &pda_91_00156_a0,
d2a6f0f5
JW		 3978 }, {
3979 .compatible = "qiaodian,qd43003c0-40",
3980 .data = &qd43003c0_40,
23167fa9
JT		 3981 }, {
3982 .compatible = "rocktech,rk070er9427",
3983 .data = &rocktech_rk070er9427,
f305047b
JS		 3984 }, {
3985 .compatible = "rocktech,rk101ii01d-ct",
3986 .data = &rocktech_rk101ii01d_ct,
0330eaf3
YY		 3987 }, {
3988 .compatible = "samsung,lsn122dl01-c01",
3989 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 3990 }, {
3991 .compatible = "samsung,ltn101nt05",
3992 .data = &samsung_ltn101nt05,
0c934306
SM		 3993 }, {
3994 .compatible = "samsung,ltn140at29-301",
3995 .data = &samsung_ltn140at29_301,
44c58c52
MR		 3996 }, {
3997 .compatible = "satoz,sat050at40h12r2",
3998 .data = &satoz_sat050at40h12r2,
cd5e1cbe
JH		 3999 }, {
4000 .compatible = "sharp,ld-d5116z01b",
4001 .data = &sharp_ld_d5116z01b,
03e3ec9a
VZ		 4002 }, {
4003 .compatible = "sharp,lq035q7db03",
4004 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 4005 }, {
4006 .compatible = "sharp,lq070y3dg3b",
4007 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 4008 }, {
4009 .compatible = "sharp,lq101k1ly04",
4010 .data = &sharp_lq101k1ly04,
739c7de9
YY		 4011 }, {
4012 .compatible = "sharp,lq123p1jx31",
4013 .data = &sharp_lq123p1jx31,
f1bd37f3
PC		 4014 }, {
4015 .compatible = "sharp,ls020b1dd01d",
4016 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 4017 }, {
4018 .compatible = "shelly,sca07010-bfn-lnn",
4019 .data = &shelly_sca07010_bfn_lnn,
105235e4
PR		 4020 }, {
4021 .compatible = "starry,kr070pe2t",
4022 .data = &starry_kr070pe2t,
9bb34c4c
DA		 4023 }, {
4024 .compatible = "starry,kr122ea0sra",
4025 .data = &starry_kr122ea0sra,
42161531
JS		 4026 }, {
4027 .compatible = "tfc,s9700rtwv43tr-01b",
4028 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 4029 }, {
4030 .compatible = "tianma,tm070jdhg30",
4031 .data = &tianma_tm070jdhg30,
b3bfcdf8
MM		 4032 }, {
4033 .compatible = "tianma,tm070jvhg33",
4034 .data = &tianma_tm070jvhg33,
870a0b12
LM		 4035 }, {
4036 .compatible = "tianma,tm070rvhg71",
4037 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 4038 }, {
4039 .compatible = "ti,nspire-cx-lcd-panel",
4040 .data = &ti_nspire_cx_lcd_panel,
4041 }, {
4042 .compatible = "ti,nspire-classic-lcd-panel",
4043 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 4044 }, {
4045 .compatible = "toshiba,lt089ac29000",
4046 .data = &toshiba_lt089ac29000,
227e4f40
BD		 4047 }, {
4048 .compatible = "tpk,f07a-0102",
4049 .data = &tpk_f07a_0102,
4050 }, {
4051 .compatible = "tpk,f10a-0102",
4052 .data = &tpk_f10a_0102,
06a9dc65
MS		 4053 }, {
4054 .compatible = "urt,umsh-8596md-t",
4055 .data = &urt_umsh_8596md_parallel,
4056 }, {
4057 .compatible = "urt,umsh-8596md-1t",
4058 .data = &urt_umsh_8596md_parallel,
4059 }, {
4060 .compatible = "urt,umsh-8596md-7t",
4061 .data = &urt_umsh_8596md_parallel,
4062 }, {
4063 .compatible = "urt,umsh-8596md-11t",
4064 .data = &urt_umsh_8596md_lvds,
4065 }, {
4066 .compatible = "urt,umsh-8596md-19t",
4067 .data = &urt_umsh_8596md_lvds,
4068 }, {
4069 .compatible = "urt,umsh-8596md-20t",
4070 .data = &urt_umsh_8596md_parallel,
04206185
FE		 4071 }, {
4072 .compatible = "vxt,vl050-8048nt-c01",
4073 .data = &vl050_8048nt_c01,
e4bac408
RG		 4074 }, {
4075 .compatible = "winstar,wf35ltiacd",
4076 .data = &winstar_wf35ltiacd,
4a1d0dbc
SR		 4077 }, {
4078 /* Must be the last entry */
4079 .compatible = "panel-dpi",
4080 .data = &panel_dpi,
280921de
TR		 4081 }, {
4082 /* sentinel */
4083 }
4084};
4085MODULE_DEVICE_TABLE(of, platform_of_match);
4086
4087static int panel_simple_platform_probe(struct platform_device *pdev)
4088{
4089 const struct of_device_id *id;
4090
4091 id = of_match_node(platform_of_match, pdev->dev.of_node);
4092 if (!id)
4093 return -ENODEV;
4094
4095 return panel_simple_probe(&pdev->dev, id->data);
4096}
4097
4098static int panel_simple_platform_remove(struct platform_device *pdev)
4099{
4100 return panel_simple_remove(&pdev->dev);
4101}
4102
d02fd93e
TR		 4103static void panel_simple_platform_shutdown(struct platform_device *pdev)
4104{
4105 panel_simple_shutdown(&pdev->dev);
4106}
4107
280921de
TR		 4108static struct platform_driver panel_simple_platform_driver = {
4109 .driver = {
4110 .name = "panel-simple",
280921de
TR		 4111 .of_match_table = platform_of_match,
4112 },
4113 .probe = panel_simple_platform_probe,
4114 .remove = panel_simple_platform_remove,
d02fd93e 4115 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 4116};
4117
210fcd9d
TR		 4118struct panel_desc_dsi {
4119 struct panel_desc desc;
4120
462658b8 4121 unsigned long flags;
210fcd9d
TR		 4122 enum mipi_dsi_pixel_format format;
4123 unsigned int lanes;
4124};
4125
d718d79e
TR		 4126static const struct drm_display_mode auo_b080uan01_mode = {
4127 .clock = 154500,
4128 .hdisplay = 1200,
4129 .hsync_start = 1200 + 62,
4130 .hsync_end = 1200 + 62 + 4,
4131 .htotal = 1200 + 62 + 4 + 62,
4132 .vdisplay = 1920,
4133 .vsync_start = 1920 + 9,
4134 .vsync_end = 1920 + 9 + 2,
4135 .vtotal = 1920 + 9 + 2 + 8,
d718d79e
TR		 4136};
4137
4138static const struct panel_desc_dsi auo_b080uan01 = {
4139 .desc = {
4140 .modes = &auo_b080uan01_mode,
4141 .num_modes = 1,
4142 .bpc = 8,
4143 .size = {
4144 .width = 108,
4145 .height = 272,
4146 },
cb62cdec 4147 .connector_type = DRM_MODE_CONNECTOR_DSI,
d718d79e
TR		 4148 },
4149 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4150 .format = MIPI_DSI_FMT_RGB888,
4151 .lanes = 4,
4152};
4153
c8521969
CZ		 4154static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4155 .clock = 160000,
4156 .hdisplay = 1200,
4157 .hsync_start = 1200 + 120,
4158 .hsync_end = 1200 + 120 + 20,
4159 .htotal = 1200 + 120 + 20 + 21,
4160 .vdisplay = 1920,
4161 .vsync_start = 1920 + 21,
4162 .vsync_end = 1920 + 21 + 3,
4163 .vtotal = 1920 + 21 + 3 + 18,
c8521969
CZ		 4164 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4165};
4166
4167static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4168 .desc = {
4169 .modes = &boe_tv080wum_nl0_mode,
4170 .num_modes = 1,
4171 .size = {
4172 .width = 107,
4173 .height = 172,
4174 },
cb62cdec 4175 .connector_type = DRM_MODE_CONNECTOR_DSI,
c8521969
CZ		 4176 },
4177 .flags = MIPI_DSI_MODE_VIDEO |
4178 MIPI_DSI_MODE_VIDEO_BURST |
4179 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4180 .format = MIPI_DSI_FMT_RGB888,
4181 .lanes = 4,
4182};
4183
712ac1ba
AC		 4184static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4185 .clock = 71000,
4186 .hdisplay = 800,
4187 .hsync_start = 800 + 32,
4188 .hsync_end = 800 + 32 + 1,
4189 .htotal = 800 + 32 + 1 + 57,
4190 .vdisplay = 1280,
4191 .vsync_start = 1280 + 28,
4192 .vsync_end = 1280 + 28 + 1,
4193 .vtotal = 1280 + 28 + 1 + 14,
712ac1ba
AC		 4194};
4195
4196static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4197 .desc = {
4198 .modes = &lg_ld070wx3_sl01_mode,
4199 .num_modes = 1,
d7a839cd 4200 .bpc = 8,
712ac1ba
AC		 4201 .size = {
4202 .width = 94,
4203 .height = 151,
4204 },
cb62cdec 4205 .connector_type = DRM_MODE_CONNECTOR_DSI,
712ac1ba 4206 },
5e4cc278 4207 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 4208 .format = MIPI_DSI_FMT_RGB888,
4209 .lanes = 4,
4210};
4211
499ce85a
AC		 4212static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4213 .clock = 67000,
4214 .hdisplay = 720,
4215 .hsync_start = 720 + 12,
4216 .hsync_end = 720 + 12 + 4,
4217 .htotal = 720 + 12 + 4 + 112,
4218 .vdisplay = 1280,
4219 .vsync_start = 1280 + 8,
4220 .vsync_end = 1280 + 8 + 4,
4221 .vtotal = 1280 + 8 + 4 + 12,
499ce85a
AC		 4222};
4223
4224static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4225 .desc = {
4226 .modes = &lg_lh500wx1_sd03_mode,
4227 .num_modes = 1,
d7a839cd 4228 .bpc = 8,
499ce85a
AC		 4229 .size = {
4230 .width = 62,
4231 .height = 110,
4232 },
cb62cdec 4233 .connector_type = DRM_MODE_CONNECTOR_DSI,
499ce85a
AC		 4234 },
4235 .flags = MIPI_DSI_MODE_VIDEO,
4236 .format = MIPI_DSI_FMT_RGB888,
4237 .lanes = 4,
4238};
4239
280921de
TR		 4240static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4241 .clock = 157200,
4242 .hdisplay = 1920,
4243 .hsync_start = 1920 + 154,
4244 .hsync_end = 1920 + 154 + 16,
4245 .htotal = 1920 + 154 + 16 + 32,
4246 .vdisplay = 1200,
4247 .vsync_start = 1200 + 17,
4248 .vsync_end = 1200 + 17 + 2,
4249 .vtotal = 1200 + 17 + 2 + 16,
280921de
TR		 4250};
4251
210fcd9d
TR		 4252static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4253 .desc = {
4254 .modes = &panasonic_vvx10f004b00_mode,
4255 .num_modes = 1,
d7a839cd 4256 .bpc = 8,
210fcd9d
TR		 4257 .size = {
4258 .width = 217,
4259 .height = 136,
4260 },
cb62cdec 4261 .connector_type = DRM_MODE_CONNECTOR_DSI,
280921de 4262 },
5e4cc278
AC		 4263 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4264 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 4265 .format = MIPI_DSI_FMT_RGB888,
4266 .lanes = 4,
4267};
4268
debcd8f9
JM		 4269static const struct drm_display_mode lg_acx467akm_7_mode = {
4270 .clock = 150000,
4271 .hdisplay = 1080,
4272 .hsync_start = 1080 + 2,
4273 .hsync_end = 1080 + 2 + 2,
4274 .htotal = 1080 + 2 + 2 + 2,
4275 .vdisplay = 1920,
4276 .vsync_start = 1920 + 2,
4277 .vsync_end = 1920 + 2 + 2,
4278 .vtotal = 1920 + 2 + 2 + 2,
debcd8f9
JM		 4279};
4280
4281static const struct panel_desc_dsi lg_acx467akm_7 = {
4282 .desc = {
4283 .modes = &lg_acx467akm_7_mode,
4284 .num_modes = 1,
4285 .bpc = 8,
4286 .size = {
4287 .width = 62,
4288 .height = 110,
4289 },
cb62cdec 4290 .connector_type = DRM_MODE_CONNECTOR_DSI,
debcd8f9
JM		 4291 },
4292 .flags = 0,
4293 .format = MIPI_DSI_FMT_RGB888,
4294 .lanes = 4,
4295};
4296
62967232
PU		 4297static const struct drm_display_mode osd101t2045_53ts_mode = {
4298 .clock = 154500,
4299 .hdisplay = 1920,
4300 .hsync_start = 1920 + 112,
4301 .hsync_end = 1920 + 112 + 16,
4302 .htotal = 1920 + 112 + 16 + 32,
4303 .vdisplay = 1200,
4304 .vsync_start = 1200 + 16,
4305 .vsync_end = 1200 + 16 + 2,
4306 .vtotal = 1200 + 16 + 2 + 16,
62967232
PU		 4307 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4308};
4309
4310static const struct panel_desc_dsi osd101t2045_53ts = {
4311 .desc = {
4312 .modes = &osd101t2045_53ts_mode,
4313 .num_modes = 1,
4314 .bpc = 8,
4315 .size = {
4316 .width = 217,
4317 .height = 136,
4318 },
cb62cdec 4319 .connector_type = DRM_MODE_CONNECTOR_DSI,
62967232
PU		 4320 },
4321 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4322 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4323 MIPI_DSI_MODE_EOT_PACKET,
4324 .format = MIPI_DSI_FMT_RGB888,
4325 .lanes = 4,
4326};
4327
210fcd9d
TR		 4328static const struct of_device_id dsi_of_match[] = {
4329 {
d718d79e
TR		 4330 .compatible = "auo,b080uan01",
4331 .data = &auo_b080uan01
c8521969
CZ		 4332 }, {
4333 .compatible = "boe,tv080wum-nl0",
4334 .data = &boe_tv080wum_nl0
d718d79e 4335 }, {
712ac1ba
AC		 4336 .compatible = "lg,ld070wx3-sl01",
4337 .data = &lg_ld070wx3_sl01
4338 }, {
499ce85a
AC		 4339 .compatible = "lg,lh500wx1-sd03",
4340 .data = &lg_lh500wx1_sd03
4341 }, {
210fcd9d
TR		 4342 .compatible = "panasonic,vvx10f004b00",
4343 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 4344 }, {
4345 .compatible = "lg,acx467akm-7",
4346 .data = &lg_acx467akm_7
62967232
PU		 4347 }, {
4348 .compatible = "osddisplays,osd101t2045-53ts",
4349 .data = &osd101t2045_53ts
210fcd9d
TR		 4350 }, {
4351 /* sentinel */
4352 }
4353};
4354MODULE_DEVICE_TABLE(of, dsi_of_match);
4355
4356static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4357{
4358 const struct panel_desc_dsi *desc;
4359 const struct of_device_id *id;
4360 int err;
4361
4362 id = of_match_node(dsi_of_match, dsi->dev.of_node);
4363 if (!id)
4364 return -ENODEV;
4365
4366 desc = id->data;
4367
4368 err = panel_simple_probe(&dsi->dev, &desc->desc);
4369 if (err < 0)
4370 return err;
4371
462658b8 4372 dsi->mode_flags = desc->flags;
210fcd9d
TR		 4373 dsi->format = desc->format;
4374 dsi->lanes = desc->lanes;
4375
7ad9db66
PU		 4376 err = mipi_dsi_attach(dsi);
4377 if (err) {
4378 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
4379
4380 drm_panel_remove(&panel->base);
4381 }
4382
4383 return err;
210fcd9d
TR		 4384}
4385
4386static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4387{
4388 int err;
4389
4390 err = mipi_dsi_detach(dsi);
4391 if (err < 0)
4392 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4393
4394 return panel_simple_remove(&dsi->dev);
4395}
4396
d02fd93e
TR		 4397static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4398{
4399 panel_simple_shutdown(&dsi->dev);
4400}
4401
210fcd9d
TR		 4402static struct mipi_dsi_driver panel_simple_dsi_driver = {
4403 .driver = {
4404 .name = "panel-simple-dsi",
210fcd9d
TR		 4405 .of_match_table = dsi_of_match,
4406 },
4407 .probe = panel_simple_dsi_probe,
4408 .remove = panel_simple_dsi_remove,
d02fd93e 4409 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 4410};
4411
4412static int __init panel_simple_init(void)
4413{
210fcd9d
TR		 4414 int err;
4415
4416 err = platform_driver_register(&panel_simple_platform_driver);
4417 if (err < 0)
4418 return err;
4419
4420 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4421 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4422 if (err < 0)
4423 return err;
4424 }
4425
4426 return 0;
280921de
TR		 4427}
4428module_init(panel_simple_init);
4429
4430static void __exit panel_simple_exit(void)
4431{
210fcd9d
TR		 4432 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4433 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4434
280921de
TR		 4435 platform_driver_unregister(&panel_simple_platform_driver);
4436}
4437module_exit(panel_simple_exit);
4438
4439MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4440MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4441MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)