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dt-bindings: display: simple: Add Satoz panel
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
cb23eae3 31#include <video/display_timing.h>
b8a2948f 32#include <video/of_display_timing.h>
cb23eae3
SR		 33#include <video/videomode.h>
34
280921de 35#include <drm/drm_crtc.h>
cb23eae3 36#include <drm/drm_device.h>
210fcd9d 37#include <drm/drm_mipi_dsi.h>
280921de
TR		 38#include <drm/drm_panel.h>
39
e362cc6a
DA		 40/**
41 * @modes: Pointer to array of fixed modes appropriate for this panel. If
42 * only one mode then this can just be the address of this the mode.
43 * NOTE: cannot be used with "timings" and also if this is specified
44 * then you cannot override the mode in the device tree.
45 * @num_modes: Number of elements in modes array.
46 * @timings: Pointer to array of display timings. NOTE: cannot be used with
47 * "modes" and also these will be used to validate a device tree
48 * override if one is present.
49 * @num_timings: Number of elements in timings array.
50 * @bpc: Bits per color.
51 * @size: Structure containing the physical size of this panel.
52 * @delay: Structure containing various delay values for this panel.
53 * @bus_format: See MEDIA_BUS_FMT_... defines.
54 * @bus_flags: See DRM_BUS_FLAG_... defines.
55 */
280921de
TR		 56struct panel_desc {
57 const struct drm_display_mode *modes;
58 unsigned int num_modes;
a5d3e625
PZ		 59 const struct display_timing *timings;
60 unsigned int num_timings;
280921de 61
0208d511
SM		 62 unsigned int bpc;
63
85533e3b
UÖ		 64 /**
65 * @width: width (in millimeters) of the panel's active display area
66 * @height: height (in millimeters) of the panel's active display area
67 */
280921de
TR		 68 struct {
69 unsigned int width;
70 unsigned int height;
71 } size;
f673c37e
AK		 72
73 /**
74 * @prepare: the time (in milliseconds) that it takes for the panel to
75 * become ready and start receiving video data
2ed3e951
DA		 76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
77 * Plug Detect isn't used.
f673c37e
AK		 78 * @enable: the time (in milliseconds) that it takes for the panel to
79 * display the first valid frame after starting to receive
80 * video data
81 * @disable: the time (in milliseconds) that it takes for the panel to
82 * turn the display off (no content is visible)
83 * @unprepare: the time (in milliseconds) that it takes for the panel
84 * to power itself down completely
85 */
86 struct {
87 unsigned int prepare;
2ed3e951 88 unsigned int hpd_absent_delay;
f673c37e
AK		 89 unsigned int enable;
90 unsigned int disable;
91 unsigned int unprepare;
92 } delay;
795f7ab3
BB		 93
94 u32 bus_format;
f0aa0838 95 u32 bus_flags;
9a2654c0 96 int connector_type;
280921de
TR		 97};
98
280921de
TR		 99struct panel_simple {
100 struct drm_panel base;
613a633e 101 bool prepared;
280921de 102 bool enabled;
2ed3e951 103 bool no_hpd;
280921de
TR		 104
105 const struct panel_desc *desc;
106
280921de
TR		 107 struct regulator *supply;
108 struct i2c_adapter *ddc;
109
cfdf0549 110 struct gpio_desc *enable_gpio;
b8a2948f
SP		 111
112 struct drm_display_mode override_mode;
280921de
TR		 113};
114
115static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
116{
117 return container_of(panel, struct panel_simple, base);
118}
119
0ce8ddd8
SR		 120static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
121 struct drm_connector *connector)
280921de 122{
280921de
TR		 123 struct drm_display_mode *mode;
124 unsigned int i, num = 0;
125
a5d3e625
PZ		 126 for (i = 0; i < panel->desc->num_timings; i++) {
127 const struct display_timing *dt = &panel->desc->timings[i];
128 struct videomode vm;
129
130 videomode_from_timing(dt, &vm);
aa6c4364 131 mode = drm_mode_create(connector->dev);
a5d3e625 132 if (!mode) {
aa6c4364 133 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 134 dt->hactive.typ, dt->vactive.typ);
135 continue;
136 }
137
138 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 139
140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
230c5b44 142 if (panel->desc->num_timings == 1)
cda55372
BB		 143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
a5d3e625
PZ		 145 drm_mode_probed_add(connector, mode);
146 num++;
147 }
148
b8a2948f
SP		 149 return num;
150}
151
0ce8ddd8
SR		 152static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
153 struct drm_connector *connector)
b8a2948f 154{
b8a2948f
SP		 155 struct drm_display_mode *mode;
156 unsigned int i, num = 0;
157
280921de
TR		 158 for (i = 0; i < panel->desc->num_modes; i++) {
159 const struct drm_display_mode *m = &panel->desc->modes[i];
160
aa6c4364 161 mode = drm_mode_duplicate(connector->dev, m);
280921de 162 if (!mode) {
aa6c4364 163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
280921de
TR		 164 m->hdisplay, m->vdisplay, m->vrefresh);
165 continue;
166 }
167
cda55372
BB		 168 mode->type |= DRM_MODE_TYPE_DRIVER;
169
170 if (panel->desc->num_modes == 1)
171 mode->type |= DRM_MODE_TYPE_PREFERRED;
172
280921de
TR		 173 drm_mode_set_name(mode);
174
175 drm_mode_probed_add(connector, mode);
176 num++;
177 }
178
b8a2948f
SP		 179 return num;
180}
181
0ce8ddd8
SR		 182static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
183 struct drm_connector *connector)
b8a2948f 184{
b8a2948f
SP		 185 struct drm_display_mode *mode;
186 bool has_override = panel->override_mode.type;
187 unsigned int num = 0;
188
189 if (!panel->desc)
190 return 0;
191
192 if (has_override) {
aa6c4364
SR		 193 mode = drm_mode_duplicate(connector->dev,
194 &panel->override_mode);
b8a2948f
SP		 195 if (mode) {
196 drm_mode_probed_add(connector, mode);
197 num = 1;
198 } else {
aa6c4364 199 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 200 }
201 }
202
203 /* Only add timings if override was not there or failed to validate */
204 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 205 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 206
207 /*
208 * Only add fixed modes if timings/override added no mode.
209 *
210 * We should only ever have either the display timings specified
211 * or a fixed mode. Anything else is rather bogus.
212 */
213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
214 if (num == 0)
0ce8ddd8 215 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 216
0208d511 217 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 218 connector->display_info.width_mm = panel->desc->size.width;
219 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 220 if (panel->desc->bus_format)
221 drm_display_info_set_bus_formats(&connector->display_info,
222 &panel->desc->bus_format, 1);
f0aa0838 223 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 224
225 return num;
226}
227
228static int panel_simple_disable(struct drm_panel *panel)
229{
230 struct panel_simple *p = to_panel_simple(panel);
231
232 if (!p->enabled)
233 return 0;
234
f673c37e
AK		 235 if (p->desc->delay.disable)
236 msleep(p->desc->delay.disable);
237
280921de
TR		 238 p->enabled = false;
239
240 return 0;
241}
242
c0e1d170
AK		 243static int panel_simple_unprepare(struct drm_panel *panel)
244{
613a633e
AK		 245 struct panel_simple *p = to_panel_simple(panel);
246
247 if (!p->prepared)
248 return 0;
249
756b918d 250 gpiod_set_value_cansleep(p->enable_gpio, 0);
613a633e
AK		 251
252 regulator_disable(p->supply);
253
f673c37e
AK		 254 if (p->desc->delay.unprepare)
255 msleep(p->desc->delay.unprepare);
256
613a633e 257 p->prepared = false;
c0e1d170 258
c0e1d170
AK		 259 return 0;
260}
261
613a633e 262static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 263{
264 struct panel_simple *p = to_panel_simple(panel);
2ed3e951 265 unsigned int delay;
280921de
TR		 266 int err;
267
613a633e 268 if (p->prepared)
280921de
TR		 269 return 0;
270
271 err = regulator_enable(p->supply);
272 if (err < 0) {
273 dev_err(panel->dev, "failed to enable supply: %d\n", err);
274 return err;
275 }
276
756b918d 277 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 278
2ed3e951
DA		 279 delay = p->desc->delay.prepare;
280 if (p->no_hpd)
281 delay += p->desc->delay.hpd_absent_delay;
282 if (delay)
283 msleep(delay);
f673c37e 284
613a633e
AK		 285 p->prepared = true;
286
287 return 0;
288}
289
290static int panel_simple_enable(struct drm_panel *panel)
291{
292 struct panel_simple *p = to_panel_simple(panel);
293
294 if (p->enabled)
295 return 0;
296
f673c37e
AK		 297 if (p->desc->delay.enable)
298 msleep(p->desc->delay.enable);
299
280921de
TR		 300 p->enabled = true;
301
302 return 0;
303}
304
0ce8ddd8
SR		 305static int panel_simple_get_modes(struct drm_panel *panel,
306 struct drm_connector *connector)
280921de
TR		 307{
308 struct panel_simple *p = to_panel_simple(panel);
309 int num = 0;
310
311 /* probe EDID if a DDC bus is available */
312 if (p->ddc) {
0ce8ddd8
SR		 313 struct edid *edid = drm_get_edid(connector, p->ddc);
314
315 drm_connector_update_edid_property(connector, edid);
280921de 316 if (edid) {
0ce8ddd8 317 num += drm_add_edid_modes(connector, edid);
280921de
TR		 318 kfree(edid);
319 }
320 }
321
322 /* add hard-coded panel modes */
0ce8ddd8 323 num += panel_simple_get_non_edid_modes(p, connector);
280921de
TR		 324
325 return num;
326}
327
a5d3e625
PZ		 328static int panel_simple_get_timings(struct drm_panel *panel,
329 unsigned int num_timings,
330 struct display_timing *timings)
331{
332 struct panel_simple *p = to_panel_simple(panel);
333 unsigned int i;
334
335 if (p->desc->num_timings < num_timings)
336 num_timings = p->desc->num_timings;
337
338 if (timings)
339 for (i = 0; i < num_timings; i++)
340 timings[i] = p->desc->timings[i];
341
342 return p->desc->num_timings;
343}
344
280921de
TR		 345static const struct drm_panel_funcs panel_simple_funcs = {
346 .disable = panel_simple_disable,
c0e1d170
AK		 347 .unprepare = panel_simple_unprepare,
348 .prepare = panel_simple_prepare,
280921de
TR		 349 .enable = panel_simple_enable,
350 .get_modes = panel_simple_get_modes,
a5d3e625 351 .get_timings = panel_simple_get_timings,
280921de
TR		 352};
353
b8a2948f
SP		 354#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
355 (to_check->field.typ >= bounds->field.min && \
356 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 357static void panel_simple_parse_panel_timing_node(struct device *dev,
358 struct panel_simple *panel,
359 const struct display_timing *ot)
b8a2948f
SP		 360{
361 const struct panel_desc *desc = panel->desc;
362 struct videomode vm;
363 unsigned int i;
364
365 if (WARN_ON(desc->num_modes)) {
366 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
367 return;
368 }
369 if (WARN_ON(!desc->num_timings)) {
370 dev_err(dev, "Reject override mode: no timings specified\n");
371 return;
372 }
373
374 for (i = 0; i < panel->desc->num_timings; i++) {
375 const struct display_timing *dt = &panel->desc->timings[i];
376
377 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
378 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
379 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
380 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
381 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
382 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
383 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
384 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
385 continue;
386
387 if (ot->flags != dt->flags)
388 continue;
389
390 videomode_from_timing(ot, &vm);
391 drm_display_mode_from_videomode(&vm, &panel->override_mode);
392 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
393 DRM_MODE_TYPE_PREFERRED;
394 break;
395 }
396
397 if (WARN_ON(!panel->override_mode.type))
398 dev_err(dev, "Reject override mode: No display_timing found\n");
399}
400
280921de
TR		 401static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
402{
280921de 403 struct panel_simple *panel;
b8a2948f 404 struct display_timing dt;
0fe1564b 405 struct device_node *ddc;
280921de
TR		 406 int err;
407
408 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
409 if (!panel)
410 return -ENOMEM;
411
412 panel->enabled = false;
613a633e 413 panel->prepared = false;
280921de
TR		 414 panel->desc = desc;
415
2ed3e951
DA		 416 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
417
280921de
TR		 418 panel->supply = devm_regulator_get(dev, "power");
419 if (IS_ERR(panel->supply))
420 return PTR_ERR(panel->supply);
421
a61400d8
AC		 422 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
423 GPIOD_OUT_LOW);
cfdf0549
AC		 424 if (IS_ERR(panel->enable_gpio)) {
425 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 426 if (err != -EPROBE_DEFER)
427 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 428 return err;
429 }
280921de 430
280921de
TR		 431 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
432 if (ddc) {
433 panel->ddc = of_find_i2c_adapter_by_node(ddc);
434 of_node_put(ddc);
435
0fe1564b
SR		 436 if (!panel->ddc)
437 return -EPROBE_DEFER;
280921de
TR		 438 }
439
b8a2948f 440 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
e362cc6a 441 panel_simple_parse_panel_timing_node(dev, panel, &dt);
b8a2948f 442
9a2654c0
LP		 443 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
444 desc->connector_type);
280921de 445
0fe1564b
SR		 446 err = drm_panel_of_backlight(&panel->base);
447 if (err)
448 goto free_ddc;
449
280921de
TR		 450 err = drm_panel_add(&panel->base);
451 if (err < 0)
452 goto free_ddc;
453
454 dev_set_drvdata(dev, panel);
455
456 return 0;
457
458free_ddc:
459 if (panel->ddc)
460 put_device(&panel->ddc->dev);
280921de
TR		 461
462 return err;
463}
464
465static int panel_simple_remove(struct device *dev)
466{
467 struct panel_simple *panel = dev_get_drvdata(dev);
468
280921de 469 drm_panel_remove(&panel->base);
0fe1564b
SR		 470 drm_panel_disable(&panel->base);
471 drm_panel_unprepare(&panel->base);
280921de
TR		 472
473 if (panel->ddc)
474 put_device(&panel->ddc->dev);
475
280921de
TR		 476 return 0;
477}
478
d02fd93e
TR		 479static void panel_simple_shutdown(struct device *dev)
480{
481 struct panel_simple *panel = dev_get_drvdata(dev);
482
0fe1564b
SR		 483 drm_panel_disable(&panel->base);
484 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 485}
486
966fea78
YF		 487static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
488 .clock = 9000,
489 .hdisplay = 480,
490 .hsync_start = 480 + 2,
491 .hsync_end = 480 + 2 + 41,
492 .htotal = 480 + 2 + 41 + 2,
493 .vdisplay = 272,
494 .vsync_start = 272 + 2,
495 .vsync_end = 272 + 2 + 10,
496 .vtotal = 272 + 2 + 10 + 2,
497 .vrefresh = 60,
498 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
499};
500
501static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
502 .modes = &ampire_am_480272h3tmqw_t01h_mode,
503 .num_modes = 1,
504 .bpc = 8,
505 .size = {
506 .width = 105,
507 .height = 67,
508 },
509 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
510};
511
1c550fa1
PZ		 512static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
513 .clock = 33333,
514 .hdisplay = 800,
515 .hsync_start = 800 + 0,
516 .hsync_end = 800 + 0 + 255,
517 .htotal = 800 + 0 + 255 + 0,
518 .vdisplay = 480,
519 .vsync_start = 480 + 2,
520 .vsync_end = 480 + 2 + 45,
521 .vtotal = 480 + 2 + 45 + 0,
522 .vrefresh = 60,
523 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
524};
525
526static const struct panel_desc ampire_am800480r3tmqwa1h = {
527 .modes = &ampire_am800480r3tmqwa1h_mode,
528 .num_modes = 1,
529 .bpc = 6,
530 .size = {
531 .width = 152,
532 .height = 91,
533 },
534 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
535};
536
c479450f
SS		 537static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
538 .pixelclock = { 26400000, 33300000, 46800000 },
539 .hactive = { 800, 800, 800 },
540 .hfront_porch = { 16, 210, 354 },
541 .hback_porch = { 45, 36, 6 },
542 .hsync_len = { 1, 10, 40 },
543 .vactive = { 480, 480, 480 },
544 .vfront_porch = { 7, 22, 147 },
545 .vback_porch = { 22, 13, 3 },
546 .vsync_len = { 1, 10, 20 },
547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
548 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
549};
550
551static const struct panel_desc armadeus_st0700_adapt = {
552 .timings = &santek_st0700i5y_rbslw_f_timing,
553 .num_timings = 1,
554 .bpc = 6,
555 .size = {
556 .width = 154,
557 .height = 86,
558 },
559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
561};
562
280921de
TR		 563static const struct drm_display_mode auo_b101aw03_mode = {
564 .clock = 51450,
565 .hdisplay = 1024,
566 .hsync_start = 1024 + 156,
567 .hsync_end = 1024 + 156 + 8,
568 .htotal = 1024 + 156 + 8 + 156,
569 .vdisplay = 600,
570 .vsync_start = 600 + 16,
571 .vsync_end = 600 + 16 + 6,
572 .vtotal = 600 + 16 + 6 + 16,
573 .vrefresh = 60,
574};
575
576static const struct panel_desc auo_b101aw03 = {
577 .modes = &auo_b101aw03_mode,
578 .num_modes = 1,
0208d511 579 .bpc = 6,
280921de
TR		 580 .size = {
581 .width = 223,
582 .height = 125,
583 },
584};
585
374bf825
DA		 586static const struct display_timing auo_b101ean01_timing = {
587 .pixelclock = { 65300000, 72500000, 75000000 },
588 .hactive = { 1280, 1280, 1280 },
589 .hfront_porch = { 18, 119, 119 },
590 .hback_porch = { 21, 21, 21 },
591 .hsync_len = { 32, 32, 32 },
592 .vactive = { 800, 800, 800 },
593 .vfront_porch = { 4, 4, 4 },
594 .vback_porch = { 8, 8, 8 },
595 .vsync_len = { 18, 20, 20 },
a531bc3d
HL		 596};
597
598static const struct panel_desc auo_b101ean01 = {
374bf825
DA		 599 .timings = &auo_b101ean01_timing,
600 .num_timings = 1,
a531bc3d
HL		 601 .bpc = 6,
602 .size = {
603 .width = 217,
604 .height = 136,
605 },
606};
607
dac746e0
RC		 608static const struct drm_display_mode auo_b101xtn01_mode = {
609 .clock = 72000,
610 .hdisplay = 1366,
611 .hsync_start = 1366 + 20,
612 .hsync_end = 1366 + 20 + 70,
613 .htotal = 1366 + 20 + 70,
614 .vdisplay = 768,
615 .vsync_start = 768 + 14,
616 .vsync_end = 768 + 14 + 42,
617 .vtotal = 768 + 14 + 42,
618 .vrefresh = 60,
619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
620};
621
622static const struct panel_desc auo_b101xtn01 = {
623 .modes = &auo_b101xtn01_mode,
624 .num_modes = 1,
625 .bpc = 6,
626 .size = {
627 .width = 223,
628 .height = 125,
629 },
630};
631
da458286
RC		 632static const struct drm_display_mode auo_b116xak01_mode = {
633 .clock = 69300,
634 .hdisplay = 1366,
635 .hsync_start = 1366 + 48,
636 .hsync_end = 1366 + 48 + 32,
637 .htotal = 1366 + 48 + 32 + 10,
638 .vdisplay = 768,
639 .vsync_start = 768 + 4,
640 .vsync_end = 768 + 4 + 6,
641 .vtotal = 768 + 4 + 6 + 15,
642 .vrefresh = 60,
643 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
644};
645
646static const struct panel_desc auo_b116xak01 = {
647 .modes = &auo_b116xak01_mode,
648 .num_modes = 1,
649 .bpc = 6,
650 .size = {
651 .width = 256,
652 .height = 144,
653 },
654 .delay = {
655 .hpd_absent_delay = 200,
656 },
657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
658 .connector_type = DRM_MODE_CONNECTOR_eDP,
659};
660
e35e305e
AK		 661static const struct drm_display_mode auo_b116xw03_mode = {
662 .clock = 70589,
663 .hdisplay = 1366,
664 .hsync_start = 1366 + 40,
665 .hsync_end = 1366 + 40 + 40,
666 .htotal = 1366 + 40 + 40 + 32,
667 .vdisplay = 768,
668 .vsync_start = 768 + 10,
669 .vsync_end = 768 + 10 + 12,
670 .vtotal = 768 + 10 + 12 + 6,
671 .vrefresh = 60,
672};
673
674static const struct panel_desc auo_b116xw03 = {
675 .modes = &auo_b116xw03_mode,
676 .num_modes = 1,
677 .bpc = 6,
678 .size = {
679 .width = 256,
680 .height = 144,
681 },
682};
683
a333f7ad
SM		 684static const struct drm_display_mode auo_b133xtn01_mode = {
685 .clock = 69500,
686 .hdisplay = 1366,
687 .hsync_start = 1366 + 48,
688 .hsync_end = 1366 + 48 + 32,
689 .htotal = 1366 + 48 + 32 + 20,
690 .vdisplay = 768,
691 .vsync_start = 768 + 3,
692 .vsync_end = 768 + 3 + 6,
693 .vtotal = 768 + 3 + 6 + 13,
694 .vrefresh = 60,
695};
696
697static const struct panel_desc auo_b133xtn01 = {
698 .modes = &auo_b133xtn01_mode,
699 .num_modes = 1,
0208d511 700 .bpc = 6,
a333f7ad
SM		 701 .size = {
702 .width = 293,
703 .height = 165,
704 },
705};
706
3e51d609
AK		 707static const struct drm_display_mode auo_b133htn01_mode = {
708 .clock = 150660,
709 .hdisplay = 1920,
710 .hsync_start = 1920 + 172,
711 .hsync_end = 1920 + 172 + 80,
712 .htotal = 1920 + 172 + 80 + 60,
713 .vdisplay = 1080,
714 .vsync_start = 1080 + 25,
715 .vsync_end = 1080 + 25 + 10,
716 .vtotal = 1080 + 25 + 10 + 10,
717 .vrefresh = 60,
718};
719
720static const struct panel_desc auo_b133htn01 = {
721 .modes = &auo_b133htn01_mode,
722 .num_modes = 1,
d7a839cd 723 .bpc = 6,
3e51d609
AK		 724 .size = {
725 .width = 293,
726 .height = 165,
727 },
728 .delay = {
729 .prepare = 105,
730 .enable = 20,
731 .unprepare = 50,
732 },
733};
734
bccfaffb
LM		 735static const struct display_timing auo_g070vvn01_timings = {
736 .pixelclock = { 33300000, 34209000, 45000000 },
737 .hactive = { 800, 800, 800 },
738 .hfront_porch = { 20, 40, 200 },
739 .hback_porch = { 87, 40, 1 },
740 .hsync_len = { 1, 48, 87 },
741 .vactive = { 480, 480, 480 },
742 .vfront_porch = { 5, 13, 200 },
743 .vback_porch = { 31, 31, 29 },
744 .vsync_len = { 1, 1, 3 },
745};
746
747static const struct panel_desc auo_g070vvn01 = {
748 .timings = &auo_g070vvn01_timings,
749 .num_timings = 1,
750 .bpc = 8,
751 .size = {
752 .width = 152,
753 .height = 91,
754 },
755 .delay = {
756 .prepare = 200,
757 .enable = 50,
758 .disable = 50,
759 .unprepare = 1000,
760 },
761};
762
4fb86404
AG		 763static const struct drm_display_mode auo_g101evn010_mode = {
764 .clock = 68930,
765 .hdisplay = 1280,
766 .hsync_start = 1280 + 82,
767 .hsync_end = 1280 + 82 + 2,
768 .htotal = 1280 + 82 + 2 + 84,
769 .vdisplay = 800,
770 .vsync_start = 800 + 8,
771 .vsync_end = 800 + 8 + 2,
772 .vtotal = 800 + 8 + 2 + 6,
773 .vrefresh = 60,
774};
775
776static const struct panel_desc auo_g101evn010 = {
777 .modes = &auo_g101evn010_mode,
778 .num_modes = 1,
779 .bpc = 6,
780 .size = {
781 .width = 216,
782 .height = 135,
783 },
784 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
785};
786
4451c287
CF		 787static const struct drm_display_mode auo_g104sn02_mode = {
788 .clock = 40000,
789 .hdisplay = 800,
790 .hsync_start = 800 + 40,
791 .hsync_end = 800 + 40 + 216,
792 .htotal = 800 + 40 + 216 + 128,
793 .vdisplay = 600,
794 .vsync_start = 600 + 10,
795 .vsync_end = 600 + 10 + 35,
796 .vtotal = 600 + 10 + 35 + 2,
797 .vrefresh = 60,
798};
799
800static const struct panel_desc auo_g104sn02 = {
801 .modes = &auo_g104sn02_mode,
802 .num_modes = 1,
803 .bpc = 8,
804 .size = {
805 .width = 211,
806 .height = 158,
807 },
808};
809
697035c6
LS		 810static const struct display_timing auo_g133han01_timings = {
811 .pixelclock = { 134000000, 141200000, 149000000 },
812 .hactive = { 1920, 1920, 1920 },
813 .hfront_porch = { 39, 58, 77 },
814 .hback_porch = { 59, 88, 117 },
815 .hsync_len = { 28, 42, 56 },
816 .vactive = { 1080, 1080, 1080 },
817 .vfront_porch = { 3, 8, 11 },
818 .vback_porch = { 5, 14, 19 },
819 .vsync_len = { 4, 14, 19 },
820};
821
822static const struct panel_desc auo_g133han01 = {
823 .timings = &auo_g133han01_timings,
824 .num_timings = 1,
825 .bpc = 8,
826 .size = {
827 .width = 293,
828 .height = 165,
829 },
830 .delay = {
831 .prepare = 200,
832 .enable = 50,
833 .disable = 50,
834 .unprepare = 1000,
835 },
836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 837 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 838};
839
8c31f603
LS		 840static const struct display_timing auo_g185han01_timings = {
841 .pixelclock = { 120000000, 144000000, 175000000 },
842 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 843 .hfront_porch = { 36, 120, 148 },
844 .hback_porch = { 24, 88, 108 },
845 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 846 .vactive = { 1080, 1080, 1080 },
847 .vfront_porch = { 6, 10, 40 },
848 .vback_porch = { 2, 5, 20 },
849 .vsync_len = { 2, 5, 20 },
850};
851
852static const struct panel_desc auo_g185han01 = {
853 .timings = &auo_g185han01_timings,
854 .num_timings = 1,
855 .bpc = 8,
856 .size = {
857 .width = 409,
858 .height = 230,
859 },
860 .delay = {
861 .prepare = 50,
862 .enable = 200,
863 .disable = 110,
864 .unprepare = 1000,
865 },
866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 868};
869
70c0d5b7
LS		 870static const struct display_timing auo_p320hvn03_timings = {
871 .pixelclock = { 106000000, 148500000, 164000000 },
872 .hactive = { 1920, 1920, 1920 },
873 .hfront_porch = { 25, 50, 130 },
874 .hback_porch = { 25, 50, 130 },
875 .hsync_len = { 20, 40, 105 },
876 .vactive = { 1080, 1080, 1080 },
877 .vfront_porch = { 8, 17, 150 },
878 .vback_porch = { 8, 17, 150 },
879 .vsync_len = { 4, 11, 100 },
880};
881
882static const struct panel_desc auo_p320hvn03 = {
883 .timings = &auo_p320hvn03_timings,
884 .num_timings = 1,
885 .bpc = 8,
886 .size = {
887 .width = 698,
888 .height = 393,
889 },
890 .delay = {
891 .prepare = 1,
892 .enable = 450,
893 .unprepare = 500,
894 },
2554f154 895 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 896 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 897};
898
7ee933a1
HS		 899static const struct drm_display_mode auo_t215hvn01_mode = {
900 .clock = 148800,
901 .hdisplay = 1920,
902 .hsync_start = 1920 + 88,
903 .hsync_end = 1920 + 88 + 44,
904 .htotal = 1920 + 88 + 44 + 148,
905 .vdisplay = 1080,
906 .vsync_start = 1080 + 4,
907 .vsync_end = 1080 + 4 + 5,
908 .vtotal = 1080 + 4 + 5 + 36,
909 .vrefresh = 60,
910};
911
912static const struct panel_desc auo_t215hvn01 = {
913 .modes = &auo_t215hvn01_mode,
914 .num_modes = 1,
915 .bpc = 8,
916 .size = {
917 .width = 430,
918 .height = 270,
919 },
920 .delay = {
921 .disable = 5,
922 .unprepare = 1000,
923 }
924};
925
d47df633
PZ		 926static const struct drm_display_mode avic_tm070ddh03_mode = {
927 .clock = 51200,
928 .hdisplay = 1024,
929 .hsync_start = 1024 + 160,
930 .hsync_end = 1024 + 160 + 4,
931 .htotal = 1024 + 160 + 4 + 156,
932 .vdisplay = 600,
933 .vsync_start = 600 + 17,
934 .vsync_end = 600 + 17 + 1,
935 .vtotal = 600 + 17 + 1 + 17,
936 .vrefresh = 60,
937};
938
939static const struct panel_desc avic_tm070ddh03 = {
940 .modes = &avic_tm070ddh03_mode,
941 .num_modes = 1,
942 .bpc = 8,
943 .size = {
944 .width = 154,
945 .height = 90,
946 },
947 .delay = {
948 .prepare = 20,
949 .enable = 200,
950 .disable = 200,
951 },
952};
953
7ad8b41c
CYT		 954static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
955 .clock = 30000,
956 .hdisplay = 800,
957 .hsync_start = 800 + 40,
958 .hsync_end = 800 + 40 + 48,
959 .htotal = 800 + 40 + 48 + 40,
960 .vdisplay = 480,
961 .vsync_start = 480 + 13,
962 .vsync_end = 480 + 13 + 3,
963 .vtotal = 480 + 13 + 3 + 29,
964};
965
966static const struct panel_desc bananapi_s070wv20_ct16 = {
967 .modes = &bananapi_s070wv20_ct16_mode,
968 .num_modes = 1,
969 .bpc = 6,
970 .size = {
971 .width = 154,
972 .height = 86,
973 },
974};
975
ae8cf41b 976static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 977 .clock = 42105,
ae8cf41b 978 .hdisplay = 1024,
e077e2f5
AH		 979 .hsync_start = 1024 + 30,
980 .hsync_end = 1024 + 30 + 30,
981 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 982 .vdisplay = 600,
e077e2f5
AH		 983 .vsync_start = 600 + 10,
984 .vsync_end = 600 + 10 + 10,
985 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 986 .vrefresh = 60,
987};
988
989static const struct panel_desc boe_hv070wsa = {
990 .modes = &boe_hv070wsa_mode,
991 .num_modes = 1,
992 .size = {
993 .width = 154,
994 .height = 90,
995 },
996};
997
cac1a411
CW		 998static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
999 {
1000 .clock = 71900,
1001 .hdisplay = 1280,
1002 .hsync_start = 1280 + 48,
1003 .hsync_end = 1280 + 48 + 32,
1004 .htotal = 1280 + 48 + 32 + 80,
1005 .vdisplay = 800,
1006 .vsync_start = 800 + 3,
1007 .vsync_end = 800 + 3 + 5,
1008 .vtotal = 800 + 3 + 5 + 24,
1009 .vrefresh = 60,
1010 },
1011 {
1012 .clock = 57500,
1013 .hdisplay = 1280,
1014 .hsync_start = 1280 + 48,
1015 .hsync_end = 1280 + 48 + 32,
1016 .htotal = 1280 + 48 + 32 + 80,
1017 .vdisplay = 800,
1018 .vsync_start = 800 + 3,
1019 .vsync_end = 800 + 3 + 5,
1020 .vtotal = 800 + 3 + 5 + 24,
1021 .vrefresh = 48,
1022 },
1023};
1024
1025static const struct panel_desc boe_nv101wxmn51 = {
1026 .modes = boe_nv101wxmn51_modes,
1027 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1028 .bpc = 8,
1029 .size = {
1030 .width = 217,
1031 .height = 136,
1032 },
1033 .delay = {
1034 .prepare = 210,
1035 .enable = 50,
1036 .unprepare = 160,
1037 },
1038};
1039
a5119818
TS		 1040static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1041 {
1042 .clock = 148500,
1043 .hdisplay = 1920,
1044 .hsync_start = 1920 + 48,
1045 .hsync_end = 1920 + 48 + 32,
1046 .htotal = 2200,
1047 .vdisplay = 1080,
1048 .vsync_start = 1080 + 3,
1049 .vsync_end = 1080 + 3 + 5,
1050 .vtotal = 1125,
1051 .vrefresh = 60,
1052 },
1053};
1054
1055static const struct panel_desc boe_nv140fhmn49 = {
1056 .modes = boe_nv140fhmn49_modes,
1057 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1058 .bpc = 6,
1059 .size = {
1060 .width = 309,
1061 .height = 174,
1062 },
1063 .delay = {
1064 .prepare = 210,
1065 .enable = 50,
1066 .unprepare = 160,
1067 },
1068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1069 .connector_type = DRM_MODE_CONNECTOR_eDP,
1070};
1071
e58edce6
GB		 1072static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1073 .clock = 9000,
1074 .hdisplay = 480,
1075 .hsync_start = 480 + 5,
1076 .hsync_end = 480 + 5 + 5,
1077 .htotal = 480 + 5 + 5 + 40,
1078 .vdisplay = 272,
1079 .vsync_start = 272 + 8,
1080 .vsync_end = 272 + 8 + 8,
1081 .vtotal = 272 + 8 + 8 + 8,
1082 .vrefresh = 60,
1083 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1084};
1085
1086static const struct panel_desc cdtech_s043wq26h_ct7 = {
1087 .modes = &cdtech_s043wq26h_ct7_mode,
1088 .num_modes = 1,
1089 .bpc = 8,
1090 .size = {
1091 .width = 95,
1092 .height = 54,
1093 },
88bc4178 1094 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1095};
1096
982f944e
GB		 1097static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1098 .clock = 35000,
1099 .hdisplay = 800,
1100 .hsync_start = 800 + 40,
1101 .hsync_end = 800 + 40 + 40,
1102 .htotal = 800 + 40 + 40 + 48,
1103 .vdisplay = 480,
1104 .vsync_start = 480 + 29,
1105 .vsync_end = 480 + 29 + 13,
1106 .vtotal = 480 + 29 + 13 + 3,
1107 .vrefresh = 60,
1108 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1109};
1110
1111static const struct panel_desc cdtech_s070wv95_ct16 = {
1112 .modes = &cdtech_s070wv95_ct16_mode,
1113 .num_modes = 1,
1114 .bpc = 8,
1115 .size = {
1116 .width = 154,
1117 .height = 85,
1118 },
1119};
1120
2cb35c80
RL		 1121static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1122 .clock = 66770,
1123 .hdisplay = 800,
1124 .hsync_start = 800 + 49,
1125 .hsync_end = 800 + 49 + 33,
1126 .htotal = 800 + 49 + 33 + 17,
1127 .vdisplay = 1280,
1128 .vsync_start = 1280 + 1,
1129 .vsync_end = 1280 + 1 + 7,
1130 .vtotal = 1280 + 1 + 7 + 15,
1131 .vrefresh = 60,
1132 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1133};
1134
1135static const struct panel_desc chunghwa_claa070wp03xg = {
1136 .modes = &chunghwa_claa070wp03xg_mode,
1137 .num_modes = 1,
1138 .bpc = 6,
1139 .size = {
1140 .width = 94,
1141 .height = 150,
1142 },
1143};
1144
4c930757
SW		 1145static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1146 .clock = 72070,
1147 .hdisplay = 1366,
1148 .hsync_start = 1366 + 58,
1149 .hsync_end = 1366 + 58 + 58,
1150 .htotal = 1366 + 58 + 58 + 58,
1151 .vdisplay = 768,
1152 .vsync_start = 768 + 4,
1153 .vsync_end = 768 + 4 + 4,
1154 .vtotal = 768 + 4 + 4 + 4,
1155 .vrefresh = 60,
1156};
1157
1158static const struct panel_desc chunghwa_claa101wa01a = {
1159 .modes = &chunghwa_claa101wa01a_mode,
1160 .num_modes = 1,
0208d511 1161 .bpc = 6,
4c930757
SW		 1162 .size = {
1163 .width = 220,
1164 .height = 120,
1165 },
1166};
1167
280921de
TR		 1168static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1169 .clock = 69300,
1170 .hdisplay = 1366,
1171 .hsync_start = 1366 + 48,
1172 .hsync_end = 1366 + 48 + 32,
1173 .htotal = 1366 + 48 + 32 + 20,
1174 .vdisplay = 768,
1175 .vsync_start = 768 + 16,
1176 .vsync_end = 768 + 16 + 8,
1177 .vtotal = 768 + 16 + 8 + 16,
1178 .vrefresh = 60,
1179};
1180
1181static const struct panel_desc chunghwa_claa101wb01 = {
1182 .modes = &chunghwa_claa101wb01_mode,
1183 .num_modes = 1,
0208d511 1184 .bpc = 6,
280921de
TR		 1185 .size = {
1186 .width = 223,
1187 .height = 125,
1188 },
1189};
1190
97ceb1fb
MV		 1191static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1192 .clock = 33260,
1193 .hdisplay = 800,
1194 .hsync_start = 800 + 40,
1195 .hsync_end = 800 + 40 + 128,
1196 .htotal = 800 + 40 + 128 + 88,
1197 .vdisplay = 480,
1198 .vsync_start = 480 + 10,
1199 .vsync_end = 480 + 10 + 2,
1200 .vtotal = 480 + 10 + 2 + 33,
1201 .vrefresh = 60,
1202 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1203};
1204
1205static const struct panel_desc dataimage_scf0700c48ggu18 = {
1206 .modes = &dataimage_scf0700c48ggu18_mode,
1207 .num_modes = 1,
1208 .bpc = 8,
1209 .size = {
1210 .width = 152,
1211 .height = 91,
1212 },
1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1214 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1215};
1216
0ca0c827
PZ		 1217static const struct display_timing dlc_dlc0700yzg_1_timing = {
1218 .pixelclock = { 45000000, 51200000, 57000000 },
1219 .hactive = { 1024, 1024, 1024 },
1220 .hfront_porch = { 100, 106, 113 },
1221 .hback_porch = { 100, 106, 113 },
1222 .hsync_len = { 100, 108, 114 },
1223 .vactive = { 600, 600, 600 },
1224 .vfront_porch = { 8, 11, 15 },
1225 .vback_porch = { 8, 11, 15 },
1226 .vsync_len = { 9, 13, 15 },
1227 .flags = DISPLAY_FLAGS_DE_HIGH,
1228};
1229
1230static const struct panel_desc dlc_dlc0700yzg_1 = {
1231 .timings = &dlc_dlc0700yzg_1_timing,
1232 .num_timings = 1,
1233 .bpc = 6,
1234 .size = {
1235 .width = 154,
1236 .height = 86,
1237 },
1238 .delay = {
1239 .prepare = 30,
1240 .enable = 200,
1241 .disable = 200,
1242 },
1243 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1245};
1246
6cbe7cd1
MF		 1247static const struct display_timing dlc_dlc1010gig_timing = {
1248 .pixelclock = { 68900000, 71100000, 73400000 },
1249 .hactive = { 1280, 1280, 1280 },
1250 .hfront_porch = { 43, 53, 63 },
1251 .hback_porch = { 43, 53, 63 },
1252 .hsync_len = { 44, 54, 64 },
1253 .vactive = { 800, 800, 800 },
1254 .vfront_porch = { 5, 8, 11 },
1255 .vback_porch = { 5, 8, 11 },
1256 .vsync_len = { 5, 7, 11 },
1257 .flags = DISPLAY_FLAGS_DE_HIGH,
1258};
1259
1260static const struct panel_desc dlc_dlc1010gig = {
1261 .timings = &dlc_dlc1010gig_timing,
1262 .num_timings = 1,
1263 .bpc = 8,
1264 .size = {
1265 .width = 216,
1266 .height = 135,
1267 },
1268 .delay = {
1269 .prepare = 60,
1270 .enable = 150,
1271 .disable = 100,
1272 .unprepare = 60,
1273 },
1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 1276};
1277
c2d24af6
AP		 1278static const struct drm_display_mode edt_et035012dm6_mode = {
1279 .clock = 6500,
1280 .hdisplay = 320,
1281 .hsync_start = 320 + 20,
1282 .hsync_end = 320 + 20 + 30,
1283 .htotal = 320 + 20 + 68,
1284 .vdisplay = 240,
1285 .vsync_start = 240 + 4,
1286 .vsync_end = 240 + 4 + 4,
1287 .vtotal = 240 + 4 + 4 + 14,
1288 .vrefresh = 60,
1289 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1290};
1291
1292static const struct panel_desc edt_et035012dm6 = {
1293 .modes = &edt_et035012dm6_mode,
1294 .num_modes = 1,
1295 .bpc = 8,
1296 .size = {
1297 .width = 70,
1298 .height = 52,
1299 },
1300 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1301 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1302};
1303
fd819bff
MV		 1304static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1305 .clock = 9000,
1306 .hdisplay = 480,
1307 .hsync_start = 480 + 2,
1308 .hsync_end = 480 + 2 + 41,
1309 .htotal = 480 + 2 + 41 + 2,
1310 .vdisplay = 272,
1311 .vsync_start = 272 + 2,
1312 .vsync_end = 272 + 2 + 10,
1313 .vtotal = 272 + 2 + 10 + 2,
1314 .vrefresh = 60,
1315 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1316};
1317
1318static const struct panel_desc edt_etm0430g0dh6 = {
1319 .modes = &edt_etm0430g0dh6_mode,
1320 .num_modes = 1,
1321 .bpc = 6,
1322 .size = {
1323 .width = 95,
1324 .height = 54,
1325 },
1326};
1327
26ab0065
SA		 1328static const struct drm_display_mode edt_et057090dhu_mode = {
1329 .clock = 25175,
1330 .hdisplay = 640,
1331 .hsync_start = 640 + 16,
1332 .hsync_end = 640 + 16 + 30,
1333 .htotal = 640 + 16 + 30 + 114,
1334 .vdisplay = 480,
1335 .vsync_start = 480 + 10,
1336 .vsync_end = 480 + 10 + 3,
1337 .vtotal = 480 + 10 + 3 + 32,
1338 .vrefresh = 60,
1339 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1340};
1341
1342static const struct panel_desc edt_et057090dhu = {
1343 .modes = &edt_et057090dhu_mode,
1344 .num_modes = 1,
0208d511 1345 .bpc = 6,
26ab0065
SA		 1346 .size = {
1347 .width = 115,
1348 .height = 86,
1349 },
eaeebffa 1350 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1351 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
26ab0065
SA		 1352};
1353
fff5de45
PZ		 1354static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1355 .clock = 33260,
1356 .hdisplay = 800,
1357 .hsync_start = 800 + 40,
1358 .hsync_end = 800 + 40 + 128,
1359 .htotal = 800 + 40 + 128 + 88,
1360 .vdisplay = 480,
1361 .vsync_start = 480 + 10,
1362 .vsync_end = 480 + 10 + 2,
1363 .vtotal = 480 + 10 + 2 + 33,
1364 .vrefresh = 60,
1365 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1366};
1367
1368static const struct panel_desc edt_etm0700g0dh6 = {
1369 .modes = &edt_etm0700g0dh6_mode,
1370 .num_modes = 1,
0208d511 1371 .bpc = 6,
fff5de45
PZ		 1372 .size = {
1373 .width = 152,
1374 .height = 91,
1375 },
eaeebffa 1376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1377 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
fff5de45
PZ		 1378};
1379
aa7e6455
JT		 1380static const struct panel_desc edt_etm0700g0bdh6 = {
1381 .modes = &edt_etm0700g0dh6_mode,
1382 .num_modes = 1,
1383 .bpc = 6,
1384 .size = {
1385 .width = 152,
1386 .height = 91,
1387 },
1388 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 1389 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
aa7e6455
JT		 1390};
1391
9158e3c3
MF		 1392static const struct display_timing evervision_vgg804821_timing = {
1393 .pixelclock = { 27600000, 33300000, 50000000 },
1394 .hactive = { 800, 800, 800 },
1395 .hfront_porch = { 40, 66, 70 },
1396 .hback_porch = { 40, 67, 70 },
1397 .hsync_len = { 40, 67, 70 },
1398 .vactive = { 480, 480, 480 },
1399 .vfront_porch = { 6, 10, 10 },
1400 .vback_porch = { 7, 11, 11 },
1401 .vsync_len = { 7, 11, 11 },
1402 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1403 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1404 DISPLAY_FLAGS_SYNC_NEGEDGE,
1405};
1406
1407static const struct panel_desc evervision_vgg804821 = {
1408 .timings = &evervision_vgg804821_timing,
1409 .num_timings = 1,
1410 .bpc = 8,
1411 .size = {
1412 .width = 108,
1413 .height = 64,
1414 },
1415 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1416 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1417};
1418
102932b0
BB		 1419static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1420 .clock = 32260,
1421 .hdisplay = 800,
1422 .hsync_start = 800 + 168,
1423 .hsync_end = 800 + 168 + 64,
1424 .htotal = 800 + 168 + 64 + 88,
1425 .vdisplay = 480,
1426 .vsync_start = 480 + 37,
1427 .vsync_end = 480 + 37 + 2,
1428 .vtotal = 480 + 37 + 2 + 8,
1429 .vrefresh = 60,
1430};
1431
1432static const struct panel_desc foxlink_fl500wvr00_a0t = {
1433 .modes = &foxlink_fl500wvr00_a0t_mode,
1434 .num_modes = 1,
d7a839cd 1435 .bpc = 8,
102932b0
BB		 1436 .size = {
1437 .width = 108,
1438 .height = 65,
1439 },
bb276cb3 1440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 1441};
1442
3be20710
JT		 1443static const struct drm_display_mode friendlyarm_hd702e_mode = {
1444 .clock = 67185,
1445 .hdisplay = 800,
1446 .hsync_start = 800 + 20,
1447 .hsync_end = 800 + 20 + 24,
1448 .htotal = 800 + 20 + 24 + 20,
1449 .vdisplay = 1280,
1450 .vsync_start = 1280 + 4,
1451 .vsync_end = 1280 + 4 + 8,
1452 .vtotal = 1280 + 4 + 8 + 4,
1453 .vrefresh = 60,
1454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1455};
1456
1457static const struct panel_desc friendlyarm_hd702e = {
1458 .modes = &friendlyarm_hd702e_mode,
1459 .num_modes = 1,
1460 .size = {
1461 .width = 94,
1462 .height = 151,
1463 },
1464};
1465
d435a2af
PZ		 1466static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1467 .clock = 9000,
1468 .hdisplay = 480,
1469 .hsync_start = 480 + 5,
1470 .hsync_end = 480 + 5 + 1,
1471 .htotal = 480 + 5 + 1 + 40,
1472 .vdisplay = 272,
1473 .vsync_start = 272 + 8,
1474 .vsync_end = 272 + 8 + 1,
1475 .vtotal = 272 + 8 + 1 + 8,
1476 .vrefresh = 60,
1477};
1478
1479static const struct panel_desc giantplus_gpg482739qs5 = {
1480 .modes = &giantplus_gpg482739qs5_mode,
1481 .num_modes = 1,
1482 .bpc = 8,
1483 .size = {
1484 .width = 95,
1485 .height = 54,
1486 },
33536a09 1487 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 1488};
1489
2c6574a9
PC		 1490static const struct display_timing giantplus_gpm940b0_timing = {
1491 .pixelclock = { 13500000, 27000000, 27500000 },
1492 .hactive = { 320, 320, 320 },
1493 .hfront_porch = { 14, 686, 718 },
1494 .hback_porch = { 50, 70, 255 },
1495 .hsync_len = { 1, 1, 1 },
1496 .vactive = { 240, 240, 240 },
1497 .vfront_porch = { 1, 1, 179 },
1498 .vback_porch = { 1, 21, 31 },
1499 .vsync_len = { 1, 1, 6 },
1500 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1501};
1502
1503static const struct panel_desc giantplus_gpm940b0 = {
1504 .timings = &giantplus_gpm940b0_timing,
1505 .num_timings = 1,
1506 .bpc = 8,
1507 .size = {
1508 .width = 60,
1509 .height = 45,
1510 },
1511 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1512 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1513};
1514
ab07725a
PZ		 1515static const struct display_timing hannstar_hsd070pww1_timing = {
1516 .pixelclock = { 64300000, 71100000, 82000000 },
1517 .hactive = { 1280, 1280, 1280 },
1518 .hfront_porch = { 1, 1, 10 },
1519 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 1520 /*
1521 * According to the data sheet, the minimum horizontal blanking interval
1522 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1523 * minimum working horizontal blanking interval to be 60 clocks.
1524 */
1525 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 1526 .vactive = { 800, 800, 800 },
1527 .vfront_porch = { 1, 1, 10 },
1528 .vback_porch = { 1, 1, 10 },
1529 .vsync_len = { 1, 21, 203 },
1530 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 1531};
1532
1533static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 1534 .timings = &hannstar_hsd070pww1_timing,
1535 .num_timings = 1,
a853205e
PZ		 1536 .bpc = 6,
1537 .size = {
1538 .width = 151,
1539 .height = 94,
1540 },
58d6a7bc 1541 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1542 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 1543};
1544
c0d607e5
EN		 1545static const struct display_timing hannstar_hsd100pxn1_timing = {
1546 .pixelclock = { 55000000, 65000000, 75000000 },
1547 .hactive = { 1024, 1024, 1024 },
1548 .hfront_porch = { 40, 40, 40 },
1549 .hback_porch = { 220, 220, 220 },
1550 .hsync_len = { 20, 60, 100 },
1551 .vactive = { 768, 768, 768 },
1552 .vfront_porch = { 7, 7, 7 },
1553 .vback_porch = { 21, 21, 21 },
1554 .vsync_len = { 10, 10, 10 },
1555 .flags = DISPLAY_FLAGS_DE_HIGH,
1556};
1557
1558static const struct panel_desc hannstar_hsd100pxn1 = {
1559 .timings = &hannstar_hsd100pxn1_timing,
1560 .num_timings = 1,
1561 .bpc = 6,
1562 .size = {
1563 .width = 203,
1564 .height = 152,
1565 },
4946b043 1566 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1567 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 1568};
1569
61ac0bf8
LS		 1570static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1571 .clock = 33333,
1572 .hdisplay = 800,
1573 .hsync_start = 800 + 85,
1574 .hsync_end = 800 + 85 + 86,
1575 .htotal = 800 + 85 + 86 + 85,
1576 .vdisplay = 480,
1577 .vsync_start = 480 + 16,
1578 .vsync_end = 480 + 16 + 13,
1579 .vtotal = 480 + 16 + 13 + 16,
1580 .vrefresh = 60,
1581};
1582
1583static const struct panel_desc hitachi_tx23d38vm0caa = {
1584 .modes = &hitachi_tx23d38vm0caa_mode,
1585 .num_modes = 1,
1586 .bpc = 6,
1587 .size = {
1588 .width = 195,
1589 .height = 117,
1590 },
6c684e3b
PZ		 1591 .delay = {
1592 .enable = 160,
1593 .disable = 160,
1594 },
61ac0bf8
LS		 1595};
1596
41bcceb4
NF		 1597static const struct drm_display_mode innolux_at043tn24_mode = {
1598 .clock = 9000,
1599 .hdisplay = 480,
1600 .hsync_start = 480 + 2,
1601 .hsync_end = 480 + 2 + 41,
1602 .htotal = 480 + 2 + 41 + 2,
1603 .vdisplay = 272,
1604 .vsync_start = 272 + 2,
a483159d
PZ		 1605 .vsync_end = 272 + 2 + 10,
1606 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 1607 .vrefresh = 60,
1608 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1609};
1610
1611static const struct panel_desc innolux_at043tn24 = {
1612 .modes = &innolux_at043tn24_mode,
1613 .num_modes = 1,
1614 .bpc = 8,
1615 .size = {
1616 .width = 95,
1617 .height = 54,
1618 },
1619 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1620 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 1621};
1622
4fc24ab3
RB		 1623static const struct drm_display_mode innolux_at070tn92_mode = {
1624 .clock = 33333,
1625 .hdisplay = 800,
1626 .hsync_start = 800 + 210,
1627 .hsync_end = 800 + 210 + 20,
1628 .htotal = 800 + 210 + 20 + 46,
1629 .vdisplay = 480,
1630 .vsync_start = 480 + 22,
1631 .vsync_end = 480 + 22 + 10,
1632 .vtotal = 480 + 22 + 23 + 10,
1633 .vrefresh = 60,
1634};
1635
1636static const struct panel_desc innolux_at070tn92 = {
1637 .modes = &innolux_at070tn92_mode,
1638 .num_modes = 1,
1639 .size = {
1640 .width = 154,
1641 .height = 86,
1642 },
1643 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1644};
1645
a5d2ade6
CF		 1646static const struct display_timing innolux_g070y2_l01_timing = {
1647 .pixelclock = { 28000000, 29500000, 32000000 },
1648 .hactive = { 800, 800, 800 },
1649 .hfront_porch = { 61, 91, 141 },
1650 .hback_porch = { 60, 90, 140 },
1651 .hsync_len = { 12, 12, 12 },
1652 .vactive = { 480, 480, 480 },
1653 .vfront_porch = { 4, 9, 30 },
1654 .vback_porch = { 4, 8, 28 },
1655 .vsync_len = { 2, 2, 2 },
1656 .flags = DISPLAY_FLAGS_DE_HIGH,
1657};
1658
1659static const struct panel_desc innolux_g070y2_l01 = {
1660 .timings = &innolux_g070y2_l01_timing,
1661 .num_timings = 1,
1662 .bpc = 6,
1663 .size = {
1664 .width = 152,
1665 .height = 91,
1666 },
1667 .delay = {
1668 .prepare = 10,
1669 .enable = 100,
1670 .disable = 100,
1671 .unprepare = 800,
1672 },
1673 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1674 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 1675};
1676
1e29b840
MO		 1677static const struct display_timing innolux_g101ice_l01_timing = {
1678 .pixelclock = { 60400000, 71100000, 74700000 },
1679 .hactive = { 1280, 1280, 1280 },
1680 .hfront_porch = { 41, 80, 100 },
1681 .hback_porch = { 40, 79, 99 },
1682 .hsync_len = { 1, 1, 1 },
1683 .vactive = { 800, 800, 800 },
1684 .vfront_porch = { 5, 11, 14 },
1685 .vback_porch = { 4, 11, 14 },
1686 .vsync_len = { 1, 1, 1 },
1687 .flags = DISPLAY_FLAGS_DE_HIGH,
1688};
1689
1690static const struct panel_desc innolux_g101ice_l01 = {
1691 .timings = &innolux_g101ice_l01_timing,
1692 .num_timings = 1,
1693 .bpc = 8,
1694 .size = {
1695 .width = 217,
1696 .height = 135,
1697 },
1698 .delay = {
1699 .enable = 200,
1700 .disable = 200,
1701 },
1702 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1703 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 1704};
1705
4ae13e48
LS		 1706static const struct display_timing innolux_g121i1_l01_timing = {
1707 .pixelclock = { 67450000, 71000000, 74550000 },
1708 .hactive = { 1280, 1280, 1280 },
1709 .hfront_porch = { 40, 80, 160 },
1710 .hback_porch = { 39, 79, 159 },
1711 .hsync_len = { 1, 1, 1 },
1712 .vactive = { 800, 800, 800 },
1713 .vfront_porch = { 5, 11, 100 },
1714 .vback_porch = { 4, 11, 99 },
1715 .vsync_len = { 1, 1, 1 },
d731f661
LS		 1716};
1717
1718static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 1719 .timings = &innolux_g121i1_l01_timing,
1720 .num_timings = 1,
d731f661
LS		 1721 .bpc = 6,
1722 .size = {
1723 .width = 261,
1724 .height = 163,
1725 },
4ae13e48
LS		 1726 .delay = {
1727 .enable = 200,
1728 .disable = 20,
1729 },
1730 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1731 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 1732};
1733
f8fa17ba
AB		 1734static const struct drm_display_mode innolux_g121x1_l03_mode = {
1735 .clock = 65000,
1736 .hdisplay = 1024,
1737 .hsync_start = 1024 + 0,
1738 .hsync_end = 1024 + 1,
1739 .htotal = 1024 + 0 + 1 + 320,
1740 .vdisplay = 768,
1741 .vsync_start = 768 + 38,
1742 .vsync_end = 768 + 38 + 1,
1743 .vtotal = 768 + 38 + 1 + 0,
1744 .vrefresh = 60,
2e8c5eb9 1745 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 1746};
1747
1748static const struct panel_desc innolux_g121x1_l03 = {
1749 .modes = &innolux_g121x1_l03_mode,
1750 .num_modes = 1,
1751 .bpc = 6,
1752 .size = {
1753 .width = 246,
1754 .height = 185,
1755 },
1756 .delay = {
1757 .enable = 200,
1758 .unprepare = 200,
1759 .disable = 400,
1760 },
1761};
1762
d719cbe9
DA		 1763/*
1764 * Datasheet specifies that at 60 Hz refresh rate:
1765 * - total horizontal time: { 1506, 1592, 1716 }
1766 * - total vertical time: { 788, 800, 868 }
1767 *
1768 * ...but doesn't go into exactly how that should be split into a front
1769 * porch, back porch, or sync length. For now we'll leave a single setting
1770 * here which allows a bit of tweaking of the pixel clock at the expense of
1771 * refresh rate.
1772 */
1773static const struct display_timing innolux_n116bge_timing = {
1774 .pixelclock = { 72600000, 76420000, 80240000 },
1775 .hactive = { 1366, 1366, 1366 },
1776 .hfront_porch = { 136, 136, 136 },
1777 .hback_porch = { 60, 60, 60 },
1778 .hsync_len = { 30, 30, 30 },
1779 .vactive = { 768, 768, 768 },
1780 .vfront_porch = { 8, 8, 8 },
1781 .vback_porch = { 12, 12, 12 },
1782 .vsync_len = { 12, 12, 12 },
1783 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
0a2288c0
TR		 1784};
1785
1786static const struct panel_desc innolux_n116bge = {
d719cbe9
DA		 1787 .timings = &innolux_n116bge_timing,
1788 .num_timings = 1,
0a2288c0
TR		 1789 .bpc = 6,
1790 .size = {
1791 .width = 256,
1792 .height = 144,
1793 },
1794};
1795
ea44739d
AB		 1796static const struct drm_display_mode innolux_n156bge_l21_mode = {
1797 .clock = 69300,
1798 .hdisplay = 1366,
1799 .hsync_start = 1366 + 16,
1800 .hsync_end = 1366 + 16 + 34,
1801 .htotal = 1366 + 16 + 34 + 50,
1802 .vdisplay = 768,
1803 .vsync_start = 768 + 2,
1804 .vsync_end = 768 + 2 + 6,
1805 .vtotal = 768 + 2 + 6 + 12,
1806 .vrefresh = 60,
1807};
1808
1809static const struct panel_desc innolux_n156bge_l21 = {
1810 .modes = &innolux_n156bge_l21_mode,
1811 .num_modes = 1,
0208d511 1812 .bpc = 6,
ea44739d
AB		 1813 .size = {
1814 .width = 344,
1815 .height = 193,
1816 },
1817};
1818
8f054b6f 1819static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 1820 .clock = 206016,
1821 .hdisplay = 2160,
1822 .hsync_start = 2160 + 48,
1823 .hsync_end = 2160 + 48 + 32,
1824 .htotal = 2160 + 48 + 32 + 80,
1825 .vdisplay = 1440,
1826 .vsync_start = 1440 + 3,
1827 .vsync_end = 1440 + 3 + 10,
1828 .vtotal = 1440 + 3 + 10 + 27,
1829 .vrefresh = 60,
1830 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1831};
1832
8f054b6f
DA		 1833static const struct panel_desc innolux_p120zdg_bf1 = {
1834 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 1835 .num_modes = 1,
1836 .bpc = 8,
1837 .size = {
8f054b6f
DA		 1838 .width = 254,
1839 .height = 169,
da50bd42 1840 },
22fd99e9 1841 .delay = {
625d3b5c 1842 .hpd_absent_delay = 200,
22fd99e9
SP		 1843 .unprepare = 500,
1844 },
da50bd42 1845};
1846
bccac3f1
MG		 1847static const struct drm_display_mode innolux_zj070na_01p_mode = {
1848 .clock = 51501,
1849 .hdisplay = 1024,
1850 .hsync_start = 1024 + 128,
1851 .hsync_end = 1024 + 128 + 64,
1852 .htotal = 1024 + 128 + 64 + 128,
1853 .vdisplay = 600,
1854 .vsync_start = 600 + 16,
1855 .vsync_end = 600 + 16 + 4,
1856 .vtotal = 600 + 16 + 4 + 16,
1857 .vrefresh = 60,
1858};
1859
1860static const struct panel_desc innolux_zj070na_01p = {
1861 .modes = &innolux_zj070na_01p_mode,
1862 .num_modes = 1,
1863 .bpc = 6,
1864 .size = {
81598846
TR		 1865 .width = 154,
1866 .height = 90,
bccac3f1
MG		 1867 },
1868};
1869
14bf60c4
LM		 1870static const struct display_timing koe_tx14d24vm1bpa_timing = {
1871 .pixelclock = { 5580000, 5850000, 6200000 },
1872 .hactive = { 320, 320, 320 },
1873 .hfront_porch = { 30, 30, 30 },
1874 .hback_porch = { 30, 30, 30 },
1875 .hsync_len = { 1, 5, 17 },
1876 .vactive = { 240, 240, 240 },
1877 .vfront_porch = { 6, 6, 6 },
1878 .vback_porch = { 5, 5, 5 },
1879 .vsync_len = { 1, 2, 11 },
1880 .flags = DISPLAY_FLAGS_DE_HIGH,
1881};
1882
1883static const struct panel_desc koe_tx14d24vm1bpa = {
1884 .timings = &koe_tx14d24vm1bpa_timing,
1885 .num_timings = 1,
1886 .bpc = 6,
1887 .size = {
1888 .width = 115,
1889 .height = 86,
1890 },
1891};
1892
8cfe8341
JT		 1893static const struct display_timing koe_tx31d200vm0baa_timing = {
1894 .pixelclock = { 39600000, 43200000, 48000000 },
1895 .hactive = { 1280, 1280, 1280 },
1896 .hfront_porch = { 16, 36, 56 },
1897 .hback_porch = { 16, 36, 56 },
1898 .hsync_len = { 8, 8, 8 },
1899 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 1900 .vfront_porch = { 6, 21, 33 },
1901 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 1902 .vsync_len = { 8, 8, 8 },
1903 .flags = DISPLAY_FLAGS_DE_HIGH,
1904};
1905
1906static const struct panel_desc koe_tx31d200vm0baa = {
1907 .timings = &koe_tx31d200vm0baa_timing,
1908 .num_timings = 1,
1909 .bpc = 6,
1910 .size = {
1911 .width = 292,
1912 .height = 109,
1913 },
1914 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1915 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 1916};
1917
8def22e5
LS		 1918static const struct display_timing kyo_tcg121xglp_timing = {
1919 .pixelclock = { 52000000, 65000000, 71000000 },
1920 .hactive = { 1024, 1024, 1024 },
1921 .hfront_porch = { 2, 2, 2 },
1922 .hback_porch = { 2, 2, 2 },
1923 .hsync_len = { 86, 124, 244 },
1924 .vactive = { 768, 768, 768 },
1925 .vfront_porch = { 2, 2, 2 },
1926 .vback_porch = { 2, 2, 2 },
1927 .vsync_len = { 6, 34, 73 },
1928 .flags = DISPLAY_FLAGS_DE_HIGH,
1929};
1930
1931static const struct panel_desc kyo_tcg121xglp = {
1932 .timings = &kyo_tcg121xglp_timing,
1933 .num_timings = 1,
1934 .bpc = 8,
1935 .size = {
1936 .width = 246,
1937 .height = 184,
1938 },
1939 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1940 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 1941};
1942
27abdd83
PK		 1943static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1944 .clock = 7000,
1945 .hdisplay = 320,
1946 .hsync_start = 320 + 20,
1947 .hsync_end = 320 + 20 + 30,
1948 .htotal = 320 + 20 + 30 + 38,
1949 .vdisplay = 240,
1950 .vsync_start = 240 + 4,
1951 .vsync_end = 240 + 4 + 3,
1952 .vtotal = 240 + 4 + 3 + 15,
1953 .vrefresh = 60,
1954};
1955
1956static const struct panel_desc lemaker_bl035_rgb_002 = {
1957 .modes = &lemaker_bl035_rgb_002_mode,
1958 .num_modes = 1,
1959 .size = {
1960 .width = 70,
1961 .height = 52,
1962 },
1963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1964 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1965};
1966
dd015002
HS		 1967static const struct drm_display_mode lg_lb070wv8_mode = {
1968 .clock = 33246,
1969 .hdisplay = 800,
1970 .hsync_start = 800 + 88,
1971 .hsync_end = 800 + 88 + 80,
1972 .htotal = 800 + 88 + 80 + 88,
1973 .vdisplay = 480,
1974 .vsync_start = 480 + 10,
1975 .vsync_end = 480 + 10 + 25,
1976 .vtotal = 480 + 10 + 25 + 10,
1977 .vrefresh = 60,
1978};
1979
1980static const struct panel_desc lg_lb070wv8 = {
1981 .modes = &lg_lb070wv8_mode,
1982 .num_modes = 1,
1983 .bpc = 16,
1984 .size = {
1985 .width = 151,
1986 .height = 91,
1987 },
1988 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1989 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 1990};
1991
c5ece402
YY		 1992static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1993 .clock = 200000,
1994 .hdisplay = 1536,
1995 .hsync_start = 1536 + 12,
1996 .hsync_end = 1536 + 12 + 16,
1997 .htotal = 1536 + 12 + 16 + 48,
1998 .vdisplay = 2048,
1999 .vsync_start = 2048 + 8,
2000 .vsync_end = 2048 + 8 + 4,
2001 .vtotal = 2048 + 8 + 4 + 8,
2002 .vrefresh = 60,
2003 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2004};
2005
2006static const struct panel_desc lg_lp079qx1_sp0v = {
2007 .modes = &lg_lp079qx1_sp0v_mode,
2008 .num_modes = 1,
2009 .size = {
2010 .width = 129,
2011 .height = 171,
2012 },
2013};
2014
0355dde2
YY		 2015static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
2016 .clock = 205210,
2017 .hdisplay = 2048,
2018 .hsync_start = 2048 + 150,
2019 .hsync_end = 2048 + 150 + 5,
2020 .htotal = 2048 + 150 + 5 + 5,
2021 .vdisplay = 1536,
2022 .vsync_start = 1536 + 3,
2023 .vsync_end = 1536 + 3 + 1,
2024 .vtotal = 1536 + 3 + 1 + 9,
2025 .vrefresh = 60,
2026};
2027
2028static const struct panel_desc lg_lp097qx1_spa1 = {
2029 .modes = &lg_lp097qx1_spa1_mode,
2030 .num_modes = 1,
2031 .size = {
2032 .width = 208,
2033 .height = 147,
2034 },
2035};
2036
690d8fa7
JS		 2037static const struct drm_display_mode lg_lp120up1_mode = {
2038 .clock = 162300,
2039 .hdisplay = 1920,
2040 .hsync_start = 1920 + 40,
2041 .hsync_end = 1920 + 40 + 40,
2042 .htotal = 1920 + 40 + 40+ 80,
2043 .vdisplay = 1280,
2044 .vsync_start = 1280 + 4,
2045 .vsync_end = 1280 + 4 + 4,
2046 .vtotal = 1280 + 4 + 4 + 12,
2047 .vrefresh = 60,
2048};
2049
2050static const struct panel_desc lg_lp120up1 = {
2051 .modes = &lg_lp120up1_mode,
2052 .num_modes = 1,
2053 .bpc = 8,
2054 .size = {
2055 .width = 267,
2056 .height = 183,
2057 },
2058};
2059
ec7c5653
TR		 2060static const struct drm_display_mode lg_lp129qe_mode = {
2061 .clock = 285250,
2062 .hdisplay = 2560,
2063 .hsync_start = 2560 + 48,
2064 .hsync_end = 2560 + 48 + 32,
2065 .htotal = 2560 + 48 + 32 + 80,
2066 .vdisplay = 1700,
2067 .vsync_start = 1700 + 3,
2068 .vsync_end = 1700 + 3 + 10,
2069 .vtotal = 1700 + 3 + 10 + 36,
2070 .vrefresh = 60,
2071};
2072
2073static const struct panel_desc lg_lp129qe = {
2074 .modes = &lg_lp129qe_mode,
2075 .num_modes = 1,
0208d511 2076 .bpc = 8,
ec7c5653
TR		 2077 .size = {
2078 .width = 272,
2079 .height = 181,
2080 },
2081};
2082
65c766ca
LM		 2083static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2084 .clock = 30400,
2085 .hdisplay = 800,
2086 .hsync_start = 800 + 0,
2087 .hsync_end = 800 + 1,
2088 .htotal = 800 + 0 + 1 + 160,
2089 .vdisplay = 480,
2090 .vsync_start = 480 + 0,
2091 .vsync_end = 480 + 48 + 1,
2092 .vtotal = 480 + 48 + 1 + 0,
2093 .vrefresh = 60,
2094 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2095};
2096
0d35408a
AF		 2097static const struct drm_display_mode logicpd_type_28_mode = {
2098 .clock = 9000,
2099 .hdisplay = 480,
2100 .hsync_start = 480 + 3,
2101 .hsync_end = 480 + 3 + 42,
2102 .htotal = 480 + 3 + 42 + 2,
2103
2104 .vdisplay = 272,
2105 .vsync_start = 272 + 2,
2106 .vsync_end = 272 + 2 + 11,
2107 .vtotal = 272 + 2 + 11 + 3,
2108 .vrefresh = 60,
2109 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2110};
2111
2112static const struct panel_desc logicpd_type_28 = {
2113 .modes = &logicpd_type_28_mode,
2114 .num_modes = 1,
2115 .bpc = 8,
2116 .size = {
2117 .width = 105,
2118 .height = 67,
2119 },
2120 .delay = {
2121 .prepare = 200,
2122 .enable = 200,
2123 .unprepare = 200,
2124 .disable = 200,
2125 },
2126 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2127 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2128 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2129};
2130
65c766ca
LM		 2131static const struct panel_desc mitsubishi_aa070mc01 = {
2132 .modes = &mitsubishi_aa070mc01_mode,
2133 .num_modes = 1,
2134 .bpc = 8,
2135 .size = {
2136 .width = 152,
2137 .height = 91,
2138 },
2139
2140 .delay = {
2141 .enable = 200,
2142 .unprepare = 200,
2143 .disable = 400,
2144 },
2145 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2146 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 2147 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2148};
2149
01bacc13
LS		 2150static const struct display_timing nec_nl12880bc20_05_timing = {
2151 .pixelclock = { 67000000, 71000000, 75000000 },
2152 .hactive = { 1280, 1280, 1280 },
2153 .hfront_porch = { 2, 30, 30 },
2154 .hback_porch = { 6, 100, 100 },
2155 .hsync_len = { 2, 30, 30 },
2156 .vactive = { 800, 800, 800 },
2157 .vfront_porch = { 5, 5, 5 },
2158 .vback_porch = { 11, 11, 11 },
2159 .vsync_len = { 7, 7, 7 },
2160};
2161
2162static const struct panel_desc nec_nl12880bc20_05 = {
2163 .timings = &nec_nl12880bc20_05_timing,
2164 .num_timings = 1,
2165 .bpc = 8,
2166 .size = {
2167 .width = 261,
2168 .height = 163,
2169 },
2170 .delay = {
2171 .enable = 50,
2172 .disable = 50,
2173 },
2174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2175 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 2176};
2177
c6e87f91 2178static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2179 .clock = 10870,
2180 .hdisplay = 480,
2181 .hsync_start = 480 + 2,
2182 .hsync_end = 480 + 2 + 41,
2183 .htotal = 480 + 2 + 41 + 2,
2184 .vdisplay = 272,
2185 .vsync_start = 272 + 2,
2186 .vsync_end = 272 + 2 + 4,
2187 .vtotal = 272 + 2 + 4 + 2,
2188 .vrefresh = 74,
4bc390c6 2189 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 2190};
2191
2192static const struct panel_desc nec_nl4827hc19_05b = {
2193 .modes = &nec_nl4827hc19_05b_mode,
2194 .num_modes = 1,
2195 .bpc = 8,
2196 .size = {
2197 .width = 95,
2198 .height = 54,
2199 },
2c80661d 2200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2201 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 2202};
2203
e6c2f066
MR		 2204static const struct drm_display_mode netron_dy_e231732_mode = {
2205 .clock = 66000,
2206 .hdisplay = 1024,
2207 .hsync_start = 1024 + 160,
2208 .hsync_end = 1024 + 160 + 70,
2209 .htotal = 1024 + 160 + 70 + 90,
2210 .vdisplay = 600,
2211 .vsync_start = 600 + 127,
2212 .vsync_end = 600 + 127 + 20,
2213 .vtotal = 600 + 127 + 20 + 3,
2214 .vrefresh = 60,
2215};
2216
2217static const struct panel_desc netron_dy_e231732 = {
2218 .modes = &netron_dy_e231732_mode,
2219 .num_modes = 1,
2220 .size = {
2221 .width = 154,
2222 .height = 87,
2223 },
2224 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2225};
2226
3b39ad7a
TV		 2227static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2228 .clock = 9000,
2229 .hdisplay = 480,
2230 .hsync_start = 480 + 2,
2231 .hsync_end = 480 + 2 + 41,
2232 .htotal = 480 + 2 + 41 + 2,
2233 .vdisplay = 272,
2234 .vsync_start = 272 + 2,
2235 .vsync_end = 272 + 2 + 10,
2236 .vtotal = 272 + 2 + 10 + 2,
2237 .vrefresh = 60,
2238 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2239};
2240
2241static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2242 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2243 .num_modes = 1,
2244 .bpc = 8,
2245 .size = {
2246 .width = 95,
2247 .height = 54,
2248 },
2249 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 2250 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2251 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3b39ad7a
TV		 2252};
2253
4177fa66
LS		 2254static const struct display_timing nlt_nl192108ac18_02d_timing = {
2255 .pixelclock = { 130000000, 148350000, 163000000 },
2256 .hactive = { 1920, 1920, 1920 },
2257 .hfront_porch = { 80, 100, 100 },
2258 .hback_porch = { 100, 120, 120 },
2259 .hsync_len = { 50, 60, 60 },
2260 .vactive = { 1080, 1080, 1080 },
2261 .vfront_porch = { 12, 30, 30 },
2262 .vback_porch = { 4, 10, 10 },
2263 .vsync_len = { 4, 5, 5 },
2264};
2265
2266static const struct panel_desc nlt_nl192108ac18_02d = {
2267 .timings = &nlt_nl192108ac18_02d_timing,
2268 .num_timings = 1,
2269 .bpc = 8,
2270 .size = {
2271 .width = 344,
2272 .height = 194,
2273 },
2274 .delay = {
2275 .unprepare = 500,
2276 },
2277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2278 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 2279};
2280
05ec0e45
FL		 2281static const struct drm_display_mode nvd_9128_mode = {
2282 .clock = 29500,
2283 .hdisplay = 800,
2284 .hsync_start = 800 + 130,
2285 .hsync_end = 800 + 130 + 98,
2286 .htotal = 800 + 0 + 130 + 98,
2287 .vdisplay = 480,
2288 .vsync_start = 480 + 10,
2289 .vsync_end = 480 + 10 + 50,
2290 .vtotal = 480 + 0 + 10 + 50,
2291};
2292
2293static const struct panel_desc nvd_9128 = {
2294 .modes = &nvd_9128_mode,
2295 .num_modes = 1,
2296 .bpc = 8,
2297 .size = {
2298 .width = 156,
2299 .height = 88,
2300 },
2301 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2302 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 2303};
2304
a99fb626
GB		 2305static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2306 .pixelclock = { 30000000, 30000000, 40000000 },
2307 .hactive = { 800, 800, 800 },
2308 .hfront_porch = { 40, 40, 40 },
2309 .hback_porch = { 40, 40, 40 },
2310 .hsync_len = { 1, 48, 48 },
2311 .vactive = { 480, 480, 480 },
2312 .vfront_porch = { 13, 13, 13 },
2313 .vback_porch = { 29, 29, 29 },
2314 .vsync_len = { 3, 3, 3 },
2315 .flags = DISPLAY_FLAGS_DE_HIGH,
2316};
2317
2318static const struct panel_desc okaya_rs800480t_7x0gp = {
2319 .timings = &okaya_rs800480t_7x0gp_timing,
2320 .num_timings = 1,
2321 .bpc = 6,
2322 .size = {
2323 .width = 154,
2324 .height = 87,
2325 },
2326 .delay = {
2327 .prepare = 41,
2328 .enable = 50,
2329 .unprepare = 41,
2330 .disable = 50,
2331 },
2332 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2333};
2334
cf5c9e6d
MR		 2335static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2336 .clock = 9000,
2337 .hdisplay = 480,
2338 .hsync_start = 480 + 5,
2339 .hsync_end = 480 + 5 + 30,
2340 .htotal = 480 + 5 + 30 + 10,
2341 .vdisplay = 272,
2342 .vsync_start = 272 + 8,
2343 .vsync_end = 272 + 8 + 5,
2344 .vtotal = 272 + 8 + 5 + 3,
2345 .vrefresh = 60,
2346};
2347
2348static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2349 .modes = &olimex_lcd_olinuxino_43ts_mode,
2350 .num_modes = 1,
2351 .size = {
30c6d7ab
JL		 2352 .width = 95,
2353 .height = 54,
cf5c9e6d 2354 },
5c2a7c6b 2355 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 2356};
2357
e8b6f561
EA		 2358/*
2359 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2360 * pixel clocks, but this is the timing that was being used in the Adafruit
2361 * installation instructions.
2362 */
2363static const struct drm_display_mode ontat_yx700wv03_mode = {
2364 .clock = 29500,
2365 .hdisplay = 800,
2366 .hsync_start = 824,
2367 .hsync_end = 896,
2368 .htotal = 992,
2369 .vdisplay = 480,
2370 .vsync_start = 483,
2371 .vsync_end = 493,
2372 .vtotal = 500,
2373 .vrefresh = 60,
2374 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2375};
2376
2377/*
2378 * Specification at:
2379 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2380 */
2381static const struct panel_desc ontat_yx700wv03 = {
2382 .modes = &ontat_yx700wv03_mode,
2383 .num_modes = 1,
2384 .bpc = 8,
2385 .size = {
2386 .width = 154,
2387 .height = 83,
2388 },
5651e5e0 2389 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 2390};
2391
9c31dcb6
NS		 2392static const struct drm_display_mode ortustech_com37h3m_mode = {
2393 .clock = 22153,
2394 .hdisplay = 480,
2395 .hsync_start = 480 + 8,
2396 .hsync_end = 480 + 8 + 10,
2397 .htotal = 480 + 8 + 10 + 10,
2398 .vdisplay = 640,
2399 .vsync_start = 640 + 4,
2400 .vsync_end = 640 + 4 + 3,
2401 .vtotal = 640 + 4 + 3 + 4,
2402 .vrefresh = 60,
2403 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2404};
2405
2406static const struct panel_desc ortustech_com37h3m = {
2407 .modes = &ortustech_com37h3m_mode,
2408 .num_modes = 1,
2409 .bpc = 8,
2410 .size = {
2411 .width = 56, /* 56.16mm */
2412 .height = 75, /* 74.88mm */
2413 },
2414 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2416 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2417};
2418
725c9d40
PZ		 2419static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2420 .clock = 25000,
2421 .hdisplay = 480,
2422 .hsync_start = 480 + 10,
2423 .hsync_end = 480 + 10 + 10,
2424 .htotal = 480 + 10 + 10 + 15,
2425 .vdisplay = 800,
2426 .vsync_start = 800 + 3,
2427 .vsync_end = 800 + 3 + 3,
2428 .vtotal = 800 + 3 + 3 + 3,
2429 .vrefresh = 60,
2430};
2431
2432static const struct panel_desc ortustech_com43h4m85ulc = {
2433 .modes = &ortustech_com43h4m85ulc_mode,
2434 .num_modes = 1,
2435 .bpc = 8,
2436 .size = {
2437 .width = 56,
2438 .height = 93,
2439 },
2440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
725c9d40
PZ		 2442};
2443
163f7a35
LP		 2444static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2445 .clock = 33000,
2446 .hdisplay = 800,
2447 .hsync_start = 800 + 210,
2448 .hsync_end = 800 + 210 + 30,
2449 .htotal = 800 + 210 + 30 + 16,
2450 .vdisplay = 480,
2451 .vsync_start = 480 + 22,
2452 .vsync_end = 480 + 22 + 13,
2453 .vtotal = 480 + 22 + 13 + 10,
2454 .vrefresh = 60,
2455 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2456};
2457
2458static const struct panel_desc osddisplays_osd070t1718_19ts = {
2459 .modes = &osddisplays_osd070t1718_19ts_mode,
2460 .num_modes = 1,
2461 .bpc = 8,
2462 .size = {
2463 .width = 152,
2464 .height = 91,
2465 },
2466 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2467 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
a793f0ee 2468 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 2469};
2470
4ba3e563
EH		 2471static const struct drm_display_mode pda_91_00156_a0_mode = {
2472 .clock = 33300,
2473 .hdisplay = 800,
2474 .hsync_start = 800 + 1,
2475 .hsync_end = 800 + 1 + 64,
2476 .htotal = 800 + 1 + 64 + 64,
2477 .vdisplay = 480,
2478 .vsync_start = 480 + 1,
2479 .vsync_end = 480 + 1 + 23,
2480 .vtotal = 480 + 1 + 23 + 22,
2481 .vrefresh = 60,
2482};
2483
2484static const struct panel_desc pda_91_00156_a0 = {
2485 .modes = &pda_91_00156_a0_mode,
2486 .num_modes = 1,
2487 .size = {
2488 .width = 152,
2489 .height = 91,
2490 },
2491 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2492};
2493
2494
d2a6f0f5
JW		 2495static const struct drm_display_mode qd43003c0_40_mode = {
2496 .clock = 9000,
2497 .hdisplay = 480,
2498 .hsync_start = 480 + 8,
2499 .hsync_end = 480 + 8 + 4,
2500 .htotal = 480 + 8 + 4 + 39,
2501 .vdisplay = 272,
2502 .vsync_start = 272 + 4,
2503 .vsync_end = 272 + 4 + 10,
2504 .vtotal = 272 + 4 + 10 + 2,
2505 .vrefresh = 60,
2506};
2507
2508static const struct panel_desc qd43003c0_40 = {
2509 .modes = &qd43003c0_40_mode,
2510 .num_modes = 1,
2511 .bpc = 8,
2512 .size = {
2513 .width = 95,
2514 .height = 53,
2515 },
2516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2517};
2518
23167fa9
JT		 2519static const struct display_timing rocktech_rk070er9427_timing = {
2520 .pixelclock = { 26400000, 33300000, 46800000 },
2521 .hactive = { 800, 800, 800 },
2522 .hfront_porch = { 16, 210, 354 },
2523 .hback_porch = { 46, 46, 46 },
2524 .hsync_len = { 1, 1, 1 },
2525 .vactive = { 480, 480, 480 },
2526 .vfront_porch = { 7, 22, 147 },
2527 .vback_porch = { 23, 23, 23 },
2528 .vsync_len = { 1, 1, 1 },
2529 .flags = DISPLAY_FLAGS_DE_HIGH,
2530};
2531
2532static const struct panel_desc rocktech_rk070er9427 = {
2533 .timings = &rocktech_rk070er9427_timing,
2534 .num_timings = 1,
2535 .bpc = 6,
2536 .size = {
2537 .width = 154,
2538 .height = 86,
2539 },
2540 .delay = {
2541 .prepare = 41,
2542 .enable = 50,
2543 .unprepare = 41,
2544 .disable = 50,
2545 },
2546 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2547};
2548
0330eaf3
YY		 2549static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2550 .clock = 271560,
2551 .hdisplay = 2560,
2552 .hsync_start = 2560 + 48,
2553 .hsync_end = 2560 + 48 + 32,
2554 .htotal = 2560 + 48 + 32 + 80,
2555 .vdisplay = 1600,
2556 .vsync_start = 1600 + 2,
2557 .vsync_end = 1600 + 2 + 5,
2558 .vtotal = 1600 + 2 + 5 + 57,
2559 .vrefresh = 60,
2560};
2561
2562static const struct panel_desc samsung_lsn122dl01_c01 = {
2563 .modes = &samsung_lsn122dl01_c01_mode,
2564 .num_modes = 1,
2565 .size = {
2566 .width = 263,
2567 .height = 164,
2568 },
2569};
2570
6d54e3d2
MD		 2571static const struct drm_display_mode samsung_ltn101nt05_mode = {
2572 .clock = 54030,
2573 .hdisplay = 1024,
2574 .hsync_start = 1024 + 24,
2575 .hsync_end = 1024 + 24 + 136,
2576 .htotal = 1024 + 24 + 136 + 160,
2577 .vdisplay = 600,
2578 .vsync_start = 600 + 3,
2579 .vsync_end = 600 + 3 + 6,
2580 .vtotal = 600 + 3 + 6 + 61,
2581 .vrefresh = 60,
2582};
2583
2584static const struct panel_desc samsung_ltn101nt05 = {
2585 .modes = &samsung_ltn101nt05_mode,
2586 .num_modes = 1,
0208d511 2587 .bpc = 6,
6d54e3d2 2588 .size = {
81598846
TR		 2589 .width = 223,
2590 .height = 125,
6d54e3d2
MD		 2591 },
2592};
2593
0c934306
SM		 2594static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2595 .clock = 76300,
2596 .hdisplay = 1366,
2597 .hsync_start = 1366 + 64,
2598 .hsync_end = 1366 + 64 + 48,
2599 .htotal = 1366 + 64 + 48 + 128,
2600 .vdisplay = 768,
2601 .vsync_start = 768 + 2,
2602 .vsync_end = 768 + 2 + 5,
2603 .vtotal = 768 + 2 + 5 + 17,
2604 .vrefresh = 60,
2605};
2606
2607static const struct panel_desc samsung_ltn140at29_301 = {
2608 .modes = &samsung_ltn140at29_301_mode,
2609 .num_modes = 1,
2610 .bpc = 6,
2611 .size = {
2612 .width = 320,
2613 .height = 187,
2614 },
2615};
2616
cd5e1cbe
JH		 2617static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2618 .clock = 168480,
2619 .hdisplay = 1920,
2620 .hsync_start = 1920 + 48,
2621 .hsync_end = 1920 + 48 + 32,
2622 .htotal = 1920 + 48 + 32 + 80,
2623 .vdisplay = 1280,
2624 .vsync_start = 1280 + 3,
2625 .vsync_end = 1280 + 3 + 10,
2626 .vtotal = 1280 + 3 + 10 + 57,
2627 .vrefresh = 60,
2628 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2629};
2630
2631static const struct panel_desc sharp_ld_d5116z01b = {
2632 .modes = &sharp_ld_d5116z01b_mode,
2633 .num_modes = 1,
2634 .bpc = 8,
2635 .size = {
2636 .width = 260,
2637 .height = 120,
2638 },
2639 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2640 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2641};
2642
dda0e4bd
NS		 2643static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2644 .clock = 33260,
2645 .hdisplay = 800,
2646 .hsync_start = 800 + 64,
2647 .hsync_end = 800 + 64 + 128,
2648 .htotal = 800 + 64 + 128 + 64,
2649 .vdisplay = 480,
2650 .vsync_start = 480 + 8,
2651 .vsync_end = 480 + 8 + 2,
2652 .vtotal = 480 + 8 + 2 + 35,
2653 .vrefresh = 60,
2654 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2655};
2656
2657static const struct panel_desc sharp_lq070y3dg3b = {
2658 .modes = &sharp_lq070y3dg3b_mode,
2659 .num_modes = 1,
2660 .bpc = 8,
2661 .size = {
2662 .width = 152, /* 152.4mm */
2663 .height = 91, /* 91.4mm */
2664 },
2665 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2666 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2667 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2668};
2669
03e3ec9a
VZ		 2670static const struct drm_display_mode sharp_lq035q7db03_mode = {
2671 .clock = 5500,
2672 .hdisplay = 240,
2673 .hsync_start = 240 + 16,
2674 .hsync_end = 240 + 16 + 7,
2675 .htotal = 240 + 16 + 7 + 5,
2676 .vdisplay = 320,
2677 .vsync_start = 320 + 9,
2678 .vsync_end = 320 + 9 + 1,
2679 .vtotal = 320 + 9 + 1 + 7,
2680 .vrefresh = 60,
2681};
2682
2683static const struct panel_desc sharp_lq035q7db03 = {
2684 .modes = &sharp_lq035q7db03_mode,
2685 .num_modes = 1,
2686 .bpc = 6,
2687 .size = {
2688 .width = 54,
2689 .height = 72,
2690 },
2691 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2692};
2693
592aa02b
JC		 2694static const struct display_timing sharp_lq101k1ly04_timing = {
2695 .pixelclock = { 60000000, 65000000, 80000000 },
2696 .hactive = { 1280, 1280, 1280 },
2697 .hfront_porch = { 20, 20, 20 },
2698 .hback_porch = { 20, 20, 20 },
2699 .hsync_len = { 10, 10, 10 },
2700 .vactive = { 800, 800, 800 },
2701 .vfront_porch = { 4, 4, 4 },
2702 .vback_porch = { 4, 4, 4 },
2703 .vsync_len = { 4, 4, 4 },
2704 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2705};
2706
2707static const struct panel_desc sharp_lq101k1ly04 = {
2708 .timings = &sharp_lq101k1ly04_timing,
2709 .num_timings = 1,
2710 .bpc = 8,
2711 .size = {
2712 .width = 217,
2713 .height = 136,
2714 },
2715 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 2716 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 2717};
2718
9f7bae2d
SP		 2719static const struct display_timing sharp_lq123p1jx31_timing = {
2720 .pixelclock = { 252750000, 252750000, 266604720 },
2721 .hactive = { 2400, 2400, 2400 },
2722 .hfront_porch = { 48, 48, 48 },
2723 .hback_porch = { 80, 80, 84 },
2724 .hsync_len = { 32, 32, 32 },
2725 .vactive = { 1600, 1600, 1600 },
2726 .vfront_porch = { 3, 3, 3 },
2727 .vback_porch = { 33, 33, 120 },
2728 .vsync_len = { 10, 10, 10 },
2729 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 2730};
2731
2732static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 2733 .timings = &sharp_lq123p1jx31_timing,
2734 .num_timings = 1,
5466a631 2735 .bpc = 8,
739c7de9
YY		 2736 .size = {
2737 .width = 259,
2738 .height = 173,
2739 },
a42f6e3f
YY		 2740 .delay = {
2741 .prepare = 110,
2742 .enable = 50,
2743 .unprepare = 550,
2744 },
739c7de9
YY		 2745};
2746
0f9cdd74
GL		 2747static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2748 .clock = 71100,
2749 .hdisplay = 1024,
2750 .hsync_start = 1024 + 168,
2751 .hsync_end = 1024 + 168 + 64,
2752 .htotal = 1024 + 168 + 64 + 88,
2753 .vdisplay = 768,
2754 .vsync_start = 768 + 37,
2755 .vsync_end = 768 + 37 + 2,
2756 .vtotal = 768 + 37 + 2 + 8,
2757 .vrefresh = 60,
2758};
2759
2760static const struct panel_desc sharp_lq150x1lg11 = {
2761 .modes = &sharp_lq150x1lg11_mode,
2762 .num_modes = 1,
2763 .bpc = 6,
2764 .size = {
2765 .width = 304,
2766 .height = 228,
2767 },
2768 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2769};
2770
f1bd37f3
PC		 2771static const struct display_timing sharp_ls020b1dd01d_timing = {
2772 .pixelclock = { 2000000, 4200000, 5000000 },
2773 .hactive = { 240, 240, 240 },
2774 .hfront_porch = { 66, 66, 66 },
2775 .hback_porch = { 1, 1, 1 },
2776 .hsync_len = { 1, 1, 1 },
2777 .vactive = { 160, 160, 160 },
2778 .vfront_porch = { 52, 52, 52 },
2779 .vback_porch = { 6, 6, 6 },
2780 .vsync_len = { 10, 10, 10 },
2781 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2782};
2783
2784static const struct panel_desc sharp_ls020b1dd01d = {
2785 .timings = &sharp_ls020b1dd01d_timing,
2786 .num_timings = 1,
2787 .bpc = 6,
2788 .size = {
2789 .width = 42,
2790 .height = 28,
2791 },
2792 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2793 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2794 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2795 | DRM_BUS_FLAG_SHARP_SIGNALS,
2796};
2797
9c6615bc
BB		 2798static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2799 .clock = 33300,
2800 .hdisplay = 800,
2801 .hsync_start = 800 + 1,
2802 .hsync_end = 800 + 1 + 64,
2803 .htotal = 800 + 1 + 64 + 64,
2804 .vdisplay = 480,
2805 .vsync_start = 480 + 1,
2806 .vsync_end = 480 + 1 + 23,
2807 .vtotal = 480 + 1 + 23 + 22,
2808 .vrefresh = 60,
2809};
2810
2811static const struct panel_desc shelly_sca07010_bfn_lnn = {
2812 .modes = &shelly_sca07010_bfn_lnn_mode,
2813 .num_modes = 1,
2814 .size = {
2815 .width = 152,
2816 .height = 91,
2817 },
2818 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2819};
2820
9bb34c4c
DA		 2821static const struct drm_display_mode starry_kr122ea0sra_mode = {
2822 .clock = 147000,
2823 .hdisplay = 1920,
2824 .hsync_start = 1920 + 16,
2825 .hsync_end = 1920 + 16 + 16,
2826 .htotal = 1920 + 16 + 16 + 32,
2827 .vdisplay = 1200,
2828 .vsync_start = 1200 + 15,
2829 .vsync_end = 1200 + 15 + 2,
2830 .vtotal = 1200 + 15 + 2 + 18,
2831 .vrefresh = 60,
2832 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2833};
2834
2835static const struct panel_desc starry_kr122ea0sra = {
2836 .modes = &starry_kr122ea0sra_mode,
2837 .num_modes = 1,
2838 .size = {
2839 .width = 263,
2840 .height = 164,
2841 },
c46b924b
BN		 2842 .delay = {
2843 .prepare = 10 + 200,
2844 .enable = 50,
2845 .unprepare = 10 + 500,
2846 },
9bb34c4c
DA		 2847};
2848
42161531
JS		 2849static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2850 .clock = 30000,
2851 .hdisplay = 800,
2852 .hsync_start = 800 + 39,
2853 .hsync_end = 800 + 39 + 47,
2854 .htotal = 800 + 39 + 47 + 39,
2855 .vdisplay = 480,
2856 .vsync_start = 480 + 13,
2857 .vsync_end = 480 + 13 + 2,
2858 .vtotal = 480 + 13 + 2 + 29,
2859 .vrefresh = 62,
2860};
2861
2862static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2863 .modes = &tfc_s9700rtwv43tr_01b_mode,
2864 .num_modes = 1,
2865 .bpc = 8,
2866 .size = {
2867 .width = 155,
2868 .height = 90,
2869 },
2870 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2872};
2873
adb973ef
GB		 2874static const struct display_timing tianma_tm070jdhg30_timing = {
2875 .pixelclock = { 62600000, 68200000, 78100000 },
2876 .hactive = { 1280, 1280, 1280 },
2877 .hfront_porch = { 15, 64, 159 },
2878 .hback_porch = { 5, 5, 5 },
2879 .hsync_len = { 1, 1, 256 },
2880 .vactive = { 800, 800, 800 },
2881 .vfront_porch = { 3, 40, 99 },
2882 .vback_porch = { 2, 2, 2 },
2883 .vsync_len = { 1, 1, 128 },
2884 .flags = DISPLAY_FLAGS_DE_HIGH,
2885};
2886
2887static const struct panel_desc tianma_tm070jdhg30 = {
2888 .timings = &tianma_tm070jdhg30_timing,
2889 .num_timings = 1,
2890 .bpc = 8,
2891 .size = {
2892 .width = 151,
2893 .height = 95,
2894 },
2895 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2896 .connector_type = DRM_MODE_CONNECTOR_LVDS,
adb973ef
GB		 2897};
2898
870a0b12
LM		 2899static const struct display_timing tianma_tm070rvhg71_timing = {
2900 .pixelclock = { 27700000, 29200000, 39600000 },
2901 .hactive = { 800, 800, 800 },
2902 .hfront_porch = { 12, 40, 212 },
2903 .hback_porch = { 88, 88, 88 },
2904 .hsync_len = { 1, 1, 40 },
2905 .vactive = { 480, 480, 480 },
2906 .vfront_porch = { 1, 13, 88 },
2907 .vback_porch = { 32, 32, 32 },
2908 .vsync_len = { 1, 1, 3 },
2909 .flags = DISPLAY_FLAGS_DE_HIGH,
2910};
2911
2912static const struct panel_desc tianma_tm070rvhg71 = {
2913 .timings = &tianma_tm070rvhg71_timing,
2914 .num_timings = 1,
2915 .bpc = 8,
2916 .size = {
2917 .width = 154,
2918 .height = 86,
2919 },
2920 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2921 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 2922};
2923
d8a0d6a3
LW		 2924static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2925 {
2926 .clock = 10000,
2927 .hdisplay = 320,
2928 .hsync_start = 320 + 50,
2929 .hsync_end = 320 + 50 + 6,
2930 .htotal = 320 + 50 + 6 + 38,
2931 .vdisplay = 240,
2932 .vsync_start = 240 + 3,
2933 .vsync_end = 240 + 3 + 1,
2934 .vtotal = 240 + 3 + 1 + 17,
2935 .vrefresh = 60,
2936 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2937 },
2938};
2939
2940static const struct panel_desc ti_nspire_cx_lcd_panel = {
2941 .modes = ti_nspire_cx_lcd_mode,
2942 .num_modes = 1,
2943 .bpc = 8,
2944 .size = {
2945 .width = 65,
2946 .height = 49,
2947 },
2948 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2949 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2950};
2951
2952static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2953 {
2954 .clock = 10000,
2955 .hdisplay = 320,
2956 .hsync_start = 320 + 6,
2957 .hsync_end = 320 + 6 + 6,
2958 .htotal = 320 + 6 + 6 + 6,
2959 .vdisplay = 240,
2960 .vsync_start = 240 + 0,
2961 .vsync_end = 240 + 0 + 1,
2962 .vtotal = 240 + 0 + 1 + 0,
2963 .vrefresh = 60,
2964 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2965 },
2966};
2967
2968static const struct panel_desc ti_nspire_classic_lcd_panel = {
2969 .modes = ti_nspire_classic_lcd_mode,
2970 .num_modes = 1,
2971 /* The grayscale panel has 8 bit for the color .. Y (black) */
2972 .bpc = 8,
2973 .size = {
2974 .width = 71,
2975 .height = 53,
2976 },
2977 /* This is the grayscale bus format */
2978 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2979 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2980};
2981
06e733e4
LS		 2982static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2983 .clock = 79500,
2984 .hdisplay = 1280,
2985 .hsync_start = 1280 + 192,
2986 .hsync_end = 1280 + 192 + 128,
2987 .htotal = 1280 + 192 + 128 + 64,
2988 .vdisplay = 768,
2989 .vsync_start = 768 + 20,
2990 .vsync_end = 768 + 20 + 7,
2991 .vtotal = 768 + 20 + 7 + 3,
2992 .vrefresh = 60,
2993};
2994
2995static const struct panel_desc toshiba_lt089ac29000 = {
2996 .modes = &toshiba_lt089ac29000_mode,
2997 .num_modes = 1,
2998 .size = {
2999 .width = 194,
3000 .height = 116,
3001 },
3002 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 3003 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
9a2654c0 3004 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 3005};
3006
227e4f40
BD		 3007static const struct drm_display_mode tpk_f07a_0102_mode = {
3008 .clock = 33260,
3009 .hdisplay = 800,
3010 .hsync_start = 800 + 40,
3011 .hsync_end = 800 + 40 + 128,
3012 .htotal = 800 + 40 + 128 + 88,
3013 .vdisplay = 480,
3014 .vsync_start = 480 + 10,
3015 .vsync_end = 480 + 10 + 2,
3016 .vtotal = 480 + 10 + 2 + 33,
3017 .vrefresh = 60,
3018};
3019
3020static const struct panel_desc tpk_f07a_0102 = {
3021 .modes = &tpk_f07a_0102_mode,
3022 .num_modes = 1,
3023 .size = {
3024 .width = 152,
3025 .height = 91,
3026 },
88bc4178 3027 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 3028};
3029
3030static const struct drm_display_mode tpk_f10a_0102_mode = {
3031 .clock = 45000,
3032 .hdisplay = 1024,
3033 .hsync_start = 1024 + 176,
3034 .hsync_end = 1024 + 176 + 5,
3035 .htotal = 1024 + 176 + 5 + 88,
3036 .vdisplay = 600,
3037 .vsync_start = 600 + 20,
3038 .vsync_end = 600 + 20 + 5,
3039 .vtotal = 600 + 20 + 5 + 25,
3040 .vrefresh = 60,
3041};
3042
3043static const struct panel_desc tpk_f10a_0102 = {
3044 .modes = &tpk_f10a_0102_mode,
3045 .num_modes = 1,
3046 .size = {
3047 .width = 223,
3048 .height = 125,
3049 },
3050};
3051
06a9dc65
MS		 3052static const struct display_timing urt_umsh_8596md_timing = {
3053 .pixelclock = { 33260000, 33260000, 33260000 },
3054 .hactive = { 800, 800, 800 },
3055 .hfront_porch = { 41, 41, 41 },
3056 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3057 .hsync_len = { 71, 128, 128 },
3058 .vactive = { 480, 480, 480 },
3059 .vfront_porch = { 10, 10, 10 },
3060 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3061 .vsync_len = { 2, 2, 2 },
3062 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3063 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3064};
3065
3066static const struct panel_desc urt_umsh_8596md_lvds = {
3067 .timings = &urt_umsh_8596md_timing,
3068 .num_timings = 1,
3069 .bpc = 6,
3070 .size = {
3071 .width = 152,
3072 .height = 91,
3073 },
3074 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 3075 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 3076};
3077
3078static const struct panel_desc urt_umsh_8596md_parallel = {
3079 .timings = &urt_umsh_8596md_timing,
3080 .num_timings = 1,
3081 .bpc = 6,
3082 .size = {
3083 .width = 152,
3084 .height = 91,
3085 },
3086 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3087};
3088
04206185
FE		 3089static const struct drm_display_mode vl050_8048nt_c01_mode = {
3090 .clock = 33333,
3091 .hdisplay = 800,
3092 .hsync_start = 800 + 210,
3093 .hsync_end = 800 + 210 + 20,
3094 .htotal = 800 + 210 + 20 + 46,
3095 .vdisplay = 480,
3096 .vsync_start = 480 + 22,
3097 .vsync_end = 480 + 22 + 10,
3098 .vtotal = 480 + 22 + 10 + 23,
3099 .vrefresh = 60,
3100 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3101};
3102
3103static const struct panel_desc vl050_8048nt_c01 = {
3104 .modes = &vl050_8048nt_c01_mode,
3105 .num_modes = 1,
3106 .bpc = 8,
3107 .size = {
3108 .width = 120,
3109 .height = 76,
3110 },
3111 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3112 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3113};
3114
e4bac408
RG		 3115static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3116 .clock = 6410,
3117 .hdisplay = 320,
3118 .hsync_start = 320 + 20,
3119 .hsync_end = 320 + 20 + 30,
3120 .htotal = 320 + 20 + 30 + 38,
3121 .vdisplay = 240,
3122 .vsync_start = 240 + 4,
3123 .vsync_end = 240 + 4 + 3,
3124 .vtotal = 240 + 4 + 3 + 15,
3125 .vrefresh = 60,
3126 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3127};
3128
3129static const struct panel_desc winstar_wf35ltiacd = {
3130 .modes = &winstar_wf35ltiacd_mode,
3131 .num_modes = 1,
3132 .bpc = 8,
3133 .size = {
3134 .width = 70,
3135 .height = 53,
3136 },
3137 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3138};
3139
fcec4163
LW		 3140static const struct drm_display_mode arm_rtsm_mode[] = {
3141 {
3142 .clock = 65000,
3143 .hdisplay = 1024,
3144 .hsync_start = 1024 + 24,
3145 .hsync_end = 1024 + 24 + 136,
3146 .htotal = 1024 + 24 + 136 + 160,
3147 .vdisplay = 768,
3148 .vsync_start = 768 + 3,
3149 .vsync_end = 768 + 3 + 6,
3150 .vtotal = 768 + 3 + 6 + 29,
3151 .vrefresh = 60,
3152 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3153 },
3154};
3155
3156static const struct panel_desc arm_rtsm = {
3157 .modes = arm_rtsm_mode,
3158 .num_modes = 1,
3159 .bpc = 8,
3160 .size = {
3161 .width = 400,
3162 .height = 300,
3163 },
3164 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3165};
3166
280921de
TR		 3167static const struct of_device_id platform_of_match[] = {
3168 {
966fea78
YF		 3169 .compatible = "ampire,am-480272h3tmqw-t01h",
3170 .data = &ampire_am_480272h3tmqw_t01h,
3171 }, {
1c550fa1
PZ		 3172 .compatible = "ampire,am800480r3tmqwa1h",
3173 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 3174 }, {
3175 .compatible = "arm,rtsm-display",
3176 .data = &arm_rtsm,
c479450f
SS		 3177 }, {
3178 .compatible = "armadeus,st0700-adapt",
3179 .data = &armadeus_st0700_adapt,
1c550fa1 3180 }, {
280921de
TR		 3181 .compatible = "auo,b101aw03",
3182 .data = &auo_b101aw03,
a531bc3d
HL		 3183 }, {
3184 .compatible = "auo,b101ean01",
3185 .data = &auo_b101ean01,
dac746e0
RC		 3186 }, {
3187 .compatible = "auo,b101xtn01",
3188 .data = &auo_b101xtn01,
da458286
RC		 3189 }, {
3190 .compatible = "auo,b116xa01",
3191 .data = &auo_b116xak01,
e35e305e
AK		 3192 }, {
3193 .compatible = "auo,b116xw03",
3194 .data = &auo_b116xw03,
3e51d609
AK		 3195 }, {
3196 .compatible = "auo,b133htn01",
3197 .data = &auo_b133htn01,
a333f7ad
SM		 3198 }, {
3199 .compatible = "auo,b133xtn01",
3200 .data = &auo_b133xtn01,
bccfaffb
LM		 3201 }, {
3202 .compatible = "auo,g070vvn01",
3203 .data = &auo_g070vvn01,
4fb86404
AG		 3204 }, {
3205 .compatible = "auo,g101evn010",
3206 .data = &auo_g101evn010,
4451c287
CF		 3207 }, {
3208 .compatible = "auo,g104sn02",
3209 .data = &auo_g104sn02,
697035c6
LS		 3210 }, {
3211 .compatible = "auo,g133han01",
3212 .data = &auo_g133han01,
8c31f603
LS		 3213 }, {
3214 .compatible = "auo,g185han01",
3215 .data = &auo_g185han01,
70c0d5b7
LS		 3216 }, {
3217 .compatible = "auo,p320hvn03",
3218 .data = &auo_p320hvn03,
7ee933a1
HS		 3219 }, {
3220 .compatible = "auo,t215hvn01",
3221 .data = &auo_t215hvn01,
d47df633
PZ		 3222 }, {
3223 .compatible = "avic,tm070ddh03",
3224 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 3225 }, {
3226 .compatible = "bananapi,s070wv20-ct16",
3227 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 3228 }, {
3229 .compatible = "boe,hv070wsa-100",
3230 .data = &boe_hv070wsa
cac1a411
CW		 3231 }, {
3232 .compatible = "boe,nv101wxmn51",
3233 .data = &boe_nv101wxmn51,
a5119818
TS		 3234 }, {
3235 .compatible = "boe,nv140fhmn49",
3236 .data = &boe_nv140fhmn49,
e58edce6
GB		 3237 }, {
3238 .compatible = "cdtech,s043wq26h-ct7",
3239 .data = &cdtech_s043wq26h_ct7,
982f944e
GB		 3240 }, {
3241 .compatible = "cdtech,s070wv95-ct16",
3242 .data = &cdtech_s070wv95_ct16,
2cb35c80
RL		 3243 }, {
3244 .compatible = "chunghwa,claa070wp03xg",
3245 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 3246 }, {
3247 .compatible = "chunghwa,claa101wa01a",
3248 .data = &chunghwa_claa101wa01a
280921de
TR		 3249 }, {
3250 .compatible = "chunghwa,claa101wb01",
3251 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 3252 }, {
3253 .compatible = "dataimage,scf0700c48ggu18",
3254 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 3255 }, {
3256 .compatible = "dlc,dlc0700yzg-1",
3257 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 3258 }, {
3259 .compatible = "dlc,dlc1010gig",
3260 .data = &dlc_dlc1010gig,
c2d24af6
AP		 3261 }, {
3262 .compatible = "edt,et035012dm6",
3263 .data = &edt_et035012dm6,
fd819bff
MV		 3264 }, {
3265 .compatible = "edt,etm0430g0dh6",
3266 .data = &edt_etm0430g0dh6,
26ab0065
SA		 3267 }, {
3268 .compatible = "edt,et057090dhu",
3269 .data = &edt_et057090dhu,
fff5de45
PZ		 3270 }, {
3271 .compatible = "edt,et070080dh6",
3272 .data = &edt_etm0700g0dh6,
3273 }, {
3274 .compatible = "edt,etm0700g0dh6",
3275 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 3276 }, {
3277 .compatible = "edt,etm0700g0bdh6",
3278 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 3279 }, {
3280 .compatible = "edt,etm0700g0edh6",
3281 .data = &edt_etm0700g0bdh6,
9158e3c3
MF		 3282 }, {
3283 .compatible = "evervision,vgg804821",
3284 .data = &evervision_vgg804821,
102932b0
BB		 3285 }, {
3286 .compatible = "foxlink,fl500wvr00-a0t",
3287 .data = &foxlink_fl500wvr00_a0t,
3be20710
JT		 3288 }, {
3289 .compatible = "friendlyarm,hd702e",
3290 .data = &friendlyarm_hd702e,
d435a2af
PZ		 3291 }, {
3292 .compatible = "giantplus,gpg482739qs5",
3293 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 3294 }, {
3295 .compatible = "giantplus,gpm940b0",
3296 .data = &giantplus_gpm940b0,
a853205e
PZ		 3297 }, {
3298 .compatible = "hannstar,hsd070pww1",
3299 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 3300 }, {
3301 .compatible = "hannstar,hsd100pxn1",
3302 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 3303 }, {
3304 .compatible = "hit,tx23d38vm0caa",
3305 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 3306 }, {
3307 .compatible = "innolux,at043tn24",
3308 .data = &innolux_at043tn24,
4fc24ab3
RB		 3309 }, {
3310 .compatible = "innolux,at070tn92",
3311 .data = &innolux_at070tn92,
1e29b840 3312 }, {
a5d2ade6
CF		 3313 .compatible = "innolux,g070y2-l01",
3314 .data = &innolux_g070y2_l01,
3315 }, {
3316 .compatible = "innolux,g101ice-l01",
1e29b840 3317 .data = &innolux_g101ice_l01
d731f661 3318 }, {
a5d2ade6 3319 .compatible = "innolux,g121i1-l01",
d731f661 3320 .data = &innolux_g121i1_l01
f8fa17ba
AB		 3321 }, {
3322 .compatible = "innolux,g121x1-l03",
3323 .data = &innolux_g121x1_l03,
0a2288c0
TR		 3324 }, {
3325 .compatible = "innolux,n116bge",
3326 .data = &innolux_n116bge,
ea44739d
AB		 3327 }, {
3328 .compatible = "innolux,n156bge-l21",
3329 .data = &innolux_n156bge_l21,
da50bd42 3330 }, {
8f054b6f
DA		 3331 .compatible = "innolux,p120zdg-bf1",
3332 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 3333 }, {
3334 .compatible = "innolux,zj070na-01p",
3335 .data = &innolux_zj070na_01p,
14bf60c4
LM		 3336 }, {
3337 .compatible = "koe,tx14d24vm1bpa",
3338 .data = &koe_tx14d24vm1bpa,
8cfe8341
JT		 3339 }, {
3340 .compatible = "koe,tx31d200vm0baa",
3341 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 3342 }, {
3343 .compatible = "kyo,tcg121xglp",
3344 .data = &kyo_tcg121xglp,
27abdd83
PK		 3345 }, {
3346 .compatible = "lemaker,bl035-rgb-002",
3347 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 3348 }, {
3349 .compatible = "lg,lb070wv8",
3350 .data = &lg_lb070wv8,
c5ece402
YY		 3351 }, {
3352 .compatible = "lg,lp079qx1-sp0v",
3353 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 3354 }, {
3355 .compatible = "lg,lp097qx1-spa1",
3356 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 3357 }, {
3358 .compatible = "lg,lp120up1",
3359 .data = &lg_lp120up1,
ec7c5653
TR		 3360 }, {
3361 .compatible = "lg,lp129qe",
3362 .data = &lg_lp129qe,
0d35408a
AF		 3363 }, {
3364 .compatible = "logicpd,type28",
3365 .data = &logicpd_type_28,
65c766ca
LM		 3366 }, {
3367 .compatible = "mitsubishi,aa070mc01-ca1",
3368 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 3369 }, {
3370 .compatible = "nec,nl12880bc20-05",
3371 .data = &nec_nl12880bc20_05,
c6e87f91 3372 }, {
3373 .compatible = "nec,nl4827hc19-05b",
3374 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 3375 }, {
3376 .compatible = "netron-dy,e231732",
3377 .data = &netron_dy_e231732,
3b39ad7a
TV		 3378 }, {
3379 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3380 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 3381 }, {
3382 .compatible = "nlt,nl192108ac18-02d",
3383 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 3384 }, {
3385 .compatible = "nvd,9128",
3386 .data = &nvd_9128,
a99fb626
GB		 3387 }, {
3388 .compatible = "okaya,rs800480t-7x0gp",
3389 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 3390 }, {
3391 .compatible = "olimex,lcd-olinuxino-43-ts",
3392 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 3393 }, {
3394 .compatible = "ontat,yx700wv03",
3395 .data = &ontat_yx700wv03,
9c31dcb6
NS		 3396 }, {
3397 .compatible = "ortustech,com37h3m05dtc",
3398 .data = &ortustech_com37h3m,
3399 }, {
3400 .compatible = "ortustech,com37h3m99dtc",
3401 .data = &ortustech_com37h3m,
725c9d40
PZ		 3402 }, {
3403 .compatible = "ortustech,com43h4m85ulc",
3404 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 3405 }, {
3406 .compatible = "osddisplays,osd070t1718-19ts",
3407 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 3408 }, {
3409 .compatible = "pda,91-00156-a0",
3410 .data = &pda_91_00156_a0,
d2a6f0f5
JW		 3411 }, {
3412 .compatible = "qiaodian,qd43003c0-40",
3413 .data = &qd43003c0_40,
23167fa9
JT		 3414 }, {
3415 .compatible = "rocktech,rk070er9427",
3416 .data = &rocktech_rk070er9427,
0330eaf3
YY		 3417 }, {
3418 .compatible = "samsung,lsn122dl01-c01",
3419 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 3420 }, {
3421 .compatible = "samsung,ltn101nt05",
3422 .data = &samsung_ltn101nt05,
0c934306
SM		 3423 }, {
3424 .compatible = "samsung,ltn140at29-301",
3425 .data = &samsung_ltn140at29_301,
cd5e1cbe
JH		 3426 }, {
3427 .compatible = "sharp,ld-d5116z01b",
3428 .data = &sharp_ld_d5116z01b,
03e3ec9a
VZ		 3429 }, {
3430 .compatible = "sharp,lq035q7db03",
3431 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 3432 }, {
3433 .compatible = "sharp,lq070y3dg3b",
3434 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 3435 }, {
3436 .compatible = "sharp,lq101k1ly04",
3437 .data = &sharp_lq101k1ly04,
739c7de9
YY		 3438 }, {
3439 .compatible = "sharp,lq123p1jx31",
3440 .data = &sharp_lq123p1jx31,
0f9cdd74
GL		 3441 }, {
3442 .compatible = "sharp,lq150x1lg11",
3443 .data = &sharp_lq150x1lg11,
f1bd37f3
PC		 3444 }, {
3445 .compatible = "sharp,ls020b1dd01d",
3446 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 3447 }, {
3448 .compatible = "shelly,sca07010-bfn-lnn",
3449 .data = &shelly_sca07010_bfn_lnn,
9bb34c4c
DA		 3450 }, {
3451 .compatible = "starry,kr122ea0sra",
3452 .data = &starry_kr122ea0sra,
42161531
JS		 3453 }, {
3454 .compatible = "tfc,s9700rtwv43tr-01b",
3455 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 3456 }, {
3457 .compatible = "tianma,tm070jdhg30",
3458 .data = &tianma_tm070jdhg30,
870a0b12
LM		 3459 }, {
3460 .compatible = "tianma,tm070rvhg71",
3461 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 3462 }, {
3463 .compatible = "ti,nspire-cx-lcd-panel",
3464 .data = &ti_nspire_cx_lcd_panel,
3465 }, {
3466 .compatible = "ti,nspire-classic-lcd-panel",
3467 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 3468 }, {
3469 .compatible = "toshiba,lt089ac29000",
3470 .data = &toshiba_lt089ac29000,
227e4f40
BD		 3471 }, {
3472 .compatible = "tpk,f07a-0102",
3473 .data = &tpk_f07a_0102,
3474 }, {
3475 .compatible = "tpk,f10a-0102",
3476 .data = &tpk_f10a_0102,
06a9dc65
MS		 3477 }, {
3478 .compatible = "urt,umsh-8596md-t",
3479 .data = &urt_umsh_8596md_parallel,
3480 }, {
3481 .compatible = "urt,umsh-8596md-1t",
3482 .data = &urt_umsh_8596md_parallel,
3483 }, {
3484 .compatible = "urt,umsh-8596md-7t",
3485 .data = &urt_umsh_8596md_parallel,
3486 }, {
3487 .compatible = "urt,umsh-8596md-11t",
3488 .data = &urt_umsh_8596md_lvds,
3489 }, {
3490 .compatible = "urt,umsh-8596md-19t",
3491 .data = &urt_umsh_8596md_lvds,
3492 }, {
3493 .compatible = "urt,umsh-8596md-20t",
3494 .data = &urt_umsh_8596md_parallel,
04206185
FE		 3495 }, {
3496 .compatible = "vxt,vl050-8048nt-c01",
3497 .data = &vl050_8048nt_c01,
e4bac408
RG		 3498 }, {
3499 .compatible = "winstar,wf35ltiacd",
3500 .data = &winstar_wf35ltiacd,
280921de
TR		 3501 }, {
3502 /* sentinel */
3503 }
3504};
3505MODULE_DEVICE_TABLE(of, platform_of_match);
3506
3507static int panel_simple_platform_probe(struct platform_device *pdev)
3508{
3509 const struct of_device_id *id;
3510
3511 id = of_match_node(platform_of_match, pdev->dev.of_node);
3512 if (!id)
3513 return -ENODEV;
3514
3515 return panel_simple_probe(&pdev->dev, id->data);
3516}
3517
3518static int panel_simple_platform_remove(struct platform_device *pdev)
3519{
3520 return panel_simple_remove(&pdev->dev);
3521}
3522
d02fd93e
TR		 3523static void panel_simple_platform_shutdown(struct platform_device *pdev)
3524{
3525 panel_simple_shutdown(&pdev->dev);
3526}
3527
280921de
TR		 3528static struct platform_driver panel_simple_platform_driver = {
3529 .driver = {
3530 .name = "panel-simple",
280921de
TR		 3531 .of_match_table = platform_of_match,
3532 },
3533 .probe = panel_simple_platform_probe,
3534 .remove = panel_simple_platform_remove,
d02fd93e 3535 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 3536};
3537
210fcd9d
TR		 3538struct panel_desc_dsi {
3539 struct panel_desc desc;
3540
462658b8 3541 unsigned long flags;
210fcd9d
TR		 3542 enum mipi_dsi_pixel_format format;
3543 unsigned int lanes;
3544};
3545
d718d79e
TR		 3546static const struct drm_display_mode auo_b080uan01_mode = {
3547 .clock = 154500,
3548 .hdisplay = 1200,
3549 .hsync_start = 1200 + 62,
3550 .hsync_end = 1200 + 62 + 4,
3551 .htotal = 1200 + 62 + 4 + 62,
3552 .vdisplay = 1920,
3553 .vsync_start = 1920 + 9,
3554 .vsync_end = 1920 + 9 + 2,
3555 .vtotal = 1920 + 9 + 2 + 8,
3556 .vrefresh = 60,
3557};
3558
3559static const struct panel_desc_dsi auo_b080uan01 = {
3560 .desc = {
3561 .modes = &auo_b080uan01_mode,
3562 .num_modes = 1,
3563 .bpc = 8,
3564 .size = {
3565 .width = 108,
3566 .height = 272,
3567 },
3568 },
3569 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3570 .format = MIPI_DSI_FMT_RGB888,
3571 .lanes = 4,
3572};
3573
c8521969
CZ		 3574static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3575 .clock = 160000,
3576 .hdisplay = 1200,
3577 .hsync_start = 1200 + 120,
3578 .hsync_end = 1200 + 120 + 20,
3579 .htotal = 1200 + 120 + 20 + 21,
3580 .vdisplay = 1920,
3581 .vsync_start = 1920 + 21,
3582 .vsync_end = 1920 + 21 + 3,
3583 .vtotal = 1920 + 21 + 3 + 18,
3584 .vrefresh = 60,
3585 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3586};
3587
3588static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3589 .desc = {
3590 .modes = &boe_tv080wum_nl0_mode,
3591 .num_modes = 1,
3592 .size = {
3593 .width = 107,
3594 .height = 172,
3595 },
3596 },
3597 .flags = MIPI_DSI_MODE_VIDEO |
3598 MIPI_DSI_MODE_VIDEO_BURST |
3599 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3600 .format = MIPI_DSI_FMT_RGB888,
3601 .lanes = 4,
3602};
3603
712ac1ba
AC		 3604static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3605 .clock = 71000,
3606 .hdisplay = 800,
3607 .hsync_start = 800 + 32,
3608 .hsync_end = 800 + 32 + 1,
3609 .htotal = 800 + 32 + 1 + 57,
3610 .vdisplay = 1280,
3611 .vsync_start = 1280 + 28,
3612 .vsync_end = 1280 + 28 + 1,
3613 .vtotal = 1280 + 28 + 1 + 14,
3614 .vrefresh = 60,
3615};
3616
3617static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3618 .desc = {
3619 .modes = &lg_ld070wx3_sl01_mode,
3620 .num_modes = 1,
d7a839cd 3621 .bpc = 8,
712ac1ba
AC		 3622 .size = {
3623 .width = 94,
3624 .height = 151,
3625 },
3626 },
5e4cc278 3627 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 3628 .format = MIPI_DSI_FMT_RGB888,
3629 .lanes = 4,
3630};
3631
499ce85a
AC		 3632static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3633 .clock = 67000,
3634 .hdisplay = 720,
3635 .hsync_start = 720 + 12,
3636 .hsync_end = 720 + 12 + 4,
3637 .htotal = 720 + 12 + 4 + 112,
3638 .vdisplay = 1280,
3639 .vsync_start = 1280 + 8,
3640 .vsync_end = 1280 + 8 + 4,
3641 .vtotal = 1280 + 8 + 4 + 12,
3642 .vrefresh = 60,
3643};
3644
3645static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3646 .desc = {
3647 .modes = &lg_lh500wx1_sd03_mode,
3648 .num_modes = 1,
d7a839cd 3649 .bpc = 8,
499ce85a
AC		 3650 .size = {
3651 .width = 62,
3652 .height = 110,
3653 },
3654 },
3655 .flags = MIPI_DSI_MODE_VIDEO,
3656 .format = MIPI_DSI_FMT_RGB888,
3657 .lanes = 4,
3658};
3659
280921de
TR		 3660static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3661 .clock = 157200,
3662 .hdisplay = 1920,
3663 .hsync_start = 1920 + 154,
3664 .hsync_end = 1920 + 154 + 16,
3665 .htotal = 1920 + 154 + 16 + 32,
3666 .vdisplay = 1200,
3667 .vsync_start = 1200 + 17,
3668 .vsync_end = 1200 + 17 + 2,
3669 .vtotal = 1200 + 17 + 2 + 16,
3670 .vrefresh = 60,
3671};
3672
210fcd9d
TR		 3673static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3674 .desc = {
3675 .modes = &panasonic_vvx10f004b00_mode,
3676 .num_modes = 1,
d7a839cd 3677 .bpc = 8,
210fcd9d
TR		 3678 .size = {
3679 .width = 217,
3680 .height = 136,
3681 },
280921de 3682 },
5e4cc278
AC		 3683 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3684 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 3685 .format = MIPI_DSI_FMT_RGB888,
3686 .lanes = 4,
3687};
3688
debcd8f9
JM		 3689static const struct drm_display_mode lg_acx467akm_7_mode = {
3690 .clock = 150000,
3691 .hdisplay = 1080,
3692 .hsync_start = 1080 + 2,
3693 .hsync_end = 1080 + 2 + 2,
3694 .htotal = 1080 + 2 + 2 + 2,
3695 .vdisplay = 1920,
3696 .vsync_start = 1920 + 2,
3697 .vsync_end = 1920 + 2 + 2,
3698 .vtotal = 1920 + 2 + 2 + 2,
3699 .vrefresh = 60,
3700};
3701
3702static const struct panel_desc_dsi lg_acx467akm_7 = {
3703 .desc = {
3704 .modes = &lg_acx467akm_7_mode,
3705 .num_modes = 1,
3706 .bpc = 8,
3707 .size = {
3708 .width = 62,
3709 .height = 110,
3710 },
3711 },
3712 .flags = 0,
3713 .format = MIPI_DSI_FMT_RGB888,
3714 .lanes = 4,
3715};
3716
62967232
PU		 3717static const struct drm_display_mode osd101t2045_53ts_mode = {
3718 .clock = 154500,
3719 .hdisplay = 1920,
3720 .hsync_start = 1920 + 112,
3721 .hsync_end = 1920 + 112 + 16,
3722 .htotal = 1920 + 112 + 16 + 32,
3723 .vdisplay = 1200,
3724 .vsync_start = 1200 + 16,
3725 .vsync_end = 1200 + 16 + 2,
3726 .vtotal = 1200 + 16 + 2 + 16,
3727 .vrefresh = 60,
3728 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3729};
3730
3731static const struct panel_desc_dsi osd101t2045_53ts = {
3732 .desc = {
3733 .modes = &osd101t2045_53ts_mode,
3734 .num_modes = 1,
3735 .bpc = 8,
3736 .size = {
3737 .width = 217,
3738 .height = 136,
3739 },
3740 },
3741 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3742 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3743 MIPI_DSI_MODE_EOT_PACKET,
3744 .format = MIPI_DSI_FMT_RGB888,
3745 .lanes = 4,
3746};
3747
210fcd9d
TR		 3748static const struct of_device_id dsi_of_match[] = {
3749 {
d718d79e
TR		 3750 .compatible = "auo,b080uan01",
3751 .data = &auo_b080uan01
c8521969
CZ		 3752 }, {
3753 .compatible = "boe,tv080wum-nl0",
3754 .data = &boe_tv080wum_nl0
d718d79e 3755 }, {
712ac1ba
AC		 3756 .compatible = "lg,ld070wx3-sl01",
3757 .data = &lg_ld070wx3_sl01
3758 }, {
499ce85a
AC		 3759 .compatible = "lg,lh500wx1-sd03",
3760 .data = &lg_lh500wx1_sd03
3761 }, {
210fcd9d
TR		 3762 .compatible = "panasonic,vvx10f004b00",
3763 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 3764 }, {
3765 .compatible = "lg,acx467akm-7",
3766 .data = &lg_acx467akm_7
62967232
PU		 3767 }, {
3768 .compatible = "osddisplays,osd101t2045-53ts",
3769 .data = &osd101t2045_53ts
210fcd9d
TR		 3770 }, {
3771 /* sentinel */
3772 }
3773};
3774MODULE_DEVICE_TABLE(of, dsi_of_match);
3775
3776static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3777{
3778 const struct panel_desc_dsi *desc;
3779 const struct of_device_id *id;
3780 int err;
3781
3782 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3783 if (!id)
3784 return -ENODEV;
3785
3786 desc = id->data;
3787
3788 err = panel_simple_probe(&dsi->dev, &desc->desc);
3789 if (err < 0)
3790 return err;
3791
462658b8 3792 dsi->mode_flags = desc->flags;
210fcd9d
TR		 3793 dsi->format = desc->format;
3794 dsi->lanes = desc->lanes;
3795
7ad9db66
PU		 3796 err = mipi_dsi_attach(dsi);
3797 if (err) {
3798 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3799
3800 drm_panel_remove(&panel->base);
3801 }
3802
3803 return err;
210fcd9d
TR		 3804}
3805
3806static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3807{
3808 int err;
3809
3810 err = mipi_dsi_detach(dsi);
3811 if (err < 0)
3812 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3813
3814 return panel_simple_remove(&dsi->dev);
3815}
3816
d02fd93e
TR		 3817static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3818{
3819 panel_simple_shutdown(&dsi->dev);
3820}
3821
210fcd9d
TR		 3822static struct mipi_dsi_driver panel_simple_dsi_driver = {
3823 .driver = {
3824 .name = "panel-simple-dsi",
210fcd9d
TR		 3825 .of_match_table = dsi_of_match,
3826 },
3827 .probe = panel_simple_dsi_probe,
3828 .remove = panel_simple_dsi_remove,
d02fd93e 3829 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 3830};
3831
3832static int __init panel_simple_init(void)
3833{
210fcd9d
TR		 3834 int err;
3835
3836 err = platform_driver_register(&panel_simple_platform_driver);
3837 if (err < 0)
3838 return err;
3839
3840 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3841 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3842 if (err < 0)
3843 return err;
3844 }
3845
3846 return 0;
280921de
TR		 3847}
3848module_init(panel_simple_init);
3849
3850static void __exit panel_simple_exit(void)
3851{
210fcd9d
TR		 3852 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3853 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3854
280921de
TR		 3855 platform_driver_unregister(&panel_simple_platform_driver);
3856}
3857module_exit(panel_simple_exit);
3858
3859MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3860MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3861MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)