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drm/panel: simple: Add more properties to Innolux G121I1-L01
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
85533e3b
UÖ		 47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
280921de
TR		 51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
f673c37e
AK		 55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
795f7ab3
BB		 73
74 u32 bus_format;
f0aa0838 75 u32 bus_flags;
280921de
TR		 76};
77
280921de
TR		 78struct panel_simple {
79 struct drm_panel base;
613a633e 80 bool prepared;
280921de
TR		 81 bool enabled;
82
83 const struct panel_desc *desc;
84
85 struct backlight_device *backlight;
86 struct regulator *supply;
87 struct i2c_adapter *ddc;
88
cfdf0549 89 struct gpio_desc *enable_gpio;
280921de
TR		 90};
91
92static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
93{
94 return container_of(panel, struct panel_simple, base);
95}
96
97static int panel_simple_get_fixed_modes(struct panel_simple *panel)
98{
99 struct drm_connector *connector = panel->base.connector;
100 struct drm_device *drm = panel->base.drm;
101 struct drm_display_mode *mode;
102 unsigned int i, num = 0;
103
104 if (!panel->desc)
105 return 0;
106
a5d3e625
PZ		 107 for (i = 0; i < panel->desc->num_timings; i++) {
108 const struct display_timing *dt = &panel->desc->timings[i];
109 struct videomode vm;
110
111 videomode_from_timing(dt, &vm);
112 mode = drm_mode_create(drm);
113 if (!mode) {
114 dev_err(drm->dev, "failed to add mode %ux%u\n",
115 dt->hactive.typ, dt->vactive.typ);
116 continue;
117 }
118
119 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 120
121 mode->type |= DRM_MODE_TYPE_DRIVER;
122
230c5b44 123 if (panel->desc->num_timings == 1)
cda55372
BB		 124 mode->type |= DRM_MODE_TYPE_PREFERRED;
125
a5d3e625
PZ		 126 drm_mode_probed_add(connector, mode);
127 num++;
128 }
129
280921de
TR		 130 for (i = 0; i < panel->desc->num_modes; i++) {
131 const struct drm_display_mode *m = &panel->desc->modes[i];
132
133 mode = drm_mode_duplicate(drm, m);
134 if (!mode) {
135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
136 m->hdisplay, m->vdisplay, m->vrefresh);
137 continue;
138 }
139
cda55372
BB		 140 mode->type |= DRM_MODE_TYPE_DRIVER;
141
142 if (panel->desc->num_modes == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
144
280921de
TR		 145 drm_mode_set_name(mode);
146
147 drm_mode_probed_add(connector, mode);
148 num++;
149 }
150
0208d511 151 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 152 connector->display_info.width_mm = panel->desc->size.width;
153 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 154 if (panel->desc->bus_format)
155 drm_display_info_set_bus_formats(&connector->display_info,
156 &panel->desc->bus_format, 1);
f0aa0838 157 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 158
159 return num;
160}
161
162static int panel_simple_disable(struct drm_panel *panel)
163{
164 struct panel_simple *p = to_panel_simple(panel);
165
166 if (!p->enabled)
167 return 0;
168
169 if (p->backlight) {
170 p->backlight->props.power = FB_BLANK_POWERDOWN;
e4aa3428 171 p->backlight->props.state |= BL_CORE_FBBLANK;
280921de
TR		 172 backlight_update_status(p->backlight);
173 }
174
f673c37e
AK		 175 if (p->desc->delay.disable)
176 msleep(p->desc->delay.disable);
177
280921de
TR		 178 p->enabled = false;
179
180 return 0;
181}
182
c0e1d170
AK		 183static int panel_simple_unprepare(struct drm_panel *panel)
184{
613a633e
AK		 185 struct panel_simple *p = to_panel_simple(panel);
186
187 if (!p->prepared)
188 return 0;
189
190 if (p->enable_gpio)
191 gpiod_set_value_cansleep(p->enable_gpio, 0);
192
193 regulator_disable(p->supply);
194
f673c37e
AK		 195 if (p->desc->delay.unprepare)
196 msleep(p->desc->delay.unprepare);
197
613a633e 198 p->prepared = false;
c0e1d170 199
c0e1d170
AK		 200 return 0;
201}
202
613a633e 203static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 204{
205 struct panel_simple *p = to_panel_simple(panel);
206 int err;
207
613a633e 208 if (p->prepared)
280921de
TR		 209 return 0;
210
211 err = regulator_enable(p->supply);
212 if (err < 0) {
213 dev_err(panel->dev, "failed to enable supply: %d\n", err);
214 return err;
215 }
216
cfdf0549 217 if (p->enable_gpio)
15c1a919 218 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 219
f673c37e
AK		 220 if (p->desc->delay.prepare)
221 msleep(p->desc->delay.prepare);
222
613a633e
AK		 223 p->prepared = true;
224
225 return 0;
226}
227
228static int panel_simple_enable(struct drm_panel *panel)
229{
230 struct panel_simple *p = to_panel_simple(panel);
231
232 if (p->enabled)
233 return 0;
234
f673c37e
AK		 235 if (p->desc->delay.enable)
236 msleep(p->desc->delay.enable);
237
280921de 238 if (p->backlight) {
e4aa3428 239 p->backlight->props.state &= ~BL_CORE_FBBLANK;
280921de
TR		 240 p->backlight->props.power = FB_BLANK_UNBLANK;
241 backlight_update_status(p->backlight);
242 }
243
244 p->enabled = true;
245
246 return 0;
247}
248
249static int panel_simple_get_modes(struct drm_panel *panel)
250{
251 struct panel_simple *p = to_panel_simple(panel);
252 int num = 0;
253
254 /* probe EDID if a DDC bus is available */
255 if (p->ddc) {
256 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 257 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 258 if (edid) {
259 num += drm_add_edid_modes(panel->connector, edid);
260 kfree(edid);
261 }
262 }
263
264 /* add hard-coded panel modes */
265 num += panel_simple_get_fixed_modes(p);
266
267 return num;
268}
269
a5d3e625
PZ		 270static int panel_simple_get_timings(struct drm_panel *panel,
271 unsigned int num_timings,
272 struct display_timing *timings)
273{
274 struct panel_simple *p = to_panel_simple(panel);
275 unsigned int i;
276
277 if (p->desc->num_timings < num_timings)
278 num_timings = p->desc->num_timings;
279
280 if (timings)
281 for (i = 0; i < num_timings; i++)
282 timings[i] = p->desc->timings[i];
283
284 return p->desc->num_timings;
285}
286
280921de
TR		 287static const struct drm_panel_funcs panel_simple_funcs = {
288 .disable = panel_simple_disable,
c0e1d170
AK		 289 .unprepare = panel_simple_unprepare,
290 .prepare = panel_simple_prepare,
280921de
TR		 291 .enable = panel_simple_enable,
292 .get_modes = panel_simple_get_modes,
a5d3e625 293 .get_timings = panel_simple_get_timings,
280921de
TR		 294};
295
296static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
297{
298 struct device_node *backlight, *ddc;
299 struct panel_simple *panel;
280921de
TR		 300 int err;
301
302 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
303 if (!panel)
304 return -ENOMEM;
305
306 panel->enabled = false;
613a633e 307 panel->prepared = false;
280921de
TR		 308 panel->desc = desc;
309
310 panel->supply = devm_regulator_get(dev, "power");
311 if (IS_ERR(panel->supply))
312 return PTR_ERR(panel->supply);
313
a61400d8
AC		 314 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
315 GPIOD_OUT_LOW);
cfdf0549
AC		 316 if (IS_ERR(panel->enable_gpio)) {
317 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 318 dev_err(dev, "failed to request GPIO: %d\n", err);
319 return err;
320 }
280921de 321
280921de
TR		 322 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
323 if (backlight) {
324 panel->backlight = of_find_backlight_by_node(backlight);
325 of_node_put(backlight);
326
cfdf0549
AC		 327 if (!panel->backlight)
328 return -EPROBE_DEFER;
280921de
TR		 329 }
330
331 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
332 if (ddc) {
333 panel->ddc = of_find_i2c_adapter_by_node(ddc);
334 of_node_put(ddc);
335
336 if (!panel->ddc) {
337 err = -EPROBE_DEFER;
338 goto free_backlight;
339 }
340 }
341
342 drm_panel_init(&panel->base);
343 panel->base.dev = dev;
344 panel->base.funcs = &panel_simple_funcs;
345
346 err = drm_panel_add(&panel->base);
347 if (err < 0)
348 goto free_ddc;
349
350 dev_set_drvdata(dev, panel);
351
352 return 0;
353
354free_ddc:
355 if (panel->ddc)
356 put_device(&panel->ddc->dev);
357free_backlight:
358 if (panel->backlight)
359 put_device(&panel->backlight->dev);
280921de
TR		 360
361 return err;
362}
363
364static int panel_simple_remove(struct device *dev)
365{
366 struct panel_simple *panel = dev_get_drvdata(dev);
367
368 drm_panel_detach(&panel->base);
369 drm_panel_remove(&panel->base);
370
371 panel_simple_disable(&panel->base);
372
373 if (panel->ddc)
374 put_device(&panel->ddc->dev);
375
376 if (panel->backlight)
377 put_device(&panel->backlight->dev);
378
280921de
TR		 379 return 0;
380}
381
d02fd93e
TR		 382static void panel_simple_shutdown(struct device *dev)
383{
384 struct panel_simple *panel = dev_get_drvdata(dev);
385
386 panel_simple_disable(&panel->base);
387}
388
1c550fa1
PZ		 389static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
390 .clock = 33333,
391 .hdisplay = 800,
392 .hsync_start = 800 + 0,
393 .hsync_end = 800 + 0 + 255,
394 .htotal = 800 + 0 + 255 + 0,
395 .vdisplay = 480,
396 .vsync_start = 480 + 2,
397 .vsync_end = 480 + 2 + 45,
398 .vtotal = 480 + 2 + 45 + 0,
399 .vrefresh = 60,
400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
401};
402
403static const struct panel_desc ampire_am800480r3tmqwa1h = {
404 .modes = &ampire_am800480r3tmqwa1h_mode,
405 .num_modes = 1,
406 .bpc = 6,
407 .size = {
408 .width = 152,
409 .height = 91,
410 },
411 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
412};
413
280921de
TR		 414static const struct drm_display_mode auo_b101aw03_mode = {
415 .clock = 51450,
416 .hdisplay = 1024,
417 .hsync_start = 1024 + 156,
418 .hsync_end = 1024 + 156 + 8,
419 .htotal = 1024 + 156 + 8 + 156,
420 .vdisplay = 600,
421 .vsync_start = 600 + 16,
422 .vsync_end = 600 + 16 + 6,
423 .vtotal = 600 + 16 + 6 + 16,
424 .vrefresh = 60,
425};
426
427static const struct panel_desc auo_b101aw03 = {
428 .modes = &auo_b101aw03_mode,
429 .num_modes = 1,
0208d511 430 .bpc = 6,
280921de
TR		 431 .size = {
432 .width = 223,
433 .height = 125,
434 },
435};
436
a531bc3d
HL		 437static const struct drm_display_mode auo_b101ean01_mode = {
438 .clock = 72500,
439 .hdisplay = 1280,
440 .hsync_start = 1280 + 119,
441 .hsync_end = 1280 + 119 + 32,
442 .htotal = 1280 + 119 + 32 + 21,
443 .vdisplay = 800,
444 .vsync_start = 800 + 4,
445 .vsync_end = 800 + 4 + 20,
446 .vtotal = 800 + 4 + 20 + 8,
447 .vrefresh = 60,
448};
449
450static const struct panel_desc auo_b101ean01 = {
451 .modes = &auo_b101ean01_mode,
452 .num_modes = 1,
453 .bpc = 6,
454 .size = {
455 .width = 217,
456 .height = 136,
457 },
458};
459
dac746e0
RC		 460static const struct drm_display_mode auo_b101xtn01_mode = {
461 .clock = 72000,
462 .hdisplay = 1366,
463 .hsync_start = 1366 + 20,
464 .hsync_end = 1366 + 20 + 70,
465 .htotal = 1366 + 20 + 70,
466 .vdisplay = 768,
467 .vsync_start = 768 + 14,
468 .vsync_end = 768 + 14 + 42,
469 .vtotal = 768 + 14 + 42,
470 .vrefresh = 60,
471 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
472};
473
474static const struct panel_desc auo_b101xtn01 = {
475 .modes = &auo_b101xtn01_mode,
476 .num_modes = 1,
477 .bpc = 6,
478 .size = {
479 .width = 223,
480 .height = 125,
481 },
482};
483
e35e305e
AK		 484static const struct drm_display_mode auo_b116xw03_mode = {
485 .clock = 70589,
486 .hdisplay = 1366,
487 .hsync_start = 1366 + 40,
488 .hsync_end = 1366 + 40 + 40,
489 .htotal = 1366 + 40 + 40 + 32,
490 .vdisplay = 768,
491 .vsync_start = 768 + 10,
492 .vsync_end = 768 + 10 + 12,
493 .vtotal = 768 + 10 + 12 + 6,
494 .vrefresh = 60,
495};
496
497static const struct panel_desc auo_b116xw03 = {
498 .modes = &auo_b116xw03_mode,
499 .num_modes = 1,
500 .bpc = 6,
501 .size = {
502 .width = 256,
503 .height = 144,
504 },
505};
506
a333f7ad
SM		 507static const struct drm_display_mode auo_b133xtn01_mode = {
508 .clock = 69500,
509 .hdisplay = 1366,
510 .hsync_start = 1366 + 48,
511 .hsync_end = 1366 + 48 + 32,
512 .htotal = 1366 + 48 + 32 + 20,
513 .vdisplay = 768,
514 .vsync_start = 768 + 3,
515 .vsync_end = 768 + 3 + 6,
516 .vtotal = 768 + 3 + 6 + 13,
517 .vrefresh = 60,
518};
519
520static const struct panel_desc auo_b133xtn01 = {
521 .modes = &auo_b133xtn01_mode,
522 .num_modes = 1,
0208d511 523 .bpc = 6,
a333f7ad
SM		 524 .size = {
525 .width = 293,
526 .height = 165,
527 },
528};
529
3e51d609
AK		 530static const struct drm_display_mode auo_b133htn01_mode = {
531 .clock = 150660,
532 .hdisplay = 1920,
533 .hsync_start = 1920 + 172,
534 .hsync_end = 1920 + 172 + 80,
535 .htotal = 1920 + 172 + 80 + 60,
536 .vdisplay = 1080,
537 .vsync_start = 1080 + 25,
538 .vsync_end = 1080 + 25 + 10,
539 .vtotal = 1080 + 25 + 10 + 10,
540 .vrefresh = 60,
541};
542
543static const struct panel_desc auo_b133htn01 = {
544 .modes = &auo_b133htn01_mode,
545 .num_modes = 1,
d7a839cd 546 .bpc = 6,
3e51d609
AK		 547 .size = {
548 .width = 293,
549 .height = 165,
550 },
551 .delay = {
552 .prepare = 105,
553 .enable = 20,
554 .unprepare = 50,
555 },
556};
557
7ee933a1
HS		 558static const struct drm_display_mode auo_t215hvn01_mode = {
559 .clock = 148800,
560 .hdisplay = 1920,
561 .hsync_start = 1920 + 88,
562 .hsync_end = 1920 + 88 + 44,
563 .htotal = 1920 + 88 + 44 + 148,
564 .vdisplay = 1080,
565 .vsync_start = 1080 + 4,
566 .vsync_end = 1080 + 4 + 5,
567 .vtotal = 1080 + 4 + 5 + 36,
568 .vrefresh = 60,
569};
570
571static const struct panel_desc auo_t215hvn01 = {
572 .modes = &auo_t215hvn01_mode,
573 .num_modes = 1,
574 .bpc = 8,
575 .size = {
576 .width = 430,
577 .height = 270,
578 },
579 .delay = {
580 .disable = 5,
581 .unprepare = 1000,
582 }
583};
584
d47df633
PZ		 585static const struct drm_display_mode avic_tm070ddh03_mode = {
586 .clock = 51200,
587 .hdisplay = 1024,
588 .hsync_start = 1024 + 160,
589 .hsync_end = 1024 + 160 + 4,
590 .htotal = 1024 + 160 + 4 + 156,
591 .vdisplay = 600,
592 .vsync_start = 600 + 17,
593 .vsync_end = 600 + 17 + 1,
594 .vtotal = 600 + 17 + 1 + 17,
595 .vrefresh = 60,
596};
597
598static const struct panel_desc avic_tm070ddh03 = {
599 .modes = &avic_tm070ddh03_mode,
600 .num_modes = 1,
601 .bpc = 8,
602 .size = {
603 .width = 154,
604 .height = 90,
605 },
606 .delay = {
607 .prepare = 20,
608 .enable = 200,
609 .disable = 200,
610 },
611};
612
2cb35c80
RL		 613static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
614 .clock = 66770,
615 .hdisplay = 800,
616 .hsync_start = 800 + 49,
617 .hsync_end = 800 + 49 + 33,
618 .htotal = 800 + 49 + 33 + 17,
619 .vdisplay = 1280,
620 .vsync_start = 1280 + 1,
621 .vsync_end = 1280 + 1 + 7,
622 .vtotal = 1280 + 1 + 7 + 15,
623 .vrefresh = 60,
624 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
625};
626
627static const struct panel_desc chunghwa_claa070wp03xg = {
628 .modes = &chunghwa_claa070wp03xg_mode,
629 .num_modes = 1,
630 .bpc = 6,
631 .size = {
632 .width = 94,
633 .height = 150,
634 },
635};
636
4c930757
SW		 637static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
638 .clock = 72070,
639 .hdisplay = 1366,
640 .hsync_start = 1366 + 58,
641 .hsync_end = 1366 + 58 + 58,
642 .htotal = 1366 + 58 + 58 + 58,
643 .vdisplay = 768,
644 .vsync_start = 768 + 4,
645 .vsync_end = 768 + 4 + 4,
646 .vtotal = 768 + 4 + 4 + 4,
647 .vrefresh = 60,
648};
649
650static const struct panel_desc chunghwa_claa101wa01a = {
651 .modes = &chunghwa_claa101wa01a_mode,
652 .num_modes = 1,
0208d511 653 .bpc = 6,
4c930757
SW		 654 .size = {
655 .width = 220,
656 .height = 120,
657 },
658};
659
280921de
TR		 660static const struct drm_display_mode chunghwa_claa101wb01_mode = {
661 .clock = 69300,
662 .hdisplay = 1366,
663 .hsync_start = 1366 + 48,
664 .hsync_end = 1366 + 48 + 32,
665 .htotal = 1366 + 48 + 32 + 20,
666 .vdisplay = 768,
667 .vsync_start = 768 + 16,
668 .vsync_end = 768 + 16 + 8,
669 .vtotal = 768 + 16 + 8 + 16,
670 .vrefresh = 60,
671};
672
673static const struct panel_desc chunghwa_claa101wb01 = {
674 .modes = &chunghwa_claa101wb01_mode,
675 .num_modes = 1,
0208d511 676 .bpc = 6,
280921de
TR		 677 .size = {
678 .width = 223,
679 .height = 125,
680 },
681};
682
26ab0065
SA		 683static const struct drm_display_mode edt_et057090dhu_mode = {
684 .clock = 25175,
685 .hdisplay = 640,
686 .hsync_start = 640 + 16,
687 .hsync_end = 640 + 16 + 30,
688 .htotal = 640 + 16 + 30 + 114,
689 .vdisplay = 480,
690 .vsync_start = 480 + 10,
691 .vsync_end = 480 + 10 + 3,
692 .vtotal = 480 + 10 + 3 + 32,
693 .vrefresh = 60,
694 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
695};
696
697static const struct panel_desc edt_et057090dhu = {
698 .modes = &edt_et057090dhu_mode,
699 .num_modes = 1,
0208d511 700 .bpc = 6,
26ab0065
SA		 701 .size = {
702 .width = 115,
703 .height = 86,
704 },
705};
706
fff5de45
PZ		 707static const struct drm_display_mode edt_etm0700g0dh6_mode = {
708 .clock = 33260,
709 .hdisplay = 800,
710 .hsync_start = 800 + 40,
711 .hsync_end = 800 + 40 + 128,
712 .htotal = 800 + 40 + 128 + 88,
713 .vdisplay = 480,
714 .vsync_start = 480 + 10,
715 .vsync_end = 480 + 10 + 2,
716 .vtotal = 480 + 10 + 2 + 33,
717 .vrefresh = 60,
718 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
719};
720
721static const struct panel_desc edt_etm0700g0dh6 = {
722 .modes = &edt_etm0700g0dh6_mode,
723 .num_modes = 1,
0208d511 724 .bpc = 6,
fff5de45
PZ		 725 .size = {
726 .width = 152,
727 .height = 91,
728 },
729};
730
102932b0
BB		 731static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
732 .clock = 32260,
733 .hdisplay = 800,
734 .hsync_start = 800 + 168,
735 .hsync_end = 800 + 168 + 64,
736 .htotal = 800 + 168 + 64 + 88,
737 .vdisplay = 480,
738 .vsync_start = 480 + 37,
739 .vsync_end = 480 + 37 + 2,
740 .vtotal = 480 + 37 + 2 + 8,
741 .vrefresh = 60,
742};
743
744static const struct panel_desc foxlink_fl500wvr00_a0t = {
745 .modes = &foxlink_fl500wvr00_a0t_mode,
746 .num_modes = 1,
d7a839cd 747 .bpc = 8,
102932b0
BB		 748 .size = {
749 .width = 108,
750 .height = 65,
751 },
bb276cb3 752 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 753};
754
d435a2af
PZ		 755static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
756 .clock = 9000,
757 .hdisplay = 480,
758 .hsync_start = 480 + 5,
759 .hsync_end = 480 + 5 + 1,
760 .htotal = 480 + 5 + 1 + 40,
761 .vdisplay = 272,
762 .vsync_start = 272 + 8,
763 .vsync_end = 272 + 8 + 1,
764 .vtotal = 272 + 8 + 1 + 8,
765 .vrefresh = 60,
766};
767
768static const struct panel_desc giantplus_gpg482739qs5 = {
769 .modes = &giantplus_gpg482739qs5_mode,
770 .num_modes = 1,
771 .bpc = 8,
772 .size = {
773 .width = 95,
774 .height = 54,
775 },
33536a09 776 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 777};
778
ab07725a
PZ		 779static const struct display_timing hannstar_hsd070pww1_timing = {
780 .pixelclock = { 64300000, 71100000, 82000000 },
781 .hactive = { 1280, 1280, 1280 },
782 .hfront_porch = { 1, 1, 10 },
783 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 784 /*
785 * According to the data sheet, the minimum horizontal blanking interval
786 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
787 * minimum working horizontal blanking interval to be 60 clocks.
788 */
789 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 790 .vactive = { 800, 800, 800 },
791 .vfront_porch = { 1, 1, 10 },
792 .vback_porch = { 1, 1, 10 },
793 .vsync_len = { 1, 21, 203 },
794 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 795};
796
797static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 798 .timings = &hannstar_hsd070pww1_timing,
799 .num_timings = 1,
a853205e
PZ		 800 .bpc = 6,
801 .size = {
802 .width = 151,
803 .height = 94,
804 },
58d6a7bc 805 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 806};
807
c0d607e5
EN		 808static const struct display_timing hannstar_hsd100pxn1_timing = {
809 .pixelclock = { 55000000, 65000000, 75000000 },
810 .hactive = { 1024, 1024, 1024 },
811 .hfront_porch = { 40, 40, 40 },
812 .hback_porch = { 220, 220, 220 },
813 .hsync_len = { 20, 60, 100 },
814 .vactive = { 768, 768, 768 },
815 .vfront_porch = { 7, 7, 7 },
816 .vback_porch = { 21, 21, 21 },
817 .vsync_len = { 10, 10, 10 },
818 .flags = DISPLAY_FLAGS_DE_HIGH,
819};
820
821static const struct panel_desc hannstar_hsd100pxn1 = {
822 .timings = &hannstar_hsd100pxn1_timing,
823 .num_timings = 1,
824 .bpc = 6,
825 .size = {
826 .width = 203,
827 .height = 152,
828 },
4946b043 829 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 830};
831
61ac0bf8
LS		 832static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
833 .clock = 33333,
834 .hdisplay = 800,
835 .hsync_start = 800 + 85,
836 .hsync_end = 800 + 85 + 86,
837 .htotal = 800 + 85 + 86 + 85,
838 .vdisplay = 480,
839 .vsync_start = 480 + 16,
840 .vsync_end = 480 + 16 + 13,
841 .vtotal = 480 + 16 + 13 + 16,
842 .vrefresh = 60,
843};
844
845static const struct panel_desc hitachi_tx23d38vm0caa = {
846 .modes = &hitachi_tx23d38vm0caa_mode,
847 .num_modes = 1,
848 .bpc = 6,
849 .size = {
850 .width = 195,
851 .height = 117,
852 },
853};
854
41bcceb4
NF		 855static const struct drm_display_mode innolux_at043tn24_mode = {
856 .clock = 9000,
857 .hdisplay = 480,
858 .hsync_start = 480 + 2,
859 .hsync_end = 480 + 2 + 41,
860 .htotal = 480 + 2 + 41 + 2,
861 .vdisplay = 272,
862 .vsync_start = 272 + 2,
863 .vsync_end = 272 + 2 + 11,
864 .vtotal = 272 + 2 + 11 + 2,
865 .vrefresh = 60,
866 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
867};
868
869static const struct panel_desc innolux_at043tn24 = {
870 .modes = &innolux_at043tn24_mode,
871 .num_modes = 1,
872 .bpc = 8,
873 .size = {
874 .width = 95,
875 .height = 54,
876 },
877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
878};
879
4fc24ab3
RB		 880static const struct drm_display_mode innolux_at070tn92_mode = {
881 .clock = 33333,
882 .hdisplay = 800,
883 .hsync_start = 800 + 210,
884 .hsync_end = 800 + 210 + 20,
885 .htotal = 800 + 210 + 20 + 46,
886 .vdisplay = 480,
887 .vsync_start = 480 + 22,
888 .vsync_end = 480 + 22 + 10,
889 .vtotal = 480 + 22 + 23 + 10,
890 .vrefresh = 60,
891};
892
893static const struct panel_desc innolux_at070tn92 = {
894 .modes = &innolux_at070tn92_mode,
895 .num_modes = 1,
896 .size = {
897 .width = 154,
898 .height = 86,
899 },
900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
901};
902
1e29b840
MO		 903static const struct display_timing innolux_g101ice_l01_timing = {
904 .pixelclock = { 60400000, 71100000, 74700000 },
905 .hactive = { 1280, 1280, 1280 },
906 .hfront_porch = { 41, 80, 100 },
907 .hback_porch = { 40, 79, 99 },
908 .hsync_len = { 1, 1, 1 },
909 .vactive = { 800, 800, 800 },
910 .vfront_porch = { 5, 11, 14 },
911 .vback_porch = { 4, 11, 14 },
912 .vsync_len = { 1, 1, 1 },
913 .flags = DISPLAY_FLAGS_DE_HIGH,
914};
915
916static const struct panel_desc innolux_g101ice_l01 = {
917 .timings = &innolux_g101ice_l01_timing,
918 .num_timings = 1,
919 .bpc = 8,
920 .size = {
921 .width = 217,
922 .height = 135,
923 },
924 .delay = {
925 .enable = 200,
926 .disable = 200,
927 },
928 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
929};
930
4ae13e48
LS		 931static const struct display_timing innolux_g121i1_l01_timing = {
932 .pixelclock = { 67450000, 71000000, 74550000 },
933 .hactive = { 1280, 1280, 1280 },
934 .hfront_porch = { 40, 80, 160 },
935 .hback_porch = { 39, 79, 159 },
936 .hsync_len = { 1, 1, 1 },
937 .vactive = { 800, 800, 800 },
938 .vfront_porch = { 5, 11, 100 },
939 .vback_porch = { 4, 11, 99 },
940 .vsync_len = { 1, 1, 1 },
d731f661
LS		 941};
942
943static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 944 .timings = &innolux_g121i1_l01_timing,
945 .num_timings = 1,
d731f661
LS		 946 .bpc = 6,
947 .size = {
948 .width = 261,
949 .height = 163,
950 },
4ae13e48
LS		 951 .delay = {
952 .enable = 200,
953 .disable = 20,
954 },
955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
d731f661
LS		 956};
957
f8fa17ba
AB		 958static const struct drm_display_mode innolux_g121x1_l03_mode = {
959 .clock = 65000,
960 .hdisplay = 1024,
961 .hsync_start = 1024 + 0,
962 .hsync_end = 1024 + 1,
963 .htotal = 1024 + 0 + 1 + 320,
964 .vdisplay = 768,
965 .vsync_start = 768 + 38,
966 .vsync_end = 768 + 38 + 1,
967 .vtotal = 768 + 38 + 1 + 0,
968 .vrefresh = 60,
2e8c5eb9 969 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 970};
971
972static const struct panel_desc innolux_g121x1_l03 = {
973 .modes = &innolux_g121x1_l03_mode,
974 .num_modes = 1,
975 .bpc = 6,
976 .size = {
977 .width = 246,
978 .height = 185,
979 },
980 .delay = {
981 .enable = 200,
982 .unprepare = 200,
983 .disable = 400,
984 },
985};
986
0a2288c0 987static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 988 .clock = 76420,
0a2288c0 989 .hdisplay = 1366,
7fe8c777
DK		 990 .hsync_start = 1366 + 136,
991 .hsync_end = 1366 + 136 + 30,
992 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 993 .vdisplay = 768,
994 .vsync_start = 768 + 8,
7fe8c777
DK		 995 .vsync_end = 768 + 8 + 12,
996 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 997 .vrefresh = 60,
998 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
999};
1000
1001static const struct panel_desc innolux_n116bge = {
1002 .modes = &innolux_n116bge_mode,
1003 .num_modes = 1,
1004 .bpc = 6,
1005 .size = {
1006 .width = 256,
1007 .height = 144,
1008 },
1009};
1010
ea44739d
AB		 1011static const struct drm_display_mode innolux_n156bge_l21_mode = {
1012 .clock = 69300,
1013 .hdisplay = 1366,
1014 .hsync_start = 1366 + 16,
1015 .hsync_end = 1366 + 16 + 34,
1016 .htotal = 1366 + 16 + 34 + 50,
1017 .vdisplay = 768,
1018 .vsync_start = 768 + 2,
1019 .vsync_end = 768 + 2 + 6,
1020 .vtotal = 768 + 2 + 6 + 12,
1021 .vrefresh = 60,
1022};
1023
1024static const struct panel_desc innolux_n156bge_l21 = {
1025 .modes = &innolux_n156bge_l21_mode,
1026 .num_modes = 1,
0208d511 1027 .bpc = 6,
ea44739d
AB		 1028 .size = {
1029 .width = 344,
1030 .height = 193,
1031 },
1032};
1033
bccac3f1
MG		 1034static const struct drm_display_mode innolux_zj070na_01p_mode = {
1035 .clock = 51501,
1036 .hdisplay = 1024,
1037 .hsync_start = 1024 + 128,
1038 .hsync_end = 1024 + 128 + 64,
1039 .htotal = 1024 + 128 + 64 + 128,
1040 .vdisplay = 600,
1041 .vsync_start = 600 + 16,
1042 .vsync_end = 600 + 16 + 4,
1043 .vtotal = 600 + 16 + 4 + 16,
1044 .vrefresh = 60,
1045};
1046
1047static const struct panel_desc innolux_zj070na_01p = {
1048 .modes = &innolux_zj070na_01p_mode,
1049 .num_modes = 1,
1050 .bpc = 6,
1051 .size = {
81598846
TR		 1052 .width = 154,
1053 .height = 90,
bccac3f1
MG		 1054 },
1055};
1056
8def22e5
LS		 1057static const struct display_timing kyo_tcg121xglp_timing = {
1058 .pixelclock = { 52000000, 65000000, 71000000 },
1059 .hactive = { 1024, 1024, 1024 },
1060 .hfront_porch = { 2, 2, 2 },
1061 .hback_porch = { 2, 2, 2 },
1062 .hsync_len = { 86, 124, 244 },
1063 .vactive = { 768, 768, 768 },
1064 .vfront_porch = { 2, 2, 2 },
1065 .vback_porch = { 2, 2, 2 },
1066 .vsync_len = { 6, 34, 73 },
1067 .flags = DISPLAY_FLAGS_DE_HIGH,
1068};
1069
1070static const struct panel_desc kyo_tcg121xglp = {
1071 .timings = &kyo_tcg121xglp_timing,
1072 .num_timings = 1,
1073 .bpc = 8,
1074 .size = {
1075 .width = 246,
1076 .height = 184,
1077 },
1078 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1079};
1080
dd015002
HS		 1081static const struct drm_display_mode lg_lb070wv8_mode = {
1082 .clock = 33246,
1083 .hdisplay = 800,
1084 .hsync_start = 800 + 88,
1085 .hsync_end = 800 + 88 + 80,
1086 .htotal = 800 + 88 + 80 + 88,
1087 .vdisplay = 480,
1088 .vsync_start = 480 + 10,
1089 .vsync_end = 480 + 10 + 25,
1090 .vtotal = 480 + 10 + 25 + 10,
1091 .vrefresh = 60,
1092};
1093
1094static const struct panel_desc lg_lb070wv8 = {
1095 .modes = &lg_lb070wv8_mode,
1096 .num_modes = 1,
1097 .bpc = 16,
1098 .size = {
1099 .width = 151,
1100 .height = 91,
1101 },
1102 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1103};
1104
c5ece402
YY		 1105static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1106 .clock = 200000,
1107 .hdisplay = 1536,
1108 .hsync_start = 1536 + 12,
1109 .hsync_end = 1536 + 12 + 16,
1110 .htotal = 1536 + 12 + 16 + 48,
1111 .vdisplay = 2048,
1112 .vsync_start = 2048 + 8,
1113 .vsync_end = 2048 + 8 + 4,
1114 .vtotal = 2048 + 8 + 4 + 8,
1115 .vrefresh = 60,
1116 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1117};
1118
1119static const struct panel_desc lg_lp079qx1_sp0v = {
1120 .modes = &lg_lp079qx1_sp0v_mode,
1121 .num_modes = 1,
1122 .size = {
1123 .width = 129,
1124 .height = 171,
1125 },
1126};
1127
0355dde2
YY		 1128static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1129 .clock = 205210,
1130 .hdisplay = 2048,
1131 .hsync_start = 2048 + 150,
1132 .hsync_end = 2048 + 150 + 5,
1133 .htotal = 2048 + 150 + 5 + 5,
1134 .vdisplay = 1536,
1135 .vsync_start = 1536 + 3,
1136 .vsync_end = 1536 + 3 + 1,
1137 .vtotal = 1536 + 3 + 1 + 9,
1138 .vrefresh = 60,
1139};
1140
1141static const struct panel_desc lg_lp097qx1_spa1 = {
1142 .modes = &lg_lp097qx1_spa1_mode,
1143 .num_modes = 1,
1144 .size = {
1145 .width = 208,
1146 .height = 147,
1147 },
1148};
1149
690d8fa7
JS		 1150static const struct drm_display_mode lg_lp120up1_mode = {
1151 .clock = 162300,
1152 .hdisplay = 1920,
1153 .hsync_start = 1920 + 40,
1154 .hsync_end = 1920 + 40 + 40,
1155 .htotal = 1920 + 40 + 40+ 80,
1156 .vdisplay = 1280,
1157 .vsync_start = 1280 + 4,
1158 .vsync_end = 1280 + 4 + 4,
1159 .vtotal = 1280 + 4 + 4 + 12,
1160 .vrefresh = 60,
1161};
1162
1163static const struct panel_desc lg_lp120up1 = {
1164 .modes = &lg_lp120up1_mode,
1165 .num_modes = 1,
1166 .bpc = 8,
1167 .size = {
1168 .width = 267,
1169 .height = 183,
1170 },
1171};
1172
ec7c5653
TR		 1173static const struct drm_display_mode lg_lp129qe_mode = {
1174 .clock = 285250,
1175 .hdisplay = 2560,
1176 .hsync_start = 2560 + 48,
1177 .hsync_end = 2560 + 48 + 32,
1178 .htotal = 2560 + 48 + 32 + 80,
1179 .vdisplay = 1700,
1180 .vsync_start = 1700 + 3,
1181 .vsync_end = 1700 + 3 + 10,
1182 .vtotal = 1700 + 3 + 10 + 36,
1183 .vrefresh = 60,
1184};
1185
1186static const struct panel_desc lg_lp129qe = {
1187 .modes = &lg_lp129qe_mode,
1188 .num_modes = 1,
0208d511 1189 .bpc = 8,
ec7c5653
TR		 1190 .size = {
1191 .width = 272,
1192 .height = 181,
1193 },
1194};
1195
c6e87f91 1196static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1197 .clock = 10870,
1198 .hdisplay = 480,
1199 .hsync_start = 480 + 2,
1200 .hsync_end = 480 + 2 + 41,
1201 .htotal = 480 + 2 + 41 + 2,
1202 .vdisplay = 272,
1203 .vsync_start = 272 + 2,
1204 .vsync_end = 272 + 2 + 4,
1205 .vtotal = 272 + 2 + 4 + 2,
1206 .vrefresh = 74,
4bc390c6 1207 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 1208};
1209
1210static const struct panel_desc nec_nl4827hc19_05b = {
1211 .modes = &nec_nl4827hc19_05b_mode,
1212 .num_modes = 1,
1213 .bpc = 8,
1214 .size = {
1215 .width = 95,
1216 .height = 54,
1217 },
2c80661d
SA		 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1219 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
c6e87f91 1220};
1221
05ec0e45
FL		 1222static const struct drm_display_mode nvd_9128_mode = {
1223 .clock = 29500,
1224 .hdisplay = 800,
1225 .hsync_start = 800 + 130,
1226 .hsync_end = 800 + 130 + 98,
1227 .htotal = 800 + 0 + 130 + 98,
1228 .vdisplay = 480,
1229 .vsync_start = 480 + 10,
1230 .vsync_end = 480 + 10 + 50,
1231 .vtotal = 480 + 0 + 10 + 50,
1232};
1233
1234static const struct panel_desc nvd_9128 = {
1235 .modes = &nvd_9128_mode,
1236 .num_modes = 1,
1237 .bpc = 8,
1238 .size = {
1239 .width = 156,
1240 .height = 88,
1241 },
1242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1243};
1244
a99fb626
GB		 1245static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1246 .pixelclock = { 30000000, 30000000, 40000000 },
1247 .hactive = { 800, 800, 800 },
1248 .hfront_porch = { 40, 40, 40 },
1249 .hback_porch = { 40, 40, 40 },
1250 .hsync_len = { 1, 48, 48 },
1251 .vactive = { 480, 480, 480 },
1252 .vfront_porch = { 13, 13, 13 },
1253 .vback_porch = { 29, 29, 29 },
1254 .vsync_len = { 3, 3, 3 },
1255 .flags = DISPLAY_FLAGS_DE_HIGH,
1256};
1257
1258static const struct panel_desc okaya_rs800480t_7x0gp = {
1259 .timings = &okaya_rs800480t_7x0gp_timing,
1260 .num_timings = 1,
1261 .bpc = 6,
1262 .size = {
1263 .width = 154,
1264 .height = 87,
1265 },
1266 .delay = {
1267 .prepare = 41,
1268 .enable = 50,
1269 .unprepare = 41,
1270 .disable = 50,
1271 },
1272 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1273};
1274
cf5c9e6d
MR		 1275static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
1276 .clock = 9000,
1277 .hdisplay = 480,
1278 .hsync_start = 480 + 5,
1279 .hsync_end = 480 + 5 + 30,
1280 .htotal = 480 + 5 + 30 + 10,
1281 .vdisplay = 272,
1282 .vsync_start = 272 + 8,
1283 .vsync_end = 272 + 8 + 5,
1284 .vtotal = 272 + 8 + 5 + 3,
1285 .vrefresh = 60,
1286};
1287
1288static const struct panel_desc olimex_lcd_olinuxino_43ts = {
1289 .modes = &olimex_lcd_olinuxino_43ts_mode,
1290 .num_modes = 1,
1291 .size = {
1292 .width = 105,
1293 .height = 67,
1294 },
5c2a7c6b 1295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 1296};
1297
e8b6f561
EA		 1298/*
1299 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
1300 * pixel clocks, but this is the timing that was being used in the Adafruit
1301 * installation instructions.
1302 */
1303static const struct drm_display_mode ontat_yx700wv03_mode = {
1304 .clock = 29500,
1305 .hdisplay = 800,
1306 .hsync_start = 824,
1307 .hsync_end = 896,
1308 .htotal = 992,
1309 .vdisplay = 480,
1310 .vsync_start = 483,
1311 .vsync_end = 493,
1312 .vtotal = 500,
1313 .vrefresh = 60,
1314 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1315};
1316
1317/*
1318 * Specification at:
1319 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
1320 */
1321static const struct panel_desc ontat_yx700wv03 = {
1322 .modes = &ontat_yx700wv03_mode,
1323 .num_modes = 1,
1324 .bpc = 8,
1325 .size = {
1326 .width = 154,
1327 .height = 83,
1328 },
1329 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1330};
1331
725c9d40
PZ		 1332static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1333 .clock = 25000,
1334 .hdisplay = 480,
1335 .hsync_start = 480 + 10,
1336 .hsync_end = 480 + 10 + 10,
1337 .htotal = 480 + 10 + 10 + 15,
1338 .vdisplay = 800,
1339 .vsync_start = 800 + 3,
1340 .vsync_end = 800 + 3 + 3,
1341 .vtotal = 800 + 3 + 3 + 3,
1342 .vrefresh = 60,
1343};
1344
1345static const struct panel_desc ortustech_com43h4m85ulc = {
1346 .modes = &ortustech_com43h4m85ulc_mode,
1347 .num_modes = 1,
1348 .bpc = 8,
1349 .size = {
1350 .width = 56,
1351 .height = 93,
1352 },
1353 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
e0932f9d 1354 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
725c9d40
PZ		 1355};
1356
d2a6f0f5
JW		 1357static const struct drm_display_mode qd43003c0_40_mode = {
1358 .clock = 9000,
1359 .hdisplay = 480,
1360 .hsync_start = 480 + 8,
1361 .hsync_end = 480 + 8 + 4,
1362 .htotal = 480 + 8 + 4 + 39,
1363 .vdisplay = 272,
1364 .vsync_start = 272 + 4,
1365 .vsync_end = 272 + 4 + 10,
1366 .vtotal = 272 + 4 + 10 + 2,
1367 .vrefresh = 60,
1368};
1369
1370static const struct panel_desc qd43003c0_40 = {
1371 .modes = &qd43003c0_40_mode,
1372 .num_modes = 1,
1373 .bpc = 8,
1374 .size = {
1375 .width = 95,
1376 .height = 53,
1377 },
1378 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1379};
1380
0330eaf3
YY		 1381static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1382 .clock = 271560,
1383 .hdisplay = 2560,
1384 .hsync_start = 2560 + 48,
1385 .hsync_end = 2560 + 48 + 32,
1386 .htotal = 2560 + 48 + 32 + 80,
1387 .vdisplay = 1600,
1388 .vsync_start = 1600 + 2,
1389 .vsync_end = 1600 + 2 + 5,
1390 .vtotal = 1600 + 2 + 5 + 57,
1391 .vrefresh = 60,
1392};
1393
1394static const struct panel_desc samsung_lsn122dl01_c01 = {
1395 .modes = &samsung_lsn122dl01_c01_mode,
1396 .num_modes = 1,
1397 .size = {
1398 .width = 263,
1399 .height = 164,
1400 },
1401};
1402
6d54e3d2
MD		 1403static const struct drm_display_mode samsung_ltn101nt05_mode = {
1404 .clock = 54030,
1405 .hdisplay = 1024,
1406 .hsync_start = 1024 + 24,
1407 .hsync_end = 1024 + 24 + 136,
1408 .htotal = 1024 + 24 + 136 + 160,
1409 .vdisplay = 600,
1410 .vsync_start = 600 + 3,
1411 .vsync_end = 600 + 3 + 6,
1412 .vtotal = 600 + 3 + 6 + 61,
1413 .vrefresh = 60,
1414};
1415
1416static const struct panel_desc samsung_ltn101nt05 = {
1417 .modes = &samsung_ltn101nt05_mode,
1418 .num_modes = 1,
0208d511 1419 .bpc = 6,
6d54e3d2 1420 .size = {
81598846
TR		 1421 .width = 223,
1422 .height = 125,
6d54e3d2
MD		 1423 },
1424};
1425
0c934306
SM		 1426static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1427 .clock = 76300,
1428 .hdisplay = 1366,
1429 .hsync_start = 1366 + 64,
1430 .hsync_end = 1366 + 64 + 48,
1431 .htotal = 1366 + 64 + 48 + 128,
1432 .vdisplay = 768,
1433 .vsync_start = 768 + 2,
1434 .vsync_end = 768 + 2 + 5,
1435 .vtotal = 768 + 2 + 5 + 17,
1436 .vrefresh = 60,
1437};
1438
1439static const struct panel_desc samsung_ltn140at29_301 = {
1440 .modes = &samsung_ltn140at29_301_mode,
1441 .num_modes = 1,
1442 .bpc = 6,
1443 .size = {
1444 .width = 320,
1445 .height = 187,
1446 },
1447};
1448
592aa02b
JC		 1449static const struct display_timing sharp_lq101k1ly04_timing = {
1450 .pixelclock = { 60000000, 65000000, 80000000 },
1451 .hactive = { 1280, 1280, 1280 },
1452 .hfront_porch = { 20, 20, 20 },
1453 .hback_porch = { 20, 20, 20 },
1454 .hsync_len = { 10, 10, 10 },
1455 .vactive = { 800, 800, 800 },
1456 .vfront_porch = { 4, 4, 4 },
1457 .vback_porch = { 4, 4, 4 },
1458 .vsync_len = { 4, 4, 4 },
1459 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
1460};
1461
1462static const struct panel_desc sharp_lq101k1ly04 = {
1463 .timings = &sharp_lq101k1ly04_timing,
1464 .num_timings = 1,
1465 .bpc = 8,
1466 .size = {
1467 .width = 217,
1468 .height = 136,
1469 },
1470 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1471};
1472
739c7de9
YY		 1473static const struct drm_display_mode sharp_lq123p1jx31_mode = {
1474 .clock = 252750,
1475 .hdisplay = 2400,
1476 .hsync_start = 2400 + 48,
1477 .hsync_end = 2400 + 48 + 32,
1478 .htotal = 2400 + 48 + 32 + 80,
1479 .vdisplay = 1600,
1480 .vsync_start = 1600 + 3,
1481 .vsync_end = 1600 + 3 + 10,
1482 .vtotal = 1600 + 3 + 10 + 33,
1483 .vrefresh = 60,
1484 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1485};
1486
1487static const struct panel_desc sharp_lq123p1jx31 = {
1488 .modes = &sharp_lq123p1jx31_mode,
1489 .num_modes = 1,
5466a631 1490 .bpc = 8,
739c7de9
YY		 1491 .size = {
1492 .width = 259,
1493 .height = 173,
1494 },
a42f6e3f
YY		 1495 .delay = {
1496 .prepare = 110,
1497 .enable = 50,
1498 .unprepare = 550,
1499 },
739c7de9
YY		 1500};
1501
0f9cdd74
GL		 1502static const struct drm_display_mode sharp_lq150x1lg11_mode = {
1503 .clock = 71100,
1504 .hdisplay = 1024,
1505 .hsync_start = 1024 + 168,
1506 .hsync_end = 1024 + 168 + 64,
1507 .htotal = 1024 + 168 + 64 + 88,
1508 .vdisplay = 768,
1509 .vsync_start = 768 + 37,
1510 .vsync_end = 768 + 37 + 2,
1511 .vtotal = 768 + 37 + 2 + 8,
1512 .vrefresh = 60,
1513};
1514
1515static const struct panel_desc sharp_lq150x1lg11 = {
1516 .modes = &sharp_lq150x1lg11_mode,
1517 .num_modes = 1,
1518 .bpc = 6,
1519 .size = {
1520 .width = 304,
1521 .height = 228,
1522 },
1523 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
1524};
1525
9c6615bc
BB		 1526static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1527 .clock = 33300,
1528 .hdisplay = 800,
1529 .hsync_start = 800 + 1,
1530 .hsync_end = 800 + 1 + 64,
1531 .htotal = 800 + 1 + 64 + 64,
1532 .vdisplay = 480,
1533 .vsync_start = 480 + 1,
1534 .vsync_end = 480 + 1 + 23,
1535 .vtotal = 480 + 1 + 23 + 22,
1536 .vrefresh = 60,
1537};
1538
1539static const struct panel_desc shelly_sca07010_bfn_lnn = {
1540 .modes = &shelly_sca07010_bfn_lnn_mode,
1541 .num_modes = 1,
1542 .size = {
1543 .width = 152,
1544 .height = 91,
1545 },
1546 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1547};
1548
9bb34c4c
DA		 1549static const struct drm_display_mode starry_kr122ea0sra_mode = {
1550 .clock = 147000,
1551 .hdisplay = 1920,
1552 .hsync_start = 1920 + 16,
1553 .hsync_end = 1920 + 16 + 16,
1554 .htotal = 1920 + 16 + 16 + 32,
1555 .vdisplay = 1200,
1556 .vsync_start = 1200 + 15,
1557 .vsync_end = 1200 + 15 + 2,
1558 .vtotal = 1200 + 15 + 2 + 18,
1559 .vrefresh = 60,
1560 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1561};
1562
1563static const struct panel_desc starry_kr122ea0sra = {
1564 .modes = &starry_kr122ea0sra_mode,
1565 .num_modes = 1,
1566 .size = {
1567 .width = 263,
1568 .height = 164,
1569 },
c46b924b
BN		 1570 .delay = {
1571 .prepare = 10 + 200,
1572 .enable = 50,
1573 .unprepare = 10 + 500,
1574 },
9bb34c4c
DA		 1575};
1576
227e4f40
BD		 1577static const struct drm_display_mode tpk_f07a_0102_mode = {
1578 .clock = 33260,
1579 .hdisplay = 800,
1580 .hsync_start = 800 + 40,
1581 .hsync_end = 800 + 40 + 128,
1582 .htotal = 800 + 40 + 128 + 88,
1583 .vdisplay = 480,
1584 .vsync_start = 480 + 10,
1585 .vsync_end = 480 + 10 + 2,
1586 .vtotal = 480 + 10 + 2 + 33,
1587 .vrefresh = 60,
1588};
1589
1590static const struct panel_desc tpk_f07a_0102 = {
1591 .modes = &tpk_f07a_0102_mode,
1592 .num_modes = 1,
1593 .size = {
1594 .width = 152,
1595 .height = 91,
1596 },
1597 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
1598};
1599
1600static const struct drm_display_mode tpk_f10a_0102_mode = {
1601 .clock = 45000,
1602 .hdisplay = 1024,
1603 .hsync_start = 1024 + 176,
1604 .hsync_end = 1024 + 176 + 5,
1605 .htotal = 1024 + 176 + 5 + 88,
1606 .vdisplay = 600,
1607 .vsync_start = 600 + 20,
1608 .vsync_end = 600 + 20 + 5,
1609 .vtotal = 600 + 20 + 5 + 25,
1610 .vrefresh = 60,
1611};
1612
1613static const struct panel_desc tpk_f10a_0102 = {
1614 .modes = &tpk_f10a_0102_mode,
1615 .num_modes = 1,
1616 .size = {
1617 .width = 223,
1618 .height = 125,
1619 },
1620};
1621
06a9dc65
MS		 1622static const struct display_timing urt_umsh_8596md_timing = {
1623 .pixelclock = { 33260000, 33260000, 33260000 },
1624 .hactive = { 800, 800, 800 },
1625 .hfront_porch = { 41, 41, 41 },
1626 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
1627 .hsync_len = { 71, 128, 128 },
1628 .vactive = { 480, 480, 480 },
1629 .vfront_porch = { 10, 10, 10 },
1630 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
1631 .vsync_len = { 2, 2, 2 },
1632 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1633 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1634};
1635
1636static const struct panel_desc urt_umsh_8596md_lvds = {
1637 .timings = &urt_umsh_8596md_timing,
1638 .num_timings = 1,
1639 .bpc = 6,
1640 .size = {
1641 .width = 152,
1642 .height = 91,
1643 },
1644 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1645};
1646
1647static const struct panel_desc urt_umsh_8596md_parallel = {
1648 .timings = &urt_umsh_8596md_timing,
1649 .num_timings = 1,
1650 .bpc = 6,
1651 .size = {
1652 .width = 152,
1653 .height = 91,
1654 },
1655 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1656};
1657
280921de
TR		 1658static const struct of_device_id platform_of_match[] = {
1659 {
1c550fa1
PZ		 1660 .compatible = "ampire,am800480r3tmqwa1h",
1661 .data = &ampire_am800480r3tmqwa1h,
1662 }, {
280921de
TR		 1663 .compatible = "auo,b101aw03",
1664 .data = &auo_b101aw03,
a531bc3d
HL		 1665 }, {
1666 .compatible = "auo,b101ean01",
1667 .data = &auo_b101ean01,
dac746e0
RC		 1668 }, {
1669 .compatible = "auo,b101xtn01",
1670 .data = &auo_b101xtn01,
e35e305e
AK		 1671 }, {
1672 .compatible = "auo,b116xw03",
1673 .data = &auo_b116xw03,
3e51d609
AK		 1674 }, {
1675 .compatible = "auo,b133htn01",
1676 .data = &auo_b133htn01,
a333f7ad
SM		 1677 }, {
1678 .compatible = "auo,b133xtn01",
1679 .data = &auo_b133xtn01,
7ee933a1
HS		 1680 }, {
1681 .compatible = "auo,t215hvn01",
1682 .data = &auo_t215hvn01,
d47df633
PZ		 1683 }, {
1684 .compatible = "avic,tm070ddh03",
1685 .data = &avic_tm070ddh03,
2cb35c80
RL		 1686 }, {
1687 .compatible = "chunghwa,claa070wp03xg",
1688 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 1689 }, {
1690 .compatible = "chunghwa,claa101wa01a",
1691 .data = &chunghwa_claa101wa01a
280921de
TR		 1692 }, {
1693 .compatible = "chunghwa,claa101wb01",
1694 .data = &chunghwa_claa101wb01
26ab0065
SA		 1695 }, {
1696 .compatible = "edt,et057090dhu",
1697 .data = &edt_et057090dhu,
fff5de45
PZ		 1698 }, {
1699 .compatible = "edt,et070080dh6",
1700 .data = &edt_etm0700g0dh6,
1701 }, {
1702 .compatible = "edt,etm0700g0dh6",
1703 .data = &edt_etm0700g0dh6,
102932b0
BB		 1704 }, {
1705 .compatible = "foxlink,fl500wvr00-a0t",
1706 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 1707 }, {
1708 .compatible = "giantplus,gpg482739qs5",
1709 .data = &giantplus_gpg482739qs5
a853205e
PZ		 1710 }, {
1711 .compatible = "hannstar,hsd070pww1",
1712 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 1713 }, {
1714 .compatible = "hannstar,hsd100pxn1",
1715 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 1716 }, {
1717 .compatible = "hit,tx23d38vm0caa",
1718 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 1719 }, {
1720 .compatible = "innolux,at043tn24",
1721 .data = &innolux_at043tn24,
4fc24ab3
RB		 1722 }, {
1723 .compatible = "innolux,at070tn92",
1724 .data = &innolux_at070tn92,
1e29b840
MO		 1725 }, {
1726 .compatible ="innolux,g101ice-l01",
1727 .data = &innolux_g101ice_l01
d731f661
LS		 1728 }, {
1729 .compatible ="innolux,g121i1-l01",
1730 .data = &innolux_g121i1_l01
f8fa17ba
AB		 1731 }, {
1732 .compatible = "innolux,g121x1-l03",
1733 .data = &innolux_g121x1_l03,
0a2288c0
TR		 1734 }, {
1735 .compatible = "innolux,n116bge",
1736 .data = &innolux_n116bge,
ea44739d
AB		 1737 }, {
1738 .compatible = "innolux,n156bge-l21",
1739 .data = &innolux_n156bge_l21,
bccac3f1
MG		 1740 }, {
1741 .compatible = "innolux,zj070na-01p",
1742 .data = &innolux_zj070na_01p,
8def22e5
LS		 1743 }, {
1744 .compatible = "kyo,tcg121xglp",
1745 .data = &kyo_tcg121xglp,
dd015002
HS		 1746 }, {
1747 .compatible = "lg,lb070wv8",
1748 .data = &lg_lb070wv8,
c5ece402
YY		 1749 }, {
1750 .compatible = "lg,lp079qx1-sp0v",
1751 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 1752 }, {
1753 .compatible = "lg,lp097qx1-spa1",
1754 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 1755 }, {
1756 .compatible = "lg,lp120up1",
1757 .data = &lg_lp120up1,
ec7c5653
TR		 1758 }, {
1759 .compatible = "lg,lp129qe",
1760 .data = &lg_lp129qe,
c6e87f91 1761 }, {
1762 .compatible = "nec,nl4827hc19-05b",
1763 .data = &nec_nl4827hc19_05b,
05ec0e45
FL		 1764 }, {
1765 .compatible = "nvd,9128",
1766 .data = &nvd_9128,
a99fb626
GB		 1767 }, {
1768 .compatible = "okaya,rs800480t-7x0gp",
1769 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 1770 }, {
1771 .compatible = "olimex,lcd-olinuxino-43-ts",
1772 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 1773 }, {
1774 .compatible = "ontat,yx700wv03",
1775 .data = &ontat_yx700wv03,
725c9d40
PZ		 1776 }, {
1777 .compatible = "ortustech,com43h4m85ulc",
1778 .data = &ortustech_com43h4m85ulc,
d2a6f0f5
JW		 1779 }, {
1780 .compatible = "qiaodian,qd43003c0-40",
1781 .data = &qd43003c0_40,
0330eaf3
YY		 1782 }, {
1783 .compatible = "samsung,lsn122dl01-c01",
1784 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 1785 }, {
1786 .compatible = "samsung,ltn101nt05",
1787 .data = &samsung_ltn101nt05,
0c934306
SM		 1788 }, {
1789 .compatible = "samsung,ltn140at29-301",
1790 .data = &samsung_ltn140at29_301,
592aa02b
JC		 1791 }, {
1792 .compatible = "sharp,lq101k1ly04",
1793 .data = &sharp_lq101k1ly04,
739c7de9
YY		 1794 }, {
1795 .compatible = "sharp,lq123p1jx31",
1796 .data = &sharp_lq123p1jx31,
0f9cdd74
GL		 1797 }, {
1798 .compatible = "sharp,lq150x1lg11",
1799 .data = &sharp_lq150x1lg11,
9c6615bc
BB		 1800 }, {
1801 .compatible = "shelly,sca07010-bfn-lnn",
1802 .data = &shelly_sca07010_bfn_lnn,
9bb34c4c
DA		 1803 }, {
1804 .compatible = "starry,kr122ea0sra",
1805 .data = &starry_kr122ea0sra,
227e4f40
BD		 1806 }, {
1807 .compatible = "tpk,f07a-0102",
1808 .data = &tpk_f07a_0102,
1809 }, {
1810 .compatible = "tpk,f10a-0102",
1811 .data = &tpk_f10a_0102,
06a9dc65
MS		 1812 }, {
1813 .compatible = "urt,umsh-8596md-t",
1814 .data = &urt_umsh_8596md_parallel,
1815 }, {
1816 .compatible = "urt,umsh-8596md-1t",
1817 .data = &urt_umsh_8596md_parallel,
1818 }, {
1819 .compatible = "urt,umsh-8596md-7t",
1820 .data = &urt_umsh_8596md_parallel,
1821 }, {
1822 .compatible = "urt,umsh-8596md-11t",
1823 .data = &urt_umsh_8596md_lvds,
1824 }, {
1825 .compatible = "urt,umsh-8596md-19t",
1826 .data = &urt_umsh_8596md_lvds,
1827 }, {
1828 .compatible = "urt,umsh-8596md-20t",
1829 .data = &urt_umsh_8596md_parallel,
280921de
TR		 1830 }, {
1831 /* sentinel */
1832 }
1833};
1834MODULE_DEVICE_TABLE(of, platform_of_match);
1835
1836static int panel_simple_platform_probe(struct platform_device *pdev)
1837{
1838 const struct of_device_id *id;
1839
1840 id = of_match_node(platform_of_match, pdev->dev.of_node);
1841 if (!id)
1842 return -ENODEV;
1843
1844 return panel_simple_probe(&pdev->dev, id->data);
1845}
1846
1847static int panel_simple_platform_remove(struct platform_device *pdev)
1848{
1849 return panel_simple_remove(&pdev->dev);
1850}
1851
d02fd93e
TR		 1852static void panel_simple_platform_shutdown(struct platform_device *pdev)
1853{
1854 panel_simple_shutdown(&pdev->dev);
1855}
1856
280921de
TR		 1857static struct platform_driver panel_simple_platform_driver = {
1858 .driver = {
1859 .name = "panel-simple",
280921de
TR		 1860 .of_match_table = platform_of_match,
1861 },
1862 .probe = panel_simple_platform_probe,
1863 .remove = panel_simple_platform_remove,
d02fd93e 1864 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1865};
1866
210fcd9d
TR		 1867struct panel_desc_dsi {
1868 struct panel_desc desc;
1869
462658b8 1870 unsigned long flags;
210fcd9d
TR		 1871 enum mipi_dsi_pixel_format format;
1872 unsigned int lanes;
1873};
1874
d718d79e
TR		 1875static const struct drm_display_mode auo_b080uan01_mode = {
1876 .clock = 154500,
1877 .hdisplay = 1200,
1878 .hsync_start = 1200 + 62,
1879 .hsync_end = 1200 + 62 + 4,
1880 .htotal = 1200 + 62 + 4 + 62,
1881 .vdisplay = 1920,
1882 .vsync_start = 1920 + 9,
1883 .vsync_end = 1920 + 9 + 2,
1884 .vtotal = 1920 + 9 + 2 + 8,
1885 .vrefresh = 60,
1886};
1887
1888static const struct panel_desc_dsi auo_b080uan01 = {
1889 .desc = {
1890 .modes = &auo_b080uan01_mode,
1891 .num_modes = 1,
1892 .bpc = 8,
1893 .size = {
1894 .width = 108,
1895 .height = 272,
1896 },
1897 },
1898 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1899 .format = MIPI_DSI_FMT_RGB888,
1900 .lanes = 4,
1901};
1902
c8521969
CZ		 1903static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1904 .clock = 160000,
1905 .hdisplay = 1200,
1906 .hsync_start = 1200 + 120,
1907 .hsync_end = 1200 + 120 + 20,
1908 .htotal = 1200 + 120 + 20 + 21,
1909 .vdisplay = 1920,
1910 .vsync_start = 1920 + 21,
1911 .vsync_end = 1920 + 21 + 3,
1912 .vtotal = 1920 + 21 + 3 + 18,
1913 .vrefresh = 60,
1914 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1915};
1916
1917static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1918 .desc = {
1919 .modes = &boe_tv080wum_nl0_mode,
1920 .num_modes = 1,
1921 .size = {
1922 .width = 107,
1923 .height = 172,
1924 },
1925 },
1926 .flags = MIPI_DSI_MODE_VIDEO |
1927 MIPI_DSI_MODE_VIDEO_BURST |
1928 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1929 .format = MIPI_DSI_FMT_RGB888,
1930 .lanes = 4,
1931};
1932
712ac1ba
AC		 1933static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1934 .clock = 71000,
1935 .hdisplay = 800,
1936 .hsync_start = 800 + 32,
1937 .hsync_end = 800 + 32 + 1,
1938 .htotal = 800 + 32 + 1 + 57,
1939 .vdisplay = 1280,
1940 .vsync_start = 1280 + 28,
1941 .vsync_end = 1280 + 28 + 1,
1942 .vtotal = 1280 + 28 + 1 + 14,
1943 .vrefresh = 60,
1944};
1945
1946static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1947 .desc = {
1948 .modes = &lg_ld070wx3_sl01_mode,
1949 .num_modes = 1,
d7a839cd 1950 .bpc = 8,
712ac1ba
AC		 1951 .size = {
1952 .width = 94,
1953 .height = 151,
1954 },
1955 },
5e4cc278 1956 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1957 .format = MIPI_DSI_FMT_RGB888,
1958 .lanes = 4,
1959};
1960
499ce85a
AC		 1961static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1962 .clock = 67000,
1963 .hdisplay = 720,
1964 .hsync_start = 720 + 12,
1965 .hsync_end = 720 + 12 + 4,
1966 .htotal = 720 + 12 + 4 + 112,
1967 .vdisplay = 1280,
1968 .vsync_start = 1280 + 8,
1969 .vsync_end = 1280 + 8 + 4,
1970 .vtotal = 1280 + 8 + 4 + 12,
1971 .vrefresh = 60,
1972};
1973
1974static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1975 .desc = {
1976 .modes = &lg_lh500wx1_sd03_mode,
1977 .num_modes = 1,
d7a839cd 1978 .bpc = 8,
499ce85a
AC		 1979 .size = {
1980 .width = 62,
1981 .height = 110,
1982 },
1983 },
1984 .flags = MIPI_DSI_MODE_VIDEO,
1985 .format = MIPI_DSI_FMT_RGB888,
1986 .lanes = 4,
1987};
1988
280921de
TR		 1989static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1990 .clock = 157200,
1991 .hdisplay = 1920,
1992 .hsync_start = 1920 + 154,
1993 .hsync_end = 1920 + 154 + 16,
1994 .htotal = 1920 + 154 + 16 + 32,
1995 .vdisplay = 1200,
1996 .vsync_start = 1200 + 17,
1997 .vsync_end = 1200 + 17 + 2,
1998 .vtotal = 1200 + 17 + 2 + 16,
1999 .vrefresh = 60,
2000};
2001
210fcd9d
TR		 2002static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
2003 .desc = {
2004 .modes = &panasonic_vvx10f004b00_mode,
2005 .num_modes = 1,
d7a839cd 2006 .bpc = 8,
210fcd9d
TR		 2007 .size = {
2008 .width = 217,
2009 .height = 136,
2010 },
280921de 2011 },
5e4cc278
AC		 2012 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2013 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 2014 .format = MIPI_DSI_FMT_RGB888,
2015 .lanes = 4,
2016};
2017
2018static const struct of_device_id dsi_of_match[] = {
2019 {
d718d79e
TR		 2020 .compatible = "auo,b080uan01",
2021 .data = &auo_b080uan01
c8521969
CZ		 2022 }, {
2023 .compatible = "boe,tv080wum-nl0",
2024 .data = &boe_tv080wum_nl0
d718d79e 2025 }, {
712ac1ba
AC		 2026 .compatible = "lg,ld070wx3-sl01",
2027 .data = &lg_ld070wx3_sl01
2028 }, {
499ce85a
AC		 2029 .compatible = "lg,lh500wx1-sd03",
2030 .data = &lg_lh500wx1_sd03
2031 }, {
210fcd9d
TR		 2032 .compatible = "panasonic,vvx10f004b00",
2033 .data = &panasonic_vvx10f004b00
2034 }, {
2035 /* sentinel */
2036 }
2037};
2038MODULE_DEVICE_TABLE(of, dsi_of_match);
2039
2040static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
2041{
2042 const struct panel_desc_dsi *desc;
2043 const struct of_device_id *id;
2044 int err;
2045
2046 id = of_match_node(dsi_of_match, dsi->dev.of_node);
2047 if (!id)
2048 return -ENODEV;
2049
2050 desc = id->data;
2051
2052 err = panel_simple_probe(&dsi->dev, &desc->desc);
2053 if (err < 0)
2054 return err;
2055
462658b8 2056 dsi->mode_flags = desc->flags;
210fcd9d
TR		 2057 dsi->format = desc->format;
2058 dsi->lanes = desc->lanes;
2059
2060 return mipi_dsi_attach(dsi);
2061}
2062
2063static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2064{
2065 int err;
2066
2067 err = mipi_dsi_detach(dsi);
2068 if (err < 0)
2069 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2070
2071 return panel_simple_remove(&dsi->dev);
2072}
2073
d02fd93e
TR		 2074static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2075{
2076 panel_simple_shutdown(&dsi->dev);
2077}
2078
210fcd9d
TR		 2079static struct mipi_dsi_driver panel_simple_dsi_driver = {
2080 .driver = {
2081 .name = "panel-simple-dsi",
210fcd9d
TR		 2082 .of_match_table = dsi_of_match,
2083 },
2084 .probe = panel_simple_dsi_probe,
2085 .remove = panel_simple_dsi_remove,
d02fd93e 2086 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 2087};
2088
2089static int __init panel_simple_init(void)
2090{
210fcd9d
TR		 2091 int err;
2092
2093 err = platform_driver_register(&panel_simple_platform_driver);
2094 if (err < 0)
2095 return err;
2096
2097 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2098 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2099 if (err < 0)
2100 return err;
2101 }
2102
2103 return 0;
280921de
TR		 2104}
2105module_init(panel_simple_init);
2106
2107static void __exit panel_simple_exit(void)
2108{
210fcd9d
TR		 2109 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2110 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2111
280921de
TR		 2112 platform_driver_unregister(&panel_simple_platform_driver);
2113}
2114module_exit(panel_simple_exit);
2115
2116MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2117MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2118MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)