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video: ep93xx: Prepare clock before using it
[linux-2.6-block.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
cb23eae3 24#include <linux/delay.h>
cfdf0549 25#include <linux/gpio/consumer.h>
48834e60 26#include <linux/iopoll.h>
280921de 27#include <linux/module.h>
280921de
TR		 28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
3235b0f2 30#include <linux/pm_runtime.h>
280921de
TR		 31#include <linux/regulator/consumer.h>
32
cb23eae3 33#include <video/display_timing.h>
b8a2948f 34#include <video/of_display_timing.h>
cb23eae3
SR		 35#include <video/videomode.h>
36
280921de 37#include <drm/drm_crtc.h>
cb23eae3 38#include <drm/drm_device.h>
74c06c28 39#include <drm/drm_dp_aux_bus.h>
cc5a3fc0 40#include <drm/drm_dp_helper.h>
210fcd9d 41#include <drm/drm_mipi_dsi.h>
280921de
TR		 42#include <drm/drm_panel.h>
43
e362cc6a 44/**
a00fa428 45 * struct panel_desc - Describes a simple panel.
e362cc6a 46 */
280921de 47struct panel_desc {
a00fa428
DA		 48 /**
49 * @modes: Pointer to array of fixed modes appropriate for this panel.
50 *
51 * If only one mode then this can just be the address of the mode.
52 * NOTE: cannot be used with "timings" and also if this is specified
53 * then you cannot override the mode in the device tree.
54 */
280921de 55 const struct drm_display_mode *modes;
a00fa428
DA		 56
57 /** @num_modes: Number of elements in modes array. */
280921de 58 unsigned int num_modes;
a00fa428
DA		 59
60 /**
61 * @timings: Pointer to array of display timings
62 *
63 * NOTE: cannot be used with "modes" and also these will be used to
64 * validate a device tree override if one is present.
65 */
a5d3e625 66 const struct display_timing *timings;
a00fa428
DA		 67
68 /** @num_timings: Number of elements in timings array. */
a5d3e625 69 unsigned int num_timings;
280921de 70
a00fa428 71 /** @bpc: Bits per color. */
0208d511
SM		 72 unsigned int bpc;
73
a00fa428 74 /** @size: Structure containing the physical size of this panel. */
280921de 75 struct {
131f909a
DA		 76 /**
77 * @size.width: Width (in mm) of the active display area.
78 */
280921de 79 unsigned int width;
131f909a
DA		 80
81 /**
82 * @size.height: Height (in mm) of the active display area.
83 */
280921de
TR		 84 unsigned int height;
85 } size;
f673c37e 86
a00fa428 87 /** @delay: Structure containing various delay values for this panel. */
f673c37e 88 struct {
131f909a
DA		 89 /**
90 * @delay.prepare: Time for the panel to become ready.
91 *
92 * The time (in milliseconds) that it takes for the panel to
93 * become ready and start receiving video data
94 */
f673c37e 95 unsigned int prepare;
131f909a
DA		 96
97 /**
98 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up.
99 *
100 * Add this to the prepare delay if we know Hot Plug Detect
101 * isn't used.
102 */
2ed3e951 103 unsigned int hpd_absent_delay;
131f909a 104
4beb04be
DA		 105 /**
106 * @delay.prepare_to_enable: Time between prepare and enable.
107 *
108 * The minimum time, in milliseconds, that needs to have passed
109 * between when prepare finished and enable may begin. If at
110 * enable time less time has passed since prepare finished,
111 * the driver waits for the remaining time.
112 *
113 * If a fixed enable delay is also specified, we'll start
114 * counting before delaying for the fixed delay.
115 *
116 * If a fixed prepare delay is also specified, we won't start
117 * counting until after the fixed delay. We can't overlap this
118 * fixed delay with the min time because the fixed delay
119 * doesn't happen at the end of the function if a HPD GPIO was
120 * specified.
121 *
122 * In other words:
123 * prepare()
124 * ...
125 * // do fixed prepare delay
126 * // wait for HPD GPIO if applicable
127 * // start counting for prepare_to_enable
128 *
129 * enable()
130 * // do fixed enable delay
131 * // enforce prepare_to_enable min time
132 */
133 unsigned int prepare_to_enable;
134
18a1488b
RN		 135 /**
136 * @delay.power_to_enable: Time for the power to enable the display on.
137 *
138 * The time (in milliseconds) to wait after powering up the display
139 * before asserting its enable pin.
140 */
141 unsigned int power_to_enable;
142
143 /**
144 * @delay.disable_to_power_off: Time for the disable to power the display off.
145 *
146 * The time (in milliseconds) to wait before powering off the display
147 * after deasserting its enable pin.
148 */
149 unsigned int disable_to_power_off;
150
131f909a
DA		 151 /**
152 * @delay.enable: Time for the panel to display a valid frame.
153 *
154 * The time (in milliseconds) that it takes for the panel to
155 * display the first valid frame after starting to receive
156 * video data.
157 */
f673c37e 158 unsigned int enable;
131f909a
DA		 159
160 /**
161 * @delay.disable: Time for the panel to turn the display off.
162 *
163 * The time (in milliseconds) that it takes for the panel to
164 * turn the display off (no content is visible).
165 */
f673c37e 166 unsigned int disable;
131f909a
DA		 167
168 /**
169 * @delay.unprepare: Time to power down completely.
170 *
171 * The time (in milliseconds) that it takes for the panel
172 * to power itself down completely.
e5e30dfc
DA		 173 *
174 * This time is used to prevent a future "prepare" from
175 * starting until at least this many milliseconds has passed.
176 * If at prepare time less time has passed since unprepare
177 * finished, the driver waits for the remaining time.
131f909a 178 */
f673c37e
AK		 179 unsigned int unprepare;
180 } delay;
795f7ab3 181
a00fa428 182 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
795f7ab3 183 u32 bus_format;
a00fa428
DA		 184
185 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
f0aa0838 186 u32 bus_flags;
a00fa428
DA		 187
188 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
9a2654c0 189 int connector_type;
280921de
TR		 190};
191
280921de
TR		 192struct panel_simple {
193 struct drm_panel base;
194 bool enabled;
2ed3e951 195 bool no_hpd;
280921de 196
3235b0f2
DA		 197 bool prepared;
198
4beb04be 199 ktime_t prepared_time;
e5e30dfc
DA		 200 ktime_t unprepared_time;
201
280921de
TR		 202 const struct panel_desc *desc;
203
280921de
TR		 204 struct regulator *supply;
205 struct i2c_adapter *ddc;
cc5a3fc0 206 struct drm_dp_aux *aux;
280921de 207
cfdf0549 208 struct gpio_desc *enable_gpio;
48834e60 209 struct gpio_desc *hpd_gpio;
b8a2948f 210
63358e24
DA		 211 struct edid *edid;
212
b8a2948f 213 struct drm_display_mode override_mode;
5759c967
DO		 214
215 enum drm_panel_orientation orientation;
280921de
TR		 216};
217
218static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
219{
220 return container_of(panel, struct panel_simple, base);
221}
222
0ce8ddd8
SR		 223static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
224 struct drm_connector *connector)
280921de 225{
280921de
TR		 226 struct drm_display_mode *mode;
227 unsigned int i, num = 0;
228
a5d3e625
PZ		 229 for (i = 0; i < panel->desc->num_timings; i++) {
230 const struct display_timing *dt = &panel->desc->timings[i];
231 struct videomode vm;
232
233 videomode_from_timing(dt, &vm);
aa6c4364 234 mode = drm_mode_create(connector->dev);
a5d3e625 235 if (!mode) {
aa6c4364 236 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
a5d3e625
PZ		 237 dt->hactive.typ, dt->vactive.typ);
238 continue;
239 }
240
241 drm_display_mode_from_videomode(&vm, mode);
cda55372
BB		 242
243 mode->type |= DRM_MODE_TYPE_DRIVER;
244
230c5b44 245 if (panel->desc->num_timings == 1)
cda55372
BB		 246 mode->type |= DRM_MODE_TYPE_PREFERRED;
247
a5d3e625
PZ		 248 drm_mode_probed_add(connector, mode);
249 num++;
250 }
251
b8a2948f
SP		 252 return num;
253}
254
0ce8ddd8
SR		 255static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
256 struct drm_connector *connector)
b8a2948f 257{
b8a2948f
SP		 258 struct drm_display_mode *mode;
259 unsigned int i, num = 0;
260
280921de
TR		 261 for (i = 0; i < panel->desc->num_modes; i++) {
262 const struct drm_display_mode *m = &panel->desc->modes[i];
263
aa6c4364 264 mode = drm_mode_duplicate(connector->dev, m);
280921de 265 if (!mode) {
aa6c4364 266 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
0425662f
VS		 267 m->hdisplay, m->vdisplay,
268 drm_mode_vrefresh(m));
280921de
TR		 269 continue;
270 }
271
cda55372
BB		 272 mode->type |= DRM_MODE_TYPE_DRIVER;
273
274 if (panel->desc->num_modes == 1)
275 mode->type |= DRM_MODE_TYPE_PREFERRED;
276
280921de
TR		 277 drm_mode_set_name(mode);
278
279 drm_mode_probed_add(connector, mode);
280 num++;
281 }
282
b8a2948f
SP		 283 return num;
284}
285
0ce8ddd8
SR		 286static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
287 struct drm_connector *connector)
b8a2948f 288{
b8a2948f
SP		 289 struct drm_display_mode *mode;
290 bool has_override = panel->override_mode.type;
291 unsigned int num = 0;
292
293 if (!panel->desc)
294 return 0;
295
296 if (has_override) {
aa6c4364
SR		 297 mode = drm_mode_duplicate(connector->dev,
298 &panel->override_mode);
b8a2948f
SP		 299 if (mode) {
300 drm_mode_probed_add(connector, mode);
301 num = 1;
302 } else {
aa6c4364 303 dev_err(panel->base.dev, "failed to add override mode\n");
b8a2948f
SP		 304 }
305 }
306
307 /* Only add timings if override was not there or failed to validate */
308 if (num == 0 && panel->desc->num_timings)
0ce8ddd8 309 num = panel_simple_get_timings_modes(panel, connector);
b8a2948f
SP		 310
311 /*
312 * Only add fixed modes if timings/override added no mode.
313 *
314 * We should only ever have either the display timings specified
315 * or a fixed mode. Anything else is rather bogus.
316 */
317 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
318 if (num == 0)
0ce8ddd8 319 num = panel_simple_get_display_modes(panel, connector);
b8a2948f 320
0208d511 321 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 322 connector->display_info.width_mm = panel->desc->size.width;
323 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 324 if (panel->desc->bus_format)
325 drm_display_info_set_bus_formats(&connector->display_info,
326 &panel->desc->bus_format, 1);
f0aa0838 327 connector->display_info.bus_flags = panel->desc->bus_flags;
280921de
TR		 328
329 return num;
330}
331
e5e30dfc
DA		 332static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
333{
334 ktime_t now_ktime, min_ktime;
335
336 if (!min_ms)
337 return;
338
339 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
340 now_ktime = ktime_get();
341
342 if (ktime_before(now_ktime, min_ktime))
343 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
344}
345
280921de
TR		 346static int panel_simple_disable(struct drm_panel *panel)
347{
348 struct panel_simple *p = to_panel_simple(panel);
349
350 if (!p->enabled)
351 return 0;
352
f673c37e
AK		 353 if (p->desc->delay.disable)
354 msleep(p->desc->delay.disable);
355
280921de
TR		 356 p->enabled = false;
357
358 return 0;
359}
360
3235b0f2
DA		 361static int panel_simple_suspend(struct device *dev)
362{
363 struct panel_simple *p = dev_get_drvdata(dev);
364
365 gpiod_set_value_cansleep(p->enable_gpio, 0);
18a1488b
RN		 366
367 if (p->desc->delay.disable_to_power_off)
368 msleep(p->desc->delay.disable_to_power_off);
369
3235b0f2
DA		 370 regulator_disable(p->supply);
371 p->unprepared_time = ktime_get();
372
63358e24
DA		 373 kfree(p->edid);
374 p->edid = NULL;
375
3235b0f2
DA		 376 return 0;
377}
378
c0e1d170
AK		 379static int panel_simple_unprepare(struct drm_panel *panel)
380{
613a633e 381 struct panel_simple *p = to_panel_simple(panel);
3235b0f2 382 int ret;
613a633e 383
3235b0f2
DA		 384 /* Unpreparing when already unprepared is a no-op */
385 if (!p->prepared)
613a633e
AK		 386 return 0;
387
3235b0f2
DA		 388 pm_runtime_mark_last_busy(panel->dev);
389 ret = pm_runtime_put_autosuspend(panel->dev);
390 if (ret < 0)
391 return ret;
392 p->prepared = false;
c0e1d170 393
c0e1d170
AK		 394 return 0;
395}
396
5c4381ee 397static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p)
48834e60
DA		 398{
399 int err;
400
401 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
402 if (IS_ERR(p->hpd_gpio)) {
403 err = PTR_ERR(p->hpd_gpio);
404
5c4381ee 405 if (err != -EPROBE_DEFER)
48834e60 406 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err);
5c4381ee
DA		 407
408 return err;
48834e60
DA		 409 }
410
411 return 0;
412}
413
3235b0f2 414static int panel_simple_prepare_once(struct panel_simple *p)
280921de 415{
3235b0f2 416 struct device *dev = p->base.dev;
2ed3e951 417 unsigned int delay;
280921de 418 int err;
48834e60 419 int hpd_asserted;
6ec52621 420 unsigned long hpd_wait_us;
280921de 421
e5e30dfc
DA		 422 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
423
280921de
TR		 424 err = regulator_enable(p->supply);
425 if (err < 0) {
3235b0f2 426 dev_err(dev, "failed to enable supply: %d\n", err);
280921de
TR		 427 return err;
428 }
429
18a1488b
RN		 430 if (p->desc->delay.power_to_enable)
431 msleep(p->desc->delay.power_to_enable);
432
756b918d 433 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 434
2ed3e951
DA		 435 delay = p->desc->delay.prepare;
436 if (p->no_hpd)
437 delay += p->desc->delay.hpd_absent_delay;
438 if (delay)
439 msleep(delay);
f673c37e 440
48834e60 441 if (p->hpd_gpio) {
6ec52621
DA		 442 if (p->desc->delay.hpd_absent_delay)
443 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL;
444 else
445 hpd_wait_us = 2000000;
446
48834e60
DA		 447 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio,
448 hpd_asserted, hpd_asserted,
6ec52621 449 1000, hpd_wait_us);
48834e60
DA		 450 if (hpd_asserted < 0)
451 err = hpd_asserted;
452
453 if (err) {
87b49717 454 if (err != -ETIMEDOUT)
3235b0f2 455 dev_err(dev,
87b49717 456 "error waiting for hpd GPIO: %d\n", err);
5e7222a3 457 goto error;
48834e60
DA		 458 }
459 }
460
4beb04be 461 p->prepared_time = ktime_get();
613a633e
AK		 462
463 return 0;
5e7222a3
DA		 464
465error:
466 gpiod_set_value_cansleep(p->enable_gpio, 0);
467 regulator_disable(p->supply);
468 p->unprepared_time = ktime_get();
469
470 return err;
613a633e
AK		 471}
472
87b49717
DA		 473/*
474 * Some panels simply don't always come up and need to be power cycled to
475 * work properly. We'll allow for a handful of retries.
476 */
477#define MAX_PANEL_PREPARE_TRIES 5
478
3235b0f2 479static int panel_simple_resume(struct device *dev)
87b49717 480{
3235b0f2 481 struct panel_simple *p = dev_get_drvdata(dev);
87b49717
DA		 482 int ret;
483 int try;
484
485 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) {
3235b0f2 486 ret = panel_simple_prepare_once(p);
87b49717
DA		 487 if (ret != -ETIMEDOUT)
488 break;
489 }
490
491 if (ret == -ETIMEDOUT)
3235b0f2 492 dev_err(dev, "Prepare timeout after %d tries\n", try);
87b49717 493 else if (try)
3235b0f2 494 dev_warn(dev, "Prepare needed %d retries\n", try);
87b49717
DA		 495
496 return ret;
497}
498
3235b0f2
DA		 499static int panel_simple_prepare(struct drm_panel *panel)
500{
501 struct panel_simple *p = to_panel_simple(panel);
502 int ret;
503
504 /* Preparing when already prepared is a no-op */
505 if (p->prepared)
506 return 0;
507
508 ret = pm_runtime_get_sync(panel->dev);
509 if (ret < 0) {
510 pm_runtime_put_autosuspend(panel->dev);
511 return ret;
512 }
513
514 p->prepared = true;
515
516 return 0;
517}
518
613a633e
AK		 519static int panel_simple_enable(struct drm_panel *panel)
520{
521 struct panel_simple *p = to_panel_simple(panel);
522
523 if (p->enabled)
524 return 0;
525
f673c37e
AK		 526 if (p->desc->delay.enable)
527 msleep(p->desc->delay.enable);
528
4beb04be
DA		 529 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable);
530
280921de
TR		 531 p->enabled = true;
532
533 return 0;
534}
535
0ce8ddd8
SR		 536static int panel_simple_get_modes(struct drm_panel *panel,
537 struct drm_connector *connector)
280921de
TR		 538{
539 struct panel_simple *p = to_panel_simple(panel);
540 int num = 0;
541
542 /* probe EDID if a DDC bus is available */
543 if (p->ddc) {
31e25395
DA		 544 pm_runtime_get_sync(panel->dev);
545
63358e24
DA		 546 if (!p->edid)
547 p->edid = drm_get_edid(connector, p->ddc);
548
549 if (p->edid)
550 num += drm_add_edid_modes(connector, p->edid);
31e25395
DA		 551
552 pm_runtime_mark_last_busy(panel->dev);
553 pm_runtime_put_autosuspend(panel->dev);
280921de
TR		 554 }
555
556 /* add hard-coded panel modes */
0ce8ddd8 557 num += panel_simple_get_non_edid_modes(p, connector);
280921de 558
5759c967
DO		 559 /* set up connector's "panel orientation" property */
560 drm_connector_set_panel_orientation(connector, p->orientation);
561
280921de
TR		 562 return num;
563}
564
a5d3e625
PZ		 565static int panel_simple_get_timings(struct drm_panel *panel,
566 unsigned int num_timings,
567 struct display_timing *timings)
568{
569 struct panel_simple *p = to_panel_simple(panel);
570 unsigned int i;
571
572 if (p->desc->num_timings < num_timings)
573 num_timings = p->desc->num_timings;
574
575 if (timings)
576 for (i = 0; i < num_timings; i++)
577 timings[i] = p->desc->timings[i];
578
579 return p->desc->num_timings;
580}
581
280921de
TR		 582static const struct drm_panel_funcs panel_simple_funcs = {
583 .disable = panel_simple_disable,
c0e1d170
AK		 584 .unprepare = panel_simple_unprepare,
585 .prepare = panel_simple_prepare,
280921de
TR		 586 .enable = panel_simple_enable,
587 .get_modes = panel_simple_get_modes,
a5d3e625 588 .get_timings = panel_simple_get_timings,
280921de
TR		 589};
590
4a1d0dbc
SR		 591static struct panel_desc panel_dpi;
592
593static int panel_dpi_probe(struct device *dev,
594 struct panel_simple *panel)
595{
596 struct display_timing *timing;
597 const struct device_node *np;
598 struct panel_desc *desc;
599 unsigned int bus_flags;
600 struct videomode vm;
4a1d0dbc
SR		 601 int ret;
602
603 np = dev->of_node;
604 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
605 if (!desc)
606 return -ENOMEM;
607
608 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
609 if (!timing)
610 return -ENOMEM;
611
612 ret = of_get_display_timing(np, "panel-timing", timing);
613 if (ret < 0) {
614 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
615 np);
616 return ret;
617 }
618
619 desc->timings = timing;
620 desc->num_timings = 1;
621
622 of_property_read_u32(np, "width-mm", &desc->size.width);
623 of_property_read_u32(np, "height-mm", &desc->size.height);
624
4a1d0dbc
SR		 625 /* Extract bus_flags from display_timing */
626 bus_flags = 0;
627 vm.flags = timing->flags;
628 drm_bus_flags_from_videomode(&vm, &bus_flags);
629 desc->bus_flags = bus_flags;
630
631 /* We do not know the connector for the DT node, so guess it */
632 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
633
634 panel->desc = desc;
635
636 return 0;
637}
638
b8a2948f
SP		 639#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
640 (to_check->field.typ >= bounds->field.min && \
641 to_check->field.typ <= bounds->field.max)
e362cc6a
DA		 642static void panel_simple_parse_panel_timing_node(struct device *dev,
643 struct panel_simple *panel,
644 const struct display_timing *ot)
b8a2948f
SP		 645{
646 const struct panel_desc *desc = panel->desc;
647 struct videomode vm;
648 unsigned int i;
649
650 if (WARN_ON(desc->num_modes)) {
651 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
652 return;
653 }
654 if (WARN_ON(!desc->num_timings)) {
655 dev_err(dev, "Reject override mode: no timings specified\n");
656 return;
657 }
658
659 for (i = 0; i < panel->desc->num_timings; i++) {
660 const struct display_timing *dt = &panel->desc->timings[i];
661
662 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
663 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
664 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
665 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
666 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
667 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
668 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
669 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
670 continue;
671
672 if (ot->flags != dt->flags)
673 continue;
674
675 videomode_from_timing(ot, &vm);
676 drm_display_mode_from_videomode(&vm, &panel->override_mode);
677 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
678 DRM_MODE_TYPE_PREFERRED;
679 break;
680 }
681
682 if (WARN_ON(!panel->override_mode.type))
683 dev_err(dev, "Reject override mode: No display_timing found\n");
684}
685
cc5a3fc0
DA		 686static int panel_simple_probe(struct device *dev, const struct panel_desc *desc,
687 struct drm_dp_aux *aux)
280921de 688{
280921de 689 struct panel_simple *panel;
b8a2948f 690 struct display_timing dt;
0fe1564b 691 struct device_node *ddc;
9f069c6f 692 int connector_type;
ddb8e853 693 u32 bus_flags;
280921de
TR		 694 int err;
695
696 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
697 if (!panel)
698 return -ENOMEM;
699
700 panel->enabled = false;
4beb04be 701 panel->prepared_time = 0;
280921de 702 panel->desc = desc;
cc5a3fc0 703 panel->aux = aux;
280921de 704
2ed3e951 705 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
48834e60 706 if (!panel->no_hpd) {
5c4381ee 707 err = panel_simple_get_hpd_gpio(dev, panel);
48834e60
DA		 708 if (err)
709 return err;
710 }
2ed3e951 711
280921de
TR		 712 panel->supply = devm_regulator_get(dev, "power");
713 if (IS_ERR(panel->supply))
714 return PTR_ERR(panel->supply);
715
a61400d8
AC		 716 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
717 GPIOD_OUT_LOW);
cfdf0549
AC		 718 if (IS_ERR(panel->enable_gpio)) {
719 err = PTR_ERR(panel->enable_gpio);
b8e93807
FE		 720 if (err != -EPROBE_DEFER)
721 dev_err(dev, "failed to request GPIO: %d\n", err);
9746c619
AC		 722 return err;
723 }
280921de 724
5759c967
DO		 725 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
726 if (err) {
727 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
728 return err;
729 }
730
280921de
TR		 731 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
732 if (ddc) {
733 panel->ddc = of_find_i2c_adapter_by_node(ddc);
734 of_node_put(ddc);
735
0fe1564b
SR		 736 if (!panel->ddc)
737 return -EPROBE_DEFER;
cc5a3fc0
DA		 738 } else if (aux) {
739 panel->ddc = &aux->ddc;
280921de
TR		 740 }
741
4a1d0dbc
SR		 742 if (desc == &panel_dpi) {
743 /* Handle the generic panel-dpi binding */
744 err = panel_dpi_probe(dev, panel);
745 if (err)
746 goto free_ddc;
747 } else {
748 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
749 panel_simple_parse_panel_timing_node(dev, panel, &dt);
750 }
b8a2948f 751
9f069c6f 752 connector_type = desc->connector_type;
ddb8e853 753 /* Catch common mistakes for panels. */
9f069c6f 754 switch (connector_type) {
ddb8e853
SR		 755 case 0:
756 dev_warn(dev, "Specify missing connector_type\n");
9f069c6f 757 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853
SR		 758 break;
759 case DRM_MODE_CONNECTOR_LVDS:
c4715837
LP		 760 WARN_ON(desc->bus_flags &
761 ~(DRM_BUS_FLAG_DE_LOW |
762 DRM_BUS_FLAG_DE_HIGH |
763 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
764 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
1185c406
LP		 765 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
766 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
767 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
768 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
769 desc->bpc != 6);
770 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
771 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
772 desc->bpc != 8);
ddb8e853
SR		 773 break;
774 case DRM_MODE_CONNECTOR_eDP:
13aceea5
RN		 775 if (desc->bpc != 6 && desc->bpc != 8 && desc->bpc != 10)
776 dev_warn(dev, "Expected bpc in {6,8,10} but got: %u\n", desc->bpc);
ddb8e853
SR		 777 break;
778 case DRM_MODE_CONNECTOR_DSI:
779 if (desc->bpc != 6 && desc->bpc != 8)
780 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
781 break;
782 case DRM_MODE_CONNECTOR_DPI:
783 bus_flags = DRM_BUS_FLAG_DE_LOW |
784 DRM_BUS_FLAG_DE_HIGH |
785 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
786 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
787 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
788 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
789 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
790 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
791 if (desc->bus_flags & ~bus_flags)
792 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
793 if (!(desc->bus_flags & bus_flags))
794 dev_warn(dev, "Specify missing bus_flags\n");
795 if (desc->bus_format == 0)
796 dev_warn(dev, "Specify missing bus_format\n");
797 if (desc->bpc != 6 && desc->bpc != 8)
798 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
799 break;
800 default:
801 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
9f069c6f 802 connector_type = DRM_MODE_CONNECTOR_DPI;
ddb8e853 803 break;
1185c406 804 }
c4715837 805
18a1488b
RN		 806 if (!panel->enable_gpio && desc->delay.disable_to_power_off)
807 dev_warn(dev, "Need a delay after disabling panel GPIO, but a GPIO wasn't provided\n");
808 if (!panel->enable_gpio && desc->delay.power_to_enable)
809 dev_warn(dev, "Need a delay before enabling panel GPIO, but a GPIO wasn't provided\n");
810
3235b0f2
DA		 811 dev_set_drvdata(dev, panel);
812
813 /*
814 * We use runtime PM for prepare / unprepare since those power the panel
815 * on and off and those can be very slow operations. This is important
816 * to optimize powering the panel on briefly to read the EDID before
817 * fully enabling the panel.
818 */
819 pm_runtime_enable(dev);
820 pm_runtime_set_autosuspend_delay(dev, 1000);
821 pm_runtime_use_autosuspend(dev);
822
9f069c6f 823 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
280921de 824
0fe1564b
SR		 825 err = drm_panel_of_backlight(&panel->base);
826 if (err)
70e12560 827 goto disable_pm_runtime;
0fe1564b 828
bfd45140 829 if (!panel->base.backlight && panel->aux) {
5ead9b5b 830 pm_runtime_get_sync(dev);
bfd45140 831 err = drm_panel_dp_aux_backlight(&panel->base, panel->aux);
5ead9b5b
DA		 832 pm_runtime_mark_last_busy(dev);
833 pm_runtime_put_autosuspend(dev);
bfd45140
RN		 834 if (err)
835 goto disable_pm_runtime;
836 }
837
c3ee8c65 838 drm_panel_add(&panel->base);
280921de 839
280921de
TR		 840 return 0;
841
70e12560 842disable_pm_runtime:
a596fcd9 843 pm_runtime_dont_use_autosuspend(dev);
70e12560 844 pm_runtime_disable(dev);
280921de 845free_ddc:
cc5a3fc0 846 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))
280921de 847 put_device(&panel->ddc->dev);
280921de
TR		 848
849 return err;
850}
851
852static int panel_simple_remove(struct device *dev)
853{
854 struct panel_simple *panel = dev_get_drvdata(dev);
855
280921de 856 drm_panel_remove(&panel->base);
0fe1564b
SR		 857 drm_panel_disable(&panel->base);
858 drm_panel_unprepare(&panel->base);
280921de 859
a596fcd9 860 pm_runtime_dont_use_autosuspend(dev);
70e12560 861 pm_runtime_disable(dev);
cc5a3fc0 862 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc))
280921de
TR		 863 put_device(&panel->ddc->dev);
864
280921de
TR		 865 return 0;
866}
867
d02fd93e
TR		 868static void panel_simple_shutdown(struct device *dev)
869{
870 struct panel_simple *panel = dev_get_drvdata(dev);
871
0fe1564b
SR		 872 drm_panel_disable(&panel->base);
873 drm_panel_unprepare(&panel->base);
d02fd93e
TR		 874}
875
bca684e6
JT		 876static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
877 .clock = 71100,
878 .hdisplay = 1280,
879 .hsync_start = 1280 + 40,
880 .hsync_end = 1280 + 40 + 80,
881 .htotal = 1280 + 40 + 80 + 40,
882 .vdisplay = 800,
883 .vsync_start = 800 + 3,
884 .vsync_end = 800 + 3 + 10,
885 .vtotal = 800 + 3 + 10 + 10,
886 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
887};
888
889static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
890 .modes = &ampire_am_1280800n3tzqw_t00h_mode,
891 .num_modes = 1,
892 .bpc = 6,
893 .size = {
894 .width = 217,
895 .height = 136,
896 },
897 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
899 .connector_type = DRM_MODE_CONNECTOR_LVDS,
900};
901
966fea78
YF		 902static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
903 .clock = 9000,
904 .hdisplay = 480,
905 .hsync_start = 480 + 2,
906 .hsync_end = 480 + 2 + 41,
907 .htotal = 480 + 2 + 41 + 2,
908 .vdisplay = 272,
909 .vsync_start = 272 + 2,
910 .vsync_end = 272 + 2 + 10,
911 .vtotal = 272 + 2 + 10 + 2,
966fea78
YF		 912 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
913};
914
915static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
916 .modes = &ampire_am_480272h3tmqw_t01h_mode,
917 .num_modes = 1,
918 .bpc = 8,
919 .size = {
920 .width = 105,
921 .height = 67,
922 },
923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
924};
925
1c550fa1
PZ		 926static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
927 .clock = 33333,
928 .hdisplay = 800,
929 .hsync_start = 800 + 0,
930 .hsync_end = 800 + 0 + 255,
931 .htotal = 800 + 0 + 255 + 0,
932 .vdisplay = 480,
933 .vsync_start = 480 + 2,
934 .vsync_end = 480 + 2 + 45,
935 .vtotal = 480 + 2 + 45 + 0,
1c550fa1
PZ		 936 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
937};
938
939static const struct panel_desc ampire_am800480r3tmqwa1h = {
940 .modes = &ampire_am800480r3tmqwa1h_mode,
941 .num_modes = 1,
942 .bpc = 6,
943 .size = {
944 .width = 152,
945 .height = 91,
946 },
947 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
948};
949
c479450f
SS		 950static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
951 .pixelclock = { 26400000, 33300000, 46800000 },
952 .hactive = { 800, 800, 800 },
953 .hfront_porch = { 16, 210, 354 },
954 .hback_porch = { 45, 36, 6 },
955 .hsync_len = { 1, 10, 40 },
956 .vactive = { 480, 480, 480 },
957 .vfront_porch = { 7, 22, 147 },
958 .vback_porch = { 22, 13, 3 },
959 .vsync_len = { 1, 10, 20 },
960 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
961 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
962};
963
964static const struct panel_desc armadeus_st0700_adapt = {
965 .timings = &santek_st0700i5y_rbslw_f_timing,
966 .num_timings = 1,
967 .bpc = 6,
968 .size = {
969 .width = 154,
970 .height = 86,
971 },
972 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 973 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
c479450f
SS		 974};
975
280921de
TR		 976static const struct drm_display_mode auo_b101aw03_mode = {
977 .clock = 51450,
978 .hdisplay = 1024,
979 .hsync_start = 1024 + 156,
980 .hsync_end = 1024 + 156 + 8,
981 .htotal = 1024 + 156 + 8 + 156,
982 .vdisplay = 600,
983 .vsync_start = 600 + 16,
984 .vsync_end = 600 + 16 + 6,
985 .vtotal = 600 + 16 + 6 + 16,
280921de
TR		 986};
987
988static const struct panel_desc auo_b101aw03 = {
989 .modes = &auo_b101aw03_mode,
990 .num_modes = 1,
0208d511 991 .bpc = 6,
280921de
TR		 992 .size = {
993 .width = 223,
994 .height = 125,
995 },
85560829 996 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 997 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 998 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 999};
1000
374bf825
DA		 1001static const struct display_timing auo_b101ean01_timing = {
1002 .pixelclock = { 65300000, 72500000, 75000000 },
1003 .hactive = { 1280, 1280, 1280 },
1004 .hfront_porch = { 18, 119, 119 },
1005 .hback_porch = { 21, 21, 21 },
1006 .hsync_len = { 32, 32, 32 },
1007 .vactive = { 800, 800, 800 },
1008 .vfront_porch = { 4, 4, 4 },
1009 .vback_porch = { 8, 8, 8 },
1010 .vsync_len = { 18, 20, 20 },
a531bc3d
HL		 1011};
1012
1013static const struct panel_desc auo_b101ean01 = {
374bf825
DA		 1014 .timings = &auo_b101ean01_timing,
1015 .num_timings = 1,
a531bc3d
HL		 1016 .bpc = 6,
1017 .size = {
1018 .width = 217,
1019 .height = 136,
1020 },
1021};
1022
dac746e0
RC		 1023static const struct drm_display_mode auo_b101xtn01_mode = {
1024 .clock = 72000,
1025 .hdisplay = 1366,
1026 .hsync_start = 1366 + 20,
1027 .hsync_end = 1366 + 20 + 70,
1028 .htotal = 1366 + 20 + 70,
1029 .vdisplay = 768,
1030 .vsync_start = 768 + 14,
1031 .vsync_end = 768 + 14 + 42,
1032 .vtotal = 768 + 14 + 42,
dac746e0
RC		 1033 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1034};
1035
1036static const struct panel_desc auo_b101xtn01 = {
1037 .modes = &auo_b101xtn01_mode,
1038 .num_modes = 1,
1039 .bpc = 6,
1040 .size = {
1041 .width = 223,
1042 .height = 125,
1043 },
1044};
1045
da458286
RC		 1046static const struct drm_display_mode auo_b116xak01_mode = {
1047 .clock = 69300,
1048 .hdisplay = 1366,
1049 .hsync_start = 1366 + 48,
1050 .hsync_end = 1366 + 48 + 32,
1051 .htotal = 1366 + 48 + 32 + 10,
1052 .vdisplay = 768,
1053 .vsync_start = 768 + 4,
1054 .vsync_end = 768 + 4 + 6,
1055 .vtotal = 768 + 4 + 6 + 15,
da458286
RC		 1056 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1057};
1058
1059static const struct panel_desc auo_b116xak01 = {
1060 .modes = &auo_b116xak01_mode,
1061 .num_modes = 1,
1062 .bpc = 6,
1063 .size = {
1064 .width = 256,
1065 .height = 144,
1066 },
1067 .delay = {
1068 .hpd_absent_delay = 200,
1069 },
1070 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1071 .connector_type = DRM_MODE_CONNECTOR_eDP,
1072};
1073
e35e305e
AK		 1074static const struct drm_display_mode auo_b116xw03_mode = {
1075 .clock = 70589,
1076 .hdisplay = 1366,
1077 .hsync_start = 1366 + 40,
1078 .hsync_end = 1366 + 40 + 40,
1079 .htotal = 1366 + 40 + 40 + 32,
1080 .vdisplay = 768,
1081 .vsync_start = 768 + 10,
1082 .vsync_end = 768 + 10 + 12,
1083 .vtotal = 768 + 10 + 12 + 6,
88d3457c 1084 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
e35e305e
AK		 1085};
1086
1087static const struct panel_desc auo_b116xw03 = {
1088 .modes = &auo_b116xw03_mode,
1089 .num_modes = 1,
1090 .bpc = 6,
1091 .size = {
1092 .width = 256,
1093 .height = 144,
1094 },
88d3457c
JS		 1095 .delay = {
1096 .enable = 400,
1097 },
1098 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
1099 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1100 .connector_type = DRM_MODE_CONNECTOR_eDP,
e35e305e
AK		 1101};
1102
a333f7ad
SM		 1103static const struct drm_display_mode auo_b133xtn01_mode = {
1104 .clock = 69500,
1105 .hdisplay = 1366,
1106 .hsync_start = 1366 + 48,
1107 .hsync_end = 1366 + 48 + 32,
1108 .htotal = 1366 + 48 + 32 + 20,
1109 .vdisplay = 768,
1110 .vsync_start = 768 + 3,
1111 .vsync_end = 768 + 3 + 6,
1112 .vtotal = 768 + 3 + 6 + 13,
a333f7ad
SM		 1113};
1114
1115static const struct panel_desc auo_b133xtn01 = {
1116 .modes = &auo_b133xtn01_mode,
1117 .num_modes = 1,
0208d511 1118 .bpc = 6,
a333f7ad
SM		 1119 .size = {
1120 .width = 293,
1121 .height = 165,
1122 },
1123};
1124
93ea7aa8
BA		 1125static const struct drm_display_mode auo_b133han05_mode = {
1126 .clock = 142600,
1127 .hdisplay = 1920,
1128 .hsync_start = 1920 + 58,
1129 .hsync_end = 1920 + 58 + 42,
1130 .htotal = 1920 + 58 + 42 + 60,
1131 .vdisplay = 1080,
1132 .vsync_start = 1080 + 3,
1133 .vsync_end = 1080 + 3 + 5,
1134 .vtotal = 1080 + 3 + 5 + 54,
1135};
1136
1137static const struct panel_desc auo_b133han05 = {
1138 .modes = &auo_b133han05_mode,
1139 .num_modes = 1,
1140 .bpc = 8,
1141 .size = {
1142 .width = 293,
1143 .height = 165,
1144 },
1145 .delay = {
1146 .prepare = 100,
1147 .enable = 20,
1148 .unprepare = 50,
1149 },
1150 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1151 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1152 .connector_type = DRM_MODE_CONNECTOR_eDP,
1153};
1154
3e51d609
AK		 1155static const struct drm_display_mode auo_b133htn01_mode = {
1156 .clock = 150660,
1157 .hdisplay = 1920,
1158 .hsync_start = 1920 + 172,
1159 .hsync_end = 1920 + 172 + 80,
1160 .htotal = 1920 + 172 + 80 + 60,
1161 .vdisplay = 1080,
1162 .vsync_start = 1080 + 25,
1163 .vsync_end = 1080 + 25 + 10,
1164 .vtotal = 1080 + 25 + 10 + 10,
3e51d609
AK		 1165};
1166
1167static const struct panel_desc auo_b133htn01 = {
1168 .modes = &auo_b133htn01_mode,
1169 .num_modes = 1,
d7a839cd 1170 .bpc = 6,
3e51d609
AK		 1171 .size = {
1172 .width = 293,
1173 .height = 165,
1174 },
1175 .delay = {
1176 .prepare = 105,
1177 .enable = 20,
1178 .unprepare = 50,
1179 },
1180};
1181
93ea7aa8
BA		 1182static const struct drm_display_mode auo_b140han06_mode = {
1183 .clock = 141000,
1184 .hdisplay = 1920,
1185 .hsync_start = 1920 + 16,
1186 .hsync_end = 1920 + 16 + 16,
1187 .htotal = 1920 + 16 + 16 + 152,
1188 .vdisplay = 1080,
1189 .vsync_start = 1080 + 3,
1190 .vsync_end = 1080 + 3 + 14,
1191 .vtotal = 1080 + 3 + 14 + 19,
1192};
1193
1194static const struct panel_desc auo_b140han06 = {
1195 .modes = &auo_b140han06_mode,
1196 .num_modes = 1,
1197 .bpc = 8,
1198 .size = {
1199 .width = 309,
1200 .height = 174,
1201 },
1202 .delay = {
1203 .prepare = 100,
1204 .enable = 20,
1205 .unprepare = 50,
1206 },
1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1208 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1209 .connector_type = DRM_MODE_CONNECTOR_eDP,
1210};
1211
bccfaffb
LM		 1212static const struct display_timing auo_g070vvn01_timings = {
1213 .pixelclock = { 33300000, 34209000, 45000000 },
1214 .hactive = { 800, 800, 800 },
1215 .hfront_porch = { 20, 40, 200 },
1216 .hback_porch = { 87, 40, 1 },
1217 .hsync_len = { 1, 48, 87 },
1218 .vactive = { 480, 480, 480 },
1219 .vfront_porch = { 5, 13, 200 },
1220 .vback_porch = { 31, 31, 29 },
1221 .vsync_len = { 1, 1, 3 },
1222};
1223
1224static const struct panel_desc auo_g070vvn01 = {
1225 .timings = &auo_g070vvn01_timings,
1226 .num_timings = 1,
1227 .bpc = 8,
1228 .size = {
1229 .width = 152,
1230 .height = 91,
1231 },
1232 .delay = {
1233 .prepare = 200,
1234 .enable = 50,
1235 .disable = 50,
1236 .unprepare = 1000,
1237 },
1238};
1239
4fb86404
AG		 1240static const struct drm_display_mode auo_g101evn010_mode = {
1241 .clock = 68930,
1242 .hdisplay = 1280,
1243 .hsync_start = 1280 + 82,
1244 .hsync_end = 1280 + 82 + 2,
1245 .htotal = 1280 + 82 + 2 + 84,
1246 .vdisplay = 800,
1247 .vsync_start = 800 + 8,
1248 .vsync_end = 800 + 8 + 2,
1249 .vtotal = 800 + 8 + 2 + 6,
4fb86404
AG		 1250};
1251
1252static const struct panel_desc auo_g101evn010 = {
1253 .modes = &auo_g101evn010_mode,
1254 .num_modes = 1,
1255 .bpc = 6,
1256 .size = {
1257 .width = 216,
1258 .height = 135,
1259 },
27a46fb7
TV		 1260 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1261 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4fb86404
AG		 1262};
1263
4451c287
CF		 1264static const struct drm_display_mode auo_g104sn02_mode = {
1265 .clock = 40000,
1266 .hdisplay = 800,
1267 .hsync_start = 800 + 40,
1268 .hsync_end = 800 + 40 + 216,
1269 .htotal = 800 + 40 + 216 + 128,
1270 .vdisplay = 600,
1271 .vsync_start = 600 + 10,
1272 .vsync_end = 600 + 10 + 35,
1273 .vtotal = 600 + 10 + 35 + 2,
4451c287
CF		 1274};
1275
1276static const struct panel_desc auo_g104sn02 = {
1277 .modes = &auo_g104sn02_mode,
1278 .num_modes = 1,
1279 .bpc = 8,
1280 .size = {
1281 .width = 211,
1282 .height = 158,
1283 },
a3050f23
SR		 1284 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1285 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4451c287
CF		 1286};
1287
03e909ac
SR		 1288static const struct drm_display_mode auo_g121ean01_mode = {
1289 .clock = 66700,
1290 .hdisplay = 1280,
1291 .hsync_start = 1280 + 58,
1292 .hsync_end = 1280 + 58 + 8,
1293 .htotal = 1280 + 58 + 8 + 70,
1294 .vdisplay = 800,
1295 .vsync_start = 800 + 6,
1296 .vsync_end = 800 + 6 + 4,
1297 .vtotal = 800 + 6 + 4 + 10,
03e909ac
SR		 1298};
1299
1300static const struct panel_desc auo_g121ean01 = {
1301 .modes = &auo_g121ean01_mode,
1302 .num_modes = 1,
1303 .bpc = 8,
1304 .size = {
1305 .width = 261,
1306 .height = 163,
1307 },
1308 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1309 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1310};
1311
697035c6
LS		 1312static const struct display_timing auo_g133han01_timings = {
1313 .pixelclock = { 134000000, 141200000, 149000000 },
1314 .hactive = { 1920, 1920, 1920 },
1315 .hfront_porch = { 39, 58, 77 },
1316 .hback_porch = { 59, 88, 117 },
1317 .hsync_len = { 28, 42, 56 },
1318 .vactive = { 1080, 1080, 1080 },
1319 .vfront_porch = { 3, 8, 11 },
1320 .vback_porch = { 5, 14, 19 },
1321 .vsync_len = { 4, 14, 19 },
1322};
1323
1324static const struct panel_desc auo_g133han01 = {
1325 .timings = &auo_g133han01_timings,
1326 .num_timings = 1,
1327 .bpc = 8,
1328 .size = {
1329 .width = 293,
1330 .height = 165,
1331 },
1332 .delay = {
1333 .prepare = 200,
1334 .enable = 50,
1335 .disable = 50,
1336 .unprepare = 1000,
1337 },
1338 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 1339 .connector_type = DRM_MODE_CONNECTOR_LVDS,
697035c6
LS		 1340};
1341
d9ccd1f2
SR		 1342static const struct drm_display_mode auo_g156xtn01_mode = {
1343 .clock = 76000,
1344 .hdisplay = 1366,
1345 .hsync_start = 1366 + 33,
1346 .hsync_end = 1366 + 33 + 67,
1347 .htotal = 1560,
1348 .vdisplay = 768,
1349 .vsync_start = 768 + 4,
1350 .vsync_end = 768 + 4 + 4,
1351 .vtotal = 806,
d9ccd1f2
SR		 1352};
1353
1354static const struct panel_desc auo_g156xtn01 = {
1355 .modes = &auo_g156xtn01_mode,
1356 .num_modes = 1,
1357 .bpc = 8,
1358 .size = {
1359 .width = 344,
1360 .height = 194,
1361 },
1362 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1363 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1364};
1365
8c31f603
LS		 1366static const struct display_timing auo_g185han01_timings = {
1367 .pixelclock = { 120000000, 144000000, 175000000 },
1368 .hactive = { 1920, 1920, 1920 },
f8c6bfc6
LS		 1369 .hfront_porch = { 36, 120, 148 },
1370 .hback_porch = { 24, 88, 108 },
1371 .hsync_len = { 20, 48, 64 },
8c31f603
LS		 1372 .vactive = { 1080, 1080, 1080 },
1373 .vfront_porch = { 6, 10, 40 },
1374 .vback_porch = { 2, 5, 20 },
1375 .vsync_len = { 2, 5, 20 },
1376};
1377
1378static const struct panel_desc auo_g185han01 = {
1379 .timings = &auo_g185han01_timings,
1380 .num_timings = 1,
1381 .bpc = 8,
1382 .size = {
1383 .width = 409,
1384 .height = 230,
1385 },
1386 .delay = {
1387 .prepare = 50,
1388 .enable = 200,
1389 .disable = 110,
1390 .unprepare = 1000,
1391 },
1392 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1393 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8c31f603
LS		 1394};
1395
2f7b832f
SR		 1396static const struct display_timing auo_g190ean01_timings = {
1397 .pixelclock = { 90000000, 108000000, 135000000 },
1398 .hactive = { 1280, 1280, 1280 },
1399 .hfront_porch = { 126, 184, 1266 },
1400 .hback_porch = { 84, 122, 844 },
1401 .hsync_len = { 70, 102, 704 },
1402 .vactive = { 1024, 1024, 1024 },
1403 .vfront_porch = { 4, 26, 76 },
1404 .vback_porch = { 2, 8, 25 },
1405 .vsync_len = { 2, 8, 25 },
1406};
1407
1408static const struct panel_desc auo_g190ean01 = {
1409 .timings = &auo_g190ean01_timings,
1410 .num_timings = 1,
1411 .bpc = 8,
1412 .size = {
1413 .width = 376,
1414 .height = 301,
1415 },
1416 .delay = {
1417 .prepare = 50,
1418 .enable = 200,
1419 .disable = 110,
1420 .unprepare = 1000,
1421 },
1422 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1423 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1424};
1425
70c0d5b7
LS		 1426static const struct display_timing auo_p320hvn03_timings = {
1427 .pixelclock = { 106000000, 148500000, 164000000 },
1428 .hactive = { 1920, 1920, 1920 },
1429 .hfront_porch = { 25, 50, 130 },
1430 .hback_porch = { 25, 50, 130 },
1431 .hsync_len = { 20, 40, 105 },
1432 .vactive = { 1080, 1080, 1080 },
1433 .vfront_porch = { 8, 17, 150 },
1434 .vback_porch = { 8, 17, 150 },
1435 .vsync_len = { 4, 11, 100 },
1436};
1437
1438static const struct panel_desc auo_p320hvn03 = {
1439 .timings = &auo_p320hvn03_timings,
1440 .num_timings = 1,
1441 .bpc = 8,
1442 .size = {
1443 .width = 698,
1444 .height = 393,
1445 },
1446 .delay = {
1447 .prepare = 1,
1448 .enable = 450,
1449 .unprepare = 500,
1450 },
2554f154 1451 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 1452 .connector_type = DRM_MODE_CONNECTOR_LVDS,
70c0d5b7
LS		 1453};
1454
7ee933a1
HS		 1455static const struct drm_display_mode auo_t215hvn01_mode = {
1456 .clock = 148800,
1457 .hdisplay = 1920,
1458 .hsync_start = 1920 + 88,
1459 .hsync_end = 1920 + 88 + 44,
1460 .htotal = 1920 + 88 + 44 + 148,
1461 .vdisplay = 1080,
1462 .vsync_start = 1080 + 4,
1463 .vsync_end = 1080 + 4 + 5,
1464 .vtotal = 1080 + 4 + 5 + 36,
7ee933a1
HS		 1465};
1466
1467static const struct panel_desc auo_t215hvn01 = {
1468 .modes = &auo_t215hvn01_mode,
1469 .num_modes = 1,
1470 .bpc = 8,
1471 .size = {
1472 .width = 430,
1473 .height = 270,
1474 },
1475 .delay = {
1476 .disable = 5,
1477 .unprepare = 1000,
1478 }
1479};
1480
d47df633
PZ		 1481static const struct drm_display_mode avic_tm070ddh03_mode = {
1482 .clock = 51200,
1483 .hdisplay = 1024,
1484 .hsync_start = 1024 + 160,
1485 .hsync_end = 1024 + 160 + 4,
1486 .htotal = 1024 + 160 + 4 + 156,
1487 .vdisplay = 600,
1488 .vsync_start = 600 + 17,
1489 .vsync_end = 600 + 17 + 1,
1490 .vtotal = 600 + 17 + 1 + 17,
d47df633
PZ		 1491};
1492
1493static const struct panel_desc avic_tm070ddh03 = {
1494 .modes = &avic_tm070ddh03_mode,
1495 .num_modes = 1,
1496 .bpc = 8,
1497 .size = {
1498 .width = 154,
1499 .height = 90,
1500 },
1501 .delay = {
1502 .prepare = 20,
1503 .enable = 200,
1504 .disable = 200,
1505 },
1506};
1507
7ad8b41c
CYT		 1508static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1509 .clock = 30000,
1510 .hdisplay = 800,
1511 .hsync_start = 800 + 40,
1512 .hsync_end = 800 + 40 + 48,
1513 .htotal = 800 + 40 + 48 + 40,
1514 .vdisplay = 480,
1515 .vsync_start = 480 + 13,
1516 .vsync_end = 480 + 13 + 3,
1517 .vtotal = 480 + 13 + 3 + 29,
1518};
1519
1520static const struct panel_desc bananapi_s070wv20_ct16 = {
1521 .modes = &bananapi_s070wv20_ct16_mode,
1522 .num_modes = 1,
1523 .bpc = 6,
1524 .size = {
1525 .width = 154,
1526 .height = 86,
1527 },
1528};
1529
ae8cf41b 1530static const struct drm_display_mode boe_hv070wsa_mode = {
e077e2f5 1531 .clock = 42105,
ae8cf41b 1532 .hdisplay = 1024,
e077e2f5
AH		 1533 .hsync_start = 1024 + 30,
1534 .hsync_end = 1024 + 30 + 30,
1535 .htotal = 1024 + 30 + 30 + 30,
ae8cf41b 1536 .vdisplay = 600,
e077e2f5
AH		 1537 .vsync_start = 600 + 10,
1538 .vsync_end = 600 + 10 + 10,
1539 .vtotal = 600 + 10 + 10 + 10,
ae8cf41b
AH		 1540};
1541
1542static const struct panel_desc boe_hv070wsa = {
1543 .modes = &boe_hv070wsa_mode,
1544 .num_modes = 1,
2a5c2ff5 1545 .bpc = 8,
ae8cf41b
AH		 1546 .size = {
1547 .width = 154,
1548 .height = 90,
1549 },
2a5c2ff5
SR		 1550 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1551 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1552 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ae8cf41b
AH		 1553};
1554
cac1a411
CW		 1555static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1556 {
1557 .clock = 71900,
1558 .hdisplay = 1280,
1559 .hsync_start = 1280 + 48,
1560 .hsync_end = 1280 + 48 + 32,
1561 .htotal = 1280 + 48 + 32 + 80,
1562 .vdisplay = 800,
1563 .vsync_start = 800 + 3,
1564 .vsync_end = 800 + 3 + 5,
1565 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1566 },
1567 {
1568 .clock = 57500,
1569 .hdisplay = 1280,
1570 .hsync_start = 1280 + 48,
1571 .hsync_end = 1280 + 48 + 32,
1572 .htotal = 1280 + 48 + 32 + 80,
1573 .vdisplay = 800,
1574 .vsync_start = 800 + 3,
1575 .vsync_end = 800 + 3 + 5,
1576 .vtotal = 800 + 3 + 5 + 24,
cac1a411
CW		 1577 },
1578};
1579
1580static const struct panel_desc boe_nv101wxmn51 = {
1581 .modes = boe_nv101wxmn51_modes,
1582 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1583 .bpc = 8,
1584 .size = {
1585 .width = 217,
1586 .height = 136,
1587 },
1588 .delay = {
1589 .prepare = 210,
1590 .enable = 50,
1591 .unprepare = 160,
1592 },
1593};
1594
a96ee0f6
DA		 1595static const struct drm_display_mode boe_nv110wtm_n61_modes[] = {
1596 {
1597 .clock = 207800,
1598 .hdisplay = 2160,
1599 .hsync_start = 2160 + 48,
1600 .hsync_end = 2160 + 48 + 32,
1601 .htotal = 2160 + 48 + 32 + 100,
1602 .vdisplay = 1440,
1603 .vsync_start = 1440 + 3,
1604 .vsync_end = 1440 + 3 + 6,
1605 .vtotal = 1440 + 3 + 6 + 31,
9dbf1a45 1606 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
a96ee0f6
DA		 1607 },
1608 {
1609 .clock = 138500,
1610 .hdisplay = 2160,
1611 .hsync_start = 2160 + 48,
1612 .hsync_end = 2160 + 48 + 32,
1613 .htotal = 2160 + 48 + 32 + 100,
1614 .vdisplay = 1440,
1615 .vsync_start = 1440 + 3,
1616 .vsync_end = 1440 + 3 + 6,
1617 .vtotal = 1440 + 3 + 6 + 31,
9dbf1a45 1618 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
a96ee0f6
DA		 1619 },
1620};
1621
1622static const struct panel_desc boe_nv110wtm_n61 = {
1623 .modes = boe_nv110wtm_n61_modes,
1624 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes),
1625 .bpc = 8,
1626 .size = {
1627 .width = 233,
1628 .height = 155,
1629 },
1630 .delay = {
1631 .hpd_absent_delay = 200,
1632 .prepare_to_enable = 80,
67cc24ac 1633 .enable = 50,
a96ee0f6
DA		 1634 .unprepare = 500,
1635 },
1636 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1637 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1638 .connector_type = DRM_MODE_CONNECTOR_eDP,
1639};
1640
cfe40d02 1641/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1642static const struct drm_display_mode boe_nv133fhm_n61_modes = {
1643 .clock = 147840,
1644 .hdisplay = 1920,
1645 .hsync_start = 1920 + 48,
1646 .hsync_end = 1920 + 48 + 32,
1647 .htotal = 1920 + 48 + 32 + 200,
1648 .vdisplay = 1080,
1649 .vsync_start = 1080 + 3,
1650 .vsync_end = 1080 + 3 + 6,
1651 .vtotal = 1080 + 3 + 6 + 31,
ab6fd5d4 1652 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
b0c664cc
BA		 1653};
1654
cfe40d02 1655/* Also used for boe_nv133fhm_n62 */
b0c664cc
BA		 1656static const struct panel_desc boe_nv133fhm_n61 = {
1657 .modes = &boe_nv133fhm_n61_modes,
1658 .num_modes = 1,
9694d9c3 1659 .bpc = 6,
b0c664cc 1660 .size = {
9694d9c3
DA		 1661 .width = 294,
1662 .height = 165,
b0c664cc
BA		 1663 },
1664 .delay = {
667d73d7
DA		 1665 /*
1666 * When power is first given to the panel there's a short
1667 * spike on the HPD line. It was explained that this spike
1668 * was until the TCON data download was complete. On
1669 * one system this was measured at 8 ms. We'll put 15 ms
1670 * in the prepare delay just to be safe and take it away
1671 * from the hpd_absent_delay (which would otherwise be 200 ms)
1672 * to handle this. That means:
1673 * - If HPD isn't hooked up you still have 200 ms delay.
1674 * - If HPD is hooked up we won't try to look at it for the
1675 * first 15 ms.
1676 */
1677 .prepare = 15,
1678 .hpd_absent_delay = 185,
1679
b0c664cc
BA		 1680 .unprepare = 500,
1681 },
1682 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1683 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
1684 .connector_type = DRM_MODE_CONNECTOR_eDP,
1685};
1686
a5119818
TS		 1687static const struct drm_display_mode boe_nv140fhmn49_modes[] = {
1688 {
1689 .clock = 148500,
1690 .hdisplay = 1920,
1691 .hsync_start = 1920 + 48,
1692 .hsync_end = 1920 + 48 + 32,
1693 .htotal = 2200,
1694 .vdisplay = 1080,
1695 .vsync_start = 1080 + 3,
1696 .vsync_end = 1080 + 3 + 5,
1697 .vtotal = 1125,
a5119818
TS		 1698 },
1699};
1700
1701static const struct panel_desc boe_nv140fhmn49 = {
1702 .modes = boe_nv140fhmn49_modes,
1703 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes),
1704 .bpc = 6,
1705 .size = {
1706 .width = 309,
1707 .height = 174,
1708 },
1709 .delay = {
1710 .prepare = 210,
1711 .enable = 50,
1712 .unprepare = 160,
1713 },
1714 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1715 .connector_type = DRM_MODE_CONNECTOR_eDP,
1716};
1717
e58edce6
GB		 1718static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1719 .clock = 9000,
1720 .hdisplay = 480,
1721 .hsync_start = 480 + 5,
1722 .hsync_end = 480 + 5 + 5,
1723 .htotal = 480 + 5 + 5 + 40,
1724 .vdisplay = 272,
1725 .vsync_start = 272 + 8,
1726 .vsync_end = 272 + 8 + 8,
1727 .vtotal = 272 + 8 + 8 + 8,
e58edce6
GB		 1728 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1729};
1730
1731static const struct panel_desc cdtech_s043wq26h_ct7 = {
1732 .modes = &cdtech_s043wq26h_ct7_mode,
1733 .num_modes = 1,
1734 .bpc = 8,
1735 .size = {
1736 .width = 95,
1737 .height = 54,
1738 },
88bc4178 1739 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
e58edce6
GB		 1740};
1741
0e3b67f6
MK		 1742/* S070PWS19HP-FC21 2017/04/22 */
1743static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1744 .clock = 51200,
1745 .hdisplay = 1024,
1746 .hsync_start = 1024 + 160,
1747 .hsync_end = 1024 + 160 + 20,
1748 .htotal = 1024 + 160 + 20 + 140,
1749 .vdisplay = 600,
1750 .vsync_start = 600 + 12,
1751 .vsync_end = 600 + 12 + 3,
1752 .vtotal = 600 + 12 + 3 + 20,
1753 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1754};
1755
1756static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1757 .modes = &cdtech_s070pws19hp_fc21_mode,
1758 .num_modes = 1,
1759 .bpc = 6,
1760 .size = {
1761 .width = 154,
1762 .height = 86,
1763 },
1764 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1766 .connector_type = DRM_MODE_CONNECTOR_DPI,
1767};
1768
1769/* S070SWV29HG-DC44 2017/09/21 */
1770static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1771 .clock = 33300,
1772 .hdisplay = 800,
1773 .hsync_start = 800 + 210,
1774 .hsync_end = 800 + 210 + 2,
1775 .htotal = 800 + 210 + 2 + 44,
1776 .vdisplay = 480,
1777 .vsync_start = 480 + 22,
1778 .vsync_end = 480 + 22 + 2,
1779 .vtotal = 480 + 22 + 2 + 21,
1780 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1781};
1782
1783static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1784 .modes = &cdtech_s070swv29hg_dc44_mode,
1785 .num_modes = 1,
1786 .bpc = 6,
1787 .size = {
1788 .width = 154,
1789 .height = 86,
1790 },
1791 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
f5436f77 1792 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
0e3b67f6
MK		 1793 .connector_type = DRM_MODE_CONNECTOR_DPI,
1794};
1795
982f944e
GB		 1796static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1797 .clock = 35000,
1798 .hdisplay = 800,
1799 .hsync_start = 800 + 40,
1800 .hsync_end = 800 + 40 + 40,
1801 .htotal = 800 + 40 + 40 + 48,
1802 .vdisplay = 480,
1803 .vsync_start = 480 + 29,
1804 .vsync_end = 480 + 29 + 13,
1805 .vtotal = 480 + 29 + 13 + 3,
982f944e
GB		 1806 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1807};
1808
1809static const struct panel_desc cdtech_s070wv95_ct16 = {
1810 .modes = &cdtech_s070wv95_ct16_mode,
1811 .num_modes = 1,
1812 .bpc = 8,
1813 .size = {
1814 .width = 154,
1815 .height = 85,
1816 },
1817};
1818
07c913c4
MV		 1819static const struct display_timing chefree_ch101olhlwh_002_timing = {
1820 .pixelclock = { 68900000, 71100000, 73400000 },
1821 .hactive = { 1280, 1280, 1280 },
1822 .hfront_porch = { 65, 80, 95 },
1823 .hback_porch = { 64, 79, 94 },
1824 .hsync_len = { 1, 1, 1 },
1825 .vactive = { 800, 800, 800 },
1826 .vfront_porch = { 7, 11, 14 },
1827 .vback_porch = { 7, 11, 14 },
1828 .vsync_len = { 1, 1, 1 },
1829 .flags = DISPLAY_FLAGS_DE_HIGH,
1830};
1831
1832static const struct panel_desc chefree_ch101olhlwh_002 = {
1833 .timings = &chefree_ch101olhlwh_002_timing,
1834 .num_timings = 1,
1835 .bpc = 8,
1836 .size = {
1837 .width = 217,
1838 .height = 135,
1839 },
1840 .delay = {
1841 .enable = 200,
1842 .disable = 200,
1843 },
1844 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1845 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1846 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1847};
1848
2cb35c80
RL		 1849static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1850 .clock = 66770,
1851 .hdisplay = 800,
1852 .hsync_start = 800 + 49,
1853 .hsync_end = 800 + 49 + 33,
1854 .htotal = 800 + 49 + 33 + 17,
1855 .vdisplay = 1280,
1856 .vsync_start = 1280 + 1,
1857 .vsync_end = 1280 + 1 + 7,
1858 .vtotal = 1280 + 1 + 7 + 15,
2cb35c80
RL		 1859 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1860};
1861
1862static const struct panel_desc chunghwa_claa070wp03xg = {
1863 .modes = &chunghwa_claa070wp03xg_mode,
1864 .num_modes = 1,
1865 .bpc = 6,
1866 .size = {
1867 .width = 94,
1868 .height = 150,
1869 },
85560829 1870 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1871 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1872 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2cb35c80
RL		 1873};
1874
4c930757
SW		 1875static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1876 .clock = 72070,
1877 .hdisplay = 1366,
1878 .hsync_start = 1366 + 58,
1879 .hsync_end = 1366 + 58 + 58,
1880 .htotal = 1366 + 58 + 58 + 58,
1881 .vdisplay = 768,
1882 .vsync_start = 768 + 4,
1883 .vsync_end = 768 + 4 + 4,
1884 .vtotal = 768 + 4 + 4 + 4,
4c930757
SW		 1885};
1886
1887static const struct panel_desc chunghwa_claa101wa01a = {
1888 .modes = &chunghwa_claa101wa01a_mode,
1889 .num_modes = 1,
0208d511 1890 .bpc = 6,
4c930757
SW		 1891 .size = {
1892 .width = 220,
1893 .height = 120,
1894 },
85560829 1895 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1896 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1897 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4c930757
SW		 1898};
1899
280921de
TR		 1900static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1901 .clock = 69300,
1902 .hdisplay = 1366,
1903 .hsync_start = 1366 + 48,
1904 .hsync_end = 1366 + 48 + 32,
1905 .htotal = 1366 + 48 + 32 + 20,
1906 .vdisplay = 768,
1907 .vsync_start = 768 + 16,
1908 .vsync_end = 768 + 16 + 8,
1909 .vtotal = 768 + 16 + 8 + 16,
280921de
TR		 1910};
1911
1912static const struct panel_desc chunghwa_claa101wb01 = {
1913 .modes = &chunghwa_claa101wb01_mode,
1914 .num_modes = 1,
0208d511 1915 .bpc = 6,
280921de
TR		 1916 .size = {
1917 .width = 223,
1918 .height = 125,
1919 },
85560829 1920 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 1921 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 1922 .connector_type = DRM_MODE_CONNECTOR_LVDS,
280921de
TR		 1923};
1924
97ceb1fb
MV		 1925static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1926 .clock = 33260,
1927 .hdisplay = 800,
1928 .hsync_start = 800 + 40,
1929 .hsync_end = 800 + 40 + 128,
1930 .htotal = 800 + 40 + 128 + 88,
1931 .vdisplay = 480,
1932 .vsync_start = 480 + 10,
1933 .vsync_end = 480 + 10 + 2,
1934 .vtotal = 480 + 10 + 2 + 33,
97ceb1fb
MV		 1935 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1936};
1937
1938static const struct panel_desc dataimage_scf0700c48ggu18 = {
1939 .modes = &dataimage_scf0700c48ggu18_mode,
1940 .num_modes = 1,
1941 .bpc = 8,
1942 .size = {
1943 .width = 152,
1944 .height = 91,
1945 },
1946 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 1947 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
97ceb1fb
MV		 1948};
1949
0ca0c827
PZ		 1950static const struct display_timing dlc_dlc0700yzg_1_timing = {
1951 .pixelclock = { 45000000, 51200000, 57000000 },
1952 .hactive = { 1024, 1024, 1024 },
1953 .hfront_porch = { 100, 106, 113 },
1954 .hback_porch = { 100, 106, 113 },
1955 .hsync_len = { 100, 108, 114 },
1956 .vactive = { 600, 600, 600 },
1957 .vfront_porch = { 8, 11, 15 },
1958 .vback_porch = { 8, 11, 15 },
1959 .vsync_len = { 9, 13, 15 },
1960 .flags = DISPLAY_FLAGS_DE_HIGH,
1961};
1962
1963static const struct panel_desc dlc_dlc0700yzg_1 = {
1964 .timings = &dlc_dlc0700yzg_1_timing,
1965 .num_timings = 1,
1966 .bpc = 6,
1967 .size = {
1968 .width = 154,
1969 .height = 86,
1970 },
1971 .delay = {
1972 .prepare = 30,
1973 .enable = 200,
1974 .disable = 200,
1975 },
1976 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 1977 .connector_type = DRM_MODE_CONNECTOR_LVDS,
0ca0c827
PZ		 1978};
1979
6cbe7cd1
MF		 1980static const struct display_timing dlc_dlc1010gig_timing = {
1981 .pixelclock = { 68900000, 71100000, 73400000 },
1982 .hactive = { 1280, 1280, 1280 },
1983 .hfront_porch = { 43, 53, 63 },
1984 .hback_porch = { 43, 53, 63 },
1985 .hsync_len = { 44, 54, 64 },
1986 .vactive = { 800, 800, 800 },
1987 .vfront_porch = { 5, 8, 11 },
1988 .vback_porch = { 5, 8, 11 },
1989 .vsync_len = { 5, 7, 11 },
1990 .flags = DISPLAY_FLAGS_DE_HIGH,
1991};
1992
1993static const struct panel_desc dlc_dlc1010gig = {
1994 .timings = &dlc_dlc1010gig_timing,
1995 .num_timings = 1,
1996 .bpc = 8,
1997 .size = {
1998 .width = 216,
1999 .height = 135,
2000 },
2001 .delay = {
2002 .prepare = 60,
2003 .enable = 150,
2004 .disable = 100,
2005 .unprepare = 60,
2006 },
2007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2008 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6cbe7cd1
MF		 2009};
2010
c2d24af6
AP		 2011static const struct drm_display_mode edt_et035012dm6_mode = {
2012 .clock = 6500,
2013 .hdisplay = 320,
2014 .hsync_start = 320 + 20,
2015 .hsync_end = 320 + 20 + 30,
2016 .htotal = 320 + 20 + 68,
2017 .vdisplay = 240,
2018 .vsync_start = 240 + 4,
2019 .vsync_end = 240 + 4 + 4,
2020 .vtotal = 240 + 4 + 4 + 14,
c2d24af6
AP		 2021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2022};
2023
2024static const struct panel_desc edt_et035012dm6 = {
2025 .modes = &edt_et035012dm6_mode,
2026 .num_modes = 1,
2027 .bpc = 8,
2028 .size = {
2029 .width = 70,
2030 .height = 52,
2031 },
2032 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2033 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
c2d24af6
AP		 2034};
2035
f08a2a1e
SR		 2036static const struct drm_display_mode edt_etm0350g0dh6_mode = {
2037 .clock = 6520,
2038 .hdisplay = 320,
2039 .hsync_start = 320 + 20,
2040 .hsync_end = 320 + 20 + 68,
2041 .htotal = 320 + 20 + 68,
2042 .vdisplay = 240,
2043 .vsync_start = 240 + 4,
2044 .vsync_end = 240 + 4 + 18,
2045 .vtotal = 240 + 4 + 18,
2046 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2047};
2048
2049static const struct panel_desc edt_etm0350g0dh6 = {
2050 .modes = &edt_etm0350g0dh6_mode,
2051 .num_modes = 1,
2052 .bpc = 6,
2053 .size = {
2054 .width = 70,
2055 .height = 53,
2056 },
2057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2058 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2059 .connector_type = DRM_MODE_CONNECTOR_DPI,
2060};
2061
82d57a59
MCR		 2062static const struct drm_display_mode edt_etm043080dh6gp_mode = {
2063 .clock = 10870,
2064 .hdisplay = 480,
2065 .hsync_start = 480 + 8,
2066 .hsync_end = 480 + 8 + 4,
2067 .htotal = 480 + 8 + 4 + 41,
2068
2069 /*
2070 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
2071 * fb_align
2072 */
2073
2074 .vdisplay = 288,
2075 .vsync_start = 288 + 2,
2076 .vsync_end = 288 + 2 + 4,
2077 .vtotal = 288 + 2 + 4 + 10,
82d57a59
MCR		 2078};
2079
2080static const struct panel_desc edt_etm043080dh6gp = {
2081 .modes = &edt_etm043080dh6gp_mode,
2082 .num_modes = 1,
2083 .bpc = 8,
2084 .size = {
2085 .width = 100,
2086 .height = 65,
2087 },
2088 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2089 .connector_type = DRM_MODE_CONNECTOR_DPI,
2090};
2091
fd819bff
MV		 2092static const struct drm_display_mode edt_etm0430g0dh6_mode = {
2093 .clock = 9000,
2094 .hdisplay = 480,
2095 .hsync_start = 480 + 2,
2096 .hsync_end = 480 + 2 + 41,
2097 .htotal = 480 + 2 + 41 + 2,
2098 .vdisplay = 272,
2099 .vsync_start = 272 + 2,
2100 .vsync_end = 272 + 2 + 10,
2101 .vtotal = 272 + 2 + 10 + 2,
fd819bff
MV		 2102 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2103};
2104
2105static const struct panel_desc edt_etm0430g0dh6 = {
2106 .modes = &edt_etm0430g0dh6_mode,
2107 .num_modes = 1,
2108 .bpc = 6,
2109 .size = {
2110 .width = 95,
2111 .height = 54,
2112 },
4824a5f7
SR		 2113 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d112e10f 2115 .connector_type = DRM_MODE_CONNECTOR_DPI,
fd819bff
MV		 2116};
2117
26ab0065
SA		 2118static const struct drm_display_mode edt_et057090dhu_mode = {
2119 .clock = 25175,
2120 .hdisplay = 640,
2121 .hsync_start = 640 + 16,
2122 .hsync_end = 640 + 16 + 30,
2123 .htotal = 640 + 16 + 30 + 114,
2124 .vdisplay = 480,
2125 .vsync_start = 480 + 10,
2126 .vsync_end = 480 + 10 + 3,
2127 .vtotal = 480 + 10 + 3 + 32,
26ab0065
SA		 2128 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2129};
2130
2131static const struct panel_desc edt_et057090dhu = {
2132 .modes = &edt_et057090dhu_mode,
2133 .num_modes = 1,
0208d511 2134 .bpc = 6,
26ab0065
SA		 2135 .size = {
2136 .width = 115,
2137 .height = 86,
2138 },
eaeebffa 2139 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 2140 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
75e73224 2141 .connector_type = DRM_MODE_CONNECTOR_DPI,
26ab0065
SA		 2142};
2143
fff5de45
PZ		 2144static const struct drm_display_mode edt_etm0700g0dh6_mode = {
2145 .clock = 33260,
2146 .hdisplay = 800,
2147 .hsync_start = 800 + 40,
2148 .hsync_end = 800 + 40 + 128,
2149 .htotal = 800 + 40 + 128 + 88,
2150 .vdisplay = 480,
2151 .vsync_start = 480 + 10,
2152 .vsync_end = 480 + 10 + 2,
2153 .vtotal = 480 + 10 + 2 + 33,
fff5de45
PZ		 2154 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2155};
2156
2157static const struct panel_desc edt_etm0700g0dh6 = {
2158 .modes = &edt_etm0700g0dh6_mode,
2159 .num_modes = 1,
0208d511 2160 .bpc = 6,
fff5de45
PZ		 2161 .size = {
2162 .width = 152,
2163 .height = 91,
2164 },
eaeebffa 2165 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 2166 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
281edb9f 2167 .connector_type = DRM_MODE_CONNECTOR_DPI,
fff5de45
PZ		 2168};
2169
aa7e6455
JT		 2170static const struct panel_desc edt_etm0700g0bdh6 = {
2171 .modes = &edt_etm0700g0dh6_mode,
2172 .num_modes = 1,
2173 .bpc = 6,
2174 .size = {
2175 .width = 152,
2176 .height = 91,
2177 },
2178 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 2179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
d112e10f 2180 .connector_type = DRM_MODE_CONNECTOR_DPI,
aa7e6455
JT		 2181};
2182
e46f73fb
SR		 2183static const struct drm_display_mode edt_etmv570g2dhu_mode = {
2184 .clock = 25175,
2185 .hdisplay = 640,
2186 .hsync_start = 640,
2187 .hsync_end = 640 + 16,
2188 .htotal = 640 + 16 + 30 + 114,
2189 .vdisplay = 480,
2190 .vsync_start = 480 + 10,
2191 .vsync_end = 480 + 10 + 3,
2192 .vtotal = 480 + 10 + 3 + 35,
2193 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
2194};
2195
2196static const struct panel_desc edt_etmv570g2dhu = {
2197 .modes = &edt_etmv570g2dhu_mode,
2198 .num_modes = 1,
2199 .bpc = 6,
2200 .size = {
2201 .width = 115,
2202 .height = 86,
2203 },
2204 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2205 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
2206 .connector_type = DRM_MODE_CONNECTOR_DPI,
2207};
2208
9158e3c3
MF		 2209static const struct display_timing evervision_vgg804821_timing = {
2210 .pixelclock = { 27600000, 33300000, 50000000 },
2211 .hactive = { 800, 800, 800 },
2212 .hfront_porch = { 40, 66, 70 },
2213 .hback_porch = { 40, 67, 70 },
2214 .hsync_len = { 40, 67, 70 },
2215 .vactive = { 480, 480, 480 },
2216 .vfront_porch = { 6, 10, 10 },
2217 .vback_porch = { 7, 11, 11 },
2218 .vsync_len = { 7, 11, 11 },
2219 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
2220 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2221 DISPLAY_FLAGS_SYNC_NEGEDGE,
2222};
2223
2224static const struct panel_desc evervision_vgg804821 = {
2225 .timings = &evervision_vgg804821_timing,
2226 .num_timings = 1,
2227 .bpc = 8,
2228 .size = {
2229 .width = 108,
2230 .height = 64,
2231 },
2232 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2233 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
9158e3c3
MF		 2234};
2235
102932b0
BB		 2236static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
2237 .clock = 32260,
2238 .hdisplay = 800,
2239 .hsync_start = 800 + 168,
2240 .hsync_end = 800 + 168 + 64,
2241 .htotal = 800 + 168 + 64 + 88,
2242 .vdisplay = 480,
2243 .vsync_start = 480 + 37,
2244 .vsync_end = 480 + 37 + 2,
2245 .vtotal = 480 + 37 + 2 + 8,
102932b0
BB		 2246};
2247
2248static const struct panel_desc foxlink_fl500wvr00_a0t = {
2249 .modes = &foxlink_fl500wvr00_a0t_mode,
2250 .num_modes = 1,
d7a839cd 2251 .bpc = 8,
102932b0
BB		 2252 .size = {
2253 .width = 108,
2254 .height = 65,
2255 },
bb276cb3 2256 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 2257};
2258
795db2af
PC		 2259static const struct drm_display_mode frida_frd350h54004_modes[] = {
2260 { /* 60 Hz */
2261 .clock = 6000,
2262 .hdisplay = 320,
2263 .hsync_start = 320 + 44,
2264 .hsync_end = 320 + 44 + 16,
2265 .htotal = 320 + 44 + 16 + 20,
2266 .vdisplay = 240,
2267 .vsync_start = 240 + 2,
2268 .vsync_end = 240 + 2 + 6,
2269 .vtotal = 240 + 2 + 6 + 2,
2270 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2271 },
2272 { /* 50 Hz */
2273 .clock = 5400,
2274 .hdisplay = 320,
2275 .hsync_start = 320 + 56,
2276 .hsync_end = 320 + 56 + 16,
2277 .htotal = 320 + 56 + 16 + 40,
2278 .vdisplay = 240,
2279 .vsync_start = 240 + 2,
2280 .vsync_end = 240 + 2 + 6,
2281 .vtotal = 240 + 2 + 6 + 2,
2282 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2283 },
7b6bd843
PC		 2284};
2285
2286static const struct panel_desc frida_frd350h54004 = {
795db2af
PC		 2287 .modes = frida_frd350h54004_modes,
2288 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
7b6bd843
PC		 2289 .bpc = 8,
2290 .size = {
2291 .width = 77,
2292 .height = 64,
2293 },
2294 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 2295 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
7b6bd843
PC		 2296 .connector_type = DRM_MODE_CONNECTOR_DPI,
2297};
2298
3be20710
JT		 2299static const struct drm_display_mode friendlyarm_hd702e_mode = {
2300 .clock = 67185,
2301 .hdisplay = 800,
2302 .hsync_start = 800 + 20,
2303 .hsync_end = 800 + 20 + 24,
2304 .htotal = 800 + 20 + 24 + 20,
2305 .vdisplay = 1280,
2306 .vsync_start = 1280 + 4,
2307 .vsync_end = 1280 + 4 + 8,
2308 .vtotal = 1280 + 4 + 8 + 4,
3be20710
JT		 2309 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2310};
2311
2312static const struct panel_desc friendlyarm_hd702e = {
2313 .modes = &friendlyarm_hd702e_mode,
2314 .num_modes = 1,
2315 .size = {
2316 .width = 94,
2317 .height = 151,
2318 },
2319};
2320
d435a2af
PZ		 2321static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2322 .clock = 9000,
2323 .hdisplay = 480,
2324 .hsync_start = 480 + 5,
2325 .hsync_end = 480 + 5 + 1,
2326 .htotal = 480 + 5 + 1 + 40,
2327 .vdisplay = 272,
2328 .vsync_start = 272 + 8,
2329 .vsync_end = 272 + 8 + 1,
2330 .vtotal = 272 + 8 + 1 + 8,
d435a2af
PZ		 2331};
2332
2333static const struct panel_desc giantplus_gpg482739qs5 = {
2334 .modes = &giantplus_gpg482739qs5_mode,
2335 .num_modes = 1,
2336 .bpc = 8,
2337 .size = {
2338 .width = 95,
2339 .height = 54,
2340 },
33536a09 2341 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 2342};
2343
2c6574a9
PC		 2344static const struct display_timing giantplus_gpm940b0_timing = {
2345 .pixelclock = { 13500000, 27000000, 27500000 },
2346 .hactive = { 320, 320, 320 },
2347 .hfront_porch = { 14, 686, 718 },
2348 .hback_porch = { 50, 70, 255 },
2349 .hsync_len = { 1, 1, 1 },
2350 .vactive = { 240, 240, 240 },
2351 .vfront_porch = { 1, 1, 179 },
2352 .vback_porch = { 1, 21, 31 },
2353 .vsync_len = { 1, 1, 6 },
2354 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2355};
2356
2357static const struct panel_desc giantplus_gpm940b0 = {
2358 .timings = &giantplus_gpm940b0_timing,
2359 .num_timings = 1,
2360 .bpc = 8,
2361 .size = {
2362 .width = 60,
2363 .height = 45,
2364 },
2365 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
f5436f77 2366 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2c6574a9
PC		 2367};
2368
ab07725a
PZ		 2369static const struct display_timing hannstar_hsd070pww1_timing = {
2370 .pixelclock = { 64300000, 71100000, 82000000 },
2371 .hactive = { 1280, 1280, 1280 },
2372 .hfront_porch = { 1, 1, 10 },
2373 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 2374 /*
2375 * According to the data sheet, the minimum horizontal blanking interval
2376 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2377 * minimum working horizontal blanking interval to be 60 clocks.
2378 */
2379 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 2380 .vactive = { 800, 800, 800 },
2381 .vfront_porch = { 1, 1, 10 },
2382 .vback_porch = { 1, 1, 10 },
2383 .vsync_len = { 1, 21, 203 },
2384 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 2385};
2386
2387static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 2388 .timings = &hannstar_hsd070pww1_timing,
2389 .num_timings = 1,
a853205e
PZ		 2390 .bpc = 6,
2391 .size = {
2392 .width = 151,
2393 .height = 94,
2394 },
58d6a7bc 2395 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2396 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a853205e
PZ		 2397};
2398
c0d607e5
EN		 2399static const struct display_timing hannstar_hsd100pxn1_timing = {
2400 .pixelclock = { 55000000, 65000000, 75000000 },
2401 .hactive = { 1024, 1024, 1024 },
2402 .hfront_porch = { 40, 40, 40 },
2403 .hback_porch = { 220, 220, 220 },
2404 .hsync_len = { 20, 60, 100 },
2405 .vactive = { 768, 768, 768 },
2406 .vfront_porch = { 7, 7, 7 },
2407 .vback_porch = { 21, 21, 21 },
2408 .vsync_len = { 10, 10, 10 },
2409 .flags = DISPLAY_FLAGS_DE_HIGH,
2410};
2411
2412static const struct panel_desc hannstar_hsd100pxn1 = {
2413 .timings = &hannstar_hsd100pxn1_timing,
2414 .num_timings = 1,
2415 .bpc = 6,
2416 .size = {
2417 .width = 203,
2418 .height = 152,
2419 },
4946b043 2420 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2421 .connector_type = DRM_MODE_CONNECTOR_LVDS,
c0d607e5
EN		 2422};
2423
61ac0bf8
LS		 2424static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2425 .clock = 33333,
2426 .hdisplay = 800,
2427 .hsync_start = 800 + 85,
2428 .hsync_end = 800 + 85 + 86,
2429 .htotal = 800 + 85 + 86 + 85,
2430 .vdisplay = 480,
2431 .vsync_start = 480 + 16,
2432 .vsync_end = 480 + 16 + 13,
2433 .vtotal = 480 + 16 + 13 + 16,
61ac0bf8
LS		 2434};
2435
2436static const struct panel_desc hitachi_tx23d38vm0caa = {
2437 .modes = &hitachi_tx23d38vm0caa_mode,
2438 .num_modes = 1,
2439 .bpc = 6,
2440 .size = {
2441 .width = 195,
2442 .height = 117,
2443 },
6c684e3b
PZ		 2444 .delay = {
2445 .enable = 160,
2446 .disable = 160,
2447 },
61ac0bf8
LS		 2448};
2449
41bcceb4
NF		 2450static const struct drm_display_mode innolux_at043tn24_mode = {
2451 .clock = 9000,
2452 .hdisplay = 480,
2453 .hsync_start = 480 + 2,
2454 .hsync_end = 480 + 2 + 41,
2455 .htotal = 480 + 2 + 41 + 2,
2456 .vdisplay = 272,
2457 .vsync_start = 272 + 2,
a483159d
PZ		 2458 .vsync_end = 272 + 2 + 10,
2459 .vtotal = 272 + 2 + 10 + 2,
41bcceb4
NF		 2460 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2461};
2462
2463static const struct panel_desc innolux_at043tn24 = {
2464 .modes = &innolux_at043tn24_mode,
2465 .num_modes = 1,
2466 .bpc = 8,
2467 .size = {
2468 .width = 95,
2469 .height = 54,
2470 },
2471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 2472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
41bcceb4
NF		 2473};
2474
4fc24ab3
RB		 2475static const struct drm_display_mode innolux_at070tn92_mode = {
2476 .clock = 33333,
2477 .hdisplay = 800,
2478 .hsync_start = 800 + 210,
2479 .hsync_end = 800 + 210 + 20,
2480 .htotal = 800 + 210 + 20 + 46,
2481 .vdisplay = 480,
2482 .vsync_start = 480 + 22,
2483 .vsync_end = 480 + 22 + 10,
2484 .vtotal = 480 + 22 + 23 + 10,
4fc24ab3
RB		 2485};
2486
2487static const struct panel_desc innolux_at070tn92 = {
2488 .modes = &innolux_at070tn92_mode,
2489 .num_modes = 1,
2490 .size = {
2491 .width = 154,
2492 .height = 86,
2493 },
2494 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2495};
2496
a5d2ade6
CF		 2497static const struct display_timing innolux_g070y2_l01_timing = {
2498 .pixelclock = { 28000000, 29500000, 32000000 },
2499 .hactive = { 800, 800, 800 },
2500 .hfront_porch = { 61, 91, 141 },
2501 .hback_porch = { 60, 90, 140 },
2502 .hsync_len = { 12, 12, 12 },
2503 .vactive = { 480, 480, 480 },
2504 .vfront_porch = { 4, 9, 30 },
2505 .vback_porch = { 4, 8, 28 },
2506 .vsync_len = { 2, 2, 2 },
2507 .flags = DISPLAY_FLAGS_DE_HIGH,
2508};
2509
2510static const struct panel_desc innolux_g070y2_l01 = {
2511 .timings = &innolux_g070y2_l01_timing,
2512 .num_timings = 1,
2513 .bpc = 6,
2514 .size = {
2515 .width = 152,
2516 .height = 91,
2517 },
2518 .delay = {
2519 .prepare = 10,
2520 .enable = 100,
2521 .disable = 100,
2522 .unprepare = 800,
2523 },
2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2525 .connector_type = DRM_MODE_CONNECTOR_LVDS,
a5d2ade6
CF		 2526};
2527
1e29b840
MO		 2528static const struct display_timing innolux_g101ice_l01_timing = {
2529 .pixelclock = { 60400000, 71100000, 74700000 },
2530 .hactive = { 1280, 1280, 1280 },
2531 .hfront_porch = { 41, 80, 100 },
2532 .hback_porch = { 40, 79, 99 },
2533 .hsync_len = { 1, 1, 1 },
2534 .vactive = { 800, 800, 800 },
2535 .vfront_porch = { 5, 11, 14 },
2536 .vback_porch = { 4, 11, 14 },
2537 .vsync_len = { 1, 1, 1 },
2538 .flags = DISPLAY_FLAGS_DE_HIGH,
2539};
2540
2541static const struct panel_desc innolux_g101ice_l01 = {
2542 .timings = &innolux_g101ice_l01_timing,
2543 .num_timings = 1,
2544 .bpc = 8,
2545 .size = {
2546 .width = 217,
2547 .height = 135,
2548 },
2549 .delay = {
2550 .enable = 200,
2551 .disable = 200,
2552 },
2553 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2554 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1e29b840
MO		 2555};
2556
4ae13e48
LS		 2557static const struct display_timing innolux_g121i1_l01_timing = {
2558 .pixelclock = { 67450000, 71000000, 74550000 },
2559 .hactive = { 1280, 1280, 1280 },
2560 .hfront_porch = { 40, 80, 160 },
2561 .hback_porch = { 39, 79, 159 },
2562 .hsync_len = { 1, 1, 1 },
2563 .vactive = { 800, 800, 800 },
2564 .vfront_porch = { 5, 11, 100 },
2565 .vback_porch = { 4, 11, 99 },
2566 .vsync_len = { 1, 1, 1 },
d731f661
LS		 2567};
2568
2569static const struct panel_desc innolux_g121i1_l01 = {
4ae13e48
LS		 2570 .timings = &innolux_g121i1_l01_timing,
2571 .num_timings = 1,
d731f661
LS		 2572 .bpc = 6,
2573 .size = {
2574 .width = 261,
2575 .height = 163,
2576 },
4ae13e48
LS		 2577 .delay = {
2578 .enable = 200,
2579 .disable = 20,
2580 },
2581 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2582 .connector_type = DRM_MODE_CONNECTOR_LVDS,
d731f661
LS		 2583};
2584
f8fa17ba
AB		 2585static const struct drm_display_mode innolux_g121x1_l03_mode = {
2586 .clock = 65000,
2587 .hdisplay = 1024,
2588 .hsync_start = 1024 + 0,
2589 .hsync_end = 1024 + 1,
2590 .htotal = 1024 + 0 + 1 + 320,
2591 .vdisplay = 768,
2592 .vsync_start = 768 + 38,
2593 .vsync_end = 768 + 38 + 1,
2594 .vtotal = 768 + 38 + 1 + 0,
2e8c5eb9 2595 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
f8fa17ba
AB		 2596};
2597
2598static const struct panel_desc innolux_g121x1_l03 = {
2599 .modes = &innolux_g121x1_l03_mode,
2600 .num_modes = 1,
2601 .bpc = 6,
2602 .size = {
2603 .width = 246,
2604 .height = 185,
2605 },
2606 .delay = {
2607 .enable = 200,
2608 .unprepare = 200,
2609 .disable = 400,
2610 },
2611};
2612
51d35631
DA		 2613static const struct drm_display_mode innolux_n116bca_ea1_mode = {
2614 .clock = 76420,
2615 .hdisplay = 1366,
2616 .hsync_start = 1366 + 136,
2617 .hsync_end = 1366 + 136 + 30,
2618 .htotal = 1366 + 136 + 30 + 60,
2619 .vdisplay = 768,
2620 .vsync_start = 768 + 8,
2621 .vsync_end = 768 + 8 + 12,
2622 .vtotal = 768 + 8 + 12 + 12,
2623 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2624};
2625
2626static const struct panel_desc innolux_n116bca_ea1 = {
2627 .modes = &innolux_n116bca_ea1_mode,
2628 .num_modes = 1,
2629 .bpc = 6,
2630 .size = {
2631 .width = 256,
2632 .height = 144,
2633 },
2634 .delay = {
2635 .hpd_absent_delay = 200,
2636 .prepare_to_enable = 80,
2637 .unprepare = 500,
2638 },
2639 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2640 .connector_type = DRM_MODE_CONNECTOR_eDP,
2641};
2642
d719cbe9
DA		 2643/*
2644 * Datasheet specifies that at 60 Hz refresh rate:
2645 * - total horizontal time: { 1506, 1592, 1716 }
2646 * - total vertical time: { 788, 800, 868 }
2647 *
2648 * ...but doesn't go into exactly how that should be split into a front
2649 * porch, back porch, or sync length. For now we'll leave a single setting
2650 * here which allows a bit of tweaking of the pixel clock at the expense of
2651 * refresh rate.
2652 */
2653static const struct display_timing innolux_n116bge_timing = {
2654 .pixelclock = { 72600000, 76420000, 80240000 },
2655 .hactive = { 1366, 1366, 1366 },
2656 .hfront_porch = { 136, 136, 136 },
2657 .hback_porch = { 60, 60, 60 },
2658 .hsync_len = { 30, 30, 30 },
2659 .vactive = { 768, 768, 768 },
2660 .vfront_porch = { 8, 8, 8 },
2661 .vback_porch = { 12, 12, 12 },
2662 .vsync_len = { 12, 12, 12 },
2663 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
0a2288c0
TR		 2664};
2665
2666static const struct panel_desc innolux_n116bge = {
d719cbe9
DA		 2667 .timings = &innolux_n116bge_timing,
2668 .num_timings = 1,
0a2288c0
TR		 2669 .bpc = 6,
2670 .size = {
2671 .width = 256,
2672 .height = 144,
2673 },
87969bcd
HS		 2674 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2675 .connector_type = DRM_MODE_CONNECTOR_eDP,
0a2288c0
TR		 2676};
2677
a14c6b0e
LH		 2678static const struct drm_display_mode innolux_n125hce_gn1_mode = {
2679 .clock = 162000,
2680 .hdisplay = 1920,
2681 .hsync_start = 1920 + 40,
2682 .hsync_end = 1920 + 40 + 40,
2683 .htotal = 1920 + 40 + 40 + 80,
2684 .vdisplay = 1080,
2685 .vsync_start = 1080 + 4,
2686 .vsync_end = 1080 + 4 + 4,
2687 .vtotal = 1080 + 4 + 4 + 24,
2688};
2689
2690static const struct panel_desc innolux_n125hce_gn1 = {
2691 .modes = &innolux_n125hce_gn1_mode,
2692 .num_modes = 1,
2693 .bpc = 8,
2694 .size = {
2695 .width = 276,
2696 .height = 155,
2697 },
2698 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2699 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2700 .connector_type = DRM_MODE_CONNECTOR_eDP,
2701};
2702
ea44739d
AB		 2703static const struct drm_display_mode innolux_n156bge_l21_mode = {
2704 .clock = 69300,
2705 .hdisplay = 1366,
2706 .hsync_start = 1366 + 16,
2707 .hsync_end = 1366 + 16 + 34,
2708 .htotal = 1366 + 16 + 34 + 50,
2709 .vdisplay = 768,
2710 .vsync_start = 768 + 2,
2711 .vsync_end = 768 + 2 + 6,
2712 .vtotal = 768 + 2 + 6 + 12,
ea44739d
AB		 2713};
2714
2715static const struct panel_desc innolux_n156bge_l21 = {
2716 .modes = &innolux_n156bge_l21_mode,
2717 .num_modes = 1,
0208d511 2718 .bpc = 6,
ea44739d
AB		 2719 .size = {
2720 .width = 344,
2721 .height = 193,
2722 },
85560829 2723 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 2724 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 2725 .connector_type = DRM_MODE_CONNECTOR_LVDS,
ea44739d
AB		 2726};
2727
8f054b6f 2728static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
da50bd42 2729 .clock = 206016,
2730 .hdisplay = 2160,
2731 .hsync_start = 2160 + 48,
2732 .hsync_end = 2160 + 48 + 32,
2733 .htotal = 2160 + 48 + 32 + 80,
2734 .vdisplay = 1440,
2735 .vsync_start = 1440 + 3,
2736 .vsync_end = 1440 + 3 + 10,
2737 .vtotal = 1440 + 3 + 10 + 27,
da50bd42 2738 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2739};
2740
8f054b6f
DA		 2741static const struct panel_desc innolux_p120zdg_bf1 = {
2742 .modes = &innolux_p120zdg_bf1_mode,
da50bd42 2743 .num_modes = 1,
2744 .bpc = 8,
2745 .size = {
8f054b6f
DA		 2746 .width = 254,
2747 .height = 169,
da50bd42 2748 },
22fd99e9 2749 .delay = {
625d3b5c 2750 .hpd_absent_delay = 200,
22fd99e9
SP		 2751 .unprepare = 500,
2752 },
da50bd42 2753};
2754
bccac3f1
MG		 2755static const struct drm_display_mode innolux_zj070na_01p_mode = {
2756 .clock = 51501,
2757 .hdisplay = 1024,
2758 .hsync_start = 1024 + 128,
2759 .hsync_end = 1024 + 128 + 64,
2760 .htotal = 1024 + 128 + 64 + 128,
2761 .vdisplay = 600,
2762 .vsync_start = 600 + 16,
2763 .vsync_end = 600 + 16 + 4,
2764 .vtotal = 600 + 16 + 4 + 16,
bccac3f1
MG		 2765};
2766
2767static const struct panel_desc innolux_zj070na_01p = {
2768 .modes = &innolux_zj070na_01p_mode,
2769 .num_modes = 1,
2770 .bpc = 6,
2771 .size = {
81598846
TR		 2772 .width = 154,
2773 .height = 90,
bccac3f1
MG		 2774 },
2775};
2776
e1ca5184
BA		 2777static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
2778 .clock = 138778,
2779 .hdisplay = 1920,
2780 .hsync_start = 1920 + 24,
2781 .hsync_end = 1920 + 24 + 48,
2782 .htotal = 1920 + 24 + 48 + 88,
2783 .vdisplay = 1080,
2784 .vsync_start = 1080 + 3,
2785 .vsync_end = 1080 + 3 + 12,
2786 .vtotal = 1080 + 3 + 12 + 17,
e1ca5184
BA		 2787 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2788};
2789
2790static const struct panel_desc ivo_m133nwf4_r0 = {
2791 .modes = &ivo_m133nwf4_r0_mode,
2792 .num_modes = 1,
2793 .bpc = 8,
2794 .size = {
2795 .width = 294,
2796 .height = 165,
2797 },
2798 .delay = {
2799 .hpd_absent_delay = 200,
2800 .unprepare = 500,
2801 },
2802 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2803 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2804 .connector_type = DRM_MODE_CONNECTOR_eDP,
2805};
2806
fc26a375
DA		 2807static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = {
2808 .clock = 81000,
2809 .hdisplay = 1366,
2810 .hsync_start = 1366 + 40,
2811 .hsync_end = 1366 + 40 + 32,
2812 .htotal = 1366 + 40 + 32 + 62,
2813 .vdisplay = 768,
2814 .vsync_start = 768 + 5,
2815 .vsync_end = 768 + 5 + 5,
2816 .vtotal = 768 + 5 + 5 + 122,
2817 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2818};
2819
2820static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = {
2821 .modes = &kingdisplay_kd116n21_30nv_a010_mode,
2822 .num_modes = 1,
2823 .bpc = 6,
2824 .size = {
2825 .width = 256,
2826 .height = 144,
2827 },
2828 .delay = {
2829 .hpd_absent_delay = 200,
2830 },
2831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2832 .connector_type = DRM_MODE_CONNECTOR_eDP,
2833};
2834
14bf60c4
LM		 2835static const struct display_timing koe_tx14d24vm1bpa_timing = {
2836 .pixelclock = { 5580000, 5850000, 6200000 },
2837 .hactive = { 320, 320, 320 },
2838 .hfront_porch = { 30, 30, 30 },
2839 .hback_porch = { 30, 30, 30 },
2840 .hsync_len = { 1, 5, 17 },
2841 .vactive = { 240, 240, 240 },
2842 .vfront_porch = { 6, 6, 6 },
2843 .vback_porch = { 5, 5, 5 },
2844 .vsync_len = { 1, 2, 11 },
2845 .flags = DISPLAY_FLAGS_DE_HIGH,
2846};
2847
2848static const struct panel_desc koe_tx14d24vm1bpa = {
2849 .timings = &koe_tx14d24vm1bpa_timing,
2850 .num_timings = 1,
2851 .bpc = 6,
2852 .size = {
2853 .width = 115,
2854 .height = 86,
2855 },
2856};
2857
8a070524
LY		 2858static const struct display_timing koe_tx26d202vm0bwa_timing = {
2859 .pixelclock = { 151820000, 156720000, 159780000 },
2860 .hactive = { 1920, 1920, 1920 },
2861 .hfront_porch = { 105, 130, 142 },
2862 .hback_porch = { 45, 70, 82 },
2863 .hsync_len = { 30, 30, 30 },
2864 .vactive = { 1200, 1200, 1200},
2865 .vfront_porch = { 3, 5, 10 },
2866 .vback_porch = { 2, 5, 10 },
2867 .vsync_len = { 5, 5, 5 },
2868};
2869
2870static const struct panel_desc koe_tx26d202vm0bwa = {
2871 .timings = &koe_tx26d202vm0bwa_timing,
2872 .num_timings = 1,
2873 .bpc = 8,
2874 .size = {
2875 .width = 217,
2876 .height = 136,
2877 },
2878 .delay = {
2879 .prepare = 1000,
2880 .enable = 1000,
2881 .unprepare = 1000,
2882 .disable = 1000,
2883 },
2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 2885 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
8a070524
LY		 2886 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2887};
2888
8cfe8341
JT		 2889static const struct display_timing koe_tx31d200vm0baa_timing = {
2890 .pixelclock = { 39600000, 43200000, 48000000 },
2891 .hactive = { 1280, 1280, 1280 },
2892 .hfront_porch = { 16, 36, 56 },
2893 .hback_porch = { 16, 36, 56 },
2894 .hsync_len = { 8, 8, 8 },
2895 .vactive = { 480, 480, 480 },
c9b6be7d
SA		 2896 .vfront_porch = { 6, 21, 33 },
2897 .vback_porch = { 6, 21, 33 },
8cfe8341
JT		 2898 .vsync_len = { 8, 8, 8 },
2899 .flags = DISPLAY_FLAGS_DE_HIGH,
2900};
2901
2902static const struct panel_desc koe_tx31d200vm0baa = {
2903 .timings = &koe_tx31d200vm0baa_timing,
2904 .num_timings = 1,
2905 .bpc = 6,
2906 .size = {
2907 .width = 292,
2908 .height = 109,
2909 },
2910 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 2911 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8cfe8341
JT		 2912};
2913
8def22e5
LS		 2914static const struct display_timing kyo_tcg121xglp_timing = {
2915 .pixelclock = { 52000000, 65000000, 71000000 },
2916 .hactive = { 1024, 1024, 1024 },
2917 .hfront_porch = { 2, 2, 2 },
2918 .hback_porch = { 2, 2, 2 },
2919 .hsync_len = { 86, 124, 244 },
2920 .vactive = { 768, 768, 768 },
2921 .vfront_porch = { 2, 2, 2 },
2922 .vback_porch = { 2, 2, 2 },
2923 .vsync_len = { 6, 34, 73 },
2924 .flags = DISPLAY_FLAGS_DE_HIGH,
2925};
2926
2927static const struct panel_desc kyo_tcg121xglp = {
2928 .timings = &kyo_tcg121xglp_timing,
2929 .num_timings = 1,
2930 .bpc = 8,
2931 .size = {
2932 .width = 246,
2933 .height = 184,
2934 },
2935 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2936 .connector_type = DRM_MODE_CONNECTOR_LVDS,
8def22e5
LS		 2937};
2938
27abdd83
PK		 2939static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2940 .clock = 7000,
2941 .hdisplay = 320,
2942 .hsync_start = 320 + 20,
2943 .hsync_end = 320 + 20 + 30,
2944 .htotal = 320 + 20 + 30 + 38,
2945 .vdisplay = 240,
2946 .vsync_start = 240 + 4,
2947 .vsync_end = 240 + 4 + 3,
2948 .vtotal = 240 + 4 + 3 + 15,
27abdd83
PK		 2949};
2950
2951static const struct panel_desc lemaker_bl035_rgb_002 = {
2952 .modes = &lemaker_bl035_rgb_002_mode,
2953 .num_modes = 1,
2954 .size = {
2955 .width = 70,
2956 .height = 52,
2957 },
2958 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2959 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2960};
2961
dd015002
HS		 2962static const struct drm_display_mode lg_lb070wv8_mode = {
2963 .clock = 33246,
2964 .hdisplay = 800,
2965 .hsync_start = 800 + 88,
2966 .hsync_end = 800 + 88 + 80,
2967 .htotal = 800 + 88 + 80 + 88,
2968 .vdisplay = 480,
2969 .vsync_start = 480 + 10,
2970 .vsync_end = 480 + 10 + 25,
2971 .vtotal = 480 + 10 + 25 + 10,
dd015002
HS		 2972};
2973
2974static const struct panel_desc lg_lb070wv8 = {
2975 .modes = &lg_lb070wv8_mode,
2976 .num_modes = 1,
a6ae2fe5 2977 .bpc = 8,
dd015002
HS		 2978 .size = {
2979 .width = 151,
2980 .height = 91,
2981 },
2982 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 2983 .connector_type = DRM_MODE_CONNECTOR_LVDS,
dd015002
HS		 2984};
2985
c5ece402
YY		 2986static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
2987 .clock = 200000,
2988 .hdisplay = 1536,
2989 .hsync_start = 1536 + 12,
2990 .hsync_end = 1536 + 12 + 16,
2991 .htotal = 1536 + 12 + 16 + 48,
2992 .vdisplay = 2048,
2993 .vsync_start = 2048 + 8,
2994 .vsync_end = 2048 + 8 + 4,
2995 .vtotal = 2048 + 8 + 4 + 8,
c5ece402
YY		 2996 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2997};
2998
2999static const struct panel_desc lg_lp079qx1_sp0v = {
3000 .modes = &lg_lp079qx1_sp0v_mode,
3001 .num_modes = 1,
3002 .size = {
3003 .width = 129,
3004 .height = 171,
3005 },
3006};
3007
0355dde2
YY		 3008static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
3009 .clock = 205210,
3010 .hdisplay = 2048,
3011 .hsync_start = 2048 + 150,
3012 .hsync_end = 2048 + 150 + 5,
3013 .htotal = 2048 + 150 + 5 + 5,
3014 .vdisplay = 1536,
3015 .vsync_start = 1536 + 3,
3016 .vsync_end = 1536 + 3 + 1,
3017 .vtotal = 1536 + 3 + 1 + 9,
0355dde2
YY		 3018};
3019
3020static const struct panel_desc lg_lp097qx1_spa1 = {
3021 .modes = &lg_lp097qx1_spa1_mode,
3022 .num_modes = 1,
3023 .size = {
3024 .width = 208,
3025 .height = 147,
3026 },
3027};
3028
690d8fa7
JS		 3029static const struct drm_display_mode lg_lp120up1_mode = {
3030 .clock = 162300,
3031 .hdisplay = 1920,
3032 .hsync_start = 1920 + 40,
3033 .hsync_end = 1920 + 40 + 40,
3034 .htotal = 1920 + 40 + 40+ 80,
3035 .vdisplay = 1280,
3036 .vsync_start = 1280 + 4,
3037 .vsync_end = 1280 + 4 + 4,
3038 .vtotal = 1280 + 4 + 4 + 12,
690d8fa7
JS		 3039};
3040
3041static const struct panel_desc lg_lp120up1 = {
3042 .modes = &lg_lp120up1_mode,
3043 .num_modes = 1,
3044 .bpc = 8,
3045 .size = {
3046 .width = 267,
3047 .height = 183,
3048 },
d53139b3 3049 .connector_type = DRM_MODE_CONNECTOR_eDP,
690d8fa7
JS		 3050};
3051
ec7c5653
TR		 3052static const struct drm_display_mode lg_lp129qe_mode = {
3053 .clock = 285250,
3054 .hdisplay = 2560,
3055 .hsync_start = 2560 + 48,
3056 .hsync_end = 2560 + 48 + 32,
3057 .htotal = 2560 + 48 + 32 + 80,
3058 .vdisplay = 1700,
3059 .vsync_start = 1700 + 3,
3060 .vsync_end = 1700 + 3 + 10,
3061 .vtotal = 1700 + 3 + 10 + 36,
ec7c5653
TR		 3062};
3063
3064static const struct panel_desc lg_lp129qe = {
3065 .modes = &lg_lp129qe_mode,
3066 .num_modes = 1,
0208d511 3067 .bpc = 8,
ec7c5653
TR		 3068 .size = {
3069 .width = 272,
3070 .height = 181,
3071 },
3072};
3073
5728fe7f
MZ		 3074static const struct display_timing logictechno_lt161010_2nh_timing = {
3075 .pixelclock = { 26400000, 33300000, 46800000 },
3076 .hactive = { 800, 800, 800 },
3077 .hfront_porch = { 16, 210, 354 },
3078 .hback_porch = { 46, 46, 46 },
3079 .hsync_len = { 1, 20, 40 },
3080 .vactive = { 480, 480, 480 },
3081 .vfront_porch = { 7, 22, 147 },
3082 .vback_porch = { 23, 23, 23 },
3083 .vsync_len = { 1, 10, 20 },
3084 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3085 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3086 DISPLAY_FLAGS_SYNC_POSEDGE,
3087};
3088
3089static const struct panel_desc logictechno_lt161010_2nh = {
3090 .timings = &logictechno_lt161010_2nh_timing,
3091 .num_timings = 1,
3092 .size = {
3093 .width = 154,
3094 .height = 86,
3095 },
3096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3097 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3098 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3099 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3100 .connector_type = DRM_MODE_CONNECTOR_DPI,
3101};
3102
3103static const struct display_timing logictechno_lt170410_2whc_timing = {
3104 .pixelclock = { 68900000, 71100000, 73400000 },
3105 .hactive = { 1280, 1280, 1280 },
3106 .hfront_porch = { 23, 60, 71 },
3107 .hback_porch = { 23, 60, 71 },
3108 .hsync_len = { 15, 40, 47 },
3109 .vactive = { 800, 800, 800 },
3110 .vfront_porch = { 5, 7, 10 },
3111 .vback_porch = { 5, 7, 10 },
3112 .vsync_len = { 6, 9, 12 },
3113 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3114 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3115 DISPLAY_FLAGS_SYNC_POSEDGE,
3116};
3117
3118static const struct panel_desc logictechno_lt170410_2whc = {
3119 .timings = &logictechno_lt170410_2whc_timing,
3120 .num_timings = 1,
3121 .size = {
3122 .width = 217,
3123 .height = 136,
3124 },
3125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
c4715837 3126 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
5728fe7f
MZ		 3127 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3128};
3129
65c766ca
LM		 3130static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
3131 .clock = 30400,
3132 .hdisplay = 800,
3133 .hsync_start = 800 + 0,
3134 .hsync_end = 800 + 1,
3135 .htotal = 800 + 0 + 1 + 160,
3136 .vdisplay = 480,
3137 .vsync_start = 480 + 0,
3138 .vsync_end = 480 + 48 + 1,
3139 .vtotal = 480 + 48 + 1 + 0,
65c766ca
LM		 3140 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3141};
3142
0d35408a 3143static const struct drm_display_mode logicpd_type_28_mode = {
f873c5d8 3144 .clock = 9107,
0d35408a
AF		 3145 .hdisplay = 480,
3146 .hsync_start = 480 + 3,
3147 .hsync_end = 480 + 3 + 42,
3148 .htotal = 480 + 3 + 42 + 2,
3149
3150 .vdisplay = 272,
3151 .vsync_start = 272 + 2,
3152 .vsync_end = 272 + 2 + 11,
3153 .vtotal = 272 + 2 + 11 + 3,
0d35408a
AF		 3154 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3155};
3156
3157static const struct panel_desc logicpd_type_28 = {
3158 .modes = &logicpd_type_28_mode,
3159 .num_modes = 1,
3160 .bpc = 8,
3161 .size = {
3162 .width = 105,
3163 .height = 67,
3164 },
3165 .delay = {
3166 .prepare = 200,
3167 .enable = 200,
3168 .unprepare = 200,
3169 .disable = 200,
3170 },
3171 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3172 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3173 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
efb94790 3174 .connector_type = DRM_MODE_CONNECTOR_DPI,
0d35408a
AF		 3175};
3176
65c766ca
LM		 3177static const struct panel_desc mitsubishi_aa070mc01 = {
3178 .modes = &mitsubishi_aa070mc01_mode,
3179 .num_modes = 1,
3180 .bpc = 8,
3181 .size = {
3182 .width = 152,
3183 .height = 91,
3184 },
3185
3186 .delay = {
3187 .enable = 200,
3188 .unprepare = 200,
3189 .disable = 400,
3190 },
3191 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3192 .connector_type = DRM_MODE_CONNECTOR_LVDS,
65c766ca
LM		 3193 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3194};
3195
01bacc13
LS		 3196static const struct display_timing nec_nl12880bc20_05_timing = {
3197 .pixelclock = { 67000000, 71000000, 75000000 },
3198 .hactive = { 1280, 1280, 1280 },
3199 .hfront_porch = { 2, 30, 30 },
3200 .hback_porch = { 6, 100, 100 },
3201 .hsync_len = { 2, 30, 30 },
3202 .vactive = { 800, 800, 800 },
3203 .vfront_porch = { 5, 5, 5 },
3204 .vback_porch = { 11, 11, 11 },
3205 .vsync_len = { 7, 7, 7 },
3206};
3207
3208static const struct panel_desc nec_nl12880bc20_05 = {
3209 .timings = &nec_nl12880bc20_05_timing,
3210 .num_timings = 1,
3211 .bpc = 8,
3212 .size = {
3213 .width = 261,
3214 .height = 163,
3215 },
3216 .delay = {
3217 .enable = 50,
3218 .disable = 50,
3219 },
3220 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3221 .connector_type = DRM_MODE_CONNECTOR_LVDS,
01bacc13
LS		 3222};
3223
c6e87f91 3224static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
3225 .clock = 10870,
3226 .hdisplay = 480,
3227 .hsync_start = 480 + 2,
3228 .hsync_end = 480 + 2 + 41,
3229 .htotal = 480 + 2 + 41 + 2,
3230 .vdisplay = 272,
3231 .vsync_start = 272 + 2,
3232 .vsync_end = 272 + 2 + 4,
3233 .vtotal = 272 + 2 + 4 + 2,
4bc390c6 3234 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 3235};
3236
3237static const struct panel_desc nec_nl4827hc19_05b = {
3238 .modes = &nec_nl4827hc19_05b_mode,
3239 .num_modes = 1,
3240 .bpc = 8,
3241 .size = {
3242 .width = 95,
3243 .height = 54,
3244 },
2c80661d 3245 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178 3246 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
c6e87f91 3247};
3248
e6c2f066
MR		 3249static const struct drm_display_mode netron_dy_e231732_mode = {
3250 .clock = 66000,
3251 .hdisplay = 1024,
3252 .hsync_start = 1024 + 160,
3253 .hsync_end = 1024 + 160 + 70,
3254 .htotal = 1024 + 160 + 70 + 90,
3255 .vdisplay = 600,
3256 .vsync_start = 600 + 127,
3257 .vsync_end = 600 + 127 + 20,
3258 .vtotal = 600 + 127 + 20 + 3,
e6c2f066
MR		 3259};
3260
3261static const struct panel_desc netron_dy_e231732 = {
3262 .modes = &netron_dy_e231732_mode,
3263 .num_modes = 1,
3264 .size = {
3265 .width = 154,
3266 .height = 87,
3267 },
3268 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3269};
3270
258145ea
VK		 3271static const struct drm_display_mode neweast_wjfh116008a_modes[] = {
3272 {
3273 .clock = 138500,
3274 .hdisplay = 1920,
3275 .hsync_start = 1920 + 48,
3276 .hsync_end = 1920 + 48 + 32,
3277 .htotal = 1920 + 48 + 32 + 80,
3278 .vdisplay = 1080,
3279 .vsync_start = 1080 + 3,
3280 .vsync_end = 1080 + 3 + 5,
3281 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 3282 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3283 }, {
3284 .clock = 110920,
3285 .hdisplay = 1920,
3286 .hsync_start = 1920 + 48,
3287 .hsync_end = 1920 + 48 + 32,
3288 .htotal = 1920 + 48 + 32 + 80,
3289 .vdisplay = 1080,
3290 .vsync_start = 1080 + 3,
3291 .vsync_end = 1080 + 3 + 5,
3292 .vtotal = 1080 + 3 + 5 + 23,
258145ea
VK		 3293 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3294 }
3295};
3296
3297static const struct panel_desc neweast_wjfh116008a = {
3298 .modes = neweast_wjfh116008a_modes,
3299 .num_modes = 2,
3300 .bpc = 6,
3301 .size = {
3302 .width = 260,
3303 .height = 150,
3304 },
3305 .delay = {
3306 .prepare = 110,
3307 .enable = 20,
3308 .unprepare = 500,
3309 },
3310 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3311 .connector_type = DRM_MODE_CONNECTOR_eDP,
3312};
3313
3b39ad7a
TV		 3314static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3315 .clock = 9000,
3316 .hdisplay = 480,
3317 .hsync_start = 480 + 2,
3318 .hsync_end = 480 + 2 + 41,
3319 .htotal = 480 + 2 + 41 + 2,
3320 .vdisplay = 272,
3321 .vsync_start = 272 + 2,
3322 .vsync_end = 272 + 2 + 10,
3323 .vtotal = 272 + 2 + 10 + 2,
3b39ad7a
TV		 3324 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3325};
3326
3327static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3328 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3329 .num_modes = 1,
3330 .bpc = 8,
3331 .size = {
3332 .width = 95,
3333 .height = 54,
3334 },
3335 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
88bc4178
LP		 3336 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3337 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
8a4f5e11 3338 .connector_type = DRM_MODE_CONNECTOR_DPI,
3b39ad7a
TV		 3339};
3340
4177fa66
LS		 3341static const struct display_timing nlt_nl192108ac18_02d_timing = {
3342 .pixelclock = { 130000000, 148350000, 163000000 },
3343 .hactive = { 1920, 1920, 1920 },
3344 .hfront_porch = { 80, 100, 100 },
3345 .hback_porch = { 100, 120, 120 },
3346 .hsync_len = { 50, 60, 60 },
3347 .vactive = { 1080, 1080, 1080 },
3348 .vfront_porch = { 12, 30, 30 },
3349 .vback_porch = { 4, 10, 10 },
3350 .vsync_len = { 4, 5, 5 },
3351};
3352
3353static const struct panel_desc nlt_nl192108ac18_02d = {
3354 .timings = &nlt_nl192108ac18_02d_timing,
3355 .num_timings = 1,
3356 .bpc = 8,
3357 .size = {
3358 .width = 344,
3359 .height = 194,
3360 },
3361 .delay = {
3362 .unprepare = 500,
3363 },
3364 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3365 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4177fa66
LS		 3366};
3367
05ec0e45
FL		 3368static const struct drm_display_mode nvd_9128_mode = {
3369 .clock = 29500,
3370 .hdisplay = 800,
3371 .hsync_start = 800 + 130,
3372 .hsync_end = 800 + 130 + 98,
3373 .htotal = 800 + 0 + 130 + 98,
3374 .vdisplay = 480,
3375 .vsync_start = 480 + 10,
3376 .vsync_end = 480 + 10 + 50,
3377 .vtotal = 480 + 0 + 10 + 50,
3378};
3379
3380static const struct panel_desc nvd_9128 = {
3381 .modes = &nvd_9128_mode,
3382 .num_modes = 1,
3383 .bpc = 8,
3384 .size = {
3385 .width = 156,
3386 .height = 88,
3387 },
3388 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 3389 .connector_type = DRM_MODE_CONNECTOR_LVDS,
05ec0e45
FL		 3390};
3391
a99fb626
GB		 3392static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3393 .pixelclock = { 30000000, 30000000, 40000000 },
3394 .hactive = { 800, 800, 800 },
3395 .hfront_porch = { 40, 40, 40 },
3396 .hback_porch = { 40, 40, 40 },
3397 .hsync_len = { 1, 48, 48 },
3398 .vactive = { 480, 480, 480 },
3399 .vfront_porch = { 13, 13, 13 },
3400 .vback_porch = { 29, 29, 29 },
3401 .vsync_len = { 3, 3, 3 },
3402 .flags = DISPLAY_FLAGS_DE_HIGH,
3403};
3404
3405static const struct panel_desc okaya_rs800480t_7x0gp = {
3406 .timings = &okaya_rs800480t_7x0gp_timing,
3407 .num_timings = 1,
3408 .bpc = 6,
3409 .size = {
3410 .width = 154,
3411 .height = 87,
3412 },
3413 .delay = {
3414 .prepare = 41,
3415 .enable = 50,
3416 .unprepare = 41,
3417 .disable = 50,
3418 },
3419 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3420};
3421
cf5c9e6d
MR		 3422static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3423 .clock = 9000,
3424 .hdisplay = 480,
3425 .hsync_start = 480 + 5,
3426 .hsync_end = 480 + 5 + 30,
3427 .htotal = 480 + 5 + 30 + 10,
3428 .vdisplay = 272,
3429 .vsync_start = 272 + 8,
3430 .vsync_end = 272 + 8 + 5,
3431 .vtotal = 272 + 8 + 5 + 3,
cf5c9e6d
MR		 3432};
3433
3434static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3435 .modes = &olimex_lcd_olinuxino_43ts_mode,
3436 .num_modes = 1,
3437 .size = {
30c6d7ab
JL		 3438 .width = 95,
3439 .height = 54,
cf5c9e6d 3440 },
5c2a7c6b 3441 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
cf5c9e6d
MR		 3442};
3443
e8b6f561
EA		 3444/*
3445 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3446 * pixel clocks, but this is the timing that was being used in the Adafruit
3447 * installation instructions.
3448 */
3449static const struct drm_display_mode ontat_yx700wv03_mode = {
3450 .clock = 29500,
3451 .hdisplay = 800,
3452 .hsync_start = 824,
3453 .hsync_end = 896,
3454 .htotal = 992,
3455 .vdisplay = 480,
3456 .vsync_start = 483,
3457 .vsync_end = 493,
3458 .vtotal = 500,
e8b6f561
EA		 3459 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3460};
3461
3462/*
3463 * Specification at:
3464 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3465 */
3466static const struct panel_desc ontat_yx700wv03 = {
3467 .modes = &ontat_yx700wv03_mode,
3468 .num_modes = 1,
3469 .bpc = 8,
3470 .size = {
3471 .width = 154,
3472 .height = 83,
3473 },
5651e5e0 3474 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
e8b6f561
EA		 3475};
3476
9c31dcb6 3477static const struct drm_display_mode ortustech_com37h3m_mode = {
855e764d 3478 .clock = 22230,
9c31dcb6 3479 .hdisplay = 480,
855e764d
NS		 3480 .hsync_start = 480 + 40,
3481 .hsync_end = 480 + 40 + 10,
3482 .htotal = 480 + 40 + 10 + 40,
9c31dcb6
NS		 3483 .vdisplay = 640,
3484 .vsync_start = 640 + 4,
855e764d
NS		 3485 .vsync_end = 640 + 4 + 2,
3486 .vtotal = 640 + 4 + 2 + 4,
9c31dcb6
NS		 3487 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3488};
3489
3490static const struct panel_desc ortustech_com37h3m = {
3491 .modes = &ortustech_com37h3m_mode,
3492 .num_modes = 1,
3493 .bpc = 8,
3494 .size = {
3495 .width = 56, /* 56.16mm */
3496 .height = 75, /* 74.88mm */
3497 },
3498 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3499 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
9c31dcb6
NS		 3500 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3501};
3502
725c9d40
PZ		 3503static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3504 .clock = 25000,
3505 .hdisplay = 480,
3506 .hsync_start = 480 + 10,
3507 .hsync_end = 480 + 10 + 10,
3508 .htotal = 480 + 10 + 10 + 15,
3509 .vdisplay = 800,
3510 .vsync_start = 800 + 3,
3511 .vsync_end = 800 + 3 + 3,
3512 .vtotal = 800 + 3 + 3 + 3,
725c9d40
PZ		 3513};
3514
3515static const struct panel_desc ortustech_com43h4m85ulc = {
3516 .modes = &ortustech_com43h4m85ulc_mode,
3517 .num_modes = 1,
3b809516 3518 .bpc = 6,
725c9d40
PZ		 3519 .size = {
3520 .width = 56,
3521 .height = 93,
3522 },
f098f168 3523 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
88bc4178 3524 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2ccedf46 3525 .connector_type = DRM_MODE_CONNECTOR_DPI,
725c9d40
PZ		 3526};
3527
163f7a35
LP		 3528static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3529 .clock = 33000,
3530 .hdisplay = 800,
3531 .hsync_start = 800 + 210,
3532 .hsync_end = 800 + 210 + 30,
3533 .htotal = 800 + 210 + 30 + 16,
3534 .vdisplay = 480,
3535 .vsync_start = 480 + 22,
3536 .vsync_end = 480 + 22 + 13,
3537 .vtotal = 480 + 22 + 13 + 10,
163f7a35
LP		 3538 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3539};
3540
3541static const struct panel_desc osddisplays_osd070t1718_19ts = {
3542 .modes = &osddisplays_osd070t1718_19ts_mode,
3543 .num_modes = 1,
3544 .bpc = 8,
3545 .size = {
3546 .width = 152,
3547 .height = 91,
3548 },
3549 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
fb0629ee
TV		 3550 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3551 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
a793f0ee 3552 .connector_type = DRM_MODE_CONNECTOR_DPI,
163f7a35
LP		 3553};
3554
4ba3e563
EH		 3555static const struct drm_display_mode pda_91_00156_a0_mode = {
3556 .clock = 33300,
3557 .hdisplay = 800,
3558 .hsync_start = 800 + 1,
3559 .hsync_end = 800 + 1 + 64,
3560 .htotal = 800 + 1 + 64 + 64,
3561 .vdisplay = 480,
3562 .vsync_start = 480 + 1,
3563 .vsync_end = 480 + 1 + 23,
3564 .vtotal = 480 + 1 + 23 + 22,
4ba3e563
EH		 3565};
3566
3567static const struct panel_desc pda_91_00156_a0 = {
3568 .modes = &pda_91_00156_a0_mode,
3569 .num_modes = 1,
3570 .size = {
3571 .width = 152,
3572 .height = 91,
3573 },
3574 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3575};
3576
d69de69f
MV		 3577static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3578 .clock = 24750,
3579 .hdisplay = 800,
3580 .hsync_start = 800 + 54,
3581 .hsync_end = 800 + 54 + 2,
3582 .htotal = 800 + 54 + 2 + 44,
3583 .vdisplay = 480,
3584 .vsync_start = 480 + 49,
3585 .vsync_end = 480 + 49 + 2,
3586 .vtotal = 480 + 49 + 2 + 22,
3587};
3588
3589static const struct panel_desc powertip_ph800480t013_idf02 = {
3590 .modes = &powertip_ph800480t013_idf02_mode,
3591 .num_modes = 1,
3592 .size = {
3593 .width = 152,
3594 .height = 91,
3595 },
3596 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3597 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3598 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3599 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3600 .connector_type = DRM_MODE_CONNECTOR_DPI,
3601};
4ba3e563 3602
d2a6f0f5
JW		 3603static const struct drm_display_mode qd43003c0_40_mode = {
3604 .clock = 9000,
3605 .hdisplay = 480,
3606 .hsync_start = 480 + 8,
3607 .hsync_end = 480 + 8 + 4,
3608 .htotal = 480 + 8 + 4 + 39,
3609 .vdisplay = 272,
3610 .vsync_start = 272 + 4,
3611 .vsync_end = 272 + 4 + 10,
3612 .vtotal = 272 + 4 + 10 + 2,
d2a6f0f5
JW		 3613};
3614
3615static const struct panel_desc qd43003c0_40 = {
3616 .modes = &qd43003c0_40_mode,
3617 .num_modes = 1,
3618 .bpc = 8,
3619 .size = {
3620 .width = 95,
3621 .height = 53,
3622 },
3623 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3624};
3625
23167fa9
JT		 3626static const struct display_timing rocktech_rk070er9427_timing = {
3627 .pixelclock = { 26400000, 33300000, 46800000 },
3628 .hactive = { 800, 800, 800 },
3629 .hfront_porch = { 16, 210, 354 },
3630 .hback_porch = { 46, 46, 46 },
3631 .hsync_len = { 1, 1, 1 },
3632 .vactive = { 480, 480, 480 },
3633 .vfront_porch = { 7, 22, 147 },
3634 .vback_porch = { 23, 23, 23 },
3635 .vsync_len = { 1, 1, 1 },
3636 .flags = DISPLAY_FLAGS_DE_HIGH,
3637};
3638
3639static const struct panel_desc rocktech_rk070er9427 = {
3640 .timings = &rocktech_rk070er9427_timing,
3641 .num_timings = 1,
3642 .bpc = 6,
3643 .size = {
3644 .width = 154,
3645 .height = 86,
3646 },
3647 .delay = {
3648 .prepare = 41,
3649 .enable = 50,
3650 .unprepare = 41,
3651 .disable = 50,
3652 },
3653 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3654};
3655
f305047b
JS		 3656static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3657 .clock = 71100,
3658 .hdisplay = 1280,
3659 .hsync_start = 1280 + 48,
3660 .hsync_end = 1280 + 48 + 32,
3661 .htotal = 1280 + 48 + 32 + 80,
3662 .vdisplay = 800,
3663 .vsync_start = 800 + 2,
3664 .vsync_end = 800 + 2 + 5,
3665 .vtotal = 800 + 2 + 5 + 16,
f305047b
JS		 3666};
3667
3668static const struct panel_desc rocktech_rk101ii01d_ct = {
3669 .modes = &rocktech_rk101ii01d_ct_mode,
3670 .num_modes = 1,
3671 .size = {
3672 .width = 217,
3673 .height = 136,
3674 },
3675 .delay = {
3676 .prepare = 50,
3677 .disable = 50,
3678 },
3679 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3680 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3681 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3682};
3683
4bfe6c8f
RN		 3684static const struct drm_display_mode samsung_atna33xc20_mode = {
3685 .clock = 138770,
3686 .hdisplay = 1920,
3687 .hsync_start = 1920 + 48,
3688 .hsync_end = 1920 + 48 + 32,
3689 .htotal = 1920 + 48 + 32 + 80,
3690 .vdisplay = 1080,
3691 .vsync_start = 1080 + 8,
3692 .vsync_end = 1080 + 8 + 8,
3693 .vtotal = 1080 + 8 + 8 + 16,
3694 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3695};
3696
3697static const struct panel_desc samsung_atna33xc20 = {
3698 .modes = &samsung_atna33xc20_mode,
3699 .num_modes = 1,
3700 .bpc = 10,
3701 .size = {
3702 .width = 294,
3703 .height = 165,
3704 },
3705 .delay = {
3706 .disable_to_power_off = 200,
3707 .power_to_enable = 400,
3708 .hpd_absent_delay = 200,
3709 .unprepare = 500,
3710 },
3711 .connector_type = DRM_MODE_CONNECTOR_eDP,
3712};
3713
0330eaf3
YY		 3714static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
3715 .clock = 271560,
3716 .hdisplay = 2560,
3717 .hsync_start = 2560 + 48,
3718 .hsync_end = 2560 + 48 + 32,
3719 .htotal = 2560 + 48 + 32 + 80,
3720 .vdisplay = 1600,
3721 .vsync_start = 1600 + 2,
3722 .vsync_end = 1600 + 2 + 5,
3723 .vtotal = 1600 + 2 + 5 + 57,
0330eaf3
YY		 3724};
3725
3726static const struct panel_desc samsung_lsn122dl01_c01 = {
3727 .modes = &samsung_lsn122dl01_c01_mode,
3728 .num_modes = 1,
3729 .size = {
3730 .width = 263,
3731 .height = 164,
3732 },
3733};
3734
6d54e3d2
MD		 3735static const struct drm_display_mode samsung_ltn101nt05_mode = {
3736 .clock = 54030,
3737 .hdisplay = 1024,
3738 .hsync_start = 1024 + 24,
3739 .hsync_end = 1024 + 24 + 136,
3740 .htotal = 1024 + 24 + 136 + 160,
3741 .vdisplay = 600,
3742 .vsync_start = 600 + 3,
3743 .vsync_end = 600 + 3 + 6,
3744 .vtotal = 600 + 3 + 6 + 61,
6d54e3d2
MD		 3745};
3746
3747static const struct panel_desc samsung_ltn101nt05 = {
3748 .modes = &samsung_ltn101nt05_mode,
3749 .num_modes = 1,
0208d511 3750 .bpc = 6,
6d54e3d2 3751 .size = {
81598846
TR		 3752 .width = 223,
3753 .height = 125,
6d54e3d2 3754 },
85560829 3755 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c4715837 3756 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
94f07917 3757 .connector_type = DRM_MODE_CONNECTOR_LVDS,
6d54e3d2
MD		 3758};
3759
0c934306
SM		 3760static const struct drm_display_mode samsung_ltn140at29_301_mode = {
3761 .clock = 76300,
3762 .hdisplay = 1366,
3763 .hsync_start = 1366 + 64,
3764 .hsync_end = 1366 + 64 + 48,
3765 .htotal = 1366 + 64 + 48 + 128,
3766 .vdisplay = 768,
3767 .vsync_start = 768 + 2,
3768 .vsync_end = 768 + 2 + 5,
3769 .vtotal = 768 + 2 + 5 + 17,
0c934306
SM		 3770};
3771
3772static const struct panel_desc samsung_ltn140at29_301 = {
3773 .modes = &samsung_ltn140at29_301_mode,
3774 .num_modes = 1,
3775 .bpc = 6,
3776 .size = {
3777 .width = 320,
3778 .height = 187,
3779 },
3780};
3781
44c58c52
MR		 3782static const struct display_timing satoz_sat050at40h12r2_timing = {
3783 .pixelclock = {33300000, 33300000, 50000000},
3784 .hactive = {800, 800, 800},
3785 .hfront_porch = {16, 210, 354},
3786 .hback_porch = {46, 46, 46},
3787 .hsync_len = {1, 1, 40},
3788 .vactive = {480, 480, 480},
3789 .vfront_porch = {7, 22, 147},
3790 .vback_porch = {23, 23, 23},
3791 .vsync_len = {1, 1, 20},
3792};
3793
3794static const struct panel_desc satoz_sat050at40h12r2 = {
3795 .timings = &satoz_sat050at40h12r2_timing,
3796 .num_timings = 1,
3797 .bpc = 8,
3798 .size = {
3799 .width = 108,
3800 .height = 65,
3801 },
34ca6b53 3802 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
44c58c52
MR		 3803 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3804};
3805
cd5e1cbe
JH		 3806static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
3807 .clock = 168480,
3808 .hdisplay = 1920,
3809 .hsync_start = 1920 + 48,
3810 .hsync_end = 1920 + 48 + 32,
3811 .htotal = 1920 + 48 + 32 + 80,
3812 .vdisplay = 1280,
3813 .vsync_start = 1280 + 3,
3814 .vsync_end = 1280 + 3 + 10,
3815 .vtotal = 1280 + 3 + 10 + 57,
cd5e1cbe
JH		 3816 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3817};
3818
3819static const struct panel_desc sharp_ld_d5116z01b = {
3820 .modes = &sharp_ld_d5116z01b_mode,
3821 .num_modes = 1,
3822 .bpc = 8,
3823 .size = {
3824 .width = 260,
3825 .height = 120,
3826 },
3827 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3828 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
3829};
3830
dda0e4bd
NS		 3831static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3832 .clock = 33260,
3833 .hdisplay = 800,
3834 .hsync_start = 800 + 64,
3835 .hsync_end = 800 + 64 + 128,
3836 .htotal = 800 + 64 + 128 + 64,
3837 .vdisplay = 480,
3838 .vsync_start = 480 + 8,
3839 .vsync_end = 480 + 8 + 2,
3840 .vtotal = 480 + 8 + 2 + 35,
dda0e4bd
NS		 3841 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3842};
3843
3844static const struct panel_desc sharp_lq070y3dg3b = {
3845 .modes = &sharp_lq070y3dg3b_mode,
3846 .num_modes = 1,
3847 .bpc = 8,
3848 .size = {
3849 .width = 152, /* 152.4mm */
3850 .height = 91, /* 91.4mm */
3851 },
3852 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 3853 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
dda0e4bd
NS		 3854 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3855};
3856
03e3ec9a
VZ		 3857static const struct drm_display_mode sharp_lq035q7db03_mode = {
3858 .clock = 5500,
3859 .hdisplay = 240,
3860 .hsync_start = 240 + 16,
3861 .hsync_end = 240 + 16 + 7,
3862 .htotal = 240 + 16 + 7 + 5,
3863 .vdisplay = 320,
3864 .vsync_start = 320 + 9,
3865 .vsync_end = 320 + 9 + 1,
3866 .vtotal = 320 + 9 + 1 + 7,
03e3ec9a
VZ		 3867};
3868
3869static const struct panel_desc sharp_lq035q7db03 = {
3870 .modes = &sharp_lq035q7db03_mode,
3871 .num_modes = 1,
3872 .bpc = 6,
3873 .size = {
3874 .width = 54,
3875 .height = 72,
3876 },
3877 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3878};
3879
592aa02b
JC		 3880static const struct display_timing sharp_lq101k1ly04_timing = {
3881 .pixelclock = { 60000000, 65000000, 80000000 },
3882 .hactive = { 1280, 1280, 1280 },
3883 .hfront_porch = { 20, 20, 20 },
3884 .hback_porch = { 20, 20, 20 },
3885 .hsync_len = { 10, 10, 10 },
3886 .vactive = { 800, 800, 800 },
3887 .vfront_porch = { 4, 4, 4 },
3888 .vback_porch = { 4, 4, 4 },
3889 .vsync_len = { 4, 4, 4 },
3890 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3891};
3892
3893static const struct panel_desc sharp_lq101k1ly04 = {
3894 .timings = &sharp_lq101k1ly04_timing,
3895 .num_timings = 1,
3896 .bpc = 8,
3897 .size = {
3898 .width = 217,
3899 .height = 136,
3900 },
3901 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
9a2654c0 3902 .connector_type = DRM_MODE_CONNECTOR_LVDS,
592aa02b
JC		 3903};
3904
9f7bae2d
SP		 3905static const struct display_timing sharp_lq123p1jx31_timing = {
3906 .pixelclock = { 252750000, 252750000, 266604720 },
3907 .hactive = { 2400, 2400, 2400 },
3908 .hfront_porch = { 48, 48, 48 },
3909 .hback_porch = { 80, 80, 84 },
3910 .hsync_len = { 32, 32, 32 },
3911 .vactive = { 1600, 1600, 1600 },
3912 .vfront_porch = { 3, 3, 3 },
3913 .vback_porch = { 33, 33, 120 },
3914 .vsync_len = { 10, 10, 10 },
3915 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
739c7de9
YY		 3916};
3917
3918static const struct panel_desc sharp_lq123p1jx31 = {
9f7bae2d
SP		 3919 .timings = &sharp_lq123p1jx31_timing,
3920 .num_timings = 1,
5466a631 3921 .bpc = 8,
739c7de9
YY		 3922 .size = {
3923 .width = 259,
3924 .height = 173,
3925 },
a42f6e3f
YY		 3926 .delay = {
3927 .prepare = 110,
3928 .enable = 50,
3929 .unprepare = 550,
3930 },
739c7de9
YY		 3931};
3932
656b7596 3933static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
e6c21e6f
PC		 3934 { /* 50 Hz */
3935 .clock = 3000,
3936 .hdisplay = 240,
3937 .hsync_start = 240 + 58,
3938 .hsync_end = 240 + 58 + 1,
3939 .htotal = 240 + 58 + 1 + 1,
3940 .vdisplay = 160,
3941 .vsync_start = 160 + 24,
3942 .vsync_end = 160 + 24 + 10,
3943 .vtotal = 160 + 24 + 10 + 6,
3944 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3945 },
656b7596 3946 { /* 60 Hz */
c1bd32b5 3947 .clock = 3000,
656b7596 3948 .hdisplay = 240,
c1bd32b5
PC		 3949 .hsync_start = 240 + 8,
3950 .hsync_end = 240 + 8 + 1,
3951 .htotal = 240 + 8 + 1 + 1,
656b7596 3952 .vdisplay = 160,
c1bd32b5
PC		 3953 .vsync_start = 160 + 24,
3954 .vsync_end = 160 + 24 + 10,
3955 .vtotal = 160 + 24 + 10 + 6,
656b7596
PC		 3956 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3957 },
f1bd37f3
PC		 3958};
3959
3960static const struct panel_desc sharp_ls020b1dd01d = {
656b7596
PC		 3961 .modes = sharp_ls020b1dd01d_modes,
3962 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
f1bd37f3
PC		 3963 .bpc = 6,
3964 .size = {
3965 .width = 42,
3966 .height = 28,
3967 },
3968 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3969 .bus_flags = DRM_BUS_FLAG_DE_HIGH
f5436f77 3970 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
f1bd37f3
PC		 3971 | DRM_BUS_FLAG_SHARP_SIGNALS,
3972};
3973
9c6615bc
BB		 3974static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3975 .clock = 33300,
3976 .hdisplay = 800,
3977 .hsync_start = 800 + 1,
3978 .hsync_end = 800 + 1 + 64,
3979 .htotal = 800 + 1 + 64 + 64,
3980 .vdisplay = 480,
3981 .vsync_start = 480 + 1,
3982 .vsync_end = 480 + 1 + 23,
3983 .vtotal = 480 + 1 + 23 + 22,
9c6615bc
BB		 3984};
3985
3986static const struct panel_desc shelly_sca07010_bfn_lnn = {
3987 .modes = &shelly_sca07010_bfn_lnn_mode,
3988 .num_modes = 1,
3989 .size = {
3990 .width = 152,
3991 .height = 91,
3992 },
3993 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3994};
3995
105235e4
PR		 3996static const struct drm_display_mode starry_kr070pe2t_mode = {
3997 .clock = 33000,
3998 .hdisplay = 800,
3999 .hsync_start = 800 + 209,
4000 .hsync_end = 800 + 209 + 1,
4001 .htotal = 800 + 209 + 1 + 45,
4002 .vdisplay = 480,
4003 .vsync_start = 480 + 22,
4004 .vsync_end = 480 + 22 + 1,
4005 .vtotal = 480 + 22 + 1 + 22,
105235e4
PR		 4006};
4007
4008static const struct panel_desc starry_kr070pe2t = {
4009 .modes = &starry_kr070pe2t_mode,
4010 .num_modes = 1,
4011 .bpc = 8,
4012 .size = {
4013 .width = 152,
4014 .height = 86,
4015 },
4016 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4017 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
41fad307 4018 .connector_type = DRM_MODE_CONNECTOR_DPI,
105235e4
PR		 4019};
4020
9bb34c4c
DA		 4021static const struct drm_display_mode starry_kr122ea0sra_mode = {
4022 .clock = 147000,
4023 .hdisplay = 1920,
4024 .hsync_start = 1920 + 16,
4025 .hsync_end = 1920 + 16 + 16,
4026 .htotal = 1920 + 16 + 16 + 32,
4027 .vdisplay = 1200,
4028 .vsync_start = 1200 + 15,
4029 .vsync_end = 1200 + 15 + 2,
4030 .vtotal = 1200 + 15 + 2 + 18,
9bb34c4c
DA		 4031 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4032};
4033
4034static const struct panel_desc starry_kr122ea0sra = {
4035 .modes = &starry_kr122ea0sra_mode,
4036 .num_modes = 1,
4037 .size = {
4038 .width = 263,
4039 .height = 164,
4040 },
c46b924b
BN		 4041 .delay = {
4042 .prepare = 10 + 200,
4043 .enable = 50,
4044 .unprepare = 10 + 500,
4045 },
9bb34c4c
DA		 4046};
4047
42161531
JS		 4048static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
4049 .clock = 30000,
4050 .hdisplay = 800,
4051 .hsync_start = 800 + 39,
4052 .hsync_end = 800 + 39 + 47,
4053 .htotal = 800 + 39 + 47 + 39,
4054 .vdisplay = 480,
4055 .vsync_start = 480 + 13,
4056 .vsync_end = 480 + 13 + 2,
4057 .vtotal = 480 + 13 + 2 + 29,
42161531
JS		 4058};
4059
4060static const struct panel_desc tfc_s9700rtwv43tr_01b = {
4061 .modes = &tfc_s9700rtwv43tr_01b_mode,
4062 .num_modes = 1,
4063 .bpc = 8,
4064 .size = {
4065 .width = 155,
4066 .height = 90,
4067 },
4068 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
42161531
JS		 4070};
4071
adb973ef
GB		 4072static const struct display_timing tianma_tm070jdhg30_timing = {
4073 .pixelclock = { 62600000, 68200000, 78100000 },
4074 .hactive = { 1280, 1280, 1280 },
4075 .hfront_porch = { 15, 64, 159 },
4076 .hback_porch = { 5, 5, 5 },
4077 .hsync_len = { 1, 1, 256 },
4078 .vactive = { 800, 800, 800 },
4079 .vfront_porch = { 3, 40, 99 },
4080 .vback_porch = { 2, 2, 2 },
4081 .vsync_len = { 1, 1, 128 },
4082 .flags = DISPLAY_FLAGS_DE_HIGH,
4083};
4084
4085static const struct panel_desc tianma_tm070jdhg30 = {
4086 .timings = &tianma_tm070jdhg30_timing,
4087 .num_timings = 1,
4088 .bpc = 8,
4089 .size = {
4090 .width = 151,
4091 .height = 95,
4092 },
4093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 4094 .connector_type = DRM_MODE_CONNECTOR_LVDS,
adb973ef
GB		 4095};
4096
b3bfcdf8
MM		 4097static const struct panel_desc tianma_tm070jvhg33 = {
4098 .timings = &tianma_tm070jdhg30_timing,
4099 .num_timings = 1,
4100 .bpc = 8,
4101 .size = {
4102 .width = 150,
4103 .height = 94,
4104 },
4105 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4106 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4107};
4108
870a0b12
LM		 4109static const struct display_timing tianma_tm070rvhg71_timing = {
4110 .pixelclock = { 27700000, 29200000, 39600000 },
4111 .hactive = { 800, 800, 800 },
4112 .hfront_porch = { 12, 40, 212 },
4113 .hback_porch = { 88, 88, 88 },
4114 .hsync_len = { 1, 1, 40 },
4115 .vactive = { 480, 480, 480 },
4116 .vfront_porch = { 1, 13, 88 },
4117 .vback_porch = { 32, 32, 32 },
4118 .vsync_len = { 1, 1, 3 },
4119 .flags = DISPLAY_FLAGS_DE_HIGH,
4120};
4121
4122static const struct panel_desc tianma_tm070rvhg71 = {
4123 .timings = &tianma_tm070rvhg71_timing,
4124 .num_timings = 1,
4125 .bpc = 8,
4126 .size = {
4127 .width = 154,
4128 .height = 86,
4129 },
4130 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
9a2654c0 4131 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870a0b12
LM		 4132};
4133
d8a0d6a3
LW		 4134static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
4135 {
4136 .clock = 10000,
4137 .hdisplay = 320,
4138 .hsync_start = 320 + 50,
4139 .hsync_end = 320 + 50 + 6,
4140 .htotal = 320 + 50 + 6 + 38,
4141 .vdisplay = 240,
4142 .vsync_start = 240 + 3,
4143 .vsync_end = 240 + 3 + 1,
4144 .vtotal = 240 + 3 + 1 + 17,
d8a0d6a3
LW		 4145 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4146 },
4147};
4148
4149static const struct panel_desc ti_nspire_cx_lcd_panel = {
4150 .modes = ti_nspire_cx_lcd_mode,
4151 .num_modes = 1,
4152 .bpc = 8,
4153 .size = {
4154 .width = 65,
4155 .height = 49,
4156 },
4157 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4158 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
d8a0d6a3
LW		 4159};
4160
4161static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
4162 {
4163 .clock = 10000,
4164 .hdisplay = 320,
4165 .hsync_start = 320 + 6,
4166 .hsync_end = 320 + 6 + 6,
4167 .htotal = 320 + 6 + 6 + 6,
4168 .vdisplay = 240,
4169 .vsync_start = 240 + 0,
4170 .vsync_end = 240 + 0 + 1,
4171 .vtotal = 240 + 0 + 1 + 0,
d8a0d6a3
LW		 4172 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4173 },
4174};
4175
4176static const struct panel_desc ti_nspire_classic_lcd_panel = {
4177 .modes = ti_nspire_classic_lcd_mode,
4178 .num_modes = 1,
4179 /* The grayscale panel has 8 bit for the color .. Y (black) */
4180 .bpc = 8,
4181 .size = {
4182 .width = 71,
4183 .height = 53,
4184 },
4185 /* This is the grayscale bus format */
4186 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
f5436f77 4187 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
d8a0d6a3
LW		 4188};
4189
06e733e4
LS		 4190static const struct drm_display_mode toshiba_lt089ac29000_mode = {
4191 .clock = 79500,
4192 .hdisplay = 1280,
4193 .hsync_start = 1280 + 192,
4194 .hsync_end = 1280 + 192 + 128,
4195 .htotal = 1280 + 192 + 128 + 64,
4196 .vdisplay = 768,
4197 .vsync_start = 768 + 20,
4198 .vsync_end = 768 + 20 + 7,
4199 .vtotal = 768 + 20 + 7 + 3,
06e733e4
LS		 4200};
4201
4202static const struct panel_desc toshiba_lt089ac29000 = {
4203 .modes = &toshiba_lt089ac29000_mode,
4204 .num_modes = 1,
4205 .size = {
4206 .width = 194,
4207 .height = 116,
4208 },
9781bd1d 4209 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
c4715837 4210 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
9a2654c0 4211 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06e733e4
LS		 4212};
4213
227e4f40
BD		 4214static const struct drm_display_mode tpk_f07a_0102_mode = {
4215 .clock = 33260,
4216 .hdisplay = 800,
4217 .hsync_start = 800 + 40,
4218 .hsync_end = 800 + 40 + 128,
4219 .htotal = 800 + 40 + 128 + 88,
4220 .vdisplay = 480,
4221 .vsync_start = 480 + 10,
4222 .vsync_end = 480 + 10 + 2,
4223 .vtotal = 480 + 10 + 2 + 33,
227e4f40
BD		 4224};
4225
4226static const struct panel_desc tpk_f07a_0102 = {
4227 .modes = &tpk_f07a_0102_mode,
4228 .num_modes = 1,
4229 .size = {
4230 .width = 152,
4231 .height = 91,
4232 },
88bc4178 4233 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
227e4f40
BD		 4234};
4235
4236static const struct drm_display_mode tpk_f10a_0102_mode = {
4237 .clock = 45000,
4238 .hdisplay = 1024,
4239 .hsync_start = 1024 + 176,
4240 .hsync_end = 1024 + 176 + 5,
4241 .htotal = 1024 + 176 + 5 + 88,
4242 .vdisplay = 600,
4243 .vsync_start = 600 + 20,
4244 .vsync_end = 600 + 20 + 5,
4245 .vtotal = 600 + 20 + 5 + 25,
227e4f40
BD		 4246};
4247
4248static const struct panel_desc tpk_f10a_0102 = {
4249 .modes = &tpk_f10a_0102_mode,
4250 .num_modes = 1,
4251 .size = {
4252 .width = 223,
4253 .height = 125,
4254 },
4255};
4256
06a9dc65
MS		 4257static const struct display_timing urt_umsh_8596md_timing = {
4258 .pixelclock = { 33260000, 33260000, 33260000 },
4259 .hactive = { 800, 800, 800 },
4260 .hfront_porch = { 41, 41, 41 },
4261 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
4262 .hsync_len = { 71, 128, 128 },
4263 .vactive = { 480, 480, 480 },
4264 .vfront_porch = { 10, 10, 10 },
4265 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4266 .vsync_len = { 2, 2, 2 },
4267 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4268 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4269};
4270
4271static const struct panel_desc urt_umsh_8596md_lvds = {
4272 .timings = &urt_umsh_8596md_timing,
4273 .num_timings = 1,
4274 .bpc = 6,
4275 .size = {
4276 .width = 152,
4277 .height = 91,
4278 },
4279 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
9a2654c0 4280 .connector_type = DRM_MODE_CONNECTOR_LVDS,
06a9dc65
MS		 4281};
4282
4283static const struct panel_desc urt_umsh_8596md_parallel = {
4284 .timings = &urt_umsh_8596md_timing,
4285 .num_timings = 1,
4286 .bpc = 6,
4287 .size = {
4288 .width = 152,
4289 .height = 91,
4290 },
4291 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4292};
4293
04206185
FE		 4294static const struct drm_display_mode vl050_8048nt_c01_mode = {
4295 .clock = 33333,
4296 .hdisplay = 800,
4297 .hsync_start = 800 + 210,
4298 .hsync_end = 800 + 210 + 20,
4299 .htotal = 800 + 210 + 20 + 46,
4300 .vdisplay = 480,
4301 .vsync_start = 480 + 22,
4302 .vsync_end = 480 + 22 + 10,
4303 .vtotal = 480 + 22 + 10 + 23,
04206185
FE		 4304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4305};
4306
4307static const struct panel_desc vl050_8048nt_c01 = {
4308 .modes = &vl050_8048nt_c01_mode,
4309 .num_modes = 1,
4310 .bpc = 8,
4311 .size = {
4312 .width = 120,
4313 .height = 76,
4314 },
4315 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
f5436f77 4316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
04206185
FE		 4317};
4318
e4bac408
RG		 4319static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4320 .clock = 6410,
4321 .hdisplay = 320,
4322 .hsync_start = 320 + 20,
4323 .hsync_end = 320 + 20 + 30,
4324 .htotal = 320 + 20 + 30 + 38,
4325 .vdisplay = 240,
4326 .vsync_start = 240 + 4,
4327 .vsync_end = 240 + 4 + 3,
4328 .vtotal = 240 + 4 + 3 + 15,
e4bac408
RG		 4329 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4330};
4331
4332static const struct panel_desc winstar_wf35ltiacd = {
4333 .modes = &winstar_wf35ltiacd_mode,
4334 .num_modes = 1,
4335 .bpc = 8,
4336 .size = {
4337 .width = 70,
4338 .height = 53,
4339 },
4340 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4341};
4342
7a1f4fa4
JT		 4343static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4344 .clock = 51200,
4345 .hdisplay = 1024,
4346 .hsync_start = 1024 + 100,
4347 .hsync_end = 1024 + 100 + 100,
4348 .htotal = 1024 + 100 + 100 + 120,
4349 .vdisplay = 600,
4350 .vsync_start = 600 + 10,
4351 .vsync_end = 600 + 10 + 10,
4352 .vtotal = 600 + 10 + 10 + 15,
4353 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4354};
4355
4356static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4357 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4358 .num_modes = 1,
4359 .bpc = 6,
4360 .size = {
4361 .width = 154,
4362 .height = 90,
4363 },
4364 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4365 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4366 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4367};
4368
fcec4163
LW		 4369static const struct drm_display_mode arm_rtsm_mode[] = {
4370 {
4371 .clock = 65000,
4372 .hdisplay = 1024,
4373 .hsync_start = 1024 + 24,
4374 .hsync_end = 1024 + 24 + 136,
4375 .htotal = 1024 + 24 + 136 + 160,
4376 .vdisplay = 768,
4377 .vsync_start = 768 + 3,
4378 .vsync_end = 768 + 3 + 6,
4379 .vtotal = 768 + 3 + 6 + 29,
fcec4163
LW		 4380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4381 },
4382};
4383
4384static const struct panel_desc arm_rtsm = {
4385 .modes = arm_rtsm_mode,
4386 .num_modes = 1,
4387 .bpc = 8,
4388 .size = {
4389 .width = 400,
4390 .height = 300,
4391 },
4392 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4393};
4394
280921de
TR		 4395static const struct of_device_id platform_of_match[] = {
4396 {
bca684e6
JT		 4397 .compatible = "ampire,am-1280800n3tzqw-t00h",
4398 .data = &ampire_am_1280800n3tzqw_t00h,
4399 }, {
966fea78
YF		 4400 .compatible = "ampire,am-480272h3tmqw-t01h",
4401 .data = &ampire_am_480272h3tmqw_t01h,
4402 }, {
1c550fa1
PZ		 4403 .compatible = "ampire,am800480r3tmqwa1h",
4404 .data = &ampire_am800480r3tmqwa1h,
fcec4163
LW		 4405 }, {
4406 .compatible = "arm,rtsm-display",
4407 .data = &arm_rtsm,
c479450f
SS		 4408 }, {
4409 .compatible = "armadeus,st0700-adapt",
4410 .data = &armadeus_st0700_adapt,
1c550fa1 4411 }, {
280921de
TR		 4412 .compatible = "auo,b101aw03",
4413 .data = &auo_b101aw03,
a531bc3d
HL		 4414 }, {
4415 .compatible = "auo,b101ean01",
4416 .data = &auo_b101ean01,
dac746e0
RC		 4417 }, {
4418 .compatible = "auo,b101xtn01",
4419 .data = &auo_b101xtn01,
da458286
RC		 4420 }, {
4421 .compatible = "auo,b116xa01",
4422 .data = &auo_b116xak01,
e35e305e
AK		 4423 }, {
4424 .compatible = "auo,b116xw03",
4425 .data = &auo_b116xw03,
93ea7aa8
BA		 4426 }, {
4427 .compatible = "auo,b133han05",
4428 .data = &auo_b133han05,
3e51d609
AK		 4429 }, {
4430 .compatible = "auo,b133htn01",
4431 .data = &auo_b133htn01,
93ea7aa8
BA		 4432 }, {
4433 .compatible = "auo,b140han06",
4434 .data = &auo_b140han06,
a333f7ad
SM		 4435 }, {
4436 .compatible = "auo,b133xtn01",
4437 .data = &auo_b133xtn01,
bccfaffb
LM		 4438 }, {
4439 .compatible = "auo,g070vvn01",
4440 .data = &auo_g070vvn01,
4fb86404
AG		 4441 }, {
4442 .compatible = "auo,g101evn010",
4443 .data = &auo_g101evn010,
4451c287
CF		 4444 }, {
4445 .compatible = "auo,g104sn02",
4446 .data = &auo_g104sn02,
03e909ac
SR		 4447 }, {
4448 .compatible = "auo,g121ean01",
4449 .data = &auo_g121ean01,
697035c6
LS		 4450 }, {
4451 .compatible = "auo,g133han01",
4452 .data = &auo_g133han01,
d9ccd1f2
SR		 4453 }, {
4454 .compatible = "auo,g156xtn01",
4455 .data = &auo_g156xtn01,
8c31f603
LS		 4456 }, {
4457 .compatible = "auo,g185han01",
4458 .data = &auo_g185han01,
2f7b832f
SR		 4459 }, {
4460 .compatible = "auo,g190ean01",
4461 .data = &auo_g190ean01,
70c0d5b7
LS		 4462 }, {
4463 .compatible = "auo,p320hvn03",
4464 .data = &auo_p320hvn03,
7ee933a1
HS		 4465 }, {
4466 .compatible = "auo,t215hvn01",
4467 .data = &auo_t215hvn01,
d47df633
PZ		 4468 }, {
4469 .compatible = "avic,tm070ddh03",
4470 .data = &avic_tm070ddh03,
7ad8b41c
CYT		 4471 }, {
4472 .compatible = "bananapi,s070wv20-ct16",
4473 .data = &bananapi_s070wv20_ct16,
ae8cf41b
AH		 4474 }, {
4475 .compatible = "boe,hv070wsa-100",
4476 .data = &boe_hv070wsa
cac1a411
CW		 4477 }, {
4478 .compatible = "boe,nv101wxmn51",
4479 .data = &boe_nv101wxmn51,
a96ee0f6
DA		 4480 }, {
4481 .compatible = "boe,nv110wtm-n61",
4482 .data = &boe_nv110wtm_n61,
b0c664cc
BA		 4483 }, {
4484 .compatible = "boe,nv133fhm-n61",
4485 .data = &boe_nv133fhm_n61,
cfe40d02
DA		 4486 }, {
4487 .compatible = "boe,nv133fhm-n62",
4488 .data = &boe_nv133fhm_n61,
a5119818
TS		 4489 }, {
4490 .compatible = "boe,nv140fhmn49",
4491 .data = &boe_nv140fhmn49,
e58edce6
GB		 4492 }, {
4493 .compatible = "cdtech,s043wq26h-ct7",
4494 .data = &cdtech_s043wq26h_ct7,
0e3b67f6
MK		 4495 }, {
4496 .compatible = "cdtech,s070pws19hp-fc21",
4497 .data = &cdtech_s070pws19hp_fc21,
4498 }, {
4499 .compatible = "cdtech,s070swv29hg-dc44",
4500 .data = &cdtech_s070swv29hg_dc44,
982f944e
GB		 4501 }, {
4502 .compatible = "cdtech,s070wv95-ct16",
4503 .data = &cdtech_s070wv95_ct16,
07c913c4
MV		 4504 }, {
4505 .compatible = "chefree,ch101olhlwh-002",
4506 .data = &chefree_ch101olhlwh_002,
2cb35c80
RL		 4507 }, {
4508 .compatible = "chunghwa,claa070wp03xg",
4509 .data = &chunghwa_claa070wp03xg,
4c930757
SW		 4510 }, {
4511 .compatible = "chunghwa,claa101wa01a",
4512 .data = &chunghwa_claa101wa01a
280921de
TR		 4513 }, {
4514 .compatible = "chunghwa,claa101wb01",
4515 .data = &chunghwa_claa101wb01
97ceb1fb
MV		 4516 }, {
4517 .compatible = "dataimage,scf0700c48ggu18",
4518 .data = &dataimage_scf0700c48ggu18,
0ca0c827
PZ		 4519 }, {
4520 .compatible = "dlc,dlc0700yzg-1",
4521 .data = &dlc_dlc0700yzg_1,
6cbe7cd1
MF		 4522 }, {
4523 .compatible = "dlc,dlc1010gig",
4524 .data = &dlc_dlc1010gig,
c2d24af6
AP		 4525 }, {
4526 .compatible = "edt,et035012dm6",
4527 .data = &edt_et035012dm6,
f08a2a1e
SR		 4528 }, {
4529 .compatible = "edt,etm0350g0dh6",
4530 .data = &edt_etm0350g0dh6,
82d57a59
MCR		 4531 }, {
4532 .compatible = "edt,etm043080dh6gp",
4533 .data = &edt_etm043080dh6gp,
fd819bff
MV		 4534 }, {
4535 .compatible = "edt,etm0430g0dh6",
4536 .data = &edt_etm0430g0dh6,
26ab0065
SA		 4537 }, {
4538 .compatible = "edt,et057090dhu",
4539 .data = &edt_et057090dhu,
fff5de45
PZ		 4540 }, {
4541 .compatible = "edt,et070080dh6",
4542 .data = &edt_etm0700g0dh6,
4543 }, {
4544 .compatible = "edt,etm0700g0dh6",
4545 .data = &edt_etm0700g0dh6,
aa7e6455
JT		 4546 }, {
4547 .compatible = "edt,etm0700g0bdh6",
4548 .data = &edt_etm0700g0bdh6,
aad34de2
JT		 4549 }, {
4550 .compatible = "edt,etm0700g0edh6",
4551 .data = &edt_etm0700g0bdh6,
e46f73fb
SR		 4552 }, {
4553 .compatible = "edt,etmv570g2dhu",
4554 .data = &edt_etmv570g2dhu,
9158e3c3
MF		 4555 }, {
4556 .compatible = "evervision,vgg804821",
4557 .data = &evervision_vgg804821,
102932b0
BB		 4558 }, {
4559 .compatible = "foxlink,fl500wvr00-a0t",
4560 .data = &foxlink_fl500wvr00_a0t,
7b6bd843
PC		 4561 }, {
4562 .compatible = "frida,frd350h54004",
4563 .data = &frida_frd350h54004,
3be20710
JT		 4564 }, {
4565 .compatible = "friendlyarm,hd702e",
4566 .data = &friendlyarm_hd702e,
d435a2af
PZ		 4567 }, {
4568 .compatible = "giantplus,gpg482739qs5",
4569 .data = &giantplus_gpg482739qs5
2c6574a9
PC		 4570 }, {
4571 .compatible = "giantplus,gpm940b0",
4572 .data = &giantplus_gpm940b0,
a853205e
PZ		 4573 }, {
4574 .compatible = "hannstar,hsd070pww1",
4575 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 4576 }, {
4577 .compatible = "hannstar,hsd100pxn1",
4578 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 4579 }, {
4580 .compatible = "hit,tx23d38vm0caa",
4581 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 4582 }, {
4583 .compatible = "innolux,at043tn24",
4584 .data = &innolux_at043tn24,
4fc24ab3
RB		 4585 }, {
4586 .compatible = "innolux,at070tn92",
4587 .data = &innolux_at070tn92,
1e29b840 4588 }, {
a5d2ade6
CF		 4589 .compatible = "innolux,g070y2-l01",
4590 .data = &innolux_g070y2_l01,
4591 }, {
4592 .compatible = "innolux,g101ice-l01",
1e29b840 4593 .data = &innolux_g101ice_l01
d731f661 4594 }, {
a5d2ade6 4595 .compatible = "innolux,g121i1-l01",
d731f661 4596 .data = &innolux_g121i1_l01
f8fa17ba
AB		 4597 }, {
4598 .compatible = "innolux,g121x1-l03",
4599 .data = &innolux_g121x1_l03,
51d35631
DA		 4600 }, {
4601 .compatible = "innolux,n116bca-ea1",
4602 .data = &innolux_n116bca_ea1,
0a2288c0
TR		 4603 }, {
4604 .compatible = "innolux,n116bge",
4605 .data = &innolux_n116bge,
a14c6b0e
LH		 4606 }, {
4607 .compatible = "innolux,n125hce-gn1",
4608 .data = &innolux_n125hce_gn1,
ea44739d
AB		 4609 }, {
4610 .compatible = "innolux,n156bge-l21",
4611 .data = &innolux_n156bge_l21,
da50bd42 4612 }, {
8f054b6f
DA		 4613 .compatible = "innolux,p120zdg-bf1",
4614 .data = &innolux_p120zdg_bf1,
bccac3f1
MG		 4615 }, {
4616 .compatible = "innolux,zj070na-01p",
4617 .data = &innolux_zj070na_01p,
e1ca5184
BA		 4618 }, {
4619 .compatible = "ivo,m133nwf4-r0",
4620 .data = &ivo_m133nwf4_r0,
fc26a375
DA		 4621 }, {
4622 .compatible = "kingdisplay,kd116n21-30nv-a010",
4623 .data = &kingdisplay_kd116n21_30nv_a010,
14bf60c4
LM		 4624 }, {
4625 .compatible = "koe,tx14d24vm1bpa",
4626 .data = &koe_tx14d24vm1bpa,
8a070524
LY		 4627 }, {
4628 .compatible = "koe,tx26d202vm0bwa",
4629 .data = &koe_tx26d202vm0bwa,
8cfe8341
JT		 4630 }, {
4631 .compatible = "koe,tx31d200vm0baa",
4632 .data = &koe_tx31d200vm0baa,
8def22e5
LS		 4633 }, {
4634 .compatible = "kyo,tcg121xglp",
4635 .data = &kyo_tcg121xglp,
27abdd83
PK		 4636 }, {
4637 .compatible = "lemaker,bl035-rgb-002",
4638 .data = &lemaker_bl035_rgb_002,
dd015002
HS		 4639 }, {
4640 .compatible = "lg,lb070wv8",
4641 .data = &lg_lb070wv8,
c5ece402
YY		 4642 }, {
4643 .compatible = "lg,lp079qx1-sp0v",
4644 .data = &lg_lp079qx1_sp0v,
0355dde2
YY		 4645 }, {
4646 .compatible = "lg,lp097qx1-spa1",
4647 .data = &lg_lp097qx1_spa1,
690d8fa7
JS		 4648 }, {
4649 .compatible = "lg,lp120up1",
4650 .data = &lg_lp120up1,
ec7c5653
TR		 4651 }, {
4652 .compatible = "lg,lp129qe",
4653 .data = &lg_lp129qe,
0d35408a
AF		 4654 }, {
4655 .compatible = "logicpd,type28",
4656 .data = &logicpd_type_28,
5728fe7f
MZ		 4657 }, {
4658 .compatible = "logictechno,lt161010-2nhc",
4659 .data = &logictechno_lt161010_2nh,
4660 }, {
4661 .compatible = "logictechno,lt161010-2nhr",
4662 .data = &logictechno_lt161010_2nh,
4663 }, {
4664 .compatible = "logictechno,lt170410-2whc",
4665 .data = &logictechno_lt170410_2whc,
65c766ca
LM		 4666 }, {
4667 .compatible = "mitsubishi,aa070mc01-ca1",
4668 .data = &mitsubishi_aa070mc01,
01bacc13
LS		 4669 }, {
4670 .compatible = "nec,nl12880bc20-05",
4671 .data = &nec_nl12880bc20_05,
c6e87f91 4672 }, {
4673 .compatible = "nec,nl4827hc19-05b",
4674 .data = &nec_nl4827hc19_05b,
e6c2f066
MR		 4675 }, {
4676 .compatible = "netron-dy,e231732",
4677 .data = &netron_dy_e231732,
258145ea
VK		 4678 }, {
4679 .compatible = "neweast,wjfh116008a",
4680 .data = &neweast_wjfh116008a,
3b39ad7a
TV		 4681 }, {
4682 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4683 .data = &newhaven_nhd_43_480272ef_atxl,
4177fa66
LS		 4684 }, {
4685 .compatible = "nlt,nl192108ac18-02d",
4686 .data = &nlt_nl192108ac18_02d,
05ec0e45
FL		 4687 }, {
4688 .compatible = "nvd,9128",
4689 .data = &nvd_9128,
a99fb626
GB		 4690 }, {
4691 .compatible = "okaya,rs800480t-7x0gp",
4692 .data = &okaya_rs800480t_7x0gp,
cf5c9e6d
MR		 4693 }, {
4694 .compatible = "olimex,lcd-olinuxino-43-ts",
4695 .data = &olimex_lcd_olinuxino_43ts,
e8b6f561
EA		 4696 }, {
4697 .compatible = "ontat,yx700wv03",
4698 .data = &ontat_yx700wv03,
9c31dcb6
NS		 4699 }, {
4700 .compatible = "ortustech,com37h3m05dtc",
4701 .data = &ortustech_com37h3m,
4702 }, {
4703 .compatible = "ortustech,com37h3m99dtc",
4704 .data = &ortustech_com37h3m,
725c9d40
PZ		 4705 }, {
4706 .compatible = "ortustech,com43h4m85ulc",
4707 .data = &ortustech_com43h4m85ulc,
163f7a35
LP		 4708 }, {
4709 .compatible = "osddisplays,osd070t1718-19ts",
4710 .data = &osddisplays_osd070t1718_19ts,
4ba3e563
EH		 4711 }, {
4712 .compatible = "pda,91-00156-a0",
4713 .data = &pda_91_00156_a0,
d69de69f
MV		 4714 }, {
4715 .compatible = "powertip,ph800480t013-idf02",
4716 .data = &powertip_ph800480t013_idf02,
d2a6f0f5
JW		 4717 }, {
4718 .compatible = "qiaodian,qd43003c0-40",
4719 .data = &qd43003c0_40,
23167fa9
JT		 4720 }, {
4721 .compatible = "rocktech,rk070er9427",
4722 .data = &rocktech_rk070er9427,
f305047b
JS		 4723 }, {
4724 .compatible = "rocktech,rk101ii01d-ct",
4725 .data = &rocktech_rk101ii01d_ct,
4bfe6c8f
RN		 4726 }, {
4727 .compatible = "samsung,atna33xc20",
4728 .data = &samsung_atna33xc20,
0330eaf3
YY		 4729 }, {
4730 .compatible = "samsung,lsn122dl01-c01",
4731 .data = &samsung_lsn122dl01_c01,
6d54e3d2
MD		 4732 }, {
4733 .compatible = "samsung,ltn101nt05",
4734 .data = &samsung_ltn101nt05,
0c934306
SM		 4735 }, {
4736 .compatible = "samsung,ltn140at29-301",
4737 .data = &samsung_ltn140at29_301,
44c58c52
MR		 4738 }, {
4739 .compatible = "satoz,sat050at40h12r2",
4740 .data = &satoz_sat050at40h12r2,
cd5e1cbe
JH		 4741 }, {
4742 .compatible = "sharp,ld-d5116z01b",
4743 .data = &sharp_ld_d5116z01b,
03e3ec9a
VZ		 4744 }, {
4745 .compatible = "sharp,lq035q7db03",
4746 .data = &sharp_lq035q7db03,
dda0e4bd
NS		 4747 }, {
4748 .compatible = "sharp,lq070y3dg3b",
4749 .data = &sharp_lq070y3dg3b,
592aa02b
JC		 4750 }, {
4751 .compatible = "sharp,lq101k1ly04",
4752 .data = &sharp_lq101k1ly04,
739c7de9
YY		 4753 }, {
4754 .compatible = "sharp,lq123p1jx31",
4755 .data = &sharp_lq123p1jx31,
f1bd37f3
PC		 4756 }, {
4757 .compatible = "sharp,ls020b1dd01d",
4758 .data = &sharp_ls020b1dd01d,
9c6615bc
BB		 4759 }, {
4760 .compatible = "shelly,sca07010-bfn-lnn",
4761 .data = &shelly_sca07010_bfn_lnn,
105235e4
PR		 4762 }, {
4763 .compatible = "starry,kr070pe2t",
4764 .data = &starry_kr070pe2t,
9bb34c4c
DA		 4765 }, {
4766 .compatible = "starry,kr122ea0sra",
4767 .data = &starry_kr122ea0sra,
42161531
JS		 4768 }, {
4769 .compatible = "tfc,s9700rtwv43tr-01b",
4770 .data = &tfc_s9700rtwv43tr_01b,
adb973ef
GB		 4771 }, {
4772 .compatible = "tianma,tm070jdhg30",
4773 .data = &tianma_tm070jdhg30,
b3bfcdf8
MM		 4774 }, {
4775 .compatible = "tianma,tm070jvhg33",
4776 .data = &tianma_tm070jvhg33,
870a0b12
LM		 4777 }, {
4778 .compatible = "tianma,tm070rvhg71",
4779 .data = &tianma_tm070rvhg71,
d8a0d6a3
LW		 4780 }, {
4781 .compatible = "ti,nspire-cx-lcd-panel",
4782 .data = &ti_nspire_cx_lcd_panel,
4783 }, {
4784 .compatible = "ti,nspire-classic-lcd-panel",
4785 .data = &ti_nspire_classic_lcd_panel,
06e733e4
LS		 4786 }, {
4787 .compatible = "toshiba,lt089ac29000",
4788 .data = &toshiba_lt089ac29000,
227e4f40
BD		 4789 }, {
4790 .compatible = "tpk,f07a-0102",
4791 .data = &tpk_f07a_0102,
4792 }, {
4793 .compatible = "tpk,f10a-0102",
4794 .data = &tpk_f10a_0102,
06a9dc65
MS		 4795 }, {
4796 .compatible = "urt,umsh-8596md-t",
4797 .data = &urt_umsh_8596md_parallel,
4798 }, {
4799 .compatible = "urt,umsh-8596md-1t",
4800 .data = &urt_umsh_8596md_parallel,
4801 }, {
4802 .compatible = "urt,umsh-8596md-7t",
4803 .data = &urt_umsh_8596md_parallel,
4804 }, {
4805 .compatible = "urt,umsh-8596md-11t",
4806 .data = &urt_umsh_8596md_lvds,
4807 }, {
4808 .compatible = "urt,umsh-8596md-19t",
4809 .data = &urt_umsh_8596md_lvds,
4810 }, {
4811 .compatible = "urt,umsh-8596md-20t",
4812 .data = &urt_umsh_8596md_parallel,
04206185
FE		 4813 }, {
4814 .compatible = "vxt,vl050-8048nt-c01",
4815 .data = &vl050_8048nt_c01,
e4bac408
RG		 4816 }, {
4817 .compatible = "winstar,wf35ltiacd",
4818 .data = &winstar_wf35ltiacd,
7a1f4fa4
JT		 4819 }, {
4820 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4821 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4a1d0dbc
SR		 4822 }, {
4823 /* Must be the last entry */
4824 .compatible = "panel-dpi",
4825 .data = &panel_dpi,
280921de
TR		 4826 }, {
4827 /* sentinel */
4828 }
4829};
4830MODULE_DEVICE_TABLE(of, platform_of_match);
4831
4832static int panel_simple_platform_probe(struct platform_device *pdev)
4833{
4834 const struct of_device_id *id;
4835
4836 id = of_match_node(platform_of_match, pdev->dev.of_node);
4837 if (!id)
4838 return -ENODEV;
4839
cc5a3fc0 4840 return panel_simple_probe(&pdev->dev, id->data, NULL);
280921de
TR		 4841}
4842
4843static int panel_simple_platform_remove(struct platform_device *pdev)
4844{
4845 return panel_simple_remove(&pdev->dev);
4846}
4847
d02fd93e
TR		 4848static void panel_simple_platform_shutdown(struct platform_device *pdev)
4849{
4850 panel_simple_shutdown(&pdev->dev);
4851}
4852
3235b0f2
DA		 4853static const struct dev_pm_ops panel_simple_pm_ops = {
4854 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4855 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4856 pm_runtime_force_resume)
4857};
4858
280921de
TR		 4859static struct platform_driver panel_simple_platform_driver = {
4860 .driver = {
4861 .name = "panel-simple",
280921de 4862 .of_match_table = platform_of_match,
3235b0f2 4863 .pm = &panel_simple_pm_ops,
280921de
TR		 4864 },
4865 .probe = panel_simple_platform_probe,
4866 .remove = panel_simple_platform_remove,
d02fd93e 4867 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 4868};
4869
210fcd9d
TR		 4870struct panel_desc_dsi {
4871 struct panel_desc desc;
4872
462658b8 4873 unsigned long flags;
210fcd9d
TR		 4874 enum mipi_dsi_pixel_format format;
4875 unsigned int lanes;
4876};
4877
d718d79e
TR		 4878static const struct drm_display_mode auo_b080uan01_mode = {
4879 .clock = 154500,
4880 .hdisplay = 1200,
4881 .hsync_start = 1200 + 62,
4882 .hsync_end = 1200 + 62 + 4,
4883 .htotal = 1200 + 62 + 4 + 62,
4884 .vdisplay = 1920,
4885 .vsync_start = 1920 + 9,
4886 .vsync_end = 1920 + 9 + 2,
4887 .vtotal = 1920 + 9 + 2 + 8,
d718d79e
TR		 4888};
4889
4890static const struct panel_desc_dsi auo_b080uan01 = {
4891 .desc = {
4892 .modes = &auo_b080uan01_mode,
4893 .num_modes = 1,
4894 .bpc = 8,
4895 .size = {
4896 .width = 108,
4897 .height = 272,
4898 },
cb62cdec 4899 .connector_type = DRM_MODE_CONNECTOR_DSI,
d718d79e
TR		 4900 },
4901 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4902 .format = MIPI_DSI_FMT_RGB888,
4903 .lanes = 4,
4904};
4905
c8521969
CZ		 4906static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4907 .clock = 160000,
4908 .hdisplay = 1200,
4909 .hsync_start = 1200 + 120,
4910 .hsync_end = 1200 + 120 + 20,
4911 .htotal = 1200 + 120 + 20 + 21,
4912 .vdisplay = 1920,
4913 .vsync_start = 1920 + 21,
4914 .vsync_end = 1920 + 21 + 3,
4915 .vtotal = 1920 + 21 + 3 + 18,
c8521969
CZ		 4916 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4917};
4918
4919static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4920 .desc = {
4921 .modes = &boe_tv080wum_nl0_mode,
4922 .num_modes = 1,
4923 .size = {
4924 .width = 107,
4925 .height = 172,
4926 },
cb62cdec 4927 .connector_type = DRM_MODE_CONNECTOR_DSI,
c8521969
CZ		 4928 },
4929 .flags = MIPI_DSI_MODE_VIDEO |
4930 MIPI_DSI_MODE_VIDEO_BURST |
4931 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4932 .format = MIPI_DSI_FMT_RGB888,
4933 .lanes = 4,
4934};
4935
712ac1ba
AC		 4936static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4937 .clock = 71000,
4938 .hdisplay = 800,
4939 .hsync_start = 800 + 32,
4940 .hsync_end = 800 + 32 + 1,
4941 .htotal = 800 + 32 + 1 + 57,
4942 .vdisplay = 1280,
4943 .vsync_start = 1280 + 28,
4944 .vsync_end = 1280 + 28 + 1,
4945 .vtotal = 1280 + 28 + 1 + 14,
712ac1ba
AC		 4946};
4947
4948static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4949 .desc = {
4950 .modes = &lg_ld070wx3_sl01_mode,
4951 .num_modes = 1,
d7a839cd 4952 .bpc = 8,
712ac1ba
AC		 4953 .size = {
4954 .width = 94,
4955 .height = 151,
4956 },
cb62cdec 4957 .connector_type = DRM_MODE_CONNECTOR_DSI,
712ac1ba 4958 },
5e4cc278 4959 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 4960 .format = MIPI_DSI_FMT_RGB888,
4961 .lanes = 4,
4962};
4963
499ce85a
AC		 4964static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4965 .clock = 67000,
4966 .hdisplay = 720,
4967 .hsync_start = 720 + 12,
4968 .hsync_end = 720 + 12 + 4,
4969 .htotal = 720 + 12 + 4 + 112,
4970 .vdisplay = 1280,
4971 .vsync_start = 1280 + 8,
4972 .vsync_end = 1280 + 8 + 4,
4973 .vtotal = 1280 + 8 + 4 + 12,
499ce85a
AC		 4974};
4975
4976static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4977 .desc = {
4978 .modes = &lg_lh500wx1_sd03_mode,
4979 .num_modes = 1,
d7a839cd 4980 .bpc = 8,
499ce85a
AC		 4981 .size = {
4982 .width = 62,
4983 .height = 110,
4984 },
cb62cdec 4985 .connector_type = DRM_MODE_CONNECTOR_DSI,
499ce85a
AC		 4986 },
4987 .flags = MIPI_DSI_MODE_VIDEO,
4988 .format = MIPI_DSI_FMT_RGB888,
4989 .lanes = 4,
4990};
4991
280921de
TR		 4992static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4993 .clock = 157200,
4994 .hdisplay = 1920,
4995 .hsync_start = 1920 + 154,
4996 .hsync_end = 1920 + 154 + 16,
4997 .htotal = 1920 + 154 + 16 + 32,
4998 .vdisplay = 1200,
4999 .vsync_start = 1200 + 17,
5000 .vsync_end = 1200 + 17 + 2,
5001 .vtotal = 1200 + 17 + 2 + 16,
280921de
TR		 5002};
5003
210fcd9d
TR		 5004static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
5005 .desc = {
5006 .modes = &panasonic_vvx10f004b00_mode,
5007 .num_modes = 1,
d7a839cd 5008 .bpc = 8,
210fcd9d
TR		 5009 .size = {
5010 .width = 217,
5011 .height = 136,
5012 },
cb62cdec 5013 .connector_type = DRM_MODE_CONNECTOR_DSI,
280921de 5014 },
5e4cc278
AC		 5015 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5016 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 5017 .format = MIPI_DSI_FMT_RGB888,
5018 .lanes = 4,
5019};
5020
debcd8f9
JM		 5021static const struct drm_display_mode lg_acx467akm_7_mode = {
5022 .clock = 150000,
5023 .hdisplay = 1080,
5024 .hsync_start = 1080 + 2,
5025 .hsync_end = 1080 + 2 + 2,
5026 .htotal = 1080 + 2 + 2 + 2,
5027 .vdisplay = 1920,
5028 .vsync_start = 1920 + 2,
5029 .vsync_end = 1920 + 2 + 2,
5030 .vtotal = 1920 + 2 + 2 + 2,
debcd8f9
JM		 5031};
5032
5033static const struct panel_desc_dsi lg_acx467akm_7 = {
5034 .desc = {
5035 .modes = &lg_acx467akm_7_mode,
5036 .num_modes = 1,
5037 .bpc = 8,
5038 .size = {
5039 .width = 62,
5040 .height = 110,
5041 },
cb62cdec 5042 .connector_type = DRM_MODE_CONNECTOR_DSI,
debcd8f9
JM		 5043 },
5044 .flags = 0,
5045 .format = MIPI_DSI_FMT_RGB888,
5046 .lanes = 4,
5047};
5048
62967232
PU		 5049static const struct drm_display_mode osd101t2045_53ts_mode = {
5050 .clock = 154500,
5051 .hdisplay = 1920,
5052 .hsync_start = 1920 + 112,
5053 .hsync_end = 1920 + 112 + 16,
5054 .htotal = 1920 + 112 + 16 + 32,
5055 .vdisplay = 1200,
5056 .vsync_start = 1200 + 16,
5057 .vsync_end = 1200 + 16 + 2,
5058 .vtotal = 1200 + 16 + 2 + 16,
62967232
PU		 5059 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
5060};
5061
5062static const struct panel_desc_dsi osd101t2045_53ts = {
5063 .desc = {
5064 .modes = &osd101t2045_53ts_mode,
5065 .num_modes = 1,
5066 .bpc = 8,
5067 .size = {
5068 .width = 217,
5069 .height = 136,
5070 },
cb62cdec 5071 .connector_type = DRM_MODE_CONNECTOR_DSI,
62967232
PU		 5072 },
5073 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
5074 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
5075 MIPI_DSI_MODE_EOT_PACKET,
5076 .format = MIPI_DSI_FMT_RGB888,
5077 .lanes = 4,
5078};
5079
210fcd9d
TR		 5080static const struct of_device_id dsi_of_match[] = {
5081 {
d718d79e
TR		 5082 .compatible = "auo,b080uan01",
5083 .data = &auo_b080uan01
c8521969
CZ		 5084 }, {
5085 .compatible = "boe,tv080wum-nl0",
5086 .data = &boe_tv080wum_nl0
d718d79e 5087 }, {
712ac1ba
AC		 5088 .compatible = "lg,ld070wx3-sl01",
5089 .data = &lg_ld070wx3_sl01
5090 }, {
499ce85a
AC		 5091 .compatible = "lg,lh500wx1-sd03",
5092 .data = &lg_lh500wx1_sd03
5093 }, {
210fcd9d
TR		 5094 .compatible = "panasonic,vvx10f004b00",
5095 .data = &panasonic_vvx10f004b00
debcd8f9
JM		 5096 }, {
5097 .compatible = "lg,acx467akm-7",
5098 .data = &lg_acx467akm_7
62967232
PU		 5099 }, {
5100 .compatible = "osddisplays,osd101t2045-53ts",
5101 .data = &osd101t2045_53ts
210fcd9d
TR		 5102 }, {
5103 /* sentinel */
5104 }
5105};
5106MODULE_DEVICE_TABLE(of, dsi_of_match);
5107
5108static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
5109{
5110 const struct panel_desc_dsi *desc;
5111 const struct of_device_id *id;
5112 int err;
5113
5114 id = of_match_node(dsi_of_match, dsi->dev.of_node);
5115 if (!id)
5116 return -ENODEV;
5117
5118 desc = id->data;
5119
cc5a3fc0 5120 err = panel_simple_probe(&dsi->dev, &desc->desc, NULL);
210fcd9d
TR		 5121 if (err < 0)
5122 return err;
5123
462658b8 5124 dsi->mode_flags = desc->flags;
210fcd9d
TR		 5125 dsi->format = desc->format;
5126 dsi->lanes = desc->lanes;
5127
7ad9db66
PU		 5128 err = mipi_dsi_attach(dsi);
5129 if (err) {
5dd331d4 5130 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
7ad9db66
PU		 5131
5132 drm_panel_remove(&panel->base);
5133 }
5134
5135 return err;
210fcd9d
TR		 5136}
5137
5138static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
5139{
5140 int err;
5141
5142 err = mipi_dsi_detach(dsi);
5143 if (err < 0)
5144 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
5145
5146 return panel_simple_remove(&dsi->dev);
5147}
5148
d02fd93e
TR		 5149static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
5150{
5151 panel_simple_shutdown(&dsi->dev);
5152}
5153
210fcd9d
TR		 5154static struct mipi_dsi_driver panel_simple_dsi_driver = {
5155 .driver = {
5156 .name = "panel-simple-dsi",
210fcd9d 5157 .of_match_table = dsi_of_match,
3235b0f2 5158 .pm = &panel_simple_pm_ops,
210fcd9d
TR		 5159 },
5160 .probe = panel_simple_dsi_probe,
5161 .remove = panel_simple_dsi_remove,
d02fd93e 5162 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 5163};
5164
74c06c28
DA		 5165static int panel_simple_dp_aux_ep_probe(struct dp_aux_ep_device *aux_ep)
5166{
5167 const struct of_device_id *id;
5168
5169 id = of_match_node(platform_of_match, aux_ep->dev.of_node);
5170 if (!id)
5171 return -ENODEV;
5172
cc5a3fc0 5173 return panel_simple_probe(&aux_ep->dev, id->data, aux_ep->aux);
74c06c28
DA		 5174}
5175
5176static void panel_simple_dp_aux_ep_remove(struct dp_aux_ep_device *aux_ep)
5177{
5178 panel_simple_remove(&aux_ep->dev);
5179}
5180
5181static void panel_simple_dp_aux_ep_shutdown(struct dp_aux_ep_device *aux_ep)
5182{
5183 panel_simple_shutdown(&aux_ep->dev);
5184}
5185
5186static struct dp_aux_ep_driver panel_simple_dp_aux_ep_driver = {
5187 .driver = {
5188 .name = "panel-simple-dp-aux",
5189 .of_match_table = platform_of_match, /* Same as platform one! */
5190 .pm = &panel_simple_pm_ops,
5191 },
5192 .probe = panel_simple_dp_aux_ep_probe,
5193 .remove = panel_simple_dp_aux_ep_remove,
5194 .shutdown = panel_simple_dp_aux_ep_shutdown,
5195};
5196
280921de
TR		 5197static int __init panel_simple_init(void)
5198{
210fcd9d
TR		 5199 int err;
5200
5201 err = platform_driver_register(&panel_simple_platform_driver);
5202 if (err < 0)
5203 return err;
5204
74c06c28
DA		 5205 err = dp_aux_dp_driver_register(&panel_simple_dp_aux_ep_driver);
5206 if (err < 0)
5207 goto err_did_platform_register;
5208
210fcd9d
TR		 5209 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
5210 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
74c06c28
DA		 5211 if (err < 0)
5212 goto err_did_aux_ep_register;
210fcd9d
TR		 5213 }
5214
5215 return 0;
74c06c28
DA		 5216
5217err_did_aux_ep_register:
5218 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver);
5219
5220err_did_platform_register:
5221 platform_driver_unregister(&panel_simple_platform_driver);
5222
5223 return err;
280921de
TR		 5224}
5225module_init(panel_simple_init);
5226
5227static void __exit panel_simple_exit(void)
5228{
210fcd9d
TR		 5229 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
5230 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
5231
74c06c28 5232 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver);
280921de
TR		 5233 platform_driver_unregister(&panel_simple_platform_driver);
5234}
5235module_exit(panel_simple_exit);
5236
5237MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
5238MODULE_DESCRIPTION("DRM Driver for Simple Panels");
5239MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)