Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_drv.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "omap_drv.h" | |
21 | ||
22 | #include "drm_crtc_helper.h" | |
23 | #include "drm_fb_helper.h" | |
5c137797 | 24 | #include "omap_dmm_tiler.h" |
cd5351f4 RC |
25 | |
26 | #define DRIVER_NAME MODULE_NAME | |
27 | #define DRIVER_DESC "OMAP DRM" | |
28 | #define DRIVER_DATE "20110917" | |
29 | #define DRIVER_MAJOR 1 | |
30 | #define DRIVER_MINOR 0 | |
31 | #define DRIVER_PATCHLEVEL 0 | |
32 | ||
cd5351f4 RC |
33 | static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS; |
34 | ||
35 | MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs"); | |
36 | module_param(num_crtc, int, 0600); | |
37 | ||
38 | /* | |
39 | * mode config funcs | |
40 | */ | |
41 | ||
42 | /* Notes about mapping DSS and DRM entities: | |
43 | * CRTC: overlay | |
44 | * encoder: manager.. with some extension to allow one primary CRTC | |
45 | * and zero or more video CRTC's to be mapped to one encoder? | |
46 | * connector: dssdev.. manager can be attached/detached from different | |
47 | * devices | |
48 | */ | |
49 | ||
50 | static void omap_fb_output_poll_changed(struct drm_device *dev) | |
51 | { | |
52 | struct omap_drm_private *priv = dev->dev_private; | |
53 | DBG("dev=%p", dev); | |
c7f904b3 | 54 | if (priv->fbdev) |
cd5351f4 | 55 | drm_fb_helper_hotplug_event(priv->fbdev); |
cd5351f4 RC |
56 | } |
57 | ||
e6ecefaa | 58 | static const struct drm_mode_config_funcs omap_mode_config_funcs = { |
cd5351f4 RC |
59 | .fb_create = omap_framebuffer_create, |
60 | .output_poll_changed = omap_fb_output_poll_changed, | |
61 | }; | |
62 | ||
63 | static int get_connector_type(struct omap_dss_device *dssdev) | |
64 | { | |
65 | switch (dssdev->type) { | |
66 | case OMAP_DISPLAY_TYPE_HDMI: | |
67 | return DRM_MODE_CONNECTOR_HDMIA; | |
4635c17d TV |
68 | case OMAP_DISPLAY_TYPE_DVI: |
69 | return DRM_MODE_CONNECTOR_DVID; | |
cd5351f4 RC |
70 | default: |
71 | return DRM_MODE_CONNECTOR_Unknown; | |
72 | } | |
73 | } | |
74 | ||
0d8f371f AT |
75 | static bool channel_used(struct drm_device *dev, enum omap_channel channel) |
76 | { | |
77 | struct omap_drm_private *priv = dev->dev_private; | |
78 | int i; | |
79 | ||
80 | for (i = 0; i < priv->num_crtcs; i++) { | |
81 | struct drm_crtc *crtc = priv->crtcs[i]; | |
82 | ||
83 | if (omap_crtc_channel(crtc) == channel) | |
84 | return true; | |
85 | } | |
86 | ||
87 | return false; | |
88 | } | |
cc823bdc AT |
89 | static void omap_disconnect_dssdevs(void) |
90 | { | |
91 | struct omap_dss_device *dssdev = NULL; | |
92 | ||
93 | for_each_dss_dev(dssdev) | |
94 | dssdev->driver->disconnect(dssdev); | |
95 | } | |
0d8f371f | 96 | |
3a01ab25 AT |
97 | static int omap_connect_dssdevs(void) |
98 | { | |
99 | int r; | |
100 | struct omap_dss_device *dssdev = NULL; | |
101 | bool no_displays = true; | |
102 | ||
103 | for_each_dss_dev(dssdev) { | |
104 | r = dssdev->driver->connect(dssdev); | |
105 | if (r == -EPROBE_DEFER) { | |
106 | omap_dss_put_device(dssdev); | |
107 | goto cleanup; | |
108 | } else if (r) { | |
109 | dev_warn(dssdev->dev, "could not connect display: %s\n", | |
110 | dssdev->name); | |
111 | } else { | |
112 | no_displays = false; | |
113 | } | |
114 | } | |
115 | ||
116 | if (no_displays) | |
117 | return -EPROBE_DEFER; | |
118 | ||
119 | return 0; | |
120 | ||
121 | cleanup: | |
122 | /* | |
123 | * if we are deferring probe, we disconnect the devices we previously | |
124 | * connected | |
125 | */ | |
cc823bdc | 126 | omap_disconnect_dssdevs(); |
3a01ab25 AT |
127 | |
128 | return r; | |
129 | } | |
0d8f371f | 130 | |
f5f9454c | 131 | static int omap_modeset_init(struct drm_device *dev) |
cd5351f4 RC |
132 | { |
133 | struct omap_drm_private *priv = dev->dev_private; | |
f5f9454c RC |
134 | struct omap_dss_device *dssdev = NULL; |
135 | int num_ovls = dss_feat_get_num_ovls(); | |
0d8f371f AT |
136 | int num_mgrs = dss_feat_get_num_mgrs(); |
137 | int num_crtcs; | |
138 | int i, id = 0; | |
04b1fc02 | 139 | |
f5f9454c | 140 | drm_mode_config_init(dev); |
cd5351f4 | 141 | |
f5f9454c | 142 | omap_drm_irq_install(dev); |
cd5351f4 | 143 | |
f5f9454c | 144 | /* |
0d8f371f AT |
145 | * We usually don't want to create a CRTC for each manager, at least |
146 | * not until we have a way to expose private planes to userspace. | |
147 | * Otherwise there would not be enough video pipes left for drm planes. | |
148 | * We use the num_crtc argument to limit the number of crtcs we create. | |
f5f9454c | 149 | */ |
0d8f371f | 150 | num_crtcs = min3(num_crtc, num_mgrs, num_ovls); |
cd5351f4 | 151 | |
0d8f371f | 152 | dssdev = NULL; |
cd5351f4 | 153 | |
f5f9454c RC |
154 | for_each_dss_dev(dssdev) { |
155 | struct drm_connector *connector; | |
156 | struct drm_encoder *encoder; | |
0d8f371f | 157 | enum omap_channel channel; |
a7e71e7f | 158 | struct omap_overlay_manager *mgr; |
c7f904b3 | 159 | |
3a01ab25 | 160 | if (!omapdss_device_is_connected(dssdev)) |
581382e3 | 161 | continue; |
a7e71e7f | 162 | |
f5f9454c | 163 | encoder = omap_encoder_init(dev, dssdev); |
cd5351f4 | 164 | |
f5f9454c RC |
165 | if (!encoder) { |
166 | dev_err(dev->dev, "could not create encoder: %s\n", | |
167 | dssdev->name); | |
168 | return -ENOMEM; | |
cd5351f4 RC |
169 | } |
170 | ||
f5f9454c RC |
171 | connector = omap_connector_init(dev, |
172 | get_connector_type(dssdev), dssdev, encoder); | |
cd5351f4 | 173 | |
f5f9454c RC |
174 | if (!connector) { |
175 | dev_err(dev->dev, "could not create connector: %s\n", | |
176 | dssdev->name); | |
177 | return -ENOMEM; | |
cd5351f4 | 178 | } |
bb5c2d9a | 179 | |
f5f9454c RC |
180 | BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders)); |
181 | BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors)); | |
cd5351f4 | 182 | |
f5f9454c RC |
183 | priv->encoders[priv->num_encoders++] = encoder; |
184 | priv->connectors[priv->num_connectors++] = connector; | |
cd5351f4 | 185 | |
f5f9454c | 186 | drm_mode_connector_attach_encoder(connector, encoder); |
cd5351f4 | 187 | |
0d8f371f AT |
188 | /* |
189 | * if we have reached the limit of the crtcs we are allowed to | |
190 | * create, let's not try to look for a crtc for this | |
191 | * panel/encoder and onwards, we will, of course, populate the | |
192 | * the possible_crtcs field for all the encoders with the final | |
193 | * set of crtcs we create | |
194 | */ | |
195 | if (id == num_crtcs) | |
196 | continue; | |
197 | ||
198 | /* | |
199 | * get the recommended DISPC channel for this encoder. For now, | |
200 | * we only try to get create a crtc out of the recommended, the | |
201 | * other possible channels to which the encoder can connect are | |
202 | * not considered. | |
203 | */ | |
0d8f371f | 204 | |
a7e71e7f TV |
205 | mgr = omapdss_find_mgr_from_display(dssdev); |
206 | channel = mgr->id; | |
0d8f371f AT |
207 | /* |
208 | * if this channel hasn't already been taken by a previously | |
209 | * allocated crtc, we create a new crtc for it | |
210 | */ | |
211 | if (!channel_used(dev, channel)) { | |
212 | struct drm_plane *plane; | |
213 | struct drm_crtc *crtc; | |
214 | ||
215 | plane = omap_plane_init(dev, id, true); | |
216 | crtc = omap_crtc_init(dev, plane, channel, id); | |
217 | ||
218 | BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs)); | |
219 | priv->crtcs[id] = crtc; | |
220 | priv->num_crtcs++; | |
221 | ||
222 | priv->planes[id] = plane; | |
223 | priv->num_planes++; | |
224 | ||
225 | id++; | |
226 | } | |
227 | } | |
228 | ||
229 | /* | |
230 | * we have allocated crtcs according to the need of the panels/encoders, | |
231 | * adding more crtcs here if needed | |
232 | */ | |
233 | for (; id < num_crtcs; id++) { | |
234 | ||
235 | /* find a free manager for this crtc */ | |
236 | for (i = 0; i < num_mgrs; i++) { | |
237 | if (!channel_used(dev, i)) { | |
238 | struct drm_plane *plane; | |
239 | struct drm_crtc *crtc; | |
240 | ||
241 | plane = omap_plane_init(dev, id, true); | |
242 | crtc = omap_crtc_init(dev, plane, i, id); | |
243 | ||
244 | BUG_ON(priv->num_crtcs >= | |
245 | ARRAY_SIZE(priv->crtcs)); | |
246 | ||
247 | priv->crtcs[id] = crtc; | |
248 | priv->num_crtcs++; | |
249 | ||
250 | priv->planes[id] = plane; | |
251 | priv->num_planes++; | |
252 | ||
253 | break; | |
254 | } else { | |
255 | continue; | |
256 | } | |
257 | } | |
258 | ||
259 | if (i == num_mgrs) { | |
260 | /* this shouldn't really happen */ | |
261 | dev_err(dev->dev, "no managers left for crtc\n"); | |
262 | return -ENOMEM; | |
263 | } | |
264 | } | |
265 | ||
266 | /* | |
267 | * Create normal planes for the remaining overlays: | |
268 | */ | |
269 | for (; id < num_ovls; id++) { | |
270 | struct drm_plane *plane = omap_plane_init(dev, id, false); | |
271 | ||
272 | BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)); | |
273 | priv->planes[priv->num_planes++] = plane; | |
274 | } | |
275 | ||
276 | for (i = 0; i < priv->num_encoders; i++) { | |
277 | struct drm_encoder *encoder = priv->encoders[i]; | |
278 | struct omap_dss_device *dssdev = | |
279 | omap_encoder_get_dssdev(encoder); | |
1f68d9c4 | 280 | struct omap_dss_device *output; |
be8e8e1c TV |
281 | |
282 | output = omapdss_find_output_from_display(dssdev); | |
0d8f371f | 283 | |
f5f9454c RC |
284 | /* figure out which crtc's we can connect the encoder to: */ |
285 | encoder->possible_crtcs = 0; | |
286 | for (id = 0; id < priv->num_crtcs; id++) { | |
0d8f371f AT |
287 | struct drm_crtc *crtc = priv->crtcs[id]; |
288 | enum omap_channel crtc_channel; | |
289 | enum omap_dss_output_id supported_outputs; | |
290 | ||
291 | crtc_channel = omap_crtc_channel(crtc); | |
292 | supported_outputs = | |
293 | dss_feat_get_supported_outputs(crtc_channel); | |
294 | ||
be8e8e1c | 295 | if (supported_outputs & output->id) |
f5f9454c | 296 | encoder->possible_crtcs |= (1 << id); |
bb5c2d9a | 297 | } |
820caabf TV |
298 | |
299 | omap_dss_put_device(output); | |
cd5351f4 RC |
300 | } |
301 | ||
0d8f371f AT |
302 | DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n", |
303 | priv->num_planes, priv->num_crtcs, priv->num_encoders, | |
304 | priv->num_connectors); | |
305 | ||
6b8ca4cf RC |
306 | dev->mode_config.min_width = 32; |
307 | dev->mode_config.min_height = 32; | |
cd5351f4 RC |
308 | |
309 | /* note: eventually will need some cpu_is_omapXYZ() type stuff here | |
310 | * to fill in these limits properly on different OMAP generations.. | |
311 | */ | |
312 | dev->mode_config.max_width = 2048; | |
313 | dev->mode_config.max_height = 2048; | |
314 | ||
315 | dev->mode_config.funcs = &omap_mode_config_funcs; | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static void omap_modeset_free(struct drm_device *dev) | |
321 | { | |
322 | drm_mode_config_cleanup(dev); | |
323 | } | |
324 | ||
325 | /* | |
326 | * drm ioctl funcs | |
327 | */ | |
328 | ||
329 | ||
330 | static int ioctl_get_param(struct drm_device *dev, void *data, | |
331 | struct drm_file *file_priv) | |
332 | { | |
5e3b0874 | 333 | struct omap_drm_private *priv = dev->dev_private; |
cd5351f4 RC |
334 | struct drm_omap_param *args = data; |
335 | ||
336 | DBG("%p: param=%llu", dev, args->param); | |
337 | ||
338 | switch (args->param) { | |
339 | case OMAP_PARAM_CHIPSET_ID: | |
5e3b0874 | 340 | args->value = priv->omaprev; |
cd5351f4 RC |
341 | break; |
342 | default: | |
343 | DBG("unknown parameter %lld", args->param); | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static int ioctl_set_param(struct drm_device *dev, void *data, | |
351 | struct drm_file *file_priv) | |
352 | { | |
353 | struct drm_omap_param *args = data; | |
354 | ||
355 | switch (args->param) { | |
356 | default: | |
357 | DBG("unknown parameter %lld", args->param); | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | static int ioctl_gem_new(struct drm_device *dev, void *data, | |
365 | struct drm_file *file_priv) | |
366 | { | |
367 | struct drm_omap_gem_new *args = data; | |
f5f9454c | 368 | VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv, |
cd5351f4 RC |
369 | args->size.bytes, args->flags); |
370 | return omap_gem_new_handle(dev, file_priv, args->size, | |
371 | args->flags, &args->handle); | |
372 | } | |
373 | ||
374 | static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data, | |
375 | struct drm_file *file_priv) | |
376 | { | |
377 | struct drm_omap_gem_cpu_prep *args = data; | |
378 | struct drm_gem_object *obj; | |
379 | int ret; | |
380 | ||
381 | VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op); | |
382 | ||
383 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 384 | if (!obj) |
cd5351f4 | 385 | return -ENOENT; |
cd5351f4 RC |
386 | |
387 | ret = omap_gem_op_sync(obj, args->op); | |
388 | ||
c7f904b3 | 389 | if (!ret) |
cd5351f4 | 390 | ret = omap_gem_op_start(obj, args->op); |
cd5351f4 RC |
391 | |
392 | drm_gem_object_unreference_unlocked(obj); | |
393 | ||
394 | return ret; | |
395 | } | |
396 | ||
397 | static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data, | |
398 | struct drm_file *file_priv) | |
399 | { | |
400 | struct drm_omap_gem_cpu_fini *args = data; | |
401 | struct drm_gem_object *obj; | |
402 | int ret; | |
403 | ||
404 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); | |
405 | ||
406 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 407 | if (!obj) |
cd5351f4 | 408 | return -ENOENT; |
cd5351f4 RC |
409 | |
410 | /* XXX flushy, flushy */ | |
411 | ret = 0; | |
412 | ||
c7f904b3 | 413 | if (!ret) |
cd5351f4 | 414 | ret = omap_gem_op_finish(obj, args->op); |
cd5351f4 RC |
415 | |
416 | drm_gem_object_unreference_unlocked(obj); | |
417 | ||
418 | return ret; | |
419 | } | |
420 | ||
421 | static int ioctl_gem_info(struct drm_device *dev, void *data, | |
422 | struct drm_file *file_priv) | |
423 | { | |
424 | struct drm_omap_gem_info *args = data; | |
425 | struct drm_gem_object *obj; | |
426 | int ret = 0; | |
427 | ||
f5f9454c | 428 | VERB("%p:%p: handle=%d", dev, file_priv, args->handle); |
cd5351f4 RC |
429 | |
430 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
c7f904b3 | 431 | if (!obj) |
cd5351f4 | 432 | return -ENOENT; |
cd5351f4 | 433 | |
f7f9f453 | 434 | args->size = omap_gem_mmap_size(obj); |
cd5351f4 RC |
435 | args->offset = omap_gem_mmap_offset(obj); |
436 | ||
437 | drm_gem_object_unreference_unlocked(obj); | |
438 | ||
439 | return ret; | |
440 | } | |
441 | ||
baa70943 | 442 | static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { |
cd5351f4 RC |
443 | DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH), |
444 | DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
445 | DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH), | |
446 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH), | |
447 | DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH), | |
448 | DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH), | |
449 | }; | |
450 | ||
451 | /* | |
452 | * drm driver funcs | |
453 | */ | |
454 | ||
455 | /** | |
456 | * load - setup chip and create an initial config | |
457 | * @dev: DRM device | |
458 | * @flags: startup flags | |
459 | * | |
460 | * The driver load routine has to do several things: | |
461 | * - initialize the memory manager | |
462 | * - allocate initial config memory | |
463 | * - setup the DRM framebuffer with the allocated memory | |
464 | */ | |
465 | static int dev_load(struct drm_device *dev, unsigned long flags) | |
466 | { | |
5e3b0874 | 467 | struct omap_drm_platform_data *pdata = dev->dev->platform_data; |
cd5351f4 RC |
468 | struct omap_drm_private *priv; |
469 | int ret; | |
470 | ||
471 | DBG("load: dev=%p", dev); | |
472 | ||
cd5351f4 | 473 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
78110bb8 | 474 | if (!priv) |
cd5351f4 | 475 | return -ENOMEM; |
cd5351f4 | 476 | |
5e3b0874 RC |
477 | priv->omaprev = pdata->omaprev; |
478 | ||
cd5351f4 RC |
479 | dev->dev_private = priv; |
480 | ||
4619cdbc | 481 | priv->wq = alloc_ordered_workqueue("omapdrm", 0); |
5609f7fe | 482 | |
f6b6036e RC |
483 | INIT_LIST_HEAD(&priv->obj_list); |
484 | ||
f7f9f453 RC |
485 | omap_gem_init(dev); |
486 | ||
cd5351f4 RC |
487 | ret = omap_modeset_init(dev); |
488 | if (ret) { | |
489 | dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret); | |
490 | dev->dev_private = NULL; | |
491 | kfree(priv); | |
492 | return ret; | |
493 | } | |
494 | ||
f5f9454c RC |
495 | ret = drm_vblank_init(dev, priv->num_crtcs); |
496 | if (ret) | |
497 | dev_warn(dev->dev, "could not init vblank\n"); | |
498 | ||
cd5351f4 RC |
499 | priv->fbdev = omap_fbdev_init(dev); |
500 | if (!priv->fbdev) { | |
501 | dev_warn(dev->dev, "omap_fbdev_init failed\n"); | |
502 | /* well, limp along without an fbdev.. maybe X11 will work? */ | |
503 | } | |
504 | ||
e78edba1 AG |
505 | /* store off drm_device for use in pm ops */ |
506 | dev_set_drvdata(dev->dev, dev); | |
507 | ||
cd5351f4 RC |
508 | drm_kms_helper_poll_init(dev); |
509 | ||
cd5351f4 RC |
510 | return 0; |
511 | } | |
512 | ||
513 | static int dev_unload(struct drm_device *dev) | |
514 | { | |
5609f7fe | 515 | struct omap_drm_private *priv = dev->dev_private; |
e2f8fd74 | 516 | int i; |
5609f7fe | 517 | |
cd5351f4 RC |
518 | DBG("unload: dev=%p", dev); |
519 | ||
cd5351f4 RC |
520 | drm_kms_helper_poll_fini(dev); |
521 | ||
522 | omap_fbdev_free(dev); | |
e2f8fd74 TV |
523 | |
524 | /* flush crtcs so the fbs get released */ | |
525 | for (i = 0; i < priv->num_crtcs; i++) | |
526 | omap_crtc_flush(priv->crtcs[i]); | |
527 | ||
cd5351f4 | 528 | omap_modeset_free(dev); |
f7f9f453 | 529 | omap_gem_deinit(dev); |
cd5351f4 | 530 | |
5609f7fe RC |
531 | destroy_workqueue(priv->wq); |
532 | ||
80e4ed54 AT |
533 | drm_vblank_cleanup(dev); |
534 | omap_drm_irq_uninstall(dev); | |
535 | ||
cd5351f4 RC |
536 | kfree(dev->dev_private); |
537 | dev->dev_private = NULL; | |
538 | ||
e78edba1 AG |
539 | dev_set_drvdata(dev->dev, NULL); |
540 | ||
cd5351f4 RC |
541 | return 0; |
542 | } | |
543 | ||
544 | static int dev_open(struct drm_device *dev, struct drm_file *file) | |
545 | { | |
546 | file->driver_priv = NULL; | |
547 | ||
548 | DBG("open: dev=%p, file=%p", dev, file); | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
cd5351f4 RC |
553 | /** |
554 | * lastclose - clean up after all DRM clients have exited | |
555 | * @dev: DRM device | |
556 | * | |
557 | * Take care of cleaning up after all DRM clients have exited. In the | |
558 | * mode setting case, we want to restore the kernel's initial mode (just | |
559 | * in case the last client left us in a bad state). | |
560 | */ | |
561 | static void dev_lastclose(struct drm_device *dev) | |
562 | { | |
3c810c61 RC |
563 | int i; |
564 | ||
cd5351f4 RC |
565 | /* we don't support vga-switcheroo.. so just make sure the fbdev |
566 | * mode is active | |
567 | */ | |
568 | struct omap_drm_private *priv = dev->dev_private; | |
569 | int ret; | |
570 | ||
571 | DBG("lastclose: dev=%p", dev); | |
572 | ||
c2a6a552 RC |
573 | if (priv->rotation_prop) { |
574 | /* need to restore default rotation state.. not sure | |
575 | * if there is a cleaner way to restore properties to | |
576 | * default state? Maybe a flag that properties should | |
577 | * automatically be restored to default state on | |
578 | * lastclose? | |
579 | */ | |
580 | for (i = 0; i < priv->num_crtcs; i++) { | |
581 | drm_object_property_set_value(&priv->crtcs[i]->base, | |
582 | priv->rotation_prop, 0); | |
583 | } | |
3c810c61 | 584 | |
c2a6a552 RC |
585 | for (i = 0; i < priv->num_planes; i++) { |
586 | drm_object_property_set_value(&priv->planes[i]->base, | |
587 | priv->rotation_prop, 0); | |
588 | } | |
3c810c61 RC |
589 | } |
590 | ||
5ea1f752 | 591 | ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); |
cd5351f4 RC |
592 | if (ret) |
593 | DBG("failed to restore crtc mode"); | |
594 | } | |
595 | ||
596 | static void dev_preclose(struct drm_device *dev, struct drm_file *file) | |
597 | { | |
598 | DBG("preclose: dev=%p", dev); | |
599 | } | |
600 | ||
601 | static void dev_postclose(struct drm_device *dev, struct drm_file *file) | |
602 | { | |
603 | DBG("postclose: dev=%p, file=%p", dev, file); | |
604 | } | |
605 | ||
78b68556 | 606 | static const struct vm_operations_struct omap_gem_vm_ops = { |
cd5351f4 RC |
607 | .fault = omap_gem_fault, |
608 | .open = drm_gem_vm_open, | |
609 | .close = drm_gem_vm_close, | |
610 | }; | |
611 | ||
ff4f3876 RC |
612 | static const struct file_operations omapdriver_fops = { |
613 | .owner = THIS_MODULE, | |
614 | .open = drm_open, | |
615 | .unlocked_ioctl = drm_ioctl, | |
616 | .release = drm_release, | |
617 | .mmap = omap_gem_mmap, | |
618 | .poll = drm_poll, | |
ff4f3876 RC |
619 | .read = drm_read, |
620 | .llseek = noop_llseek, | |
621 | }; | |
622 | ||
cd5351f4 RC |
623 | static struct drm_driver omap_drm_driver = { |
624 | .driver_features = | |
6ad11bc3 | 625 | DRIVER_HAVE_IRQ | DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, |
cd5351f4 RC |
626 | .load = dev_load, |
627 | .unload = dev_unload, | |
628 | .open = dev_open, | |
cd5351f4 RC |
629 | .lastclose = dev_lastclose, |
630 | .preclose = dev_preclose, | |
631 | .postclose = dev_postclose, | |
915b4d11 | 632 | .set_busid = drm_platform_set_busid, |
cd5351f4 | 633 | .get_vblank_counter = drm_vblank_count, |
f5f9454c RC |
634 | .enable_vblank = omap_irq_enable_vblank, |
635 | .disable_vblank = omap_irq_disable_vblank, | |
636 | .irq_preinstall = omap_irq_preinstall, | |
637 | .irq_postinstall = omap_irq_postinstall, | |
638 | .irq_uninstall = omap_irq_uninstall, | |
639 | .irq_handler = omap_irq_handler, | |
6169a148 AG |
640 | #ifdef CONFIG_DEBUG_FS |
641 | .debugfs_init = omap_debugfs_init, | |
642 | .debugfs_cleanup = omap_debugfs_cleanup, | |
643 | #endif | |
6ad11bc3 | 644 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
3080b838 | 645 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
6ad11bc3 | 646 | .gem_prime_export = omap_gem_prime_export, |
3080b838 | 647 | .gem_prime_import = omap_gem_prime_import, |
cd5351f4 RC |
648 | .gem_free_object = omap_gem_free_object, |
649 | .gem_vm_ops = &omap_gem_vm_ops, | |
650 | .dumb_create = omap_gem_dumb_create, | |
651 | .dumb_map_offset = omap_gem_dumb_map_offset, | |
43387b37 | 652 | .dumb_destroy = drm_gem_dumb_destroy, |
cd5351f4 RC |
653 | .ioctls = ioctls, |
654 | .num_ioctls = DRM_OMAP_NUM_IOCTLS, | |
ff4f3876 | 655 | .fops = &omapdriver_fops, |
cd5351f4 RC |
656 | .name = DRIVER_NAME, |
657 | .desc = DRIVER_DESC, | |
658 | .date = DRIVER_DATE, | |
659 | .major = DRIVER_MAJOR, | |
660 | .minor = DRIVER_MINOR, | |
661 | .patchlevel = DRIVER_PATCHLEVEL, | |
662 | }; | |
663 | ||
664 | static int pdev_suspend(struct platform_device *pDevice, pm_message_t state) | |
665 | { | |
666 | DBG(""); | |
667 | return 0; | |
668 | } | |
669 | ||
670 | static int pdev_resume(struct platform_device *device) | |
671 | { | |
672 | DBG(""); | |
673 | return 0; | |
674 | } | |
675 | ||
676 | static void pdev_shutdown(struct platform_device *device) | |
677 | { | |
678 | DBG(""); | |
679 | } | |
680 | ||
681 | static int pdev_probe(struct platform_device *device) | |
682 | { | |
3a01ab25 AT |
683 | int r; |
684 | ||
591a0ac7 TV |
685 | if (omapdss_is_initialized() == false) |
686 | return -EPROBE_DEFER; | |
687 | ||
3a01ab25 AT |
688 | omap_crtc_pre_init(); |
689 | ||
690 | r = omap_connect_dssdevs(); | |
691 | if (r) { | |
692 | omap_crtc_pre_uninit(); | |
693 | return r; | |
694 | } | |
695 | ||
cd5351f4 RC |
696 | DBG("%s", device->name); |
697 | return drm_platform_init(&omap_drm_driver, device); | |
698 | } | |
699 | ||
700 | static int pdev_remove(struct platform_device *device) | |
701 | { | |
702 | DBG(""); | |
5c137797 | 703 | |
707cf58a TV |
704 | drm_put_dev(platform_get_drvdata(device)); |
705 | ||
cc823bdc AT |
706 | omap_disconnect_dssdevs(); |
707 | omap_crtc_pre_uninit(); | |
fd3c0253 | 708 | |
cd5351f4 RC |
709 | return 0; |
710 | } | |
711 | ||
e78edba1 AG |
712 | #ifdef CONFIG_PM |
713 | static const struct dev_pm_ops omapdrm_pm_ops = { | |
714 | .resume = omap_gem_resume, | |
715 | }; | |
716 | #endif | |
717 | ||
6717cd29 | 718 | static struct platform_driver pdev = { |
cd5351f4 RC |
719 | .driver = { |
720 | .name = DRIVER_NAME, | |
721 | .owner = THIS_MODULE, | |
e78edba1 AG |
722 | #ifdef CONFIG_PM |
723 | .pm = &omapdrm_pm_ops, | |
724 | #endif | |
cd5351f4 RC |
725 | }, |
726 | .probe = pdev_probe, | |
727 | .remove = pdev_remove, | |
728 | .suspend = pdev_suspend, | |
729 | .resume = pdev_resume, | |
730 | .shutdown = pdev_shutdown, | |
731 | }; | |
732 | ||
733 | static int __init omap_drm_init(void) | |
734 | { | |
ea7e3a66 TV |
735 | int r; |
736 | ||
cd5351f4 | 737 | DBG("init"); |
ea7e3a66 TV |
738 | |
739 | r = platform_driver_register(&omap_dmm_driver); | |
740 | if (r) { | |
741 | pr_err("DMM driver registration failed\n"); | |
742 | return r; | |
be0775ac | 743 | } |
ea7e3a66 TV |
744 | |
745 | r = platform_driver_register(&pdev); | |
746 | if (r) { | |
747 | pr_err("omapdrm driver registration failed\n"); | |
748 | platform_driver_unregister(&omap_dmm_driver); | |
749 | return r; | |
750 | } | |
751 | ||
752 | return 0; | |
cd5351f4 RC |
753 | } |
754 | ||
755 | static void __exit omap_drm_fini(void) | |
756 | { | |
757 | DBG("fini"); | |
ea7e3a66 | 758 | |
cd5351f4 | 759 | platform_driver_unregister(&pdev); |
ea7e3a66 TV |
760 | |
761 | platform_driver_unregister(&omap_dmm_driver); | |
cd5351f4 RC |
762 | } |
763 | ||
764 | /* need late_initcall() so we load after dss_driver's are loaded */ | |
765 | late_initcall(omap_drm_init); | |
766 | module_exit(omap_drm_fini); | |
767 | ||
768 | MODULE_AUTHOR("Rob Clark <rob@ti.com>"); | |
769 | MODULE_DESCRIPTION("OMAP DRM Display Driver"); | |
770 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
771 | MODULE_LICENSE("GPL v2"); |