Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
8bb0daff | 2 | * drivers/gpu/drm/omapdrm/omap_crtc.c |
cd5351f4 RC |
3 | * |
4 | * Copyright (C) 2011 Texas Instruments | |
5 | * Author: Rob Clark <rob@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
69a12263 LP |
20 | #include <drm/drm_atomic.h> |
21 | #include <drm/drm_atomic_helper.h> | |
2d278f54 LP |
22 | #include <drm/drm_crtc.h> |
23 | #include <drm/drm_crtc_helper.h> | |
b9ed9f0e | 24 | #include <drm/drm_mode.h> |
3cb9ae4f | 25 | #include <drm/drm_plane_helper.h> |
2d278f54 LP |
26 | |
27 | #include "omap_drv.h" | |
cd5351f4 RC |
28 | |
29 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) | |
30 | ||
31 | struct omap_crtc { | |
32 | struct drm_crtc base; | |
f5f9454c | 33 | |
bb5c2d9a | 34 | const char *name; |
f5f9454c | 35 | enum omap_channel channel; |
f5f9454c | 36 | |
f5f9454c | 37 | struct omap_video_timings timings; |
f5f9454c | 38 | |
a42133a7 | 39 | struct omap_drm_irq vblank_irq; |
f5f9454c RC |
40 | struct omap_drm_irq error_irq; |
41 | ||
a36af73f | 42 | bool ignore_digit_sync_lost; |
5f741b39 TV |
43 | |
44 | bool pending; | |
45 | wait_queue_head_t pending_wait; | |
f5f9454c RC |
46 | }; |
47 | ||
971fb3e5 LP |
48 | /* ----------------------------------------------------------------------------- |
49 | * Helper Functions | |
50 | */ | |
51 | ||
0d8f371f AT |
52 | uint32_t pipe2vbl(struct drm_crtc *crtc) |
53 | { | |
54 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
55 | ||
56 | return dispc_mgr_get_vsync_irq(omap_crtc->channel); | |
57 | } | |
58 | ||
4029755e | 59 | struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc) |
971fb3e5 LP |
60 | { |
61 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
62 | return &omap_crtc->timings; | |
63 | } | |
64 | ||
65 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
66 | { | |
67 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
68 | return omap_crtc->channel; | |
69 | } | |
70 | ||
5f741b39 TV |
71 | int omap_crtc_wait_pending(struct drm_crtc *crtc) |
72 | { | |
73 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
74 | ||
61f3c40b TV |
75 | /* |
76 | * Timeout is set to a "sufficiently" high value, which should cover | |
77 | * a single frame refresh even on slower displays. | |
78 | */ | |
5f741b39 TV |
79 | return wait_event_timeout(omap_crtc->pending_wait, |
80 | !omap_crtc->pending, | |
61f3c40b | 81 | msecs_to_jiffies(250)); |
5f741b39 TV |
82 | } |
83 | ||
971fb3e5 LP |
84 | /* ----------------------------------------------------------------------------- |
85 | * DSS Manager Functions | |
86 | */ | |
87 | ||
f5f9454c RC |
88 | /* |
89 | * Manager-ops, callbacks from output when they need to configure | |
90 | * the upstream part of the video pipe. | |
91 | * | |
92 | * Most of these we can ignore until we add support for command-mode | |
93 | * panels.. for video-mode the crtc-helpers already do an adequate | |
94 | * job of sequencing the setup of the video pipe in the proper order | |
95 | */ | |
96 | ||
04b1fc02 TV |
97 | /* ovl-mgr-id -> crtc */ |
98 | static struct omap_crtc *omap_crtcs[8]; | |
3a924138 | 99 | static struct omap_dss_device *omap_crtc_output[8]; |
04b1fc02 | 100 | |
f5f9454c | 101 | /* we can probably ignore these until we support command-mode panels: */ |
e5cbb6e8 | 102 | static int omap_crtc_dss_connect(enum omap_channel channel, |
1f68d9c4 | 103 | struct omap_dss_device *dst) |
a7e71e7f | 104 | { |
e5cbb6e8 TV |
105 | struct omap_overlay_manager *mgr = omap_dss_get_overlay_manager(channel); |
106 | ||
107 | if (omap_crtc_output[channel]) | |
a7e71e7f TV |
108 | return -EINVAL; |
109 | ||
e5cbb6e8 | 110 | if ((dispc_mgr_get_supported_outputs(channel) & dst->id) == 0) |
a7e71e7f TV |
111 | return -EINVAL; |
112 | ||
e5cbb6e8 | 113 | omap_crtc_output[channel] = dst; |
3a924138 | 114 | |
a7e71e7f TV |
115 | dst->manager = mgr; |
116 | mgr->output = dst; | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
e5cbb6e8 | 121 | static void omap_crtc_dss_disconnect(enum omap_channel channel, |
1f68d9c4 | 122 | struct omap_dss_device *dst) |
a7e71e7f | 123 | { |
e5cbb6e8 TV |
124 | struct omap_overlay_manager *mgr = omap_dss_get_overlay_manager(channel); |
125 | ||
126 | omap_crtc_output[channel] = NULL; | |
3a924138 | 127 | |
a7e71e7f TV |
128 | mgr->output->manager = NULL; |
129 | mgr->output = NULL; | |
130 | } | |
131 | ||
e5cbb6e8 | 132 | static void omap_crtc_dss_start_update(enum omap_channel channel) |
f5f9454c RC |
133 | { |
134 | } | |
135 | ||
4029755e | 136 | /* Called only from the encoder enable/disable and suspend/resume handlers. */ |
8472b570 LP |
137 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) |
138 | { | |
139 | struct drm_device *dev = crtc->dev; | |
140 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
141 | enum omap_channel channel = omap_crtc->channel; | |
142 | struct omap_irq_wait *wait; | |
143 | u32 framedone_irq, vsync_irq; | |
144 | int ret; | |
145 | ||
3a924138 | 146 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { |
4e4b53ce TV |
147 | dispc_mgr_enable(channel, enable); |
148 | return; | |
149 | } | |
150 | ||
8472b570 LP |
151 | if (dispc_mgr_is_enabled(channel) == enable) |
152 | return; | |
153 | ||
ef422283 TV |
154 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
155 | /* | |
156 | * Digit output produces some sync lost interrupts during the | |
157 | * first frame when enabling, so we need to ignore those. | |
158 | */ | |
159 | omap_crtc->ignore_digit_sync_lost = true; | |
160 | } | |
8472b570 LP |
161 | |
162 | framedone_irq = dispc_mgr_get_framedone_irq(channel); | |
163 | vsync_irq = dispc_mgr_get_vsync_irq(channel); | |
164 | ||
165 | if (enable) { | |
166 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | |
167 | } else { | |
168 | /* | |
169 | * When we disable the digit output, we need to wait for | |
170 | * FRAMEDONE to know that DISPC has finished with the output. | |
171 | * | |
172 | * OMAP2/3 does not have FRAMEDONE irq for digit output, and in | |
173 | * that case we need to use vsync interrupt, and wait for both | |
174 | * even and odd frames. | |
175 | */ | |
176 | ||
177 | if (framedone_irq) | |
178 | wait = omap_irq_wait_init(dev, framedone_irq, 1); | |
179 | else | |
180 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | |
181 | } | |
182 | ||
183 | dispc_mgr_enable(channel, enable); | |
184 | ||
185 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | |
186 | if (ret) { | |
187 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
188 | omap_crtc->name, enable ? "enable" : "disable"); | |
189 | } | |
190 | ||
ef422283 TV |
191 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
192 | omap_crtc->ignore_digit_sync_lost = false; | |
193 | /* make sure the irq handler sees the value above */ | |
194 | mb(); | |
195 | } | |
8472b570 LP |
196 | } |
197 | ||
506096a1 | 198 | |
e5cbb6e8 | 199 | static int omap_crtc_dss_enable(enum omap_channel channel) |
f5f9454c | 200 | { |
e5cbb6e8 | 201 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
dee8260d | 202 | struct omap_overlay_manager_info info; |
506096a1 | 203 | |
dee8260d LP |
204 | memset(&info, 0, sizeof(info)); |
205 | info.default_color = 0x00000000; | |
206 | info.trans_key = 0x00000000; | |
207 | info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST; | |
208 | info.trans_enabled = false; | |
209 | ||
210 | dispc_mgr_setup(omap_crtc->channel, &info); | |
506096a1 TV |
211 | dispc_mgr_set_timings(omap_crtc->channel, |
212 | &omap_crtc->timings); | |
8472b570 | 213 | omap_crtc_set_enabled(&omap_crtc->base, true); |
506096a1 | 214 | |
f5f9454c RC |
215 | return 0; |
216 | } | |
217 | ||
e5cbb6e8 | 218 | static void omap_crtc_dss_disable(enum omap_channel channel) |
f5f9454c | 219 | { |
e5cbb6e8 | 220 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
506096a1 | 221 | |
8472b570 | 222 | omap_crtc_set_enabled(&omap_crtc->base, false); |
f5f9454c RC |
223 | } |
224 | ||
e5cbb6e8 | 225 | static void omap_crtc_dss_set_timings(enum omap_channel channel, |
f5f9454c RC |
226 | const struct omap_video_timings *timings) |
227 | { | |
e5cbb6e8 | 228 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
f5f9454c RC |
229 | DBG("%s", omap_crtc->name); |
230 | omap_crtc->timings = *timings; | |
f5f9454c RC |
231 | } |
232 | ||
e5cbb6e8 | 233 | static void omap_crtc_dss_set_lcd_config(enum omap_channel channel, |
f5f9454c RC |
234 | const struct dss_lcd_mgr_config *config) |
235 | { | |
e5cbb6e8 | 236 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
f5f9454c RC |
237 | DBG("%s", omap_crtc->name); |
238 | dispc_mgr_set_lcd_config(omap_crtc->channel, config); | |
239 | } | |
240 | ||
4343f0f8 | 241 | static int omap_crtc_dss_register_framedone( |
e5cbb6e8 | 242 | enum omap_channel channel, |
f5f9454c RC |
243 | void (*handler)(void *), void *data) |
244 | { | |
245 | return 0; | |
246 | } | |
247 | ||
4343f0f8 | 248 | static void omap_crtc_dss_unregister_framedone( |
e5cbb6e8 | 249 | enum omap_channel channel, |
f5f9454c RC |
250 | void (*handler)(void *), void *data) |
251 | { | |
252 | } | |
253 | ||
254 | static const struct dss_mgr_ops mgr_ops = { | |
4343f0f8 LP |
255 | .connect = omap_crtc_dss_connect, |
256 | .disconnect = omap_crtc_dss_disconnect, | |
257 | .start_update = omap_crtc_dss_start_update, | |
258 | .enable = omap_crtc_dss_enable, | |
259 | .disable = omap_crtc_dss_disable, | |
260 | .set_timings = omap_crtc_dss_set_timings, | |
261 | .set_lcd_config = omap_crtc_dss_set_lcd_config, | |
262 | .register_framedone_handler = omap_crtc_dss_register_framedone, | |
263 | .unregister_framedone_handler = omap_crtc_dss_unregister_framedone, | |
cd5351f4 RC |
264 | }; |
265 | ||
971fb3e5 | 266 | /* ----------------------------------------------------------------------------- |
1d5e5ea1 | 267 | * Setup, Flush and Page Flip |
971fb3e5 LP |
268 | */ |
269 | ||
fa16d262 | 270 | static void omap_crtc_complete_page_flip(struct drm_crtc *crtc) |
15d02e92 | 271 | { |
fa16d262 | 272 | struct drm_pending_vblank_event *event; |
15d02e92 | 273 | struct drm_device *dev = crtc->dev; |
fa16d262 | 274 | unsigned long flags; |
15d02e92 | 275 | |
5f741b39 | 276 | event = crtc->state->event; |
c397cfd4 | 277 | |
5f741b39 TV |
278 | if (!event) |
279 | return; | |
c397cfd4 LP |
280 | |
281 | spin_lock_irqsave(&dev->event_lock, flags); | |
c397cfd4 | 282 | |
5f741b39 | 283 | list_del(&event->base.link); |
c397cfd4 | 284 | |
5f741b39 TV |
285 | /* |
286 | * Queue the event for delivery if it's still linked to a file | |
287 | * handle, otherwise just destroy it. | |
288 | */ | |
289 | if (event->base.file_priv) | |
290 | drm_crtc_send_vblank_event(crtc, event); | |
291 | else | |
292 | event->base.destroy(&event->base); | |
c397cfd4 | 293 | |
5f741b39 | 294 | spin_unlock_irqrestore(&dev->event_lock, flags); |
15d02e92 LP |
295 | } |
296 | ||
971fb3e5 LP |
297 | static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus) |
298 | { | |
299 | struct omap_crtc *omap_crtc = | |
300 | container_of(irq, struct omap_crtc, error_irq); | |
a36af73f TV |
301 | |
302 | if (omap_crtc->ignore_digit_sync_lost) { | |
303 | irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
304 | if (!irqstatus) | |
305 | return; | |
306 | } | |
307 | ||
3b143fc8 | 308 | DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); |
971fb3e5 LP |
309 | } |
310 | ||
a42133a7 | 311 | static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus) |
971fb3e5 LP |
312 | { |
313 | struct omap_crtc *omap_crtc = | |
a42133a7 LP |
314 | container_of(irq, struct omap_crtc, vblank_irq); |
315 | struct drm_device *dev = omap_crtc->base.dev; | |
971fb3e5 | 316 | |
a42133a7 LP |
317 | if (dispc_mgr_go_busy(omap_crtc->channel)) |
318 | return; | |
319 | ||
320 | DBG("%s: apply done", omap_crtc->name); | |
5f741b39 | 321 | |
a42133a7 LP |
322 | __omap_irq_unregister(dev, &omap_crtc->vblank_irq); |
323 | ||
5f741b39 TV |
324 | rmb(); |
325 | WARN_ON(!omap_crtc->pending); | |
326 | omap_crtc->pending = false; | |
327 | wmb(); | |
328 | ||
329 | /* wake up userspace */ | |
fa16d262 | 330 | omap_crtc_complete_page_flip(&omap_crtc->base); |
a42133a7 | 331 | |
5f741b39 TV |
332 | /* wake up omap_atomic_complete */ |
333 | wake_up(&omap_crtc->pending_wait); | |
971fb3e5 LP |
334 | } |
335 | ||
971fb3e5 LP |
336 | /* ----------------------------------------------------------------------------- |
337 | * CRTC Functions | |
f5f9454c RC |
338 | */ |
339 | ||
cd5351f4 RC |
340 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
341 | { | |
342 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
343 | |
344 | DBG("%s", omap_crtc->name); | |
345 | ||
a42133a7 | 346 | WARN_ON(omap_crtc->vblank_irq.registered); |
f5f9454c RC |
347 | omap_irq_unregister(crtc->dev, &omap_crtc->error_irq); |
348 | ||
cd5351f4 | 349 | drm_crtc_cleanup(crtc); |
f5f9454c | 350 | |
cd5351f4 RC |
351 | kfree(omap_crtc); |
352 | } | |
353 | ||
f1d57fb5 LP |
354 | static bool omap_crtc_mode_fixup(struct drm_crtc *crtc, |
355 | const struct drm_display_mode *mode, | |
356 | struct drm_display_mode *adjusted_mode) | |
357 | { | |
358 | return true; | |
359 | } | |
360 | ||
361 | static void omap_crtc_enable(struct drm_crtc *crtc) | |
cd5351f4 RC |
362 | { |
363 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
364 | ||
f1d57fb5 | 365 | DBG("%s", omap_crtc->name); |
f5f9454c | 366 | |
5f741b39 TV |
367 | rmb(); |
368 | WARN_ON(omap_crtc->pending); | |
369 | omap_crtc->pending = true; | |
370 | wmb(); | |
371 | ||
372 | omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); | |
373 | ||
f1d57fb5 | 374 | drm_crtc_vblank_on(crtc); |
cd5351f4 RC |
375 | } |
376 | ||
f1d57fb5 | 377 | static void omap_crtc_disable(struct drm_crtc *crtc) |
cd5351f4 | 378 | { |
f1d57fb5 | 379 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f1d57fb5 LP |
380 | |
381 | DBG("%s", omap_crtc->name); | |
382 | ||
f1d57fb5 | 383 | drm_crtc_vblank_off(crtc); |
cd5351f4 RC |
384 | } |
385 | ||
f7a73b65 | 386 | static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) |
cd5351f4 RC |
387 | { |
388 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f7a73b65 | 389 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
f5f9454c RC |
390 | |
391 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
f7a73b65 LP |
392 | omap_crtc->name, mode->base.id, mode->name, |
393 | mode->vrefresh, mode->clock, | |
394 | mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, | |
395 | mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal, | |
396 | mode->type, mode->flags); | |
f5f9454c RC |
397 | |
398 | copy_timings_drm_to_omap(&omap_crtc->timings, mode); | |
cd5351f4 RC |
399 | } |
400 | ||
c201d00f DV |
401 | static void omap_crtc_atomic_begin(struct drm_crtc *crtc, |
402 | struct drm_crtc_state *old_crtc_state) | |
de8e4100 | 403 | { |
fa16d262 | 404 | } |
cd5351f4 | 405 | |
c201d00f DV |
406 | static void omap_crtc_atomic_flush(struct drm_crtc *crtc, |
407 | struct drm_crtc_state *old_crtc_state) | |
fa16d262 | 408 | { |
6646dfd0 TV |
409 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
410 | ||
411 | WARN_ON(omap_crtc->vblank_irq.registered); | |
412 | ||
413 | if (dispc_mgr_is_enabled(omap_crtc->channel)) { | |
5f741b39 | 414 | |
6646dfd0 TV |
415 | DBG("%s: GO", omap_crtc->name); |
416 | ||
5f741b39 TV |
417 | rmb(); |
418 | WARN_ON(omap_crtc->pending); | |
419 | omap_crtc->pending = true; | |
420 | wmb(); | |
421 | ||
6646dfd0 TV |
422 | dispc_mgr_go(omap_crtc->channel); |
423 | omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); | |
6646dfd0 | 424 | } |
cd5351f4 RC |
425 | } |
426 | ||
6bdad6cf TV |
427 | static bool omap_crtc_is_plane_prop(struct drm_device *dev, |
428 | struct drm_property *property) | |
429 | { | |
430 | struct omap_drm_private *priv = dev->dev_private; | |
431 | ||
432 | return property == priv->zorder_prop || | |
433 | property == dev->mode_config.rotation_property; | |
434 | } | |
435 | ||
afc34932 LP |
436 | static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, |
437 | struct drm_crtc_state *state, | |
438 | struct drm_property *property, | |
439 | uint64_t val) | |
3c810c61 | 440 | { |
6bdad6cf | 441 | struct drm_device *dev = crtc->dev; |
afc34932 | 442 | |
6bdad6cf TV |
443 | if (omap_crtc_is_plane_prop(dev, property)) { |
444 | struct drm_plane_state *plane_state; | |
445 | struct drm_plane *plane = crtc->primary; | |
446 | ||
447 | /* | |
448 | * Delegate property set to the primary plane. Get the plane | |
449 | * state and set the property directly. | |
450 | */ | |
afc34932 | 451 | |
6bdad6cf TV |
452 | plane_state = drm_atomic_get_plane_state(state->state, plane); |
453 | if (IS_ERR(plane_state)) | |
454 | return PTR_ERR(plane_state); | |
afc34932 | 455 | |
6bdad6cf TV |
456 | return drm_atomic_plane_set_property(plane, plane_state, |
457 | property, val); | |
458 | } | |
459 | ||
460 | return -EINVAL; | |
afc34932 | 461 | } |
1e0fdfc2 | 462 | |
afc34932 LP |
463 | static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, |
464 | const struct drm_crtc_state *state, | |
465 | struct drm_property *property, | |
466 | uint64_t *val) | |
467 | { | |
6bdad6cf TV |
468 | struct drm_device *dev = crtc->dev; |
469 | ||
470 | if (omap_crtc_is_plane_prop(dev, property)) { | |
471 | /* | |
472 | * Delegate property get to the primary plane. The | |
473 | * drm_atomic_plane_get_property() function isn't exported, but | |
474 | * can be called through drm_object_property_get_value() as that | |
475 | * will call drm_atomic_get_property() for atomic drivers. | |
476 | */ | |
477 | return drm_object_property_get_value(&crtc->primary->base, | |
478 | property, val); | |
479 | } | |
480 | ||
481 | return -EINVAL; | |
3c810c61 RC |
482 | } |
483 | ||
cd5351f4 | 484 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
69a12263 | 485 | .reset = drm_atomic_helper_crtc_reset, |
9416c9df | 486 | .set_config = drm_atomic_helper_set_config, |
cd5351f4 | 487 | .destroy = omap_crtc_destroy, |
fa16d262 | 488 | .page_flip = drm_atomic_helper_page_flip, |
afc34932 | 489 | .set_property = drm_atomic_helper_crtc_set_property, |
69a12263 LP |
490 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, |
491 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
afc34932 LP |
492 | .atomic_set_property = omap_crtc_atomic_set_property, |
493 | .atomic_get_property = omap_crtc_atomic_get_property, | |
cd5351f4 RC |
494 | }; |
495 | ||
496 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
cd5351f4 | 497 | .mode_fixup = omap_crtc_mode_fixup, |
f7a73b65 | 498 | .mode_set_nofb = omap_crtc_mode_set_nofb, |
f1d57fb5 LP |
499 | .disable = omap_crtc_disable, |
500 | .enable = omap_crtc_enable, | |
de8e4100 LP |
501 | .atomic_begin = omap_crtc_atomic_begin, |
502 | .atomic_flush = omap_crtc_atomic_flush, | |
cd5351f4 RC |
503 | }; |
504 | ||
971fb3e5 LP |
505 | /* ----------------------------------------------------------------------------- |
506 | * Init and Cleanup | |
507 | */ | |
e2f8fd74 | 508 | |
f5f9454c | 509 | static const char *channel_names[] = { |
222025e4 LP |
510 | [OMAP_DSS_CHANNEL_LCD] = "lcd", |
511 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
512 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
513 | [OMAP_DSS_CHANNEL_LCD3] = "lcd3", | |
f5f9454c RC |
514 | }; |
515 | ||
04b1fc02 TV |
516 | void omap_crtc_pre_init(void) |
517 | { | |
518 | dss_install_mgr_ops(&mgr_ops); | |
519 | } | |
520 | ||
3a01ab25 AT |
521 | void omap_crtc_pre_uninit(void) |
522 | { | |
523 | dss_uninstall_mgr_ops(); | |
524 | } | |
525 | ||
cd5351f4 RC |
526 | /* initialize crtc */ |
527 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
f5f9454c | 528 | struct drm_plane *plane, enum omap_channel channel, int id) |
cd5351f4 RC |
529 | { |
530 | struct drm_crtc *crtc = NULL; | |
f5f9454c | 531 | struct omap_crtc *omap_crtc; |
ef6b0e02 | 532 | int ret; |
f5f9454c RC |
533 | |
534 | DBG("%s", channel_names[channel]); | |
cd5351f4 | 535 | |
f5f9454c | 536 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 537 | if (!omap_crtc) |
ef6b0e02 | 538 | return NULL; |
cd5351f4 | 539 | |
cd5351f4 | 540 | crtc = &omap_crtc->base; |
bb5c2d9a | 541 | |
5f741b39 | 542 | init_waitqueue_head(&omap_crtc->pending_wait); |
f5f9454c | 543 | |
0d8f371f | 544 | omap_crtc->channel = channel; |
0d8f371f | 545 | omap_crtc->name = channel_names[channel]; |
0d8f371f | 546 | |
a42133a7 LP |
547 | omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc); |
548 | omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq; | |
f5f9454c RC |
549 | |
550 | omap_crtc->error_irq.irqmask = | |
551 | dispc_mgr_get_sync_lost_irq(channel); | |
552 | omap_crtc->error_irq.irq = omap_crtc_error_irq; | |
553 | omap_irq_register(dev, &omap_crtc->error_irq); | |
554 | ||
ef6b0e02 | 555 | ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, |
f9882876 | 556 | &omap_crtc_funcs, NULL); |
ef6b0e02 LP |
557 | if (ret < 0) { |
558 | kfree(omap_crtc); | |
559 | return NULL; | |
560 | } | |
561 | ||
cd5351f4 RC |
562 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); |
563 | ||
ef6b0e02 | 564 | omap_plane_install_properties(crtc->primary, &crtc->base); |
3c810c61 | 565 | |
04b1fc02 TV |
566 | omap_crtcs[channel] = omap_crtc; |
567 | ||
cd5351f4 | 568 | return crtc; |
cd5351f4 | 569 | } |