Commit | Line | Data |
---|---|---|
cd5351f4 | 1 | /* |
bb5cdf8d | 2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
cd5351f4 RC |
3 | * Author: Rob Clark <rob@ti.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
69a12263 LP |
18 | #include <drm/drm_atomic.h> |
19 | #include <drm/drm_atomic_helper.h> | |
2d278f54 LP |
20 | #include <drm/drm_crtc.h> |
21 | #include <drm/drm_crtc_helper.h> | |
b9ed9f0e | 22 | #include <drm/drm_mode.h> |
3cb9ae4f | 23 | #include <drm/drm_plane_helper.h> |
a7631c4b | 24 | #include <linux/math64.h> |
2d278f54 LP |
25 | |
26 | #include "omap_drv.h" | |
cd5351f4 | 27 | |
3dfeb631 ML |
28 | #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base) |
29 | ||
30 | struct omap_crtc_state { | |
31 | /* Must be first. */ | |
32 | struct drm_crtc_state base; | |
33 | /* Shadow values for legacy userspace support. */ | |
34 | unsigned int rotation; | |
35 | unsigned int zpos; | |
36 | }; | |
37 | ||
cd5351f4 RC |
38 | #define to_omap_crtc(x) container_of(x, struct omap_crtc, base) |
39 | ||
40 | struct omap_crtc { | |
41 | struct drm_crtc base; | |
f5f9454c | 42 | |
bb5c2d9a | 43 | const char *name; |
f5f9454c | 44 | enum omap_channel channel; |
f5f9454c | 45 | |
da11bbbb | 46 | struct videomode vm; |
f5f9454c | 47 | |
a36af73f | 48 | bool ignore_digit_sync_lost; |
5f741b39 | 49 | |
f933a3a9 | 50 | bool enabled; |
5f741b39 TV |
51 | bool pending; |
52 | wait_queue_head_t pending_wait; | |
577d3983 | 53 | struct drm_pending_vblank_event *event; |
f5f9454c RC |
54 | }; |
55 | ||
971fb3e5 LP |
56 | /* ----------------------------------------------------------------------------- |
57 | * Helper Functions | |
58 | */ | |
59 | ||
4520ff28 | 60 | struct videomode *omap_crtc_timings(struct drm_crtc *crtc) |
971fb3e5 LP |
61 | { |
62 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
da11bbbb | 63 | return &omap_crtc->vm; |
971fb3e5 LP |
64 | } |
65 | ||
66 | enum omap_channel omap_crtc_channel(struct drm_crtc *crtc) | |
67 | { | |
68 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
69 | return omap_crtc->channel; | |
70 | } | |
71 | ||
d173d3dc LP |
72 | static bool omap_crtc_is_pending(struct drm_crtc *crtc) |
73 | { | |
74 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
75 | unsigned long flags; | |
76 | bool pending; | |
77 | ||
78 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | |
79 | pending = omap_crtc->pending; | |
80 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | |
81 | ||
82 | return pending; | |
83 | } | |
84 | ||
5f741b39 TV |
85 | int omap_crtc_wait_pending(struct drm_crtc *crtc) |
86 | { | |
87 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
88 | ||
61f3c40b TV |
89 | /* |
90 | * Timeout is set to a "sufficiently" high value, which should cover | |
91 | * a single frame refresh even on slower displays. | |
92 | */ | |
5f741b39 | 93 | return wait_event_timeout(omap_crtc->pending_wait, |
d173d3dc | 94 | !omap_crtc_is_pending(crtc), |
61f3c40b | 95 | msecs_to_jiffies(250)); |
5f741b39 TV |
96 | } |
97 | ||
971fb3e5 LP |
98 | /* ----------------------------------------------------------------------------- |
99 | * DSS Manager Functions | |
100 | */ | |
101 | ||
f5f9454c RC |
102 | /* |
103 | * Manager-ops, callbacks from output when they need to configure | |
104 | * the upstream part of the video pipe. | |
105 | * | |
106 | * Most of these we can ignore until we add support for command-mode | |
107 | * panels.. for video-mode the crtc-helpers already do an adequate | |
108 | * job of sequencing the setup of the video pipe in the proper order | |
109 | */ | |
110 | ||
04b1fc02 TV |
111 | /* ovl-mgr-id -> crtc */ |
112 | static struct omap_crtc *omap_crtcs[8]; | |
3a924138 | 113 | static struct omap_dss_device *omap_crtc_output[8]; |
04b1fc02 | 114 | |
f5f9454c | 115 | /* we can probably ignore these until we support command-mode panels: */ |
e5cbb6e8 | 116 | static int omap_crtc_dss_connect(enum omap_channel channel, |
1f68d9c4 | 117 | struct omap_dss_device *dst) |
a7e71e7f | 118 | { |
9f759225 TV |
119 | const struct dispc_ops *dispc_ops = dispc_get_ops(); |
120 | ||
e5cbb6e8 | 121 | if (omap_crtc_output[channel]) |
a7e71e7f TV |
122 | return -EINVAL; |
123 | ||
9f759225 | 124 | if ((dispc_ops->mgr_get_supported_outputs(channel) & dst->id) == 0) |
a7e71e7f TV |
125 | return -EINVAL; |
126 | ||
e5cbb6e8 | 127 | omap_crtc_output[channel] = dst; |
49239503 | 128 | dst->dispc_channel_connected = true; |
a7e71e7f TV |
129 | |
130 | return 0; | |
131 | } | |
132 | ||
e5cbb6e8 | 133 | static void omap_crtc_dss_disconnect(enum omap_channel channel, |
1f68d9c4 | 134 | struct omap_dss_device *dst) |
a7e71e7f | 135 | { |
e5cbb6e8 | 136 | omap_crtc_output[channel] = NULL; |
49239503 | 137 | dst->dispc_channel_connected = false; |
a7e71e7f TV |
138 | } |
139 | ||
e5cbb6e8 | 140 | static void omap_crtc_dss_start_update(enum omap_channel channel) |
f5f9454c RC |
141 | { |
142 | } | |
143 | ||
4029755e | 144 | /* Called only from the encoder enable/disable and suspend/resume handlers. */ |
8472b570 LP |
145 | static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) |
146 | { | |
147 | struct drm_device *dev = crtc->dev; | |
9f759225 | 148 | struct omap_drm_private *priv = dev->dev_private; |
8472b570 LP |
149 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
150 | enum omap_channel channel = omap_crtc->channel; | |
151 | struct omap_irq_wait *wait; | |
152 | u32 framedone_irq, vsync_irq; | |
153 | int ret; | |
154 | ||
03af8157 LP |
155 | if (WARN_ON(omap_crtc->enabled == enable)) |
156 | return; | |
157 | ||
3a924138 | 158 | if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { |
9f759225 | 159 | priv->dispc_ops->mgr_enable(channel, enable); |
f933a3a9 | 160 | omap_crtc->enabled = enable; |
4e4b53ce TV |
161 | return; |
162 | } | |
163 | ||
ef422283 TV |
164 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
165 | /* | |
166 | * Digit output produces some sync lost interrupts during the | |
167 | * first frame when enabling, so we need to ignore those. | |
168 | */ | |
169 | omap_crtc->ignore_digit_sync_lost = true; | |
170 | } | |
8472b570 | 171 | |
9f759225 TV |
172 | framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel); |
173 | vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel); | |
8472b570 LP |
174 | |
175 | if (enable) { | |
176 | wait = omap_irq_wait_init(dev, vsync_irq, 1); | |
177 | } else { | |
178 | /* | |
179 | * When we disable the digit output, we need to wait for | |
180 | * FRAMEDONE to know that DISPC has finished with the output. | |
181 | * | |
182 | * OMAP2/3 does not have FRAMEDONE irq for digit output, and in | |
183 | * that case we need to use vsync interrupt, and wait for both | |
184 | * even and odd frames. | |
185 | */ | |
186 | ||
187 | if (framedone_irq) | |
188 | wait = omap_irq_wait_init(dev, framedone_irq, 1); | |
189 | else | |
190 | wait = omap_irq_wait_init(dev, vsync_irq, 2); | |
191 | } | |
192 | ||
9f759225 | 193 | priv->dispc_ops->mgr_enable(channel, enable); |
f933a3a9 | 194 | omap_crtc->enabled = enable; |
8472b570 LP |
195 | |
196 | ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); | |
197 | if (ret) { | |
198 | dev_err(dev->dev, "%s: timeout waiting for %s\n", | |
199 | omap_crtc->name, enable ? "enable" : "disable"); | |
200 | } | |
201 | ||
ef422283 TV |
202 | if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) { |
203 | omap_crtc->ignore_digit_sync_lost = false; | |
204 | /* make sure the irq handler sees the value above */ | |
205 | mb(); | |
206 | } | |
8472b570 LP |
207 | } |
208 | ||
506096a1 | 209 | |
e5cbb6e8 | 210 | static int omap_crtc_dss_enable(enum omap_channel channel) |
f5f9454c | 211 | { |
e5cbb6e8 | 212 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
9f759225 | 213 | struct omap_drm_private *priv = omap_crtc->base.dev->dev_private; |
506096a1 | 214 | |
9f759225 | 215 | priv->dispc_ops->mgr_set_timings(omap_crtc->channel, &omap_crtc->vm); |
8472b570 | 216 | omap_crtc_set_enabled(&omap_crtc->base, true); |
506096a1 | 217 | |
f5f9454c RC |
218 | return 0; |
219 | } | |
220 | ||
e5cbb6e8 | 221 | static void omap_crtc_dss_disable(enum omap_channel channel) |
f5f9454c | 222 | { |
e5cbb6e8 | 223 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
506096a1 | 224 | |
8472b570 | 225 | omap_crtc_set_enabled(&omap_crtc->base, false); |
f5f9454c RC |
226 | } |
227 | ||
e5cbb6e8 | 228 | static void omap_crtc_dss_set_timings(enum omap_channel channel, |
da11bbbb | 229 | const struct videomode *vm) |
f5f9454c | 230 | { |
e5cbb6e8 | 231 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
f5f9454c | 232 | DBG("%s", omap_crtc->name); |
da11bbbb | 233 | omap_crtc->vm = *vm; |
f5f9454c RC |
234 | } |
235 | ||
e5cbb6e8 | 236 | static void omap_crtc_dss_set_lcd_config(enum omap_channel channel, |
f5f9454c RC |
237 | const struct dss_lcd_mgr_config *config) |
238 | { | |
e5cbb6e8 | 239 | struct omap_crtc *omap_crtc = omap_crtcs[channel]; |
9f759225 TV |
240 | struct omap_drm_private *priv = omap_crtc->base.dev->dev_private; |
241 | ||
f5f9454c | 242 | DBG("%s", omap_crtc->name); |
9f759225 | 243 | priv->dispc_ops->mgr_set_lcd_config(omap_crtc->channel, config); |
f5f9454c RC |
244 | } |
245 | ||
4343f0f8 | 246 | static int omap_crtc_dss_register_framedone( |
e5cbb6e8 | 247 | enum omap_channel channel, |
f5f9454c RC |
248 | void (*handler)(void *), void *data) |
249 | { | |
250 | return 0; | |
251 | } | |
252 | ||
4343f0f8 | 253 | static void omap_crtc_dss_unregister_framedone( |
e5cbb6e8 | 254 | enum omap_channel channel, |
f5f9454c RC |
255 | void (*handler)(void *), void *data) |
256 | { | |
257 | } | |
258 | ||
259 | static const struct dss_mgr_ops mgr_ops = { | |
4343f0f8 LP |
260 | .connect = omap_crtc_dss_connect, |
261 | .disconnect = omap_crtc_dss_disconnect, | |
262 | .start_update = omap_crtc_dss_start_update, | |
263 | .enable = omap_crtc_dss_enable, | |
264 | .disable = omap_crtc_dss_disable, | |
265 | .set_timings = omap_crtc_dss_set_timings, | |
266 | .set_lcd_config = omap_crtc_dss_set_lcd_config, | |
267 | .register_framedone_handler = omap_crtc_dss_register_framedone, | |
268 | .unregister_framedone_handler = omap_crtc_dss_unregister_framedone, | |
cd5351f4 RC |
269 | }; |
270 | ||
971fb3e5 | 271 | /* ----------------------------------------------------------------------------- |
1d5e5ea1 | 272 | * Setup, Flush and Page Flip |
971fb3e5 LP |
273 | */ |
274 | ||
dfe9cfcc | 275 | void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus) |
971fb3e5 | 276 | { |
e0519af7 | 277 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
a36af73f TV |
278 | |
279 | if (omap_crtc->ignore_digit_sync_lost) { | |
280 | irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
281 | if (!irqstatus) | |
282 | return; | |
283 | } | |
284 | ||
3b143fc8 | 285 | DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus); |
971fb3e5 LP |
286 | } |
287 | ||
14389a37 | 288 | void omap_crtc_vblank_irq(struct drm_crtc *crtc) |
971fb3e5 | 289 | { |
14389a37 | 290 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
9f759225 TV |
291 | struct drm_device *dev = omap_crtc->base.dev; |
292 | struct omap_drm_private *priv = dev->dev_private; | |
14389a37 | 293 | bool pending; |
971fb3e5 | 294 | |
14389a37 LP |
295 | spin_lock(&crtc->dev->event_lock); |
296 | /* | |
297 | * If the dispc is busy we're racing the flush operation. Try again on | |
298 | * the next vblank interrupt. | |
299 | */ | |
9f759225 | 300 | if (priv->dispc_ops->mgr_go_busy(omap_crtc->channel)) { |
14389a37 | 301 | spin_unlock(&crtc->dev->event_lock); |
a42133a7 | 302 | return; |
14389a37 | 303 | } |
a42133a7 | 304 | |
14389a37 LP |
305 | /* Send the vblank event if one has been requested. */ |
306 | if (omap_crtc->event) { | |
307 | drm_crtc_send_vblank_event(crtc, omap_crtc->event); | |
308 | omap_crtc->event = NULL; | |
309 | } | |
a42133a7 | 310 | |
14389a37 | 311 | pending = omap_crtc->pending; |
5f741b39 | 312 | omap_crtc->pending = false; |
d173d3dc | 313 | spin_unlock(&crtc->dev->event_lock); |
5f741b39 | 314 | |
14389a37 LP |
315 | if (pending) |
316 | drm_crtc_vblank_put(crtc); | |
a42133a7 | 317 | |
14389a37 | 318 | /* Wake up omap_atomic_complete. */ |
5f741b39 | 319 | wake_up(&omap_crtc->pending_wait); |
14389a37 LP |
320 | |
321 | DBG("%s: apply done", omap_crtc->name); | |
971fb3e5 LP |
322 | } |
323 | ||
7e3d9274 TV |
324 | static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) |
325 | { | |
9f759225 | 326 | struct omap_drm_private *priv = crtc->dev->dev_private; |
7e3d9274 TV |
327 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
328 | struct omap_overlay_manager_info info; | |
329 | ||
330 | memset(&info, 0, sizeof(info)); | |
331 | ||
332 | info.default_color = 0x000000; | |
333 | info.trans_enabled = false; | |
334 | info.partial_alpha_enabled = false; | |
335 | info.cpr_enable = false; | |
336 | ||
9f759225 | 337 | priv->dispc_ops->mgr_setup(omap_crtc->channel, &info); |
7e3d9274 TV |
338 | } |
339 | ||
971fb3e5 LP |
340 | /* ----------------------------------------------------------------------------- |
341 | * CRTC Functions | |
f5f9454c RC |
342 | */ |
343 | ||
cd5351f4 RC |
344 | static void omap_crtc_destroy(struct drm_crtc *crtc) |
345 | { | |
346 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f5f9454c RC |
347 | |
348 | DBG("%s", omap_crtc->name); | |
349 | ||
cd5351f4 | 350 | drm_crtc_cleanup(crtc); |
f5f9454c | 351 | |
cd5351f4 RC |
352 | kfree(omap_crtc); |
353 | } | |
354 | ||
ce9a8f1a LP |
355 | static void omap_crtc_arm_event(struct drm_crtc *crtc) |
356 | { | |
357 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
358 | ||
359 | WARN_ON(omap_crtc->pending); | |
360 | omap_crtc->pending = true; | |
361 | ||
362 | if (crtc->state->event) { | |
363 | omap_crtc->event = crtc->state->event; | |
364 | crtc->state->event = NULL; | |
365 | } | |
366 | } | |
367 | ||
0b20a0f8 LP |
368 | static void omap_crtc_atomic_enable(struct drm_crtc *crtc, |
369 | struct drm_crtc_state *old_state) | |
cd5351f4 RC |
370 | { |
371 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
14389a37 | 372 | int ret; |
cd5351f4 | 373 | |
f1d57fb5 | 374 | DBG("%s", omap_crtc->name); |
f5f9454c | 375 | |
d173d3dc | 376 | spin_lock_irq(&crtc->dev->event_lock); |
14389a37 LP |
377 | drm_crtc_vblank_on(crtc); |
378 | ret = drm_crtc_vblank_get(crtc); | |
379 | WARN_ON(ret != 0); | |
380 | ||
ce9a8f1a | 381 | omap_crtc_arm_event(crtc); |
d173d3dc | 382 | spin_unlock_irq(&crtc->dev->event_lock); |
cd5351f4 RC |
383 | } |
384 | ||
64581714 LP |
385 | static void omap_crtc_atomic_disable(struct drm_crtc *crtc, |
386 | struct drm_crtc_state *old_state) | |
cd5351f4 | 387 | { |
f1d57fb5 | 388 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
f1d57fb5 LP |
389 | |
390 | DBG("%s", omap_crtc->name); | |
391 | ||
ce9a8f1a LP |
392 | spin_lock_irq(&crtc->dev->event_lock); |
393 | if (crtc->state->event) { | |
394 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
395 | crtc->state->event = NULL; | |
396 | } | |
397 | spin_unlock_irq(&crtc->dev->event_lock); | |
398 | ||
f1d57fb5 | 399 | drm_crtc_vblank_off(crtc); |
cd5351f4 RC |
400 | } |
401 | ||
a7631c4b PU |
402 | static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, |
403 | const struct drm_display_mode *mode) | |
404 | { | |
405 | struct omap_drm_private *priv = crtc->dev->dev_private; | |
406 | ||
407 | /* Check for bandwidth limit */ | |
408 | if (priv->max_bandwidth) { | |
409 | /* | |
410 | * Estimation for the bandwidth need of a given mode with one | |
411 | * full screen plane: | |
412 | * bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal)) | |
413 | * ^^ Refresh rate ^^ | |
414 | * | |
415 | * The interlaced mode is taken into account by using the | |
416 | * pixelclock in the calculation. | |
417 | * | |
418 | * The equation is rearranged for 64bit arithmetic. | |
419 | */ | |
420 | uint64_t bandwidth = mode->clock * 1000; | |
421 | unsigned int bpp = 4; | |
422 | ||
423 | bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; | |
424 | bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); | |
425 | ||
426 | /* | |
427 | * Reject modes which would need more bandwidth if used with one | |
428 | * full resolution plane (most common use case). | |
429 | */ | |
430 | if (priv->max_bandwidth < bandwidth) | |
431 | return MODE_BAD; | |
432 | } | |
433 | ||
434 | return MODE_OK; | |
435 | } | |
436 | ||
f7a73b65 | 437 | static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc) |
cd5351f4 RC |
438 | { |
439 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); | |
f7a73b65 | 440 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
50fa9f0b TV |
441 | struct omap_drm_private *priv = crtc->dev->dev_private; |
442 | const u32 flags_mask = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_DE_LOW | | |
443 | DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_PIXDATA_NEGEDGE | | |
444 | DISPLAY_FLAGS_SYNC_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE; | |
445 | unsigned int i; | |
f5f9454c RC |
446 | |
447 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
f7a73b65 LP |
448 | omap_crtc->name, mode->base.id, mode->name, |
449 | mode->vrefresh, mode->clock, | |
450 | mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal, | |
451 | mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal, | |
452 | mode->type, mode->flags); | |
f5f9454c | 453 | |
da11bbbb | 454 | drm_display_mode_to_videomode(mode, &omap_crtc->vm); |
50fa9f0b TV |
455 | |
456 | /* | |
457 | * HACK: This fixes the vm flags. | |
458 | * struct drm_display_mode does not contain the VSYNC/HSYNC/DE flags | |
459 | * and they get lost when converting back and forth between | |
460 | * struct drm_display_mode and struct videomode. The hack below | |
461 | * goes and fetches the missing flags from the panel drivers. | |
462 | * | |
463 | * Correct solution would be to use DRM's bus-flags, but that's not | |
464 | * easily possible before the omapdrm's panel/encoder driver model | |
465 | * has been changed to the DRM model. | |
466 | */ | |
467 | ||
468 | for (i = 0; i < priv->num_encoders; ++i) { | |
469 | struct drm_encoder *encoder = priv->encoders[i]; | |
470 | ||
471 | if (encoder->crtc == crtc) { | |
472 | struct omap_dss_device *dssdev; | |
473 | ||
474 | dssdev = omap_encoder_get_dssdev(encoder); | |
475 | ||
476 | if (dssdev) { | |
477 | struct videomode vm = {0}; | |
478 | ||
479 | dssdev->driver->get_timings(dssdev, &vm); | |
480 | ||
481 | omap_crtc->vm.flags |= vm.flags & flags_mask; | |
482 | } | |
483 | ||
484 | break; | |
485 | } | |
486 | } | |
cd5351f4 RC |
487 | } |
488 | ||
492a426a JS |
489 | static int omap_crtc_atomic_check(struct drm_crtc *crtc, |
490 | struct drm_crtc_state *state) | |
491 | { | |
3dfeb631 ML |
492 | struct drm_plane_state *pri_state; |
493 | ||
492a426a | 494 | if (state->color_mgmt_changed && state->gamma_lut) { |
dfe9cfcc | 495 | unsigned int length = state->gamma_lut->length / |
492a426a JS |
496 | sizeof(struct drm_color_lut); |
497 | ||
498 | if (length < 2) | |
499 | return -EINVAL; | |
500 | } | |
501 | ||
3dfeb631 ML |
502 | pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary); |
503 | if (pri_state) { | |
504 | struct omap_crtc_state *omap_crtc_state = | |
505 | to_omap_crtc_state(state); | |
506 | ||
507 | /* Mirror new values for zpos and rotation in omap_crtc_state */ | |
508 | omap_crtc_state->zpos = pri_state->zpos; | |
509 | omap_crtc_state->rotation = pri_state->rotation; | |
510 | } | |
511 | ||
492a426a JS |
512 | return 0; |
513 | } | |
514 | ||
c201d00f | 515 | static void omap_crtc_atomic_begin(struct drm_crtc *crtc, |
577d3983 | 516 | struct drm_crtc_state *old_crtc_state) |
de8e4100 | 517 | { |
fa16d262 | 518 | } |
cd5351f4 | 519 | |
c201d00f | 520 | static void omap_crtc_atomic_flush(struct drm_crtc *crtc, |
577d3983 | 521 | struct drm_crtc_state *old_crtc_state) |
fa16d262 | 522 | { |
9f759225 | 523 | struct omap_drm_private *priv = crtc->dev->dev_private; |
6646dfd0 | 524 | struct omap_crtc *omap_crtc = to_omap_crtc(crtc); |
14389a37 | 525 | int ret; |
6646dfd0 | 526 | |
492a426a JS |
527 | if (crtc->state->color_mgmt_changed) { |
528 | struct drm_color_lut *lut = NULL; | |
dfe9cfcc | 529 | unsigned int length = 0; |
492a426a JS |
530 | |
531 | if (crtc->state->gamma_lut) { | |
532 | lut = (struct drm_color_lut *) | |
533 | crtc->state->gamma_lut->data; | |
534 | length = crtc->state->gamma_lut->length / | |
535 | sizeof(*lut); | |
536 | } | |
9f759225 | 537 | priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length); |
492a426a JS |
538 | } |
539 | ||
7e3d9274 TV |
540 | omap_crtc_write_crtc_properties(crtc); |
541 | ||
e025d386 | 542 | /* Only flush the CRTC if it is currently enabled. */ |
f933a3a9 LP |
543 | if (!omap_crtc->enabled) |
544 | return; | |
5f741b39 | 545 | |
f933a3a9 | 546 | DBG("%s: GO", omap_crtc->name); |
6646dfd0 | 547 | |
14389a37 LP |
548 | ret = drm_crtc_vblank_get(crtc); |
549 | WARN_ON(ret != 0); | |
550 | ||
d173d3dc | 551 | spin_lock_irq(&crtc->dev->event_lock); |
9f759225 | 552 | priv->dispc_ops->mgr_go(omap_crtc->channel); |
ce9a8f1a | 553 | omap_crtc_arm_event(crtc); |
d173d3dc | 554 | spin_unlock_irq(&crtc->dev->event_lock); |
cd5351f4 RC |
555 | } |
556 | ||
afc34932 LP |
557 | static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, |
558 | struct drm_crtc_state *state, | |
559 | struct drm_property *property, | |
dfe9cfcc | 560 | u64 val) |
3c810c61 | 561 | { |
3dfeb631 ML |
562 | struct omap_drm_private *priv = crtc->dev->dev_private; |
563 | struct drm_plane_state *plane_state; | |
afc34932 | 564 | |
3dfeb631 ML |
565 | /* |
566 | * Delegate property set to the primary plane. Get the plane state and | |
567 | * set the property directly, the shadow copy will be assigned in the | |
568 | * omap_crtc_atomic_check callback. This way updates to plane state will | |
569 | * always be mirrored in the crtc state correctly. | |
570 | */ | |
571 | plane_state = drm_atomic_get_plane_state(state->state, crtc->primary); | |
572 | if (IS_ERR(plane_state)) | |
573 | return PTR_ERR(plane_state); | |
574 | ||
575 | if (property == crtc->primary->rotation_property) | |
576 | plane_state->rotation = val; | |
577 | else if (property == priv->zorder_prop) | |
578 | plane_state->zpos = val; | |
579 | else | |
580 | return -EINVAL; | |
6bdad6cf | 581 | |
3dfeb631 | 582 | return 0; |
afc34932 | 583 | } |
1e0fdfc2 | 584 | |
afc34932 LP |
585 | static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, |
586 | const struct drm_crtc_state *state, | |
587 | struct drm_property *property, | |
dfe9cfcc | 588 | u64 *val) |
afc34932 | 589 | { |
3dfeb631 ML |
590 | struct omap_drm_private *priv = crtc->dev->dev_private; |
591 | struct omap_crtc_state *omap_state = to_omap_crtc_state(state); | |
592 | ||
593 | if (property == crtc->primary->rotation_property) | |
594 | *val = omap_state->rotation; | |
595 | else if (property == priv->zorder_prop) | |
596 | *val = omap_state->zpos; | |
597 | else | |
598 | return -EINVAL; | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
603 | static void omap_crtc_reset(struct drm_crtc *crtc) | |
604 | { | |
605 | if (crtc->state) | |
606 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
607 | ||
608 | kfree(crtc->state); | |
609 | crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL); | |
610 | ||
611 | if (crtc->state) | |
612 | crtc->state->crtc = crtc; | |
613 | } | |
614 | ||
615 | static struct drm_crtc_state * | |
616 | omap_crtc_duplicate_state(struct drm_crtc *crtc) | |
617 | { | |
618 | struct omap_crtc_state *state, *current_state; | |
619 | ||
620 | if (WARN_ON(!crtc->state)) | |
621 | return NULL; | |
622 | ||
623 | current_state = to_omap_crtc_state(crtc->state); | |
624 | ||
625 | state = kmalloc(sizeof(*state), GFP_KERNEL); | |
2419672f DC |
626 | if (!state) |
627 | return NULL; | |
628 | ||
629 | __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); | |
3dfeb631 ML |
630 | |
631 | state->zpos = current_state->zpos; | |
632 | state->rotation = current_state->rotation; | |
6bdad6cf | 633 | |
3dfeb631 | 634 | return &state->base; |
3c810c61 RC |
635 | } |
636 | ||
cd5351f4 | 637 | static const struct drm_crtc_funcs omap_crtc_funcs = { |
3dfeb631 | 638 | .reset = omap_crtc_reset, |
9416c9df | 639 | .set_config = drm_atomic_helper_set_config, |
cd5351f4 | 640 | .destroy = omap_crtc_destroy, |
fa16d262 | 641 | .page_flip = drm_atomic_helper_page_flip, |
492a426a | 642 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
3dfeb631 | 643 | .atomic_duplicate_state = omap_crtc_duplicate_state, |
69a12263 | 644 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, |
afc34932 LP |
645 | .atomic_set_property = omap_crtc_atomic_set_property, |
646 | .atomic_get_property = omap_crtc_atomic_get_property, | |
0396162a TV |
647 | .enable_vblank = omap_irq_enable_vblank, |
648 | .disable_vblank = omap_irq_disable_vblank, | |
cd5351f4 RC |
649 | }; |
650 | ||
651 | static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = { | |
f7a73b65 | 652 | .mode_set_nofb = omap_crtc_mode_set_nofb, |
492a426a | 653 | .atomic_check = omap_crtc_atomic_check, |
de8e4100 LP |
654 | .atomic_begin = omap_crtc_atomic_begin, |
655 | .atomic_flush = omap_crtc_atomic_flush, | |
0b20a0f8 | 656 | .atomic_enable = omap_crtc_atomic_enable, |
64581714 | 657 | .atomic_disable = omap_crtc_atomic_disable, |
a7631c4b | 658 | .mode_valid = omap_crtc_mode_valid, |
cd5351f4 RC |
659 | }; |
660 | ||
971fb3e5 LP |
661 | /* ----------------------------------------------------------------------------- |
662 | * Init and Cleanup | |
663 | */ | |
e2f8fd74 | 664 | |
f5f9454c | 665 | static const char *channel_names[] = { |
222025e4 LP |
666 | [OMAP_DSS_CHANNEL_LCD] = "lcd", |
667 | [OMAP_DSS_CHANNEL_DIGIT] = "tv", | |
668 | [OMAP_DSS_CHANNEL_LCD2] = "lcd2", | |
669 | [OMAP_DSS_CHANNEL_LCD3] = "lcd3", | |
f5f9454c RC |
670 | }; |
671 | ||
04b1fc02 TV |
672 | void omap_crtc_pre_init(void) |
673 | { | |
e8e13b15 JS |
674 | memset(omap_crtcs, 0, sizeof(omap_crtcs)); |
675 | ||
04b1fc02 TV |
676 | dss_install_mgr_ops(&mgr_ops); |
677 | } | |
678 | ||
3a01ab25 AT |
679 | void omap_crtc_pre_uninit(void) |
680 | { | |
681 | dss_uninstall_mgr_ops(); | |
682 | } | |
683 | ||
cd5351f4 RC |
684 | /* initialize crtc */ |
685 | struct drm_crtc *omap_crtc_init(struct drm_device *dev, | |
e8e13b15 | 686 | struct drm_plane *plane, struct omap_dss_device *dssdev) |
cd5351f4 | 687 | { |
9f759225 | 688 | struct omap_drm_private *priv = dev->dev_private; |
cd5351f4 | 689 | struct drm_crtc *crtc = NULL; |
f5f9454c | 690 | struct omap_crtc *omap_crtc; |
e8e13b15 JS |
691 | enum omap_channel channel; |
692 | struct omap_dss_device *out; | |
ef6b0e02 | 693 | int ret; |
f5f9454c | 694 | |
e8e13b15 JS |
695 | out = omapdss_find_output_from_display(dssdev); |
696 | channel = out->dispc_channel; | |
697 | omap_dss_put_device(out); | |
698 | ||
f5f9454c | 699 | DBG("%s", channel_names[channel]); |
cd5351f4 | 700 | |
e8e13b15 JS |
701 | /* Multiple displays on same channel is not allowed */ |
702 | if (WARN_ON(omap_crtcs[channel] != NULL)) | |
703 | return ERR_PTR(-EINVAL); | |
704 | ||
f5f9454c | 705 | omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL); |
78110bb8 | 706 | if (!omap_crtc) |
e8e13b15 | 707 | return ERR_PTR(-ENOMEM); |
cd5351f4 | 708 | |
cd5351f4 | 709 | crtc = &omap_crtc->base; |
bb5c2d9a | 710 | |
5f741b39 | 711 | init_waitqueue_head(&omap_crtc->pending_wait); |
f5f9454c | 712 | |
0d8f371f | 713 | omap_crtc->channel = channel; |
0d8f371f | 714 | omap_crtc->name = channel_names[channel]; |
0d8f371f | 715 | |
ef6b0e02 | 716 | ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, |
f9882876 | 717 | &omap_crtc_funcs, NULL); |
ef6b0e02 | 718 | if (ret < 0) { |
e8e13b15 JS |
719 | dev_err(dev->dev, "%s(): could not init crtc for: %s\n", |
720 | __func__, dssdev->name); | |
ef6b0e02 | 721 | kfree(omap_crtc); |
e8e13b15 | 722 | return ERR_PTR(ret); |
ef6b0e02 LP |
723 | } |
724 | ||
cd5351f4 RC |
725 | drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs); |
726 | ||
492a426a JS |
727 | /* The dispc API adapts to what ever size, but the HW supports |
728 | * 256 element gamma table for LCDs and 1024 element table for | |
729 | * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma | |
730 | * tables so lets use that. Size of HW gamma table can be | |
731 | * extracted with dispc_mgr_gamma_size(). If it returns 0 | |
732 | * gamma table is not supprted. | |
733 | */ | |
9f759225 | 734 | if (priv->dispc_ops->mgr_gamma_size(channel)) { |
dfe9cfcc | 735 | unsigned int gamma_lut_size = 256; |
492a426a JS |
736 | |
737 | drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size); | |
738 | drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); | |
739 | } | |
740 | ||
ef6b0e02 | 741 | omap_plane_install_properties(crtc->primary, &crtc->base); |
3c810c61 | 742 | |
04b1fc02 TV |
743 | omap_crtcs[channel] = omap_crtc; |
744 | ||
cd5351f4 | 745 | return crtc; |
cd5351f4 | 746 | } |