[linux-2.6-block.git] / drivers / gpu / drm / omapdrm / dss / hdmi_wp.c

/*
 * HDMI wrapper
 *
 * Copyright (C) 2013 Texas Instruments Incorporated
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */

#define DSS_SUBSYS_NAME "HDMIWP"

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <video/omapdss.h>

#include "dss.h"
#include "hdmi.h"

void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))

	DUMPREG(HDMI_WP_REVISION);
	DUMPREG(HDMI_WP_SYSCONFIG);
	DUMPREG(HDMI_WP_IRQSTATUS_RAW);
	DUMPREG(HDMI_WP_IRQSTATUS);
	DUMPREG(HDMI_WP_IRQENABLE_SET);
	DUMPREG(HDMI_WP_IRQENABLE_CLR);
	DUMPREG(HDMI_WP_IRQWAKEEN);
	DUMPREG(HDMI_WP_PWR_CTRL);
	DUMPREG(HDMI_WP_DEBOUNCE);
	DUMPREG(HDMI_WP_VIDEO_CFG);
	DUMPREG(HDMI_WP_VIDEO_SIZE);
	DUMPREG(HDMI_WP_VIDEO_TIMING_H);
	DUMPREG(HDMI_WP_VIDEO_TIMING_V);
	DUMPREG(HDMI_WP_CLK);
	DUMPREG(HDMI_WP_AUDIO_CFG);
	DUMPREG(HDMI_WP_AUDIO_CFG2);
	DUMPREG(HDMI_WP_AUDIO_CTRL);
	DUMPREG(HDMI_WP_AUDIO_DATA);
}

u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
{
	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
}

void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
{
	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
	/* flush posted write */
	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
}

void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
{
	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
}

void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
{
	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
}

/* PHY_PWR_CMD */
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
{
	/* Return if already the state */
	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
		return 0;

	/* Command for power control of HDMI PHY */
	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);

	/* Status of the power control of HDMI PHY */
	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
			!= val) {
		DSSERR("Failed to set PHY power mode to %d\n", val);
		return -ETIMEDOUT;
	}

	return 0;
}

/* PLL_PWR_CMD */
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
{
	/* Command for power control of HDMI PLL */
	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);

	/* wait till PHY_PWR_STATUS is set */
	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
			!= val) {
		DSSERR("Failed to set PLL_PWR_STATUS\n");
		return -ETIMEDOUT;
	}

	return 0;
}

int hdmi_wp_video_start(struct hdmi_wp_data *wp)
{
	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);

	return 0;
}

void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
{
	int i;

	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);

	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);

	for (i = 0; i < 50; ++i) {
		u32 v;

		msleep(20);

		v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
		if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
			return;
	}

	DSSERR("no HDMI FRAMEDONE when disabling output\n");
}

void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
		struct hdmi_video_format *video_fmt)
{
	u32 l = 0;

	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
		10, 8);

	l |= FLD_VAL(video_fmt->y_res, 31, 16);
	l |= FLD_VAL(video_fmt->x_res, 15, 0);
	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
}

void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
		struct omap_video_timings *timings)
{
	u32 r;
	bool vsync_pol, hsync_pol;
	DSSDBG("Enter hdmi_wp_video_config_interface\n");

	vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
	hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;

	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
	r = FLD_MOD(r, vsync_pol, 7, 7);
	r = FLD_MOD(r, hsync_pol, 6, 6);
	r = FLD_MOD(r, timings->interlace, 3, 3);
	r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
}

void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
		struct omap_video_timings *timings)
{
	u32 timing_h = 0;
	u32 timing_v = 0;
	unsigned hsw_offset = 1;

	DSSDBG("Enter hdmi_wp_video_config_timing\n");

	/*
	 * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
	 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1.
	 * However, we don't support OMAP5 ES1 at all, so we can just check for
	 * OMAP4 here.
	 */
	if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
	    omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
	    omapdss_get_version() == OMAPDSS_VER_OMAP4)
		hsw_offset = 0;

	timing_h |= FLD_VAL(timings->hbp, 31, 20);
	timing_h |= FLD_VAL(timings->hfp, 19, 8);
	timing_h |= FLD_VAL(timings->hsw - hsw_offset, 7, 0);
	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);

	timing_v |= FLD_VAL(timings->vbp, 31, 20);
	timing_v |= FLD_VAL(timings->vfp, 19, 8);
	timing_v |= FLD_VAL(timings->vsw, 7, 0);
	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
}

void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
		struct omap_video_timings *timings, struct hdmi_config *param)
{
	DSSDBG("Enter hdmi_wp_video_init_format\n");

	video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
	video_fmt->y_res = param->timings.y_res;
	video_fmt->x_res = param->timings.x_res;

	timings->hbp = param->timings.hbp;
	timings->hfp = param->timings.hfp;
	timings->hsw = param->timings.hsw;
	timings->vbp = param->timings.vbp;
	timings->vfp = param->timings.vfp;
	timings->vsw = param->timings.vsw;

	timings->vsync_level = param->timings.vsync_level;
	timings->hsync_level = param->timings.hsync_level;
	timings->interlace = param->timings.interlace;
	timings->double_pixel = param->timings.double_pixel;

	if (param->timings.interlace) {
		video_fmt->y_res /= 2;
		timings->vbp /= 2;
		timings->vfp /= 2;
		timings->vsw /= 2;
	}

	if (param->timings.double_pixel) {
		video_fmt->x_res *= 2;
		timings->hfp *= 2;
		timings->hsw *= 2;
		timings->hbp *= 2;
	}
}

void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
		struct hdmi_audio_format *aud_fmt)
{
	u32 r;

	DSSDBG("Enter hdmi_wp_audio_config_format\n");

	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
	if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
	    omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
	    omapdss_get_version() == OMAPDSS_VER_OMAP4) {
		r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
		r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
	}
	r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
	r = FLD_MOD(r, aud_fmt->type, 4, 4);
	r = FLD_MOD(r, aud_fmt->justification, 3, 3);
	r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
	r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
	r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
}

void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
		struct hdmi_audio_dma *aud_dma)
{
	u32 r;

	DSSDBG("Enter hdmi_wp_audio_config_dma\n");

	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
	r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
	r = FLD_MOD(r, aud_dma->block_size, 7, 0);
	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);

	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
	r = FLD_MOD(r, aud_dma->mode, 9, 9);
	r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
}

int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
{
	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);

	return 0;
}

int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
{
	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);

	return 0;
}

int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
{
	struct resource *res;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
	if (!res) {
		DSSERR("can't get WP mem resource\n");
		return -EINVAL;
	}
	wp->phys_base = res->start;

	wp->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wp->base)) {
		DSSERR("can't ioremap HDMI WP\n");
		return PTR_ERR(wp->base);
	}

	return 0;
}

phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
{
	return wp->phys_base + HDMI_WP_AUDIO_DATA;
}
Commit	Line	Data
f382d9eb AT	1	/*
	2	* HDMI wrapper
	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*/
	10
ac9f2421 TV	11	#define DSS_SUBSYS_NAME "HDMIWP"
ac9f2421 TV	12
f382d9eb	13	#include <linux/kernel.h>
f382d9eb AT	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/platform_device.h>
2d802453	17	#include <linux/seq_file.h>
f382d9eb AT	18	#include <video/omapdss.h>
	19
	20	#include "dss.h"
ef26958a	21	#include "hdmi.h"
f382d9eb AT	22
	23	void hdmi_wp_dump(struct hdmi_wp_data wp, struct seq_file s)
	24	{
	25	#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
	26
	27	DUMPREG(HDMI_WP_REVISION);
	28	DUMPREG(HDMI_WP_SYSCONFIG);
	29	DUMPREG(HDMI_WP_IRQSTATUS_RAW);
	30	DUMPREG(HDMI_WP_IRQSTATUS);
	31	DUMPREG(HDMI_WP_IRQENABLE_SET);
	32	DUMPREG(HDMI_WP_IRQENABLE_CLR);
	33	DUMPREG(HDMI_WP_IRQWAKEEN);
	34	DUMPREG(HDMI_WP_PWR_CTRL);
	35	DUMPREG(HDMI_WP_DEBOUNCE);
	36	DUMPREG(HDMI_WP_VIDEO_CFG);
	37	DUMPREG(HDMI_WP_VIDEO_SIZE);
	38	DUMPREG(HDMI_WP_VIDEO_TIMING_H);
	39	DUMPREG(HDMI_WP_VIDEO_TIMING_V);
42116517	40	DUMPREG(HDMI_WP_CLK);
f382d9eb AT	41	DUMPREG(HDMI_WP_AUDIO_CFG);
	42	DUMPREG(HDMI_WP_AUDIO_CFG2);
	43	DUMPREG(HDMI_WP_AUDIO_CTRL);
	44	DUMPREG(HDMI_WP_AUDIO_DATA);
	45	}
	46
	47	u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
	48	{
	49	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
	50	}
	51
	52	void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
	53	{
	54	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
	55	/* flush posted write */
	56	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
	57	}
	58
	59	void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
	60	{
	61	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
	62	}
	63
	64	void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
	65	{
	66	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
	67	}
	68
	69	/* PHY_PWR_CMD */
	70	int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
	71	{
	72	/* Return if already the state */
	73	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
	74	return 0;
	75
	76	/* Command for power control of HDMI PHY */
	77	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
	78
	79	/* Status of the power control of HDMI PHY */
	80	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
	81	!= val) {
ac9f2421	82	DSSERR("Failed to set PHY power mode to %d\n", val);
f382d9eb AT	83	return -ETIMEDOUT;
	84	}
	85
	86	return 0;
	87	}
	88
	89	/* PLL_PWR_CMD */
	90	int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
	91	{
	92	/* Command for power control of HDMI PLL */
	93	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
	94
	95	/* wait till PHY_PWR_STATUS is set */
	96	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
	97	!= val) {
ac9f2421	98	DSSERR("Failed to set PLL_PWR_STATUS\n");
f382d9eb AT	99	return -ETIMEDOUT;
	100	}
	101
	102	return 0;
	103	}
	104
	105	int hdmi_wp_video_start(struct hdmi_wp_data *wp)
	106	{
	107	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
	108
	109	return 0;
	110	}
	111
	112	void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
	113	{
a9fad688 TV	114	int i;
	115
	116	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
	117
f382d9eb	118	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
a9fad688 TV	119
	120	for (i = 0; i < 50; ++i) {
	121	u32 v;
	122
	123	msleep(20);
	124
	125	v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
	126	if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
	127	return;
	128	}
	129
	130	DSSERR("no HDMI FRAMEDONE when disabling output\n");
f382d9eb AT	131	}
	132
	133	void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
	134	struct hdmi_video_format *video_fmt)
	135	{
	136	u32 l = 0;
	137
	138	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
	139	10, 8);
	140
	141	l \|= FLD_VAL(video_fmt->y_res, 31, 16);
	142	l \|= FLD_VAL(video_fmt->x_res, 15, 0);
	143	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
	144	}
	145
	146	void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
	147	struct omap_video_timings *timings)
	148	{
	149	u32 r;
	150	bool vsync_pol, hsync_pol;
ac9f2421	151	DSSDBG("Enter hdmi_wp_video_config_interface\n");
f382d9eb AT	152
	153	vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
	154	hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
	155
	156	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
	157	r = FLD_MOD(r, vsync_pol, 7, 7);
	158	r = FLD_MOD(r, hsync_pol, 6, 6);
	159	r = FLD_MOD(r, timings->interlace, 3, 3);
	160	r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
	161	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
	162	}
	163
	164	void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
	165	struct omap_video_timings *timings)
	166	{
	167	u32 timing_h = 0;
	168	u32 timing_v = 0;
c92e8727	169	unsigned hsw_offset = 1;
f382d9eb	170
ac9f2421	171	DSSDBG("Enter hdmi_wp_video_config_timing\n");
f382d9eb	172
c92e8727 TV	173	/*
	174	* On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5
	175	* ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1.
	176	* However, we don't support OMAP5 ES1 at all, so we can just check for
	177	* OMAP4 here.
	178	*/
	179	if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 \|\|
	180	omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 \|\|
	181	omapdss_get_version() == OMAPDSS_VER_OMAP4)
	182	hsw_offset = 0;
	183
f382d9eb AT	184	timing_h \|= FLD_VAL(timings->hbp, 31, 20);
f382d9eb AT	185	timing_h \|= FLD_VAL(timings->hfp, 19, 8);
c92e8727	186	timing_h \|= FLD_VAL(timings->hsw - hsw_offset, 7, 0);
f382d9eb AT	187	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
	188
	189	timing_v \|= FLD_VAL(timings->vbp, 31, 20);
	190	timing_v \|= FLD_VAL(timings->vfp, 19, 8);
	191	timing_v \|= FLD_VAL(timings->vsw, 7, 0);
	192	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
	193	}
	194
	195	void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
	196	struct omap_video_timings timings, struct hdmi_config param)
	197	{
ac9f2421	198	DSSDBG("Enter hdmi_wp_video_init_format\n");
f382d9eb AT	199
	200	video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
	201	video_fmt->y_res = param->timings.y_res;
	202	video_fmt->x_res = param->timings.x_res;
	203
	204	timings->hbp = param->timings.hbp;
	205	timings->hfp = param->timings.hfp;
	206	timings->hsw = param->timings.hsw;
	207	timings->vbp = param->timings.vbp;
	208	timings->vfp = param->timings.vfp;
	209	timings->vsw = param->timings.vsw;
b2af8092	210
f382d9eb AT	211	timings->vsync_level = param->timings.vsync_level;
	212	timings->hsync_level = param->timings.hsync_level;
	213	timings->interlace = param->timings.interlace;
b2af8092 TV	214	timings->double_pixel = param->timings.double_pixel;
	215
	216	if (param->timings.interlace) {
	217	video_fmt->y_res /= 2;
	218	timings->vbp /= 2;
	219	timings->vfp /= 2;
	220	timings->vsw /= 2;
	221	}
	222
	223	if (param->timings.double_pixel) {
	224	video_fmt->x_res *= 2;
	225	timings->hfp *= 2;
	226	timings->hsw *= 2;
	227	timings->hbp *= 2;
	228	}
f382d9eb AT	229	}
f382d9eb AT	230
f382d9eb AT	231	void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
	232	struct hdmi_audio_format *aud_fmt)
	233	{
	234	u32 r;
	235
	236	DSSDBG("Enter hdmi_wp_audio_config_format\n");
	237
	238	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
086f8281 JS	239	if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 \|\|
	240	omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 \|\|
	241	omapdss_get_version() == OMAPDSS_VER_OMAP4) {
	242	r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
	243	r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
	244	}
f382d9eb AT	245	r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
	246	r = FLD_MOD(r, aud_fmt->type, 4, 4);
	247	r = FLD_MOD(r, aud_fmt->justification, 3, 3);
	248	r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
	249	r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
	250	r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
	251	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
	252	}
	253
	254	void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
	255	struct hdmi_audio_dma *aud_dma)
	256	{
	257	u32 r;
	258
	259	DSSDBG("Enter hdmi_wp_audio_config_dma\n");
	260
	261	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
	262	r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
	263	r = FLD_MOD(r, aud_dma->block_size, 7, 0);
	264	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
	265
	266	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
	267	r = FLD_MOD(r, aud_dma->mode, 9, 9);
	268	r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
	269	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
	270	}
	271
	272	int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
	273	{
	274	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
	275
	276	return 0;
	277	}
	278
	279	int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
	280	{
	281	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
	282
	283	return 0;
	284	}
f382d9eb	285
f382d9eb AT	286	int hdmi_wp_init(struct platform_device pdev, struct hdmi_wp_data wp)
	287	{
	288	struct resource *res;
f382d9eb	289
77601507	290	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
f382d9eb	291	if (!res) {
fc2daf3b TV	292	DSSERR("can't get WP mem resource\n");
fc2daf3b TV	293	return -EINVAL;
f382d9eb	294	}
58652163	295	wp->phys_base = res->start;
f382d9eb	296
fc2daf3b	297	wp->base = devm_ioremap_resource(&pdev->dev, res);
2b22df83	298	if (IS_ERR(wp->base)) {
f382d9eb	299	DSSERR("can't ioremap HDMI WP\n");
2b22df83	300	return PTR_ERR(wp->base);
f382d9eb AT	301	}
	302
	303	return 0;
	304	}
58652163 JS	305
	306	phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
	307	{
	308	return wp->phys_base + HDMI_WP_AUDIO_DATA;
	309	}