drm: omapdrm: Remove duplicate error messages when mapping memory
[linux-2.6-block.git] / drivers / gpu / drm / omapdrm / dss / hdmi5.c
CommitLineData
f5bab222
TV
1/*
2 * HDMI driver for OMAP5
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25#define DSS_SUBSYS_NAME "HDMI"
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/interrupt.h>
32#include <linux/mutex.h>
33#include <linux/delay.h>
34#include <linux/string.h>
35#include <linux/platform_device.h>
36#include <linux/pm_runtime.h>
37#include <linux/clk.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
736e60dd 40#include <linux/component.h>
d9e32ecd 41#include <linux/of.h>
09bffa6e 42#include <linux/of_graph.h>
45302d7e 43#include <sound/omap-hdmi-audio.h>
f5bab222 44
32043da7 45#include "omapdss.h"
f5bab222
TV
46#include "hdmi5_core.h"
47#include "dss.h"
48#include "dss_features.h"
49
945514b5 50static struct omap_hdmi hdmi;
f5bab222
TV
51
52static int hdmi_runtime_get(void)
53{
54 int r;
55
56 DSSDBG("hdmi_runtime_get\n");
57
58 r = pm_runtime_get_sync(&hdmi.pdev->dev);
59 WARN_ON(r < 0);
60 if (r < 0)
61 return r;
62
63 return 0;
64}
65
66static void hdmi_runtime_put(void)
67{
68 int r;
69
70 DSSDBG("hdmi_runtime_put\n");
71
72 r = pm_runtime_put_sync(&hdmi.pdev->dev);
73 WARN_ON(r < 0 && r != -ENOSYS);
74}
75
76static irqreturn_t hdmi_irq_handler(int irq, void *data)
77{
78 struct hdmi_wp_data *wp = data;
79 u32 irqstatus;
80
81 irqstatus = hdmi_wp_get_irqstatus(wp);
82 hdmi_wp_set_irqstatus(wp, irqstatus);
83
84 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
85 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
86 u32 v;
87 /*
88 * If we get both connect and disconnect interrupts at the same
89 * time, turn off the PHY, clear interrupts, and restart, which
90 * raises connect interrupt if a cable is connected, or nothing
91 * if cable is not connected.
92 */
93
94 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
95
96 /*
97 * We always get bogus CONNECT & DISCONNECT interrupts when
98 * setting the PHY to LDOON. To ignore those, we force the RXDET
99 * line to 0 until the PHY power state has been changed.
100 */
101 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
102 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
103 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
104 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
105
106 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
107 HDMI_IRQ_LINK_DISCONNECT);
108
109 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
110
111 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
112
113 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
114 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
115 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
116 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
117 }
118
119 return IRQ_HANDLED;
120}
121
122static int hdmi_init_regulator(void)
123{
f5bab222
TV
124 struct regulator *reg;
125
126 if (hdmi.vdda_reg != NULL)
127 return 0;
128
129 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
130 if (IS_ERR(reg)) {
131 DSSERR("can't get VDDA regulator\n");
132 return PTR_ERR(reg);
133 }
134
f5bab222
TV
135 hdmi.vdda_reg = reg;
136
137 return 0;
138}
139
140static int hdmi_power_on_core(struct omap_dss_device *dssdev)
141{
142 int r;
143
144 r = regulator_enable(hdmi.vdda_reg);
145 if (r)
146 return r;
147
148 r = hdmi_runtime_get();
149 if (r)
150 goto err_runtime_get;
151
152 /* Make selection of HDMI in DSS */
153 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
154
155 hdmi.core_enabled = true;
156
157 return 0;
158
159err_runtime_get:
160 regulator_disable(hdmi.vdda_reg);
161
162 return r;
163}
164
165static void hdmi_power_off_core(struct omap_dss_device *dssdev)
166{
167 hdmi.core_enabled = false;
168
169 hdmi_runtime_put();
170 regulator_disable(hdmi.vdda_reg);
171}
172
173static int hdmi_power_on_full(struct omap_dss_device *dssdev)
174{
175 int r;
da11bbbb 176 struct videomode *vm;
86e95f92 177 enum omap_channel channel = dssdev->dispc_channel;
c84c3a5b 178 struct dss_pll_clock_info hdmi_cinfo = { 0 };
67d8ffdd 179 unsigned pc;
f5bab222
TV
180
181 r = hdmi_power_on_core(dssdev);
182 if (r)
183 return r;
184
da11bbbb 185 vm = &hdmi.cfg.vm;
f5bab222 186
da11bbbb
PU
187 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
188 vm->vactive);
f5bab222 189
da11bbbb
PU
190 pc = vm->pixelclock;
191 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
67d8ffdd
TV
192 pc *= 2;
193
c107751d
TV
194 /* DSS_HDMI_TCLK is bitclk / 10 */
195 pc *= 10;
196
c17dc0e3
TV
197 dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin),
198 pc, &hdmi_cinfo);
f5bab222
TV
199
200 /* disable and clear irqs */
201 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
202 hdmi_wp_set_irqstatus(&hdmi.wp,
203 hdmi_wp_get_irqstatus(&hdmi.wp));
204
c84c3a5b 205 r = dss_pll_enable(&hdmi.pll.pll);
f5bab222 206 if (r) {
c2fbd061 207 DSSERR("Failed to enable PLL\n");
f5bab222
TV
208 goto err_pll_enable;
209 }
210
c84c3a5b 211 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
c2fbd061
TV
212 if (r) {
213 DSSERR("Failed to configure PLL\n");
214 goto err_pll_cfg;
215 }
216
c84c3a5b
TV
217 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
218 hdmi_cinfo.clkout[0]);
f5bab222
TV
219 if (r) {
220 DSSDBG("Failed to start PHY\n");
221 goto err_phy_cfg;
222 }
223
224 r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
225 if (r)
226 goto err_phy_pwr;
227
228 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
229
f5bab222 230 /* tv size */
da11bbbb 231 dss_mgr_set_timings(channel, vm);
f5bab222 232
86e95f92 233 r = dss_mgr_enable(channel);
f5bab222
TV
234 if (r)
235 goto err_mgr_enable;
236
4e4b53ce
TV
237 r = hdmi_wp_video_start(&hdmi.wp);
238 if (r)
239 goto err_vid_enable;
240
f5bab222
TV
241 hdmi_wp_set_irqenable(&hdmi.wp,
242 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
243
244 return 0;
245
f5bab222 246err_vid_enable:
86e95f92 247 dss_mgr_disable(channel);
4e4b53ce 248err_mgr_enable:
f5bab222
TV
249 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
250err_phy_pwr:
251err_phy_cfg:
c2fbd061 252err_pll_cfg:
c84c3a5b 253 dss_pll_disable(&hdmi.pll.pll);
f5bab222
TV
254err_pll_enable:
255 hdmi_power_off_core(dssdev);
256 return -EIO;
257}
258
259static void hdmi_power_off_full(struct omap_dss_device *dssdev)
260{
86e95f92 261 enum omap_channel channel = dssdev->dispc_channel;
f5bab222
TV
262
263 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
264
f5bab222
TV
265 hdmi_wp_video_stop(&hdmi.wp);
266
86e95f92 267 dss_mgr_disable(channel);
4e4b53ce 268
f5bab222
TV
269 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
270
c84c3a5b 271 dss_pll_disable(&hdmi.pll.pll);
f5bab222
TV
272
273 hdmi_power_off_core(dssdev);
274}
275
276static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
da11bbbb 277 struct videomode *vm)
f5bab222 278{
da11bbbb 279 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
f5bab222
TV
280 return -EINVAL;
281
282 return 0;
283}
284
285static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
da11bbbb 286 struct videomode *vm)
f5bab222 287{
f5bab222
TV
288 mutex_lock(&hdmi.lock);
289
da11bbbb 290 hdmi.cfg.vm = *vm;
f5bab222 291
da11bbbb 292 dispc_set_tv_pclk(vm->pixelclock);
f5bab222
TV
293
294 mutex_unlock(&hdmi.lock);
295}
296
297static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
da11bbbb 298 struct videomode *vm)
f5bab222 299{
da11bbbb 300 *vm = hdmi.cfg.vm;
f5bab222
TV
301}
302
303static void hdmi_dump_regs(struct seq_file *s)
304{
305 mutex_lock(&hdmi.lock);
306
307 if (hdmi_runtime_get()) {
308 mutex_unlock(&hdmi.lock);
309 return;
310 }
311
312 hdmi_wp_dump(&hdmi.wp, s);
313 hdmi_pll_dump(&hdmi.pll, s);
314 hdmi_phy_dump(&hdmi.phy, s);
315 hdmi5_core_dump(&hdmi.core, s);
316
317 hdmi_runtime_put();
318 mutex_unlock(&hdmi.lock);
319}
320
321static int read_edid(u8 *buf, int len)
322{
323 int r;
324 int idlemode;
325
326 mutex_lock(&hdmi.lock);
327
328 r = hdmi_runtime_get();
329 BUG_ON(r);
330
331 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
332 /* No-idle mode */
333 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
334
335 r = hdmi5_read_edid(&hdmi.core, buf, len);
336
337 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
338
339 hdmi_runtime_put();
340 mutex_unlock(&hdmi.lock);
341
342 return r;
343}
344
8a9d4626
JS
345static void hdmi_start_audio_stream(struct omap_hdmi *hd)
346{
347 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
348 hdmi_wp_audio_enable(&hd->wp, true);
349 hdmi_wp_audio_core_req_enable(&hd->wp, true);
350}
351
352static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
353{
354 hdmi_wp_audio_core_req_enable(&hd->wp, false);
355 hdmi_wp_audio_enable(&hd->wp, false);
356 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
357}
358
f5bab222
TV
359static int hdmi_display_enable(struct omap_dss_device *dssdev)
360{
361 struct omap_dss_device *out = &hdmi.output;
8a9d4626 362 unsigned long flags;
f5bab222
TV
363 int r = 0;
364
365 DSSDBG("ENTER hdmi_display_enable\n");
366
367 mutex_lock(&hdmi.lock);
368
f1504ad0 369 if (!out->dispc_channel_connected) {
f5bab222
TV
370 DSSERR("failed to enable display: no output/manager\n");
371 r = -ENODEV;
372 goto err0;
373 }
374
375 r = hdmi_power_on_full(dssdev);
376 if (r) {
377 DSSERR("failed to power on device\n");
378 goto err0;
379 }
380
8a9d4626
JS
381 if (hdmi.audio_configured) {
382 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
da11bbbb 383 hdmi.cfg.vm.pixelclock);
8a9d4626
JS
384 if (r) {
385 DSSERR("Error restoring audio configuration: %d", r);
386 hdmi.audio_abort_cb(&hdmi.pdev->dev);
387 hdmi.audio_configured = false;
388 }
389 }
390
391 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
392 if (hdmi.audio_configured && hdmi.audio_playing)
393 hdmi_start_audio_stream(&hdmi);
45302d7e 394 hdmi.display_enabled = true;
8a9d4626 395 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
45302d7e 396
f5bab222
TV
397 mutex_unlock(&hdmi.lock);
398 return 0;
399
400err0:
401 mutex_unlock(&hdmi.lock);
402 return r;
403}
404
405static void hdmi_display_disable(struct omap_dss_device *dssdev)
406{
8a9d4626
JS
407 unsigned long flags;
408
f5bab222
TV
409 DSSDBG("Enter hdmi_display_disable\n");
410
411 mutex_lock(&hdmi.lock);
412
8a9d4626
JS
413 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
414 hdmi_stop_audio_stream(&hdmi);
415 hdmi.display_enabled = false;
416 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
45302d7e 417
f5bab222
TV
418 hdmi_power_off_full(dssdev);
419
420 mutex_unlock(&hdmi.lock);
421}
422
423static int hdmi_core_enable(struct omap_dss_device *dssdev)
424{
425 int r = 0;
426
427 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
428
429 mutex_lock(&hdmi.lock);
430
431 r = hdmi_power_on_core(dssdev);
432 if (r) {
433 DSSERR("failed to power on device\n");
434 goto err0;
435 }
436
437 mutex_unlock(&hdmi.lock);
438 return 0;
439
440err0:
441 mutex_unlock(&hdmi.lock);
442 return r;
443}
444
445static void hdmi_core_disable(struct omap_dss_device *dssdev)
446{
447 DSSDBG("Enter omapdss_hdmi_core_disable\n");
448
449 mutex_lock(&hdmi.lock);
450
451 hdmi_power_off_core(dssdev);
452
453 mutex_unlock(&hdmi.lock);
454}
455
f5bab222
TV
456static int hdmi_connect(struct omap_dss_device *dssdev,
457 struct omap_dss_device *dst)
458{
86e95f92 459 enum omap_channel channel = dssdev->dispc_channel;
f5bab222
TV
460 int r;
461
462 r = hdmi_init_regulator();
463 if (r)
464 return r;
465
86e95f92 466 r = dss_mgr_connect(channel, dssdev);
f5bab222
TV
467 if (r)
468 return r;
469
470 r = omapdss_output_set_device(dssdev, dst);
471 if (r) {
472 DSSERR("failed to connect output to new device: %s\n",
473 dst->name);
86e95f92 474 dss_mgr_disconnect(channel, dssdev);
f5bab222
TV
475 return r;
476 }
477
478 return 0;
479}
480
481static void hdmi_disconnect(struct omap_dss_device *dssdev,
482 struct omap_dss_device *dst)
483{
86e95f92
TV
484 enum omap_channel channel = dssdev->dispc_channel;
485
f5bab222
TV
486 WARN_ON(dst != dssdev->dst);
487
488 if (dst != dssdev->dst)
489 return;
490
491 omapdss_output_unset_device(dssdev);
492
86e95f92 493 dss_mgr_disconnect(channel, dssdev);
f5bab222
TV
494}
495
496static int hdmi_read_edid(struct omap_dss_device *dssdev,
497 u8 *edid, int len)
498{
499 bool need_enable;
500 int r;
501
502 need_enable = hdmi.core_enabled == false;
503
504 if (need_enable) {
505 r = hdmi_core_enable(dssdev);
506 if (r)
507 return r;
508 }
509
510 r = read_edid(edid, len);
511
512 if (need_enable)
513 hdmi_core_disable(dssdev);
514
515 return r;
516}
517
769dcb11
TV
518static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
519 const struct hdmi_avi_infoframe *avi)
520{
521 hdmi.cfg.infoframe = *avi;
522 return 0;
523}
524
525static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
526 bool hdmi_mode)
527{
528 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
529 return 0;
530}
531
f5bab222
TV
532static const struct omapdss_hdmi_ops hdmi_ops = {
533 .connect = hdmi_connect,
534 .disconnect = hdmi_disconnect,
535
536 .enable = hdmi_display_enable,
537 .disable = hdmi_display_disable,
538
539 .check_timings = hdmi_display_check_timing,
540 .set_timings = hdmi_display_set_timing,
541 .get_timings = hdmi_display_get_timings,
542
543 .read_edid = hdmi_read_edid,
769dcb11
TV
544 .set_infoframe = hdmi_set_infoframe,
545 .set_hdmi_mode = hdmi_set_hdmi_mode,
f5bab222
TV
546};
547
548static void hdmi_init_output(struct platform_device *pdev)
549{
550 struct omap_dss_device *out = &hdmi.output;
551
552 out->dev = &pdev->dev;
553 out->id = OMAP_DSS_OUTPUT_HDMI;
554 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
555 out->name = "hdmi.0";
556 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
557 out->ops.hdmi = &hdmi_ops;
558 out->owner = THIS_MODULE;
559
560 omapdss_register_output(out);
561}
562
39c1b7bf 563static void hdmi_uninit_output(struct platform_device *pdev)
f5bab222
TV
564{
565 struct omap_dss_device *out = &hdmi.output;
566
567 omapdss_unregister_output(out);
568}
569
570static int hdmi_probe_of(struct platform_device *pdev)
571{
572 struct device_node *node = pdev->dev.of_node;
573 struct device_node *ep;
574 int r;
575
09bffa6e 576 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
f5bab222
TV
577 if (!ep)
578 return 0;
579
580 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
581 if (r)
582 goto err;
583
584 of_node_put(ep);
585 return 0;
586
587err:
588 of_node_put(ep);
589 return r;
590}
591
45302d7e
JS
592/* Audio callbacks */
593static int hdmi_audio_startup(struct device *dev,
594 void (*abort_cb)(struct device *dev))
595{
596 struct omap_hdmi *hd = dev_get_drvdata(dev);
597 int ret = 0;
598
599 mutex_lock(&hd->lock);
600
601 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
602 ret = -EPERM;
603 goto out;
604 }
605
606 hd->audio_abort_cb = abort_cb;
607
608out:
609 mutex_unlock(&hd->lock);
610
611 return ret;
612}
613
614static int hdmi_audio_shutdown(struct device *dev)
615{
616 struct omap_hdmi *hd = dev_get_drvdata(dev);
617
618 mutex_lock(&hd->lock);
619 hd->audio_abort_cb = NULL;
8a9d4626
JS
620 hd->audio_configured = false;
621 hd->audio_playing = false;
45302d7e
JS
622 mutex_unlock(&hd->lock);
623
624 return 0;
625}
626
627static int hdmi_audio_start(struct device *dev)
628{
629 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 630 unsigned long flags;
45302d7e
JS
631
632 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
45302d7e 633
8a9d4626 634 spin_lock_irqsave(&hd->audio_playing_lock, flags);
2d7639bc 635
8a9d4626
JS
636 if (hd->display_enabled)
637 hdmi_start_audio_stream(hd);
638 hd->audio_playing = true;
45302d7e 639
8a9d4626 640 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
641 return 0;
642}
643
644static void hdmi_audio_stop(struct device *dev)
645{
646 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 647 unsigned long flags;
45302d7e
JS
648
649 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
45302d7e 650
8a9d4626
JS
651 spin_lock_irqsave(&hd->audio_playing_lock, flags);
652
653 if (hd->display_enabled)
654 hdmi_stop_audio_stream(hd);
655 hd->audio_playing = false;
2d7639bc 656
8a9d4626 657 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
658}
659
660static int hdmi_audio_config(struct device *dev,
661 struct omap_dss_audio *dss_audio)
662{
663 struct omap_hdmi *hd = dev_get_drvdata(dev);
664 int ret;
665
666 mutex_lock(&hd->lock);
667
668 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
669 ret = -EPERM;
670 goto out;
671 }
672
673 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
da11bbbb 674 hd->cfg.vm.pixelclock);
45302d7e 675
8a9d4626
JS
676 if (!ret) {
677 hd->audio_configured = true;
678 hd->audio_config = *dss_audio;
679 }
45302d7e
JS
680out:
681 mutex_unlock(&hd->lock);
682
683 return ret;
684}
685
686static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
687 .audio_startup = hdmi_audio_startup,
688 .audio_shutdown = hdmi_audio_shutdown,
689 .audio_start = hdmi_audio_start,
690 .audio_stop = hdmi_audio_stop,
691 .audio_config = hdmi_audio_config,
692};
693
694static int hdmi_audio_register(struct device *dev)
695{
696 struct omap_hdmi_audio_pdata pdata = {
697 .dev = dev,
698 .dss_version = omapdss_get_version(),
699 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
700 .ops = &hdmi_audio_ops,
701 };
702
703 hdmi.audio_pdev = platform_device_register_data(
704 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
705 &pdata, sizeof(pdata));
706
707 if (IS_ERR(hdmi.audio_pdev))
708 return PTR_ERR(hdmi.audio_pdev);
709
8a9d4626
JS
710 hdmi_runtime_get();
711 hdmi.wp_idlemode =
712 REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
713 hdmi_runtime_put();
714
45302d7e
JS
715 return 0;
716}
717
f5bab222 718/* HDMI HW IP initialisation */
736e60dd 719static int hdmi5_bind(struct device *dev, struct device *master, void *data)
f5bab222 720{
736e60dd 721 struct platform_device *pdev = to_platform_device(dev);
f5bab222
TV
722 int r;
723 int irq;
724
725 hdmi.pdev = pdev;
945514b5 726 dev_set_drvdata(&pdev->dev, &hdmi);
f5bab222
TV
727
728 mutex_init(&hdmi.lock);
8a9d4626 729 spin_lock_init(&hdmi.audio_playing_lock);
f5bab222
TV
730
731 if (pdev->dev.of_node) {
732 r = hdmi_probe_of(pdev);
733 if (r)
734 return r;
735 }
736
737 r = hdmi_wp_init(pdev, &hdmi.wp);
738 if (r)
739 return r;
740
03aafa2c 741 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
f5bab222
TV
742 if (r)
743 return r;
744
745 r = hdmi_phy_init(pdev, &hdmi.phy);
746 if (r)
c84c3a5b 747 goto err;
f5bab222
TV
748
749 r = hdmi5_core_init(pdev, &hdmi.core);
750 if (r)
c84c3a5b 751 goto err;
f5bab222
TV
752
753 irq = platform_get_irq(pdev, 0);
754 if (irq < 0) {
755 DSSERR("platform_get_irq failed\n");
c84c3a5b
TV
756 r = -ENODEV;
757 goto err;
f5bab222
TV
758 }
759
760 r = devm_request_threaded_irq(&pdev->dev, irq,
761 NULL, hdmi_irq_handler,
762 IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
763 if (r) {
764 DSSERR("HDMI IRQ request failed\n");
c84c3a5b 765 goto err;
f5bab222
TV
766 }
767
768 pm_runtime_enable(&pdev->dev);
769
770 hdmi_init_output(pdev);
771
45302d7e
JS
772 r = hdmi_audio_register(&pdev->dev);
773 if (r) {
774 DSSERR("Registering HDMI audio failed %d\n", r);
775 hdmi_uninit_output(pdev);
776 pm_runtime_disable(&pdev->dev);
777 return r;
778 }
779
f5bab222
TV
780 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
781
782 return 0;
c84c3a5b
TV
783err:
784 hdmi_pll_uninit(&hdmi.pll);
785 return r;
f5bab222
TV
786}
787
736e60dd 788static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
f5bab222 789{
736e60dd
TV
790 struct platform_device *pdev = to_platform_device(dev);
791
45302d7e
JS
792 if (hdmi.audio_pdev)
793 platform_device_unregister(hdmi.audio_pdev);
794
f5bab222
TV
795 hdmi_uninit_output(pdev);
796
c84c3a5b
TV
797 hdmi_pll_uninit(&hdmi.pll);
798
f5bab222 799 pm_runtime_disable(&pdev->dev);
736e60dd
TV
800}
801
802static const struct component_ops hdmi5_component_ops = {
803 .bind = hdmi5_bind,
804 .unbind = hdmi5_unbind,
805};
f5bab222 806
736e60dd
TV
807static int hdmi5_probe(struct platform_device *pdev)
808{
809 return component_add(&pdev->dev, &hdmi5_component_ops);
810}
811
812static int hdmi5_remove(struct platform_device *pdev)
813{
814 component_del(&pdev->dev, &hdmi5_component_ops);
f5bab222
TV
815 return 0;
816}
817
818static int hdmi_runtime_suspend(struct device *dev)
819{
f5bab222
TV
820 dispc_runtime_put();
821
822 return 0;
823}
824
825static int hdmi_runtime_resume(struct device *dev)
826{
827 int r;
828
829 r = dispc_runtime_get();
830 if (r < 0)
831 return r;
832
f5bab222
TV
833 return 0;
834}
835
836static const struct dev_pm_ops hdmi_pm_ops = {
837 .runtime_suspend = hdmi_runtime_suspend,
838 .runtime_resume = hdmi_runtime_resume,
839};
840
841static const struct of_device_id hdmi_of_match[] = {
842 { .compatible = "ti,omap5-hdmi", },
adb5ff83 843 { .compatible = "ti,dra7-hdmi", },
f5bab222
TV
844 {},
845};
846
847static struct platform_driver omapdss_hdmihw_driver = {
736e60dd
TV
848 .probe = hdmi5_probe,
849 .remove = hdmi5_remove,
f5bab222
TV
850 .driver = {
851 .name = "omapdss_hdmi5",
f5bab222
TV
852 .pm = &hdmi_pm_ops,
853 .of_match_table = hdmi_of_match,
422ccbd5 854 .suppress_bind_attrs = true,
f5bab222
TV
855 },
856};
857
858int __init hdmi5_init_platform_driver(void)
859{
860 return platform_driver_register(&omapdss_hdmihw_driver);
861}
862
ede92695 863void hdmi5_uninit_platform_driver(void)
f5bab222
TV
864{
865 platform_driver_unregister(&omapdss_hdmihw_driver);
866}