Merge tag 'dmaengine-fix-4.7-rc4' of git://git.infradead.org/users/vkoul/slave-dma
[linux-block.git] / drivers / gpu / drm / omapdrm / dss / hdmi5.c
CommitLineData
f5bab222
TV
1/*
2 * HDMI driver for OMAP5
3 *
4 * Copyright (C) 2014 Texas Instruments Incorporated
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25#define DSS_SUBSYS_NAME "HDMI"
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/interrupt.h>
32#include <linux/mutex.h>
33#include <linux/delay.h>
34#include <linux/string.h>
35#include <linux/platform_device.h>
36#include <linux/pm_runtime.h>
37#include <linux/clk.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
736e60dd 40#include <linux/component.h>
d9e32ecd 41#include <linux/of.h>
f5bab222 42#include <video/omapdss.h>
45302d7e 43#include <sound/omap-hdmi-audio.h>
f5bab222
TV
44
45#include "hdmi5_core.h"
46#include "dss.h"
47#include "dss_features.h"
48
945514b5 49static struct omap_hdmi hdmi;
f5bab222
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50
51static int hdmi_runtime_get(void)
52{
53 int r;
54
55 DSSDBG("hdmi_runtime_get\n");
56
57 r = pm_runtime_get_sync(&hdmi.pdev->dev);
58 WARN_ON(r < 0);
59 if (r < 0)
60 return r;
61
62 return 0;
63}
64
65static void hdmi_runtime_put(void)
66{
67 int r;
68
69 DSSDBG("hdmi_runtime_put\n");
70
71 r = pm_runtime_put_sync(&hdmi.pdev->dev);
72 WARN_ON(r < 0 && r != -ENOSYS);
73}
74
75static irqreturn_t hdmi_irq_handler(int irq, void *data)
76{
77 struct hdmi_wp_data *wp = data;
78 u32 irqstatus;
79
80 irqstatus = hdmi_wp_get_irqstatus(wp);
81 hdmi_wp_set_irqstatus(wp, irqstatus);
82
83 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
84 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
85 u32 v;
86 /*
87 * If we get both connect and disconnect interrupts at the same
88 * time, turn off the PHY, clear interrupts, and restart, which
89 * raises connect interrupt if a cable is connected, or nothing
90 * if cable is not connected.
91 */
92
93 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
94
95 /*
96 * We always get bogus CONNECT & DISCONNECT interrupts when
97 * setting the PHY to LDOON. To ignore those, we force the RXDET
98 * line to 0 until the PHY power state has been changed.
99 */
100 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
101 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
102 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
103 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
104
105 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
106 HDMI_IRQ_LINK_DISCONNECT);
107
108 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
109
110 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
111
112 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
113 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
114 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
115 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
116 }
117
118 return IRQ_HANDLED;
119}
120
121static int hdmi_init_regulator(void)
122{
f5bab222
TV
123 struct regulator *reg;
124
125 if (hdmi.vdda_reg != NULL)
126 return 0;
127
128 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
129 if (IS_ERR(reg)) {
130 DSSERR("can't get VDDA regulator\n");
131 return PTR_ERR(reg);
132 }
133
f5bab222
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134 hdmi.vdda_reg = reg;
135
136 return 0;
137}
138
139static int hdmi_power_on_core(struct omap_dss_device *dssdev)
140{
141 int r;
142
143 r = regulator_enable(hdmi.vdda_reg);
144 if (r)
145 return r;
146
147 r = hdmi_runtime_get();
148 if (r)
149 goto err_runtime_get;
150
151 /* Make selection of HDMI in DSS */
152 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
153
154 hdmi.core_enabled = true;
155
156 return 0;
157
158err_runtime_get:
159 regulator_disable(hdmi.vdda_reg);
160
161 return r;
162}
163
164static void hdmi_power_off_core(struct omap_dss_device *dssdev)
165{
166 hdmi.core_enabled = false;
167
168 hdmi_runtime_put();
169 regulator_disable(hdmi.vdda_reg);
170}
171
172static int hdmi_power_on_full(struct omap_dss_device *dssdev)
173{
174 int r;
175 struct omap_video_timings *p;
86e95f92 176 enum omap_channel channel = dssdev->dispc_channel;
c84c3a5b 177 struct dss_pll_clock_info hdmi_cinfo = { 0 };
67d8ffdd 178 unsigned pc;
f5bab222
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179
180 r = hdmi_power_on_core(dssdev);
181 if (r)
182 return r;
183
184 p = &hdmi.cfg.timings;
185
186 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
187
67d8ffdd
TV
188 pc = p->pixelclock;
189 if (p->double_pixel)
190 pc *= 2;
191
192 hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);
f5bab222
TV
193
194 /* disable and clear irqs */
195 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
196 hdmi_wp_set_irqstatus(&hdmi.wp,
197 hdmi_wp_get_irqstatus(&hdmi.wp));
198
c84c3a5b 199 r = dss_pll_enable(&hdmi.pll.pll);
f5bab222 200 if (r) {
c2fbd061 201 DSSERR("Failed to enable PLL\n");
f5bab222
TV
202 goto err_pll_enable;
203 }
204
c84c3a5b 205 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
c2fbd061
TV
206 if (r) {
207 DSSERR("Failed to configure PLL\n");
208 goto err_pll_cfg;
209 }
210
c84c3a5b
TV
211 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
212 hdmi_cinfo.clkout[0]);
f5bab222
TV
213 if (r) {
214 DSSDBG("Failed to start PHY\n");
215 goto err_phy_cfg;
216 }
217
218 r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
219 if (r)
220 goto err_phy_pwr;
221
222 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
223
224 /* bypass TV gamma table */
225 dispc_enable_gamma_table(0);
226
227 /* tv size */
86e95f92 228 dss_mgr_set_timings(channel, p);
f5bab222 229
86e95f92 230 r = dss_mgr_enable(channel);
f5bab222
TV
231 if (r)
232 goto err_mgr_enable;
233
4e4b53ce
TV
234 r = hdmi_wp_video_start(&hdmi.wp);
235 if (r)
236 goto err_vid_enable;
237
f5bab222
TV
238 hdmi_wp_set_irqenable(&hdmi.wp,
239 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
240
241 return 0;
242
f5bab222 243err_vid_enable:
86e95f92 244 dss_mgr_disable(channel);
4e4b53ce 245err_mgr_enable:
f5bab222
TV
246 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
247err_phy_pwr:
248err_phy_cfg:
c2fbd061 249err_pll_cfg:
c84c3a5b 250 dss_pll_disable(&hdmi.pll.pll);
f5bab222
TV
251err_pll_enable:
252 hdmi_power_off_core(dssdev);
253 return -EIO;
254}
255
256static void hdmi_power_off_full(struct omap_dss_device *dssdev)
257{
86e95f92 258 enum omap_channel channel = dssdev->dispc_channel;
f5bab222
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259
260 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
261
f5bab222
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262 hdmi_wp_video_stop(&hdmi.wp);
263
86e95f92 264 dss_mgr_disable(channel);
4e4b53ce 265
f5bab222
TV
266 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
267
c84c3a5b 268 dss_pll_disable(&hdmi.pll.pll);
f5bab222
TV
269
270 hdmi_power_off_core(dssdev);
271}
272
273static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
274 struct omap_video_timings *timings)
275{
86e95f92 276 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, timings))
f5bab222
TV
277 return -EINVAL;
278
279 return 0;
280}
281
282static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
283 struct omap_video_timings *timings)
284{
f5bab222
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285 mutex_lock(&hdmi.lock);
286
769dcb11 287 hdmi.cfg.timings = *timings;
f5bab222 288
769dcb11 289 dispc_set_tv_pclk(timings->pixelclock);
f5bab222
TV
290
291 mutex_unlock(&hdmi.lock);
292}
293
294static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
295 struct omap_video_timings *timings)
296{
769dcb11 297 *timings = hdmi.cfg.timings;
f5bab222
TV
298}
299
300static void hdmi_dump_regs(struct seq_file *s)
301{
302 mutex_lock(&hdmi.lock);
303
304 if (hdmi_runtime_get()) {
305 mutex_unlock(&hdmi.lock);
306 return;
307 }
308
309 hdmi_wp_dump(&hdmi.wp, s);
310 hdmi_pll_dump(&hdmi.pll, s);
311 hdmi_phy_dump(&hdmi.phy, s);
312 hdmi5_core_dump(&hdmi.core, s);
313
314 hdmi_runtime_put();
315 mutex_unlock(&hdmi.lock);
316}
317
318static int read_edid(u8 *buf, int len)
319{
320 int r;
321 int idlemode;
322
323 mutex_lock(&hdmi.lock);
324
325 r = hdmi_runtime_get();
326 BUG_ON(r);
327
328 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
329 /* No-idle mode */
330 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
331
332 r = hdmi5_read_edid(&hdmi.core, buf, len);
333
334 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
335
336 hdmi_runtime_put();
337 mutex_unlock(&hdmi.lock);
338
339 return r;
340}
341
8a9d4626
JS
342static void hdmi_start_audio_stream(struct omap_hdmi *hd)
343{
344 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
345 hdmi_wp_audio_enable(&hd->wp, true);
346 hdmi_wp_audio_core_req_enable(&hd->wp, true);
347}
348
349static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
350{
351 hdmi_wp_audio_core_req_enable(&hd->wp, false);
352 hdmi_wp_audio_enable(&hd->wp, false);
353 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
354}
355
f5bab222
TV
356static int hdmi_display_enable(struct omap_dss_device *dssdev)
357{
358 struct omap_dss_device *out = &hdmi.output;
8a9d4626 359 unsigned long flags;
f5bab222
TV
360 int r = 0;
361
362 DSSDBG("ENTER hdmi_display_enable\n");
363
364 mutex_lock(&hdmi.lock);
365
f1504ad0 366 if (!out->dispc_channel_connected) {
f5bab222
TV
367 DSSERR("failed to enable display: no output/manager\n");
368 r = -ENODEV;
369 goto err0;
370 }
371
372 r = hdmi_power_on_full(dssdev);
373 if (r) {
374 DSSERR("failed to power on device\n");
375 goto err0;
376 }
377
8a9d4626
JS
378 if (hdmi.audio_configured) {
379 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
380 hdmi.cfg.timings.pixelclock);
381 if (r) {
382 DSSERR("Error restoring audio configuration: %d", r);
383 hdmi.audio_abort_cb(&hdmi.pdev->dev);
384 hdmi.audio_configured = false;
385 }
386 }
387
388 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
389 if (hdmi.audio_configured && hdmi.audio_playing)
390 hdmi_start_audio_stream(&hdmi);
45302d7e 391 hdmi.display_enabled = true;
8a9d4626 392 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
45302d7e 393
f5bab222
TV
394 mutex_unlock(&hdmi.lock);
395 return 0;
396
397err0:
398 mutex_unlock(&hdmi.lock);
399 return r;
400}
401
402static void hdmi_display_disable(struct omap_dss_device *dssdev)
403{
8a9d4626
JS
404 unsigned long flags;
405
f5bab222
TV
406 DSSDBG("Enter hdmi_display_disable\n");
407
408 mutex_lock(&hdmi.lock);
409
8a9d4626
JS
410 spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
411 hdmi_stop_audio_stream(&hdmi);
412 hdmi.display_enabled = false;
413 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
45302d7e 414
f5bab222
TV
415 hdmi_power_off_full(dssdev);
416
417 mutex_unlock(&hdmi.lock);
418}
419
420static int hdmi_core_enable(struct omap_dss_device *dssdev)
421{
422 int r = 0;
423
424 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
425
426 mutex_lock(&hdmi.lock);
427
428 r = hdmi_power_on_core(dssdev);
429 if (r) {
430 DSSERR("failed to power on device\n");
431 goto err0;
432 }
433
434 mutex_unlock(&hdmi.lock);
435 return 0;
436
437err0:
438 mutex_unlock(&hdmi.lock);
439 return r;
440}
441
442static void hdmi_core_disable(struct omap_dss_device *dssdev)
443{
444 DSSDBG("Enter omapdss_hdmi_core_disable\n");
445
446 mutex_lock(&hdmi.lock);
447
448 hdmi_power_off_core(dssdev);
449
450 mutex_unlock(&hdmi.lock);
451}
452
f5bab222
TV
453static int hdmi_connect(struct omap_dss_device *dssdev,
454 struct omap_dss_device *dst)
455{
86e95f92 456 enum omap_channel channel = dssdev->dispc_channel;
f5bab222
TV
457 int r;
458
459 r = hdmi_init_regulator();
460 if (r)
461 return r;
462
86e95f92 463 r = dss_mgr_connect(channel, dssdev);
f5bab222
TV
464 if (r)
465 return r;
466
467 r = omapdss_output_set_device(dssdev, dst);
468 if (r) {
469 DSSERR("failed to connect output to new device: %s\n",
470 dst->name);
86e95f92 471 dss_mgr_disconnect(channel, dssdev);
f5bab222
TV
472 return r;
473 }
474
475 return 0;
476}
477
478static void hdmi_disconnect(struct omap_dss_device *dssdev,
479 struct omap_dss_device *dst)
480{
86e95f92
TV
481 enum omap_channel channel = dssdev->dispc_channel;
482
f5bab222
TV
483 WARN_ON(dst != dssdev->dst);
484
485 if (dst != dssdev->dst)
486 return;
487
488 omapdss_output_unset_device(dssdev);
489
86e95f92 490 dss_mgr_disconnect(channel, dssdev);
f5bab222
TV
491}
492
493static int hdmi_read_edid(struct omap_dss_device *dssdev,
494 u8 *edid, int len)
495{
496 bool need_enable;
497 int r;
498
499 need_enable = hdmi.core_enabled == false;
500
501 if (need_enable) {
502 r = hdmi_core_enable(dssdev);
503 if (r)
504 return r;
505 }
506
507 r = read_edid(edid, len);
508
509 if (need_enable)
510 hdmi_core_disable(dssdev);
511
512 return r;
513}
514
769dcb11
TV
515static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
516 const struct hdmi_avi_infoframe *avi)
517{
518 hdmi.cfg.infoframe = *avi;
519 return 0;
520}
521
522static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
523 bool hdmi_mode)
524{
525 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
526 return 0;
527}
528
f5bab222
TV
529static const struct omapdss_hdmi_ops hdmi_ops = {
530 .connect = hdmi_connect,
531 .disconnect = hdmi_disconnect,
532
533 .enable = hdmi_display_enable,
534 .disable = hdmi_display_disable,
535
536 .check_timings = hdmi_display_check_timing,
537 .set_timings = hdmi_display_set_timing,
538 .get_timings = hdmi_display_get_timings,
539
540 .read_edid = hdmi_read_edid,
769dcb11
TV
541 .set_infoframe = hdmi_set_infoframe,
542 .set_hdmi_mode = hdmi_set_hdmi_mode,
f5bab222
TV
543};
544
545static void hdmi_init_output(struct platform_device *pdev)
546{
547 struct omap_dss_device *out = &hdmi.output;
548
549 out->dev = &pdev->dev;
550 out->id = OMAP_DSS_OUTPUT_HDMI;
551 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
552 out->name = "hdmi.0";
553 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
554 out->ops.hdmi = &hdmi_ops;
555 out->owner = THIS_MODULE;
556
557 omapdss_register_output(out);
558}
559
39c1b7bf 560static void hdmi_uninit_output(struct platform_device *pdev)
f5bab222
TV
561{
562 struct omap_dss_device *out = &hdmi.output;
563
564 omapdss_unregister_output(out);
565}
566
567static int hdmi_probe_of(struct platform_device *pdev)
568{
569 struct device_node *node = pdev->dev.of_node;
570 struct device_node *ep;
571 int r;
572
573 ep = omapdss_of_get_first_endpoint(node);
574 if (!ep)
575 return 0;
576
577 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
578 if (r)
579 goto err;
580
581 of_node_put(ep);
582 return 0;
583
584err:
585 of_node_put(ep);
586 return r;
587}
588
45302d7e
JS
589/* Audio callbacks */
590static int hdmi_audio_startup(struct device *dev,
591 void (*abort_cb)(struct device *dev))
592{
593 struct omap_hdmi *hd = dev_get_drvdata(dev);
594 int ret = 0;
595
596 mutex_lock(&hd->lock);
597
598 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
599 ret = -EPERM;
600 goto out;
601 }
602
603 hd->audio_abort_cb = abort_cb;
604
605out:
606 mutex_unlock(&hd->lock);
607
608 return ret;
609}
610
611static int hdmi_audio_shutdown(struct device *dev)
612{
613 struct omap_hdmi *hd = dev_get_drvdata(dev);
614
615 mutex_lock(&hd->lock);
616 hd->audio_abort_cb = NULL;
8a9d4626
JS
617 hd->audio_configured = false;
618 hd->audio_playing = false;
45302d7e
JS
619 mutex_unlock(&hd->lock);
620
621 return 0;
622}
623
624static int hdmi_audio_start(struct device *dev)
625{
626 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 627 unsigned long flags;
45302d7e
JS
628
629 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
45302d7e 630
8a9d4626 631 spin_lock_irqsave(&hd->audio_playing_lock, flags);
2d7639bc 632
8a9d4626
JS
633 if (hd->display_enabled)
634 hdmi_start_audio_stream(hd);
635 hd->audio_playing = true;
45302d7e 636
8a9d4626 637 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
638 return 0;
639}
640
641static void hdmi_audio_stop(struct device *dev)
642{
643 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 644 unsigned long flags;
45302d7e
JS
645
646 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
45302d7e 647
8a9d4626
JS
648 spin_lock_irqsave(&hd->audio_playing_lock, flags);
649
650 if (hd->display_enabled)
651 hdmi_stop_audio_stream(hd);
652 hd->audio_playing = false;
2d7639bc 653
8a9d4626 654 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
655}
656
657static int hdmi_audio_config(struct device *dev,
658 struct omap_dss_audio *dss_audio)
659{
660 struct omap_hdmi *hd = dev_get_drvdata(dev);
661 int ret;
662
663 mutex_lock(&hd->lock);
664
665 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
666 ret = -EPERM;
667 goto out;
668 }
669
670 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
671 hd->cfg.timings.pixelclock);
672
8a9d4626
JS
673 if (!ret) {
674 hd->audio_configured = true;
675 hd->audio_config = *dss_audio;
676 }
45302d7e
JS
677out:
678 mutex_unlock(&hd->lock);
679
680 return ret;
681}
682
683static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
684 .audio_startup = hdmi_audio_startup,
685 .audio_shutdown = hdmi_audio_shutdown,
686 .audio_start = hdmi_audio_start,
687 .audio_stop = hdmi_audio_stop,
688 .audio_config = hdmi_audio_config,
689};
690
691static int hdmi_audio_register(struct device *dev)
692{
693 struct omap_hdmi_audio_pdata pdata = {
694 .dev = dev,
695 .dss_version = omapdss_get_version(),
696 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
697 .ops = &hdmi_audio_ops,
698 };
699
700 hdmi.audio_pdev = platform_device_register_data(
701 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
702 &pdata, sizeof(pdata));
703
704 if (IS_ERR(hdmi.audio_pdev))
705 return PTR_ERR(hdmi.audio_pdev);
706
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707 hdmi_runtime_get();
708 hdmi.wp_idlemode =
709 REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
710 hdmi_runtime_put();
711
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712 return 0;
713}
714
f5bab222 715/* HDMI HW IP initialisation */
736e60dd 716static int hdmi5_bind(struct device *dev, struct device *master, void *data)
f5bab222 717{
736e60dd 718 struct platform_device *pdev = to_platform_device(dev);
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719 int r;
720 int irq;
721
722 hdmi.pdev = pdev;
945514b5 723 dev_set_drvdata(&pdev->dev, &hdmi);
f5bab222
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724
725 mutex_init(&hdmi.lock);
8a9d4626 726 spin_lock_init(&hdmi.audio_playing_lock);
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727
728 if (pdev->dev.of_node) {
729 r = hdmi_probe_of(pdev);
730 if (r)
731 return r;
732 }
733
734 r = hdmi_wp_init(pdev, &hdmi.wp);
735 if (r)
736 return r;
737
03aafa2c 738 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
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739 if (r)
740 return r;
741
742 r = hdmi_phy_init(pdev, &hdmi.phy);
743 if (r)
c84c3a5b 744 goto err;
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745
746 r = hdmi5_core_init(pdev, &hdmi.core);
747 if (r)
c84c3a5b 748 goto err;
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749
750 irq = platform_get_irq(pdev, 0);
751 if (irq < 0) {
752 DSSERR("platform_get_irq failed\n");
c84c3a5b
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753 r = -ENODEV;
754 goto err;
f5bab222
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755 }
756
757 r = devm_request_threaded_irq(&pdev->dev, irq,
758 NULL, hdmi_irq_handler,
759 IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
760 if (r) {
761 DSSERR("HDMI IRQ request failed\n");
c84c3a5b 762 goto err;
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763 }
764
765 pm_runtime_enable(&pdev->dev);
766
767 hdmi_init_output(pdev);
768
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769 r = hdmi_audio_register(&pdev->dev);
770 if (r) {
771 DSSERR("Registering HDMI audio failed %d\n", r);
772 hdmi_uninit_output(pdev);
773 pm_runtime_disable(&pdev->dev);
774 return r;
775 }
776
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777 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
778
779 return 0;
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780err:
781 hdmi_pll_uninit(&hdmi.pll);
782 return r;
f5bab222
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783}
784
736e60dd 785static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
f5bab222 786{
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787 struct platform_device *pdev = to_platform_device(dev);
788
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789 if (hdmi.audio_pdev)
790 platform_device_unregister(hdmi.audio_pdev);
791
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792 hdmi_uninit_output(pdev);
793
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794 hdmi_pll_uninit(&hdmi.pll);
795
f5bab222 796 pm_runtime_disable(&pdev->dev);
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797}
798
799static const struct component_ops hdmi5_component_ops = {
800 .bind = hdmi5_bind,
801 .unbind = hdmi5_unbind,
802};
f5bab222 803
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804static int hdmi5_probe(struct platform_device *pdev)
805{
806 return component_add(&pdev->dev, &hdmi5_component_ops);
807}
808
809static int hdmi5_remove(struct platform_device *pdev)
810{
811 component_del(&pdev->dev, &hdmi5_component_ops);
f5bab222
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812 return 0;
813}
814
815static int hdmi_runtime_suspend(struct device *dev)
816{
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817 dispc_runtime_put();
818
819 return 0;
820}
821
822static int hdmi_runtime_resume(struct device *dev)
823{
824 int r;
825
826 r = dispc_runtime_get();
827 if (r < 0)
828 return r;
829
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830 return 0;
831}
832
833static const struct dev_pm_ops hdmi_pm_ops = {
834 .runtime_suspend = hdmi_runtime_suspend,
835 .runtime_resume = hdmi_runtime_resume,
836};
837
838static const struct of_device_id hdmi_of_match[] = {
839 { .compatible = "ti,omap5-hdmi", },
adb5ff83 840 { .compatible = "ti,dra7-hdmi", },
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841 {},
842};
843
844static struct platform_driver omapdss_hdmihw_driver = {
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845 .probe = hdmi5_probe,
846 .remove = hdmi5_remove,
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847 .driver = {
848 .name = "omapdss_hdmi5",
f5bab222
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849 .pm = &hdmi_pm_ops,
850 .of_match_table = hdmi_of_match,
422ccbd5 851 .suppress_bind_attrs = true,
f5bab222
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852 },
853};
854
855int __init hdmi5_init_platform_driver(void)
856{
857 return platform_driver_register(&omapdss_hdmihw_driver);
858}
859
ede92695 860void hdmi5_uninit_platform_driver(void)
f5bab222
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861{
862 platform_driver_unregister(&omapdss_hdmihw_driver);
863}