drm/omap: fix maximum sizes
[linux-2.6-block.git] / drivers / gpu / drm / omapdrm / dss / hdmi5.c
CommitLineData
f5bab222
TV
1/*
2 * HDMI driver for OMAP5
3 *
bb5cdf8d 4 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
f5bab222
TV
5 *
6 * Authors:
7 * Yong Zhi
8 * Mythri pk
9 * Archit Taneja <archit@ti.com>
10 * Tomi Valkeinen <tomi.valkeinen@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published by
14 * the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program. If not, see <http://www.gnu.org/licenses/>.
23 */
24
25#define DSS_SUBSYS_NAME "HDMI"
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/interrupt.h>
32#include <linux/mutex.h>
33#include <linux/delay.h>
34#include <linux/string.h>
35#include <linux/platform_device.h>
36#include <linux/pm_runtime.h>
37#include <linux/clk.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
736e60dd 40#include <linux/component.h>
d9e32ecd 41#include <linux/of.h>
09bffa6e 42#include <linux/of_graph.h>
45302d7e 43#include <sound/omap-hdmi-audio.h>
f5bab222 44
32043da7 45#include "omapdss.h"
f5bab222
TV
46#include "hdmi5_core.h"
47#include "dss.h"
f5bab222 48
c44991ce 49static int hdmi_runtime_get(struct omap_hdmi *hdmi)
f5bab222
TV
50{
51 int r;
52
53 DSSDBG("hdmi_runtime_get\n");
54
c44991ce 55 r = pm_runtime_get_sync(&hdmi->pdev->dev);
f5bab222
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56 WARN_ON(r < 0);
57 if (r < 0)
58 return r;
59
60 return 0;
61}
62
c44991ce 63static void hdmi_runtime_put(struct omap_hdmi *hdmi)
f5bab222
TV
64{
65 int r;
66
67 DSSDBG("hdmi_runtime_put\n");
68
c44991ce 69 r = pm_runtime_put_sync(&hdmi->pdev->dev);
f5bab222
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70 WARN_ON(r < 0 && r != -ENOSYS);
71}
72
73static irqreturn_t hdmi_irq_handler(int irq, void *data)
74{
c44991ce
LP
75 struct omap_hdmi *hdmi = data;
76 struct hdmi_wp_data *wp = &hdmi->wp;
f5bab222
TV
77 u32 irqstatus;
78
79 irqstatus = hdmi_wp_get_irqstatus(wp);
80 hdmi_wp_set_irqstatus(wp, irqstatus);
81
82 if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
83 irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
84 u32 v;
85 /*
86 * If we get both connect and disconnect interrupts at the same
87 * time, turn off the PHY, clear interrupts, and restart, which
88 * raises connect interrupt if a cable is connected, or nothing
89 * if cable is not connected.
90 */
91
92 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
93
94 /*
95 * We always get bogus CONNECT & DISCONNECT interrupts when
96 * setting the PHY to LDOON. To ignore those, we force the RXDET
97 * line to 0 until the PHY power state has been changed.
98 */
c44991ce 99 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
f5bab222
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100 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
101 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
c44991ce 102 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
f5bab222
TV
103
104 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
105 HDMI_IRQ_LINK_DISCONNECT);
106
107 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
108
c44991ce 109 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
f5bab222
TV
110
111 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
112 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
113 } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
114 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
115 }
116
117 return IRQ_HANDLED;
118}
119
c44991ce 120static int hdmi_init_regulator(struct omap_hdmi *hdmi)
f5bab222 121{
f5bab222
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122 struct regulator *reg;
123
c44991ce 124 if (hdmi->vdda_reg != NULL)
f5bab222
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125 return 0;
126
c44991ce 127 reg = devm_regulator_get(&hdmi->pdev->dev, "vdda");
f5bab222
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128 if (IS_ERR(reg)) {
129 DSSERR("can't get VDDA regulator\n");
130 return PTR_ERR(reg);
131 }
132
c44991ce 133 hdmi->vdda_reg = reg;
f5bab222
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134
135 return 0;
136}
137
c44991ce 138static int hdmi_power_on_core(struct omap_hdmi *hdmi)
f5bab222
TV
139{
140 int r;
141
c44991ce 142 r = regulator_enable(hdmi->vdda_reg);
f5bab222
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143 if (r)
144 return r;
145
c44991ce 146 r = hdmi_runtime_get(hdmi);
f5bab222
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147 if (r)
148 goto err_runtime_get;
149
150 /* Make selection of HDMI in DSS */
c44991ce 151 dss_select_hdmi_venc_clk_source(hdmi->dss, DSS_HDMI_M_PCLK);
f5bab222 152
c44991ce 153 hdmi->core_enabled = true;
f5bab222
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154
155 return 0;
156
157err_runtime_get:
c44991ce 158 regulator_disable(hdmi->vdda_reg);
f5bab222
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159
160 return r;
161}
162
c44991ce 163static void hdmi_power_off_core(struct omap_hdmi *hdmi)
f5bab222 164{
c44991ce 165 hdmi->core_enabled = false;
f5bab222 166
c44991ce
LP
167 hdmi_runtime_put(hdmi);
168 regulator_disable(hdmi->vdda_reg);
f5bab222
TV
169}
170
c44991ce 171static int hdmi_power_on_full(struct omap_hdmi *hdmi)
f5bab222
TV
172{
173 int r;
da11bbbb 174 struct videomode *vm;
c84c3a5b 175 struct dss_pll_clock_info hdmi_cinfo = { 0 };
d11e5c82 176 unsigned int pc;
f5bab222 177
c44991ce 178 r = hdmi_power_on_core(hdmi);
f5bab222
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179 if (r)
180 return r;
181
c44991ce 182 vm = &hdmi->cfg.vm;
f5bab222 183
da11bbbb
PU
184 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
185 vm->vactive);
f5bab222 186
da11bbbb
PU
187 pc = vm->pixelclock;
188 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
67d8ffdd
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189 pc *= 2;
190
c107751d
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191 /* DSS_HDMI_TCLK is bitclk / 10 */
192 pc *= 10;
193
c44991ce 194 dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
c17dc0e3 195 pc, &hdmi_cinfo);
f5bab222
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196
197 /* disable and clear irqs */
c44991ce
LP
198 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
199 hdmi_wp_set_irqstatus(&hdmi->wp,
200 hdmi_wp_get_irqstatus(&hdmi->wp));
f5bab222 201
c44991ce 202 r = dss_pll_enable(&hdmi->pll.pll);
f5bab222 203 if (r) {
c2fbd061 204 DSSERR("Failed to enable PLL\n");
f5bab222
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205 goto err_pll_enable;
206 }
207
c44991ce 208 r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
c2fbd061
TV
209 if (r) {
210 DSSERR("Failed to configure PLL\n");
211 goto err_pll_cfg;
212 }
213
c44991ce 214 r = hdmi_phy_configure(&hdmi->phy, hdmi_cinfo.clkdco,
c84c3a5b 215 hdmi_cinfo.clkout[0]);
f5bab222
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216 if (r) {
217 DSSDBG("Failed to start PHY\n");
218 goto err_phy_cfg;
219 }
220
c44991ce 221 r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON);
f5bab222
TV
222 if (r)
223 goto err_phy_pwr;
224
c44991ce 225 hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
f5bab222 226
f5bab222 227 /* tv size */
c44991ce 228 dss_mgr_set_timings(&hdmi->output, vm);
f5bab222 229
c44991ce 230 r = dss_mgr_enable(&hdmi->output);
f5bab222
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231 if (r)
232 goto err_mgr_enable;
233
c44991ce 234 r = hdmi_wp_video_start(&hdmi->wp);
4e4b53ce
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235 if (r)
236 goto err_vid_enable;
237
c44991ce 238 hdmi_wp_set_irqenable(&hdmi->wp,
f5bab222
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239 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
240
241 return 0;
242
f5bab222 243err_vid_enable:
c44991ce 244 dss_mgr_disable(&hdmi->output);
4e4b53ce 245err_mgr_enable:
c44991ce 246 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
f5bab222
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247err_phy_pwr:
248err_phy_cfg:
c2fbd061 249err_pll_cfg:
c44991ce 250 dss_pll_disable(&hdmi->pll.pll);
f5bab222 251err_pll_enable:
c44991ce 252 hdmi_power_off_core(hdmi);
f5bab222
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253 return -EIO;
254}
255
c44991ce 256static void hdmi_power_off_full(struct omap_hdmi *hdmi)
f5bab222 257{
c44991ce 258 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
f5bab222 259
c44991ce 260 hdmi_wp_video_stop(&hdmi->wp);
f5bab222 261
c44991ce 262 dss_mgr_disable(&hdmi->output);
4e4b53ce 263
c44991ce 264 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
f5bab222 265
c44991ce 266 dss_pll_disable(&hdmi->pll.pll);
f5bab222 267
c44991ce 268 hdmi_power_off_core(hdmi);
f5bab222
TV
269}
270
271static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
da11bbbb 272 struct videomode *vm)
f5bab222 273{
c44991ce
LP
274 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
275
276 if (!dispc_mgr_timings_ok(hdmi->dss->dispc, dssdev->dispc_channel, vm))
f5bab222
TV
277 return -EINVAL;
278
279 return 0;
280}
281
282static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
da11bbbb 283 struct videomode *vm)
f5bab222 284{
c44991ce
LP
285 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
286
287 mutex_lock(&hdmi->lock);
f5bab222 288
c44991ce 289 hdmi->cfg.vm = *vm;
f5bab222 290
c44991ce 291 dispc_set_tv_pclk(hdmi->dss->dispc, vm->pixelclock);
f5bab222 292
c44991ce 293 mutex_unlock(&hdmi->lock);
f5bab222
TV
294}
295
296static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
da11bbbb 297 struct videomode *vm)
f5bab222 298{
c44991ce
LP
299 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
300
301 *vm = hdmi->cfg.vm;
f5bab222
TV
302}
303
f33656e1 304static int hdmi_dump_regs(struct seq_file *s, void *p)
f5bab222 305{
c44991ce
LP
306 struct omap_hdmi *hdmi = s->private;
307
308 mutex_lock(&hdmi->lock);
f5bab222 309
c44991ce
LP
310 if (hdmi_runtime_get(hdmi)) {
311 mutex_unlock(&hdmi->lock);
f33656e1 312 return 0;
f5bab222
TV
313 }
314
c44991ce
LP
315 hdmi_wp_dump(&hdmi->wp, s);
316 hdmi_pll_dump(&hdmi->pll, s);
317 hdmi_phy_dump(&hdmi->phy, s);
318 hdmi5_core_dump(&hdmi->core, s);
f5bab222 319
c44991ce
LP
320 hdmi_runtime_put(hdmi);
321 mutex_unlock(&hdmi->lock);
f33656e1 322 return 0;
f5bab222
TV
323}
324
c44991ce 325static int read_edid(struct omap_hdmi *hdmi, u8 *buf, int len)
f5bab222
TV
326{
327 int r;
328 int idlemode;
329
c44991ce 330 mutex_lock(&hdmi->lock);
f5bab222 331
c44991ce 332 r = hdmi_runtime_get(hdmi);
f5bab222
TV
333 BUG_ON(r);
334
c44991ce 335 idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
f5bab222 336 /* No-idle mode */
c44991ce 337 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
f5bab222 338
c44991ce 339 r = hdmi5_read_edid(&hdmi->core, buf, len);
f5bab222 340
c44991ce 341 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
f5bab222 342
c44991ce
LP
343 hdmi_runtime_put(hdmi);
344 mutex_unlock(&hdmi->lock);
f5bab222
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345
346 return r;
347}
348
8a9d4626
JS
349static void hdmi_start_audio_stream(struct omap_hdmi *hd)
350{
c44991ce 351 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
8a9d4626
JS
352 hdmi_wp_audio_enable(&hd->wp, true);
353 hdmi_wp_audio_core_req_enable(&hd->wp, true);
354}
355
356static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
357{
358 hdmi_wp_audio_core_req_enable(&hd->wp, false);
359 hdmi_wp_audio_enable(&hd->wp, false);
360 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
361}
362
f5bab222
TV
363static int hdmi_display_enable(struct omap_dss_device *dssdev)
364{
c44991ce 365 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
8a9d4626 366 unsigned long flags;
f5bab222
TV
367 int r = 0;
368
369 DSSDBG("ENTER hdmi_display_enable\n");
370
c44991ce 371 mutex_lock(&hdmi->lock);
f5bab222 372
c44991ce 373 if (!dssdev->dispc_channel_connected) {
f5bab222
TV
374 DSSERR("failed to enable display: no output/manager\n");
375 r = -ENODEV;
376 goto err0;
377 }
378
c44991ce 379 r = hdmi_power_on_full(hdmi);
f5bab222
TV
380 if (r) {
381 DSSERR("failed to power on device\n");
382 goto err0;
383 }
384
c44991ce
LP
385 if (hdmi->audio_configured) {
386 r = hdmi5_audio_config(&hdmi->core, &hdmi->wp,
387 &hdmi->audio_config,
388 hdmi->cfg.vm.pixelclock);
8a9d4626
JS
389 if (r) {
390 DSSERR("Error restoring audio configuration: %d", r);
c44991ce
LP
391 hdmi->audio_abort_cb(&hdmi->pdev->dev);
392 hdmi->audio_configured = false;
8a9d4626
JS
393 }
394 }
395
c44991ce
LP
396 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
397 if (hdmi->audio_configured && hdmi->audio_playing)
398 hdmi_start_audio_stream(hdmi);
399 hdmi->display_enabled = true;
400 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
45302d7e 401
c44991ce 402 mutex_unlock(&hdmi->lock);
f5bab222
TV
403 return 0;
404
405err0:
c44991ce 406 mutex_unlock(&hdmi->lock);
f5bab222
TV
407 return r;
408}
409
410static void hdmi_display_disable(struct omap_dss_device *dssdev)
411{
c44991ce 412 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
8a9d4626
JS
413 unsigned long flags;
414
f5bab222
TV
415 DSSDBG("Enter hdmi_display_disable\n");
416
c44991ce 417 mutex_lock(&hdmi->lock);
f5bab222 418
c44991ce
LP
419 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
420 hdmi_stop_audio_stream(hdmi);
421 hdmi->display_enabled = false;
422 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
45302d7e 423
c44991ce 424 hdmi_power_off_full(hdmi);
f5bab222 425
c44991ce 426 mutex_unlock(&hdmi->lock);
f5bab222
TV
427}
428
c44991ce 429static int hdmi_core_enable(struct omap_hdmi *hdmi)
f5bab222
TV
430{
431 int r = 0;
432
433 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
434
c44991ce 435 mutex_lock(&hdmi->lock);
f5bab222 436
c44991ce 437 r = hdmi_power_on_core(hdmi);
f5bab222
TV
438 if (r) {
439 DSSERR("failed to power on device\n");
440 goto err0;
441 }
442
c44991ce 443 mutex_unlock(&hdmi->lock);
f5bab222
TV
444 return 0;
445
446err0:
c44991ce 447 mutex_unlock(&hdmi->lock);
f5bab222
TV
448 return r;
449}
450
c44991ce 451static void hdmi_core_disable(struct omap_hdmi *hdmi)
f5bab222
TV
452{
453 DSSDBG("Enter omapdss_hdmi_core_disable\n");
454
c44991ce 455 mutex_lock(&hdmi->lock);
f5bab222 456
c44991ce 457 hdmi_power_off_core(hdmi);
f5bab222 458
c44991ce 459 mutex_unlock(&hdmi->lock);
f5bab222
TV
460}
461
f5bab222
TV
462static int hdmi_connect(struct omap_dss_device *dssdev,
463 struct omap_dss_device *dst)
464{
c44991ce 465 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
f5bab222
TV
466 int r;
467
c44991ce 468 r = hdmi_init_regulator(hdmi);
f5bab222
TV
469 if (r)
470 return r;
471
c44991ce 472 r = dss_mgr_connect(&hdmi->output, dssdev);
f5bab222
TV
473 if (r)
474 return r;
475
476 r = omapdss_output_set_device(dssdev, dst);
477 if (r) {
478 DSSERR("failed to connect output to new device: %s\n",
479 dst->name);
c44991ce 480 dss_mgr_disconnect(&hdmi->output, dssdev);
f5bab222
TV
481 return r;
482 }
483
484 return 0;
485}
486
487static void hdmi_disconnect(struct omap_dss_device *dssdev,
488 struct omap_dss_device *dst)
489{
c44991ce
LP
490 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
491
f5bab222
TV
492 WARN_ON(dst != dssdev->dst);
493
494 if (dst != dssdev->dst)
495 return;
496
497 omapdss_output_unset_device(dssdev);
498
c44991ce 499 dss_mgr_disconnect(&hdmi->output, dssdev);
f5bab222
TV
500}
501
502static int hdmi_read_edid(struct omap_dss_device *dssdev,
503 u8 *edid, int len)
504{
c44991ce 505 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
f5bab222
TV
506 bool need_enable;
507 int r;
508
c44991ce 509 need_enable = hdmi->core_enabled == false;
f5bab222
TV
510
511 if (need_enable) {
c44991ce 512 r = hdmi_core_enable(hdmi);
f5bab222
TV
513 if (r)
514 return r;
515 }
516
c44991ce 517 r = read_edid(hdmi, edid, len);
f5bab222
TV
518
519 if (need_enable)
c44991ce 520 hdmi_core_disable(hdmi);
f5bab222
TV
521
522 return r;
523}
524
769dcb11
TV
525static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
526 const struct hdmi_avi_infoframe *avi)
527{
c44991ce
LP
528 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
529
530 hdmi->cfg.infoframe = *avi;
769dcb11
TV
531 return 0;
532}
533
534static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
535 bool hdmi_mode)
536{
c44991ce
LP
537 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
538
539 hdmi->cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
769dcb11
TV
540 return 0;
541}
542
f5bab222
TV
543static const struct omapdss_hdmi_ops hdmi_ops = {
544 .connect = hdmi_connect,
545 .disconnect = hdmi_disconnect,
546
547 .enable = hdmi_display_enable,
548 .disable = hdmi_display_disable,
549
550 .check_timings = hdmi_display_check_timing,
551 .set_timings = hdmi_display_set_timing,
552 .get_timings = hdmi_display_get_timings,
553
554 .read_edid = hdmi_read_edid,
769dcb11
TV
555 .set_infoframe = hdmi_set_infoframe,
556 .set_hdmi_mode = hdmi_set_hdmi_mode,
f5bab222
TV
557};
558
c44991ce 559static void hdmi_init_output(struct omap_hdmi *hdmi)
f5bab222 560{
c44991ce 561 struct omap_dss_device *out = &hdmi->output;
f5bab222 562
c44991ce 563 out->dev = &hdmi->pdev->dev;
f5bab222
TV
564 out->id = OMAP_DSS_OUTPUT_HDMI;
565 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
566 out->name = "hdmi.0";
567 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
568 out->ops.hdmi = &hdmi_ops;
569 out->owner = THIS_MODULE;
570
571 omapdss_register_output(out);
572}
573
c44991ce 574static void hdmi_uninit_output(struct omap_hdmi *hdmi)
f5bab222 575{
c44991ce 576 struct omap_dss_device *out = &hdmi->output;
f5bab222
TV
577
578 omapdss_unregister_output(out);
579}
580
c44991ce 581static int hdmi_probe_of(struct omap_hdmi *hdmi)
f5bab222 582{
c44991ce 583 struct platform_device *pdev = hdmi->pdev;
f5bab222
TV
584 struct device_node *node = pdev->dev.of_node;
585 struct device_node *ep;
586 int r;
587
09bffa6e 588 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
f5bab222
TV
589 if (!ep)
590 return 0;
591
c44991ce 592 r = hdmi_parse_lanes_of(pdev, ep, &hdmi->phy);
f5bab222
TV
593 if (r)
594 goto err;
595
596 of_node_put(ep);
597 return 0;
598
599err:
600 of_node_put(ep);
601 return r;
602}
603
45302d7e
JS
604/* Audio callbacks */
605static int hdmi_audio_startup(struct device *dev,
606 void (*abort_cb)(struct device *dev))
607{
608 struct omap_hdmi *hd = dev_get_drvdata(dev);
609 int ret = 0;
610
611 mutex_lock(&hd->lock);
612
613 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
614 ret = -EPERM;
615 goto out;
616 }
617
618 hd->audio_abort_cb = abort_cb;
619
620out:
621 mutex_unlock(&hd->lock);
622
623 return ret;
624}
625
626static int hdmi_audio_shutdown(struct device *dev)
627{
628 struct omap_hdmi *hd = dev_get_drvdata(dev);
629
630 mutex_lock(&hd->lock);
631 hd->audio_abort_cb = NULL;
8a9d4626
JS
632 hd->audio_configured = false;
633 hd->audio_playing = false;
45302d7e
JS
634 mutex_unlock(&hd->lock);
635
636 return 0;
637}
638
639static int hdmi_audio_start(struct device *dev)
640{
641 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 642 unsigned long flags;
45302d7e
JS
643
644 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
45302d7e 645
8a9d4626 646 spin_lock_irqsave(&hd->audio_playing_lock, flags);
2d7639bc 647
8a9d4626
JS
648 if (hd->display_enabled)
649 hdmi_start_audio_stream(hd);
650 hd->audio_playing = true;
45302d7e 651
8a9d4626 652 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
653 return 0;
654}
655
656static void hdmi_audio_stop(struct device *dev)
657{
658 struct omap_hdmi *hd = dev_get_drvdata(dev);
8a9d4626 659 unsigned long flags;
45302d7e
JS
660
661 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
45302d7e 662
8a9d4626
JS
663 spin_lock_irqsave(&hd->audio_playing_lock, flags);
664
665 if (hd->display_enabled)
666 hdmi_stop_audio_stream(hd);
667 hd->audio_playing = false;
2d7639bc 668
8a9d4626 669 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
45302d7e
JS
670}
671
672static int hdmi_audio_config(struct device *dev,
673 struct omap_dss_audio *dss_audio)
674{
675 struct omap_hdmi *hd = dev_get_drvdata(dev);
676 int ret;
677
678 mutex_lock(&hd->lock);
679
680 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
681 ret = -EPERM;
682 goto out;
683 }
684
685 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
da11bbbb 686 hd->cfg.vm.pixelclock);
45302d7e 687
8a9d4626
JS
688 if (!ret) {
689 hd->audio_configured = true;
690 hd->audio_config = *dss_audio;
691 }
45302d7e
JS
692out:
693 mutex_unlock(&hd->lock);
694
695 return ret;
696}
697
698static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
699 .audio_startup = hdmi_audio_startup,
700 .audio_shutdown = hdmi_audio_shutdown,
701 .audio_start = hdmi_audio_start,
702 .audio_stop = hdmi_audio_stop,
703 .audio_config = hdmi_audio_config,
704};
705
c44991ce 706static int hdmi_audio_register(struct omap_hdmi *hdmi)
45302d7e
JS
707{
708 struct omap_hdmi_audio_pdata pdata = {
c44991ce 709 .dev = &hdmi->pdev->dev,
d20fa5a0 710 .version = 5,
c44991ce 711 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
45302d7e
JS
712 .ops = &hdmi_audio_ops,
713 };
714
c44991ce
LP
715 hdmi->audio_pdev = platform_device_register_data(
716 &hdmi->pdev->dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
45302d7e
JS
717 &pdata, sizeof(pdata));
718
c44991ce
LP
719 if (IS_ERR(hdmi->audio_pdev))
720 return PTR_ERR(hdmi->audio_pdev);
45302d7e 721
c44991ce
LP
722 hdmi_runtime_get(hdmi);
723 hdmi->wp_idlemode =
724 REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
725 hdmi_runtime_put(hdmi);
8a9d4626 726
45302d7e
JS
727 return 0;
728}
729
f5bab222 730/* HDMI HW IP initialisation */
736e60dd 731static int hdmi5_bind(struct device *dev, struct device *master, void *data)
f5bab222 732{
736e60dd 733 struct platform_device *pdev = to_platform_device(dev);
7b295257 734 struct dss_device *dss = dss_get_device(master);
c44991ce 735 struct omap_hdmi *hdmi;
f5bab222
TV
736 int r;
737 int irq;
738
c44991ce
LP
739 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
740 if (!hdmi)
741 return -ENOMEM;
f5bab222 742
c44991ce
LP
743 hdmi->pdev = pdev;
744 hdmi->dss = dss;
745 dev_set_drvdata(&pdev->dev, hdmi);
f5bab222 746
c44991ce
LP
747 mutex_init(&hdmi->lock);
748 spin_lock_init(&hdmi->audio_playing_lock);
749
750 r = hdmi_probe_of(hdmi);
1dff212c 751 if (r)
c44991ce 752 goto err_free;
f5bab222 753
c44991ce 754 r = hdmi_wp_init(pdev, &hdmi->wp, 5);
f5bab222 755 if (r)
c44991ce 756 goto err_free;
f5bab222 757
c44991ce 758 r = hdmi_pll_init(dss, pdev, &hdmi->pll, &hdmi->wp);
f5bab222 759 if (r)
c44991ce 760 goto err_free;
f5bab222 761
c44991ce 762 r = hdmi_phy_init(pdev, &hdmi->phy, 5);
f5bab222 763 if (r)
c44991ce 764 goto err_pll;
f5bab222 765
c44991ce 766 r = hdmi5_core_init(pdev, &hdmi->core);
f5bab222 767 if (r)
c44991ce 768 goto err_pll;
f5bab222
TV
769
770 irq = platform_get_irq(pdev, 0);
771 if (irq < 0) {
772 DSSERR("platform_get_irq failed\n");
c84c3a5b 773 r = -ENODEV;
c44991ce 774 goto err_pll;
f5bab222
TV
775 }
776
777 r = devm_request_threaded_irq(&pdev->dev, irq,
778 NULL, hdmi_irq_handler,
c44991ce 779 IRQF_ONESHOT, "OMAP HDMI", hdmi);
f5bab222
TV
780 if (r) {
781 DSSERR("HDMI IRQ request failed\n");
c44991ce 782 goto err_pll;
f5bab222
TV
783 }
784
785 pm_runtime_enable(&pdev->dev);
786
c44991ce 787 hdmi_init_output(hdmi);
f5bab222 788
c44991ce 789 r = hdmi_audio_register(hdmi);
45302d7e
JS
790 if (r) {
791 DSSERR("Registering HDMI audio failed %d\n", r);
c44991ce 792 hdmi_uninit_output(hdmi);
45302d7e
JS
793 pm_runtime_disable(&pdev->dev);
794 return r;
795 }
796
c44991ce
LP
797 hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
798 hdmi);
f5bab222
TV
799
800 return 0;
c44991ce
LP
801
802err_pll:
803 hdmi_pll_uninit(&hdmi->pll);
804err_free:
805 kfree(hdmi);
c84c3a5b 806 return r;
f5bab222
TV
807}
808
736e60dd 809static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
f5bab222 810{
c44991ce
LP
811 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
812
813 dss_debugfs_remove_file(hdmi->debugfs);
736e60dd 814
c44991ce
LP
815 if (hdmi->audio_pdev)
816 platform_device_unregister(hdmi->audio_pdev);
f33656e1 817
c44991ce 818 hdmi_uninit_output(hdmi);
45302d7e 819
c44991ce 820 hdmi_pll_uninit(&hdmi->pll);
f5bab222 821
c44991ce 822 pm_runtime_disable(dev);
c84c3a5b 823
c44991ce 824 kfree(hdmi);
736e60dd
TV
825}
826
827static const struct component_ops hdmi5_component_ops = {
828 .bind = hdmi5_bind,
829 .unbind = hdmi5_unbind,
830};
f5bab222 831
736e60dd
TV
832static int hdmi5_probe(struct platform_device *pdev)
833{
834 return component_add(&pdev->dev, &hdmi5_component_ops);
835}
836
837static int hdmi5_remove(struct platform_device *pdev)
838{
839 component_del(&pdev->dev, &hdmi5_component_ops);
f5bab222
TV
840 return 0;
841}
842
843static int hdmi_runtime_suspend(struct device *dev)
844{
50638ae5
LP
845 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
846
847 dispc_runtime_put(hdmi->dss->dispc);
f5bab222
TV
848
849 return 0;
850}
851
852static int hdmi_runtime_resume(struct device *dev)
853{
50638ae5 854 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
f5bab222
TV
855 int r;
856
50638ae5 857 r = dispc_runtime_get(hdmi->dss->dispc);
f5bab222
TV
858 if (r < 0)
859 return r;
860
f5bab222
TV
861 return 0;
862}
863
864static const struct dev_pm_ops hdmi_pm_ops = {
865 .runtime_suspend = hdmi_runtime_suspend,
866 .runtime_resume = hdmi_runtime_resume,
867};
868
869static const struct of_device_id hdmi_of_match[] = {
870 { .compatible = "ti,omap5-hdmi", },
adb5ff83 871 { .compatible = "ti,dra7-hdmi", },
f5bab222
TV
872 {},
873};
874
d66c36a3 875struct platform_driver omapdss_hdmi5hw_driver = {
736e60dd
TV
876 .probe = hdmi5_probe,
877 .remove = hdmi5_remove,
f5bab222
TV
878 .driver = {
879 .name = "omapdss_hdmi5",
f5bab222
TV
880 .pm = &hdmi_pm_ops,
881 .of_match_table = hdmi_of_match,
422ccbd5 882 .suppress_bind_attrs = true,
f5bab222
TV
883 },
884};