[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nvkm / subdev / mc / gf100.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "priv.h"

static const struct nvkm_mc_map
gf100_mc_reset[] = {
	{ 0x00020000, NVKM_ENGINE_MSPDEC },
	{ 0x00008000, NVKM_ENGINE_MSVLD },
	{ 0x00001000, NVKM_ENGINE_GR },
	{ 0x00000100, NVKM_ENGINE_FIFO },
	{ 0x00000080, NVKM_ENGINE_CE1 },
	{ 0x00000040, NVKM_ENGINE_CE0 },
	{ 0x00000002, NVKM_ENGINE_MSPPP },
	{}
};

static const struct nvkm_mc_map
gf100_mc_intr[] = {
	{ 0x04000000, NVKM_ENGINE_DISP },
	{ 0x00020000, NVKM_ENGINE_MSPDEC },
	{ 0x00008000, NVKM_ENGINE_MSVLD },
	{ 0x00001000, NVKM_ENGINE_GR },
	{ 0x00000100, NVKM_ENGINE_FIFO },
	{ 0x00000040, NVKM_ENGINE_CE1 },
	{ 0x00000020, NVKM_ENGINE_CE0 },
	{ 0x00000001, NVKM_ENGINE_MSPPP },
	{ 0x40000000, NVKM_SUBDEV_IBUS },
	{ 0x10000000, NVKM_SUBDEV_BUS },
	{ 0x08000000, NVKM_SUBDEV_FB },
	{ 0x02000000, NVKM_SUBDEV_LTC },
	{ 0x01000000, NVKM_SUBDEV_PMU },
	{ 0x00200000, NVKM_SUBDEV_GPIO },
	{ 0x00200000, NVKM_SUBDEV_I2C },
	{ 0x00100000, NVKM_SUBDEV_TIMER },
	{ 0x00040000, NVKM_SUBDEV_THERM },
	{ 0x00002000, NVKM_SUBDEV_FB },
	{},
};

void
gf100_mc_intr_unarm(struct nvkm_mc *mc)
{
	struct nvkm_device *device = mc->subdev.device;
	nvkm_wr32(device, 0x000140, 0x00000000);
	nvkm_wr32(device, 0x000144, 0x00000000);
	nvkm_rd32(device, 0x000140);
}

void
gf100_mc_intr_rearm(struct nvkm_mc *mc)
{
	struct nvkm_device *device = mc->subdev.device;
	nvkm_wr32(device, 0x000140, 0x00000001);
	nvkm_wr32(device, 0x000144, 0x00000001);
}

u32
gf100_mc_intr_mask(struct nvkm_mc *mc)
{
	struct nvkm_device *device = mc->subdev.device;
	u32 intr0 = nvkm_rd32(device, 0x000100);
	u32 intr1 = nvkm_rd32(device, 0x000104);
	return intr0 | intr1;
}

void
gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
{
	nvkm_wr32(mc->subdev.device, 0x000260, data);
}

static const struct nvkm_mc_func
gf100_mc = {
	.init = nv50_mc_init,
	.intr = gf100_mc_intr,
	.intr_unarm = gf100_mc_intr_unarm,
	.intr_rearm = gf100_mc_intr_rearm,
	.intr_mask = gf100_mc_intr_mask,
	.reset = gf100_mc_reset,
	.unk260 = gf100_mc_unk260,
};

int
gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
{
	return nvkm_mc_new_(&gf100_mc, device, index, pmc);
}
Commit	Line	Data
7d9115de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
54dcadd5	24	#include "priv.h"
7d9115de	25
a6bb38e9 BS	26	static const struct nvkm_mc_map
	27	gf100_mc_reset[] = {
	28	{ 0x00020000, NVKM_ENGINE_MSPDEC },
68f3f702	29	{ 0x00008000, NVKM_ENGINE_MSVLD },
a6bb38e9 BS	30	{ 0x00001000, NVKM_ENGINE_GR },
	31	{ 0x00000100, NVKM_ENGINE_FIFO },
	32	{ 0x00000080, NVKM_ENGINE_CE1 },
	33	{ 0x00000040, NVKM_ENGINE_CE0 },
	34	{ 0x00000002, NVKM_ENGINE_MSPPP },
	35	{}
	36	};
	37
	38	static const struct nvkm_mc_map
	39	gf100_mc_intr[] = {
	40	{ 0x04000000, NVKM_ENGINE_DISP },
68f3f702	41	{ 0x00020000, NVKM_ENGINE_MSPDEC },
a6bb38e9 BS	42	{ 0x00008000, NVKM_ENGINE_MSVLD },
	43	{ 0x00001000, NVKM_ENGINE_GR },
	44	{ 0x00000100, NVKM_ENGINE_FIFO },
	45	{ 0x00000040, NVKM_ENGINE_CE1 },
	46	{ 0x00000020, NVKM_ENGINE_CE0 },
	47	{ 0x00000001, NVKM_ENGINE_MSPPP },
68f3f702	48	{ 0x40000000, NVKM_SUBDEV_IBUS },
a6bb38e9 BS	49	{ 0x10000000, NVKM_SUBDEV_BUS },
	50	{ 0x08000000, NVKM_SUBDEV_FB },
	51	{ 0x02000000, NVKM_SUBDEV_LTC },
	52	{ 0x01000000, NVKM_SUBDEV_PMU },
	53	{ 0x00200000, NVKM_SUBDEV_GPIO },
	54	{ 0x00200000, NVKM_SUBDEV_I2C },
	55	{ 0x00100000, NVKM_SUBDEV_TIMER },
	56	{ 0x00040000, NVKM_SUBDEV_THERM },
	57	{ 0x00002000, NVKM_SUBDEV_FB },
7d9115de BS	58	{},
	59	};
	60
ae0a5b2d BS	61	void
	62	gf100_mc_intr_unarm(struct nvkm_mc *mc)
	63	{
	64	struct nvkm_device *device = mc->subdev.device;
	65	nvkm_wr32(device, 0x000140, 0x00000000);
	66	nvkm_wr32(device, 0x000144, 0x00000000);
	67	nvkm_rd32(device, 0x000140);
	68	}
	69
	70	void
	71	gf100_mc_intr_rearm(struct nvkm_mc *mc)
	72	{
	73	struct nvkm_device *device = mc->subdev.device;
	74	nvkm_wr32(device, 0x000140, 0x00000001);
	75	nvkm_wr32(device, 0x000144, 0x00000001);
	76	}
	77
	78	u32
	79	gf100_mc_intr_mask(struct nvkm_mc *mc)
	80	{
	81	struct nvkm_device *device = mc->subdev.device;
	82	u32 intr0 = nvkm_rd32(device, 0x000100);
	83	u32 intr1 = nvkm_rd32(device, 0x000104);
	84	return intr0 \| intr1;
	85	}
	86
7d155dac	87	void
2ca0ddbc	88	gf100_mc_unk260(struct nvkm_mc *mc, u32 data)
7d155dac	89	{
25e3a463	90	nvkm_wr32(mc->subdev.device, 0x000260, data);
7d155dac BS	91	}
7d155dac BS	92
54dcadd5 BS	93	static const struct nvkm_mc_func
	94	gf100_mc = {
	95	.init = nv50_mc_init,
d7e5fcd2	96	.intr = gf100_mc_intr,
ae0a5b2d BS	97	.intr_unarm = gf100_mc_intr_unarm,
	98	.intr_rearm = gf100_mc_intr_rearm,
	99	.intr_mask = gf100_mc_intr_mask,
a6bb38e9	100	.reset = gf100_mc_reset,
d7e5fcd2	101	.unk260 = gf100_mc_unk260,
54dcadd5 BS	102	};
	103
	104	int
	105	gf100_mc_new(struct nvkm_device device, int index, struct nvkm_mc *pmc)
	106	{
	107	return nvkm_mc_new_(&gf100_mc, device, index, pmc);
	108	}