[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / nv20.c

#include "nv20.h"
#include "regs.h"

#include <core/client.h>
#include <core/handle.h>
#include <engine/fifo.h>
#include <subdev/fb.h>
#include <subdev/timer.h>

/*******************************************************************************
 * Graphics object classes
 ******************************************************************************/

static struct nvkm_oclass
nv20_gr_sclass[] = {
	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
	{ 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
	{},
};

/*******************************************************************************
 * PGRAPH context
 ******************************************************************************/

static int
nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
		     struct nvkm_oclass *oclass, void *data, u32 size,
		     struct nvkm_object **pobject)
{
	struct nv20_gr_chan *chan;
	int ret, i;

	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
				     16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
	*pobject = nv_object(chan);
	if (ret)
		return ret;

	chan->chid = nvkm_fifo_chan(parent)->chid;

	nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
	nv_wo32(chan, 0x033c, 0xffff0000);
	nv_wo32(chan, 0x03a0, 0x0fff0000);
	nv_wo32(chan, 0x03a4, 0x0fff0000);
	nv_wo32(chan, 0x047c, 0x00000101);
	nv_wo32(chan, 0x0490, 0x00000111);
	nv_wo32(chan, 0x04a8, 0x44400000);
	for (i = 0x04d4; i <= 0x04e0; i += 4)
		nv_wo32(chan, i, 0x00030303);
	for (i = 0x04f4; i <= 0x0500; i += 4)
		nv_wo32(chan, i, 0x00080000);
	for (i = 0x050c; i <= 0x0518; i += 4)
		nv_wo32(chan, i, 0x01012000);
	for (i = 0x051c; i <= 0x0528; i += 4)
		nv_wo32(chan, i, 0x000105b8);
	for (i = 0x052c; i <= 0x0538; i += 4)
		nv_wo32(chan, i, 0x00080008);
	for (i = 0x055c; i <= 0x0598; i += 4)
		nv_wo32(chan, i, 0x07ff0000);
	nv_wo32(chan, 0x05a4, 0x4b7fffff);
	nv_wo32(chan, 0x05fc, 0x00000001);
	nv_wo32(chan, 0x0604, 0x00004000);
	nv_wo32(chan, 0x0610, 0x00000001);
	nv_wo32(chan, 0x0618, 0x00040000);
	nv_wo32(chan, 0x061c, 0x00010000);
	for (i = 0x1c1c; i <= 0x248c; i += 16) {
		nv_wo32(chan, (i + 0), 0x10700ff9);
		nv_wo32(chan, (i + 4), 0x0436086c);
		nv_wo32(chan, (i + 8), 0x000c001b);
	}
	nv_wo32(chan, 0x281c, 0x3f800000);
	nv_wo32(chan, 0x2830, 0x3f800000);
	nv_wo32(chan, 0x285c, 0x40000000);
	nv_wo32(chan, 0x2860, 0x3f800000);
	nv_wo32(chan, 0x2864, 0x3f000000);
	nv_wo32(chan, 0x286c, 0x40000000);
	nv_wo32(chan, 0x2870, 0x3f800000);
	nv_wo32(chan, 0x2878, 0xbf800000);
	nv_wo32(chan, 0x2880, 0xbf800000);
	nv_wo32(chan, 0x34a4, 0x000fe000);
	nv_wo32(chan, 0x3530, 0x000003f8);
	nv_wo32(chan, 0x3540, 0x002fe000);
	for (i = 0x355c; i <= 0x3578; i += 4)
		nv_wo32(chan, i, 0x001c527c);
	return 0;
}

int
nv20_gr_context_init(struct nvkm_object *object)
{
	struct nv20_gr_priv *priv = (void *)object->engine;
	struct nv20_gr_chan *chan = (void *)object;
	int ret;

	ret = nvkm_gr_context_init(&chan->base);
	if (ret)
		return ret;

	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
	return 0;
}

int
nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
{
	struct nv20_gr_priv *priv = (void *)object->engine;
	struct nv20_gr_chan *chan = (void *)object;
	int chid = -1;

	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	if (nv_rd32(priv, 0x400144) & 0x00010000)
		chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
	if (chan->chid == chid) {
		nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
		nv_wr32(priv, 0x400788, 0x00000002);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
		nv_wr32(priv, 0x400144, 0x10000000);
		nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
	}
	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);

	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
	return nvkm_gr_context_fini(&chan->base, suspend);
}

static struct nvkm_oclass
nv20_gr_cclass = {
	.handle = NV_ENGCTX(GR, 0x20),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv20_gr_context_ctor,
		.dtor = _nvkm_gr_context_dtor,
		.init = nv20_gr_context_init,
		.fini = nv20_gr_context_fini,
		.rd32 = _nvkm_gr_context_rd32,
		.wr32 = _nvkm_gr_context_wr32,
	},
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

void
nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
{
	struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
	struct nvkm_fifo *fifo = nvkm_fifo(engine);
	struct nv20_gr_priv *priv = (void *)engine;
	unsigned long flags;

	fifo->pause(fifo, &flags);
	nv04_gr_idle(priv);

	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);

	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);

	if (nv_device(engine)->chipset != 0x34) {
		nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	}

	fifo->start(fifo, &flags);
}

void
nv20_gr_intr(struct nvkm_subdev *subdev)
{
	struct nvkm_engine *engine = nv_engine(subdev);
	struct nvkm_object *engctx;
	struct nvkm_handle *handle;
	struct nv20_gr_priv *priv = (void *)subdev;
	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	u32 chid = (addr & 0x01f00000) >> 20;
	u32 subc = (addr & 0x00070000) >> 16;
	u32 mthd = (addr & 0x00001ffc);
	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
	u32 show = stat;

	engctx = nvkm_engctx_get(engine, chid);
	if (stat & NV_PGRAPH_INTR_ERROR) {
		if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
			handle = nvkm_handle_get_class(engctx, class);
			if (handle && !nv_call(handle->object, mthd, data))
				show &= ~NV_PGRAPH_INTR_ERROR;
			nvkm_handle_put(handle);
		}
	}

	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);

	if (show) {
		nv_error(priv, "%s", "");
		nvkm_bitfield_print(nv10_gr_intr_name, show);
		pr_cont(" nsource:");
		nvkm_bitfield_print(nv04_gr_nsource, nsource);
		pr_cont(" nstatus:");
		nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
		pr_cont("\n");
		nv_error(priv,
			 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
			 chid, nvkm_client_name(engctx), subc, class, mthd,
			 data);
	}

	nvkm_engctx_put(engctx);
}

static int
nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	     struct nvkm_oclass *oclass, void *data, u32 size,
	     struct nvkm_object **pobject)
{
	struct nv20_gr_priv *priv;
	int ret;

	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
			      NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
	if (ret)
		return ret;

	nv_subdev(priv)->unit = 0x00001000;
	nv_subdev(priv)->intr = nv20_gr_intr;
	nv_engine(priv)->cclass = &nv20_gr_cclass;
	nv_engine(priv)->sclass = nv20_gr_sclass;
	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
	return 0;
}

void
nv20_gr_dtor(struct nvkm_object *object)
{
	struct nv20_gr_priv *priv = (void *)object;
	nvkm_gpuobj_ref(NULL, &priv->ctxtab);
	nvkm_gr_destroy(&priv->base);
}

int
nv20_gr_init(struct nvkm_object *object)
{
	struct nvkm_engine *engine = nv_engine(object);
	struct nv20_gr_priv *priv = (void *)engine;
	struct nvkm_fb *fb = nvkm_fb(object);
	u32 tmp, vramsz;
	int ret, i;

	ret = nvkm_gr_init(&priv->base);
	if (ret)
		return ret;

	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);

	if (nv_device(priv)->chipset == 0x20) {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
		for (i = 0; i < 15; i++)
			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	} else {
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
		for (i = 0; i < 32; i++)
			nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
		nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	}

	nv_wr32(priv, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
	nv_wr32(priv, 0x40009C           , 0x00000040);

	if (nv_device(priv)->chipset >= 0x25) {
		nv_wr32(priv, 0x400890, 0x00a8cfff);
		nv_wr32(priv, 0x400610, 0x304B1FB6);
		nv_wr32(priv, 0x400B80, 0x1cbd3883);
		nv_wr32(priv, 0x400B84, 0x44000000);
		nv_wr32(priv, 0x400098, 0x40000080);
		nv_wr32(priv, 0x400B88, 0x000000ff);

	} else {
		nv_wr32(priv, 0x400880, 0x0008c7df);
		nv_wr32(priv, 0x400094, 0x00000005);
		nv_wr32(priv, 0x400B80, 0x45eae20e);
		nv_wr32(priv, 0x400B84, 0x24000000);
		nv_wr32(priv, 0x400098, 0x00000040);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
		nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
		nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < fb->tile.regions; i++)
		engine->tile_prog(engine, i);

	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));

	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
	nv_wr32(priv, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);

	/* begin RAM config */
	vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
	nv_wr32(priv, 0x400820, 0);
	nv_wr32(priv, 0x400824, 0);
	nv_wr32(priv, 0x400864, vramsz - 1);
	nv_wr32(priv, 0x400868, vramsz - 1);

	/* interesting.. the below overwrites some of the tile setup above.. */
	nv_wr32(priv, 0x400B20, 0x00000000);
	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);

	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
	return 0;
}

struct nvkm_oclass
nv20_gr_oclass = {
	.handle = NV_ENGINE(GR, 0x20),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv20_gr_ctor,
		.dtor = nv20_gr_dtor,
		.init = nv20_gr_init,
		.fini = _nvkm_gr_fini,
	},
};
Commit	Line	Data
e3c71eb2 BS	1	#include "nv20.h"
	2	#include "regs.h"
	3
93260d3c	4	#include <core/client.h>
ebb945a9	5	#include <core/handle.h>
ebb945a9	6	#include <engine/fifo.h>
e3c71eb2 BS	7	#include <subdev/fb.h>
e3c71eb2 BS	8	#include <subdev/timer.h>
ebb945a9 BS	9
	10	/*******************************************************************************
	11	* Graphics object classes
	12	******************************************************************************/
	13
e3c71eb2	14	static struct nvkm_oclass
b8bf04e1 BS	15	nv20_gr_sclass[] = {
	16	{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
	17	{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
	18	{ 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
	19	{ 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
	20	{ 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
	21	{ 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
	22	{ 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
	23	{ 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
	24	{ 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
	25	{ 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
	26	{ 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
	27	{ 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */
	28	{ 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */
	29	{ 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */
	30	{ 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
ebb945a9	31	{},
a0b1de84 BS	32	};
a0b1de84 BS	33
ebb945a9 BS	34	/*******************************************************************************
	35	* PGRAPH context
	36	******************************************************************************/
6ee73861	37
ebb945a9	38	static int
e3c71eb2 BS	39	nv20_gr_context_ctor(struct nvkm_object parent, struct nvkm_object engine,
	40	struct nvkm_oclass oclass, void data, u32 size,
	41	struct nvkm_object **pobject)
a0b1de84	42	{
b8bf04e1	43	struct nv20_gr_chan *chan;
ebb945a9	44	int ret, i;
a0b1de84	45
e3c71eb2 BS	46	ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
e3c71eb2 BS	47	16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
ebb945a9 BS	48	*pobject = nv_object(chan);
	49	if (ret)
	50	return ret;
a0b1de84	51
e3c71eb2	52	chan->chid = nvkm_fifo_chan(parent)->chid;
b8c157d3	53
ebb945a9 BS	54	nv_wo32(chan, 0x0000, 0x00000001 \| (chan->chid << 24));
	55	nv_wo32(chan, 0x033c, 0xffff0000);
	56	nv_wo32(chan, 0x03a0, 0x0fff0000);
	57	nv_wo32(chan, 0x03a4, 0x0fff0000);
	58	nv_wo32(chan, 0x047c, 0x00000101);
	59	nv_wo32(chan, 0x0490, 0x00000111);
	60	nv_wo32(chan, 0x04a8, 0x44400000);
6ee73861	61	for (i = 0x04d4; i <= 0x04e0; i += 4)
ebb945a9	62	nv_wo32(chan, i, 0x00030303);
6ee73861	63	for (i = 0x04f4; i <= 0x0500; i += 4)
ebb945a9	64	nv_wo32(chan, i, 0x00080000);
6ee73861	65	for (i = 0x050c; i <= 0x0518; i += 4)
ebb945a9	66	nv_wo32(chan, i, 0x01012000);
6ee73861	67	for (i = 0x051c; i <= 0x0528; i += 4)
ebb945a9	68	nv_wo32(chan, i, 0x000105b8);
6ee73861	69	for (i = 0x052c; i <= 0x0538; i += 4)
ebb945a9	70	nv_wo32(chan, i, 0x00080008);
6ee73861	71	for (i = 0x055c; i <= 0x0598; i += 4)
ebb945a9 BS	72	nv_wo32(chan, i, 0x07ff0000);
	73	nv_wo32(chan, 0x05a4, 0x4b7fffff);
	74	nv_wo32(chan, 0x05fc, 0x00000001);
	75	nv_wo32(chan, 0x0604, 0x00004000);
	76	nv_wo32(chan, 0x0610, 0x00000001);
	77	nv_wo32(chan, 0x0618, 0x00040000);
	78	nv_wo32(chan, 0x061c, 0x00010000);
6ee73861	79	for (i = 0x1c1c; i <= 0x248c; i += 16) {
ebb945a9 BS	80	nv_wo32(chan, (i + 0), 0x10700ff9);
	81	nv_wo32(chan, (i + 4), 0x0436086c);
	82	nv_wo32(chan, (i + 8), 0x000c001b);
6ee73861	83	}
ebb945a9 BS	84	nv_wo32(chan, 0x281c, 0x3f800000);
	85	nv_wo32(chan, 0x2830, 0x3f800000);
	86	nv_wo32(chan, 0x285c, 0x40000000);
	87	nv_wo32(chan, 0x2860, 0x3f800000);
	88	nv_wo32(chan, 0x2864, 0x3f000000);
	89	nv_wo32(chan, 0x286c, 0x40000000);
	90	nv_wo32(chan, 0x2870, 0x3f800000);
	91	nv_wo32(chan, 0x2878, 0xbf800000);
	92	nv_wo32(chan, 0x2880, 0xbf800000);
	93	nv_wo32(chan, 0x34a4, 0x000fe000);
	94	nv_wo32(chan, 0x3530, 0x000003f8);
	95	nv_wo32(chan, 0x3540, 0x002fe000);
6ee73861	96	for (i = 0x355c; i <= 0x3578; i += 4)
ebb945a9 BS	97	nv_wo32(chan, i, 0x001c527c);
ebb945a9 BS	98	return 0;
6ee73861 BS	99	}
6ee73861 BS	100
ebb945a9	101	int
e3c71eb2	102	nv20_gr_context_init(struct nvkm_object *object)
6ee73861	103	{
b8bf04e1 BS	104	struct nv20_gr_priv priv = (void )object->engine;
b8bf04e1 BS	105	struct nv20_gr_chan chan = (void )object;
ebb945a9	106	int ret;
6ee73861	107
e3c71eb2	108	ret = nvkm_gr_context_init(&chan->base);
ebb945a9 BS	109	if (ret)
ebb945a9 BS	110	return ret;
6ee73861	111
ebb945a9 BS	112	nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
ebb945a9 BS	113	return 0;
6ee73861 BS	114	}
6ee73861 BS	115
ebb945a9	116	int
e3c71eb2	117	nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
6ee73861	118	{
b8bf04e1 BS	119	struct nv20_gr_priv priv = (void )object->engine;
b8bf04e1 BS	120	struct nv20_gr_chan chan = (void )object;
ebb945a9 BS	121	int chid = -1;
	122
	123	nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
	124	if (nv_rd32(priv, 0x400144) & 0x00010000)
	125	chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
	126	if (chan->chid == chid) {
	127	nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
	128	nv_wr32(priv, 0x400788, 0x00000002);
	129	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	130	nv_wr32(priv, 0x400144, 0x10000000);
	131	nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
6ee73861	132	}
ebb945a9	133	nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
6ee73861	134
ebb945a9	135	nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
e3c71eb2	136	return nvkm_gr_context_fini(&chan->base, suspend);
6ee73861 BS	137	}
6ee73861 BS	138
e3c71eb2	139	static struct nvkm_oclass
b8bf04e1	140	nv20_gr_cclass = {
ebb945a9	141	.handle = NV_ENGCTX(GR, 0x20),
e3c71eb2	142	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1	143	.ctor = nv20_gr_context_ctor,
e3c71eb2	144	.dtor = _nvkm_gr_context_dtor,
b8bf04e1 BS	145	.init = nv20_gr_context_init,
b8bf04e1 BS	146	.fini = nv20_gr_context_fini,
e3c71eb2 BS	147	.rd32 = _nvkm_gr_context_rd32,
e3c71eb2 BS	148	.wr32 = _nvkm_gr_context_wr32,
ebb945a9 BS	149	},
ebb945a9 BS	150	};
6ee73861	151
ebb945a9 BS	152	/*******************************************************************************
	153	* PGRAPH engine/subdev functions
	154	******************************************************************************/
6ee73861 BS	155
6ee73861 BS	156	void
e3c71eb2	157	nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
6ee73861	158	{
e3c71eb2	159	struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
6189f1b0	160	struct nvkm_fifo *fifo = nvkm_fifo(engine);
b8bf04e1	161	struct nv20_gr_priv priv = (void )engine;
3945e475	162	unsigned long flags;
6ee73861	163
6189f1b0	164	fifo->pause(fifo, &flags);
b8bf04e1	165	nv04_gr_idle(priv);
3945e475	166
ebb945a9 BS	167	nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
	168	nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
	169	nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
3945e475	170
ebb945a9 BS	171	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
	172	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
	173	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
	174	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
	175	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
	176	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
3945e475	177
fafa0cb3	178	if (nv_device(engine)->chipset != 0x34) {
ebb945a9 BS	179	nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
	180	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
	181	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
	182	}
6ee73861	183
6189f1b0	184	fifo->start(fifo, &flags);
6ee73861 BS	185	}
6ee73861 BS	186
ebb945a9	187	void
e3c71eb2	188	nv20_gr_intr(struct nvkm_subdev *subdev)
0d87c100	189	{
e3c71eb2 BS	190	struct nvkm_engine *engine = nv_engine(subdev);
	191	struct nvkm_object *engctx;
	192	struct nvkm_handle *handle;
b8bf04e1	193	struct nv20_gr_priv priv = (void )subdev;
ebb945a9 BS	194	u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
	195	u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
	196	u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
	197	u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
	198	u32 chid = (addr & 0x01f00000) >> 20;
	199	u32 subc = (addr & 0x00070000) >> 16;
	200	u32 mthd = (addr & 0x00001ffc);
	201	u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
	202	u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
ebb945a9 BS	203	u32 show = stat;
ebb945a9 BS	204
e3c71eb2	205	engctx = nvkm_engctx_get(engine, chid);
ebb945a9 BS	206	if (stat & NV_PGRAPH_INTR_ERROR) {
ebb945a9 BS	207	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
e3c71eb2	208	handle = nvkm_handle_get_class(engctx, class);
ebb945a9 BS	209	if (handle && !nv_call(handle->object, mthd, data))
ebb945a9 BS	210	show &= ~NV_PGRAPH_INTR_ERROR;
e3c71eb2	211	nvkm_handle_put(handle);
ebb945a9	212	}
87a326a3	213	}
87a326a3	214
ebb945a9 BS	215	nv_wr32(priv, NV03_PGRAPH_INTR, stat);
	216	nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
	217
	218	if (show) {
950fbfab	219	nv_error(priv, "%s", "");
e3c71eb2	220	nvkm_bitfield_print(nv10_gr_intr_name, show);
f533da10	221	pr_cont(" nsource:");
e3c71eb2	222	nvkm_bitfield_print(nv04_gr_nsource, nsource);
f533da10	223	pr_cont(" nstatus:");
e3c71eb2	224	nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
f533da10	225	pr_cont("\n");
93260d3c MS	226	nv_error(priv,
93260d3c MS	227	"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
e3c71eb2	228	chid, nvkm_client_name(engctx), subc, class, mthd,
93260d3c	229	data);
6ee73861	230	}
72a14827	231
e3c71eb2	232	nvkm_engctx_put(engctx);
ebb945a9	233	}
6ee73861	234
ebb945a9	235	static int
e3c71eb2 BS	236	nv20_gr_ctor(struct nvkm_object parent, struct nvkm_object engine,
	237	struct nvkm_oclass oclass, void data, u32 size,
	238	struct nvkm_object **pobject)
ebb945a9	239	{
b8bf04e1	240	struct nv20_gr_priv *priv;
ebb945a9	241	int ret;
6ee73861	242
e3c71eb2	243	ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
ebb945a9 BS	244	*pobject = nv_object(priv);
	245	if (ret)
	246	return ret;
6ee73861	247
e3c71eb2 BS	248	ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
e3c71eb2 BS	249	NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
ebb945a9 BS	250	if (ret)
ebb945a9 BS	251	return ret;
6ee73861	252
ebb945a9	253	nv_subdev(priv)->unit = 0x00001000;
b8bf04e1 BS	254	nv_subdev(priv)->intr = nv20_gr_intr;
	255	nv_engine(priv)->cclass = &nv20_gr_cclass;
	256	nv_engine(priv)->sclass = nv20_gr_sclass;
	257	nv_engine(priv)->tile_prog = nv20_gr_tile_prog;
6ee73861 BS	258	return 0;
	259	}
	260
ebb945a9	261	void
e3c71eb2	262	nv20_gr_dtor(struct nvkm_object *object)
6ee73861	263	{
b8bf04e1	264	struct nv20_gr_priv priv = (void )object;
e3c71eb2 BS	265	nvkm_gpuobj_ref(NULL, &priv->ctxtab);
e3c71eb2 BS	266	nvkm_gr_destroy(&priv->base);
ebb945a9	267	}
6ee73861	268
ebb945a9	269	int
e3c71eb2	270	nv20_gr_init(struct nvkm_object *object)
ebb945a9	271	{
e3c71eb2	272	struct nvkm_engine *engine = nv_engine(object);
b8bf04e1	273	struct nv20_gr_priv priv = (void )engine;
b1e4553c	274	struct nvkm_fb *fb = nvkm_fb(object);
ebb945a9 BS	275	u32 tmp, vramsz;
ebb945a9 BS	276	int ret, i;
6ee73861	277
e3c71eb2	278	ret = nvkm_gr_init(&priv->base);
ebb945a9 BS	279	if (ret)
ebb945a9 BS	280	return ret;
6ee73861	281
ebb945a9	282	nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
6ee73861	283
ebb945a9 BS	284	if (nv_device(priv)->chipset == 0x20) {
	285	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
	286	for (i = 0; i < 15; i++)
	287	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
	288	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
	289	} else {
	290	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
	291	for (i = 0; i < 32; i++)
	292	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
	293	nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
6ee73861 BS	294	}
6ee73861 BS	295
ebb945a9 BS	296	nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
ebb945a9 BS	297	nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
6ee73861	298
ebb945a9 BS	299	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	300	nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
	301	nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
	302	nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
	303	nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
	304	nv_wr32(priv, 0x40009C , 0x00000040);
274fec93	305
ebb945a9 BS	306	if (nv_device(priv)->chipset >= 0x25) {
	307	nv_wr32(priv, 0x400890, 0x00a8cfff);
	308	nv_wr32(priv, 0x400610, 0x304B1FB6);
	309	nv_wr32(priv, 0x400B80, 0x1cbd3883);
	310	nv_wr32(priv, 0x400B84, 0x44000000);
	311	nv_wr32(priv, 0x400098, 0x40000080);
	312	nv_wr32(priv, 0x400B88, 0x000000ff);
274fec93	313
ebb945a9 BS	314	} else {
	315	nv_wr32(priv, 0x400880, 0x0008c7df);
	316	nv_wr32(priv, 0x400094, 0x00000005);
	317	nv_wr32(priv, 0x400B80, 0x45eae20e);
	318	nv_wr32(priv, 0x400B84, 0x24000000);
	319	nv_wr32(priv, 0x400098, 0x00000040);
	320	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
	321	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
	322	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
	323	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
274fec93	324	}
a0b1de84	325
ebb945a9	326	/* Turn all the tiling regions off. */
b1e4553c	327	for (i = 0; i < fb->tile.regions; i++)
ebb945a9	328	engine->tile_prog(engine, i);
a0b1de84	329
ebb945a9 BS	330	nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
	331	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
	332	nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
a0b1de84	333
ebb945a9 BS	334	nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
ebb945a9 BS	335	nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
a0b1de84	336
ebb945a9 BS	337	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
	338	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
	339	tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) \| 0x00020100;
	340	nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
a0b1de84	341
ebb945a9	342	/* begin RAM config */
420b9469	343	vramsz = nv_device_resource_len(nv_device(priv), 0) - 1;
ebb945a9 BS	344	nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
	345	nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
	346	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
	347	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
	348	nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
	349	nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
	350	nv_wr32(priv, 0x400820, 0);
	351	nv_wr32(priv, 0x400824, 0);
	352	nv_wr32(priv, 0x400864, vramsz - 1);
	353	nv_wr32(priv, 0x400868, vramsz - 1);
a0b1de84	354
ebb945a9 BS	355	/* interesting.. the below overwrites some of the tile setup above.. */
	356	nv_wr32(priv, 0x400B20, 0x00000000);
	357	nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
a0b1de84	358
ebb945a9 BS	359	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
	360	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
	361	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
	362	nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
a0b1de84 BS	363	return 0;
a0b1de84 BS	364	}
ebb945a9	365
e3c71eb2	366	struct nvkm_oclass
b8bf04e1	367	nv20_gr_oclass = {
ebb945a9	368	.handle = NV_ENGINE(GR, 0x20),
e3c71eb2	369	.ofuncs = &(struct nvkm_ofuncs) {
b8bf04e1 BS	370	.ctor = nv20_gr_ctor,
	371	.dtor = nv20_gr_dtor,
	372	.init = nv20_gr_init,
e3c71eb2	373	.fini = _nvkm_gr_fini,
ebb945a9 BS	374	},
ebb945a9 BS	375	};