[linux-block.git] / drivers / gpu / drm / nouveau / nvkm / engine / gr / gf117.c

/*
 * Copyright 2013 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs <bskeggs@redhat.com>
 */
#include "gf100.h"
#include "ctxgf100.h"

#include <nvif/class.h>

/*******************************************************************************
 * PGRAPH register lists
 ******************************************************************************/

static const struct gf100_gr_init
gf117_gr_init_pe_0[] = {
	{ 0x41980c,   1, 0x04, 0x00000010 },
	{ 0x419844,   1, 0x04, 0x00000000 },
	{ 0x41984c,   1, 0x04, 0x00005bc8 },
	{ 0x419850,   3, 0x04, 0x00000000 },
	{}
};

const struct gf100_gr_init
gf117_gr_init_pes_0[] = {
	{ 0x41be04,   1, 0x04, 0x00000000 },
	{ 0x41be08,   1, 0x04, 0x00000004 },
	{ 0x41be0c,   1, 0x04, 0x00000000 },
	{ 0x41be10,   1, 0x04, 0x003b8bc7 },
	{ 0x41be14,   2, 0x04, 0x00000000 },
	{}
};

const struct gf100_gr_init
gf117_gr_init_wwdx_0[] = {
	{ 0x41bfd4,   1, 0x04, 0x00800000 },
	{ 0x41bfdc,   1, 0x04, 0x00000000 },
	{ 0x41bff8,   2, 0x04, 0x00000000 },
	{}
};

const struct gf100_gr_init
gf117_gr_init_cbm_0[] = {
	{ 0x41becc,   1, 0x04, 0x00000000 },
	{ 0x41bee8,   2, 0x04, 0x00000000 },
	{}
};

static const struct gf100_gr_pack
gf117_gr_pack_mmio[] = {
	{ gf100_gr_init_main_0 },
	{ gf100_gr_init_fe_0 },
	{ gf100_gr_init_pri_0 },
	{ gf100_gr_init_rstr2d_0 },
	{ gf119_gr_init_pd_0 },
	{ gf119_gr_init_ds_0 },
	{ gf100_gr_init_scc_0 },
	{ gf119_gr_init_prop_0 },
	{ gf108_gr_init_gpc_unk_0 },
	{ gf100_gr_init_setup_0 },
	{ gf100_gr_init_crstr_0 },
	{ gf108_gr_init_setup_1 },
	{ gf100_gr_init_zcull_0 },
	{ gf119_gr_init_gpm_0 },
	{ gf119_gr_init_gpc_unk_1 },
	{ gf100_gr_init_gcc_0 },
	{ gf100_gr_init_tpccs_0 },
	{ gf119_gr_init_tex_0 },
	{ gf117_gr_init_pe_0 },
	{ gf100_gr_init_l1c_0 },
	{ gf100_gr_init_mpc_0 },
	{ gf119_gr_init_sm_0 },
	{ gf117_gr_init_pes_0 },
	{ gf117_gr_init_wwdx_0 },
	{ gf117_gr_init_cbm_0 },
	{ gf100_gr_init_be_0 },
	{ gf119_gr_init_fe_1 },
	{}
};

/*******************************************************************************
 * PGRAPH engine/subdev functions
 ******************************************************************************/

#include "fuc/hubgf117.fuc3.h"

static struct gf100_gr_ucode
gf117_gr_fecs_ucode = {
	.code.data = gf117_grhub_code,
	.code.size = sizeof(gf117_grhub_code),
	.data.data = gf117_grhub_data,
	.data.size = sizeof(gf117_grhub_data),
};

#include "fuc/gpcgf117.fuc3.h"

static struct gf100_gr_ucode
gf117_gr_gpccs_ucode = {
	.code.data = gf117_grgpc_code,
	.code.size = sizeof(gf117_grgpc_code),
	.data.data = gf117_grgpc_data,
	.data.size = sizeof(gf117_grgpc_data),
};

void
gf117_gr_init_zcull(struct gf100_gr *gr)
{
	struct nvkm_device *device = gr->base.engine.subdev.device;
	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
	/*TODO: fill in litter vals for gf117-gm2xx */
	const u8 tile_nr = !gr->func->gpc_nr ? ALIGN(gr->tpc_total, 32) :
			   (gr->func->gpc_nr * gr->func->tpc_nr);
	u8 bank[GPC_MAX] = {}, gpc, i, j;
	u32 data;

	for (i = 0; i < tile_nr; i += 8) {
		for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
			data |= bank[gr->tile[i + j]] << (j * 4);
			bank[gr->tile[i + j]]++;
		}
		nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
	}

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
			  gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
							 gr->tpc_total);
		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
	}

	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
}

static const struct gf100_gr_func
gf117_gr = {
	.oneinit_tiles = gf100_gr_oneinit_tiles,
	.oneinit_sm_id = gf100_gr_oneinit_sm_id,
	.init = gf100_gr_init,
	.init_gpc_mmu = gf100_gr_init_gpc_mmu,
	.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
	.init_zcull = gf117_gr_init_zcull,
	.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
	.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
	.init_40601c = gf100_gr_init_40601c,
	.init_419cc0 = gf100_gr_init_419cc0,
	.init_419eb4 = gf100_gr_init_419eb4,
	.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
	.init_shader_exceptions = gf100_gr_init_shader_exceptions,
	.init_rop_exceptions = gf100_gr_init_rop_exceptions,
	.init_exception2 = gf100_gr_init_exception2,
	.init_400054 = gf100_gr_init_400054,
	.trap_mp = gf100_gr_trap_mp,
	.mmio = gf117_gr_pack_mmio,
	.fecs.ucode = &gf117_gr_fecs_ucode,
	.fecs.reset = gf100_gr_fecs_reset,
	.gpccs.ucode = &gf117_gr_gpccs_ucode,
	.rops = gf100_gr_rops,
	.ppc_nr = 1,
	.grctx = &gf117_grctx,
	.zbc = &gf100_gr_zbc,
	.sclass = {
		{ -1, -1, FERMI_TWOD_A },
		{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
		{ -1, -1, FERMI_A, &gf100_fermi },
		{ -1, -1, FERMI_B, &gf100_fermi },
		{ -1, -1, FERMI_C, &gf100_fermi },
		{ -1, -1, FERMI_COMPUTE_A },
		{ -1, -1, FERMI_COMPUTE_B },
		{}
	}
};

static const struct gf100_gr_fwif
gf117_gr_fwif[] = {
	{ -1, gf100_gr_load, &gf117_gr },
	{ -1, gf100_gr_nofw, &gf117_gr },
	{}
};

int
gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
	return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr);
}
Commit	Line	Data
26410c67 ML	1	/*
	2	* Copyright 2013 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs <bskeggs@redhat.com>
	23	*/
e3c71eb2 BS	24	#include "gf100.h"
e3c71eb2 BS	25	#include "ctxgf100.h"
26410c67	26
27f3d6cf BS	27	#include <nvif/class.h>
27f3d6cf BS	28
26410c67	29	/*******************************************************************************
c33b1e8c	30	* PGRAPH register lists
26410c67 ML	31	******************************************************************************/
26410c67 ML	32
e3c71eb2 BS	33	static const struct gf100_gr_init
e3c71eb2 BS	34	gf117_gr_init_pe_0[] = {
26410c67 ML	35	{ 0x41980c, 1, 0x04, 0x00000010 },
	36	{ 0x419844, 1, 0x04, 0x00000000 },
	37	{ 0x41984c, 1, 0x04, 0x00005bc8 },
c33b1e8c	38	{ 0x419850, 3, 0x04, 0x00000000 },
26410c67 ML	39	{}
	40	};
	41
e3c71eb2 BS	42	const struct gf100_gr_init
e3c71eb2 BS	43	gf117_gr_init_pes_0[] = {
c33b1e8c BS	44	{ 0x41be04, 1, 0x04, 0x00000000 },
	45	{ 0x41be08, 1, 0x04, 0x00000004 },
	46	{ 0x41be0c, 1, 0x04, 0x00000000 },
	47	{ 0x41be10, 1, 0x04, 0x003b8bc7 },
	48	{ 0x41be14, 2, 0x04, 0x00000000 },
88e98d49 BS	49	{}
	50	};
	51
e3c71eb2 BS	52	const struct gf100_gr_init
e3c71eb2 BS	53	gf117_gr_init_wwdx_0[] = {
c33b1e8c BS	54	{ 0x41bfd4, 1, 0x04, 0x00800000 },
	55	{ 0x41bfdc, 1, 0x04, 0x00000000 },
	56	{ 0x41bff8, 2, 0x04, 0x00000000 },
88e98d49 BS	57	{}
	58	};
	59
e3c71eb2 BS	60	const struct gf100_gr_init
e3c71eb2 BS	61	gf117_gr_init_cbm_0[] = {
c33b1e8c BS	62	{ 0x41becc, 1, 0x04, 0x00000000 },
c33b1e8c BS	63	{ 0x41bee8, 2, 0x04, 0x00000000 },
26410c67 ML	64	{}
	65	};
	66
e3c71eb2 BS	67	static const struct gf100_gr_pack
	68	gf117_gr_pack_mmio[] = {
	69	{ gf100_gr_init_main_0 },
	70	{ gf100_gr_init_fe_0 },
	71	{ gf100_gr_init_pri_0 },
	72	{ gf100_gr_init_rstr2d_0 },
	73	{ gf119_gr_init_pd_0 },
	74	{ gf119_gr_init_ds_0 },
	75	{ gf100_gr_init_scc_0 },
	76	{ gf119_gr_init_prop_0 },
	77	{ gf108_gr_init_gpc_unk_0 },
	78	{ gf100_gr_init_setup_0 },
	79	{ gf100_gr_init_crstr_0 },
	80	{ gf108_gr_init_setup_1 },
	81	{ gf100_gr_init_zcull_0 },
	82	{ gf119_gr_init_gpm_0 },
	83	{ gf119_gr_init_gpc_unk_1 },
	84	{ gf100_gr_init_gcc_0 },
	85	{ gf100_gr_init_tpccs_0 },
	86	{ gf119_gr_init_tex_0 },
	87	{ gf117_gr_init_pe_0 },
	88	{ gf100_gr_init_l1c_0 },
	89	{ gf100_gr_init_mpc_0 },
	90	{ gf119_gr_init_sm_0 },
	91	{ gf117_gr_init_pes_0 },
	92	{ gf117_gr_init_wwdx_0 },
	93	{ gf117_gr_init_cbm_0 },
	94	{ gf100_gr_init_be_0 },
	95	{ gf119_gr_init_fe_1 },
c33b1e8c BS	96	{}
	97	};
	98
	99	/*******************************************************************************
	100	* PGRAPH engine/subdev functions
	101	******************************************************************************/
	102
e3c71eb2	103	#include "fuc/hubgf117.fuc3.h"
c33b1e8c	104
f3a8b664	105	static struct gf100_gr_ucode
e3c71eb2 BS	106	gf117_gr_fecs_ucode = {
	107	.code.data = gf117_grhub_code,
	108	.code.size = sizeof(gf117_grhub_code),
	109	.data.data = gf117_grhub_data,
	110	.data.size = sizeof(gf117_grhub_data),
c33b1e8c BS	111	};
c33b1e8c BS	112
e3c71eb2	113	#include "fuc/gpcgf117.fuc3.h"
c33b1e8c	114
f3a8b664	115	static struct gf100_gr_ucode
e3c71eb2 BS	116	gf117_gr_gpccs_ucode = {
	117	.code.data = gf117_grgpc_code,
	118	.code.size = sizeof(gf117_grgpc_code),
	119	.data.data = gf117_grgpc_data,
	120	.data.size = sizeof(gf117_grgpc_data),
26410c67 ML	121	};
26410c67 ML	122
02917aa3 BS	123	void
	124	gf117_gr_init_zcull(struct gf100_gr *gr)
	125	{
	126	struct nvkm_device *device = gr->base.engine.subdev.device;
	127	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
e2eeec75 BS	128	/TODO: fill in litter vals for gf117-gm2xx /
	129	const u8 tile_nr = !gr->func->gpc_nr ? ALIGN(gr->tpc_total, 32) :
	130	(gr->func->gpc_nr * gr->func->tpc_nr);
d00ffc0c BS	131	u8 bank[GPC_MAX] = {}, gpc, i, j;
	132	u32 data;
	133
	134	for (i = 0; i < tile_nr; i += 8) {
	135	for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
	136	data \|= bank[gr->tile[i + j]] << (j * 4);
	137	bank[gr->tile[i + j]]++;
	138	}
	139	nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
02917aa3 BS	140	}
02917aa3 BS	141
d00ffc0c BS	142	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
	143	nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
	144	gr->screen_tile_row_offset << 8 \| gr->tpc_nr[gpc]);
	145	nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 \|
	146	gr->tpc_total);
	147	nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
	148	}
02917aa3 BS	149
	150	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);
	151	}
	152
27f3d6cf BS	153	static const struct gf100_gr_func
27f3d6cf BS	154	gf117_gr = {
5f6474a4	155	.oneinit_tiles = gf100_gr_oneinit_tiles,
068cae74	156	.oneinit_sm_id = gf100_gr_oneinit_sm_id,
c85ee6ca	157	.init = gf100_gr_init,
223eaf4b	158	.init_gpc_mmu = gf100_gr_init_gpc_mmu,
2fe5ff63	159	.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
02917aa3	160	.init_zcull = gf117_gr_init_zcull,
bfd27f39	161	.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
2585a1b1	162	.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
2b297b0d	163	.init_40601c = gf100_gr_init_40601c,
0feab025	164	.init_419cc0 = gf100_gr_init_419cc0,
0a84a513	165	.init_419eb4 = gf100_gr_init_419eb4,
f3ef80c0	166	.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
4615e9b4	167	.init_shader_exceptions = gf100_gr_init_shader_exceptions,
b6d93fa7	168	.init_rop_exceptions = gf100_gr_init_rop_exceptions,
1a344688	169	.init_exception2 = gf100_gr_init_exception2,
04547482	170	.init_400054 = gf100_gr_init_400054,
5c05a589	171	.trap_mp = gf100_gr_trap_mp,
c85ee6ca BS	172	.mmio = gf117_gr_pack_mmio,
c85ee6ca BS	173	.fecs.ucode = &gf117_gr_fecs_ucode,
be99d041	174	.fecs.reset = gf100_gr_fecs_reset,
c85ee6ca	175	.gpccs.ucode = &gf117_gr_gpccs_ucode,
64cb5a31	176	.rops = gf100_gr_rops,
c85ee6ca	177	.ppc_nr = 1,
27f3d6cf	178	.grctx = &gf117_grctx,
e9d03335	179	.zbc = &gf100_gr_zbc,
27f3d6cf BS	180	.sclass = {
	181	{ -1, -1, FERMI_TWOD_A },
	182	{ -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
	183	{ -1, -1, FERMI_A, &gf100_fermi },
	184	{ -1, -1, FERMI_B, &gf100_fermi },
	185	{ -1, -1, FERMI_C, &gf100_fermi },
	186	{ -1, -1, FERMI_COMPUTE_A },
2e69a5cd	187	{ -1, -1, FERMI_COMPUTE_B },
27f3d6cf BS	188	{}
	189	}
	190	};
	191
ef16dc27 BS	192	static const struct gf100_gr_fwif
	193	gf117_gr_fwif[] = {
	194	{ -1, gf100_gr_load, &gf117_gr },
	195	{ -1, gf100_gr_nofw, &gf117_gr },
	196	{}
	197	};
	198
c85ee6ca	199	int
864d37c3	200	gf117_gr_new(struct nvkm_device device, enum nvkm_subdev_type type, int inst, struct nvkm_gr *pgr)
c85ee6ca	201	{
864d37c3	202	return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr);
c85ee6ca	203	}