Commit | Line | Data |
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4b223eef | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
4b223eef BS |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
e3c71eb2 BS |
24 | #include "gf100.h" |
25 | #include "ctxgf100.h" | |
26 | #include "fuc/os.h" | |
27 | ||
28 | #include <core/client.h> | |
e3c71eb2 | 29 | #include <core/option.h> |
33bcb4c3 | 30 | #include <core/firmware.h> |
c9469aae | 31 | #include <subdev/secboot.h> |
e3c71eb2 BS |
32 | #include <subdev/fb.h> |
33 | #include <subdev/mc.h> | |
c85ee6ca | 34 | #include <subdev/pmu.h> |
e3c71eb2 | 35 | #include <subdev/timer.h> |
a65955e1 | 36 | #include <engine/fifo.h> |
e3c71eb2 BS |
37 | |
38 | #include <nvif/class.h> | |
53a6df77 | 39 | #include <nvif/cl9097.h> |
e3c71eb2 | 40 | #include <nvif/unpack.h> |
0411de85 | 41 | |
ac9738bb BS |
42 | /******************************************************************************* |
43 | * Zero Bandwidth Clear | |
44 | ******************************************************************************/ | |
45 | ||
46 | static void | |
bfee3f3d | 47 | gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) |
ac9738bb | 48 | { |
276836d4 | 49 | struct nvkm_device *device = gr->base.engine.subdev.device; |
bfee3f3d | 50 | if (gr->zbc_color[zbc].format) { |
276836d4 BS |
51 | nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); |
52 | nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); | |
53 | nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); | |
54 | nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); | |
55 | } | |
56 | nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); | |
57 | nvkm_wr32(device, 0x405820, zbc); | |
58 | nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ | |
ac9738bb BS |
59 | } |
60 | ||
61 | static int | |
bfee3f3d | 62 | gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, |
e3c71eb2 | 63 | const u32 ds[4], const u32 l2[4]) |
ac9738bb | 64 | { |
70bc7182 | 65 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
ac9738bb BS |
66 | int zbc = -ENOSPC, i; |
67 | ||
68 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { | |
bfee3f3d BS |
69 | if (gr->zbc_color[i].format) { |
70 | if (gr->zbc_color[i].format != format) | |
ac9738bb | 71 | continue; |
bfee3f3d BS |
72 | if (memcmp(gr->zbc_color[i].ds, ds, sizeof( |
73 | gr->zbc_color[i].ds))) | |
ac9738bb | 74 | continue; |
bfee3f3d BS |
75 | if (memcmp(gr->zbc_color[i].l2, l2, sizeof( |
76 | gr->zbc_color[i].l2))) { | |
ac9738bb BS |
77 | WARN_ON(1); |
78 | return -EINVAL; | |
79 | } | |
80 | return i; | |
81 | } else { | |
82 | zbc = (zbc < 0) ? i : zbc; | |
83 | } | |
84 | } | |
85 | ||
da7c74ea BS |
86 | if (zbc < 0) |
87 | return zbc; | |
88 | ||
bfee3f3d BS |
89 | memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); |
90 | memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); | |
91 | gr->zbc_color[zbc].format = format; | |
70bc7182 | 92 | nvkm_ltc_zbc_color_get(ltc, zbc, l2); |
bfee3f3d | 93 | gf100_gr_zbc_clear_color(gr, zbc); |
ac9738bb BS |
94 | return zbc; |
95 | } | |
96 | ||
97 | static void | |
bfee3f3d | 98 | gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) |
ac9738bb | 99 | { |
276836d4 | 100 | struct nvkm_device *device = gr->base.engine.subdev.device; |
bfee3f3d | 101 | if (gr->zbc_depth[zbc].format) |
276836d4 BS |
102 | nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); |
103 | nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); | |
104 | nvkm_wr32(device, 0x405820, zbc); | |
105 | nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ | |
ac9738bb BS |
106 | } |
107 | ||
108 | static int | |
bfee3f3d | 109 | gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, |
e3c71eb2 | 110 | const u32 ds, const u32 l2) |
ac9738bb | 111 | { |
70bc7182 | 112 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
ac9738bb BS |
113 | int zbc = -ENOSPC, i; |
114 | ||
115 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { | |
bfee3f3d BS |
116 | if (gr->zbc_depth[i].format) { |
117 | if (gr->zbc_depth[i].format != format) | |
ac9738bb | 118 | continue; |
bfee3f3d | 119 | if (gr->zbc_depth[i].ds != ds) |
ac9738bb | 120 | continue; |
bfee3f3d | 121 | if (gr->zbc_depth[i].l2 != l2) { |
ac9738bb BS |
122 | WARN_ON(1); |
123 | return -EINVAL; | |
124 | } | |
125 | return i; | |
126 | } else { | |
127 | zbc = (zbc < 0) ? i : zbc; | |
128 | } | |
129 | } | |
130 | ||
da7c74ea BS |
131 | if (zbc < 0) |
132 | return zbc; | |
133 | ||
bfee3f3d BS |
134 | gr->zbc_depth[zbc].format = format; |
135 | gr->zbc_depth[zbc].ds = ds; | |
136 | gr->zbc_depth[zbc].l2 = l2; | |
70bc7182 | 137 | nvkm_ltc_zbc_depth_get(ltc, zbc, l2); |
bfee3f3d | 138 | gf100_gr_zbc_clear_depth(gr, zbc); |
ac9738bb BS |
139 | return zbc; |
140 | } | |
141 | ||
ebb945a9 BS |
142 | /******************************************************************************* |
143 | * Graphics object classes | |
144 | ******************************************************************************/ | |
5bf561ee BS |
145 | #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object) |
146 | ||
147 | struct gf100_gr_object { | |
148 | struct nvkm_object object; | |
149 | struct gf100_gr_chan *chan; | |
150 | }; | |
ebb945a9 | 151 | |
ac9738bb | 152 | static int |
e3c71eb2 | 153 | gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) |
ac9738bb | 154 | { |
0d7fc246 | 155 | struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); |
ac9738bb BS |
156 | union { |
157 | struct fermi_a_zbc_color_v0 v0; | |
158 | } *args = data; | |
f01c4e68 | 159 | int ret = -ENOSYS; |
ac9738bb | 160 | |
f01c4e68 | 161 | if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { |
ac9738bb BS |
162 | switch (args->v0.format) { |
163 | case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: | |
164 | case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: | |
165 | case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: | |
166 | case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: | |
167 | case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: | |
168 | case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: | |
169 | case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: | |
170 | case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: | |
171 | case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: | |
172 | case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: | |
173 | case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: | |
174 | case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: | |
175 | case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: | |
176 | case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: | |
177 | case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: | |
178 | case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: | |
179 | case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: | |
180 | case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: | |
181 | case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: | |
bfee3f3d | 182 | ret = gf100_gr_zbc_color_get(gr, args->v0.format, |
e3c71eb2 BS |
183 | args->v0.ds, |
184 | args->v0.l2); | |
ac9738bb BS |
185 | if (ret >= 0) { |
186 | args->v0.index = ret; | |
187 | return 0; | |
188 | } | |
189 | break; | |
190 | default: | |
191 | return -EINVAL; | |
192 | } | |
193 | } | |
194 | ||
195 | return ret; | |
196 | } | |
197 | ||
198 | static int | |
e3c71eb2 | 199 | gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) |
ac9738bb | 200 | { |
0d7fc246 | 201 | struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); |
ac9738bb BS |
202 | union { |
203 | struct fermi_a_zbc_depth_v0 v0; | |
204 | } *args = data; | |
f01c4e68 | 205 | int ret = -ENOSYS; |
ac9738bb | 206 | |
f01c4e68 | 207 | if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { |
ac9738bb BS |
208 | switch (args->v0.format) { |
209 | case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: | |
bfee3f3d | 210 | ret = gf100_gr_zbc_depth_get(gr, args->v0.format, |
e3c71eb2 BS |
211 | args->v0.ds, |
212 | args->v0.l2); | |
ac9738bb BS |
213 | return (ret >= 0) ? 0 : -ENOSPC; |
214 | default: | |
215 | return -EINVAL; | |
216 | } | |
217 | } | |
218 | ||
219 | return ret; | |
220 | } | |
221 | ||
222 | static int | |
e3c71eb2 | 223 | gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) |
ac9738bb | 224 | { |
f01c4e68 | 225 | nvif_ioctl(object, "fermi mthd %08x\n", mthd); |
ac9738bb BS |
226 | switch (mthd) { |
227 | case FERMI_A_ZBC_COLOR: | |
e3c71eb2 | 228 | return gf100_fermi_mthd_zbc_color(object, data, size); |
ac9738bb | 229 | case FERMI_A_ZBC_DEPTH: |
e3c71eb2 | 230 | return gf100_fermi_mthd_zbc_depth(object, data, size); |
ac9738bb BS |
231 | default: |
232 | break; | |
233 | } | |
234 | return -EINVAL; | |
235 | } | |
236 | ||
27f3d6cf BS |
237 | const struct nvkm_object_func |
238 | gf100_fermi = { | |
e3c71eb2 | 239 | .mthd = gf100_fermi_mthd, |
ac9738bb BS |
240 | }; |
241 | ||
a65955e1 BS |
242 | static void |
243 | gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) | |
d6bd3803 | 244 | { |
a65955e1 BS |
245 | nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); |
246 | nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); | |
d6bd3803 BS |
247 | } |
248 | ||
a65955e1 BS |
249 | static bool |
250 | gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) | |
251 | { | |
252 | switch (class & 0x00ff) { | |
253 | case 0x97: | |
254 | case 0xc0: | |
255 | switch (mthd) { | |
256 | case 0x1528: | |
257 | gf100_gr_mthd_set_shader_exceptions(device, data); | |
258 | return true; | |
259 | default: | |
260 | break; | |
261 | } | |
262 | break; | |
263 | default: | |
264 | break; | |
265 | } | |
266 | return false; | |
267 | } | |
d6bd3803 | 268 | |
5bf561ee BS |
269 | static const struct nvkm_object_func |
270 | gf100_gr_object_func = { | |
271 | }; | |
272 | ||
273 | static int | |
274 | gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, | |
275 | struct nvkm_object **pobject) | |
276 | { | |
277 | struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent); | |
278 | struct gf100_gr_object *object; | |
279 | ||
280 | if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) | |
281 | return -ENOMEM; | |
282 | *pobject = &object->object; | |
283 | ||
284 | nvkm_object_ctor(oclass->base.func ? oclass->base.func : | |
285 | &gf100_gr_object_func, oclass, &object->object); | |
286 | object->chan = chan; | |
287 | return 0; | |
288 | } | |
289 | ||
27f3d6cf BS |
290 | static int |
291 | gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) | |
292 | { | |
293 | struct gf100_gr *gr = gf100_gr(base); | |
294 | int c = 0; | |
295 | ||
296 | while (gr->func->sclass[c].oclass) { | |
297 | if (c++ == index) { | |
298 | *sclass = gr->func->sclass[index]; | |
5bf561ee | 299 | sclass->ctor = gf100_gr_object_new; |
27f3d6cf BS |
300 | return index; |
301 | } | |
302 | } | |
303 | ||
304 | return c; | |
305 | } | |
ebb945a9 | 306 | |
ebb945a9 BS |
307 | /******************************************************************************* |
308 | * PGRAPH context | |
309 | ******************************************************************************/ | |
966a5b7d | 310 | |
27f3d6cf BS |
311 | static int |
312 | gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, | |
313 | int align, struct nvkm_gpuobj **pgpuobj) | |
966a5b7d | 314 | { |
27f3d6cf BS |
315 | struct gf100_gr_chan *chan = gf100_gr_chan(object); |
316 | struct gf100_gr *gr = chan->gr; | |
317 | int ret, i; | |
318 | ||
319 | ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, | |
320 | align, false, parent, pgpuobj); | |
321 | if (ret) | |
322 | return ret; | |
323 | ||
324 | nvkm_kmap(*pgpuobj); | |
325 | for (i = 0; i < gr->size; i += 4) | |
326 | nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); | |
327 | ||
328 | if (!gr->firmware) { | |
329 | nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); | |
330 | nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); | |
331 | } else { | |
332 | nvkm_wo32(*pgpuobj, 0xf4, 0); | |
333 | nvkm_wo32(*pgpuobj, 0xf8, 0); | |
334 | nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); | |
335 | nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); | |
336 | nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); | |
337 | nvkm_wo32(*pgpuobj, 0x1c, 1); | |
338 | nvkm_wo32(*pgpuobj, 0x20, 0); | |
339 | nvkm_wo32(*pgpuobj, 0x28, 0); | |
340 | nvkm_wo32(*pgpuobj, 0x2c, 0); | |
341 | } | |
342 | nvkm_done(*pgpuobj); | |
343 | return 0; | |
344 | } | |
345 | ||
346 | static void * | |
347 | gf100_gr_chan_dtor(struct nvkm_object *object) | |
348 | { | |
349 | struct gf100_gr_chan *chan = gf100_gr_chan(object); | |
350 | int i; | |
351 | ||
352 | for (i = 0; i < ARRAY_SIZE(chan->data); i++) { | |
353 | if (chan->data[i].vma.node) { | |
354 | nvkm_vm_unmap(&chan->data[i].vma); | |
355 | nvkm_vm_put(&chan->data[i].vma); | |
356 | } | |
357 | nvkm_memory_del(&chan->data[i].mem); | |
358 | } | |
359 | ||
360 | if (chan->mmio_vma.node) { | |
361 | nvkm_vm_unmap(&chan->mmio_vma); | |
362 | nvkm_vm_put(&chan->mmio_vma); | |
363 | } | |
364 | nvkm_memory_del(&chan->mmio); | |
365 | return chan; | |
366 | } | |
367 | ||
368 | static const struct nvkm_object_func | |
369 | gf100_gr_chan = { | |
370 | .dtor = gf100_gr_chan_dtor, | |
371 | .bind = gf100_gr_chan_bind, | |
372 | }; | |
373 | ||
374 | static int | |
375 | gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, | |
376 | const struct nvkm_oclass *oclass, | |
377 | struct nvkm_object **pobject) | |
378 | { | |
379 | struct gf100_gr *gr = gf100_gr(base); | |
bfee3f3d BS |
380 | struct gf100_gr_data *data = gr->mmio_data; |
381 | struct gf100_gr_mmio *mmio = gr->mmio_list; | |
e3c71eb2 | 382 | struct gf100_gr_chan *chan; |
227c95d9 | 383 | struct nvkm_device *device = gr->base.engine.subdev.device; |
966a5b7d | 384 | int ret, i; |
966a5b7d | 385 | |
27f3d6cf BS |
386 | if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) |
387 | return -ENOMEM; | |
388 | nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); | |
389 | chan->gr = gr; | |
390 | *pobject = &chan->object; | |
966a5b7d | 391 | |
ac1499d9 BS |
392 | /* allocate memory for a "mmio list" buffer that's used by the HUB |
393 | * fuc to modify some per-context register settings on first load | |
394 | * of the context. | |
395 | */ | |
227c95d9 BS |
396 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, |
397 | false, &chan->mmio); | |
73a60c0d BS |
398 | if (ret) |
399 | return ret; | |
400 | ||
27f3d6cf | 401 | ret = nvkm_vm_get(fifoch->vm, 0x1000, 12, NV_MEM_ACCESS_RW | |
227c95d9 | 402 | NV_MEM_ACCESS_SYS, &chan->mmio_vma); |
73a60c0d BS |
403 | if (ret) |
404 | return ret; | |
405 | ||
227c95d9 BS |
406 | nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); |
407 | ||
ac1499d9 | 408 | /* allocate buffers referenced by mmio list */ |
bfee3f3d | 409 | for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { |
227c95d9 BS |
410 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, |
411 | data->size, data->align, false, | |
412 | &chan->data[i].mem); | |
ac1499d9 BS |
413 | if (ret) |
414 | return ret; | |
73a60c0d | 415 | |
27f3d6cf BS |
416 | ret = nvkm_vm_get(fifoch->vm, |
417 | nvkm_memory_size(chan->data[i].mem), 12, | |
418 | data->access, &chan->data[i].vma); | |
ac1499d9 BS |
419 | if (ret) |
420 | return ret; | |
966a5b7d | 421 | |
227c95d9 | 422 | nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); |
ac1499d9 | 423 | data++; |
966a5b7d BS |
424 | } |
425 | ||
ac1499d9 | 426 | /* finally, fill in the mmio list and point the context at it */ |
142ea05f | 427 | nvkm_kmap(chan->mmio); |
bfee3f3d | 428 | for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { |
ac1499d9 BS |
429 | u32 addr = mmio->addr; |
430 | u32 data = mmio->data; | |
966a5b7d | 431 | |
694c6caf | 432 | if (mmio->buffer >= 0) { |
ebb945a9 | 433 | u64 info = chan->data[mmio->buffer].vma.offset; |
ac1499d9 BS |
434 | data |= info >> mmio->shift; |
435 | } | |
73a60c0d | 436 | |
142ea05f BS |
437 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); |
438 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); | |
ac1499d9 BS |
439 | mmio++; |
440 | } | |
142ea05f | 441 | nvkm_done(chan->mmio); |
ebb945a9 | 442 | return 0; |
4b223eef BS |
443 | } |
444 | ||
ebb945a9 | 445 | /******************************************************************************* |
c33b1e8c | 446 | * PGRAPH register lists |
ebb945a9 BS |
447 | ******************************************************************************/ |
448 | ||
e3c71eb2 BS |
449 | const struct gf100_gr_init |
450 | gf100_gr_init_main_0[] = { | |
30f4e087 BS |
451 | { 0x400080, 1, 0x04, 0x003083c2 }, |
452 | { 0x400088, 1, 0x04, 0x00006fe7 }, | |
453 | { 0x40008c, 1, 0x04, 0x00000000 }, | |
454 | { 0x400090, 1, 0x04, 0x00000030 }, | |
455 | { 0x40013c, 1, 0x04, 0x013901f7 }, | |
456 | { 0x400140, 1, 0x04, 0x00000100 }, | |
457 | { 0x400144, 1, 0x04, 0x00000000 }, | |
458 | { 0x400148, 1, 0x04, 0x00000110 }, | |
459 | { 0x400138, 1, 0x04, 0x00000000 }, | |
460 | { 0x400130, 2, 0x04, 0x00000000 }, | |
461 | { 0x400124, 1, 0x04, 0x00000002 }, | |
462 | {} | |
463 | }; | |
464 | ||
e3c71eb2 BS |
465 | const struct gf100_gr_init |
466 | gf100_gr_init_fe_0[] = { | |
30f4e087 BS |
467 | { 0x40415c, 1, 0x04, 0x00000000 }, |
468 | { 0x404170, 1, 0x04, 0x00000000 }, | |
469 | {} | |
470 | }; | |
471 | ||
e3c71eb2 BS |
472 | const struct gf100_gr_init |
473 | gf100_gr_init_pri_0[] = { | |
30f4e087 BS |
474 | { 0x404488, 2, 0x04, 0x00000000 }, |
475 | {} | |
476 | }; | |
477 | ||
e3c71eb2 BS |
478 | const struct gf100_gr_init |
479 | gf100_gr_init_rstr2d_0[] = { | |
30f4e087 BS |
480 | { 0x407808, 1, 0x04, 0x00000000 }, |
481 | {} | |
482 | }; | |
483 | ||
e3c71eb2 BS |
484 | const struct gf100_gr_init |
485 | gf100_gr_init_pd_0[] = { | |
30f4e087 BS |
486 | { 0x406024, 1, 0x04, 0x00000000 }, |
487 | {} | |
488 | }; | |
489 | ||
e3c71eb2 BS |
490 | const struct gf100_gr_init |
491 | gf100_gr_init_ds_0[] = { | |
30f4e087 BS |
492 | { 0x405844, 1, 0x04, 0x00ffffff }, |
493 | { 0x405850, 1, 0x04, 0x00000000 }, | |
494 | { 0x405908, 1, 0x04, 0x00000000 }, | |
495 | {} | |
496 | }; | |
497 | ||
e3c71eb2 BS |
498 | const struct gf100_gr_init |
499 | gf100_gr_init_scc_0[] = { | |
30f4e087 BS |
500 | { 0x40803c, 1, 0x04, 0x00000000 }, |
501 | {} | |
502 | }; | |
503 | ||
e3c71eb2 BS |
504 | const struct gf100_gr_init |
505 | gf100_gr_init_prop_0[] = { | |
30f4e087 | 506 | { 0x4184a0, 1, 0x04, 0x00000000 }, |
97af71fa BS |
507 | {} |
508 | }; | |
509 | ||
e3c71eb2 BS |
510 | const struct gf100_gr_init |
511 | gf100_gr_init_gpc_unk_0[] = { | |
30f4e087 BS |
512 | { 0x418604, 1, 0x04, 0x00000000 }, |
513 | { 0x418680, 1, 0x04, 0x00000000 }, | |
514 | { 0x418714, 1, 0x04, 0x80000000 }, | |
515 | { 0x418384, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
516 | {} |
517 | }; | |
518 | ||
e3c71eb2 BS |
519 | const struct gf100_gr_init |
520 | gf100_gr_init_setup_0[] = { | |
30f4e087 | 521 | { 0x418814, 3, 0x04, 0x00000000 }, |
97af71fa BS |
522 | {} |
523 | }; | |
524 | ||
e3c71eb2 BS |
525 | const struct gf100_gr_init |
526 | gf100_gr_init_crstr_0[] = { | |
30f4e087 | 527 | { 0x418b04, 1, 0x04, 0x00000000 }, |
97af71fa BS |
528 | {} |
529 | }; | |
530 | ||
e3c71eb2 BS |
531 | const struct gf100_gr_init |
532 | gf100_gr_init_setup_1[] = { | |
30f4e087 BS |
533 | { 0x4188c8, 1, 0x04, 0x80000000 }, |
534 | { 0x4188cc, 1, 0x04, 0x00000000 }, | |
535 | { 0x4188d0, 1, 0x04, 0x00010000 }, | |
536 | { 0x4188d4, 1, 0x04, 0x00000001 }, | |
97af71fa BS |
537 | {} |
538 | }; | |
539 | ||
e3c71eb2 BS |
540 | const struct gf100_gr_init |
541 | gf100_gr_init_zcull_0[] = { | |
30f4e087 BS |
542 | { 0x418910, 1, 0x04, 0x00010001 }, |
543 | { 0x418914, 1, 0x04, 0x00000301 }, | |
544 | { 0x418918, 1, 0x04, 0x00800000 }, | |
545 | { 0x418980, 1, 0x04, 0x77777770 }, | |
546 | { 0x418984, 3, 0x04, 0x77777777 }, | |
97af71fa BS |
547 | {} |
548 | }; | |
549 | ||
e3c71eb2 BS |
550 | const struct gf100_gr_init |
551 | gf100_gr_init_gpm_0[] = { | |
30f4e087 BS |
552 | { 0x418c04, 1, 0x04, 0x00000000 }, |
553 | { 0x418c88, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
554 | {} |
555 | }; | |
556 | ||
e3c71eb2 BS |
557 | const struct gf100_gr_init |
558 | gf100_gr_init_gpc_unk_1[] = { | |
30f4e087 BS |
559 | { 0x418d00, 1, 0x04, 0x00000000 }, |
560 | { 0x418f08, 1, 0x04, 0x00000000 }, | |
561 | { 0x418e00, 1, 0x04, 0x00000050 }, | |
562 | { 0x418e08, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
563 | {} |
564 | }; | |
565 | ||
e3c71eb2 BS |
566 | const struct gf100_gr_init |
567 | gf100_gr_init_gcc_0[] = { | |
30f4e087 BS |
568 | { 0x41900c, 1, 0x04, 0x00000000 }, |
569 | { 0x419018, 1, 0x04, 0x00000000 }, | |
570 | {} | |
571 | }; | |
572 | ||
e3c71eb2 BS |
573 | const struct gf100_gr_init |
574 | gf100_gr_init_tpccs_0[] = { | |
30f4e087 BS |
575 | { 0x419d08, 2, 0x04, 0x00000000 }, |
576 | { 0x419d10, 1, 0x04, 0x00000014 }, | |
7e194533 BS |
577 | {} |
578 | }; | |
579 | ||
e3c71eb2 BS |
580 | const struct gf100_gr_init |
581 | gf100_gr_init_tex_0[] = { | |
30f4e087 BS |
582 | { 0x419ab0, 1, 0x04, 0x00000000 }, |
583 | { 0x419ab8, 1, 0x04, 0x000000e7 }, | |
584 | { 0x419abc, 2, 0x04, 0x00000000 }, | |
7e194533 BS |
585 | {} |
586 | }; | |
587 | ||
e3c71eb2 BS |
588 | const struct gf100_gr_init |
589 | gf100_gr_init_pe_0[] = { | |
30f4e087 BS |
590 | { 0x41980c, 3, 0x04, 0x00000000 }, |
591 | { 0x419844, 1, 0x04, 0x00000000 }, | |
592 | { 0x41984c, 1, 0x04, 0x00005bc5 }, | |
593 | { 0x419850, 4, 0x04, 0x00000000 }, | |
7e194533 BS |
594 | {} |
595 | }; | |
596 | ||
e3c71eb2 BS |
597 | const struct gf100_gr_init |
598 | gf100_gr_init_l1c_0[] = { | |
30f4e087 BS |
599 | { 0x419c98, 1, 0x04, 0x00000000 }, |
600 | { 0x419ca8, 1, 0x04, 0x80000000 }, | |
601 | { 0x419cb4, 1, 0x04, 0x00000000 }, | |
602 | { 0x419cb8, 1, 0x04, 0x00008bf4 }, | |
603 | { 0x419cbc, 1, 0x04, 0x28137606 }, | |
604 | { 0x419cc0, 2, 0x04, 0x00000000 }, | |
7e194533 BS |
605 | {} |
606 | }; | |
607 | ||
e3c71eb2 BS |
608 | const struct gf100_gr_init |
609 | gf100_gr_init_wwdx_0[] = { | |
30f4e087 BS |
610 | { 0x419bd4, 1, 0x04, 0x00800000 }, |
611 | { 0x419bdc, 1, 0x04, 0x00000000 }, | |
7e194533 BS |
612 | {} |
613 | }; | |
614 | ||
e3c71eb2 BS |
615 | const struct gf100_gr_init |
616 | gf100_gr_init_tpccs_1[] = { | |
30f4e087 | 617 | { 0x419d2c, 1, 0x04, 0x00000000 }, |
7e194533 BS |
618 | {} |
619 | }; | |
620 | ||
e3c71eb2 BS |
621 | const struct gf100_gr_init |
622 | gf100_gr_init_mpc_0[] = { | |
30f4e087 | 623 | { 0x419c0c, 1, 0x04, 0x00000000 }, |
7e194533 BS |
624 | {} |
625 | }; | |
626 | ||
e3c71eb2 BS |
627 | static const struct gf100_gr_init |
628 | gf100_gr_init_sm_0[] = { | |
30f4e087 BS |
629 | { 0x419e00, 1, 0x04, 0x00000000 }, |
630 | { 0x419ea0, 1, 0x04, 0x00000000 }, | |
631 | { 0x419ea4, 1, 0x04, 0x00000100 }, | |
632 | { 0x419ea8, 1, 0x04, 0x00001100 }, | |
633 | { 0x419eac, 1, 0x04, 0x11100702 }, | |
634 | { 0x419eb0, 1, 0x04, 0x00000003 }, | |
635 | { 0x419eb4, 4, 0x04, 0x00000000 }, | |
636 | { 0x419ec8, 1, 0x04, 0x06060618 }, | |
637 | { 0x419ed0, 1, 0x04, 0x0eff0e38 }, | |
638 | { 0x419ed4, 1, 0x04, 0x011104f1 }, | |
639 | { 0x419edc, 1, 0x04, 0x00000000 }, | |
640 | { 0x419f00, 1, 0x04, 0x00000000 }, | |
641 | { 0x419f2c, 1, 0x04, 0x00000000 }, | |
642 | {} | |
643 | }; | |
644 | ||
e3c71eb2 BS |
645 | const struct gf100_gr_init |
646 | gf100_gr_init_be_0[] = { | |
30f4e087 BS |
647 | { 0x40880c, 1, 0x04, 0x00000000 }, |
648 | { 0x408910, 9, 0x04, 0x00000000 }, | |
649 | { 0x408950, 1, 0x04, 0x00000000 }, | |
650 | { 0x408954, 1, 0x04, 0x0000ffff }, | |
651 | { 0x408984, 1, 0x04, 0x00000000 }, | |
652 | { 0x408988, 1, 0x04, 0x08040201 }, | |
653 | { 0x40898c, 1, 0x04, 0x80402010 }, | |
654 | {} | |
655 | }; | |
656 | ||
e3c71eb2 BS |
657 | const struct gf100_gr_init |
658 | gf100_gr_init_fe_1[] = { | |
c33b1e8c BS |
659 | { 0x4040f0, 1, 0x04, 0x00000000 }, |
660 | {} | |
661 | }; | |
662 | ||
e3c71eb2 BS |
663 | const struct gf100_gr_init |
664 | gf100_gr_init_pe_1[] = { | |
c33b1e8c BS |
665 | { 0x419880, 1, 0x04, 0x00000002 }, |
666 | {} | |
667 | }; | |
668 | ||
e3c71eb2 BS |
669 | static const struct gf100_gr_pack |
670 | gf100_gr_pack_mmio[] = { | |
671 | { gf100_gr_init_main_0 }, | |
672 | { gf100_gr_init_fe_0 }, | |
673 | { gf100_gr_init_pri_0 }, | |
674 | { gf100_gr_init_rstr2d_0 }, | |
675 | { gf100_gr_init_pd_0 }, | |
676 | { gf100_gr_init_ds_0 }, | |
677 | { gf100_gr_init_scc_0 }, | |
678 | { gf100_gr_init_prop_0 }, | |
679 | { gf100_gr_init_gpc_unk_0 }, | |
680 | { gf100_gr_init_setup_0 }, | |
681 | { gf100_gr_init_crstr_0 }, | |
682 | { gf100_gr_init_setup_1 }, | |
683 | { gf100_gr_init_zcull_0 }, | |
684 | { gf100_gr_init_gpm_0 }, | |
685 | { gf100_gr_init_gpc_unk_1 }, | |
686 | { gf100_gr_init_gcc_0 }, | |
687 | { gf100_gr_init_tpccs_0 }, | |
688 | { gf100_gr_init_tex_0 }, | |
689 | { gf100_gr_init_pe_0 }, | |
690 | { gf100_gr_init_l1c_0 }, | |
691 | { gf100_gr_init_wwdx_0 }, | |
692 | { gf100_gr_init_tpccs_1 }, | |
693 | { gf100_gr_init_mpc_0 }, | |
694 | { gf100_gr_init_sm_0 }, | |
695 | { gf100_gr_init_be_0 }, | |
696 | { gf100_gr_init_fe_1 }, | |
697 | { gf100_gr_init_pe_1 }, | |
26410c67 ML |
698 | {} |
699 | }; | |
700 | ||
c33b1e8c BS |
701 | /******************************************************************************* |
702 | * PGRAPH engine/subdev functions | |
703 | ******************************************************************************/ | |
704 | ||
ac9738bb | 705 | void |
bfee3f3d | 706 | gf100_gr_zbc_init(struct gf100_gr *gr) |
ac9738bb BS |
707 | { |
708 | const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
709 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; | |
710 | const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, | |
711 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; | |
712 | const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
713 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; | |
714 | const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, | |
715 | 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; | |
70bc7182 | 716 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
ac9738bb BS |
717 | int index; |
718 | ||
bfee3f3d BS |
719 | if (!gr->zbc_color[0].format) { |
720 | gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); | |
721 | gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); | |
722 | gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); | |
723 | gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); | |
724 | gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); | |
725 | gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); | |
ac9738bb BS |
726 | } |
727 | ||
728 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) | |
bfee3f3d | 729 | gf100_gr_zbc_clear_color(gr, index); |
ac9738bb | 730 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
bfee3f3d | 731 | gf100_gr_zbc_clear_depth(gr, index); |
ac9738bb BS |
732 | } |
733 | ||
4a8cf451 AC |
734 | /** |
735 | * Wait until GR goes idle. GR is considered idle if it is disabled by the | |
736 | * MC (0x200) register, or GR is not busy and a context switch is not in | |
737 | * progress. | |
738 | */ | |
739 | int | |
bfee3f3d | 740 | gf100_gr_wait_idle(struct gf100_gr *gr) |
4a8cf451 | 741 | { |
109c2f2f BS |
742 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
743 | struct nvkm_device *device = subdev->device; | |
4a8cf451 AC |
744 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); |
745 | bool gr_enabled, ctxsw_active, gr_busy; | |
746 | ||
747 | do { | |
748 | /* | |
749 | * required to make sure FIFO_ENGINE_STATUS (0x2640) is | |
750 | * up-to-date | |
751 | */ | |
276836d4 | 752 | nvkm_rd32(device, 0x400700); |
4a8cf451 | 753 | |
276836d4 BS |
754 | gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; |
755 | ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; | |
756 | gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; | |
4a8cf451 AC |
757 | |
758 | if (!gr_enabled || (!gr_busy && !ctxsw_active)) | |
759 | return 0; | |
760 | } while (time_before(jiffies, end_jiffies)); | |
761 | ||
109c2f2f BS |
762 | nvkm_error(subdev, |
763 | "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", | |
764 | gr_enabled, ctxsw_active, gr_busy); | |
4a8cf451 AC |
765 | return -EAGAIN; |
766 | } | |
767 | ||
30f4e087 | 768 | void |
bfee3f3d | 769 | gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
4b223eef | 770 | { |
276836d4 | 771 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
772 | const struct gf100_gr_pack *pack; |
773 | const struct gf100_gr_init *init; | |
c33b1e8c BS |
774 | |
775 | pack_for_each_init(init, pack, p) { | |
776 | u32 next = init->addr + init->count * init->pitch; | |
777 | u32 addr = init->addr; | |
778 | while (addr < next) { | |
276836d4 | 779 | nvkm_wr32(device, addr, init->data); |
30f4e087 BS |
780 | addr += init->pitch; |
781 | } | |
782 | } | |
ebb945a9 BS |
783 | } |
784 | ||
785 | void | |
bfee3f3d | 786 | gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
ebb945a9 | 787 | { |
276836d4 | 788 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
789 | const struct gf100_gr_pack *pack; |
790 | const struct gf100_gr_init *init; | |
c33b1e8c | 791 | u32 data = 0; |
30f4e087 | 792 | |
276836d4 | 793 | nvkm_wr32(device, 0x400208, 0x80000000); |
c33b1e8c BS |
794 | |
795 | pack_for_each_init(init, pack, p) { | |
796 | u32 next = init->addr + init->count * init->pitch; | |
797 | u32 addr = init->addr; | |
798 | ||
799 | if ((pack == p && init == p->init) || data != init->data) { | |
276836d4 | 800 | nvkm_wr32(device, 0x400204, init->data); |
30f4e087 BS |
801 | data = init->data; |
802 | } | |
ebb945a9 | 803 | |
c33b1e8c | 804 | while (addr < next) { |
276836d4 | 805 | nvkm_wr32(device, 0x400200, addr); |
4a8cf451 AC |
806 | /** |
807 | * Wait for GR to go idle after submitting a | |
808 | * GO_IDLE bundle | |
809 | */ | |
810 | if ((addr & 0xffff) == 0xe100) | |
bfee3f3d | 811 | gf100_gr_wait_idle(gr); |
c4584adc BS |
812 | nvkm_msec(device, 2000, |
813 | if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) | |
814 | break; | |
815 | ); | |
30f4e087 | 816 | addr += init->pitch; |
30f4e087 BS |
817 | } |
818 | } | |
c33b1e8c | 819 | |
276836d4 | 820 | nvkm_wr32(device, 0x400208, 0x00000000); |
30f4e087 BS |
821 | } |
822 | ||
823 | void | |
bfee3f3d | 824 | gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
30f4e087 | 825 | { |
276836d4 | 826 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
827 | const struct gf100_gr_pack *pack; |
828 | const struct gf100_gr_init *init; | |
c33b1e8c | 829 | u32 data = 0; |
30f4e087 | 830 | |
c33b1e8c BS |
831 | pack_for_each_init(init, pack, p) { |
832 | u32 ctrl = 0x80000000 | pack->type; | |
833 | u32 next = init->addr + init->count * init->pitch; | |
834 | u32 addr = init->addr; | |
835 | ||
836 | if ((pack == p && init == p->init) || data != init->data) { | |
276836d4 | 837 | nvkm_wr32(device, 0x40448c, init->data); |
c33b1e8c BS |
838 | data = init->data; |
839 | } | |
840 | ||
841 | while (addr < next) { | |
276836d4 | 842 | nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); |
c33b1e8c | 843 | addr += init->pitch; |
30f4e087 BS |
844 | } |
845 | } | |
846 | } | |
847 | ||
848 | u64 | |
c85ee6ca | 849 | gf100_gr_units(struct nvkm_gr *base) |
30f4e087 | 850 | { |
c85ee6ca | 851 | struct gf100_gr *gr = gf100_gr(base); |
30f4e087 BS |
852 | u64 cfg; |
853 | ||
bfee3f3d BS |
854 | cfg = (u32)gr->gpc_nr; |
855 | cfg |= (u32)gr->tpc_total << 8; | |
856 | cfg |= (u64)gr->rop_nr << 32; | |
30f4e087 BS |
857 | |
858 | return cfg; | |
ebb945a9 BS |
859 | } |
860 | ||
caf2be8a IM |
861 | static const struct nvkm_bitfield gf100_dispatch_error[] = { |
862 | { 0x00000001, "INJECTED_BUNDLE_ERROR" }, | |
863 | { 0x00000002, "CLASS_SUBCH_MISMATCH" }, | |
864 | { 0x00000004, "SUBCHSW_DURING_NOTIFY" }, | |
865 | {} | |
866 | }; | |
867 | ||
868 | static const struct nvkm_bitfield gf100_m2mf_error[] = { | |
869 | { 0x00000001, "PUSH_TOO_MUCH_DATA" }, | |
870 | { 0x00000002, "PUSH_NOT_ENOUGH_DATA" }, | |
871 | {} | |
872 | }; | |
873 | ||
874 | static const struct nvkm_bitfield gf100_unk6_error[] = { | |
875 | { 0x00000001, "TEMP_TOO_SMALL" }, | |
876 | {} | |
877 | }; | |
878 | ||
879 | static const struct nvkm_bitfield gf100_ccache_error[] = { | |
880 | { 0x00000001, "INTR" }, | |
881 | { 0x00000002, "LDCONST_OOB" }, | |
882 | {} | |
883 | }; | |
884 | ||
885 | static const struct nvkm_bitfield gf100_macro_error[] = { | |
886 | { 0x00000001, "TOO_FEW_PARAMS" }, | |
887 | { 0x00000002, "TOO_MANY_PARAMS" }, | |
888 | { 0x00000004, "ILLEGAL_OPCODE" }, | |
889 | { 0x00000008, "DOUBLE_BRANCH" }, | |
890 | { 0x00000010, "WATCHDOG" }, | |
891 | {} | |
892 | }; | |
893 | ||
109c2f2f | 894 | static const struct nvkm_bitfield gk104_sked_error[] = { |
caf2be8a | 895 | { 0x00000040, "CTA_RESUME" }, |
109c2f2f BS |
896 | { 0x00000080, "CONSTANT_BUFFER_SIZE" }, |
897 | { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, | |
898 | { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, | |
899 | { 0x00000800, "WARP_CSTACK_SIZE" }, | |
900 | { 0x00001000, "TOTAL_TEMP_SIZE" }, | |
901 | { 0x00002000, "REGISTER_COUNT" }, | |
902 | { 0x00040000, "TOTAL_THREADS" }, | |
903 | { 0x00100000, "PROGRAM_OFFSET" }, | |
904 | { 0x00200000, "SHARED_MEMORY_SIZE" }, | |
caf2be8a IM |
905 | { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" }, |
906 | { 0x01000000, "MEMORY_WINDOW_OVERLAP" }, | |
109c2f2f BS |
907 | { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, |
908 | { 0x04000000, "TOTAL_REGISTER_COUNT" }, | |
30f4e087 BS |
909 | {} |
910 | }; | |
911 | ||
109c2f2f BS |
912 | static const struct nvkm_bitfield gf100_gpc_rop_error[] = { |
913 | { 0x00000002, "RT_PITCH_OVERRUN" }, | |
914 | { 0x00000010, "RT_WIDTH_OVERRUN" }, | |
915 | { 0x00000020, "RT_HEIGHT_OVERRUN" }, | |
916 | { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, | |
917 | { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, | |
918 | { 0x00000400, "RT_LINEAR_MISMATCH" }, | |
30f4e087 BS |
919 | {} |
920 | }; | |
921 | ||
ebb945a9 | 922 | static void |
bfee3f3d | 923 | gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) |
ebb945a9 | 924 | { |
109c2f2f BS |
925 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
926 | struct nvkm_device *device = subdev->device; | |
927 | char error[128]; | |
30f4e087 | 928 | u32 trap[4]; |
ebb945a9 | 929 | |
109c2f2f | 930 | trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; |
276836d4 BS |
931 | trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); |
932 | trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); | |
933 | trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); | |
ebb945a9 | 934 | |
109c2f2f | 935 | nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); |
30f4e087 | 936 | |
109c2f2f BS |
937 | nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " |
938 | "format = %x, storage type = %x\n", | |
939 | gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, | |
940 | (trap[2] >> 8) & 0x3f, trap[3] & 0xff); | |
276836d4 | 941 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
ebb945a9 BS |
942 | } |
943 | ||
e3c71eb2 | 944 | static const struct nvkm_enum gf100_mp_warp_error[] = { |
fec43a72 BS |
945 | { 0x00, "NO_ERROR" }, |
946 | { 0x01, "STACK_MISMATCH" }, | |
947 | { 0x05, "MISALIGNED_PC" }, | |
948 | { 0x08, "MISALIGNED_GPR" }, | |
949 | { 0x09, "INVALID_OPCODE" }, | |
950 | { 0x0d, "GPR_OUT_OF_BOUNDS" }, | |
951 | { 0x0e, "MEM_OUT_OF_BOUNDS" }, | |
952 | { 0x0f, "UNALIGNED_MEM_ACCESS" }, | |
3988f645 | 953 | { 0x10, "INVALID_ADDR_SPACE" }, |
fec43a72 BS |
954 | { 0x11, "INVALID_PARAM" }, |
955 | {} | |
956 | }; | |
957 | ||
e3c71eb2 | 958 | static const struct nvkm_bitfield gf100_mp_global_error[] = { |
fec43a72 BS |
959 | { 0x00000004, "MULTIPLE_WARP_ERRORS" }, |
960 | { 0x00000008, "OUT_OF_STACK_SPACE" }, | |
961 | {} | |
962 | }; | |
963 | ||
964 | static void | |
bfee3f3d | 965 | gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) |
fec43a72 | 966 | { |
109c2f2f BS |
967 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
968 | struct nvkm_device *device = subdev->device; | |
276836d4 BS |
969 | u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); |
970 | u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); | |
109c2f2f BS |
971 | const struct nvkm_enum *warp; |
972 | char glob[128]; | |
fec43a72 | 973 | |
109c2f2f BS |
974 | nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); |
975 | warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); | |
976 | ||
977 | nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " | |
978 | "global %08x [%s] warp %04x [%s]\n", | |
979 | gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); | |
fec43a72 | 980 | |
276836d4 BS |
981 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); |
982 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); | |
fec43a72 BS |
983 | } |
984 | ||
f73221e4 | 985 | static void |
bfee3f3d | 986 | gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) |
f73221e4 | 987 | { |
109c2f2f BS |
988 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
989 | struct nvkm_device *device = subdev->device; | |
276836d4 | 990 | u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); |
f73221e4 BS |
991 | |
992 | if (stat & 0x00000001) { | |
276836d4 | 993 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); |
109c2f2f | 994 | nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); |
276836d4 | 995 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); |
f73221e4 BS |
996 | stat &= ~0x00000001; |
997 | } | |
998 | ||
999 | if (stat & 0x00000002) { | |
bfee3f3d | 1000 | gf100_gr_trap_mp(gr, gpc, tpc); |
f73221e4 BS |
1001 | stat &= ~0x00000002; |
1002 | } | |
1003 | ||
1004 | if (stat & 0x00000004) { | |
276836d4 | 1005 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); |
109c2f2f | 1006 | nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); |
276836d4 | 1007 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); |
f73221e4 BS |
1008 | stat &= ~0x00000004; |
1009 | } | |
1010 | ||
1011 | if (stat & 0x00000008) { | |
276836d4 | 1012 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); |
109c2f2f | 1013 | nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); |
276836d4 | 1014 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); |
f73221e4 BS |
1015 | stat &= ~0x00000008; |
1016 | } | |
1017 | ||
1018 | if (stat) { | |
109c2f2f | 1019 | nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); |
f73221e4 BS |
1020 | } |
1021 | } | |
1022 | ||
1023 | static void | |
bfee3f3d | 1024 | gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) |
f73221e4 | 1025 | { |
109c2f2f BS |
1026 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1027 | struct nvkm_device *device = subdev->device; | |
276836d4 | 1028 | u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); |
f73221e4 BS |
1029 | int tpc; |
1030 | ||
1031 | if (stat & 0x00000001) { | |
bfee3f3d | 1032 | gf100_gr_trap_gpc_rop(gr, gpc); |
f73221e4 BS |
1033 | stat &= ~0x00000001; |
1034 | } | |
1035 | ||
1036 | if (stat & 0x00000002) { | |
276836d4 | 1037 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); |
109c2f2f | 1038 | nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); |
276836d4 | 1039 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
f73221e4 BS |
1040 | stat &= ~0x00000002; |
1041 | } | |
1042 | ||
1043 | if (stat & 0x00000004) { | |
276836d4 | 1044 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); |
109c2f2f | 1045 | nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); |
276836d4 | 1046 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
f73221e4 BS |
1047 | stat &= ~0x00000004; |
1048 | } | |
1049 | ||
1050 | if (stat & 0x00000008) { | |
276836d4 | 1051 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); |
109c2f2f | 1052 | nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); |
276836d4 | 1053 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
f73221e4 BS |
1054 | stat &= ~0x00000009; |
1055 | } | |
1056 | ||
bfee3f3d | 1057 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
f73221e4 BS |
1058 | u32 mask = 0x00010000 << tpc; |
1059 | if (stat & mask) { | |
bfee3f3d | 1060 | gf100_gr_trap_tpc(gr, gpc, tpc); |
276836d4 | 1061 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); |
f73221e4 BS |
1062 | stat &= ~mask; |
1063 | } | |
1064 | } | |
1065 | ||
1066 | if (stat) { | |
109c2f2f | 1067 | nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); |
f73221e4 BS |
1068 | } |
1069 | } | |
1070 | ||
1071 | static void | |
bfee3f3d | 1072 | gf100_gr_trap_intr(struct gf100_gr *gr) |
f73221e4 | 1073 | { |
109c2f2f BS |
1074 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1075 | struct nvkm_device *device = subdev->device; | |
caf2be8a | 1076 | char error[128]; |
276836d4 | 1077 | u32 trap = nvkm_rd32(device, 0x400108); |
109c2f2f | 1078 | int rop, gpc; |
f73221e4 BS |
1079 | |
1080 | if (trap & 0x00000001) { | |
276836d4 | 1081 | u32 stat = nvkm_rd32(device, 0x404000); |
caf2be8a IM |
1082 | |
1083 | nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error, | |
1084 | stat & 0x3fffffff); | |
1085 | nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error); | |
276836d4 BS |
1086 | nvkm_wr32(device, 0x404000, 0xc0000000); |
1087 | nvkm_wr32(device, 0x400108, 0x00000001); | |
f73221e4 BS |
1088 | trap &= ~0x00000001; |
1089 | } | |
1090 | ||
1091 | if (trap & 0x00000002) { | |
276836d4 | 1092 | u32 stat = nvkm_rd32(device, 0x404600); |
caf2be8a IM |
1093 | |
1094 | nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, | |
1095 | stat & 0x3fffffff); | |
1096 | nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error); | |
1097 | ||
276836d4 BS |
1098 | nvkm_wr32(device, 0x404600, 0xc0000000); |
1099 | nvkm_wr32(device, 0x400108, 0x00000002); | |
f73221e4 BS |
1100 | trap &= ~0x00000002; |
1101 | } | |
1102 | ||
1103 | if (trap & 0x00000008) { | |
276836d4 | 1104 | u32 stat = nvkm_rd32(device, 0x408030); |
caf2be8a IM |
1105 | |
1106 | nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, | |
1107 | stat & 0x3fffffff); | |
1108 | nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error); | |
276836d4 BS |
1109 | nvkm_wr32(device, 0x408030, 0xc0000000); |
1110 | nvkm_wr32(device, 0x400108, 0x00000008); | |
f73221e4 BS |
1111 | trap &= ~0x00000008; |
1112 | } | |
1113 | ||
1114 | if (trap & 0x00000010) { | |
276836d4 | 1115 | u32 stat = nvkm_rd32(device, 0x405840); |
caf2be8a IM |
1116 | nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n", |
1117 | stat, stat & 0xffffff, (stat >> 24) & 0x3f); | |
276836d4 BS |
1118 | nvkm_wr32(device, 0x405840, 0xc0000000); |
1119 | nvkm_wr32(device, 0x400108, 0x00000010); | |
f73221e4 BS |
1120 | trap &= ~0x00000010; |
1121 | } | |
1122 | ||
1123 | if (trap & 0x00000040) { | |
276836d4 | 1124 | u32 stat = nvkm_rd32(device, 0x40601c); |
caf2be8a IM |
1125 | |
1126 | nvkm_snprintbf(error, sizeof(error), gf100_unk6_error, | |
1127 | stat & 0x3fffffff); | |
1128 | nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error); | |
1129 | ||
276836d4 BS |
1130 | nvkm_wr32(device, 0x40601c, 0xc0000000); |
1131 | nvkm_wr32(device, 0x400108, 0x00000040); | |
f73221e4 BS |
1132 | trap &= ~0x00000040; |
1133 | } | |
1134 | ||
1135 | if (trap & 0x00000080) { | |
276836d4 | 1136 | u32 stat = nvkm_rd32(device, 0x404490); |
caf2be8a IM |
1137 | u32 pc = nvkm_rd32(device, 0x404494); |
1138 | u32 op = nvkm_rd32(device, 0x40449c); | |
1139 | ||
1140 | nvkm_snprintbf(error, sizeof(error), gf100_macro_error, | |
1141 | stat & 0x1fffffff); | |
1142 | nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n", | |
1143 | stat, error, pc & 0x7ff, | |
1144 | (pc & 0x10000000) ? "" : " (invalid)", | |
1145 | op); | |
1146 | ||
276836d4 BS |
1147 | nvkm_wr32(device, 0x404490, 0xc0000000); |
1148 | nvkm_wr32(device, 0x400108, 0x00000080); | |
f73221e4 BS |
1149 | trap &= ~0x00000080; |
1150 | } | |
1151 | ||
30f4e087 | 1152 | if (trap & 0x00000100) { |
109c2f2f | 1153 | u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; |
30f4e087 | 1154 | |
caf2be8a IM |
1155 | nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat); |
1156 | nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error); | |
30f4e087 | 1157 | |
109c2f2f | 1158 | if (stat) |
276836d4 BS |
1159 | nvkm_wr32(device, 0x407020, 0x40000000); |
1160 | nvkm_wr32(device, 0x400108, 0x00000100); | |
30f4e087 BS |
1161 | trap &= ~0x00000100; |
1162 | } | |
1163 | ||
f73221e4 | 1164 | if (trap & 0x01000000) { |
276836d4 | 1165 | u32 stat = nvkm_rd32(device, 0x400118); |
bfee3f3d | 1166 | for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { |
f73221e4 BS |
1167 | u32 mask = 0x00000001 << gpc; |
1168 | if (stat & mask) { | |
bfee3f3d | 1169 | gf100_gr_trap_gpc(gr, gpc); |
276836d4 | 1170 | nvkm_wr32(device, 0x400118, mask); |
f73221e4 BS |
1171 | stat &= ~mask; |
1172 | } | |
1173 | } | |
276836d4 | 1174 | nvkm_wr32(device, 0x400108, 0x01000000); |
f73221e4 BS |
1175 | trap &= ~0x01000000; |
1176 | } | |
1177 | ||
1178 | if (trap & 0x02000000) { | |
bfee3f3d | 1179 | for (rop = 0; rop < gr->rop_nr; rop++) { |
276836d4 BS |
1180 | u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); |
1181 | u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); | |
109c2f2f | 1182 | nvkm_error(subdev, "ROP%d %08x %08x\n", |
f73221e4 | 1183 | rop, statz, statc); |
276836d4 BS |
1184 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); |
1185 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); | |
f73221e4 | 1186 | } |
276836d4 | 1187 | nvkm_wr32(device, 0x400108, 0x02000000); |
f73221e4 BS |
1188 | trap &= ~0x02000000; |
1189 | } | |
1190 | ||
1191 | if (trap) { | |
109c2f2f | 1192 | nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); |
276836d4 | 1193 | nvkm_wr32(device, 0x400108, trap); |
f73221e4 BS |
1194 | } |
1195 | } | |
1196 | ||
30f4e087 | 1197 | static void |
bfee3f3d | 1198 | gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) |
30f4e087 | 1199 | { |
109c2f2f BS |
1200 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1201 | struct nvkm_device *device = subdev->device; | |
1202 | nvkm_error(subdev, "%06x - done %08x\n", base, | |
1203 | nvkm_rd32(device, base + 0x400)); | |
1204 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, | |
1205 | nvkm_rd32(device, base + 0x800), | |
1206 | nvkm_rd32(device, base + 0x804), | |
1207 | nvkm_rd32(device, base + 0x808), | |
1208 | nvkm_rd32(device, base + 0x80c)); | |
1209 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, | |
1210 | nvkm_rd32(device, base + 0x810), | |
1211 | nvkm_rd32(device, base + 0x814), | |
1212 | nvkm_rd32(device, base + 0x818), | |
1213 | nvkm_rd32(device, base + 0x81c)); | |
30f4e087 BS |
1214 | } |
1215 | ||
1216 | void | |
bfee3f3d | 1217 | gf100_gr_ctxctl_debug(struct gf100_gr *gr) |
30f4e087 | 1218 | { |
276836d4 BS |
1219 | struct nvkm_device *device = gr->base.engine.subdev.device; |
1220 | u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; | |
30f4e087 BS |
1221 | u32 gpc; |
1222 | ||
bfee3f3d | 1223 | gf100_gr_ctxctl_debug_unit(gr, 0x409000); |
30f4e087 | 1224 | for (gpc = 0; gpc < gpcnr; gpc++) |
bfee3f3d | 1225 | gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); |
30f4e087 BS |
1226 | } |
1227 | ||
1228 | static void | |
bfee3f3d | 1229 | gf100_gr_ctxctl_isr(struct gf100_gr *gr) |
30f4e087 | 1230 | { |
109c2f2f BS |
1231 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1232 | struct nvkm_device *device = subdev->device; | |
276836d4 | 1233 | u32 stat = nvkm_rd32(device, 0x409c18); |
30f4e087 | 1234 | |
23f67841 | 1235 | if (stat & 0x00000001) { |
276836d4 | 1236 | u32 code = nvkm_rd32(device, 0x409814); |
23f67841 | 1237 | if (code == E_BAD_FWMTHD) { |
276836d4 BS |
1238 | u32 class = nvkm_rd32(device, 0x409808); |
1239 | u32 addr = nvkm_rd32(device, 0x40980c); | |
23f67841 BS |
1240 | u32 subc = (addr & 0x00070000) >> 16; |
1241 | u32 mthd = (addr & 0x00003ffc); | |
276836d4 | 1242 | u32 data = nvkm_rd32(device, 0x409810); |
23f67841 | 1243 | |
109c2f2f BS |
1244 | nvkm_error(subdev, "FECS MTHD subc %d class %04x " |
1245 | "mthd %04x data %08x\n", | |
1246 | subc, class, mthd, data); | |
23f67841 | 1247 | |
276836d4 | 1248 | nvkm_wr32(device, 0x409c20, 0x00000001); |
23f67841 BS |
1249 | stat &= ~0x00000001; |
1250 | } else { | |
109c2f2f | 1251 | nvkm_error(subdev, "FECS ucode error %d\n", code); |
23f67841 BS |
1252 | } |
1253 | } | |
30f4e087 | 1254 | |
23f67841 | 1255 | if (stat & 0x00080000) { |
109c2f2f | 1256 | nvkm_error(subdev, "FECS watchdog timeout\n"); |
bfee3f3d | 1257 | gf100_gr_ctxctl_debug(gr); |
276836d4 | 1258 | nvkm_wr32(device, 0x409c20, 0x00080000); |
23f67841 BS |
1259 | stat &= ~0x00080000; |
1260 | } | |
1261 | ||
1262 | if (stat) { | |
109c2f2f | 1263 | nvkm_error(subdev, "FECS %08x\n", stat); |
bfee3f3d | 1264 | gf100_gr_ctxctl_debug(gr); |
276836d4 | 1265 | nvkm_wr32(device, 0x409c20, stat); |
23f67841 | 1266 | } |
30f4e087 BS |
1267 | } |
1268 | ||
ebb945a9 | 1269 | static void |
c85ee6ca | 1270 | gf100_gr_intr(struct nvkm_gr *base) |
ebb945a9 | 1271 | { |
c85ee6ca BS |
1272 | struct gf100_gr *gr = gf100_gr(base); |
1273 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; | |
1274 | struct nvkm_device *device = subdev->device; | |
a65955e1 BS |
1275 | struct nvkm_fifo_chan *chan; |
1276 | unsigned long flags; | |
276836d4 BS |
1277 | u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; |
1278 | u32 stat = nvkm_rd32(device, 0x400100); | |
1279 | u32 addr = nvkm_rd32(device, 0x400704); | |
ebb945a9 BS |
1280 | u32 mthd = (addr & 0x00003ffc); |
1281 | u32 subc = (addr & 0x00070000) >> 16; | |
276836d4 BS |
1282 | u32 data = nvkm_rd32(device, 0x400708); |
1283 | u32 code = nvkm_rd32(device, 0x400110); | |
91c772ec | 1284 | u32 class; |
8f0649b5 BS |
1285 | const char *name = "unknown"; |
1286 | int chid = -1; | |
72a14827 | 1287 | |
a65955e1 | 1288 | chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); |
8f0649b5 BS |
1289 | if (chan) { |
1290 | name = chan->object.client->name; | |
1291 | chid = chan->chid; | |
1292 | } | |
a65955e1 | 1293 | |
c85ee6ca | 1294 | if (device->card_type < NV_E0 || subc < 4) |
276836d4 | 1295 | class = nvkm_rd32(device, 0x404200 + (subc * 4)); |
91c772ec BS |
1296 | else |
1297 | class = 0x0000; | |
1298 | ||
c6a7b026 LP |
1299 | if (stat & 0x00000001) { |
1300 | /* | |
1301 | * notifier interrupt, only needed for cyclestats | |
1302 | * can be safely ignored | |
1303 | */ | |
276836d4 | 1304 | nvkm_wr32(device, 0x400100, 0x00000001); |
c6a7b026 LP |
1305 | stat &= ~0x00000001; |
1306 | } | |
1307 | ||
ebb945a9 | 1308 | if (stat & 0x00000010) { |
a65955e1 | 1309 | if (!gf100_gr_mthd_sw(device, class, mthd, data)) { |
109c2f2f BS |
1310 | nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " |
1311 | "subc %d class %04x mthd %04x data %08x\n", | |
8f0649b5 BS |
1312 | chid, inst << 12, name, subc, |
1313 | class, mthd, data); | |
ebb945a9 | 1314 | } |
276836d4 | 1315 | nvkm_wr32(device, 0x400100, 0x00000010); |
ebb945a9 BS |
1316 | stat &= ~0x00000010; |
1317 | } | |
1318 | ||
1319 | if (stat & 0x00000020) { | |
109c2f2f BS |
1320 | nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " |
1321 | "subc %d class %04x mthd %04x data %08x\n", | |
8f0649b5 | 1322 | chid, inst << 12, name, subc, class, mthd, data); |
276836d4 | 1323 | nvkm_wr32(device, 0x400100, 0x00000020); |
ebb945a9 BS |
1324 | stat &= ~0x00000020; |
1325 | } | |
1326 | ||
1327 | if (stat & 0x00100000) { | |
109c2f2f BS |
1328 | const struct nvkm_enum *en = |
1329 | nvkm_enum_find(nv50_data_error_names, code); | |
1330 | nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " | |
1331 | "subc %d class %04x mthd %04x data %08x\n", | |
1332 | code, en ? en->name : "", chid, inst << 12, | |
8f0649b5 | 1333 | name, subc, class, mthd, data); |
276836d4 | 1334 | nvkm_wr32(device, 0x400100, 0x00100000); |
ebb945a9 BS |
1335 | stat &= ~0x00100000; |
1336 | } | |
1337 | ||
1338 | if (stat & 0x00200000) { | |
109c2f2f | 1339 | nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", |
8f0649b5 | 1340 | chid, inst << 12, name); |
bfee3f3d | 1341 | gf100_gr_trap_intr(gr); |
276836d4 | 1342 | nvkm_wr32(device, 0x400100, 0x00200000); |
ebb945a9 BS |
1343 | stat &= ~0x00200000; |
1344 | } | |
1345 | ||
1346 | if (stat & 0x00080000) { | |
bfee3f3d | 1347 | gf100_gr_ctxctl_isr(gr); |
276836d4 | 1348 | nvkm_wr32(device, 0x400100, 0x00080000); |
ebb945a9 BS |
1349 | stat &= ~0x00080000; |
1350 | } | |
1351 | ||
1352 | if (stat) { | |
109c2f2f | 1353 | nvkm_error(subdev, "intr %08x\n", stat); |
276836d4 | 1354 | nvkm_wr32(device, 0x400100, stat); |
ebb945a9 BS |
1355 | } |
1356 | ||
276836d4 | 1357 | nvkm_wr32(device, 0x400500, 0x00010001); |
a65955e1 | 1358 | nvkm_fifo_chan_put(device->fifo, flags, &chan); |
ebb945a9 BS |
1359 | } |
1360 | ||
30f4e087 | 1361 | void |
bfee3f3d | 1362 | gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, |
e3c71eb2 | 1363 | struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) |
ebb945a9 | 1364 | { |
276836d4 | 1365 | struct nvkm_device *device = gr->base.engine.subdev.device; |
30f4e087 | 1366 | int i; |
ebb945a9 | 1367 | |
276836d4 | 1368 | nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); |
30f4e087 | 1369 | for (i = 0; i < data->size / 4; i++) |
276836d4 | 1370 | nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); |
ebb945a9 | 1371 | |
276836d4 | 1372 | nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); |
30f4e087 BS |
1373 | for (i = 0; i < code->size / 4; i++) { |
1374 | if ((i & 0x3f) == 0) | |
276836d4 BS |
1375 | nvkm_wr32(device, fuc_base + 0x0188, i >> 6); |
1376 | nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); | |
30f4e087 | 1377 | } |
370eec76 AC |
1378 | |
1379 | /* code must be padded to 0x40 words */ | |
1380 | for (; i & 0x3f; i++) | |
276836d4 | 1381 | nvkm_wr32(device, fuc_base + 0x0184, 0); |
966a5b7d BS |
1382 | } |
1383 | ||
a32b2ffb | 1384 | static void |
bfee3f3d | 1385 | gf100_gr_init_csdata(struct gf100_gr *gr, |
e3c71eb2 BS |
1386 | const struct gf100_gr_pack *pack, |
1387 | u32 falcon, u32 starstar, u32 base) | |
a32b2ffb | 1388 | { |
276836d4 | 1389 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
1390 | const struct gf100_gr_pack *iter; |
1391 | const struct gf100_gr_init *init; | |
c33b1e8c | 1392 | u32 addr = ~0, prev = ~0, xfer = 0; |
a32b2ffb BS |
1393 | u32 star, temp; |
1394 | ||
276836d4 BS |
1395 | nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); |
1396 | star = nvkm_rd32(device, falcon + 0x01c4); | |
1397 | temp = nvkm_rd32(device, falcon + 0x01c4); | |
a32b2ffb BS |
1398 | if (temp > star) |
1399 | star = temp; | |
276836d4 | 1400 | nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); |
a32b2ffb | 1401 | |
c33b1e8c BS |
1402 | pack_for_each_init(init, iter, pack) { |
1403 | u32 head = init->addr - base; | |
1404 | u32 tail = head + init->count * init->pitch; | |
1405 | while (head < tail) { | |
1406 | if (head != prev + 4 || xfer >= 32) { | |
1407 | if (xfer) { | |
1408 | u32 data = ((--xfer << 26) | addr); | |
276836d4 | 1409 | nvkm_wr32(device, falcon + 0x01c4, data); |
c33b1e8c BS |
1410 | star += 4; |
1411 | } | |
1412 | addr = head; | |
1413 | xfer = 0; | |
a32b2ffb | 1414 | } |
c33b1e8c BS |
1415 | prev = head; |
1416 | xfer = xfer + 1; | |
1417 | head = head + init->pitch; | |
a32b2ffb | 1418 | } |
c33b1e8c | 1419 | } |
a32b2ffb | 1420 | |
276836d4 BS |
1421 | nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); |
1422 | nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); | |
1423 | nvkm_wr32(device, falcon + 0x01c4, star + 4); | |
a32b2ffb BS |
1424 | } |
1425 | ||
30f4e087 | 1426 | int |
bfee3f3d | 1427 | gf100_gr_init_ctxctl(struct gf100_gr *gr) |
966a5b7d | 1428 | { |
27f3d6cf | 1429 | const struct gf100_grctx_func *grctx = gr->func->grctx; |
109c2f2f BS |
1430 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1431 | struct nvkm_device *device = subdev->device; | |
c9469aae | 1432 | struct nvkm_secboot *sb = device->secboot; |
30f4e087 | 1433 | int i; |
ebb945a9 | 1434 | |
bfee3f3d | 1435 | if (gr->firmware) { |
30f4e087 | 1436 | /* load fuc microcode */ |
54dcadd5 | 1437 | nvkm_mc_unk260(device->mc, 0); |
c9469aae AC |
1438 | |
1439 | /* securely-managed falcons must be reset using secure boot */ | |
1440 | if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) | |
1441 | nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS); | |
1442 | else | |
1443 | gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, | |
1444 | &gr->fuc409d); | |
1445 | if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) | |
1446 | nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS); | |
1447 | else | |
1448 | gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, | |
1449 | &gr->fuc41ad); | |
1450 | ||
54dcadd5 | 1451 | nvkm_mc_unk260(device->mc, 1); |
ebb945a9 | 1452 | |
30f4e087 | 1453 | /* start both of them running */ |
276836d4 BS |
1454 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1455 | nvkm_wr32(device, 0x41a10c, 0x00000000); | |
1456 | nvkm_wr32(device, 0x40910c, 0x00000000); | |
c9469aae AC |
1457 | |
1458 | if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) | |
1459 | nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS); | |
1460 | else | |
1461 | nvkm_wr32(device, 0x41a100, 0x00000002); | |
1462 | if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) | |
1463 | nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS); | |
1464 | else | |
1465 | nvkm_wr32(device, 0x409100, 0x00000002); | |
c4584adc BS |
1466 | if (nvkm_msec(device, 2000, |
1467 | if (nvkm_rd32(device, 0x409800) & 0x00000001) | |
1468 | break; | |
1469 | ) < 0) | |
1470 | return -EBUSY; | |
bfee3f3d | 1471 | |
276836d4 BS |
1472 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1473 | nvkm_wr32(device, 0x409500, 0x7fffffff); | |
1474 | nvkm_wr32(device, 0x409504, 0x00000021); | |
bfee3f3d | 1475 | |
276836d4 BS |
1476 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1477 | nvkm_wr32(device, 0x409500, 0x00000000); | |
1478 | nvkm_wr32(device, 0x409504, 0x00000010); | |
c4584adc BS |
1479 | if (nvkm_msec(device, 2000, |
1480 | if ((gr->size = nvkm_rd32(device, 0x409800))) | |
1481 | break; | |
1482 | ) < 0) | |
30f4e087 | 1483 | return -EBUSY; |
0411de85 | 1484 | |
276836d4 BS |
1485 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1486 | nvkm_wr32(device, 0x409500, 0x00000000); | |
1487 | nvkm_wr32(device, 0x409504, 0x00000016); | |
c4584adc BS |
1488 | if (nvkm_msec(device, 2000, |
1489 | if (nvkm_rd32(device, 0x409800)) | |
1490 | break; | |
1491 | ) < 0) | |
ac1499d9 | 1492 | return -EBUSY; |
ac1499d9 | 1493 | |
276836d4 BS |
1494 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1495 | nvkm_wr32(device, 0x409500, 0x00000000); | |
1496 | nvkm_wr32(device, 0x409504, 0x00000025); | |
c4584adc BS |
1497 | if (nvkm_msec(device, 2000, |
1498 | if (nvkm_rd32(device, 0x409800)) | |
1499 | break; | |
1500 | ) < 0) | |
ac1499d9 | 1501 | return -EBUSY; |
ac1499d9 | 1502 | |
c85ee6ca | 1503 | if (device->chipset >= 0xe0) { |
276836d4 BS |
1504 | nvkm_wr32(device, 0x409800, 0x00000000); |
1505 | nvkm_wr32(device, 0x409500, 0x00000001); | |
1506 | nvkm_wr32(device, 0x409504, 0x00000030); | |
c4584adc BS |
1507 | if (nvkm_msec(device, 2000, |
1508 | if (nvkm_rd32(device, 0x409800)) | |
1509 | break; | |
1510 | ) < 0) | |
30f4e087 | 1511 | return -EBUSY; |
30f4e087 | 1512 | |
276836d4 BS |
1513 | nvkm_wr32(device, 0x409810, 0xb00095c8); |
1514 | nvkm_wr32(device, 0x409800, 0x00000000); | |
1515 | nvkm_wr32(device, 0x409500, 0x00000001); | |
1516 | nvkm_wr32(device, 0x409504, 0x00000031); | |
c4584adc BS |
1517 | if (nvkm_msec(device, 2000, |
1518 | if (nvkm_rd32(device, 0x409800)) | |
1519 | break; | |
1520 | ) < 0) | |
30f4e087 | 1521 | return -EBUSY; |
30f4e087 | 1522 | |
276836d4 BS |
1523 | nvkm_wr32(device, 0x409810, 0x00080420); |
1524 | nvkm_wr32(device, 0x409800, 0x00000000); | |
1525 | nvkm_wr32(device, 0x409500, 0x00000001); | |
1526 | nvkm_wr32(device, 0x409504, 0x00000032); | |
c4584adc BS |
1527 | if (nvkm_msec(device, 2000, |
1528 | if (nvkm_rd32(device, 0x409800)) | |
1529 | break; | |
1530 | ) < 0) | |
30f4e087 | 1531 | return -EBUSY; |
30f4e087 | 1532 | |
276836d4 BS |
1533 | nvkm_wr32(device, 0x409614, 0x00000070); |
1534 | nvkm_wr32(device, 0x409614, 0x00000770); | |
1535 | nvkm_wr32(device, 0x40802c, 0x00000001); | |
30f4e087 BS |
1536 | } |
1537 | ||
bfee3f3d BS |
1538 | if (gr->data == NULL) { |
1539 | int ret = gf100_grctx_generate(gr); | |
ebb945a9 | 1540 | if (ret) { |
109c2f2f | 1541 | nvkm_error(subdev, "failed to construct context\n"); |
ebb945a9 BS |
1542 | return ret; |
1543 | } | |
1544 | } | |
1545 | ||
1546 | return 0; | |
96616b4c | 1547 | } else |
c85ee6ca | 1548 | if (!gr->func->fecs.ucode) { |
96616b4c | 1549 | return -ENOSYS; |
0411de85 | 1550 | } |
966a5b7d | 1551 | |
ac1499d9 | 1552 | /* load HUB microcode */ |
54dcadd5 | 1553 | nvkm_mc_unk260(device->mc, 0); |
276836d4 | 1554 | nvkm_wr32(device, 0x4091c0, 0x01000000); |
c85ee6ca BS |
1555 | for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++) |
1556 | nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]); | |
ac1499d9 | 1557 | |
276836d4 | 1558 | nvkm_wr32(device, 0x409180, 0x01000000); |
c85ee6ca | 1559 | for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) { |
ac1499d9 | 1560 | if ((i & 0x3f) == 0) |
276836d4 | 1561 | nvkm_wr32(device, 0x409188, i >> 6); |
c85ee6ca | 1562 | nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]); |
ac1499d9 BS |
1563 | } |
1564 | ||
1565 | /* load GPC microcode */ | |
276836d4 | 1566 | nvkm_wr32(device, 0x41a1c0, 0x01000000); |
c85ee6ca BS |
1567 | for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++) |
1568 | nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]); | |
ac1499d9 | 1569 | |
276836d4 | 1570 | nvkm_wr32(device, 0x41a180, 0x01000000); |
c85ee6ca | 1571 | for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) { |
ac1499d9 | 1572 | if ((i & 0x3f) == 0) |
276836d4 | 1573 | nvkm_wr32(device, 0x41a188, i >> 6); |
c85ee6ca | 1574 | nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]); |
ac1499d9 | 1575 | } |
54dcadd5 | 1576 | nvkm_mc_unk260(device->mc, 1); |
966a5b7d | 1577 | |
c33b1e8c | 1578 | /* load register lists */ |
27f3d6cf BS |
1579 | gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); |
1580 | gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); | |
1581 | gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); | |
1582 | gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); | |
a32b2ffb | 1583 | |
ac1499d9 | 1584 | /* start HUB ucode running, it'll init the GPCs */ |
276836d4 BS |
1585 | nvkm_wr32(device, 0x40910c, 0x00000000); |
1586 | nvkm_wr32(device, 0x409100, 0x00000002); | |
c4584adc BS |
1587 | if (nvkm_msec(device, 2000, |
1588 | if (nvkm_rd32(device, 0x409800) & 0x80000000) | |
1589 | break; | |
1590 | ) < 0) { | |
bfee3f3d | 1591 | gf100_gr_ctxctl_debug(gr); |
966a5b7d BS |
1592 | return -EBUSY; |
1593 | } | |
966a5b7d | 1594 | |
276836d4 | 1595 | gr->size = nvkm_rd32(device, 0x409804); |
bfee3f3d BS |
1596 | if (gr->data == NULL) { |
1597 | int ret = gf100_grctx_generate(gr); | |
ac1499d9 | 1598 | if (ret) { |
109c2f2f | 1599 | nvkm_error(subdev, "failed to construct context\n"); |
ac1499d9 BS |
1600 | return ret; |
1601 | } | |
966a5b7d BS |
1602 | } |
1603 | ||
1604 | return 0; | |
4b223eef BS |
1605 | } |
1606 | ||
c85ee6ca BS |
1607 | static int |
1608 | gf100_gr_oneinit(struct nvkm_gr *base) | |
1609 | { | |
1610 | struct gf100_gr *gr = gf100_gr(base); | |
1611 | struct nvkm_device *device = gr->base.engine.subdev.device; | |
1612 | int ret, i, j; | |
1613 | ||
1614 | nvkm_pmu_pgob(device->pmu, false); | |
1615 | ||
1616 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, | |
1617 | &gr->unk4188b4); | |
1618 | if (ret) | |
1619 | return ret; | |
1620 | ||
1621 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, | |
1622 | &gr->unk4188b8); | |
1623 | if (ret) | |
1624 | return ret; | |
1625 | ||
1626 | nvkm_kmap(gr->unk4188b4); | |
1627 | for (i = 0; i < 0x1000; i += 4) | |
1628 | nvkm_wo32(gr->unk4188b4, i, 0x00000010); | |
1629 | nvkm_done(gr->unk4188b4); | |
1630 | ||
1631 | nvkm_kmap(gr->unk4188b8); | |
1632 | for (i = 0; i < 0x1000; i += 4) | |
1633 | nvkm_wo32(gr->unk4188b8, i, 0x00000010); | |
1634 | nvkm_done(gr->unk4188b8); | |
1635 | ||
1636 | gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; | |
1637 | gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; | |
1638 | for (i = 0; i < gr->gpc_nr; i++) { | |
1639 | gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); | |
1640 | gr->tpc_total += gr->tpc_nr[i]; | |
1641 | gr->ppc_nr[i] = gr->func->ppc_nr; | |
1642 | for (j = 0; j < gr->ppc_nr[i]; j++) { | |
1643 | u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); | |
2fb2b3c6 BS |
1644 | if (mask) |
1645 | gr->ppc_mask[i] |= (1 << j); | |
c85ee6ca BS |
1646 | gr->ppc_tpc_nr[i][j] = hweight8(mask); |
1647 | } | |
1648 | } | |
1649 | ||
1650 | /*XXX: these need figuring out... though it might not even matter */ | |
1651 | switch (device->chipset) { | |
1652 | case 0xc0: | |
1653 | if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ | |
1654 | gr->magic_not_rop_nr = 0x07; | |
1655 | } else | |
1656 | if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ | |
1657 | gr->magic_not_rop_nr = 0x05; | |
1658 | } else | |
1659 | if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ | |
1660 | gr->magic_not_rop_nr = 0x06; | |
1661 | } | |
1662 | break; | |
1663 | case 0xc3: /* 450, 4/0/0/0, 2 */ | |
1664 | gr->magic_not_rop_nr = 0x03; | |
1665 | break; | |
1666 | case 0xc4: /* 460, 3/4/0/0, 4 */ | |
1667 | gr->magic_not_rop_nr = 0x01; | |
1668 | break; | |
1669 | case 0xc1: /* 2/0/0/0, 1 */ | |
1670 | gr->magic_not_rop_nr = 0x01; | |
1671 | break; | |
1672 | case 0xc8: /* 4/4/3/4, 5 */ | |
1673 | gr->magic_not_rop_nr = 0x06; | |
1674 | break; | |
1675 | case 0xce: /* 4/4/0/0, 4 */ | |
1676 | gr->magic_not_rop_nr = 0x03; | |
1677 | break; | |
1678 | case 0xcf: /* 4/0/0/0, 3 */ | |
1679 | gr->magic_not_rop_nr = 0x03; | |
1680 | break; | |
1681 | case 0xd7: | |
1682 | case 0xd9: /* 1/0/0/0, 1 */ | |
1683 | case 0xea: /* gk20a */ | |
1684 | case 0x12b: /* gm20b */ | |
1685 | gr->magic_not_rop_nr = 0x01; | |
1686 | break; | |
1687 | } | |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
1692 | int | |
1693 | gf100_gr_init_(struct nvkm_gr *base) | |
1694 | { | |
1695 | struct gf100_gr *gr = gf100_gr(base); | |
1696 | nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); | |
1697 | return gr->func->init(gr); | |
1698 | } | |
1699 | ||
1700 | void | |
1701 | gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) | |
1702 | { | |
1703 | kfree(fuc->data); | |
1704 | fuc->data = NULL; | |
1705 | } | |
1706 | ||
336c4652 AC |
1707 | static void |
1708 | gf100_gr_dtor_init(struct gf100_gr_pack *pack) | |
1709 | { | |
1710 | vfree(pack); | |
1711 | } | |
1712 | ||
c85ee6ca BS |
1713 | void * |
1714 | gf100_gr_dtor(struct nvkm_gr *base) | |
1715 | { | |
1716 | struct gf100_gr *gr = gf100_gr(base); | |
1717 | ||
1718 | if (gr->func->dtor) | |
1719 | gr->func->dtor(gr); | |
1720 | kfree(gr->data); | |
1721 | ||
1722 | gf100_gr_dtor_fw(&gr->fuc409c); | |
1723 | gf100_gr_dtor_fw(&gr->fuc409d); | |
1724 | gf100_gr_dtor_fw(&gr->fuc41ac); | |
1725 | gf100_gr_dtor_fw(&gr->fuc41ad); | |
1726 | ||
336c4652 AC |
1727 | gf100_gr_dtor_init(gr->fuc_bundle); |
1728 | gf100_gr_dtor_init(gr->fuc_method); | |
1729 | gf100_gr_dtor_init(gr->fuc_sw_ctx); | |
1730 | gf100_gr_dtor_init(gr->fuc_sw_nonctx); | |
1731 | ||
c85ee6ca BS |
1732 | nvkm_memory_del(&gr->unk4188b8); |
1733 | nvkm_memory_del(&gr->unk4188b4); | |
1734 | return gr; | |
1735 | } | |
1736 | ||
1737 | static const struct nvkm_gr_func | |
1738 | gf100_gr_ = { | |
1739 | .dtor = gf100_gr_dtor, | |
1740 | .oneinit = gf100_gr_oneinit, | |
1741 | .init = gf100_gr_init_, | |
1742 | .intr = gf100_gr_intr, | |
1743 | .units = gf100_gr_units, | |
1744 | .chan_new = gf100_gr_chan_new, | |
1745 | .object_get = gf100_gr_object_get, | |
1746 | }; | |
1747 | ||
1748 | int | |
1749 | gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, | |
1750 | struct gf100_gr_fuc *fuc) | |
1751 | { | |
1752 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; | |
1753 | struct nvkm_device *device = subdev->device; | |
1754 | const struct firmware *fw; | |
c85ee6ca | 1755 | int ret; |
c85ee6ca | 1756 | |
33bcb4c3 | 1757 | ret = nvkm_firmware_get(device, fwname, &fw); |
c85ee6ca BS |
1758 | if (ret) { |
1759 | nvkm_error(subdev, "failed to load %s\n", fwname); | |
1760 | return ret; | |
1761 | } | |
1762 | ||
1763 | fuc->size = fw->size; | |
1764 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); | |
33bcb4c3 | 1765 | nvkm_firmware_put(fw); |
c85ee6ca BS |
1766 | return (fuc->data != NULL) ? 0 : -ENOMEM; |
1767 | } | |
1768 | ||
1769 | int | |
1770 | gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, | |
1771 | int index, struct gf100_gr *gr) | |
1772 | { | |
1773 | int ret; | |
1774 | ||
1775 | gr->func = func; | |
1776 | gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", | |
1777 | func->fecs.ucode == NULL); | |
1778 | ||
1779 | ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000, | |
1780 | gr->firmware || func->fecs.ucode != NULL, | |
1781 | &gr->base); | |
1782 | if (ret) | |
1783 | return ret; | |
1784 | ||
c85ee6ca BS |
1785 | return 0; |
1786 | } | |
1787 | ||
30f4e087 | 1788 | int |
c85ee6ca BS |
1789 | gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, |
1790 | int index, struct nvkm_gr **pgr) | |
1791 | { | |
1792 | struct gf100_gr *gr; | |
18cd5bc8 AC |
1793 | int ret; |
1794 | ||
c85ee6ca BS |
1795 | if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) |
1796 | return -ENOMEM; | |
1797 | *pgr = &gr->base; | |
18cd5bc8 AC |
1798 | |
1799 | ret = gf100_gr_ctor(func, device, index, gr); | |
1800 | if (ret) | |
1801 | return ret; | |
1802 | ||
1803 | if (gr->firmware) { | |
1804 | if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || | |
1805 | gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || | |
1806 | gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || | |
1807 | gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) | |
1808 | return -ENODEV; | |
1809 | } | |
1810 | ||
1811 | return 0; | |
c85ee6ca BS |
1812 | } |
1813 | ||
1814 | int | |
1815 | gf100_gr_init(struct gf100_gr *gr) | |
4b223eef | 1816 | { |
276836d4 | 1817 | struct nvkm_device *device = gr->base.engine.subdev.device; |
bfee3f3d | 1818 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); |
30f4e087 BS |
1819 | u32 data[TPC_MAX / 8] = {}; |
1820 | u8 tpcnr[GPC_MAX]; | |
1821 | int gpc, tpc, rop; | |
c85ee6ca | 1822 | int i; |
ebb945a9 | 1823 | |
276836d4 BS |
1824 | nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); |
1825 | nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); | |
1826 | nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); | |
1827 | nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); | |
1828 | nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); | |
1829 | nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); | |
227c95d9 BS |
1830 | nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); |
1831 | nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); | |
30f4e087 | 1832 | |
c85ee6ca | 1833 | gf100_gr_mmio(gr, gr->func->mmio); |
30f4e087 | 1834 | |
28dca905 BS |
1835 | nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001); |
1836 | ||
bfee3f3d BS |
1837 | memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); |
1838 | for (i = 0, gpc = -1; i < gr->tpc_total; i++) { | |
30f4e087 | 1839 | do { |
bfee3f3d | 1840 | gpc = (gpc + 1) % gr->gpc_nr; |
30f4e087 | 1841 | } while (!tpcnr[gpc]); |
bfee3f3d | 1842 | tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; |
30f4e087 BS |
1843 | |
1844 | data[i / 8] |= tpc << ((i % 8) * 4); | |
1845 | } | |
1846 | ||
276836d4 BS |
1847 | nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); |
1848 | nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); | |
1849 | nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); | |
1850 | nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); | |
30f4e087 | 1851 | |
bfee3f3d | 1852 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { |
276836d4 | 1853 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), |
bfee3f3d | 1854 | gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); |
276836d4 | 1855 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | |
bfee3f3d | 1856 | gr->tpc_total); |
276836d4 | 1857 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); |
30f4e087 BS |
1858 | } |
1859 | ||
c85ee6ca | 1860 | if (device->chipset != 0xd7) |
276836d4 | 1861 | nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); |
26410c67 | 1862 | else |
276836d4 | 1863 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
bfee3f3d | 1864 | |
276836d4 | 1865 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
bfee3f3d | 1866 | |
276836d4 | 1867 | nvkm_wr32(device, 0x400500, 0x00010001); |
bfee3f3d | 1868 | |
276836d4 BS |
1869 | nvkm_wr32(device, 0x400100, 0xffffffff); |
1870 | nvkm_wr32(device, 0x40013c, 0xffffffff); | |
bfee3f3d | 1871 | |
276836d4 BS |
1872 | nvkm_wr32(device, 0x409c24, 0x000f0000); |
1873 | nvkm_wr32(device, 0x404000, 0xc0000000); | |
1874 | nvkm_wr32(device, 0x404600, 0xc0000000); | |
1875 | nvkm_wr32(device, 0x408030, 0xc0000000); | |
1876 | nvkm_wr32(device, 0x40601c, 0xc0000000); | |
1877 | nvkm_wr32(device, 0x404490, 0xc0000000); | |
1878 | nvkm_wr32(device, 0x406018, 0xc0000000); | |
1879 | nvkm_wr32(device, 0x405840, 0xc0000000); | |
1880 | nvkm_wr32(device, 0x405844, 0x00ffffff); | |
1881 | nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); | |
1882 | nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); | |
bfee3f3d BS |
1883 | |
1884 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { | |
276836d4 BS |
1885 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
1886 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
1887 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
1888 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
bfee3f3d | 1889 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
276836d4 BS |
1890 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); |
1891 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); | |
1892 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); | |
1893 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); | |
1894 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); | |
1895 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); | |
1896 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); | |
30f4e087 | 1897 | } |
276836d4 BS |
1898 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); |
1899 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); | |
30f4e087 BS |
1900 | } |
1901 | ||
bfee3f3d | 1902 | for (rop = 0; rop < gr->rop_nr; rop++) { |
276836d4 BS |
1903 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); |
1904 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); | |
1905 | nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); | |
1906 | nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); | |
30f4e087 | 1907 | } |
ebb945a9 | 1908 | |
276836d4 BS |
1909 | nvkm_wr32(device, 0x400108, 0xffffffff); |
1910 | nvkm_wr32(device, 0x400138, 0xffffffff); | |
1911 | nvkm_wr32(device, 0x400118, 0xffffffff); | |
1912 | nvkm_wr32(device, 0x400130, 0xffffffff); | |
1913 | nvkm_wr32(device, 0x40011c, 0xffffffff); | |
1914 | nvkm_wr32(device, 0x400134, 0xffffffff); | |
30f4e087 | 1915 | |
276836d4 | 1916 | nvkm_wr32(device, 0x400054, 0x34ce3464); |
ac9738bb | 1917 | |
bfee3f3d | 1918 | gf100_gr_zbc_init(gr); |
ac9738bb | 1919 | |
bfee3f3d | 1920 | return gf100_gr_init_ctxctl(gr); |
30f4e087 BS |
1921 | } |
1922 | ||
e3c71eb2 | 1923 | #include "fuc/hubgf100.fuc3.h" |
30f4e087 | 1924 | |
e3c71eb2 BS |
1925 | struct gf100_gr_ucode |
1926 | gf100_gr_fecs_ucode = { | |
1927 | .code.data = gf100_grhub_code, | |
1928 | .code.size = sizeof(gf100_grhub_code), | |
1929 | .data.data = gf100_grhub_data, | |
1930 | .data.size = sizeof(gf100_grhub_data), | |
30f4e087 BS |
1931 | }; |
1932 | ||
e3c71eb2 | 1933 | #include "fuc/gpcgf100.fuc3.h" |
30f4e087 | 1934 | |
e3c71eb2 BS |
1935 | struct gf100_gr_ucode |
1936 | gf100_gr_gpccs_ucode = { | |
1937 | .code.data = gf100_grgpc_code, | |
1938 | .code.size = sizeof(gf100_grgpc_code), | |
1939 | .data.data = gf100_grgpc_data, | |
1940 | .data.size = sizeof(gf100_grgpc_data), | |
30f4e087 BS |
1941 | }; |
1942 | ||
27f3d6cf BS |
1943 | static const struct gf100_gr_func |
1944 | gf100_gr = { | |
c85ee6ca BS |
1945 | .init = gf100_gr_init, |
1946 | .mmio = gf100_gr_pack_mmio, | |
1947 | .fecs.ucode = &gf100_gr_fecs_ucode, | |
1948 | .gpccs.ucode = &gf100_gr_gpccs_ucode, | |
27f3d6cf BS |
1949 | .grctx = &gf100_grctx, |
1950 | .sclass = { | |
1951 | { -1, -1, FERMI_TWOD_A }, | |
1952 | { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, | |
1953 | { -1, -1, FERMI_A, &gf100_fermi }, | |
1954 | { -1, -1, FERMI_COMPUTE_A }, | |
1955 | {} | |
1956 | } | |
1957 | }; | |
1958 | ||
c85ee6ca BS |
1959 | int |
1960 | gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) | |
1961 | { | |
1962 | return gf100_gr_new_(&gf100_gr, device, index, pgr); | |
1963 | } |