Commit | Line | Data |
---|---|---|
6ee73861 | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
6ee73861 | 3 | * |
ebb945a9 BS |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
6ee73861 | 10 | * |
ebb945a9 BS |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. | |
6ee73861 | 13 | * |
ebb945a9 BS |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
6ee73861 | 21 | * |
ebb945a9 | 22 | * Authors: Ben Skeggs |
6ee73861 | 23 | */ |
05c7145d | 24 | #include "nv04.h" |
9a65a38c BS |
25 | #include "channv04.h" |
26 | #include "regsnv04.h" | |
6ee73861 | 27 | |
02a841d4 | 28 | #include <core/ramht.h> |
ebb945a9 | 29 | #include <subdev/fb.h> |
d8e83994 | 30 | #include <subdev/instmem.h> |
ebb945a9 | 31 | |
ebb945a9 BS |
32 | static struct ramfc_desc |
33 | nv40_ramfc[] = { | |
c420b2dc BS |
34 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, |
35 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, | |
36 | { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, | |
37 | { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, | |
38 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, | |
39 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE }, | |
40 | { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, | |
41 | { 2, 28, 0x18, 28, 0x002058 }, | |
42 | { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE }, | |
43 | { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 }, | |
44 | { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, | |
45 | { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, | |
46 | { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, | |
47 | { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, | |
48 | { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, | |
49 | { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE }, | |
50 | { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE }, | |
51 | { 32, 0, 0x40, 0, 0x0032e4 }, | |
52 | { 32, 0, 0x44, 0, 0x0032e8 }, | |
53 | { 32, 0, 0x4c, 0, 0x002088 }, | |
54 | { 32, 0, 0x50, 0, 0x003300 }, | |
55 | { 32, 0, 0x54, 0, 0x00330c }, | |
56 | {} | |
57 | }; | |
58 | ||
05c7145d | 59 | static struct nvkm_oclass |
ebb945a9 BS |
60 | nv40_fifo_cclass = { |
61 | .handle = NV_ENGCTX(FIFO, 0x40), | |
05c7145d | 62 | .ofuncs = &(struct nvkm_ofuncs) { |
ebb945a9 | 63 | .ctor = nv04_fifo_context_ctor, |
05c7145d BS |
64 | .dtor = _nvkm_fifo_context_dtor, |
65 | .init = _nvkm_fifo_context_init, | |
66 | .fini = _nvkm_fifo_context_fini, | |
67 | .rd32 = _nvkm_fifo_context_rd32, | |
68 | .wr32 = _nvkm_fifo_context_wr32, | |
ebb945a9 BS |
69 | }, |
70 | }; | |
6ee73861 | 71 | |
c420b2dc | 72 | static int |
05c7145d | 73 | nv40_fifo_init(struct nvkm_object *object) |
6ee73861 | 74 | { |
6189f1b0 | 75 | struct nv04_fifo *fifo = (void *)object; |
87744403 BS |
76 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
77 | struct nvkm_fb *fb = device->fb; | |
5b1ab0c2 BS |
78 | struct nvkm_instmem *imem = device->imem; |
79 | struct nvkm_ramht *ramht = imem->ramht; | |
80 | struct nvkm_memory *ramro = imem->ramro; | |
81 | struct nvkm_memory *ramfc = imem->ramfc; | |
ebb945a9 | 82 | int ret; |
6ee73861 | 83 | |
6189f1b0 | 84 | ret = nvkm_fifo_init(&fifo->base); |
ebb945a9 BS |
85 | if (ret) |
86 | return ret; | |
6ee73861 | 87 | |
87744403 BS |
88 | nvkm_wr32(device, 0x002040, 0x000000ff); |
89 | nvkm_wr32(device, 0x002044, 0x2101ffff); | |
90 | nvkm_wr32(device, 0x002058, 0x00000001); | |
6ee73861 | 91 | |
87744403 | 92 | nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | |
5b1ab0c2 | 93 | ((ramht->bits - 9) << 16) | |
1d2a1e53 | 94 | (ramht->gpuobj->addr >> 8)); |
5b1ab0c2 | 95 | nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); |
6ee73861 | 96 | |
6189f1b0 | 97 | switch (nv_device(fifo)->chipset) { |
6ee73861 BS |
98 | case 0x47: |
99 | case 0x49: | |
100 | case 0x4b: | |
87744403 | 101 | nvkm_wr32(device, 0x002230, 0x00000001); |
6ee73861 BS |
102 | case 0x40: |
103 | case 0x41: | |
104 | case 0x42: | |
105 | case 0x43: | |
106 | case 0x45: | |
6ee73861 | 107 | case 0x48: |
87744403 | 108 | nvkm_wr32(device, 0x002220, 0x00030002); |
6ee73861 BS |
109 | break; |
110 | default: | |
87744403 BS |
111 | nvkm_wr32(device, 0x002230, 0x00000000); |
112 | nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 + | |
5b1ab0c2 BS |
113 | nvkm_memory_addr(ramfc)) >> 16) | |
114 | 0x00030000); | |
6ee73861 BS |
115 | break; |
116 | } | |
6ee73861 | 117 | |
87744403 | 118 | nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); |
6ee73861 | 119 | |
87744403 BS |
120 | nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); |
121 | nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); | |
6ee73861 | 122 | |
87744403 BS |
123 | nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); |
124 | nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); | |
125 | nvkm_wr32(device, NV03_PFIFO_CACHES, 1); | |
6ee73861 BS |
126 | return 0; |
127 | } | |
c420b2dc | 128 | |
9a65a38c BS |
129 | static int |
130 | nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, | |
131 | struct nvkm_oclass *oclass, void *data, u32 size, | |
132 | struct nvkm_object **pobject) | |
133 | { | |
134 | struct nv04_fifo *fifo; | |
135 | int ret; | |
136 | ||
137 | ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); | |
138 | *pobject = nv_object(fifo); | |
139 | if (ret) | |
140 | return ret; | |
141 | ||
142 | nv_subdev(fifo)->unit = 0x00000100; | |
143 | nv_subdev(fifo)->intr = nv04_fifo_intr; | |
144 | nv_engine(fifo)->cclass = &nv40_fifo_cclass; | |
145 | nv_engine(fifo)->sclass = nv40_fifo_sclass; | |
146 | fifo->base.pause = nv04_fifo_pause; | |
147 | fifo->base.start = nv04_fifo_start; | |
148 | fifo->ramfc_desc = nv40_ramfc; | |
149 | return 0; | |
150 | } | |
151 | ||
05c7145d BS |
152 | struct nvkm_oclass * |
153 | nv40_fifo_oclass = &(struct nvkm_oclass) { | |
ebb945a9 | 154 | .handle = NV_ENGINE(FIFO, 0x40), |
05c7145d | 155 | .ofuncs = &(struct nvkm_ofuncs) { |
ebb945a9 BS |
156 | .ctor = nv40_fifo_ctor, |
157 | .dtor = nv04_fifo_dtor, | |
158 | .init = nv40_fifo_init, | |
05c7145d | 159 | .fini = _nvkm_fifo_fini, |
ebb945a9 BS |
160 | }, |
161 | }; |