drm/nouveau/fifo: merge gk104_fifo_func into nvkm_host_func
[linux-block.git] / drivers / gpu / drm / nouveau / nvkm / engine / fifo / gm200.c
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1/*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "gk104.h"
9a65a38c 25#include "changk104.h"
89025bd4 26
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27#include <nvif/class.h>
28
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29int
30gm200_fifo_pbdma_nr(struct gk104_fifo *fifo)
31{
32 struct nvkm_device *device = fifo->base.engine.subdev.device;
33 return nvkm_rd32(device, 0x002004) & 0x000000ff;
34}
35
36const struct gk104_fifo_pbdma_func
37gm200_fifo_pbdma = {
38 .nr = gm200_fifo_pbdma_nr,
39 .init = gk104_fifo_pbdma_init,
40 .init_timeout = gk208_fifo_pbdma_init_timeout,
41};
42
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43int
44gm200_fifo_chid_nr(struct nvkm_fifo *fifo)
45{
46 return nvkm_rd32(fifo->engine.subdev.device, 0x002008);
47}
48
9be9c606 49static const struct nvkm_fifo_func
db1eb528 50gm200_fifo = {
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51 .dtor = gk104_fifo_dtor,
52 .oneinit = gk104_fifo_oneinit,
8c18138c 53 .chid_nr = gm200_fifo_chid_nr,
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54 .info = gk104_fifo_info,
55 .init = gk104_fifo_init,
56 .fini = gk104_fifo_fini,
57 .intr = gk104_fifo_intr,
58 .intr_mmu_fault_unit = gm107_fifo_intr_mmu_fault_unit,
59 .mmu_fault = &gm107_fifo_mmu_fault,
ddc669e2 60 .fault.access = gk104_fifo_fault_access,
0cdc3fdf 61 .fault.engine = gm107_fifo_fault_engine,
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62 .fault.reason = gk104_fifo_fault_reason,
63 .fault.hubclient = gk104_fifo_fault_hubclient,
64 .fault.gpcclient = gk104_fifo_fault_gpcclient,
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65 .engine_id = gk104_fifo_engine_id,
66 .id_engine = gk104_fifo_id_engine,
67 .uevent_init = gk104_fifo_uevent_init,
68 .uevent_fini = gk104_fifo_uevent_fini,
69 .recover_chan = gk104_fifo_recover_chan,
eda12417 70 .runlist = &gm107_fifo_runlist,
9be9c606 71 .pbdma = &gm200_fifo_pbdma,
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72 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp },
73 .chan = {{ 0, 0, MAXWELL_CHANNEL_GPFIFO_A }, &gm107_chan, .ctor = &gk104_fifo_gpfifo_new },
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74};
75
3326060a 76int
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77gm200_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
78 struct nvkm_fifo **pfifo)
89025bd4 79{
8c18138c 80 return gk104_fifo_new_(&gm200_fifo, device, type, inst, 0, pfifo);
89025bd4 81}