Commit | Line | Data |
---|---|---|
ebb945a9 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
878da15a | 24 | #include "nv50.h" |
2a7909c0 | 25 | #include "rootnv50.h" |
ebb945a9 | 26 | |
bf0eb898 | 27 | #include <core/client.h> |
117e1633 | 28 | #include <core/enum.h> |
2a7909c0 | 29 | #include <core/gpuobj.h> |
186ecad2 | 30 | #include <subdev/bios.h> |
186ecad2 BS |
31 | #include <subdev/bios/disp.h> |
32 | #include <subdev/bios/init.h> | |
33 | #include <subdev/bios/pll.h> | |
88524bc0 | 34 | #include <subdev/devinit.h> |
70cabe4a | 35 | |
79ca2770 BS |
36 | static void |
37 | nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head) | |
38 | { | |
878da15a | 39 | struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); |
2fde1f1c BS |
40 | struct nvkm_device *device = disp->engine.subdev.device; |
41 | nvkm_mask(device, 0x61002c, (4 << head), 0); | |
79ca2770 BS |
42 | } |
43 | ||
44 | static void | |
45 | nv50_disp_vblank_init(struct nvkm_event *event, int type, int head) | |
46 | { | |
878da15a | 47 | struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank); |
2fde1f1c BS |
48 | struct nvkm_device *device = disp->engine.subdev.device; |
49 | nvkm_mask(device, 0x61002c, (4 << head), (4 << head)); | |
79ca2770 BS |
50 | } |
51 | ||
52 | const struct nvkm_event_func | |
53 | nv50_disp_vblank_func = { | |
878da15a | 54 | .ctor = nvkm_disp_vblank_ctor, |
79ca2770 BS |
55 | .init = nv50_disp_vblank_init, |
56 | .fini = nv50_disp_vblank_fini, | |
57 | }; | |
58 | ||
878da15a | 59 | static const struct nvkm_enum |
117e1633 BS |
60 | nv50_disp_intr_error_type[] = { |
61 | { 3, "ILLEGAL_MTHD" }, | |
62 | { 4, "INVALID_VALUE" }, | |
63 | { 5, "INVALID_STATE" }, | |
64 | { 7, "INVALID_HANDLE" }, | |
65 | {} | |
66 | }; | |
186ecad2 | 67 | |
878da15a | 68 | static const struct nvkm_enum |
117e1633 BS |
69 | nv50_disp_intr_error_code[] = { |
70 | { 0x00, "" }, | |
71 | {} | |
72 | }; | |
186ecad2 | 73 | |
117e1633 | 74 | static void |
fd166a18 | 75 | nv50_disp_intr_error(struct nv50_disp *disp, int chid) |
117e1633 | 76 | { |
84407824 BS |
77 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
78 | struct nvkm_device *device = subdev->device; | |
2fde1f1c BS |
79 | u32 data = nvkm_rd32(device, 0x610084 + (chid * 0x08)); |
80 | u32 addr = nvkm_rd32(device, 0x610080 + (chid * 0x08)); | |
117e1633 BS |
81 | u32 code = (addr & 0x00ff0000) >> 16; |
82 | u32 type = (addr & 0x00007000) >> 12; | |
83 | u32 mthd = (addr & 0x00000ffc); | |
878da15a | 84 | const struct nvkm_enum *ec, *et; |
117e1633 | 85 | |
878da15a | 86 | et = nvkm_enum_find(nv50_disp_intr_error_type, type); |
878da15a | 87 | ec = nvkm_enum_find(nv50_disp_intr_error_code, code); |
117e1633 | 88 | |
84407824 BS |
89 | nvkm_error(subdev, |
90 | "ERROR %d [%s] %02x [%s] chid %d mthd %04x data %08x\n", | |
91 | type, et ? et->name : "", code, ec ? ec->name : "", | |
92 | chid, mthd, data); | |
117e1633 | 93 | |
0ce41e3c | 94 | if (chid < ARRAY_SIZE(disp->chan)) { |
9cf6ba20 BS |
95 | switch (mthd) { |
96 | case 0x0080: | |
0ce41e3c | 97 | nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR); |
9cf6ba20 BS |
98 | break; |
99 | default: | |
100 | break; | |
101 | } | |
102 | } | |
103 | ||
2fde1f1c BS |
104 | nvkm_wr32(device, 0x610020, 0x00010000 << chid); |
105 | nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000); | |
186ecad2 BS |
106 | } |
107 | ||
415f12ef | 108 | static struct nvkm_output * |
fd166a18 | 109 | exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, |
415f12ef | 110 | u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
186ecad2 BS |
111 | struct nvbios_outp *info) |
112 | { | |
84407824 BS |
113 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
114 | struct nvkm_bios *bios = subdev->device->bios; | |
415f12ef BS |
115 | struct nvkm_output *outp; |
116 | u16 mask, type; | |
186ecad2 | 117 | |
415f12ef | 118 | if (or < 4) { |
186ecad2 BS |
119 | type = DCB_OUTPUT_ANALOG; |
120 | mask = 0; | |
476e84e1 | 121 | } else |
415f12ef | 122 | if (or < 8) { |
186ecad2 BS |
123 | switch (ctrl & 0x00000f00) { |
124 | case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; | |
125 | case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; | |
126 | case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; | |
127 | case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; | |
128 | case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; | |
129 | case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; | |
130 | default: | |
84407824 | 131 | nvkm_error(subdev, "unknown SOR mc %08x\n", ctrl); |
415f12ef | 132 | return NULL; |
186ecad2 | 133 | } |
415f12ef | 134 | or -= 4; |
476e84e1 | 135 | } else { |
415f12ef | 136 | or = or - 8; |
476e84e1 BS |
137 | type = 0x0010; |
138 | mask = 0; | |
139 | switch (ctrl & 0x00000f00) { | |
fd166a18 | 140 | case 0x00000000: type |= disp->pior.type[or]; break; |
476e84e1 | 141 | default: |
84407824 | 142 | nvkm_error(subdev, "unknown PIOR mc %08x\n", ctrl); |
415f12ef | 143 | return NULL; |
476e84e1 | 144 | } |
186ecad2 BS |
145 | } |
146 | ||
147 | mask = 0x00c0 & (mask << 6); | |
415f12ef | 148 | mask |= 0x0001 << or; |
186ecad2 BS |
149 | mask |= 0x0100 << head; |
150 | ||
fd166a18 | 151 | list_for_each_entry(outp, &disp->base.outp, head) { |
415f12ef BS |
152 | if ((outp->info.hasht & 0xff) == type && |
153 | (outp->info.hashm & mask) == mask) { | |
154 | *data = nvbios_outp_match(bios, outp->info.hasht, | |
155 | outp->info.hashm, | |
156 | ver, hdr, cnt, len, info); | |
157 | if (!*data) | |
158 | return NULL; | |
159 | return outp; | |
160 | } | |
161 | } | |
476e84e1 | 162 | |
415f12ef | 163 | return NULL; |
186ecad2 BS |
164 | } |
165 | ||
1ae5a62b | 166 | static struct nvkm_output * |
fd166a18 | 167 | exec_script(struct nv50_disp *disp, int head, int id) |
186ecad2 | 168 | { |
2fde1f1c BS |
169 | struct nvkm_device *device = disp->base.engine.subdev.device; |
170 | struct nvkm_bios *bios = device->bios; | |
415f12ef | 171 | struct nvkm_output *outp; |
186ecad2 | 172 | struct nvbios_outp info; |
186ecad2 | 173 | u8 ver, hdr, cnt, len; |
415f12ef | 174 | u32 data, ctrl = 0; |
b969fa52 | 175 | u32 reg; |
186ecad2 BS |
176 | int i; |
177 | ||
476e84e1 | 178 | /* DAC */ |
fd166a18 | 179 | for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++) |
2fde1f1c | 180 | ctrl = nvkm_rd32(device, 0x610b5c + (i * 8)); |
186ecad2 | 181 | |
476e84e1 | 182 | /* SOR */ |
c684cef7 | 183 | if (!(ctrl & (1 << head))) { |
fd166a18 BS |
184 | if (nv_device(disp)->chipset < 0x90 || |
185 | nv_device(disp)->chipset == 0x92 || | |
186 | nv_device(disp)->chipset == 0xa0) { | |
b969fa52 | 187 | reg = 0x610b74; |
c684cef7 | 188 | } else { |
b969fa52 | 189 | reg = 0x610798; |
c684cef7 | 190 | } |
fd166a18 | 191 | for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++) |
2fde1f1c | 192 | ctrl = nvkm_rd32(device, reg + (i * 8)); |
b969fa52 | 193 | i += 4; |
186ecad2 BS |
194 | } |
195 | ||
476e84e1 BS |
196 | /* PIOR */ |
197 | if (!(ctrl & (1 << head))) { | |
fd166a18 | 198 | for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++) |
2fde1f1c | 199 | ctrl = nvkm_rd32(device, 0x610b84 + (i * 8)); |
476e84e1 BS |
200 | i += 8; |
201 | } | |
202 | ||
186ecad2 | 203 | if (!(ctrl & (1 << head))) |
1ae5a62b | 204 | return NULL; |
c684cef7 | 205 | i--; |
186ecad2 | 206 | |
fd166a18 | 207 | outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); |
415f12ef | 208 | if (outp) { |
186ecad2 | 209 | struct nvbios_init init = { |
fd166a18 | 210 | .subdev = nv_subdev(disp), |
186ecad2 BS |
211 | .bios = bios, |
212 | .offset = info.script[id], | |
415f12ef | 213 | .outp = &outp->info, |
186ecad2 BS |
214 | .crtc = head, |
215 | .execute = 1, | |
216 | }; | |
217 | ||
1ae5a62b | 218 | nvbios_exec(&init); |
186ecad2 BS |
219 | } |
220 | ||
1ae5a62b | 221 | return outp; |
186ecad2 BS |
222 | } |
223 | ||
415f12ef | 224 | static struct nvkm_output * |
fd166a18 | 225 | exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) |
186ecad2 | 226 | { |
2fde1f1c BS |
227 | struct nvkm_device *device = disp->base.engine.subdev.device; |
228 | struct nvkm_bios *bios = device->bios; | |
415f12ef | 229 | struct nvkm_output *outp; |
186ecad2 BS |
230 | struct nvbios_outp info1; |
231 | struct nvbios_ocfg info2; | |
232 | u8 ver, hdr, cnt, len; | |
415f12ef | 233 | u32 data, ctrl = 0; |
b969fa52 | 234 | u32 reg; |
186ecad2 BS |
235 | int i; |
236 | ||
476e84e1 | 237 | /* DAC */ |
fd166a18 | 238 | for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++) |
2fde1f1c | 239 | ctrl = nvkm_rd32(device, 0x610b58 + (i * 8)); |
186ecad2 | 240 | |
476e84e1 | 241 | /* SOR */ |
c684cef7 | 242 | if (!(ctrl & (1 << head))) { |
fd166a18 BS |
243 | if (nv_device(disp)->chipset < 0x90 || |
244 | nv_device(disp)->chipset == 0x92 || | |
245 | nv_device(disp)->chipset == 0xa0) { | |
b969fa52 | 246 | reg = 0x610b70; |
c684cef7 | 247 | } else { |
b969fa52 | 248 | reg = 0x610794; |
c684cef7 | 249 | } |
fd166a18 | 250 | for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++) |
2fde1f1c | 251 | ctrl = nvkm_rd32(device, reg + (i * 8)); |
b969fa52 | 252 | i += 4; |
186ecad2 BS |
253 | } |
254 | ||
476e84e1 BS |
255 | /* PIOR */ |
256 | if (!(ctrl & (1 << head))) { | |
fd166a18 | 257 | for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++) |
2fde1f1c | 258 | ctrl = nvkm_rd32(device, 0x610b80 + (i * 8)); |
476e84e1 BS |
259 | i += 8; |
260 | } | |
261 | ||
186ecad2 | 262 | if (!(ctrl & (1 << head))) |
415f12ef | 263 | return NULL; |
c684cef7 | 264 | i--; |
186ecad2 | 265 | |
fd166a18 | 266 | outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); |
ba5e01b0 | 267 | if (!outp) |
415f12ef | 268 | return NULL; |
186ecad2 | 269 | |
415f12ef BS |
270 | if (outp->info.location == 0) { |
271 | switch (outp->info.type) { | |
476e84e1 | 272 | case DCB_OUTPUT_TMDS: |
415f12ef | 273 | *conf = (ctrl & 0x00000f00) >> 8; |
476e84e1 | 274 | if (pclk >= 165000) |
415f12ef | 275 | *conf |= 0x0100; |
476e84e1 BS |
276 | break; |
277 | case DCB_OUTPUT_LVDS: | |
fd166a18 | 278 | *conf = disp->sor.lvdsconf; |
476e84e1 BS |
279 | break; |
280 | case DCB_OUTPUT_DP: | |
415f12ef | 281 | *conf = (ctrl & 0x00000f00) >> 8; |
476e84e1 BS |
282 | break; |
283 | case DCB_OUTPUT_ANALOG: | |
284 | default: | |
415f12ef | 285 | *conf = 0x00ff; |
476e84e1 BS |
286 | break; |
287 | } | |
288 | } else { | |
415f12ef | 289 | *conf = (ctrl & 0x00000f00) >> 8; |
476e84e1 | 290 | pclk = pclk / 2; |
186ecad2 BS |
291 | } |
292 | ||
415f12ef | 293 | data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2); |
0a0afd28 | 294 | if (data && id < 0xff) { |
186ecad2 BS |
295 | data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); |
296 | if (data) { | |
297 | struct nvbios_init init = { | |
fd166a18 | 298 | .subdev = nv_subdev(disp), |
186ecad2 BS |
299 | .bios = bios, |
300 | .offset = data, | |
415f12ef | 301 | .outp = &outp->info, |
186ecad2 BS |
302 | .crtc = head, |
303 | .execute = 1, | |
304 | }; | |
305 | ||
46c13c13 | 306 | nvbios_exec(&init); |
186ecad2 BS |
307 | } |
308 | } | |
309 | ||
415f12ef | 310 | return outp; |
186ecad2 BS |
311 | } |
312 | ||
313 | static void | |
fd166a18 | 314 | nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head) |
186ecad2 | 315 | { |
fd166a18 | 316 | exec_script(disp, head, 1); |
16d4c031 | 317 | } |
186ecad2 | 318 | |
16d4c031 | 319 | static void |
fd166a18 | 320 | nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head) |
16d4c031 | 321 | { |
46484438 | 322 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
fd166a18 | 323 | struct nvkm_output *outp = exec_script(disp, head, 2); |
1ae5a62b BS |
324 | |
325 | /* the binary driver does this outside of the supervisor handling | |
326 | * (after the third supervisor from a detach). we (currently?) | |
327 | * allow both detach/attach to happen in the same set of | |
328 | * supervisor interrupts, so it would make sense to execute this | |
329 | * (full power down?) script after all the detach phases of the | |
330 | * supervisor handling. like with training if needed from the | |
331 | * second supervisor, nvidia doesn't do this, so who knows if it's | |
332 | * entirely safe, but it does appear to work.. | |
333 | * | |
334 | * without this script being run, on some configurations i've | |
335 | * seen, switching from DP to TMDS on a DP connector may result | |
336 | * in a blank screen (SOR_PWR off/on can restore it) | |
337 | */ | |
338 | if (outp && outp->info.type == DCB_OUTPUT_DP) { | |
f2c906fc | 339 | struct nvkm_output_dp *outpdp = nvkm_output_dp(outp); |
1ae5a62b | 340 | struct nvbios_init init = { |
46484438 BS |
341 | .subdev = subdev, |
342 | .bios = subdev->device->bios, | |
1ae5a62b BS |
343 | .outp = &outp->info, |
344 | .crtc = head, | |
345 | .offset = outpdp->info.script[4], | |
346 | .execute = 1, | |
347 | }; | |
348 | ||
349 | nvbios_exec(&init); | |
350 | atomic_set(&outpdp->lt.done, 0); | |
351 | } | |
186ecad2 BS |
352 | } |
353 | ||
354 | static void | |
fd166a18 | 355 | nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head) |
16d4c031 | 356 | { |
2fde1f1c BS |
357 | struct nvkm_device *device = disp->base.engine.subdev.device; |
358 | struct nvkm_devinit *devinit = device->devinit; | |
359 | u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; | |
16d4c031 | 360 | if (pclk) |
88524bc0 | 361 | devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); |
16d4c031 BS |
362 | } |
363 | ||
364 | static void | |
fd166a18 | 365 | nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, |
16d4c031 | 366 | struct dcb_output *outp, u32 pclk) |
186ecad2 | 367 | { |
84407824 BS |
368 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
369 | struct nvkm_device *device = subdev->device; | |
186ecad2 BS |
370 | const int link = !(outp->sorconf.link & 1); |
371 | const int or = ffs(outp->or) - 1; | |
372 | const u32 soff = ( or * 0x800); | |
373 | const u32 loff = (link * 0x080) + soff; | |
2fde1f1c | 374 | const u32 ctrl = nvkm_rd32(device, 0x610794 + (or * 8)); |
186ecad2 | 375 | const u32 symbol = 100000; |
2fde1f1c BS |
376 | const s32 vactive = nvkm_rd32(device, 0x610af8 + (head * 0x540)) & 0xffff; |
377 | const s32 vblanke = nvkm_rd32(device, 0x610ae8 + (head * 0x540)) & 0xffff; | |
378 | const s32 vblanks = nvkm_rd32(device, 0x610af0 + (head * 0x540)) & 0xffff; | |
379 | u32 dpctrl = nvkm_rd32(device, 0x61c10c + loff); | |
380 | u32 clksor = nvkm_rd32(device, 0x614300 + soff); | |
186ecad2 BS |
381 | int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; |
382 | int TU, VTUi, VTUf, VTUa; | |
383 | u64 link_data_rate, link_ratio, unk; | |
384 | u32 best_diff = 64 * symbol; | |
c354080d | 385 | u32 link_nr, link_bw, bits; |
9506140f BS |
386 | u64 value; |
387 | ||
388 | link_bw = (clksor & 0x000c0000) ? 270000 : 162000; | |
389 | link_nr = hweight32(dpctrl & 0x000f0000); | |
390 | ||
391 | /* symbols/hblank - algorithm taken from comments in tegra driver */ | |
392 | value = vblanke + vactive - vblanks - 7; | |
393 | value = value * link_bw; | |
394 | do_div(value, pclk); | |
395 | value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); | |
2fde1f1c | 396 | nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, value); |
9506140f BS |
397 | |
398 | /* symbols/vblank - algorithm taken from comments in tegra driver */ | |
399 | value = vblanks - vblanke - 25; | |
400 | value = value * link_bw; | |
401 | do_div(value, pclk); | |
402 | value = value - ((36 / link_nr) + 3) - 1; | |
2fde1f1c | 403 | nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, value); |
9506140f BS |
404 | |
405 | /* watermark / activesym */ | |
bf2c886a BS |
406 | if ((ctrl & 0xf0000) == 0x60000) bits = 30; |
407 | else if ((ctrl & 0xf0000) == 0x50000) bits = 24; | |
408 | else bits = 18; | |
409 | ||
186ecad2 BS |
410 | link_data_rate = (pclk * bits / 8) / link_nr; |
411 | ||
412 | /* calculate ratio of packed data rate to link symbol rate */ | |
413 | link_ratio = link_data_rate * symbol; | |
c354080d | 414 | do_div(link_ratio, link_bw); |
186ecad2 BS |
415 | |
416 | for (TU = 64; TU >= 32; TU--) { | |
417 | /* calculate average number of valid symbols in each TU */ | |
418 | u32 tu_valid = link_ratio * TU; | |
419 | u32 calc, diff; | |
420 | ||
421 | /* find a hw representation for the fraction.. */ | |
422 | VTUi = tu_valid / symbol; | |
423 | calc = VTUi * symbol; | |
424 | diff = tu_valid - calc; | |
425 | if (diff) { | |
426 | if (diff >= (symbol / 2)) { | |
427 | VTUf = symbol / (symbol - diff); | |
428 | if (symbol - (VTUf * diff)) | |
429 | VTUf++; | |
430 | ||
431 | if (VTUf <= 15) { | |
432 | VTUa = 1; | |
433 | calc += symbol - (symbol / VTUf); | |
434 | } else { | |
435 | VTUa = 0; | |
436 | VTUf = 1; | |
437 | calc += symbol; | |
438 | } | |
439 | } else { | |
440 | VTUa = 0; | |
441 | VTUf = min((int)(symbol / diff), 15); | |
442 | calc += symbol / VTUf; | |
443 | } | |
444 | ||
445 | diff = calc - tu_valid; | |
446 | } else { | |
447 | /* no remainder, but the hw doesn't like the fractional | |
448 | * part to be zero. decrement the integer part and | |
449 | * have the fraction add a whole symbol back | |
450 | */ | |
451 | VTUa = 0; | |
452 | VTUf = 1; | |
453 | VTUi--; | |
454 | } | |
455 | ||
456 | if (diff < best_diff) { | |
457 | best_diff = diff; | |
458 | bestTU = TU; | |
459 | bestVTUa = VTUa; | |
460 | bestVTUf = VTUf; | |
461 | bestVTUi = VTUi; | |
462 | if (diff == 0) | |
463 | break; | |
464 | } | |
465 | } | |
466 | ||
467 | if (!bestTU) { | |
84407824 | 468 | nvkm_error(subdev, "unable to find suitable dp config\n"); |
186ecad2 BS |
469 | return; |
470 | } | |
471 | ||
472 | /* XXX close to vbios numbers, but not right */ | |
473 | unk = (symbol - link_ratio) * bestTU; | |
474 | unk *= link_ratio; | |
c354080d BS |
475 | do_div(unk, symbol); |
476 | do_div(unk, symbol); | |
186ecad2 BS |
477 | unk += 6; |
478 | ||
2fde1f1c BS |
479 | nvkm_mask(device, 0x61c10c + loff, 0x000001fc, bestTU << 2); |
480 | nvkm_mask(device, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | | |
186ecad2 BS |
481 | bestVTUf << 16 | |
482 | bestVTUi << 8 | unk); | |
483 | } | |
484 | ||
485 | static void | |
fd166a18 | 486 | nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) |
186ecad2 | 487 | { |
2fde1f1c | 488 | struct nvkm_device *device = disp->base.engine.subdev.device; |
415f12ef | 489 | struct nvkm_output *outp; |
2fde1f1c | 490 | u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
16d4c031 BS |
491 | u32 hval, hreg = 0x614200 + (head * 0x800); |
492 | u32 oval, oreg; | |
415f12ef | 493 | u32 mask, conf; |
0a0afd28 | 494 | |
fd166a18 | 495 | outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); |
415f12ef BS |
496 | if (!outp) |
497 | return; | |
186ecad2 | 498 | |
55f083c3 BS |
499 | /* we allow both encoder attach and detach operations to occur |
500 | * within a single supervisor (ie. modeset) sequence. the | |
501 | * encoder detach scripts quite often switch off power to the | |
502 | * lanes, which requires the link to be re-trained. | |
503 | * | |
504 | * this is not generally an issue as the sink "must" (heh) | |
505 | * signal an irq when it's lost sync so the driver can | |
506 | * re-train. | |
507 | * | |
508 | * however, on some boards, if one does not configure at least | |
509 | * the gpu side of the link *before* attaching, then various | |
510 | * things can go horribly wrong (PDISP disappearing from mmio, | |
511 | * third supervisor never happens, etc). | |
512 | * | |
513 | * the solution is simply to retrain here, if necessary. last | |
514 | * i checked, the binary driver userspace does not appear to | |
515 | * trigger this situation (it forces an UPDATE between steps). | |
516 | */ | |
b17932c0 | 517 | if (outp->info.type == DCB_OUTPUT_DP) { |
415f12ef | 518 | u32 soff = (ffs(outp->info.or) - 1) * 0x08; |
b17932c0 BS |
519 | u32 ctrl, datarate; |
520 | ||
521 | if (outp->info.location == 0) { | |
2fde1f1c | 522 | ctrl = nvkm_rd32(device, 0x610794 + soff); |
b17932c0 BS |
523 | soff = 1; |
524 | } else { | |
2fde1f1c | 525 | ctrl = nvkm_rd32(device, 0x610b80 + soff); |
b17932c0 BS |
526 | soff = 2; |
527 | } | |
415f12ef BS |
528 | |
529 | switch ((ctrl & 0x000f0000) >> 16) { | |
0713b451 BS |
530 | case 6: datarate = pclk * 30; break; |
531 | case 5: datarate = pclk * 24; break; | |
415f12ef BS |
532 | case 2: |
533 | default: | |
0713b451 | 534 | datarate = pclk * 18; |
415f12ef | 535 | break; |
186ecad2 | 536 | } |
186ecad2 | 537 | |
55f083c3 | 538 | if (nvkm_output_dp_train(outp, datarate / soff, true)) |
f2c906fc | 539 | OUTP_ERR(outp, "link not trained before attach"); |
415f12ef BS |
540 | } |
541 | ||
fd166a18 | 542 | exec_clkcmp(disp, head, 0, pclk, &conf); |
415f12ef BS |
543 | |
544 | if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { | |
545 | oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; | |
546 | oval = 0x00000000; | |
547 | hval = 0x00000000; | |
548 | mask = 0xffffffff; | |
549 | } else | |
550 | if (!outp->info.location) { | |
551 | if (outp->info.type == DCB_OUTPUT_DP) | |
fd166a18 | 552 | nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk); |
415f12ef BS |
553 | oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; |
554 | oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; | |
555 | hval = 0x00000000; | |
556 | mask = 0x00000707; | |
557 | } else { | |
558 | oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800; | |
559 | oval = 0x00000001; | |
560 | hval = 0x00000001; | |
561 | mask = 0x00000707; | |
16d4c031 | 562 | } |
415f12ef | 563 | |
2fde1f1c BS |
564 | nvkm_mask(device, hreg, 0x0000000f, hval); |
565 | nvkm_mask(device, oreg, mask, oval); | |
186ecad2 BS |
566 | } |
567 | ||
568 | /* If programming a TMDS output on a SOR that can also be configured for | |
569 | * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. | |
570 | * | |
571 | * It looks like the VBIOS TMDS scripts make an attempt at this, however, | |
572 | * the VBIOS scripts on at least one board I have only switch it off on | |
573 | * link 0, causing a blank display if the output has previously been | |
574 | * programmed for DisplayPort. | |
575 | */ | |
576 | static void | |
fd166a18 | 577 | nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp, |
878da15a | 578 | struct dcb_output *outp) |
186ecad2 | 579 | { |
2fde1f1c BS |
580 | struct nvkm_device *device = disp->base.engine.subdev.device; |
581 | struct nvkm_bios *bios = device->bios; | |
186ecad2 BS |
582 | const int link = !(outp->sorconf.link & 1); |
583 | const int or = ffs(outp->or) - 1; | |
584 | const u32 loff = (or * 0x800) + (link * 0x80); | |
585 | const u16 mask = (outp->sorconf.link << 6) | outp->or; | |
5838ae61 | 586 | struct dcb_output match; |
186ecad2 BS |
587 | u8 ver, hdr; |
588 | ||
5838ae61 | 589 | if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) |
2fde1f1c | 590 | nvkm_mask(device, 0x61c10c + loff, 0x00000001, 0x00000000); |
186ecad2 BS |
591 | } |
592 | ||
593 | static void | |
fd166a18 | 594 | nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head) |
186ecad2 | 595 | { |
2fde1f1c | 596 | struct nvkm_device *device = disp->base.engine.subdev.device; |
415f12ef | 597 | struct nvkm_output *outp; |
2fde1f1c | 598 | u32 pclk = nvkm_rd32(device, 0x610ad0 + (head * 0x540)) & 0x3fffff; |
415f12ef | 599 | u32 conf; |
16d4c031 | 600 | |
fd166a18 | 601 | outp = exec_clkcmp(disp, head, 1, pclk, &conf); |
415f12ef BS |
602 | if (!outp) |
603 | return; | |
604 | ||
605 | if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) | |
fd166a18 | 606 | nv50_disp_intr_unk40_0_tmds(disp, &outp->info); |
186ecad2 BS |
607 | } |
608 | ||
5cc027f6 BS |
609 | void |
610 | nv50_disp_intr_supervisor(struct work_struct *work) | |
186ecad2 | 611 | { |
fd166a18 BS |
612 | struct nv50_disp *disp = |
613 | container_of(work, struct nv50_disp, supervisor); | |
84407824 BS |
614 | struct nvkm_subdev *subdev = &disp->base.engine.subdev; |
615 | struct nvkm_device *device = subdev->device; | |
2fde1f1c | 616 | u32 super = nvkm_rd32(device, 0x610030); |
16d4c031 | 617 | int head; |
186ecad2 | 618 | |
84407824 | 619 | nvkm_debug(subdev, "supervisor %08x %08x\n", disp->super, super); |
186ecad2 | 620 | |
fd166a18 | 621 | if (disp->super & 0x00000010) { |
0ce41e3c | 622 | nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); |
fd166a18 | 623 | for (head = 0; head < disp->head.nr; head++) { |
16d4c031 BS |
624 | if (!(super & (0x00000020 << head))) |
625 | continue; | |
626 | if (!(super & (0x00000080 << head))) | |
627 | continue; | |
fd166a18 | 628 | nv50_disp_intr_unk10_0(disp, head); |
16d4c031 BS |
629 | } |
630 | } else | |
fd166a18 BS |
631 | if (disp->super & 0x00000020) { |
632 | for (head = 0; head < disp->head.nr; head++) { | |
16d4c031 BS |
633 | if (!(super & (0x00000080 << head))) |
634 | continue; | |
fd166a18 | 635 | nv50_disp_intr_unk20_0(disp, head); |
16d4c031 | 636 | } |
fd166a18 | 637 | for (head = 0; head < disp->head.nr; head++) { |
16d4c031 BS |
638 | if (!(super & (0x00000200 << head))) |
639 | continue; | |
fd166a18 | 640 | nv50_disp_intr_unk20_1(disp, head); |
16d4c031 | 641 | } |
fd166a18 | 642 | for (head = 0; head < disp->head.nr; head++) { |
16d4c031 BS |
643 | if (!(super & (0x00000080 << head))) |
644 | continue; | |
fd166a18 | 645 | nv50_disp_intr_unk20_2(disp, head); |
16d4c031 BS |
646 | } |
647 | } else | |
fd166a18 BS |
648 | if (disp->super & 0x00000040) { |
649 | for (head = 0; head < disp->head.nr; head++) { | |
16d4c031 BS |
650 | if (!(super & (0x00000080 << head))) |
651 | continue; | |
fd166a18 | 652 | nv50_disp_intr_unk40_0(disp, head); |
16d4c031 BS |
653 | } |
654 | } | |
655 | ||
2fde1f1c | 656 | nvkm_wr32(device, 0x610030, 0x80000000); |
186ecad2 BS |
657 | } |
658 | ||
70cabe4a | 659 | void |
878da15a | 660 | nv50_disp_intr(struct nvkm_subdev *subdev) |
ebb945a9 | 661 | { |
fd166a18 | 662 | struct nv50_disp *disp = (void *)subdev; |
2fde1f1c BS |
663 | struct nvkm_device *device = disp->base.engine.subdev.device; |
664 | u32 intr0 = nvkm_rd32(device, 0x610020); | |
665 | u32 intr1 = nvkm_rd32(device, 0x610024); | |
ebb945a9 | 666 | |
117e1633 BS |
667 | while (intr0 & 0x001f0000) { |
668 | u32 chid = __ffs(intr0 & 0x001f0000) - 16; | |
fd166a18 | 669 | nv50_disp_intr_error(disp, chid); |
117e1633 | 670 | intr0 &= ~(0x00010000 << chid); |
186ecad2 BS |
671 | } |
672 | ||
b38a2322 BS |
673 | while (intr0 & 0x0000001f) { |
674 | u32 chid = __ffs(intr0 & 0x0000001f); | |
fd166a18 | 675 | nv50_disp_chan_uevent_send(disp, chid); |
b38a2322 BS |
676 | intr0 &= ~(0x00000001 << chid); |
677 | } | |
678 | ||
186ecad2 | 679 | if (intr1 & 0x00000004) { |
fd166a18 | 680 | nvkm_disp_vblank(&disp->base, 0); |
2fde1f1c | 681 | nvkm_wr32(device, 0x610024, 0x00000004); |
ebb945a9 BS |
682 | } |
683 | ||
186ecad2 | 684 | if (intr1 & 0x00000008) { |
fd166a18 | 685 | nvkm_disp_vblank(&disp->base, 1); |
2fde1f1c | 686 | nvkm_wr32(device, 0x610024, 0x00000008); |
ebb945a9 BS |
687 | } |
688 | ||
186ecad2 | 689 | if (intr1 & 0x00000070) { |
fd166a18 BS |
690 | disp->super = (intr1 & 0x00000070); |
691 | schedule_work(&disp->supervisor); | |
2fde1f1c | 692 | nvkm_wr32(device, 0x610024, disp->super); |
186ecad2 | 693 | } |
ebb945a9 BS |
694 | } |
695 | ||
0ce41e3c BS |
696 | static const struct nvkm_disp_func |
697 | nv50_disp = { | |
698 | .root = &nv50_disp_root_oclass, | |
699 | }; | |
700 | ||
ebb945a9 | 701 | static int |
878da15a BS |
702 | nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
703 | struct nvkm_oclass *oclass, void *data, u32 size, | |
704 | struct nvkm_object **pobject) | |
ebb945a9 | 705 | { |
fd166a18 | 706 | struct nv50_disp *disp; |
ebb945a9 BS |
707 | int ret; |
708 | ||
878da15a | 709 | ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", |
fd166a18 BS |
710 | "display", &disp); |
711 | *pobject = nv_object(disp); | |
ebb945a9 BS |
712 | if (ret) |
713 | return ret; | |
714 | ||
0ce41e3c BS |
715 | disp->base.func = &nv50_disp; |
716 | ||
fd166a18 | 717 | ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent); |
b38a2322 BS |
718 | if (ret) |
719 | return ret; | |
720 | ||
fd166a18 BS |
721 | nv_subdev(disp)->intr = nv50_disp_intr; |
722 | INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor); | |
fd166a18 BS |
723 | disp->head.nr = 2; |
724 | disp->dac.nr = 3; | |
725 | disp->sor.nr = 2; | |
726 | disp->pior.nr = 3; | |
727 | disp->dac.power = nv50_dac_power; | |
728 | disp->dac.sense = nv50_dac_sense; | |
729 | disp->sor.power = nv50_sor_power; | |
730 | disp->pior.power = nv50_pior_power; | |
ebb945a9 BS |
731 | return 0; |
732 | } | |
733 | ||
878da15a | 734 | struct nvkm_oclass * |
a8f8b489 BS |
735 | nv50_disp_oclass = &(struct nv50_disp_impl) { |
736 | .base.base.handle = NV_ENGINE(DISP, 0x50), | |
878da15a | 737 | .base.base.ofuncs = &(struct nvkm_ofuncs) { |
ebb945a9 | 738 | .ctor = nv50_disp_ctor, |
878da15a BS |
739 | .dtor = _nvkm_disp_dtor, |
740 | .init = _nvkm_disp_init, | |
741 | .fini = _nvkm_disp_fini, | |
ebb945a9 | 742 | }, |
f2c906fc BS |
743 | .base.outp.internal.crt = nv50_dac_output_new, |
744 | .base.outp.internal.tmds = nv50_sor_output_new, | |
745 | .base.outp.internal.lvds = nv50_sor_output_new, | |
746 | .base.outp.external.tmds = nv50_pior_output_new, | |
747 | .base.outp.external.dp = nv50_pior_dp_new, | |
79ca2770 | 748 | .base.vblank = &nv50_disp_vblank_func, |
2a7909c0 | 749 | .head.scanoutpos = nv50_disp_root_scanoutpos, |
a8f8b489 | 750 | }.base.base; |