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Merge tag 'for-linux-6.12-ofs1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / base.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
9719047b
BS		 24#include "priv.h"
25#include "acpi.h"
9274f4a9 26
a1bfb29a 27#include <core/option.h>
d01c3092 28
a1bfb29a 29#include <subdev/bios.h>
b138eca6 30#include <subdev/therm.h>
9274f4a9
BS		 31
32static DEFINE_MUTEX(nv_devices_mutex);
33static LIST_HEAD(nv_devices);
34
7974dd1b
BS		 35static struct nvkm_device *
36nvkm_device_find_locked(u64 handle)
9274f4a9 37{
7974dd1b 38 struct nvkm_device *device;
9274f4a9 39 list_for_each_entry(device, &nv_devices, head) {
7974dd1b
BS		 40 if (device->handle == handle)
41 return device;
9274f4a9 42 }
7974dd1b
BS		 43 return NULL;
44}
45
46struct nvkm_device *
47nvkm_device_find(u64 handle)
48{
49 struct nvkm_device *device;
50 mutex_lock(&nv_devices_mutex);
51 device = nvkm_device_find_locked(handle);
9274f4a9 52 mutex_unlock(&nv_devices_mutex);
7974dd1b 53 return device;
9274f4a9
BS		 54}
55
6cf813fb
BS		 56static const struct nvkm_device_chip
57nv4_chipset = {
58 .name = "NV04",
e07f50d3 59 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 60 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 61 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 62 .devinit = { 0x00000001, nv04_devinit_new },
b7a9369a 63 .fb = { 0x00000001, nv04_fb_new },
c6ce0861 64 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 65 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 66 .mc = { 0x00000001, nv04_mc_new },
6dd123ba 67 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 68 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 69 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 70 .disp = { 0x00000001, nv04_disp_new },
09f409d7 71 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 72 .fifo = { 0x00000001, nv04_fifo_new },
864d37c3 73 .gr = { 0x00000001, nv04_gr_new },
8d6461d8 74 .sw = { 0x00000001, nv04_sw_new },
6cf813fb
BS		 75};
76
77static const struct nvkm_device_chip
78nv5_chipset = {
79 .name = "NV05",
e07f50d3 80 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 81 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 82 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 83 .devinit = { 0x00000001, nv05_devinit_new },
b7a9369a 84 .fb = { 0x00000001, nv04_fb_new },
c6ce0861 85 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 86 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 87 .mc = { 0x00000001, nv04_mc_new },
6dd123ba 88 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 89 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 90 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 91 .disp = { 0x00000001, nv04_disp_new },
09f409d7 92 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 93 .fifo = { 0x00000001, nv04_fifo_new },
864d37c3 94 .gr = { 0x00000001, nv04_gr_new },
8d6461d8 95 .sw = { 0x00000001, nv04_sw_new },
6cf813fb
BS		 96};
97
98static const struct nvkm_device_chip
99nv10_chipset = {
100 .name = "NV10",
e07f50d3 101 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 102 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 103 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 104 .devinit = { 0x00000001, nv10_devinit_new },
b7a9369a 105 .fb = { 0x00000001, nv10_fb_new },
01055c01 106 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 107 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 108 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 109 .mc = { 0x00000001, nv04_mc_new },
6dd123ba 110 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 111 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 112 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 113 .disp = { 0x00000001, nv04_disp_new },
09f409d7 114 .dma = { 0x00000001, nv04_dma_new },
864d37c3 115 .gr = { 0x00000001, nv10_gr_new },
6cf813fb
BS		 116};
117
118static const struct nvkm_device_chip
119nv11_chipset = {
120 .name = "NV11",
e07f50d3 121 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 122 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 123 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 124 .devinit = { 0x00000001, nv10_devinit_new },
b7a9369a 125 .fb = { 0x00000001, nv10_fb_new },
01055c01 126 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 127 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 128 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 129 .mc = { 0x00000001, nv11_mc_new },
6dd123ba 130 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 131 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 132 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 133 .disp = { 0x00000001, nv04_disp_new },
09f409d7 134 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 135 .fifo = { 0x00000001, nv10_fifo_new },
864d37c3 136 .gr = { 0x00000001, nv15_gr_new },
8d6461d8 137 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 138};
139
140static const struct nvkm_device_chip
141nv15_chipset = {
142 .name = "NV15",
e07f50d3 143 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 144 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 145 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 146 .devinit = { 0x00000001, nv10_devinit_new },
b7a9369a 147 .fb = { 0x00000001, nv10_fb_new },
01055c01 148 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 149 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 150 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 151 .mc = { 0x00000001, nv04_mc_new },
6dd123ba 152 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 153 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 154 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 155 .disp = { 0x00000001, nv04_disp_new },
09f409d7 156 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 157 .fifo = { 0x00000001, nv10_fifo_new },
864d37c3 158 .gr = { 0x00000001, nv15_gr_new },
8d6461d8 159 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 160};
161
162static const struct nvkm_device_chip
163nv17_chipset = {
164 .name = "NV17",
e07f50d3 165 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 166 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 167 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 168 .devinit = { 0x00000001, nv10_devinit_new },
b7a9369a 169 .fb = { 0x00000001, nv10_fb_new },
01055c01 170 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 171 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 172 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 173 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 174 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 175 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 176 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 177 .disp = { 0x00000001, nv04_disp_new },
09f409d7 178 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 179 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 180 .gr = { 0x00000001, nv17_gr_new },
8d6461d8 181 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 182};
183
184static const struct nvkm_device_chip
185nv18_chipset = {
186 .name = "NV18",
e07f50d3 187 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 188 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 189 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 190 .devinit = { 0x00000001, nv10_devinit_new },
b7a9369a 191 .fb = { 0x00000001, nv10_fb_new },
01055c01 192 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 193 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 194 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 195 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 196 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 197 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 198 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 199 .disp = { 0x00000001, nv04_disp_new },
09f409d7 200 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 201 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 202 .gr = { 0x00000001, nv17_gr_new },
8d6461d8 203 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 204};
205
206static const struct nvkm_device_chip
207nv1a_chipset = {
208 .name = "nForce",
e07f50d3 209 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 210 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 211 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 212 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 213 .fb = { 0x00000001, nv1a_fb_new },
01055c01 214 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 215 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 216 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 217 .mc = { 0x00000001, nv04_mc_new },
6dd123ba 218 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 219 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 220 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 221 .disp = { 0x00000001, nv04_disp_new },
09f409d7 222 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 223 .fifo = { 0x00000001, nv10_fifo_new },
864d37c3 224 .gr = { 0x00000001, nv15_gr_new },
8d6461d8 225 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 226};
227
228static const struct nvkm_device_chip
229nv1f_chipset = {
230 .name = "nForce2",
e07f50d3 231 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 232 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 233 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 234 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 235 .fb = { 0x00000001, nv1a_fb_new },
01055c01 236 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 237 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 238 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 239 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 240 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 241 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 242 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 243 .disp = { 0x00000001, nv04_disp_new },
09f409d7 244 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 245 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 246 .gr = { 0x00000001, nv17_gr_new },
8d6461d8 247 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 248};
249
250static const struct nvkm_device_chip
251nv20_chipset = {
252 .name = "NV20",
e07f50d3 253 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 254 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 255 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 256 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 257 .fb = { 0x00000001, nv20_fb_new },
01055c01 258 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 259 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 260 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 261 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 262 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 263 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 264 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 265 .disp = { 0x00000001, nv04_disp_new },
09f409d7 266 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 267 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 268 .gr = { 0x00000001, nv20_gr_new },
8d6461d8 269 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 270};
271
272static const struct nvkm_device_chip
273nv25_chipset = {
274 .name = "NV25",
e07f50d3 275 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 276 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 277 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 278 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 279 .fb = { 0x00000001, nv25_fb_new },
01055c01 280 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 281 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 282 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 283 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 284 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 285 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 286 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 287 .disp = { 0x00000001, nv04_disp_new },
09f409d7 288 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 289 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 290 .gr = { 0x00000001, nv25_gr_new },
8d6461d8 291 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 292};
293
294static const struct nvkm_device_chip
295nv28_chipset = {
296 .name = "NV28",
e07f50d3 297 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 298 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 299 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 300 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 301 .fb = { 0x00000001, nv25_fb_new },
01055c01 302 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 303 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 304 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 305 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 306 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 307 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 308 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 309 .disp = { 0x00000001, nv04_disp_new },
09f409d7 310 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 311 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 312 .gr = { 0x00000001, nv25_gr_new },
8d6461d8 313 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 314};
315
316static const struct nvkm_device_chip
317nv2a_chipset = {
318 .name = "NV2A",
e07f50d3 319 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 320 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 321 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 322 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 323 .fb = { 0x00000001, nv25_fb_new },
01055c01 324 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 325 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 326 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 327 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 328 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 329 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 330 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 331 .disp = { 0x00000001, nv04_disp_new },
09f409d7 332 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 333 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 334 .gr = { 0x00000001, nv2a_gr_new },
8d6461d8 335 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 336};
337
338static const struct nvkm_device_chip
339nv30_chipset = {
340 .name = "NV30",
e07f50d3 341 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 342 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 343 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 344 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 345 .fb = { 0x00000001, nv30_fb_new },
01055c01 346 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 347 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 348 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 349 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 350 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 351 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 352 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 353 .disp = { 0x00000001, nv04_disp_new },
09f409d7 354 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 355 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 356 .gr = { 0x00000001, nv30_gr_new },
8d6461d8 357 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 358};
359
360static const struct nvkm_device_chip
361nv31_chipset = {
362 .name = "NV31",
e07f50d3 363 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 364 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 365 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 366 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 367 .fb = { 0x00000001, nv30_fb_new },
01055c01 368 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 369 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 370 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 371 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 372 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 373 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 374 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 375 .disp = { 0x00000001, nv04_disp_new },
09f409d7 376 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 377 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 378 .gr = { 0x00000001, nv30_gr_new },
e5e95a76 379 .mpeg = { 0x00000001, nv31_mpeg_new },
8d6461d8 380 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 381};
382
383static const struct nvkm_device_chip
384nv34_chipset = {
385 .name = "NV34",
e07f50d3 386 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 387 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 388 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 389 .devinit = { 0x00000001, nv10_devinit_new },
b7a9369a 390 .fb = { 0x00000001, nv10_fb_new },
01055c01 391 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 392 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 393 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 394 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 395 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 396 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 397 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 398 .disp = { 0x00000001, nv04_disp_new },
09f409d7 399 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 400 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 401 .gr = { 0x00000001, nv34_gr_new },
e5e95a76 402 .mpeg = { 0x00000001, nv31_mpeg_new },
8d6461d8 403 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 404};
405
406static const struct nvkm_device_chip
407nv35_chipset = {
408 .name = "NV35",
e07f50d3 409 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 410 .bus = { 0x00000001, nv04_bus_new },
98fd7f83 411 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 412 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 413 .fb = { 0x00000001, nv35_fb_new },
01055c01 414 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 415 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 416 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 417 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 418 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 419 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 420 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 421 .disp = { 0x00000001, nv04_disp_new },
09f409d7 422 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 423 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 424 .gr = { 0x00000001, nv35_gr_new },
8d6461d8 425 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 426};
427
428static const struct nvkm_device_chip
429nv36_chipset = {
430 .name = "NV36",
e07f50d3 431 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 432 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 433 .clk = { 0x00000001, nv04_clk_new },
4a34fd0e 434 .devinit = { 0x00000001, nv20_devinit_new },
b7a9369a 435 .fb = { 0x00000001, nv36_fb_new },
01055c01 436 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 437 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 438 .imem = { 0x00000001, nv04_instmem_new },
1fc2fddf 439 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 440 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 441 .pci = { 0x00000001, nv04_pci_new },
9aad54d5 442 .timer = { 0x00000001, nv04_timer_new },
a7f000ec 443 .disp = { 0x00000001, nv04_disp_new },
09f409d7 444 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 445 .fifo = { 0x00000001, nv17_fifo_new },
864d37c3 446 .gr = { 0x00000001, nv35_gr_new },
e5e95a76 447 .mpeg = { 0x00000001, nv31_mpeg_new },
8d6461d8 448 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 449};
450
451static const struct nvkm_device_chip
452nv40_chipset = {
453 .name = "NV40",
e07f50d3 454 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 455 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 456 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 457 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 458 .fb = { 0x00000001, nv40_fb_new },
01055c01 459 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 460 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 461 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 462 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 463 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 464 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 465 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 466 .timer = { 0x00000001, nv40_timer_new },
d07be5d7 467 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 468 .disp = { 0x00000001, nv04_disp_new },
09f409d7 469 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 470 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 471 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 472 .mpeg = { 0x00000001, nv40_mpeg_new },
8d6461d8 473 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 474};
475
476static const struct nvkm_device_chip
477nv41_chipset = {
478 .name = "NV41",
e07f50d3 479 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 480 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 481 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 482 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 483 .fb = { 0x00000001, nv41_fb_new },
01055c01 484 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 485 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 486 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 487 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 488 .mmu = { 0x00000001, nv41_mmu_new },
9b70cd54 489 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 490 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 491 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 492 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 493 .disp = { 0x00000001, nv04_disp_new },
09f409d7 494 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 495 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 496 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 497 .mpeg = { 0x00000001, nv40_mpeg_new },
8d6461d8 498 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 499};
500
501static const struct nvkm_device_chip
502nv42_chipset = {
503 .name = "NV42",
e07f50d3 504 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 505 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 506 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 507 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 508 .fb = { 0x00000001, nv41_fb_new },
01055c01 509 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 510 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 511 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 512 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 513 .mmu = { 0x00000001, nv41_mmu_new },
9b70cd54 514 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 515 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 516 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 517 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 518 .disp = { 0x00000001, nv04_disp_new },
09f409d7 519 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 520 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 521 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 522 .mpeg = { 0x00000001, nv40_mpeg_new },
8d6461d8 523 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 524};
525
526static const struct nvkm_device_chip
527nv43_chipset = {
528 .name = "NV43",
e07f50d3 529 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 530 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 531 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 532 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 533 .fb = { 0x00000001, nv41_fb_new },
01055c01 534 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 535 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 536 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 537 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 538 .mmu = { 0x00000001, nv41_mmu_new },
9b70cd54 539 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 540 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 541 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 542 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 543 .disp = { 0x00000001, nv04_disp_new },
09f409d7 544 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 545 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 546 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 547 .mpeg = { 0x00000001, nv40_mpeg_new },
8d6461d8 548 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 549};
550
551static const struct nvkm_device_chip
552nv44_chipset = {
553 .name = "NV44",
e07f50d3 554 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 555 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 556 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 557 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 558 .fb = { 0x00000001, nv44_fb_new },
01055c01 559 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 560 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 561 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 562 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 563 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 564 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 565 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 566 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 567 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 568 .disp = { 0x00000001, nv04_disp_new },
09f409d7 569 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 570 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 571 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 572 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 573 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 574};
575
576static const struct nvkm_device_chip
577nv45_chipset = {
578 .name = "NV45",
e07f50d3 579 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 580 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 581 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 582 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 583 .fb = { 0x00000001, nv40_fb_new },
01055c01 584 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 585 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 586 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 587 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 588 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 589 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 590 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 591 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 592 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 593 .disp = { 0x00000001, nv04_disp_new },
09f409d7 594 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 595 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 596 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 597 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 598 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 599};
600
601static const struct nvkm_device_chip
602nv46_chipset = {
603 .name = "G72",
e07f50d3 604 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 605 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 606 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 607 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 608 .fb = { 0x00000001, nv46_fb_new },
01055c01 609 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 610 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 611 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 612 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 613 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 614 .pci = { 0x00000001, nv46_pci_new },
0aec69c7 615 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 616 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 617 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 618 .disp = { 0x00000001, nv04_disp_new },
09f409d7 619 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 620 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 621 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 622 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 623 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 624};
625
626static const struct nvkm_device_chip
627nv47_chipset = {
628 .name = "G70",
e07f50d3 629 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 630 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 631 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 632 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 633 .fb = { 0x00000001, nv47_fb_new },
01055c01 634 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 635 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 636 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 637 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 638 .mmu = { 0x00000001, nv41_mmu_new },
9b70cd54 639 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 640 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 641 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 642 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 643 .disp = { 0x00000001, nv04_disp_new },
09f409d7 644 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 645 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 646 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 647 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 648 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 649};
650
651static const struct nvkm_device_chip
652nv49_chipset = {
653 .name = "G71",
e07f50d3 654 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 655 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 656 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 657 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 658 .fb = { 0x00000001, nv49_fb_new },
01055c01 659 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 660 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 661 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 662 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 663 .mmu = { 0x00000001, nv41_mmu_new },
9b70cd54 664 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 665 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 666 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 667 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 668 .disp = { 0x00000001, nv04_disp_new },
09f409d7 669 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 670 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 671 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 672 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 673 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 674};
675
676static const struct nvkm_device_chip
677nv4a_chipset = {
678 .name = "NV44A",
e07f50d3 679 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 680 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 681 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 682 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 683 .fb = { 0x00000001, nv44_fb_new },
01055c01 684 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 685 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 686 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 687 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 688 .mmu = { 0x00000001, nv04_mmu_new },
9b70cd54 689 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 690 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 691 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 692 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 693 .disp = { 0x00000001, nv04_disp_new },
09f409d7 694 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 695 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 696 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 697 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 698 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 699};
700
701static const struct nvkm_device_chip
702nv4b_chipset = {
703 .name = "G73",
e07f50d3 704 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 705 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 706 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 707 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 708 .fb = { 0x00000001, nv49_fb_new },
01055c01 709 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 710 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 711 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 712 .mc = { 0x00000001, nv17_mc_new },
6dd123ba 713 .mmu = { 0x00000001, nv41_mmu_new },
9b70cd54 714 .pci = { 0x00000001, nv40_pci_new },
0aec69c7 715 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 716 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 717 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 718 .disp = { 0x00000001, nv04_disp_new },
09f409d7 719 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 720 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 721 .gr = { 0x00000001, nv40_gr_new },
e5e95a76 722 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 723 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 724};
725
726static const struct nvkm_device_chip
727nv4c_chipset = {
728 .name = "C61",
e07f50d3 729 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 730 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 731 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 732 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 733 .fb = { 0x00000001, nv46_fb_new },
01055c01 734 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 735 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 736 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 737 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 738 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 739 .pci = { 0x00000001, nv4c_pci_new },
0aec69c7 740 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 741 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 742 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 743 .disp = { 0x00000001, nv04_disp_new },
09f409d7 744 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 745 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 746 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 747 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 748 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 749};
750
751static const struct nvkm_device_chip
752nv4e_chipset = {
753 .name = "C51",
e07f50d3 754 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 755 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 756 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 757 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 758 .fb = { 0x00000001, nv4e_fb_new },
01055c01 759 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 760 .i2c = { 0x00000001, nv4e_i2c_new },
d9691a22 761 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 762 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 763 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 764 .pci = { 0x00000001, nv4c_pci_new },
0aec69c7 765 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 766 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 767 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 768 .disp = { 0x00000001, nv04_disp_new },
09f409d7 769 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 770 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 771 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 772 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 773 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 774};
775
776static const struct nvkm_device_chip
777nv50_chipset = {
778 .name = "G80",
917b24a3 779 .bar = { 0x00000001, nv50_bar_new },
e07f50d3 780 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 781 .bus = { 0x00000001, nv50_bus_new },
98fd7f83 782 .clk = { 0x00000001, nv50_clk_new },
4a34fd0e 783 .devinit = { 0x00000001, nv50_devinit_new },
b7a9369a 784 .fb = { 0x00000001, nv50_fb_new },
8d056d99 785 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 786 .gpio = { 0x00000001, nv50_gpio_new },
c6ce0861 787 .i2c = { 0x00000001, nv50_i2c_new },
d9691a22 788 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 789 .mc = { 0x00000001, nv50_mc_new },
6dd123ba 790 .mmu = { 0x00000001, nv50_mmu_new },
0a7bff10 791 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 792 .pci = { 0x00000001, nv46_pci_new },
0aec69c7 793 .therm = { 0x00000001, nv50_therm_new },
9aad54d5 794 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 795 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 796 .disp = { 0x00000001, nv50_disp_new },
09f409d7 797 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 798 .fifo = { 0x00000001, nv50_fifo_new },
864d37c3 799 .gr = { 0x00000001, nv50_gr_new },
e5e95a76 800 .mpeg = { 0x00000001, nv50_mpeg_new },
8d6461d8 801 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 802};
803
804static const struct nvkm_device_chip
805nv63_chipset = {
806 .name = "C73",
e07f50d3 807 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 808 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 809 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 810 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 811 .fb = { 0x00000001, nv46_fb_new },
01055c01 812 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 813 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 814 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 815 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 816 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 817 .pci = { 0x00000001, nv4c_pci_new },
0aec69c7 818 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 819 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 820 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 821 .disp = { 0x00000001, nv04_disp_new },
09f409d7 822 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 823 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 824 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 825 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 826 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 827};
828
829static const struct nvkm_device_chip
830nv67_chipset = {
831 .name = "C67",
e07f50d3 832 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 833 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 834 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 835 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 836 .fb = { 0x00000001, nv46_fb_new },
01055c01 837 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 838 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 839 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 840 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 841 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 842 .pci = { 0x00000001, nv4c_pci_new },
0aec69c7 843 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 844 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 845 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 846 .disp = { 0x00000001, nv04_disp_new },
09f409d7 847 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 848 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 849 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 850 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 851 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 852};
853
854static const struct nvkm_device_chip
855nv68_chipset = {
856 .name = "C68",
e07f50d3 857 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 858 .bus = { 0x00000001, nv31_bus_new },
98fd7f83 859 .clk = { 0x00000001, nv40_clk_new },
4a34fd0e 860 .devinit = { 0x00000001, nv1a_devinit_new },
b7a9369a 861 .fb = { 0x00000001, nv46_fb_new },
01055c01 862 .gpio = { 0x00000001, nv10_gpio_new },
c6ce0861 863 .i2c = { 0x00000001, nv04_i2c_new },
d9691a22 864 .imem = { 0x00000001, nv40_instmem_new },
1fc2fddf 865 .mc = { 0x00000001, nv44_mc_new },
6dd123ba 866 .mmu = { 0x00000001, nv44_mmu_new },
9b70cd54 867 .pci = { 0x00000001, nv4c_pci_new },
0aec69c7 868 .therm = { 0x00000001, nv40_therm_new },
9aad54d5 869 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 870 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 871 .disp = { 0x00000001, nv04_disp_new },
09f409d7 872 .dma = { 0x00000001, nv04_dma_new },
ab0db2bd 873 .fifo = { 0x00000001, nv40_fifo_new },
864d37c3 874 .gr = { 0x00000001, nv44_gr_new },
e5e95a76 875 .mpeg = { 0x00000001, nv44_mpeg_new },
8d6461d8 876 .sw = { 0x00000001, nv10_sw_new },
6cf813fb
BS		 877};
878
879static const struct nvkm_device_chip
880nv84_chipset = {
881 .name = "G84",
917b24a3 882 .bar = { 0x00000001, g84_bar_new },
e07f50d3 883 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 884 .bus = { 0x00000001, nv50_bus_new },
98fd7f83 885 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 886 .devinit = { 0x00000001, g84_devinit_new },
b7a9369a 887 .fb = { 0x00000001, g84_fb_new },
8d056d99 888 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 889 .gpio = { 0x00000001, nv50_gpio_new },
c6ce0861 890 .i2c = { 0x00000001, nv50_i2c_new },
d9691a22 891 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 892 .mc = { 0x00000001, g84_mc_new },
6dd123ba 893 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 894 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 895 .pci = { 0x00000001, g84_pci_new },
0aec69c7 896 .therm = { 0x00000001, g84_therm_new },
9aad54d5 897 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 898 .volt = { 0x00000001, nv40_volt_new },
fcc08a7c 899 .bsp = { 0x00000001, g84_bsp_new },
0b26ca68 900 .cipher = { 0x00000001, g84_cipher_new },
a7f000ec 901 .disp = { 0x00000001, g84_disp_new },
09f409d7 902 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 903 .fifo = { 0x00000001, g84_fifo_new },
864d37c3 904 .gr = { 0x00000001, g84_gr_new },
e5e95a76 905 .mpeg = { 0x00000001, g84_mpeg_new },
8d6461d8 906 .sw = { 0x00000001, nv50_sw_new },
fcc08a7c 907 .vp = { 0x00000001, g84_vp_new },
6cf813fb
BS		 908};
909
910static const struct nvkm_device_chip
911nv86_chipset = {
912 .name = "G86",
917b24a3 913 .bar = { 0x00000001, g84_bar_new },
e07f50d3 914 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 915 .bus = { 0x00000001, nv50_bus_new },
98fd7f83 916 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 917 .devinit = { 0x00000001, g84_devinit_new },
b7a9369a 918 .fb = { 0x00000001, g84_fb_new },
8d056d99 919 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 920 .gpio = { 0x00000001, nv50_gpio_new },
c6ce0861 921 .i2c = { 0x00000001, nv50_i2c_new },
d9691a22 922 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 923 .mc = { 0x00000001, g84_mc_new },
6dd123ba 924 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 925 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 926 .pci = { 0x00000001, g84_pci_new },
0aec69c7 927 .therm = { 0x00000001, g84_therm_new },
9aad54d5 928 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 929 .volt = { 0x00000001, nv40_volt_new },
fcc08a7c 930 .bsp = { 0x00000001, g84_bsp_new },
0b26ca68 931 .cipher = { 0x00000001, g84_cipher_new },
a7f000ec 932 .disp = { 0x00000001, g84_disp_new },
09f409d7 933 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 934 .fifo = { 0x00000001, g84_fifo_new },
864d37c3 935 .gr = { 0x00000001, g84_gr_new },
e5e95a76 936 .mpeg = { 0x00000001, g84_mpeg_new },
8d6461d8 937 .sw = { 0x00000001, nv50_sw_new },
fcc08a7c 938 .vp = { 0x00000001, g84_vp_new },
6cf813fb
BS		 939};
940
941static const struct nvkm_device_chip
942nv92_chipset = {
943 .name = "G92",
917b24a3 944 .bar = { 0x00000001, g84_bar_new },
e07f50d3 945 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 946 .bus = { 0x00000001, nv50_bus_new },
98fd7f83 947 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 948 .devinit = { 0x00000001, g84_devinit_new },
b7a9369a 949 .fb = { 0x00000001, g84_fb_new },
8d056d99 950 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 951 .gpio = { 0x00000001, nv50_gpio_new },
c6ce0861 952 .i2c = { 0x00000001, nv50_i2c_new },
d9691a22 953 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 954 .mc = { 0x00000001, g84_mc_new },
6dd123ba 955 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 956 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 957 .pci = { 0x00000001, g92_pci_new },
0aec69c7 958 .therm = { 0x00000001, g84_therm_new },
9aad54d5 959 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 960 .volt = { 0x00000001, nv40_volt_new },
fcc08a7c 961 .bsp = { 0x00000001, g84_bsp_new },
0b26ca68 962 .cipher = { 0x00000001, g84_cipher_new },
a7f000ec 963 .disp = { 0x00000001, g84_disp_new },
09f409d7 964 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 965 .fifo = { 0x00000001, g84_fifo_new },
864d37c3 966 .gr = { 0x00000001, g84_gr_new },
e5e95a76 967 .mpeg = { 0x00000001, g84_mpeg_new },
8d6461d8 968 .sw = { 0x00000001, nv50_sw_new },
fcc08a7c 969 .vp = { 0x00000001, g84_vp_new },
6cf813fb
BS		 970};
971
972static const struct nvkm_device_chip
973nv94_chipset = {
974 .name = "G94",
917b24a3 975 .bar = { 0x00000001, g84_bar_new },
e07f50d3 976 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 977 .bus = { 0x00000001, g94_bus_new },
98fd7f83 978 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 979 .devinit = { 0x00000001, g84_devinit_new },
b7a9369a 980 .fb = { 0x00000001, g84_fb_new },
8d056d99 981 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 982 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 983 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 984 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 985 .mc = { 0x00000001, g84_mc_new },
6dd123ba 986 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 987 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 988 .pci = { 0x00000001, g94_pci_new },
0aec69c7 989 .therm = { 0x00000001, g84_therm_new },
9aad54d5 990 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 991 .volt = { 0x00000001, nv40_volt_new },
fcc08a7c 992 .bsp = { 0x00000001, g84_bsp_new },
0b26ca68 993 .cipher = { 0x00000001, g84_cipher_new },
a7f000ec 994 .disp = { 0x00000001, g94_disp_new },
09f409d7 995 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 996 .fifo = { 0x00000001, g84_fifo_new },
864d37c3 997 .gr = { 0x00000001, g84_gr_new },
e5e95a76 998 .mpeg = { 0x00000001, g84_mpeg_new },
8d6461d8 999 .sw = { 0x00000001, nv50_sw_new },
fcc08a7c 1000 .vp = { 0x00000001, g84_vp_new },
6cf813fb
BS		 1001};
1002
1003static const struct nvkm_device_chip
1004nv96_chipset = {
1005 .name = "G96",
917b24a3 1006 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1007 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1008 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1009 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 1010 .devinit = { 0x00000001, g84_devinit_new },
b7a9369a 1011 .fb = { 0x00000001, g84_fb_new },
8d056d99 1012 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1013 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1014 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1015 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1016 .mc = { 0x00000001, g84_mc_new },
6dd123ba 1017 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 1018 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1019 .pci = { 0x00000001, g94_pci_new },
0aec69c7 1020 .therm = { 0x00000001, g84_therm_new },
9aad54d5 1021 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1022 .volt = { 0x00000001, nv40_volt_new },
fcc08a7c 1023 .bsp = { 0x00000001, g84_bsp_new },
0b26ca68 1024 .cipher = { 0x00000001, g84_cipher_new },
a7f000ec 1025 .disp = { 0x00000001, g94_disp_new },
09f409d7 1026 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 1027 .fifo = { 0x00000001, g84_fifo_new },
864d37c3 1028 .gr = { 0x00000001, g84_gr_new },
e5e95a76 1029 .mpeg = { 0x00000001, g84_mpeg_new },
8d6461d8 1030 .sw = { 0x00000001, nv50_sw_new },
fcc08a7c 1031 .vp = { 0x00000001, g84_vp_new },
6cf813fb
BS		 1032};
1033
1034static const struct nvkm_device_chip
1035nv98_chipset = {
1036 .name = "G98",
917b24a3 1037 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1038 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1039 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1040 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 1041 .devinit = { 0x00000001, g98_devinit_new },
b7a9369a 1042 .fb = { 0x00000001, g84_fb_new },
8d056d99 1043 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1044 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1045 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1046 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1047 .mc = { 0x00000001, g98_mc_new },
6dd123ba 1048 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 1049 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1050 .pci = { 0x00000001, g94_pci_new },
0aec69c7 1051 .therm = { 0x00000001, g84_therm_new },
9aad54d5 1052 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1053 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 1054 .disp = { 0x00000001, g94_disp_new },
09f409d7 1055 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1056 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1057 .gr = { 0x00000001, g84_gr_new },
96321606 1058 .mspdec = { 0x00000001, g98_mspdec_new },
07a356bb 1059 .msppp = { 0x00000001, g98_msppp_new },
b15147bd 1060 .msvld = { 0x00000001, g98_msvld_new },
400c2a45 1061 .sec = { 0x00000001, g98_sec_new },
8d6461d8 1062 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1063};
1064
1065static const struct nvkm_device_chip
1066nva0_chipset = {
1067 .name = "GT200",
917b24a3 1068 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1069 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1070 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1071 .clk = { 0x00000001, g84_clk_new },
4a34fd0e 1072 .devinit = { 0x00000001, g84_devinit_new },
b7a9369a 1073 .fb = { 0x00000001, g84_fb_new },
8d056d99 1074 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1075 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1076 .i2c = { 0x00000001, nv50_i2c_new },
d9691a22 1077 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1078 .mc = { 0x00000001, g84_mc_new },
6dd123ba 1079 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 1080 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1081 .pci = { 0x00000001, g94_pci_new },
0aec69c7 1082 .therm = { 0x00000001, g84_therm_new },
9aad54d5 1083 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1084 .volt = { 0x00000001, nv40_volt_new },
fcc08a7c 1085 .bsp = { 0x00000001, g84_bsp_new },
0b26ca68 1086 .cipher = { 0x00000001, g84_cipher_new },
a7f000ec 1087 .disp = { 0x00000001, gt200_disp_new },
09f409d7 1088 .dma = { 0x00000001, nv50_dma_new },
ab0db2bd 1089 .fifo = { 0x00000001, g84_fifo_new },
864d37c3 1090 .gr = { 0x00000001, gt200_gr_new },
e5e95a76 1091 .mpeg = { 0x00000001, g84_mpeg_new },
8d6461d8 1092 .sw = { 0x00000001, nv50_sw_new },
fcc08a7c 1093 .vp = { 0x00000001, g84_vp_new },
6cf813fb
BS		 1094};
1095
1096static const struct nvkm_device_chip
1097nva3_chipset = {
1098 .name = "GT215",
917b24a3 1099 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1100 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1101 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1102 .clk = { 0x00000001, gt215_clk_new },
4a34fd0e 1103 .devinit = { 0x00000001, gt215_devinit_new },
b7a9369a 1104 .fb = { 0x00000001, gt215_fb_new },
8d056d99 1105 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1106 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1107 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1108 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1109 .mc = { 0x00000001, gt215_mc_new },
6dd123ba 1110 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 1111 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1112 .pci = { 0x00000001, g94_pci_new },
e4b15b4c 1113 .pmu = { 0x00000001, gt215_pmu_new },
0aec69c7 1114 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1115 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1116 .volt = { 0x00000001, nv40_volt_new },
50551b15 1117 .ce = { 0x00000001, gt215_ce_new },
a7f000ec 1118 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1119 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1120 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1121 .gr = { 0x00000001, gt215_gr_new },
e5e95a76 1122 .mpeg = { 0x00000001, g84_mpeg_new },
96321606 1123 .mspdec = { 0x00000001, gt215_mspdec_new },
07a356bb 1124 .msppp = { 0x00000001, gt215_msppp_new },
b15147bd 1125 .msvld = { 0x00000001, gt215_msvld_new },
8d6461d8 1126 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1127};
1128
1129static const struct nvkm_device_chip
1130nva5_chipset = {
1131 .name = "GT216",
917b24a3 1132 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1133 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1134 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1135 .clk = { 0x00000001, gt215_clk_new },
4a34fd0e 1136 .devinit = { 0x00000001, gt215_devinit_new },
b7a9369a 1137 .fb = { 0x00000001, gt215_fb_new },
8d056d99 1138 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1139 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1140 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1141 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1142 .mc = { 0x00000001, gt215_mc_new },
6dd123ba 1143 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 1144 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1145 .pci = { 0x00000001, g94_pci_new },
e4b15b4c 1146 .pmu = { 0x00000001, gt215_pmu_new },
0aec69c7 1147 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1148 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1149 .volt = { 0x00000001, nv40_volt_new },
50551b15 1150 .ce = { 0x00000001, gt215_ce_new },
a7f000ec 1151 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1152 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1153 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1154 .gr = { 0x00000001, gt215_gr_new },
96321606 1155 .mspdec = { 0x00000001, gt215_mspdec_new },
07a356bb 1156 .msppp = { 0x00000001, gt215_msppp_new },
b15147bd 1157 .msvld = { 0x00000001, gt215_msvld_new },
8d6461d8 1158 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1159};
1160
1161static const struct nvkm_device_chip
1162nva8_chipset = {
1163 .name = "GT218",
917b24a3 1164 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1165 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1166 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1167 .clk = { 0x00000001, gt215_clk_new },
4a34fd0e 1168 .devinit = { 0x00000001, gt215_devinit_new },
b7a9369a 1169 .fb = { 0x00000001, gt215_fb_new },
8d056d99 1170 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1171 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1172 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1173 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1174 .mc = { 0x00000001, gt215_mc_new },
6dd123ba 1175 .mmu = { 0x00000001, g84_mmu_new },
0a7bff10 1176 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1177 .pci = { 0x00000001, g94_pci_new },
e4b15b4c 1178 .pmu = { 0x00000001, gt215_pmu_new },
0aec69c7 1179 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1180 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1181 .volt = { 0x00000001, nv40_volt_new },
50551b15 1182 .ce = { 0x00000001, gt215_ce_new },
a7f000ec 1183 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1184 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1185 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1186 .gr = { 0x00000001, gt215_gr_new },
96321606 1187 .mspdec = { 0x00000001, gt215_mspdec_new },
07a356bb 1188 .msppp = { 0x00000001, gt215_msppp_new },
b15147bd 1189 .msvld = { 0x00000001, gt215_msvld_new },
8d6461d8 1190 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1191};
1192
1193static const struct nvkm_device_chip
1194nvaa_chipset = {
1195 .name = "MCP77/MCP78",
917b24a3 1196 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1197 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1198 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1199 .clk = { 0x00000001, mcp77_clk_new },
4a34fd0e 1200 .devinit = { 0x00000001, g98_devinit_new },
b7a9369a 1201 .fb = { 0x00000001, mcp77_fb_new },
8d056d99 1202 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1203 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1204 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1205 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1206 .mc = { 0x00000001, g98_mc_new },
6dd123ba 1207 .mmu = { 0x00000001, mcp77_mmu_new },
0a7bff10 1208 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1209 .pci = { 0x00000001, g94_pci_new },
0aec69c7 1210 .therm = { 0x00000001, g84_therm_new },
9aad54d5 1211 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1212 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 1213 .disp = { 0x00000001, mcp77_disp_new },
09f409d7 1214 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1215 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1216 .gr = { 0x00000001, gt200_gr_new },
96321606 1217 .mspdec = { 0x00000001, g98_mspdec_new },
07a356bb 1218 .msppp = { 0x00000001, g98_msppp_new },
b15147bd 1219 .msvld = { 0x00000001, g98_msvld_new },
400c2a45 1220 .sec = { 0x00000001, g98_sec_new },
8d6461d8 1221 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1222};
1223
1224static const struct nvkm_device_chip
1225nvac_chipset = {
1226 .name = "MCP79/MCP7A",
917b24a3 1227 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1228 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1229 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1230 .clk = { 0x00000001, mcp77_clk_new },
4a34fd0e 1231 .devinit = { 0x00000001, g98_devinit_new },
b7a9369a 1232 .fb = { 0x00000001, mcp77_fb_new },
8d056d99 1233 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1234 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1235 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1236 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1237 .mc = { 0x00000001, g98_mc_new },
6dd123ba 1238 .mmu = { 0x00000001, mcp77_mmu_new },
0a7bff10 1239 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1240 .pci = { 0x00000001, g94_pci_new },
0aec69c7 1241 .therm = { 0x00000001, g84_therm_new },
9aad54d5 1242 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1243 .volt = { 0x00000001, nv40_volt_new },
a7f000ec 1244 .disp = { 0x00000001, mcp77_disp_new },
09f409d7 1245 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1246 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1247 .gr = { 0x00000001, mcp79_gr_new },
96321606 1248 .mspdec = { 0x00000001, g98_mspdec_new },
07a356bb 1249 .msppp = { 0x00000001, g98_msppp_new },
b15147bd 1250 .msvld = { 0x00000001, g98_msvld_new },
400c2a45 1251 .sec = { 0x00000001, g98_sec_new },
8d6461d8 1252 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1253};
1254
1255static const struct nvkm_device_chip
1256nvaf_chipset = {
1257 .name = "MCP89",
917b24a3 1258 .bar = { 0x00000001, g84_bar_new },
e07f50d3 1259 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1260 .bus = { 0x00000001, g94_bus_new },
98fd7f83 1261 .clk = { 0x00000001, gt215_clk_new },
4a34fd0e 1262 .devinit = { 0x00000001, mcp89_devinit_new },
b7a9369a 1263 .fb = { 0x00000001, mcp89_fb_new },
8d056d99 1264 .fuse = { 0x00000001, nv50_fuse_new },
01055c01 1265 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1266 .i2c = { 0x00000001, g94_i2c_new },
d9691a22 1267 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 1268 .mc = { 0x00000001, gt215_mc_new },
6dd123ba 1269 .mmu = { 0x00000001, mcp77_mmu_new },
0a7bff10 1270 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1271 .pci = { 0x00000001, g94_pci_new },
e4b15b4c 1272 .pmu = { 0x00000001, gt215_pmu_new },
0aec69c7 1273 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1274 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1275 .volt = { 0x00000001, nv40_volt_new },
50551b15 1276 .ce = { 0x00000001, gt215_ce_new },
a7f000ec 1277 .disp = { 0x00000001, mcp89_disp_new },
09f409d7 1278 .dma = { 0x00000001, nv50_dma_new },
d94470e9 1279 .fifo = { 0x00000001, g98_fifo_new },
864d37c3 1280 .gr = { 0x00000001, mcp89_gr_new },
96321606 1281 .mspdec = { 0x00000001, gt215_mspdec_new },
07a356bb 1282 .msppp = { 0x00000001, gt215_msppp_new },
b15147bd 1283 .msvld = { 0x00000001, mcp89_msvld_new },
8d6461d8 1284 .sw = { 0x00000001, nv50_sw_new },
6cf813fb
BS		 1285};
1286
1287static const struct nvkm_device_chip
1288nvc0_chipset = {
1289 .name = "GF100",
917b24a3 1290 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1291 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1292 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1293 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1294 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1295 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1296 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1297 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1298 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1299 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1300 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1301 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1302 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1303 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1304 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1305 .pci = { 0x00000001, gf100_pci_new },
e4b15b4c 1306 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1307 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1308 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1309 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1310 .volt = { 0x00000001, gf100_volt_new },
50551b15 1311 .ce = { 0x00000003, gf100_ce_new },
a7f000ec 1312 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1313 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1314 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1315 .gr = { 0x00000001, gf100_gr_new },
96321606 1316 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1317 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1318 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1319 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1320};
1321
1322static const struct nvkm_device_chip
1323nvc1_chipset = {
1324 .name = "GF108",
917b24a3 1325 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1326 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1327 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1328 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1329 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1330 .fb = { 0x00000001, gf108_fb_new },
8d056d99 1331 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1332 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1333 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1334 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1335 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1336 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1337 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1338 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1339 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1340 .pci = { 0x00000001, gf106_pci_new },
e4b15b4c 1341 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1342 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1343 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1344 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1345 .volt = { 0x00000001, gf100_volt_new },
50551b15 1346 .ce = { 0x00000001, gf100_ce_new },
a7f000ec 1347 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1348 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1349 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1350 .gr = { 0x00000001, gf108_gr_new },
96321606 1351 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1352 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1353 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1354 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1355};
1356
1357static const struct nvkm_device_chip
1358nvc3_chipset = {
1359 .name = "GF106",
917b24a3 1360 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1361 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1362 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1363 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1364 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1365 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1366 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1367 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1368 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1369 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1370 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1371 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1372 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1373 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1374 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1375 .pci = { 0x00000001, gf106_pci_new },
e4b15b4c 1376 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1377 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1378 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1379 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1380 .volt = { 0x00000001, gf100_volt_new },
50551b15 1381 .ce = { 0x00000001, gf100_ce_new },
a7f000ec 1382 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1383 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1384 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1385 .gr = { 0x00000001, gf104_gr_new },
96321606 1386 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1387 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1388 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1389 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1390};
1391
1392static const struct nvkm_device_chip
1393nvc4_chipset = {
1394 .name = "GF104",
917b24a3 1395 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1396 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1397 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1398 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1399 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1400 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1401 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1402 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1403 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1404 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1405 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1406 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1407 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1408 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1409 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1410 .pci = { 0x00000001, gf100_pci_new },
e4b15b4c 1411 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1412 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1413 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1414 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1415 .volt = { 0x00000001, gf100_volt_new },
50551b15 1416 .ce = { 0x00000003, gf100_ce_new },
a7f000ec 1417 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1418 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1419 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1420 .gr = { 0x00000001, gf104_gr_new },
96321606 1421 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1422 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1423 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1424 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1425};
1426
1427static const struct nvkm_device_chip
1428nvc8_chipset = {
1429 .name = "GF110",
917b24a3 1430 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1431 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1432 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1433 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1434 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1435 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1436 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1437 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1438 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1439 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1440 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1441 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1442 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1443 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1444 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1445 .pci = { 0x00000001, gf100_pci_new },
e4b15b4c 1446 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1447 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1448 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1449 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1450 .volt = { 0x00000001, gf100_volt_new },
50551b15 1451 .ce = { 0x00000003, gf100_ce_new },
a7f000ec 1452 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1453 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1454 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1455 .gr = { 0x00000001, gf110_gr_new },
96321606 1456 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1457 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1458 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1459 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1460};
1461
1462static const struct nvkm_device_chip
1463nvce_chipset = {
1464 .name = "GF114",
917b24a3 1465 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1466 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1467 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1468 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1469 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1470 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1471 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1472 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1473 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1474 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1475 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1476 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1477 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1478 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1479 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1480 .pci = { 0x00000001, gf100_pci_new },
e4b15b4c 1481 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1482 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1483 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1484 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1485 .volt = { 0x00000001, gf100_volt_new },
50551b15 1486 .ce = { 0x00000003, gf100_ce_new },
a7f000ec 1487 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1488 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1489 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1490 .gr = { 0x00000001, gf104_gr_new },
96321606 1491 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1492 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1493 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1494 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1495};
1496
1497static const struct nvkm_device_chip
1498nvcf_chipset = {
1499 .name = "GF116",
917b24a3 1500 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1501 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1502 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1503 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1504 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1505 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1506 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1507 .gpio = { 0x00000001, g94_gpio_new },
c6ce0861 1508 .i2c = { 0x00000001, g94_i2c_new },
4dea1a96 1509 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1510 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1511 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1512 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1513 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1514 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1515 .pci = { 0x00000001, gf106_pci_new },
e4b15b4c 1516 .pmu = { 0x00000001, gf100_pmu_new },
26fbb4c8 1517 .privring = { 0x00000001, gf100_privring_new },
0aec69c7 1518 .therm = { 0x00000001, gt215_therm_new },
9aad54d5 1519 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1520 .volt = { 0x00000001, gf100_volt_new },
50551b15 1521 .ce = { 0x00000001, gf100_ce_new },
a7f000ec 1522 .disp = { 0x00000001, gt215_disp_new },
09f409d7 1523 .dma = { 0x00000001, gf100_dma_new },
ab0db2bd 1524 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1525 .gr = { 0x00000001, gf104_gr_new },
96321606 1526 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1527 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1528 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1529 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1530};
1531
1532static const struct nvkm_device_chip
1533nvd7_chipset = {
1534 .name = "GF117",
917b24a3 1535 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1536 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1537 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1538 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1539 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1540 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1541 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1542 .gpio = { 0x00000001, gf119_gpio_new },
c6ce0861 1543 .i2c = { 0x00000001, gf117_i2c_new },
4dea1a96 1544 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1545 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1546 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1547 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1548 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1549 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1550 .pci = { 0x00000001, gf106_pci_new },
26fbb4c8 1551 .privring = { 0x00000001, gf117_privring_new },
0aec69c7 1552 .therm = { 0x00000001, gf119_therm_new },
9aad54d5 1553 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1554 .volt = { 0x00000001, gf117_volt_new },
50551b15 1555 .ce = { 0x00000001, gf100_ce_new },
a7f000ec 1556 .disp = { 0x00000001, gf119_disp_new },
09f409d7 1557 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1558 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1559 .gr = { 0x00000001, gf117_gr_new },
96321606 1560 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1561 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1562 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1563 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1564};
1565
1566static const struct nvkm_device_chip
1567nvd9_chipset = {
1568 .name = "GF119",
917b24a3 1569 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1570 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1571 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1572 .clk = { 0x00000001, gf100_clk_new },
4a34fd0e 1573 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1574 .fb = { 0x00000001, gf100_fb_new },
8d056d99 1575 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1576 .gpio = { 0x00000001, gf119_gpio_new },
c6ce0861 1577 .i2c = { 0x00000001, gf119_i2c_new },
4dea1a96 1578 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1579 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1580 .ltc = { 0x00000001, gf100_ltc_new },
1fc2fddf 1581 .mc = { 0x00000001, gf100_mc_new },
6dd123ba 1582 .mmu = { 0x00000001, gf100_mmu_new },
0a7bff10 1583 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1584 .pci = { 0x00000001, gf106_pci_new },
e4b15b4c 1585 .pmu = { 0x00000001, gf119_pmu_new },
26fbb4c8 1586 .privring = { 0x00000001, gf117_privring_new },
0aec69c7 1587 .therm = { 0x00000001, gf119_therm_new },
9aad54d5 1588 .timer = { 0x00000001, nv41_timer_new },
d07be5d7 1589 .volt = { 0x00000001, gf100_volt_new },
50551b15 1590 .ce = { 0x00000001, gf100_ce_new },
a7f000ec 1591 .disp = { 0x00000001, gf119_disp_new },
09f409d7 1592 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1593 .fifo = { 0x00000001, gf100_fifo_new },
864d37c3 1594 .gr = { 0x00000001, gf119_gr_new },
96321606 1595 .mspdec = { 0x00000001, gf100_mspdec_new },
07a356bb 1596 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1597 .msvld = { 0x00000001, gf100_msvld_new },
8d6461d8 1598 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1599};
1600
1601static const struct nvkm_device_chip
1602nve4_chipset = {
1603 .name = "GK104",
917b24a3 1604 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1605 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1606 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1607 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1608 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1609 .fb = { 0x00000001, gk104_fb_new },
8d056d99 1610 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1611 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1612 .i2c = { 0x00000001, gk104_i2c_new },
4dea1a96 1613 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1614 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1615 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1616 .mc = { 0x00000001, gk104_mc_new },
6dd123ba 1617 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1618 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1619 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1620 .pmu = { 0x00000001, gk104_pmu_new },
26fbb4c8 1621 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1622 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1623 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1624 .top = { 0x00000001, gk104_top_new },
d07be5d7 1625 .volt = { 0x00000001, gk104_volt_new },
50551b15 1626 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1627 .disp = { 0x00000001, gk104_disp_new },
09f409d7 1628 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1629 .fifo = { 0x00000001, gk104_fifo_new },
864d37c3 1630 .gr = { 0x00000001, gk104_gr_new },
96321606 1631 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1632 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1633 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1634 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1635};
1636
1637static const struct nvkm_device_chip
1638nve6_chipset = {
1639 .name = "GK106",
917b24a3 1640 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1641 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1642 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1643 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1644 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1645 .fb = { 0x00000001, gk104_fb_new },
8d056d99 1646 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1647 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1648 .i2c = { 0x00000001, gk104_i2c_new },
4dea1a96 1649 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1650 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1651 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1652 .mc = { 0x00000001, gk104_mc_new },
6dd123ba 1653 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1654 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1655 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1656 .pmu = { 0x00000001, gk104_pmu_new },
26fbb4c8 1657 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1658 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1659 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1660 .top = { 0x00000001, gk104_top_new },
d07be5d7 1661 .volt = { 0x00000001, gk104_volt_new },
50551b15 1662 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1663 .disp = { 0x00000001, gk104_disp_new },
09f409d7 1664 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1665 .fifo = { 0x00000001, gk104_fifo_new },
864d37c3 1666 .gr = { 0x00000001, gk104_gr_new },
96321606 1667 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1668 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1669 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1670 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1671};
1672
1673static const struct nvkm_device_chip
1674nve7_chipset = {
1675 .name = "GK107",
917b24a3 1676 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1677 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1678 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1679 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1680 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1681 .fb = { 0x00000001, gk104_fb_new },
8d056d99 1682 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1683 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1684 .i2c = { 0x00000001, gk104_i2c_new },
4dea1a96 1685 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1686 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1687 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1688 .mc = { 0x00000001, gk104_mc_new },
6dd123ba 1689 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1690 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1691 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1692 .pmu = { 0x00000001, gk104_pmu_new },
26fbb4c8 1693 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1694 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1695 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1696 .top = { 0x00000001, gk104_top_new },
d07be5d7 1697 .volt = { 0x00000001, gk104_volt_new },
50551b15 1698 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1699 .disp = { 0x00000001, gk104_disp_new },
09f409d7 1700 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1701 .fifo = { 0x00000001, gk104_fifo_new },
864d37c3 1702 .gr = { 0x00000001, gk104_gr_new },
96321606 1703 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1704 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1705 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1706 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1707};
1708
1709static const struct nvkm_device_chip
1710nvea_chipset = {
1711 .name = "GK20A",
917b24a3 1712 .bar = { 0x00000001, gk20a_bar_new },
d37766e5 1713 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1714 .clk = { 0x00000001, gk20a_clk_new },
b7a9369a 1715 .fb = { 0x00000001, gk20a_fb_new },
8d056d99 1716 .fuse = { 0x00000001, gf100_fuse_new },
d9691a22 1717 .imem = { 0x00000001, gk20a_instmem_new },
0afc1c4c 1718 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1719 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1720 .mmu = { 0x00000001, gk20a_mmu_new },
e4b15b4c 1721 .pmu = { 0x00000001, gk20a_pmu_new },
26fbb4c8 1722 .privring = { 0x00000001, gk20a_privring_new },
9aad54d5 1723 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 1724 .top = { 0x00000001, gk104_top_new },
d07be5d7 1725 .volt = { 0x00000001, gk20a_volt_new },
50551b15 1726 .ce = { 0x00000004, gk104_ce_new },
09f409d7 1727 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1728 .fifo = { 0x00000001, gk20a_fifo_new },
864d37c3 1729 .gr = { 0x00000001, gk20a_gr_new },
8d6461d8 1730 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1731};
1732
1733static const struct nvkm_device_chip
1734nvf0_chipset = {
1735 .name = "GK110",
917b24a3 1736 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1737 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1738 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1739 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1740 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1741 .fb = { 0x00000001, gk110_fb_new },
8d056d99 1742 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1743 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1744 .i2c = { 0x00000001, gk110_i2c_new },
4dea1a96 1745 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1746 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1747 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1748 .mc = { 0x00000001, gk104_mc_new },
6dd123ba 1749 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1750 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1751 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1752 .pmu = { 0x00000001, gk110_pmu_new },
26fbb4c8 1753 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1754 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1755 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1756 .top = { 0x00000001, gk104_top_new },
d07be5d7 1757 .volt = { 0x00000001, gk104_volt_new },
50551b15 1758 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1759 .disp = { 0x00000001, gk110_disp_new },
09f409d7 1760 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1761 .fifo = { 0x00000001, gk110_fifo_new },
864d37c3 1762 .gr = { 0x00000001, gk110_gr_new },
96321606 1763 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1764 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1765 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1766 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1767};
1768
1769static const struct nvkm_device_chip
1770nvf1_chipset = {
1771 .name = "GK110B",
917b24a3 1772 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1773 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1774 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1775 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1776 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1777 .fb = { 0x00000001, gk110_fb_new },
8d056d99 1778 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1779 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1780 .i2c = { 0x00000001, gk110_i2c_new },
4dea1a96 1781 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1782 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1783 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1784 .mc = { 0x00000001, gk104_mc_new },
6dd123ba 1785 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1786 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1787 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1788 .pmu = { 0x00000001, gk110_pmu_new },
26fbb4c8 1789 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1790 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1791 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1792 .top = { 0x00000001, gk104_top_new },
d07be5d7 1793 .volt = { 0x00000001, gk104_volt_new },
50551b15 1794 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1795 .disp = { 0x00000001, gk110_disp_new },
09f409d7 1796 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1797 .fifo = { 0x00000001, gk110_fifo_new },
864d37c3 1798 .gr = { 0x00000001, gk110b_gr_new },
96321606 1799 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1800 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1801 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1802 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1803};
1804
1805static const struct nvkm_device_chip
1806nv106_chipset = {
1807 .name = "GK208B",
917b24a3 1808 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1809 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1810 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1811 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1812 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1813 .fb = { 0x00000001, gk110_fb_new },
8d056d99 1814 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1815 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1816 .i2c = { 0x00000001, gk110_i2c_new },
4dea1a96 1817 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1818 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1819 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1820 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1821 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1822 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1823 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1824 .pmu = { 0x00000001, gk208_pmu_new },
26fbb4c8 1825 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1826 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1827 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1828 .top = { 0x00000001, gk104_top_new },
d07be5d7 1829 .volt = { 0x00000001, gk104_volt_new },
50551b15 1830 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1831 .disp = { 0x00000001, gk110_disp_new },
09f409d7 1832 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1833 .fifo = { 0x00000001, gk208_fifo_new },
864d37c3 1834 .gr = { 0x00000001, gk208_gr_new },
96321606 1835 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1836 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1837 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1838 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1839};
1840
1841static const struct nvkm_device_chip
1842nv108_chipset = {
1843 .name = "GK208",
917b24a3 1844 .bar = { 0x00000001, gf100_bar_new },
e07f50d3 1845 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1846 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1847 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1848 .devinit = { 0x00000001, gf100_devinit_new },
b7a9369a 1849 .fb = { 0x00000001, gk110_fb_new },
8d056d99 1850 .fuse = { 0x00000001, gf100_fuse_new },
01055c01 1851 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1852 .i2c = { 0x00000001, gk110_i2c_new },
4dea1a96 1853 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1854 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1855 .ltc = { 0x00000001, gk104_ltc_new },
1fc2fddf 1856 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1857 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1858 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1859 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1860 .pmu = { 0x00000001, gk208_pmu_new },
26fbb4c8 1861 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1862 .therm = { 0x00000001, gk104_therm_new },
9aad54d5 1863 .timer = { 0x00000001, nv41_timer_new },
601c2a06 1864 .top = { 0x00000001, gk104_top_new },
d07be5d7 1865 .volt = { 0x00000001, gk104_volt_new },
50551b15 1866 .ce = { 0x00000007, gk104_ce_new },
a7f000ec 1867 .disp = { 0x00000001, gk110_disp_new },
09f409d7 1868 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1869 .fifo = { 0x00000001, gk208_fifo_new },
864d37c3 1870 .gr = { 0x00000001, gk208_gr_new },
96321606 1871 .mspdec = { 0x00000001, gk104_mspdec_new },
07a356bb 1872 .msppp = { 0x00000001, gf100_msppp_new },
b15147bd 1873 .msvld = { 0x00000001, gk104_msvld_new },
8d6461d8 1874 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1875};
1876
1877static const struct nvkm_device_chip
1878nv117_chipset = {
1879 .name = "GM107",
917b24a3 1880 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 1881 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1882 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1883 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1884 .devinit = { 0x00000001, gm107_devinit_new },
b7a9369a 1885 .fb = { 0x00000001, gm107_fb_new },
8d056d99 1886 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 1887 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1888 .i2c = { 0x00000001, gk110_i2c_new },
4dea1a96 1889 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1890 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1891 .ltc = { 0x00000001, gm107_ltc_new },
1fc2fddf 1892 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1893 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1894 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1895 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1896 .pmu = { 0x00000001, gm107_pmu_new },
26fbb4c8 1897 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1898 .therm = { 0x00000001, gm107_therm_new },
9aad54d5 1899 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 1900 .top = { 0x00000001, gk104_top_new },
d07be5d7 1901 .volt = { 0x00000001, gk104_volt_new },
50551b15 1902 .ce = { 0x00000005, gm107_ce_new },
a7f000ec 1903 .disp = { 0x00000001, gm107_disp_new },
09f409d7 1904 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1905 .fifo = { 0x00000001, gm107_fifo_new },
864d37c3 1906 .gr = { 0x00000001, gm107_gr_new },
f8aeb133 1907 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 1908 .nvenc = { 0x00000001, gm107_nvenc_new },
8d6461d8 1909 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 1910};
1911
f9e20294
BS		 1912static const struct nvkm_device_chip
1913nv118_chipset = {
1914 .name = "GM108",
917b24a3 1915 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 1916 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1917 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 1918 .clk = { 0x00000001, gk104_clk_new },
4a34fd0e 1919 .devinit = { 0x00000001, gm107_devinit_new },
b7a9369a 1920 .fb = { 0x00000001, gm107_fb_new },
8d056d99 1921 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 1922 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1923 .i2c = { 0x00000001, gk110_i2c_new },
4dea1a96 1924 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1925 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1926 .ltc = { 0x00000001, gm107_ltc_new },
1fc2fddf 1927 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1928 .mmu = { 0x00000001, gk104_mmu_new },
0a7bff10 1929 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1930 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1931 .pmu = { 0x00000001, gm107_pmu_new },
26fbb4c8 1932 .privring = { 0x00000001, gk104_privring_new },
0aec69c7 1933 .therm = { 0x00000001, gm107_therm_new },
9aad54d5 1934 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 1935 .top = { 0x00000001, gk104_top_new },
d07be5d7 1936 .volt = { 0x00000001, gk104_volt_new },
50551b15 1937 .ce = { 0x00000005, gm107_ce_new },
a7f000ec 1938 .disp = { 0x00000001, gm107_disp_new },
09f409d7 1939 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1940 .fifo = { 0x00000001, gm107_fifo_new },
864d37c3 1941 .gr = { 0x00000001, gm107_gr_new },
8d6461d8 1942 .sw = { 0x00000001, gf100_sw_new },
f9e20294
BS		 1943};
1944
2ed95a4c
BS		 1945static const struct nvkm_device_chip
1946nv120_chipset = {
1947 .name = "GM200",
c288b4de 1948 .acr = { 0x00000001, gm200_acr_new },
917b24a3 1949 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 1950 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1951 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 1952 .devinit = { 0x00000001, gm200_devinit_new },
b7a9369a 1953 .fb = { 0x00000001, gm200_fb_new },
8d056d99 1954 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 1955 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1956 .i2c = { 0x00000001, gm200_i2c_new },
4dea1a96 1957 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1958 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1959 .ltc = { 0x00000001, gm200_ltc_new },
1fc2fddf 1960 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1961 .mmu = { 0x00000001, gm200_mmu_new },
0a7bff10 1962 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1963 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1964 .pmu = { 0x00000001, gm200_pmu_new },
26fbb4c8 1965 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 1966 .therm = { 0x00000001, gm200_therm_new },
9aad54d5 1967 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 1968 .top = { 0x00000001, gk104_top_new },
d07be5d7 1969 .volt = { 0x00000001, gk104_volt_new },
50551b15 1970 .ce = { 0x00000007, gm200_ce_new },
a7f000ec 1971 .disp = { 0x00000001, gm200_disp_new },
09f409d7 1972 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 1973 .fifo = { 0x00000001, gm200_fifo_new },
864d37c3 1974 .gr = { 0x00000001, gm200_gr_new },
f8aeb133 1975 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 1976 .nvenc = { 0x00000003, gm107_nvenc_new },
8d6461d8 1977 .sw = { 0x00000001, gf100_sw_new },
2ed95a4c
BS		 1978};
1979
6cf813fb
BS		 1980static const struct nvkm_device_chip
1981nv124_chipset = {
1982 .name = "GM204",
c288b4de 1983 .acr = { 0x00000001, gm200_acr_new },
917b24a3 1984 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 1985 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 1986 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 1987 .devinit = { 0x00000001, gm200_devinit_new },
b7a9369a 1988 .fb = { 0x00000001, gm200_fb_new },
8d056d99 1989 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 1990 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 1991 .i2c = { 0x00000001, gm200_i2c_new },
4dea1a96 1992 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 1993 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 1994 .ltc = { 0x00000001, gm200_ltc_new },
1fc2fddf 1995 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 1996 .mmu = { 0x00000001, gm200_mmu_new },
0a7bff10 1997 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 1998 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 1999 .pmu = { 0x00000001, gm200_pmu_new },
26fbb4c8 2000 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2001 .therm = { 0x00000001, gm200_therm_new },
9aad54d5 2002 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2003 .top = { 0x00000001, gk104_top_new },
d07be5d7 2004 .volt = { 0x00000001, gk104_volt_new },
50551b15 2005 .ce = { 0x00000007, gm200_ce_new },
a7f000ec 2006 .disp = { 0x00000001, gm200_disp_new },
09f409d7 2007 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2008 .fifo = { 0x00000001, gm200_fifo_new },
864d37c3 2009 .gr = { 0x00000001, gm200_gr_new },
f8aeb133 2010 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2011 .nvenc = { 0x00000003, gm107_nvenc_new },
8d6461d8 2012 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 2013};
2014
2015static const struct nvkm_device_chip
2016nv126_chipset = {
2017 .name = "GM206",
c288b4de 2018 .acr = { 0x00000001, gm200_acr_new },
917b24a3 2019 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2020 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2021 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2022 .devinit = { 0x00000001, gm200_devinit_new },
b7a9369a 2023 .fb = { 0x00000001, gm200_fb_new },
8d056d99 2024 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2025 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2026 .i2c = { 0x00000001, gm200_i2c_new },
4dea1a96 2027 .iccsense = { 0x00000001, gf100_iccsense_new },
d9691a22 2028 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2029 .ltc = { 0x00000001, gm200_ltc_new },
1fc2fddf 2030 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 2031 .mmu = { 0x00000001, gm200_mmu_new },
0a7bff10 2032 .mxm = { 0x00000001, nv50_mxm_new },
9b70cd54 2033 .pci = { 0x00000001, gk104_pci_new },
e4b15b4c 2034 .pmu = { 0x00000001, gm200_pmu_new },
26fbb4c8 2035 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2036 .therm = { 0x00000001, gm200_therm_new },
9aad54d5 2037 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2038 .top = { 0x00000001, gk104_top_new },
d07be5d7 2039 .volt = { 0x00000001, gk104_volt_new },
50551b15 2040 .ce = { 0x00000007, gm200_ce_new },
a7f000ec 2041 .disp = { 0x00000001, gm200_disp_new },
09f409d7 2042 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2043 .fifo = { 0x00000001, gm200_fifo_new },
864d37c3 2044 .gr = { 0x00000001, gm200_gr_new },
f8aeb133 2045 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2046 .nvenc = { 0x00000001, gm107_nvenc_new },
8d6461d8 2047 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 2048};
2049
2050static const struct nvkm_device_chip
2051nv12b_chipset = {
2052 .name = "GM20B",
c288b4de 2053 .acr = { 0x00000001, gm20b_acr_new },
917b24a3 2054 .bar = { 0x00000001, gm20b_bar_new },
d37766e5 2055 .bus = { 0x00000001, gf100_bus_new },
98fd7f83 2056 .clk = { 0x00000001, gm20b_clk_new },
b7a9369a 2057 .fb = { 0x00000001, gm20b_fb_new },
8d056d99 2058 .fuse = { 0x00000001, gm107_fuse_new },
d9691a22 2059 .imem = { 0x00000001, gk20a_instmem_new },
0afc1c4c 2060 .ltc = { 0x00000001, gm200_ltc_new },
1fc2fddf 2061 .mc = { 0x00000001, gk20a_mc_new },
6dd123ba 2062 .mmu = { 0x00000001, gm20b_mmu_new },
e4b15b4c 2063 .pmu = { 0x00000001, gm20b_pmu_new },
26fbb4c8 2064 .privring = { 0x00000001, gk20a_privring_new },
9aad54d5 2065 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2066 .top = { 0x00000001, gk104_top_new },
d07be5d7 2067 .volt = { 0x00000001, gm20b_volt_new },
50551b15 2068 .ce = { 0x00000004, gm200_ce_new },
09f409d7 2069 .dma = { 0x00000001, gf119_dma_new },
8c18138c 2070 .fifo = { 0x00000001, gm200_fifo_new },
864d37c3 2071 .gr = { 0x00000001, gm20b_gr_new },
8d6461d8 2072 .sw = { 0x00000001, gf100_sw_new },
6cf813fb
BS		 2073};
2074
7f53abdb
BS		 2075static const struct nvkm_device_chip
2076nv130_chipset = {
2077 .name = "GP100",
c288b4de 2078 .acr = { 0x00000001, gm200_acr_new },
917b24a3 2079 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2080 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2081 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2082 .devinit = { 0x00000001, gm200_devinit_new },
77689f1b 2083 .fault = { 0x00000001, gp100_fault_new },
b7a9369a 2084 .fb = { 0x00000001, gp100_fb_new },
8d056d99 2085 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2086 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2087 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2088 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2089 .ltc = { 0x00000001, gp100_ltc_new },
1fc2fddf 2090 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2091 .mmu = { 0x00000001, gp100_mmu_new },
0aec69c7 2092 .therm = { 0x00000001, gp100_therm_new },
9b70cd54 2093 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2094 .pmu = { 0x00000001, gm200_pmu_new },
26fbb4c8 2095 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2096 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2097 .top = { 0x00000001, gk104_top_new },
50551b15 2098 .ce = { 0x0000003f, gp100_ce_new },
09f409d7 2099 .dma = { 0x00000001, gf119_dma_new },
a7f000ec 2100 .disp = { 0x00000001, gp100_disp_new },
ab0db2bd 2101 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2102 .gr = { 0x00000001, gp100_gr_new },
f8aeb133 2103 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2104 .nvenc = { 0x00000007, gm107_nvenc_new },
8d6461d8 2105 .sw = { 0x00000001, gf100_sw_new },
7f53abdb
BS		 2106};
2107
17ff521d
BS		 2108static const struct nvkm_device_chip
2109nv132_chipset = {
2110 .name = "GP102",
c288b4de 2111 .acr = { 0x00000001, gp102_acr_new },
917b24a3 2112 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2113 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2114 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2115 .devinit = { 0x00000001, gm200_devinit_new },
77689f1b 2116 .fault = { 0x00000001, gp100_fault_new },
b7a9369a 2117 .fb = { 0x00000001, gp102_fb_new },
8d056d99 2118 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2119 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2120 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2121 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2122 .ltc = { 0x00000001, gp102_ltc_new },
1fc2fddf 2123 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2124 .mmu = { 0x00000001, gp100_mmu_new },
0aec69c7 2125 .therm = { 0x00000001, gp100_therm_new },
9b70cd54 2126 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2127 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2128 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2129 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2130 .top = { 0x00000001, gk104_top_new },
50551b15 2131 .ce = { 0x0000000f, gp102_ce_new },
a7f000ec 2132 .disp = { 0x00000001, gp102_disp_new },
09f409d7 2133 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2134 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2135 .gr = { 0x00000001, gp102_gr_new },
f8aeb133 2136 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2137 .nvenc = { 0x00000003, gm107_nvenc_new },
d1866250 2138 .sec2 = { 0x00000001, gp102_sec2_new },
8d6461d8 2139 .sw = { 0x00000001, gf100_sw_new },
17ff521d
BS		 2140};
2141
cfb083f6
BS		 2142static const struct nvkm_device_chip
2143nv134_chipset = {
2144 .name = "GP104",
c288b4de 2145 .acr = { 0x00000001, gp102_acr_new },
917b24a3 2146 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2147 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2148 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2149 .devinit = { 0x00000001, gm200_devinit_new },
77689f1b 2150 .fault = { 0x00000001, gp100_fault_new },
b7a9369a 2151 .fb = { 0x00000001, gp102_fb_new },
8d056d99 2152 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2153 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2154 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2155 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2156 .ltc = { 0x00000001, gp102_ltc_new },
1fc2fddf 2157 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2158 .mmu = { 0x00000001, gp100_mmu_new },
0aec69c7 2159 .therm = { 0x00000001, gp100_therm_new },
9b70cd54 2160 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2161 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2162 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2163 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2164 .top = { 0x00000001, gk104_top_new },
50551b15 2165 .ce = { 0x0000000f, gp102_ce_new },
a7f000ec 2166 .disp = { 0x00000001, gp102_disp_new },
09f409d7 2167 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2168 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2169 .gr = { 0x00000001, gp104_gr_new },
f8aeb133 2170 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2171 .nvenc = { 0x00000003, gm107_nvenc_new },
d1866250 2172 .sec2 = { 0x00000001, gp102_sec2_new },
8d6461d8 2173 .sw = { 0x00000001, gf100_sw_new },
cfb083f6
BS		 2174};
2175
1fe487d7
BS		 2176static const struct nvkm_device_chip
2177nv136_chipset = {
2178 .name = "GP106",
c288b4de 2179 .acr = { 0x00000001, gp102_acr_new },
917b24a3 2180 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2181 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2182 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2183 .devinit = { 0x00000001, gm200_devinit_new },
77689f1b 2184 .fault = { 0x00000001, gp100_fault_new },
b7a9369a 2185 .fb = { 0x00000001, gp102_fb_new },
8d056d99 2186 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2187 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2188 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2189 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2190 .ltc = { 0x00000001, gp102_ltc_new },
1fc2fddf 2191 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2192 .mmu = { 0x00000001, gp100_mmu_new },
0aec69c7 2193 .therm = { 0x00000001, gp100_therm_new },
9b70cd54 2194 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2195 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2196 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2197 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2198 .top = { 0x00000001, gk104_top_new },
50551b15 2199 .ce = { 0x0000000f, gp102_ce_new },
a7f000ec 2200 .disp = { 0x00000001, gp102_disp_new },
09f409d7 2201 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2202 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2203 .gr = { 0x00000001, gp104_gr_new },
f8aeb133 2204 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2205 .nvenc = { 0x00000001, gm107_nvenc_new },
d1866250 2206 .sec2 = { 0x00000001, gp102_sec2_new },
8d6461d8 2207 .sw = { 0x00000001, gf100_sw_new },
1fe487d7
BS		 2208};
2209
2ebd42bc
BS		 2210static const struct nvkm_device_chip
2211nv137_chipset = {
2212 .name = "GP107",
c288b4de 2213 .acr = { 0x00000001, gp102_acr_new },
917b24a3 2214 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2215 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2216 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2217 .devinit = { 0x00000001, gm200_devinit_new },
77689f1b 2218 .fault = { 0x00000001, gp100_fault_new },
b7a9369a 2219 .fb = { 0x00000001, gp102_fb_new },
8d056d99 2220 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2221 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2222 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2223 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2224 .ltc = { 0x00000001, gp102_ltc_new },
1fc2fddf 2225 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2226 .mmu = { 0x00000001, gp100_mmu_new },
0aec69c7 2227 .therm = { 0x00000001, gp100_therm_new },
9b70cd54 2228 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2229 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2230 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2231 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2232 .top = { 0x00000001, gk104_top_new },
50551b15 2233 .ce = { 0x0000000f, gp102_ce_new },
a7f000ec 2234 .disp = { 0x00000001, gp102_disp_new },
09f409d7 2235 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2236 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2237 .gr = { 0x00000001, gp107_gr_new },
f8aeb133 2238 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2239 .nvenc = { 0x00000003, gm107_nvenc_new },
d1866250 2240 .sec2 = { 0x00000001, gp102_sec2_new },
8d6461d8 2241 .sw = { 0x00000001, gf100_sw_new },
2ebd42bc
BS		 2242};
2243
2659b4ce
IM		 2244static const struct nvkm_device_chip
2245nv138_chipset = {
2246 .name = "GP108",
c288b4de 2247 .acr = { 0x00000001, gp108_acr_new },
917b24a3 2248 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2249 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2250 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2251 .devinit = { 0x00000001, gm200_devinit_new },
77689f1b 2252 .fault = { 0x00000001, gp100_fault_new },
b7a9369a 2253 .fb = { 0x00000001, gp102_fb_new },
8d056d99 2254 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2255 .gpio = { 0x00000001, gk104_gpio_new },
c6ce0861 2256 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2257 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2258 .ltc = { 0x00000001, gp102_ltc_new },
1fc2fddf 2259 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2260 .mmu = { 0x00000001, gp100_mmu_new },
0aec69c7 2261 .therm = { 0x00000001, gp100_therm_new },
9b70cd54 2262 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2263 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2264 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2265 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2266 .top = { 0x00000001, gk104_top_new },
50551b15 2267 .ce = { 0x0000000f, gp102_ce_new },
a7f000ec 2268 .disp = { 0x00000001, gp102_disp_new },
09f409d7 2269 .dma = { 0x00000001, gf119_dma_new },
ab0db2bd 2270 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2271 .gr = { 0x00000001, gp108_gr_new },
f8aeb133 2272 .nvdec = { 0x00000001, gm107_nvdec_new },
d1866250 2273 .sec2 = { 0x00000001, gp108_sec2_new },
8d6461d8 2274 .sw = { 0x00000001, gf100_sw_new },
2659b4ce
IM		 2275};
2276
fa1dbc49
AC		 2277static const struct nvkm_device_chip
2278nv13b_chipset = {
2279 .name = "GP10B",
c288b4de 2280 .acr = { 0x00000001, gp10b_acr_new },
917b24a3 2281 .bar = { 0x00000001, gm20b_bar_new },
d37766e5 2282 .bus = { 0x00000001, gf100_bus_new },
77689f1b 2283 .fault = { 0x00000001, gp10b_fault_new },
b7a9369a 2284 .fb = { 0x00000001, gp10b_fb_new },
8d056d99 2285 .fuse = { 0x00000001, gm107_fuse_new },
d9691a22 2286 .imem = { 0x00000001, gk20a_instmem_new },
0afc1c4c 2287 .ltc = { 0x00000001, gp10b_ltc_new },
1fc2fddf 2288 .mc = { 0x00000001, gp10b_mc_new },
6dd123ba 2289 .mmu = { 0x00000001, gp10b_mmu_new },
e4b15b4c 2290 .pmu = { 0x00000001, gp10b_pmu_new },
26fbb4c8 2291 .privring = { 0x00000001, gp10b_privring_new },
9aad54d5 2292 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2293 .top = { 0x00000001, gk104_top_new },
50551b15 2294 .ce = { 0x00000001, gp100_ce_new },
09f409d7 2295 .dma = { 0x00000001, gf119_dma_new },
8c18138c 2296 .fifo = { 0x00000001, gp100_fifo_new },
864d37c3 2297 .gr = { 0x00000001, gp10b_gr_new },
8d6461d8 2298 .sw = { 0x00000001, gf100_sw_new },
fa1dbc49
AC		 2299};
2300
c1f856bb
BS		 2301static const struct nvkm_device_chip
2302nv140_chipset = {
2303 .name = "GV100",
2541626c 2304 .acr = { 0x00000001, gv100_acr_new },
917b24a3 2305 .bar = { 0x00000001, gm107_bar_new },
e07f50d3 2306 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2307 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2308 .devinit = { 0x00000001, gv100_devinit_new },
77689f1b 2309 .fault = { 0x00000001, gv100_fault_new },
b7a9369a 2310 .fb = { 0x00000001, gv100_fb_new },
8d056d99 2311 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2312 .gpio = { 0x00000001, gk104_gpio_new },
b240b212 2313 .gsp = { 0x00000001, gv100_gsp_new },
c6ce0861 2314 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2315 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2316 .ltc = { 0x00000001, gp102_ltc_new },
1fc2fddf 2317 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2318 .mmu = { 0x00000001, gv100_mmu_new },
9b70cd54 2319 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2320 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2321 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2322 .therm = { 0x00000001, gp100_therm_new },
9aad54d5 2323 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2324 .top = { 0x00000001, gk104_top_new },
f83d1c31 2325 .vfn = { 0x00000001, gv100_vfn_new },
50551b15 2326 .ce = { 0x000001ff, gv100_ce_new },
a7f000ec 2327 .disp = { 0x00000001, gv100_disp_new },
09f409d7 2328 .dma = { 0x00000001, gv100_dma_new },
ab0db2bd 2329 .fifo = { 0x00000001, gv100_fifo_new },
864d37c3 2330 .gr = { 0x00000001, gv100_gr_new },
f8aeb133 2331 .nvdec = { 0x00000001, gm107_nvdec_new },
ee532a8d 2332 .nvenc = { 0x00000007, gm107_nvenc_new },
d1866250 2333 .sec2 = { 0x00000001, gp108_sec2_new },
c1f856bb
BS		 2334};
2335
7ebec5f4
BS		 2336static const struct nvkm_device_chip
2337nv162_chipset = {
2338 .name = "TU102",
c288b4de 2339 .acr = { 0x00000001, tu102_acr_new },
917b24a3 2340 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2341 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2342 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2343 .devinit = { 0x00000001, tu102_devinit_new },
77689f1b 2344 .fault = { 0x00000001, tu102_fault_new },
b4806009 2345 .fb = { 0x00000001, tu102_fb_new },
8d056d99 2346 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2347 .gpio = { 0x00000001, gk104_gpio_new },
015ef618 2348 .gsp = { 0x00000001, tu102_gsp_new },
c6ce0861 2349 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2350 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2351 .ltc = { 0x00000001, gp102_ltc_new },
fe76fe49 2352 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2353 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2354 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2355 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2356 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2357 .therm = { 0x00000001, gp100_therm_new },
9aad54d5 2358 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2359 .top = { 0x00000001, gk104_top_new },
f83d1c31 2360 .vfn = { 0x00000001, tu102_vfn_new },
50551b15 2361 .ce = { 0x0000001f, tu102_ce_new },
a7f000ec 2362 .disp = { 0x00000001, tu102_disp_new },
09f409d7 2363 .dma = { 0x00000001, gv100_dma_new },
ab0db2bd 2364 .fifo = { 0x00000001, tu102_fifo_new },
864d37c3 2365 .gr = { 0x00000001, tu102_gr_new },
796928c6 2366 .nvdec = { 0x00000001, tu102_nvdec_new },
47c9136b 2367 .nvenc = { 0x00000001, tu102_nvenc_new },
d1866250 2368 .sec2 = { 0x00000001, tu102_sec2_new },
7ebec5f4
BS		 2369};
2370
344d9c8f
BS		 2371static const struct nvkm_device_chip
2372nv164_chipset = {
2373 .name = "TU104",
c288b4de 2374 .acr = { 0x00000001, tu102_acr_new },
917b24a3 2375 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2376 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2377 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2378 .devinit = { 0x00000001, tu102_devinit_new },
77689f1b 2379 .fault = { 0x00000001, tu102_fault_new },
b4806009 2380 .fb = { 0x00000001, tu102_fb_new },
8d056d99 2381 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2382 .gpio = { 0x00000001, gk104_gpio_new },
015ef618 2383 .gsp = { 0x00000001, tu102_gsp_new },
c6ce0861 2384 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2385 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2386 .ltc = { 0x00000001, gp102_ltc_new },
fe76fe49 2387 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2388 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2389 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2390 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2391 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2392 .therm = { 0x00000001, gp100_therm_new },
9aad54d5 2393 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2394 .top = { 0x00000001, gk104_top_new },
f83d1c31 2395 .vfn = { 0x00000001, tu102_vfn_new },
50551b15 2396 .ce = { 0x0000001f, tu102_ce_new },
a7f000ec 2397 .disp = { 0x00000001, tu102_disp_new },
09f409d7 2398 .dma = { 0x00000001, gv100_dma_new },
ab0db2bd 2399 .fifo = { 0x00000001, tu102_fifo_new },
864d37c3 2400 .gr = { 0x00000001, tu102_gr_new },
796928c6 2401 .nvdec = { 0x00000003, tu102_nvdec_new },
47c9136b 2402 .nvenc = { 0x00000001, tu102_nvenc_new },
d1866250 2403 .sec2 = { 0x00000001, tu102_sec2_new },
344d9c8f
BS		 2404};
2405
2cc0d7c0
BS		 2406static const struct nvkm_device_chip
2407nv166_chipset = {
2408 .name = "TU106",
c288b4de 2409 .acr = { 0x00000001, tu102_acr_new },
917b24a3 2410 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2411 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2412 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2413 .devinit = { 0x00000001, tu102_devinit_new },
77689f1b 2414 .fault = { 0x00000001, tu102_fault_new },
b4806009 2415 .fb = { 0x00000001, tu102_fb_new },
8d056d99 2416 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2417 .gpio = { 0x00000001, gk104_gpio_new },
015ef618 2418 .gsp = { 0x00000001, tu102_gsp_new },
c6ce0861 2419 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2420 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2421 .ltc = { 0x00000001, gp102_ltc_new },
fe76fe49 2422 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2423 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2424 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2425 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2426 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2427 .therm = { 0x00000001, gp100_therm_new },
9aad54d5 2428 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2429 .top = { 0x00000001, gk104_top_new },
f83d1c31 2430 .vfn = { 0x00000001, tu102_vfn_new },
50551b15 2431 .ce = { 0x0000001f, tu102_ce_new },
a7f000ec 2432 .disp = { 0x00000001, tu102_disp_new },
09f409d7 2433 .dma = { 0x00000001, gv100_dma_new },
ab0db2bd 2434 .fifo = { 0x00000001, tu102_fifo_new },
864d37c3 2435 .gr = { 0x00000001, tu102_gr_new },
796928c6 2436 .nvdec = { 0x00000007, tu102_nvdec_new },
47c9136b 2437 .nvenc = { 0x00000001, tu102_nvenc_new },
d1866250 2438 .sec2 = { 0x00000001, tu102_sec2_new },
2cc0d7c0
BS		 2439};
2440
e15b682a
BS		 2441static const struct nvkm_device_chip
2442nv167_chipset = {
2443 .name = "TU117",
c288b4de 2444 .acr = { 0x00000001, tu102_acr_new },
917b24a3 2445 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2446 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2447 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2448 .devinit = { 0x00000001, tu102_devinit_new },
77689f1b 2449 .fault = { 0x00000001, tu102_fault_new },
b4806009 2450 .fb = { 0x00000001, tu102_fb_new },
8d056d99 2451 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2452 .gpio = { 0x00000001, gk104_gpio_new },
015ef618 2453 .gsp = { 0x00000001, tu116_gsp_new },
c6ce0861 2454 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2455 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2456 .ltc = { 0x00000001, gp102_ltc_new },
fe76fe49 2457 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2458 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2459 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2460 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2461 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2462 .therm = { 0x00000001, gp100_therm_new },
9aad54d5 2463 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2464 .top = { 0x00000001, gk104_top_new },
f83d1c31 2465 .vfn = { 0x00000001, tu102_vfn_new },
50551b15 2466 .ce = { 0x0000001f, tu102_ce_new },
a7f000ec 2467 .disp = { 0x00000001, tu102_disp_new },
09f409d7 2468 .dma = { 0x00000001, gv100_dma_new },
ab0db2bd 2469 .fifo = { 0x00000001, tu102_fifo_new },
864d37c3 2470 .gr = { 0x00000001, tu102_gr_new },
796928c6 2471 .nvdec = { 0x00000001, tu102_nvdec_new },
47c9136b 2472 .nvenc = { 0x00000001, tu102_nvenc_new },
d1866250 2473 .sec2 = { 0x00000001, tu102_sec2_new },
e15b682a
BS		 2474};
2475
75dec321
BS		 2476static const struct nvkm_device_chip
2477nv168_chipset = {
2478 .name = "TU116",
c288b4de 2479 .acr = { 0x00000001, tu102_acr_new },
917b24a3 2480 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2481 .bios = { 0x00000001, nvkm_bios_new },
d37766e5 2482 .bus = { 0x00000001, gf100_bus_new },
4a34fd0e 2483 .devinit = { 0x00000001, tu102_devinit_new },
77689f1b 2484 .fault = { 0x00000001, tu102_fault_new },
b4806009 2485 .fb = { 0x00000001, tu102_fb_new },
8d056d99 2486 .fuse = { 0x00000001, gm107_fuse_new },
01055c01 2487 .gpio = { 0x00000001, gk104_gpio_new },
015ef618 2488 .gsp = { 0x00000001, tu116_gsp_new },
c6ce0861 2489 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2490 .imem = { 0x00000001, nv50_instmem_new },
0afc1c4c 2491 .ltc = { 0x00000001, gp102_ltc_new },
fe76fe49 2492 .mc = { 0x00000001, gp100_mc_new },
6dd123ba 2493 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2494 .pci = { 0x00000001, gp100_pci_new },
e4b15b4c 2495 .pmu = { 0x00000001, gp102_pmu_new },
26fbb4c8 2496 .privring = { 0x00000001, gm200_privring_new },
0aec69c7 2497 .therm = { 0x00000001, gp100_therm_new },
9aad54d5 2498 .timer = { 0x00000001, gk20a_timer_new },
601c2a06 2499 .top = { 0x00000001, gk104_top_new },
f83d1c31 2500 .vfn = { 0x00000001, tu102_vfn_new },
50551b15 2501 .ce = { 0x0000001f, tu102_ce_new },
a7f000ec 2502 .disp = { 0x00000001, tu102_disp_new },
09f409d7 2503 .dma = { 0x00000001, gv100_dma_new },
ab0db2bd 2504 .fifo = { 0x00000001, tu102_fifo_new },
864d37c3 2505 .gr = { 0x00000001, tu102_gr_new },
796928c6 2506 .nvdec = { 0x00000001, tu102_nvdec_new },
47c9136b 2507 .nvenc = { 0x00000001, tu102_nvenc_new },
d1866250 2508 .sec2 = { 0x00000001, tu102_sec2_new },
75dec321
BS		 2509};
2510
3b050680
BS		 2511static const struct nvkm_device_chip
2512nv170_chipset = {
2513 .name = "GA100",
917b24a3 2514 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2515 .bios = { 0x00000001, nvkm_bios_new },
4a34fd0e 2516 .devinit = { 0x00000001, ga100_devinit_new },
e5f92c87 2517 .fault = { 0x00000001, tu102_fault_new },
b7a9369a 2518 .fb = { 0x00000001, ga100_fb_new },
01055c01 2519 .gpio = { 0x00000001, gk104_gpio_new },
015ef618 2520 .gsp = { 0x00000001, ga100_gsp_new },
c6ce0861 2521 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2522 .imem = { 0x00000001, nv50_instmem_new },
1fc2fddf 2523 .mc = { 0x00000001, ga100_mc_new },
6dd123ba 2524 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2525 .pci = { 0x00000001, gp100_pci_new },
26fbb4c8 2526 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2527 .timer = { 0x00000001, gk20a_timer_new },
f6df392d 2528 .top = { 0x00000001, ga100_top_new },
f83d1c31 2529 .vfn = { 0x00000001, ga100_vfn_new },
05d271c3 2530 .ce = { 0x000003ff, ga100_ce_new },
7f4f35ea 2531 .fifo = { 0x00000001, ga100_fifo_new },
142cd602 2532 .nvdec = { 0x0000001f, ga100_nvdec_new },
ca968634 2533 .nvjpg = { 0x00000001, ga100_nvjpg_new },
015185cc 2534 .ofa = { 0x00000001, ga100_ofa_new },
3b050680
BS		 2535};
2536
2537static const struct nvkm_device_chip
2538nv172_chipset = {
2539 .name = "GA102",
4b569ded 2540 .acr = { 0x00000001, ga102_acr_new },
917b24a3 2541 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2542 .bios = { 0x00000001, nvkm_bios_new },
4a34fd0e 2543 .devinit = { 0x00000001, ga100_devinit_new },
e5f92c87 2544 .fault = { 0x00000001, tu102_fault_new },
b7a9369a 2545 .fb = { 0x00000001, ga102_fb_new },
01055c01 2546 .gpio = { 0x00000001, ga102_gpio_new },
4b569ded 2547 .gsp = { 0x00000001, ga102_gsp_new },
c6ce0861 2548 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2549 .imem = { 0x00000001, nv50_instmem_new },
21e938d0 2550 .ltc = { 0x00000001, ga102_ltc_new },
1fc2fddf 2551 .mc = { 0x00000001, ga100_mc_new },
6dd123ba 2552 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2553 .pci = { 0x00000001, gp100_pci_new },
26fbb4c8 2554 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2555 .timer = { 0x00000001, gk20a_timer_new },
f6df392d 2556 .top = { 0x00000001, ga100_top_new },
f83d1c31 2557 .vfn = { 0x00000001, ga100_vfn_new },
05d271c3 2558 .ce = { 0x0000001f, ga102_ce_new },
a7f000ec 2559 .disp = { 0x00000001, ga102_disp_new },
09f409d7 2560 .dma = { 0x00000001, gv100_dma_new },
49b2dfc0 2561 .fifo = { 0x00000001, ga102_fifo_new },
c4bdac75 2562 .gr = { 0x00000001, ga102_gr_new },
796928c6 2563 .nvdec = { 0x00000003, ga102_nvdec_new },
08ab88f5 2564 .nvenc = { 0x00000001, ga102_nvenc_new },
015185cc 2565 .ofa = { 0x00000001, ga102_ofa_new },
4b569ded 2566 .sec2 = { 0x00000001, ga102_sec2_new },
3b050680
BS		 2567};
2568
c20ee574
KH		 2569static const struct nvkm_device_chip
2570nv173_chipset = {
2571 .name = "GA103",
4b569ded 2572 .acr = { 0x00000001, ga102_acr_new },
c20ee574
KH		 2573 .bar = { 0x00000001, tu102_bar_new },
2574 .bios = { 0x00000001, nvkm_bios_new },
2575 .devinit = { 0x00000001, ga100_devinit_new },
e5f92c87 2576 .fault = { 0x00000001, tu102_fault_new },
c20ee574
KH		 2577 .fb = { 0x00000001, ga102_fb_new },
2578 .gpio = { 0x00000001, ga102_gpio_new },
4b569ded 2579 .gsp = { 0x00000001, ga102_gsp_new },
c20ee574
KH		 2580 .i2c = { 0x00000001, gm200_i2c_new },
2581 .imem = { 0x00000001, nv50_instmem_new },
21e938d0 2582 .ltc = { 0x00000001, ga102_ltc_new },
c20ee574
KH		 2583 .mc = { 0x00000001, ga100_mc_new },
2584 .mmu = { 0x00000001, tu102_mmu_new },
2585 .pci = { 0x00000001, gp100_pci_new },
2586 .privring = { 0x00000001, gm200_privring_new },
2587 .timer = { 0x00000001, gk20a_timer_new },
2588 .top = { 0x00000001, ga100_top_new },
f83d1c31 2589 .vfn = { 0x00000001, ga100_vfn_new },
05d271c3 2590 .ce = { 0x0000001f, ga102_ce_new },
c20ee574
KH		 2591 .disp = { 0x00000001, ga102_disp_new },
2592 .dma = { 0x00000001, gv100_dma_new },
2593 .fifo = { 0x00000001, ga102_fifo_new },
c4bdac75 2594 .gr = { 0x00000001, ga102_gr_new },
796928c6 2595 .nvdec = { 0x00000003, ga102_nvdec_new },
08ab88f5 2596 .nvenc = { 0x00000001, ga102_nvenc_new },
015185cc 2597 .ofa = { 0x00000001, ga102_ofa_new },
4b569ded 2598 .sec2 = { 0x00000001, ga102_sec2_new },
c20ee574
KH		 2599};
2600
3b050680
BS		 2601static const struct nvkm_device_chip
2602nv174_chipset = {
2603 .name = "GA104",
4b569ded 2604 .acr = { 0x00000001, ga102_acr_new },
917b24a3 2605 .bar = { 0x00000001, tu102_bar_new },
e07f50d3 2606 .bios = { 0x00000001, nvkm_bios_new },
4a34fd0e 2607 .devinit = { 0x00000001, ga100_devinit_new },
e5f92c87 2608 .fault = { 0x00000001, tu102_fault_new },
b7a9369a 2609 .fb = { 0x00000001, ga102_fb_new },
01055c01 2610 .gpio = { 0x00000001, ga102_gpio_new },
4b569ded 2611 .gsp = { 0x00000001, ga102_gsp_new },
c6ce0861 2612 .i2c = { 0x00000001, gm200_i2c_new },
d9691a22 2613 .imem = { 0x00000001, nv50_instmem_new },
21e938d0 2614 .ltc = { 0x00000001, ga102_ltc_new },
1fc2fddf 2615 .mc = { 0x00000001, ga100_mc_new },
6dd123ba 2616 .mmu = { 0x00000001, tu102_mmu_new },
9b70cd54 2617 .pci = { 0x00000001, gp100_pci_new },
26fbb4c8 2618 .privring = { 0x00000001, gm200_privring_new },
9aad54d5 2619 .timer = { 0x00000001, gk20a_timer_new },
f6df392d 2620 .top = { 0x00000001, ga100_top_new },
f83d1c31 2621 .vfn = { 0x00000001, ga100_vfn_new },
05d271c3 2622 .ce = { 0x0000001f, ga102_ce_new },
a7f000ec 2623 .disp = { 0x00000001, ga102_disp_new },
09f409d7 2624 .dma = { 0x00000001, gv100_dma_new },
49b2dfc0 2625 .fifo = { 0x00000001, ga102_fifo_new },
c4bdac75 2626 .gr = { 0x00000001, ga102_gr_new },
796928c6 2627 .nvdec = { 0x00000003, ga102_nvdec_new },
08ab88f5 2628 .nvenc = { 0x00000001, ga102_nvenc_new },
015185cc 2629 .ofa = { 0x00000001, ga102_ofa_new },
4b569ded 2630 .sec2 = { 0x00000001, ga102_sec2_new },
3b050680
BS		 2631};
2632
46741e4f
BS		 2633static const struct nvkm_device_chip
2634nv176_chipset = {
2635 .name = "GA106",
4b569ded 2636 .acr = { 0x00000001, ga102_acr_new },
46741e4f
BS		 2637 .bar = { 0x00000001, tu102_bar_new },
2638 .bios = { 0x00000001, nvkm_bios_new },
2639 .devinit = { 0x00000001, ga100_devinit_new },
e5f92c87 2640 .fault = { 0x00000001, tu102_fault_new },
46741e4f
BS		 2641 .fb = { 0x00000001, ga102_fb_new },
2642 .gpio = { 0x00000001, ga102_gpio_new },
4b569ded 2643 .gsp = { 0x00000001, ga102_gsp_new },
46741e4f
BS		 2644 .i2c = { 0x00000001, gm200_i2c_new },
2645 .imem = { 0x00000001, nv50_instmem_new },
21e938d0 2646 .ltc = { 0x00000001, ga102_ltc_new },
46741e4f
BS		 2647 .mc = { 0x00000001, ga100_mc_new },
2648 .mmu = { 0x00000001, tu102_mmu_new },
2649 .pci = { 0x00000001, gp100_pci_new },
2650 .privring = { 0x00000001, gm200_privring_new },
2651 .timer = { 0x00000001, gk20a_timer_new },
2652 .top = { 0x00000001, ga100_top_new },
f83d1c31 2653 .vfn = { 0x00000001, ga100_vfn_new },
05d271c3 2654 .ce = { 0x0000001f, ga102_ce_new },
46741e4f
BS		 2655 .disp = { 0x00000001, ga102_disp_new },
2656 .dma = { 0x00000001, gv100_dma_new },
2657 .fifo = { 0x00000001, ga102_fifo_new },
c4bdac75 2658 .gr = { 0x00000001, ga102_gr_new },
796928c6 2659 .nvdec = { 0x00000003, ga102_nvdec_new },
08ab88f5 2660 .nvenc = { 0x00000001, ga102_nvenc_new },
015185cc 2661 .ofa = { 0x00000001, ga102_ofa_new },
4b569ded 2662 .sec2 = { 0x00000001, ga102_sec2_new },
46741e4f
BS		 2663};
2664
fa25f28e
BS		 2665static const struct nvkm_device_chip
2666nv177_chipset = {
2667 .name = "GA107",
4b569ded 2668 .acr = { 0x00000001, ga102_acr_new },
fa25f28e
BS		 2669 .bar = { 0x00000001, tu102_bar_new },
2670 .bios = { 0x00000001, nvkm_bios_new },
2671 .devinit = { 0x00000001, ga100_devinit_new },
e5f92c87 2672 .fault = { 0x00000001, tu102_fault_new },
fa25f28e
BS		 2673 .fb = { 0x00000001, ga102_fb_new },
2674 .gpio = { 0x00000001, ga102_gpio_new },
4b569ded 2675 .gsp = { 0x00000001, ga102_gsp_new },
fa25f28e
BS		 2676 .i2c = { 0x00000001, gm200_i2c_new },
2677 .imem = { 0x00000001, nv50_instmem_new },
21e938d0 2678 .ltc = { 0x00000001, ga102_ltc_new },
fa25f28e
BS		 2679 .mc = { 0x00000001, ga100_mc_new },
2680 .mmu = { 0x00000001, tu102_mmu_new },
2681 .pci = { 0x00000001, gp100_pci_new },
2682 .privring = { 0x00000001, gm200_privring_new },
2683 .timer = { 0x00000001, gk20a_timer_new },
2684 .top = { 0x00000001, ga100_top_new },
f83d1c31 2685 .vfn = { 0x00000001, ga100_vfn_new },
05d271c3 2686 .ce = { 0x0000001f, ga102_ce_new },
fa25f28e
BS		 2687 .disp = { 0x00000001, ga102_disp_new },
2688 .dma = { 0x00000001, gv100_dma_new },
49b2dfc0 2689 .fifo = { 0x00000001, ga102_fifo_new },
c4bdac75 2690 .gr = { 0x00000001, ga102_gr_new },
796928c6 2691 .nvdec = { 0x00000003, ga102_nvdec_new },
08ab88f5 2692 .nvenc = { 0x00000001, ga102_nvenc_new },
015185cc 2693 .ofa = { 0x00000001, ga102_ofa_new },
4b569ded 2694 .sec2 = { 0x00000001, ga102_sec2_new },
fa25f28e
BS		 2695};
2696
176fdcbd
BS		 2697static const struct nvkm_device_chip
2698nv192_chipset = {
2699 .name = "AD102",
5bf02571 2700 .bar = { 0x00000001, tu102_bar_new },
176fdcbd
BS		 2701 .bios = { 0x00000001, nvkm_bios_new },
2702 .devinit = { 0x00000001, ga100_devinit_new },
5bf02571 2703 .fault = { 0x00000001, tu102_fault_new },
176fdcbd
BS		 2704 .fb = { 0x00000001, ga102_fb_new },
2705 .gsp = { 0x00000001, ad102_gsp_new },
5bf02571
BS		 2706 .imem = { 0x00000001, nv50_instmem_new },
2707 .mmu = { 0x00000001, tu102_mmu_new },
176fdcbd
BS		 2708 .pci = { 0x00000001, gp100_pci_new },
2709 .timer = { 0x00000001, gk20a_timer_new },
830531e9 2710 .vfn = { 0x00000001, ga100_vfn_new },
b5ce219a 2711 .ce = { 0x0000001f, ga102_ce_new },
9e994444
BS		 2712 .disp = { 0x00000001, ad102_disp_new },
2713 .dma = { 0x00000001, gv100_dma_new },
2a77d015 2714 .fifo = { 0x00000001, ga102_fifo_new },
361c3cd8 2715 .gr = { 0x00000001, ad102_gr_new },
142cd602 2716 .nvdec = { 0x0000000f, ad102_nvdec_new },
08ab88f5 2717 .nvenc = { 0x00000007, ad102_nvenc_new },
ca968634 2718 .nvjpg = { 0x0000000f, ad102_nvjpg_new },
015185cc 2719 .ofa = { 0x00000001, ad102_ofa_new },
176fdcbd
BS		 2720 .sec2 = { 0x00000001, ga102_sec2_new },
2721};
2722
2723static const struct nvkm_device_chip
2724nv193_chipset = {
2725 .name = "AD103",
5bf02571 2726 .bar = { 0x00000001, tu102_bar_new },
176fdcbd
BS		 2727 .bios = { 0x00000001, nvkm_bios_new },
2728 .devinit = { 0x00000001, ga100_devinit_new },
5bf02571 2729 .fault = { 0x00000001, tu102_fault_new },
176fdcbd
BS		 2730 .fb = { 0x00000001, ga102_fb_new },
2731 .gsp = { 0x00000001, ad102_gsp_new },
5bf02571
BS		 2732 .imem = { 0x00000001, nv50_instmem_new },
2733 .mmu = { 0x00000001, tu102_mmu_new },
176fdcbd
BS		 2734 .pci = { 0x00000001, gp100_pci_new },
2735 .timer = { 0x00000001, gk20a_timer_new },
830531e9 2736 .vfn = { 0x00000001, ga100_vfn_new },
b5ce219a 2737 .ce = { 0x0000001f, ga102_ce_new },
9e994444
BS		 2738 .disp = { 0x00000001, ad102_disp_new },
2739 .dma = { 0x00000001, gv100_dma_new },
2a77d015 2740 .fifo = { 0x00000001, ga102_fifo_new },
361c3cd8 2741 .gr = { 0x00000001, ad102_gr_new },
142cd602 2742 .nvdec = { 0x0000000f, ad102_nvdec_new },
08ab88f5 2743 .nvenc = { 0x00000007, ad102_nvenc_new },
ca968634 2744 .nvjpg = { 0x0000000f, ad102_nvjpg_new },
015185cc 2745 .ofa = { 0x00000001, ad102_ofa_new },
176fdcbd
BS		 2746 .sec2 = { 0x00000001, ga102_sec2_new },
2747};
2748
2749static const struct nvkm_device_chip
2750nv194_chipset = {
2751 .name = "AD104",
5bf02571 2752 .bar = { 0x00000001, tu102_bar_new },
176fdcbd
BS		 2753 .bios = { 0x00000001, nvkm_bios_new },
2754 .devinit = { 0x00000001, ga100_devinit_new },
5bf02571 2755 .fault = { 0x00000001, tu102_fault_new },
176fdcbd
BS		 2756 .fb = { 0x00000001, ga102_fb_new },
2757 .gsp = { 0x00000001, ad102_gsp_new },
5bf02571
BS		 2758 .imem = { 0x00000001, nv50_instmem_new },
2759 .mmu = { 0x00000001, tu102_mmu_new },
176fdcbd
BS		 2760 .pci = { 0x00000001, gp100_pci_new },
2761 .timer = { 0x00000001, gk20a_timer_new },
830531e9 2762 .vfn = { 0x00000001, ga100_vfn_new },
b5ce219a 2763 .ce = { 0x0000001f, ga102_ce_new },
9e994444
BS		 2764 .disp = { 0x00000001, ad102_disp_new },
2765 .dma = { 0x00000001, gv100_dma_new },
2a77d015 2766 .fifo = { 0x00000001, ga102_fifo_new },
361c3cd8 2767 .gr = { 0x00000001, ad102_gr_new },
142cd602 2768 .nvdec = { 0x0000000f, ad102_nvdec_new },
08ab88f5 2769 .nvenc = { 0x00000007, ad102_nvenc_new },
ca968634 2770 .nvjpg = { 0x0000000f, ad102_nvjpg_new },
015185cc 2771 .ofa = { 0x00000001, ad102_ofa_new },
176fdcbd
BS		 2772 .sec2 = { 0x00000001, ga102_sec2_new },
2773};
2774
2775static const struct nvkm_device_chip
2776nv196_chipset = {
2777 .name = "AD106",
5bf02571 2778 .bar = { 0x00000001, tu102_bar_new },
176fdcbd
BS		 2779 .bios = { 0x00000001, nvkm_bios_new },
2780 .devinit = { 0x00000001, ga100_devinit_new },
5bf02571 2781 .fault = { 0x00000001, tu102_fault_new },
176fdcbd
BS		 2782 .fb = { 0x00000001, ga102_fb_new },
2783 .gsp = { 0x00000001, ad102_gsp_new },
5bf02571
BS		 2784 .imem = { 0x00000001, nv50_instmem_new },
2785 .mmu = { 0x00000001, tu102_mmu_new },
176fdcbd
BS		 2786 .pci = { 0x00000001, gp100_pci_new },
2787 .timer = { 0x00000001, gk20a_timer_new },
830531e9 2788 .vfn = { 0x00000001, ga100_vfn_new },
b5ce219a 2789 .ce = { 0x0000001f, ga102_ce_new },
9e994444
BS		 2790 .disp = { 0x00000001, ad102_disp_new },
2791 .dma = { 0x00000001, gv100_dma_new },
2a77d015 2792 .fifo = { 0x00000001, ga102_fifo_new },
361c3cd8 2793 .gr = { 0x00000001, ad102_gr_new },
142cd602 2794 .nvdec = { 0x0000000f, ad102_nvdec_new },
08ab88f5 2795 .nvenc = { 0x00000007, ad102_nvenc_new },
ca968634 2796 .nvjpg = { 0x0000000f, ad102_nvjpg_new },
015185cc 2797 .ofa = { 0x00000001, ad102_ofa_new },
176fdcbd
BS		 2798 .sec2 = { 0x00000001, ga102_sec2_new },
2799};
2800
2801static const struct nvkm_device_chip
2802nv197_chipset = {
2803 .name = "AD107",
5bf02571 2804 .bar = { 0x00000001, tu102_bar_new },
176fdcbd
BS		 2805 .bios = { 0x00000001, nvkm_bios_new },
2806 .devinit = { 0x00000001, ga100_devinit_new },
5bf02571 2807 .fault = { 0x00000001, tu102_fault_new },
176fdcbd
BS		 2808 .fb = { 0x00000001, ga102_fb_new },
2809 .gsp = { 0x00000001, ad102_gsp_new },
5bf02571
BS		 2810 .imem = { 0x00000001, nv50_instmem_new },
2811 .mmu = { 0x00000001, tu102_mmu_new },
176fdcbd
BS		 2812 .pci = { 0x00000001, gp100_pci_new },
2813 .timer = { 0x00000001, gk20a_timer_new },
830531e9 2814 .vfn = { 0x00000001, ga100_vfn_new },
b5ce219a 2815 .ce = { 0x0000001f, ga102_ce_new },
9e994444
BS		 2816 .disp = { 0x00000001, ad102_disp_new },
2817 .dma = { 0x00000001, gv100_dma_new },
2a77d015 2818 .fifo = { 0x00000001, ga102_fifo_new },
361c3cd8 2819 .gr = { 0x00000001, ad102_gr_new },
142cd602 2820 .nvdec = { 0x0000000f, ad102_nvdec_new },
08ab88f5 2821 .nvenc = { 0x00000007, ad102_nvenc_new },
ca968634 2822 .nvjpg = { 0x0000000f, ad102_nvjpg_new },
015185cc 2823 .ofa = { 0x00000001, ad102_ofa_new },
176fdcbd
BS		 2824 .sec2 = { 0x00000001, ga102_sec2_new },
2825};
2826
6cf813fb 2827struct nvkm_subdev *
efe2a9ec 2828nvkm_device_subdev(struct nvkm_device *device, int type, int inst)
6cf813fb 2829{
efe2a9ec 2830 struct nvkm_subdev *subdev;
6cf813fb 2831
efe2a9ec 2832 list_for_each_entry(subdev, &device->subdev, head) {
5ef25f06 2833 if (subdev->type == type && subdev->inst == inst)
efe2a9ec 2834 return subdev;
6cf813fb 2835 }
efe2a9ec 2836
6cf813fb
BS		 2837 return NULL;
2838}
2839
2840struct nvkm_engine *
efe2a9ec 2841nvkm_device_engine(struct nvkm_device *device, int type, int inst)
6cf813fb 2842{
efe2a9ec
BS		 2843 struct nvkm_subdev *subdev = nvkm_device_subdev(device, type, inst);
2844 if (subdev && subdev->func == &nvkm_engine)
2845 return container_of(subdev, struct nvkm_engine, subdev);
6cf813fb
BS		 2846 return NULL;
2847}
2848
a1e88736
BS		 2849int
2850nvkm_device_fini(struct nvkm_device *device, bool suspend)
066a5d09 2851{
6cf813fb
BS		 2852 const char *action = suspend ? "suspend" : "fini";
2853 struct nvkm_subdev *subdev;
54d10db1 2854 int ret;
6cf813fb
BS		 2855 s64 time;
2856
2857 nvdev_trace(device, "%s running...\n", action);
2858 time = ktime_to_us(ktime_get());
2859
2860 nvkm_acpi_fini(device);
10caad33 2861
54d10db1
BS		 2862 list_for_each_entry_reverse(subdev, &device->subdev, head) {
2863 ret = nvkm_subdev_fini(subdev, suspend);
2864 if (ret && suspend)
2865 goto fail;
10caad33
BS		 2866 }
2867
b138eca6 2868 nvkm_therm_clkgate_fini(device->therm, suspend);
7974dd1b
BS		 2869
2870 if (device->func->fini)
2871 device->func->fini(device, suspend);
6cf813fb 2872
727fd72f
BS		 2873 nvkm_intr_unarm(device);
2874
6cf813fb
BS		 2875 time = ktime_to_us(ktime_get()) - time;
2876 nvdev_trace(device, "%s completed in %lldus...\n", action, time);
2877 return 0;
2878
10caad33 2879fail:
54d10db1
BS		 2880 list_for_each_entry_from(subdev, &device->subdev, head) {
2881 int rret = nvkm_subdev_init(subdev);
2882 if (rret)
2883 nvkm_fatal(subdev, "failed restart, %d\n", ret);
2884 }
10caad33 2885
6cf813fb 2886 nvdev_trace(device, "%s failed with %d\n", action, ret);
10caad33 2887 return ret;
066a5d09
BS		 2888}
2889
6cf813fb 2890static int
7974dd1b
BS		 2891nvkm_device_preinit(struct nvkm_device *device)
2892{
6cf813fb 2893 struct nvkm_subdev *subdev;
54d10db1 2894 int ret;
7974dd1b
BS		 2895 s64 time;
2896
2897 nvdev_trace(device, "preinit running...\n");
2898 time = ktime_to_us(ktime_get());
2899
727fd72f
BS		 2900 nvkm_intr_unarm(device);
2901
7974dd1b
BS		 2902 if (device->func->preinit) {
2903 ret = device->func->preinit(device);
2904 if (ret)
2905 goto fail;
2906 }
2907
54d10db1
BS		 2908 list_for_each_entry(subdev, &device->subdev, head) {
2909 ret = nvkm_subdev_preinit(subdev);
2910 if (ret)
2911 goto fail;
6cf813fb
BS		 2912 }
2913
0fa5680c 2914 ret = nvkm_devinit_post(device->devinit);
8de65bd0
BS		 2915 if (ret)
2916 goto fail;
6cf813fb 2917
eec3f6df
BS		 2918 ret = nvkm_top_parse(device);
2919 if (ret)
2920 goto fail;
2921
e3f32495
BS		 2922 ret = nvkm_fb_mem_unlock(device->fb);
2923 if (ret)
2924 goto fail;
2925
7974dd1b
BS		 2926 time = ktime_to_us(ktime_get()) - time;
2927 nvdev_trace(device, "preinit completed in %lldus\n", time);
2928 return 0;
2929
2930fail:
2931 nvdev_error(device, "preinit failed with %d\n", ret);
2932 return ret;
2933}
2934
a1e88736
BS		 2935int
2936nvkm_device_init(struct nvkm_device *device)
066a5d09 2937{
6cf813fb 2938 struct nvkm_subdev *subdev;
54d10db1 2939 int ret;
6cf813fb 2940 s64 time;
ed76a870 2941
7974dd1b
BS		 2942 ret = nvkm_device_preinit(device);
2943 if (ret)
2944 return ret;
2945
6cf813fb
BS		 2946 nvkm_device_fini(device, false);
2947
2948 nvdev_trace(device, "init running...\n");
2949 time = ktime_to_us(ktime_get());
10caad33 2950
727fd72f
BS		 2951 nvkm_intr_rearm(device);
2952
2b700825
BS		 2953 if (device->func->init) {
2954 ret = device->func->init(device);
2955 if (ret)
2956 goto fail;
2957 }
2958
54d10db1
BS		 2959 list_for_each_entry(subdev, &device->subdev, head) {
2960 ret = nvkm_subdev_init(subdev);
2961 if (ret)
2962 goto fail_subdev;
10caad33
BS		 2963 }
2964
6cf813fb 2965 nvkm_acpi_init(device);
b138eca6 2966 nvkm_therm_clkgate_enable(device->therm);
6cf813fb
BS		 2967
2968 time = ktime_to_us(ktime_get()) - time;
2969 nvdev_trace(device, "init completed in %lldus\n", time);
2970 return 0;
2971
2b700825 2972fail_subdev:
54d10db1
BS		 2973 list_for_each_entry_from(subdev, &device->subdev, head)
2974 nvkm_subdev_fini(subdev, false);
2b700825 2975fail:
0529a46a
AC		 2976 nvkm_device_fini(device, false);
2977
6cf813fb 2978 nvdev_error(device, "init failed with %d\n", ret);
10caad33 2979 return ret;
066a5d09
BS		 2980}
2981
e781dc8f
BS		 2982void
2983nvkm_device_del(struct nvkm_device **pdevice)
2984{
2985 struct nvkm_device *device = *pdevice;
54d10db1 2986 struct nvkm_subdev *subdev, *subtmp;
e781dc8f 2987 if (device) {
e781dc8f 2988 mutex_lock(&nv_devices_mutex);
54d10db1 2989
727fd72f
BS		 2990 nvkm_intr_dtor(device);
2991
54d10db1 2992 list_for_each_entry_safe_reverse(subdev, subtmp, &device->subdev, head)
6cf813fb 2993 nvkm_subdev_del(&subdev);
0ac9d210 2994
e781dc8f
BS		 2995 if (device->pri)
2996 iounmap(device->pri);
0ac9d210 2997 list_del(&device->head);
7974dd1b
BS		 2998
2999 if (device->func->dtor)
3000 *pdevice = device->func->dtor(device);
0ac9d210 3001 mutex_unlock(&nv_devices_mutex);
e781dc8f 3002
7974dd1b 3003 kfree(*pdevice);
e781dc8f
BS		 3004 *pdevice = NULL;
3005 }
3006}
3007
dcd292c1 3008/* returns true if the GPU is in the CPU native byte order */
51c05340 3009static inline bool
0f85bbb6 3010nvkm_device_endianness(struct nvkm_device *device)
51c05340 3011{
51c05340 3012#ifdef __BIG_ENDIAN
dcd292c1 3013 const bool big_endian = true;
51c05340 3014#else
dcd292c1 3015 const bool big_endian = false;
51c05340 3016#endif
dcd292c1
KH		 3017
3018 /* Read NV_PMC_BOOT_1, and assume non-functional endian switch if it
3019 * doesn't contain the expected values.
3020 */
3021 u32 pmc_boot_1 = nvkm_rd32(device, 0x000004);
3022 if (pmc_boot_1 && pmc_boot_1 != 0x01000001)
3023 return !big_endian; /* Assume GPU is LE in this case. */
3024
3025 /* 0 means LE and 0x01000001 means BE GPU. Condition is true when
3026 * GPU/CPU endianness don't match.
3027 */
3028 if (big_endian == !pmc_boot_1) {
3029 nvkm_wr32(device, 0x000004, 0x01000001);
3030 nvkm_rd32(device, 0x000000);
3031 if (nvkm_rd32(device, 0x000004) != (big_endian ? 0x01000001 : 0x00000000))
3032 return !big_endian; /* Assume GPU is LE on any unexpected read-back. */
3033 }
3034
3035 /* CPU/GPU endianness should (hopefully) match. */
51c05340
KH		 3036 return true;
3037}
3038
9274f4a9 3039int
7974dd1b
BS		 3040nvkm_device_ctor(const struct nvkm_device_func *func,
3041 const struct nvkm_device_quirk *quirk,
26c9e8ef 3042 struct device *dev, enum nvkm_device_type type, u64 handle,
7974dd1b 3043 const char *name, const char *cfg, const char *dbg,
7974dd1b 3044 struct nvkm_device *device)
9274f4a9 3045{
6cf813fb 3046 struct nvkm_subdev *subdev;
0ac9d210 3047 u64 mmio_base, mmio_size;
2924779b 3048 u32 boot0, boot1, strap;
be0ed63f 3049 int ret = -EEXIST, j;
a2ac09a0 3050 unsigned chipset;
9274f4a9
BS		 3051
3052 mutex_lock(&nv_devices_mutex);
7974dd1b
BS		 3053 if (nvkm_device_find_locked(handle))
3054 goto done;
9274f4a9 3055
7974dd1b 3056 device->func = func;
7974dd1b 3057 device->quirk = quirk;
26c9e8ef
BS		 3058 device->dev = dev;
3059 device->type = type;
7974dd1b 3060 device->handle = handle;
9274f4a9
BS		 3061 device->cfgopt = cfg;
3062 device->dbgopt = dbg;
7974dd1b 3063 device->name = name;
0d5dd3f3 3064 list_add_tail(&device->head, &nv_devices);
68f3f702 3065 device->debug = nvkm_dbgopt(device->dbgopt, "device");
54d10db1 3066 INIT_LIST_HEAD(&device->subdev);
6cf813fb 3067
7e8820fe
BS		 3068 mmio_base = device->func->resource_addr(device, 0);
3069 mmio_size = device->func->resource_size(device, 0);
0ac9d210 3070
b5bd7cf7
BS		 3071 device->pri = ioremap(mmio_base, mmio_size);
3072 if (device->pri == NULL) {
3073 nvdev_error(device, "unable to map PRI\n");
3074 ret = -ENOMEM;
3075 goto done;
24d5ff40 3076 }
0ac9d210 3077
24d5ff40 3078 /* identify the chipset, and determine classes of subdev/engines */
0ac9d210 3079
b5bd7cf7
BS		 3080 /* switch mmio to cpu's native endianness */
3081 if (!nvkm_device_endianness(device)) {
3082 nvdev_error(device,
3083 "Couldn't switch GPU to CPUs endianness\n");
3084 ret = -ENOSYS;
3085 goto done;
3086 }
a2ac09a0 3087
b5bd7cf7 3088 boot0 = nvkm_rd32(device, 0x000000);
a2ac09a0 3089
b5bd7cf7
BS		 3090 /* chipset can be overridden for devel/testing purposes */
3091 chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0);
3092 if (chipset) {
3093 u32 override_boot0;
3094
3095 if (chipset >= 0x10) {
3096 override_boot0 = ((chipset & 0x1ff) << 20);
3097 override_boot0 |= 0x000000a1;
3098 } else {
3099 if (chipset != 0x04)
3100 override_boot0 = 0x20104000;
0ac9d210 3101 else
b5bd7cf7 3102 override_boot0 = 0x20004000;
0ac9d210
BS		 3103 }
3104
b5bd7cf7
BS		 3105 nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n",
3106 boot0, override_boot0);
3107 boot0 = override_boot0;
3108 }
3b050680 3109
b5bd7cf7
BS		 3110 /* determine chipset and derive architecture from it */
3111 if ((boot0 & 0x1f000000) > 0) {
3112 device->chipset = (boot0 & 0x1ff00000) >> 20;
3113 device->chiprev = (boot0 & 0x000000ff);
3114 switch (device->chipset & 0x1f0) {
3115 case 0x010: {
3116 if (0x461 & (1 << (device->chipset & 0xf)))
3117 device->card_type = NV_10;
3118 else
3119 device->card_type = NV_11;
3120 device->chiprev = 0x00;
3b050680 3121 break;
0ac9d210 3122 }
b5bd7cf7
BS		 3123 case 0x020: device->card_type = NV_20; break;
3124 case 0x030: device->card_type = NV_30; break;
3125 case 0x040:
3126 case 0x060: device->card_type = NV_40; break;
3127 case 0x050:
3128 case 0x080:
3129 case 0x090:
3130 case 0x0a0: device->card_type = NV_50; break;
3131 case 0x0c0:
3132 case 0x0d0: device->card_type = NV_C0; break;
3133 case 0x0e0:
3134 case 0x0f0:
3135 case 0x100: device->card_type = NV_E0; break;
3136 case 0x110:
3137 case 0x120: device->card_type = GM100; break;
3138 case 0x130: device->card_type = GP100; break;
3139 case 0x140: device->card_type = GV100; break;
3140 case 0x160: device->card_type = TU100; break;
3141 case 0x170: device->card_type = GA100; break;
3142 case 0x190: device->card_type = AD100; break;
3143 default:
3144 break;
3145 }
3146 } else
3147 if ((boot0 & 0xff00fff0) == 0x20004000) {
3148 if (boot0 & 0x00f00000)
3149 device->chipset = 0x05;
3150 else
3151 device->chipset = 0x04;
3152 device->card_type = NV_04;
3153 }
0ac9d210 3154
b5bd7cf7
BS		 3155 switch (device->chipset) {
3156 case 0x004: device->chip = &nv4_chipset; break;
3157 case 0x005: device->chip = &nv5_chipset; break;
3158 case 0x010: device->chip = &nv10_chipset; break;
3159 case 0x011: device->chip = &nv11_chipset; break;
3160 case 0x015: device->chip = &nv15_chipset; break;
3161 case 0x017: device->chip = &nv17_chipset; break;
3162 case 0x018: device->chip = &nv18_chipset; break;
3163 case 0x01a: device->chip = &nv1a_chipset; break;
3164 case 0x01f: device->chip = &nv1f_chipset; break;
3165 case 0x020: device->chip = &nv20_chipset; break;
3166 case 0x025: device->chip = &nv25_chipset; break;
3167 case 0x028: device->chip = &nv28_chipset; break;
3168 case 0x02a: device->chip = &nv2a_chipset; break;
3169 case 0x030: device->chip = &nv30_chipset; break;
3170 case 0x031: device->chip = &nv31_chipset; break;
3171 case 0x034: device->chip = &nv34_chipset; break;
3172 case 0x035: device->chip = &nv35_chipset; break;
3173 case 0x036: device->chip = &nv36_chipset; break;
3174 case 0x040: device->chip = &nv40_chipset; break;
3175 case 0x041: device->chip = &nv41_chipset; break;
3176 case 0x042: device->chip = &nv42_chipset; break;
3177 case 0x043: device->chip = &nv43_chipset; break;
3178 case 0x044: device->chip = &nv44_chipset; break;
3179 case 0x045: device->chip = &nv45_chipset; break;
3180 case 0x046: device->chip = &nv46_chipset; break;
3181 case 0x047: device->chip = &nv47_chipset; break;
3182 case 0x049: device->chip = &nv49_chipset; break;
3183 case 0x04a: device->chip = &nv4a_chipset; break;
3184 case 0x04b: device->chip = &nv4b_chipset; break;
3185 case 0x04c: device->chip = &nv4c_chipset; break;
3186 case 0x04e: device->chip = &nv4e_chipset; break;
3187 case 0x050: device->chip = &nv50_chipset; break;
3188 case 0x063: device->chip = &nv63_chipset; break;
3189 case 0x067: device->chip = &nv67_chipset; break;
3190 case 0x068: device->chip = &nv68_chipset; break;
3191 case 0x084: device->chip = &nv84_chipset; break;
3192 case 0x086: device->chip = &nv86_chipset; break;
3193 case 0x092: device->chip = &nv92_chipset; break;
3194 case 0x094: device->chip = &nv94_chipset; break;
3195 case 0x096: device->chip = &nv96_chipset; break;
3196 case 0x098: device->chip = &nv98_chipset; break;
3197 case 0x0a0: device->chip = &nva0_chipset; break;
3198 case 0x0a3: device->chip = &nva3_chipset; break;
3199 case 0x0a5: device->chip = &nva5_chipset; break;
3200 case 0x0a8: device->chip = &nva8_chipset; break;
3201 case 0x0aa: device->chip = &nvaa_chipset; break;
3202 case 0x0ac: device->chip = &nvac_chipset; break;
3203 case 0x0af: device->chip = &nvaf_chipset; break;
3204 case 0x0c0: device->chip = &nvc0_chipset; break;
3205 case 0x0c1: device->chip = &nvc1_chipset; break;
3206 case 0x0c3: device->chip = &nvc3_chipset; break;
3207 case 0x0c4: device->chip = &nvc4_chipset; break;
3208 case 0x0c8: device->chip = &nvc8_chipset; break;
3209 case 0x0ce: device->chip = &nvce_chipset; break;
3210 case 0x0cf: device->chip = &nvcf_chipset; break;
3211 case 0x0d7: device->chip = &nvd7_chipset; break;
3212 case 0x0d9: device->chip = &nvd9_chipset; break;
3213 case 0x0e4: device->chip = &nve4_chipset; break;
3214 case 0x0e6: device->chip = &nve6_chipset; break;
3215 case 0x0e7: device->chip = &nve7_chipset; break;
3216 case 0x0ea: device->chip = &nvea_chipset; break;
3217 case 0x0f0: device->chip = &nvf0_chipset; break;
3218 case 0x0f1: device->chip = &nvf1_chipset; break;
3219 case 0x106: device->chip = &nv106_chipset; break;
3220 case 0x108: device->chip = &nv108_chipset; break;
3221 case 0x117: device->chip = &nv117_chipset; break;
3222 case 0x118: device->chip = &nv118_chipset; break;
3223 case 0x120: device->chip = &nv120_chipset; break;
3224 case 0x124: device->chip = &nv124_chipset; break;
3225 case 0x126: device->chip = &nv126_chipset; break;
3226 case 0x12b: device->chip = &nv12b_chipset; break;
3227 case 0x130: device->chip = &nv130_chipset; break;
3228 case 0x132: device->chip = &nv132_chipset; break;
3229 case 0x134: device->chip = &nv134_chipset; break;
3230 case 0x136: device->chip = &nv136_chipset; break;
3231 case 0x137: device->chip = &nv137_chipset; break;
3232 case 0x138: device->chip = &nv138_chipset; break;
3233 case 0x13b: device->chip = &nv13b_chipset; break;
3234 case 0x140: device->chip = &nv140_chipset; break;
3235 case 0x162: device->chip = &nv162_chipset; break;
3236 case 0x164: device->chip = &nv164_chipset; break;
3237 case 0x166: device->chip = &nv166_chipset; break;
3238 case 0x167: device->chip = &nv167_chipset; break;
3239 case 0x168: device->chip = &nv168_chipset; break;
3240 case 0x172: device->chip = &nv172_chipset; break;
3241 case 0x173: device->chip = &nv173_chipset; break;
3242 case 0x174: device->chip = &nv174_chipset; break;
3243 case 0x176: device->chip = &nv176_chipset; break;
3244 case 0x177: device->chip = &nv177_chipset; break;
3245 case 0x192: device->chip = &nv192_chipset; break;
3246 case 0x193: device->chip = &nv193_chipset; break;
3247 case 0x194: device->chip = &nv194_chipset; break;
3248 case 0x196: device->chip = &nv196_chipset; break;
3249 case 0x197: device->chip = &nv197_chipset; break;
3250 default:
3251 if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
3252 switch (device->chipset) {
3253 case 0x170: device->chip = &nv170_chipset; break;
3254 default:
3255 break;
3256 }
3257 }
0ac9d210 3258
b5bd7cf7
BS		 3259 if (!device->chip) {
3260 nvdev_error(device, "unknown chipset (%08x)\n", boot0);
2924779b
KH		 3261 ret = -ENODEV;
3262 goto done;
3263 }
b5bd7cf7
BS		 3264 break;
3265 }
2924779b 3266
b5bd7cf7
BS		 3267 nvdev_info(device, "NVIDIA %s (%08x)\n",
3268 device->chip->name, boot0);
2924779b 3269
b5bd7cf7
BS		 3270 /* vGPU detection */
3271 boot1 = nvkm_rd32(device, 0x0000004);
3272 if (device->card_type >= TU100 && (boot1 & 0x00030000)) {
3273 nvdev_info(device, "vGPUs are not supported\n");
3274 ret = -ENODEV;
3275 goto done;
3276 }
0ac9d210 3277
b5bd7cf7
BS		 3278 /* read strapping information */
3279 strap = nvkm_rd32(device, 0x101000);
3280
3281 /* determine frequency of timing crystal */
3282 if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
3283 (device->chipset >= 0x20 && device->chipset < 0x25))
3284 strap &= 0x00000040;
3285 else
3286 strap &= 0x00400040;
3287
3288 switch (strap) {
3289 case 0x00000000: device->crystal = 13500; break;
3290 case 0x00000040: device->crystal = 14318; break;
3291 case 0x00400000: device->crystal = 27000; break;
3292 case 0x00400040: device->crystal = 25000; break;
0ac9d210
BS		 3293 }
3294
6cf813fb
BS		 3295 if (!device->name)
3296 device->name = device->chip->name;
3297
a1e88736 3298 mutex_init(&device->mutex);
727fd72f 3299 nvkm_intr_ctor(device);
6cf813fb 3300
be0ed63f 3301#define NVKM_LAYOUT_ONCE(type,data,ptr) \
b5bd7cf7 3302 if (device->chip->ptr.inst) { \
f483253f
BS		 3303 WARN_ON(device->chip->ptr.inst != 0x00000001); \
3304 ret = device->chip->ptr.ctor(device, (type), -1, &device->ptr); \
3305 subdev = nvkm_device_subdev(device, (type), 0); \
3306 if (ret) { \
3307 nvkm_subdev_del(&subdev); \
3308 device->ptr = NULL; \
3309 if (ret != -ENODEV) { \
3310 nvdev_error(device, "%s ctor failed: %d\n", \
3311 nvkm_subdev_type[(type)], ret); \
3312 goto done; \
3313 } \
3314 } else { \
3315 subdev->pself = (void **)&device->ptr; \
3316 } \
be0ed63f
BS		 3317 }
3318#define NVKM_LAYOUT_INST(type,data,ptr,cnt) \
f483253f
BS		 3319 WARN_ON(device->chip->ptr.inst & ~((1 << ARRAY_SIZE(device->ptr)) - 1)); \
3320 for (j = 0; device->chip->ptr.inst && j < ARRAY_SIZE(device->ptr); j++) { \
b5bd7cf7 3321 if (device->chip->ptr.inst & BIT(j)) { \
93f43ed8 3322 ret = device->chip->ptr.ctor(device, (type), (j), &device->ptr[j]); \
f483253f
BS		 3323 subdev = nvkm_device_subdev(device, (type), (j)); \
3324 if (ret) { \
3325 nvkm_subdev_del(&subdev); \
3326 device->ptr[j] = NULL; \
3327 if (ret != -ENODEV) { \
3328 nvdev_error(device, "%s%d ctor failed: %d\n", \
3329 nvkm_subdev_type[(type)], (j), ret); \
3330 goto done; \
3331 } \
3332 } else { \
3333 subdev->pself = (void **)&device->ptr[j]; \
3334 } \
3335 } \
be0ed63f 3336 }
f483253f
BS		 3337#include <core/layout.h>
3338#undef NVKM_LAYOUT_INST
3339#undef NVKM_LAYOUT_ONCE
6cf813fb 3340
727fd72f 3341 ret = nvkm_intr_install(device);
9274f4a9 3342done:
b5bd7cf7 3343 if (ret && device->pri) {
0f85bbb6 3344 iounmap(device->pri);
24d5ff40 3345 device->pri = NULL;
24d5ff40 3346 }
9274f4a9
BS		 3347 mutex_unlock(&nv_devices_mutex);
3348 return ret;
3349}
Linux 6.x block layer and io_uring tree(s)