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drm/nvd0/disp: untested LVDS support
[linux-block.git] / drivers / gpu / drm / nouveau / nvd0_display.c
CommitLineData
26f6d88b
BS		 1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
51beb428 25#include <linux/dma-mapping.h>
83fc083c 26
26f6d88b 27#include "drmP.h"
83fc083c 28#include "drm_crtc_helper.h"
26f6d88b
BS		 29
30#include "nouveau_drv.h"
31#include "nouveau_connector.h"
32#include "nouveau_encoder.h"
33#include "nouveau_crtc.h"
438d99e3 34#include "nouveau_fb.h"
3a89cd02 35#include "nv50_display.h"
26f6d88b 36
efd272a7
BS		 37#define MEM_SYNC 0xe0000001
38#define MEM_VRAM 0xe0010000
c0cc92a1 39#include "nouveau_dma.h"
efd272a7 40
26f6d88b
BS		 41struct nvd0_display {
42 struct nouveau_gpuobj *mem;
51beb428
BS		 43 struct {
44 dma_addr_t handle;
45 u32 *ptr;
46 } evo[1];
3a89cd02
BS		 47 struct {
48 struct dcb_entry *dis;
49 struct dcb_entry *ena;
50 int crtc;
51 int pclk;
ff8ff503 52 u16 cfg;
3a89cd02 53 } irq;
26f6d88b
BS		 54};
55
56static struct nvd0_display *
57nvd0_display(struct drm_device *dev)
58{
59 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 return dev_priv->engine.display.priv;
61}
62
51beb428
BS		 63static int
64evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
65{
66 int ret = 0;
67 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
68 nv_wr32(dev, 0x610704 + (id * 0x10), data);
69 nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
70 if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
71 ret = -EBUSY;
72 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
73 return ret;
74}
75
76static u32 *
77evo_wait(struct drm_device *dev, int id, int nr)
78{
79 struct nvd0_display *disp = nvd0_display(dev);
80 u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
81
82 if (put + nr >= (PAGE_SIZE / 4)) {
83 disp->evo[id].ptr[put] = 0x20000000;
84
85 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
86 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
87 NV_ERROR(dev, "evo %d dma stalled\n", id);
88 return NULL;
89 }
90
91 put = 0;
92 }
93
94 return disp->evo[id].ptr + put;
95}
96
97static void
98evo_kick(u32 *push, struct drm_device *dev, int id)
99{
100 struct nvd0_display *disp = nvd0_display(dev);
101 nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
102}
103
104#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
105#define evo_data(p,d) *((p)++) = (d)
106
83fc083c
BS		 107static struct drm_crtc *
108nvd0_display_crtc_get(struct drm_encoder *encoder)
109{
110 return nouveau_encoder(encoder)->crtc;
111}
112
438d99e3
BS		 113/******************************************************************************
114 * CRTC
115 *****************************************************************************/
116static int
117nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
118{
119 struct drm_device *dev = nv_crtc->base.dev;
120 u32 *push, mode;
121
122 mode = 0x00000000;
123 if (on) {
124 /* 0x11: 6bpc dynamic 2x2
125 * 0x13: 8bpc dynamic 2x2
126 * 0x19: 6bpc static 2x2
127 * 0x1b: 8bpc static 2x2
128 * 0x21: 6bpc temporal
129 * 0x23: 8bpc temporal
130 */
131 mode = 0x00000011;
132 }
133
134 push = evo_wait(dev, 0, 4);
135 if (push) {
136 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x300), 1);
137 evo_data(push, mode);
138 if (update) {
139 evo_mthd(push, 0x0080, 1);
140 evo_data(push, 0x00000000);
141 }
142 evo_kick(push, dev, 0);
143 }
144
145 return 0;
146}
147
148static int
149nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, int type, bool update)
150{
151 struct drm_display_mode *mode = &nv_crtc->base.mode;
152 struct drm_device *dev = nv_crtc->base.dev;
f3fdc52d
BS		 153 struct nouveau_connector *nv_connector;
154 u32 *push, outX, outY;
155
156 outX = mode->hdisplay;
157 outY = mode->vdisplay;
158
159 nv_connector = nouveau_crtc_connector_get(nv_crtc);
160 if (nv_connector && nv_connector->native_mode) {
161 struct drm_display_mode *native = nv_connector->native_mode;
162 u32 xratio = (native->hdisplay << 19) / mode->hdisplay;
163 u32 yratio = (native->vdisplay << 19) / mode->vdisplay;
164
165 switch (type) {
166 case DRM_MODE_SCALE_ASPECT:
167 if (xratio > yratio) {
168 outX = (mode->hdisplay * yratio) >> 19;
169 outY = (mode->vdisplay * yratio) >> 19;
170 } else {
171 outX = (mode->hdisplay * xratio) >> 19;
172 outY = (mode->vdisplay * xratio) >> 19;
173 }
174 break;
175 case DRM_MODE_SCALE_FULLSCREEN:
176 outX = native->hdisplay;
177 outY = native->vdisplay;
178 break;
179 default:
180 break;
181 }
182 }
438d99e3
BS		 183
184 push = evo_wait(dev, 0, 16);
185 if (push) {
186 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
f3fdc52d
BS		 187 evo_data(push, (outY << 16) | outX);
188 evo_data(push, (outY << 16) | outX);
189 evo_data(push, (outY << 16) | outX);
438d99e3
BS		 190 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
191 evo_data(push, 0x00000000);
438d99e3
BS		 192 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
193 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
194 if (update) {
195 evo_mthd(push, 0x0080, 1);
196 evo_data(push, 0x00000000);
197 }
198 evo_kick(push, dev, 0);
199 }
200
201 return 0;
202}
203
204static int
205nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
206 int x, int y, bool update)
207{
208 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
209 u32 *push;
210
438d99e3
BS		 211 push = evo_wait(fb->dev, 0, 16);
212 if (push) {
213 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
214 evo_data(push, nvfb->nvbo->bo.offset >> 8);
215 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
216 evo_data(push, (fb->height << 16) | fb->width);
217 evo_data(push, nvfb->r_pitch);
218 evo_data(push, nvfb->r_format);
c0cc92a1 219 evo_data(push, nvfb->r_dma);
c6f2f71d
BS		 220 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
221 evo_data(push, (y << 16) | x);
a46232ee
BS		 222 if (update) {
223 evo_mthd(push, 0x0080, 1);
224 evo_data(push, 0x00000000);
225 }
438d99e3
BS		 226 evo_kick(push, fb->dev, 0);
227 }
228
c0cc92a1 229 nv_crtc->fb.tile_flags = nvfb->r_dma;
438d99e3
BS		 230 return 0;
231}
232
233static void
234nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
235{
236 struct drm_device *dev = nv_crtc->base.dev;
237 u32 *push = evo_wait(dev, 0, 16);
238 if (push) {
239 if (show) {
240 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
241 evo_data(push, 0x85000000);
242 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
243 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
244 evo_data(push, MEM_VRAM);
245 } else {
246 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
247 evo_data(push, 0x05000000);
248 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
249 evo_data(push, 0x00000000);
250 }
251
252 if (update) {
253 evo_mthd(push, 0x0080, 1);
254 evo_data(push, 0x00000000);
255 }
256
257 evo_kick(push, dev, 0);
258 }
259}
260
261static void
262nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
263{
264}
265
266static void
267nvd0_crtc_prepare(struct drm_crtc *crtc)
268{
269 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
270 u32 *push;
271
272 push = evo_wait(crtc->dev, 0, 2);
273 if (push) {
274 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
275 evo_data(push, 0x00000000);
276 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
277 evo_data(push, 0x03000000);
278 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
279 evo_data(push, 0x00000000);
280 evo_kick(push, crtc->dev, 0);
281 }
282
283 nvd0_crtc_cursor_show(nv_crtc, false, false);
284}
285
286static void
287nvd0_crtc_commit(struct drm_crtc *crtc)
288{
289 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
290 u32 *push;
291
292 push = evo_wait(crtc->dev, 0, 32);
293 if (push) {
294 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
295 evo_data(push, nv_crtc->fb.tile_flags);
296 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
297 evo_data(push, 0x83000000);
298 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
299 evo_data(push, 0x00000000);
300 evo_data(push, 0x00000000);
301 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
302 evo_data(push, MEM_VRAM);
8ea0d4aa
BS		 303 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
304 evo_data(push, 0xffffff00);
438d99e3
BS		 305 evo_kick(push, crtc->dev, 0);
306 }
307
308 nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
309}
310
311static bool
312nvd0_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
313 struct drm_display_mode *adjusted_mode)
314{
315 return true;
316}
317
318static int
319nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
320{
321 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
322 int ret;
323
324 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
325 if (ret)
326 return ret;
327
328 if (old_fb) {
329 nvfb = nouveau_framebuffer(old_fb);
330 nouveau_bo_unpin(nvfb->nvbo);
331 }
332
333 return 0;
334}
335
336static int
337nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
338 struct drm_display_mode *mode, int x, int y,
339 struct drm_framebuffer *old_fb)
340{
341 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
342 struct nouveau_connector *nv_connector;
343 u32 htotal = mode->htotal;
344 u32 vtotal = mode->vtotal;
345 u32 hsyncw = mode->hsync_end - mode->hsync_start - 1;
346 u32 vsyncw = mode->vsync_end - mode->vsync_start - 1;
347 u32 hfrntp = mode->hsync_start - mode->hdisplay;
348 u32 vfrntp = mode->vsync_start - mode->vdisplay;
349 u32 hbackp = mode->htotal - mode->hsync_end;
350 u32 vbackp = mode->vtotal - mode->vsync_end;
351 u32 hss2be = hsyncw + hbackp;
352 u32 vss2be = vsyncw + vbackp;
353 u32 hss2de = htotal - hfrntp;
354 u32 vss2de = vtotal - vfrntp;
629c1b92 355 u32 syncs, *push;
438d99e3
BS		 356 int ret;
357
629c1b92
BS		 358 syncs = 0x00000001;
359 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
360 syncs |= 0x00000008;
361 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
362 syncs |= 0x00000010;
363
438d99e3
BS		 364 ret = nvd0_crtc_swap_fbs(crtc, old_fb);
365 if (ret)
366 return ret;
367
368 push = evo_wait(crtc->dev, 0, 64);
369 if (push) {
370 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 5);
629c1b92 371 evo_data(push, 0x00000000);
438d99e3
BS		 372 evo_data(push, (vtotal << 16) | htotal);
373 evo_data(push, (vsyncw << 16) | hsyncw);
374 evo_data(push, (vss2be << 16) | hss2be);
375 evo_data(push, (vss2de << 16) | hss2de);
376 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
377 evo_data(push, 0x00000000); /* ??? */
378 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
379 evo_data(push, mode->clock * 1000);
380 evo_data(push, 0x00200000); /* ??? */
381 evo_data(push, mode->clock * 1000);
629c1b92
BS		 382 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 1);
383 evo_data(push, syncs);
438d99e3
BS		 384 evo_kick(push, crtc->dev, 0);
385 }
386
387 nv_connector = nouveau_crtc_connector_get(nv_crtc);
388 nvd0_crtc_set_dither(nv_crtc, nv_connector->use_dithering, false);
389 nvd0_crtc_set_scale(nv_crtc, nv_connector->scaling_mode, false);
390 nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
391 return 0;
392}
393
394static int
395nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
396 struct drm_framebuffer *old_fb)
397{
398 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
399 int ret;
400
401 ret = nvd0_crtc_swap_fbs(crtc, old_fb);
402 if (ret)
403 return ret;
404
405 nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
406 return 0;
407}
408
409static int
410nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
411 struct drm_framebuffer *fb, int x, int y,
412 enum mode_set_atomic state)
413{
414 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
415 nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
416 return 0;
417}
418
419static void
420nvd0_crtc_lut_load(struct drm_crtc *crtc)
421{
422 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
423 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
424 int i;
425
426 for (i = 0; i < 256; i++) {
8ea0d4aa
BS		 427 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
428 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
429 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
438d99e3
BS		 430 }
431}
432
433static int
434nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
435 uint32_t handle, uint32_t width, uint32_t height)
436{
437 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
438 struct drm_device *dev = crtc->dev;
439 struct drm_gem_object *gem;
440 struct nouveau_bo *nvbo;
441 bool visible = (handle != 0);
442 int i, ret = 0;
443
444 if (visible) {
445 if (width != 64 || height != 64)
446 return -EINVAL;
447
448 gem = drm_gem_object_lookup(dev, file_priv, handle);
449 if (unlikely(!gem))
450 return -ENOENT;
451 nvbo = nouveau_gem_object(gem);
452
453 ret = nouveau_bo_map(nvbo);
454 if (ret == 0) {
455 for (i = 0; i < 64 * 64; i++) {
456 u32 v = nouveau_bo_rd32(nvbo, i);
457 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
458 }
459 nouveau_bo_unmap(nvbo);
460 }
461
462 drm_gem_object_unreference_unlocked(gem);
463 }
464
465 if (visible != nv_crtc->cursor.visible) {
466 nvd0_crtc_cursor_show(nv_crtc, visible, true);
467 nv_crtc->cursor.visible = visible;
468 }
469
470 return ret;
471}
472
473static int
474nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
475{
476 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
477 const u32 data = (y << 16) | x;
478
479 nv_wr32(crtc->dev, 0x64d084 + (nv_crtc->index * 0x1000), data);
480 nv_wr32(crtc->dev, 0x64d080 + (nv_crtc->index * 0x1000), 0x00000000);
481 return 0;
482}
483
484static void
485nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
486 uint32_t start, uint32_t size)
487{
488 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
489 u32 end = max(start + size, (u32)256);
490 u32 i;
491
492 for (i = start; i < end; i++) {
493 nv_crtc->lut.r[i] = r[i];
494 nv_crtc->lut.g[i] = g[i];
495 nv_crtc->lut.b[i] = b[i];
496 }
497
498 nvd0_crtc_lut_load(crtc);
499}
500
501static void
502nvd0_crtc_destroy(struct drm_crtc *crtc)
503{
504 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
505 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
506 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
507 nouveau_bo_unmap(nv_crtc->lut.nvbo);
508 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
509 drm_crtc_cleanup(crtc);
510 kfree(crtc);
511}
512
513static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
514 .dpms = nvd0_crtc_dpms,
515 .prepare = nvd0_crtc_prepare,
516 .commit = nvd0_crtc_commit,
517 .mode_fixup = nvd0_crtc_mode_fixup,
518 .mode_set = nvd0_crtc_mode_set,
519 .mode_set_base = nvd0_crtc_mode_set_base,
520 .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
521 .load_lut = nvd0_crtc_lut_load,
522};
523
524static const struct drm_crtc_funcs nvd0_crtc_func = {
525 .cursor_set = nvd0_crtc_cursor_set,
526 .cursor_move = nvd0_crtc_cursor_move,
527 .gamma_set = nvd0_crtc_gamma_set,
528 .set_config = drm_crtc_helper_set_config,
529 .destroy = nvd0_crtc_destroy,
530};
531
532static int
533nvd0_crtc_create(struct drm_device *dev, int index)
534{
535 struct nouveau_crtc *nv_crtc;
536 struct drm_crtc *crtc;
537 int ret, i;
538
539 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
540 if (!nv_crtc)
541 return -ENOMEM;
542
543 nv_crtc->index = index;
544 nv_crtc->set_dither = nvd0_crtc_set_dither;
545 nv_crtc->set_scale = nvd0_crtc_set_scale;
546 for (i = 0; i < 256; i++) {
547 nv_crtc->lut.r[i] = i << 8;
548 nv_crtc->lut.g[i] = i << 8;
549 nv_crtc->lut.b[i] = i << 8;
550 }
551
552 crtc = &nv_crtc->base;
553 drm_crtc_init(dev, crtc, &nvd0_crtc_func);
554 drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
555 drm_mode_crtc_set_gamma_size(crtc, 256);
556
557 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
558 0, 0x0000, &nv_crtc->cursor.nvbo);
559 if (!ret) {
560 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
561 if (!ret)
562 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
563 if (ret)
564 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
565 }
566
567 if (ret)
568 goto out;
569
8ea0d4aa 570 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
438d99e3
BS		 571 0, 0x0000, &nv_crtc->lut.nvbo);
572 if (!ret) {
573 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
574 if (!ret)
575 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
576 if (ret)
577 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
578 }
579
580 if (ret)
581 goto out;
582
583 nvd0_crtc_lut_load(crtc);
584
585out:
586 if (ret)
587 nvd0_crtc_destroy(crtc);
588 return ret;
589}
590
26f6d88b
BS		 591/******************************************************************************
592 * DAC
593 *****************************************************************************/
8eaa9669
BS		 594static void
595nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
596{
597 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
598 struct drm_device *dev = encoder->dev;
599 int or = nv_encoder->or;
600 u32 dpms_ctrl;
601
602 dpms_ctrl = 0x80000000;
603 if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
604 dpms_ctrl |= 0x00000001;
605 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
606 dpms_ctrl |= 0x00000004;
607
608 nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
609 nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
610 nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
611}
612
613static bool
614nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
615 struct drm_display_mode *adjusted_mode)
616{
617 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
618 struct nouveau_connector *nv_connector;
619
620 nv_connector = nouveau_encoder_connector_get(nv_encoder);
621 if (nv_connector && nv_connector->native_mode) {
622 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
623 int id = adjusted_mode->base.id;
624 *adjusted_mode = *nv_connector->native_mode;
625 adjusted_mode->base.id = id;
626 }
627 }
628
629 return true;
630}
631
632static void
633nvd0_dac_prepare(struct drm_encoder *encoder)
634{
635}
636
637static void
638nvd0_dac_commit(struct drm_encoder *encoder)
639{
640}
641
642static void
643nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
644 struct drm_display_mode *adjusted_mode)
645{
646 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
647 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
648 u32 *push;
649
650 nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
651
ff8ff503 652 push = evo_wait(encoder->dev, 0, 4);
8eaa9669 653 if (push) {
ff8ff503 654 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 2);
8eaa9669 655 evo_data(push, 1 << nv_crtc->index);
ff8ff503 656 evo_data(push, 0x00ff);
8eaa9669
BS		 657 evo_kick(push, encoder->dev, 0);
658 }
659
660 nv_encoder->crtc = encoder->crtc;
661}
662
663static void
664nvd0_dac_disconnect(struct drm_encoder *encoder)
665{
666 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
667 struct drm_device *dev = encoder->dev;
668 u32 *push;
669
670 if (nv_encoder->crtc) {
671 nvd0_crtc_prepare(nv_encoder->crtc);
672
673 push = evo_wait(dev, 0, 4);
674 if (push) {
675 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
676 evo_data(push, 0x00000000);
677 evo_mthd(push, 0x0080, 1);
678 evo_data(push, 0x00000000);
679 evo_kick(push, dev, 0);
680 }
681
682 nv_encoder->crtc = NULL;
683 }
684}
685
b6d8e7ec
BS		 686static enum drm_connector_status
687nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
688{
b681993f
BS		 689 enum drm_connector_status status = connector_status_disconnected;
690 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
691 struct drm_device *dev = encoder->dev;
692 int or = nv_encoder->or;
693 u32 load;
694
695 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
696 udelay(9500);
697 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
698
699 load = nv_rd32(dev, 0x61a00c + (or * 0x800));
700 if ((load & 0x38000000) == 0x38000000)
701 status = connector_status_connected;
702
703 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
704 return status;
b6d8e7ec
BS		 705}
706
8eaa9669
BS		 707static void
708nvd0_dac_destroy(struct drm_encoder *encoder)
709{
710 drm_encoder_cleanup(encoder);
711 kfree(encoder);
712}
713
714static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
715 .dpms = nvd0_dac_dpms,
716 .mode_fixup = nvd0_dac_mode_fixup,
717 .prepare = nvd0_dac_prepare,
718 .commit = nvd0_dac_commit,
719 .mode_set = nvd0_dac_mode_set,
720 .disable = nvd0_dac_disconnect,
721 .get_crtc = nvd0_display_crtc_get,
b6d8e7ec 722 .detect = nvd0_dac_detect
8eaa9669
BS		 723};
724
725static const struct drm_encoder_funcs nvd0_dac_func = {
726 .destroy = nvd0_dac_destroy,
727};
728
729static int
730nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe)
731{
732 struct drm_device *dev = connector->dev;
733 struct nouveau_encoder *nv_encoder;
734 struct drm_encoder *encoder;
735
736 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
737 if (!nv_encoder)
738 return -ENOMEM;
739 nv_encoder->dcb = dcbe;
740 nv_encoder->or = ffs(dcbe->or) - 1;
741
742 encoder = to_drm_encoder(nv_encoder);
743 encoder->possible_crtcs = dcbe->heads;
744 encoder->possible_clones = 0;
745 drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
746 drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
747
748 drm_mode_connector_attach_encoder(connector, encoder);
749 return 0;
750}
26f6d88b
BS		 751
752/******************************************************************************
753 * SOR
754 *****************************************************************************/
83fc083c
BS		 755static void
756nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
757{
758 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
759 struct drm_device *dev = encoder->dev;
760 struct drm_encoder *partner;
761 int or = nv_encoder->or;
762 u32 dpms_ctrl;
763
764 nv_encoder->last_dpms = mode;
765
766 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
767 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
768
769 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
770 continue;
771
772 if (nv_partner != nv_encoder &&
773 nv_partner->dcb->or == nv_encoder->or) {
774 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
775 return;
776 break;
777 }
778 }
779
780 dpms_ctrl = (mode == DRM_MODE_DPMS_ON);
781 dpms_ctrl |= 0x80000000;
782
783 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
784 nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
785 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
786 nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
787}
788
789static bool
790nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
791 struct drm_display_mode *adjusted_mode)
792{
793 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
794 struct nouveau_connector *nv_connector;
795
796 nv_connector = nouveau_encoder_connector_get(nv_encoder);
797 if (nv_connector && nv_connector->native_mode) {
798 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
799 int id = adjusted_mode->base.id;
800 *adjusted_mode = *nv_connector->native_mode;
801 adjusted_mode->base.id = id;
802 }
803 }
804
805 return true;
806}
807
808static void
809nvd0_sor_prepare(struct drm_encoder *encoder)
810{
811}
812
813static void
814nvd0_sor_commit(struct drm_encoder *encoder)
815{
816}
817
818static void
3b6d83d1
BS		 819nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
820 struct drm_display_mode *mode)
83fc083c 821{
3b6d83d1 822 struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
83fc083c
BS		 823 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
824 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3b6d83d1
BS		 825 struct nouveau_connector *nv_connector;
826 struct nvbios *bios = &dev_priv->vbios;
83fc083c 827 u32 mode_ctrl = (1 << nv_crtc->index);
ff8ff503 828 u32 *push, or_config;
83fc083c 829
3b6d83d1
BS		 830 nv_connector = nouveau_encoder_connector_get(nv_encoder);
831 switch (nv_encoder->dcb->type) {
832 case OUTPUT_TMDS:
833 if (nv_encoder->dcb->sorconf.link & 1) {
834 if (mode->clock < 165000)
835 mode_ctrl |= 0x00000100;
836 else
837 mode_ctrl |= 0x00000500;
838 } else {
839 mode_ctrl |= 0x00000200;
840 }
841
842 or_config = (mode_ctrl & 0x00000f00) >> 8;
843 if (mode->clock >= 165000)
844 or_config |= 0x0100;
845 break;
846 case OUTPUT_LVDS:
847 or_config = (mode_ctrl & 0x00000f00) >> 8;
848 if (bios->fp_no_ddc) {
849 if (bios->fp.dual_link)
850 or_config |= 0x0100;
851 if (bios->fp.if_is_24bit)
852 or_config |= 0x0200;
853 } else {
854 if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS_SPWG) {
855 if (((u8 *)nv_connector->edid)[121] == 2)
856 or_config |= 0x0100;
857 } else
858 if (mode->clock >= bios->fp.duallink_transition_clk) {
859 or_config |= 0x0100;
860 }
83fc083c 861
3b6d83d1
BS		 862 if (or_config & 0x0100) {
863 if (bios->fp.strapless_is_24bit & 2)
864 or_config |= 0x0200;
865 } else {
866 if (bios->fp.strapless_is_24bit & 1)
867 or_config |= 0x0200;
868 }
869
870 if (nv_connector->base.display_info.bpc == 8)
871 or_config |= 0x0200;
872
873 }
874 break;
875 default:
876 BUG_ON(1);
877 break;
878 }
ff8ff503 879
83fc083c
BS		 880 nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
881
ff8ff503 882 push = evo_wait(encoder->dev, 0, 4);
83fc083c 883 if (push) {
ff8ff503 884 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 2);
83fc083c 885 evo_data(push, mode_ctrl);
ff8ff503 886 evo_data(push, or_config);
438d99e3 887 evo_kick(push, encoder->dev, 0);
83fc083c
BS		 888 }
889
890 nv_encoder->crtc = encoder->crtc;
891}
892
893static void
894nvd0_sor_disconnect(struct drm_encoder *encoder)
895{
896 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
897 struct drm_device *dev = encoder->dev;
438d99e3 898 u32 *push;
83fc083c
BS		 899
900 if (nv_encoder->crtc) {
438d99e3
BS		 901 nvd0_crtc_prepare(nv_encoder->crtc);
902
903 push = evo_wait(dev, 0, 4);
83fc083c
BS		 904 if (push) {
905 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
906 evo_data(push, 0x00000000);
907 evo_mthd(push, 0x0080, 1);
908 evo_data(push, 0x00000000);
909 evo_kick(push, dev, 0);
910 }
911
912 nv_encoder->crtc = NULL;
913 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
914 }
915}
916
917static void
918nvd0_sor_destroy(struct drm_encoder *encoder)
919{
920 drm_encoder_cleanup(encoder);
921 kfree(encoder);
922}
923
924static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
925 .dpms = nvd0_sor_dpms,
926 .mode_fixup = nvd0_sor_mode_fixup,
927 .prepare = nvd0_sor_prepare,
928 .commit = nvd0_sor_commit,
929 .mode_set = nvd0_sor_mode_set,
930 .disable = nvd0_sor_disconnect,
931 .get_crtc = nvd0_display_crtc_get,
932};
933
934static const struct drm_encoder_funcs nvd0_sor_func = {
935 .destroy = nvd0_sor_destroy,
936};
937
938static int
939nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
940{
941 struct drm_device *dev = connector->dev;
942 struct nouveau_encoder *nv_encoder;
943 struct drm_encoder *encoder;
944
945 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
946 if (!nv_encoder)
947 return -ENOMEM;
948 nv_encoder->dcb = dcbe;
949 nv_encoder->or = ffs(dcbe->or) - 1;
950 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
951
952 encoder = to_drm_encoder(nv_encoder);
953 encoder->possible_crtcs = dcbe->heads;
954 encoder->possible_clones = 0;
955 drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
956 drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
957
958 drm_mode_connector_attach_encoder(connector, encoder);
959 return 0;
960}
26f6d88b
BS		 961
962/******************************************************************************
963 * IRQ
964 *****************************************************************************/
3a89cd02
BS		 965static struct dcb_entry *
966lookup_dcb(struct drm_device *dev, int id, u32 mc)
967{
968 struct drm_nouveau_private *dev_priv = dev->dev_private;
969 int type, or, i;
970
971 if (id < 4) {
972 type = OUTPUT_ANALOG;
973 or = id;
974 } else {
3b6d83d1
BS		 975 switch (mc & 0x00000f00) {
976 case 0x00000000: type = OUTPUT_LVDS; break;
977 case 0x00000100: type = OUTPUT_TMDS; break;
978 case 0x00000200: type = OUTPUT_TMDS; break;
979 case 0x00000500: type = OUTPUT_TMDS; break;
980 default:
981 return NULL;
982 }
983
984 or = id - 4;
3a89cd02
BS		 985 }
986
987 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
988 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
989 if (dcb->type == type && (dcb->or & (1 << or)))
990 return dcb;
991 }
992
993 NV_INFO(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
994 return NULL;
995}
996
270a5747
BS		 997static void
998nvd0_display_unk1_handler(struct drm_device *dev)
999{
3a89cd02
BS		 1000 struct nvd0_display *disp = nvd0_display(dev);
1001 struct dcb_entry *dcb;
1002 u32 unkn, crtc = 0;
1003 int i;
1004
a36f04c0
BS		 1005 NV_INFO(dev, "PDISP: 1 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
1006 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
270a5747 1007
3a89cd02
BS		 1008 unkn = nv_rd32(dev, 0x6101d4);
1009 if (!unkn) {
1010 unkn = nv_rd32(dev, 0x6109d4);
1011 crtc = 1;
1012 }
1013
1014 disp->irq.ena = NULL;
1015 disp->irq.dis = NULL;
1016 disp->irq.crtc = crtc;
1017 disp->irq.pclk = nv_rd32(dev, 0x660450 + (disp->irq.crtc * 0x300));
1018 disp->irq.pclk /= 1000;
1019
1020 for (i = 0; i < 8; i++) {
1021 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1022 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1023
1024 if (mcc & (1 << crtc))
1025 disp->irq.dis = lookup_dcb(dev, i, mcc);
1026
1027 if (mcp & (1 << crtc)) {
ff8ff503 1028 disp->irq.cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
3a89cd02 1029 disp->irq.ena = lookup_dcb(dev, i, mcp);
3a89cd02
BS		 1030 }
1031 }
1032
1033 dcb = disp->irq.dis;
1034 if (dcb)
1035 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1036
270a5747
BS		 1037 nv_wr32(dev, 0x6101d4, 0x00000000);
1038 nv_wr32(dev, 0x6109d4, 0x00000000);
1039 nv_wr32(dev, 0x6101d0, 0x80000000);
1040}
1041
1042static void
1043nvd0_display_unk2_handler(struct drm_device *dev)
1044{
3a89cd02
BS		 1045 struct nvd0_display *disp = nvd0_display(dev);
1046 struct dcb_entry *dcb;
1047 int crtc = disp->irq.crtc;
1048 int pclk = disp->irq.pclk;
1049 int or;
1050 u32 tmp;
1051
a36f04c0
BS		 1052 NV_INFO(dev, "PDISP: 2 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
1053 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
270a5747 1054
3a89cd02
BS		 1055 dcb = disp->irq.dis;
1056 disp->irq.dis = NULL;
1057 if (dcb)
1058 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1059
1060 nv50_crtc_set_clock(dev, crtc, pclk);
1061
1062 dcb = disp->irq.ena;
1063 if (!dcb)
1064 goto ack;
1065 or = ffs(dcb->or) - 1;
1066
ff8ff503 1067 nouveau_bios_run_display_table(dev, disp->irq.cfg, pclk, dcb, crtc);
3a89cd02
BS		 1068
1069 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1070 switch (dcb->type) {
1071 case OUTPUT_ANALOG:
1072 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1073 break;
1074 case OUTPUT_TMDS:
3b6d83d1
BS		 1075 case OUTPUT_LVDS:
1076 if (disp->irq.cfg & 0x00000100)
3a89cd02
BS		 1077 tmp = 0x00000101;
1078 else
1079 tmp = 0x00000000;
1080
1081 nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1082 break;
1083 default:
1084 break;
1085 }
1086
1087ack:
270a5747
BS		 1088 nv_wr32(dev, 0x6101d4, 0x00000000);
1089 nv_wr32(dev, 0x6109d4, 0x00000000);
1090 nv_wr32(dev, 0x6101d0, 0x80000000);
1091}
1092
1093static void
1094nvd0_display_unk4_handler(struct drm_device *dev)
1095{
3a89cd02
BS		 1096 struct nvd0_display *disp = nvd0_display(dev);
1097 struct dcb_entry *dcb;
1098 int crtc = disp->irq.crtc;
1099 int pclk = disp->irq.pclk;
1100
a36f04c0
BS		 1101 NV_INFO(dev, "PDISP: 4 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
1102 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
270a5747 1103
3a89cd02
BS		 1104 dcb = disp->irq.ena;
1105 disp->irq.ena = NULL;
1106 if (!dcb)
1107 goto ack;
1108
ff8ff503 1109 nouveau_bios_run_display_table(dev, disp->irq.cfg, pclk, dcb, crtc);
3a89cd02
BS		 1110
1111ack:
270a5747
BS		 1112 nv_wr32(dev, 0x6101d4, 0x00000000);
1113 nv_wr32(dev, 0x6109d4, 0x00000000);
1114 nv_wr32(dev, 0x6101d0, 0x80000000);
1115}
1116
4600522a
BS		 1117static void
1118nvd0_display_intr(struct drm_device *dev)
1119{
1120 u32 intr = nv_rd32(dev, 0x610088);
1121
1122 if (intr & 0x00000002) {
1123 u32 stat = nv_rd32(dev, 0x61009c);
1124 int chid = ffs(stat) - 1;
1125 if (chid >= 0) {
1126 u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1127 u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1128 u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1129
1130 NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1131 "0x%08x 0x%08x\n",
1132 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1133 nv_wr32(dev, 0x61009c, (1 << chid));
1134 nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1135 }
1136
1137 intr &= ~0x00000002;
1138 }
1139
270a5747
BS		 1140 if (intr & 0x00100000) {
1141 u32 stat = nv_rd32(dev, 0x6100ac);
1142
1143 if (stat & 0x00000007) {
1144 nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1145
1146 if (stat & 0x00000001)
1147 nvd0_display_unk1_handler(dev);
1148 if (stat & 0x00000002)
1149 nvd0_display_unk2_handler(dev);
1150 if (stat & 0x00000004)
1151 nvd0_display_unk4_handler(dev);
1152 stat &= ~0x00000007;
1153 }
1154
1155 if (stat) {
1156 NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1157 nv_wr32(dev, 0x6100ac, stat);
1158 }
1159
1160 intr &= ~0x00100000;
1161 }
1162
4600522a
BS		 1163 if (intr & 0x01000000) {
1164 u32 stat = nv_rd32(dev, 0x6100bc);
1165 nv_wr32(dev, 0x6100bc, stat);
1166 intr &= ~0x01000000;
1167 }
1168
1169 if (intr & 0x02000000) {
1170 u32 stat = nv_rd32(dev, 0x6108bc);
1171 nv_wr32(dev, 0x6108bc, stat);
1172 intr &= ~0x02000000;
1173 }
1174
1175 if (intr)
1176 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1177}
26f6d88b
BS		 1178
1179/******************************************************************************
1180 * Init
1181 *****************************************************************************/
1182static void
1183nvd0_display_fini(struct drm_device *dev)
1184{
1185 int i;
1186
1187 /* fini cursors */
1188 for (i = 14; i >= 13; i--) {
1189 if (!(nv_rd32(dev, 0x610490 + (i * 0x10)) & 0x00000001))
1190 continue;
1191
1192 nv_mask(dev, 0x610490 + (i * 0x10), 0x00000001, 0x00000000);
1193 nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00000000);
1194 nv_mask(dev, 0x610090, 1 << i, 0x00000000);
1195 nv_mask(dev, 0x6100a0, 1 << i, 0x00000000);
1196 }
1197
1198 /* fini master */
1199 if (nv_rd32(dev, 0x610490) & 0x00000010) {
1200 nv_mask(dev, 0x610490, 0x00000010, 0x00000000);
1201 nv_mask(dev, 0x610490, 0x00000003, 0x00000000);
1202 nv_wait(dev, 0x610490, 0x80000000, 0x00000000);
1203 nv_mask(dev, 0x610090, 0x00000001, 0x00000000);
1204 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000000);
1205 }
1206}
1207
1208int
1209nvd0_display_init(struct drm_device *dev)
1210{
1211 struct nvd0_display *disp = nvd0_display(dev);
efd272a7 1212 u32 *push;
26f6d88b
BS		 1213 int i;
1214
a36f04c0
BS		 1215 if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1216 nv_wr32(dev, 0x6100ac, 0x00000100);
1217 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1218 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1219 NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1220 nv_rd32(dev, 0x6194e8));
1221 return -EBUSY;
1222 }
1223 }
1224
1225 /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1226 * work at all unless you do the SOR part below.
1227 */
1d6e7a59
BS		 1228 for (i = 0; i < 3; i++) {
1229 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1230 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1231 }
1232
1d6e7a59
BS		 1233 for (i = 0; i < 4; i++) {
1234 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1235 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1236 }
1237
a36f04c0
BS		 1238 for (i = 0; i < 2; i++) {
1239 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1240 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1241 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1242 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1243 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1244 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
26f6d88b
BS		 1245 }
1246
a36f04c0 1247 /* point at our hash table / objects, enable interrupts */
26f6d88b 1248 nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
270a5747 1249 nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
26f6d88b
BS		 1250
1251 /* init master */
51beb428 1252 nv_wr32(dev, 0x610494, (disp->evo[0].handle >> 8) | 3);
26f6d88b 1253 nv_wr32(dev, 0x610498, 0x00010000);
efd272a7 1254 nv_wr32(dev, 0x61049c, 0x00000001);
26f6d88b
BS		 1255 nv_mask(dev, 0x610490, 0x00000010, 0x00000010);
1256 nv_wr32(dev, 0x640000, 0x00000000);
1257 nv_wr32(dev, 0x610490, 0x01000013);
1258 if (!nv_wait(dev, 0x610490, 0x80000000, 0x00000000)) {
1259 NV_ERROR(dev, "PDISP: master 0x%08x\n",
1260 nv_rd32(dev, 0x610490));
1261 return -EBUSY;
1262 }
1263 nv_mask(dev, 0x610090, 0x00000001, 0x00000001);
1264 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001);
1265
1266 /* init cursors */
1267 for (i = 13; i <= 14; i++) {
1268 nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001);
1269 if (!nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00010000)) {
1270 NV_ERROR(dev, "PDISP: curs%d 0x%08x\n", i,
1271 nv_rd32(dev, 0x610490 + (i * 0x10)));
1272 return -EBUSY;
1273 }
1274
1275 nv_mask(dev, 0x610090, 1 << i, 1 << i);
1276 nv_mask(dev, 0x6100a0, 1 << i, 1 << i);
1277 }
1278
efd272a7
BS		 1279 push = evo_wait(dev, 0, 32);
1280 if (!push)
1281 return -EBUSY;
1282 evo_mthd(push, 0x0088, 1);
1283 evo_data(push, MEM_SYNC);
1284 evo_mthd(push, 0x0084, 1);
1285 evo_data(push, 0x00000000);
1286 evo_mthd(push, 0x0084, 1);
1287 evo_data(push, 0x80000000);
1288 evo_mthd(push, 0x008c, 1);
1289 evo_data(push, 0x00000000);
1290 evo_kick(push, dev, 0);
1291
26f6d88b
BS		 1292 return 0;
1293}
1294
1295void
1296nvd0_display_destroy(struct drm_device *dev)
1297{
1298 struct drm_nouveau_private *dev_priv = dev->dev_private;
1299 struct nvd0_display *disp = nvd0_display(dev);
51beb428 1300 struct pci_dev *pdev = dev->pdev;
26f6d88b
BS		 1301
1302 nvd0_display_fini(dev);
1303
51beb428 1304 pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
26f6d88b 1305 nouveau_gpuobj_ref(NULL, &disp->mem);
4600522a 1306 nouveau_irq_unregister(dev, 26);
51beb428
BS		 1307
1308 dev_priv->engine.display.priv = NULL;
26f6d88b
BS		 1309 kfree(disp);
1310}
1311
1312int
1313nvd0_display_create(struct drm_device *dev)
1314{
1315 struct drm_nouveau_private *dev_priv = dev->dev_private;
efd272a7 1316 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
83fc083c
BS		 1317 struct dcb_table *dcb = &dev_priv->vbios.dcb;
1318 struct drm_connector *connector, *tmp;
51beb428 1319 struct pci_dev *pdev = dev->pdev;
26f6d88b 1320 struct nvd0_display *disp;
83fc083c
BS		 1321 struct dcb_entry *dcbe;
1322 int ret, i;
26f6d88b
BS		 1323
1324 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1325 if (!disp)
1326 return -ENOMEM;
1327 dev_priv->engine.display.priv = disp;
1328
438d99e3
BS		 1329 /* create crtc objects to represent the hw heads */
1330 for (i = 0; i < 2; i++) {
1331 ret = nvd0_crtc_create(dev, i);
1332 if (ret)
1333 goto out;
1334 }
1335
83fc083c
BS		 1336 /* create encoder/connector objects based on VBIOS DCB table */
1337 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1338 connector = nouveau_connector_create(dev, dcbe->connector);
1339 if (IS_ERR(connector))
1340 continue;
1341
1342 if (dcbe->location != DCB_LOC_ON_CHIP) {
1343 NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1344 dcbe->type, ffs(dcbe->or) - 1);
1345 continue;
1346 }
1347
1348 switch (dcbe->type) {
1349 case OUTPUT_TMDS:
3b6d83d1 1350 case OUTPUT_LVDS:
83fc083c
BS		 1351 nvd0_sor_create(connector, dcbe);
1352 break;
8eaa9669
BS		 1353 case OUTPUT_ANALOG:
1354 nvd0_dac_create(connector, dcbe);
1355 break;
83fc083c
BS		 1356 default:
1357 NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
1358 dcbe->type, ffs(dcbe->or) - 1);
1359 continue;
1360 }
1361 }
1362
1363 /* cull any connectors we created that don't have an encoder */
1364 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
1365 if (connector->encoder_ids[0])
1366 continue;
1367
1368 NV_WARN(dev, "%s has no encoders, removing\n",
1369 drm_get_connector_name(connector));
1370 connector->funcs->destroy(connector);
1371 }
1372
4600522a
BS		 1373 /* setup interrupt handling */
1374 nouveau_irq_register(dev, 26, nvd0_display_intr);
1375
51beb428 1376 /* hash table and dma objects for the memory areas we care about */
efd272a7
BS		 1377 ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
1378 NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
26f6d88b
BS		 1379 if (ret)
1380 goto out;
1381
efd272a7
BS		 1382 nv_wo32(disp->mem, 0x1000, 0x00000049);
1383 nv_wo32(disp->mem, 0x1004, (disp->mem->vinst + 0x2000) >> 8);
1384 nv_wo32(disp->mem, 0x1008, (disp->mem->vinst + 0x2fff) >> 8);
1385 nv_wo32(disp->mem, 0x100c, 0x00000000);
1386 nv_wo32(disp->mem, 0x1010, 0x00000000);
1387 nv_wo32(disp->mem, 0x1014, 0x00000000);
1388 nv_wo32(disp->mem, 0x0000, MEM_SYNC);
1389 nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
1390
c0cc92a1 1391 nv_wo32(disp->mem, 0x1020, 0x00000049);
efd272a7
BS		 1392 nv_wo32(disp->mem, 0x1024, 0x00000000);
1393 nv_wo32(disp->mem, 0x1028, (dev_priv->vram_size - 1) >> 8);
1394 nv_wo32(disp->mem, 0x102c, 0x00000000);
1395 nv_wo32(disp->mem, 0x1030, 0x00000000);
1396 nv_wo32(disp->mem, 0x1034, 0x00000000);
1397 nv_wo32(disp->mem, 0x0008, MEM_VRAM);
1398 nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
1399
c0cc92a1
BS		 1400 nv_wo32(disp->mem, 0x1040, 0x00000009);
1401 nv_wo32(disp->mem, 0x1044, 0x00000000);
1402 nv_wo32(disp->mem, 0x1048, (dev_priv->vram_size - 1) >> 8);
1403 nv_wo32(disp->mem, 0x104c, 0x00000000);
1404 nv_wo32(disp->mem, 0x1050, 0x00000000);
1405 nv_wo32(disp->mem, 0x1054, 0x00000000);
1406 nv_wo32(disp->mem, 0x0010, NvEvoVRAM_LP);
1407 nv_wo32(disp->mem, 0x0014, (0x1040 << 9) | 0x00000001);
1408
1409 nv_wo32(disp->mem, 0x1060, 0x0fe00009);
1410 nv_wo32(disp->mem, 0x1064, 0x00000000);
1411 nv_wo32(disp->mem, 0x1068, (dev_priv->vram_size - 1) >> 8);
1412 nv_wo32(disp->mem, 0x106c, 0x00000000);
1413 nv_wo32(disp->mem, 0x1070, 0x00000000);
1414 nv_wo32(disp->mem, 0x1074, 0x00000000);
1415 nv_wo32(disp->mem, 0x0018, NvEvoFB32);
1416 nv_wo32(disp->mem, 0x001c, (0x1060 << 9) | 0x00000001);
1417
efd272a7
BS		 1418 pinstmem->flush(dev);
1419
51beb428
BS		 1420 /* push buffers for evo channels */
1421 disp->evo[0].ptr =
1422 pci_alloc_consistent(pdev, PAGE_SIZE, &disp->evo[0].handle);
1423 if (!disp->evo[0].ptr) {
1424 ret = -ENOMEM;
1425 goto out;
1426 }
1427
26f6d88b
BS		 1428 ret = nvd0_display_init(dev);
1429 if (ret)
1430 goto out;
1431
1432out:
1433 if (ret)
1434 nvd0_display_destroy(dev);
1435 return ret;
1436}
Linux 6.x block layer and io_uring tree(s)