[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nva3_pm.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_bios.h"
#include "nouveau_pm.h"

static u32 read_clk(struct drm_device *, int, bool);
static u32 read_pll(struct drm_device *, u32, int);

static u32
read_vco(struct drm_device *dev, int clk)
{
	u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
	if ((sctl & 0x00000030) != 0x00000030)
		return read_pll(dev, 0x00e820, 0x41);
	return read_pll(dev, 0x00e8a0, 0x42);
}

static u32
read_clk(struct drm_device *dev, int clk, bool ignore_en)
{
	u32 sctl, sdiv, sclk;

	if (clk >= 0x40)
		return 27000;

	sctl = nv_rd32(dev, 0x4120 + (clk * 4));
	if (!ignore_en && !(sctl & 0x00000100))
		return 0;

	switch (sctl & 0x00003000) {
	case 0x00000000:
		return 27000;
	case 0x00002000:
		if (sctl & 0x00000040)
			return 108000;
		return 100000;
	case 0x00003000:
		sclk = read_vco(dev, clk);
		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_pll(struct drm_device *dev, u32 pll, int clk)
{
	u32 ctrl = nv_rd32(dev, pll + 0);
	u32 sclk, P = 1, N = 1, M = 1;

	if (!(ctrl & 0x00000008)) {
		u32 coef = nv_rd32(dev, pll + 4);
		M = (coef & 0x000000ff) >> 0;
		N = (coef & 0x0000ff00) >> 8;
		P = (coef & 0x003f0000) >> 16;
		if ((pll & 0x00ff00) == 0x00e800)
			P = 1;

		sclk = read_clk(dev, 0x00 + clk, false);
	} else {
		sclk = read_clk(dev, 0x10 + clk, false);
	}

	return sclk * N / (M * P);
}

struct creg {
	u32 clk;
	u32 pll;
};

static int
calc_clk(struct drm_device *dev, u32 pll, int clk, u32 khz, struct creg *reg)
{
	struct pll_lims limits;
	u32 oclk, sclk, sdiv;
	int P, N, M, diff;
	int ret;

	reg->pll = 0;
	reg->clk = 0;

	switch (khz) {
	case 27000:
		reg->clk = 0x00000100;
		return khz;
	case 100000:
		reg->clk = 0x00002100;
		return khz;
	case 108000:
		reg->clk = 0x00002140;
		return khz;
	default:
		sclk = read_vco(dev, clk);
		sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
		if (sdiv > 4) {
			oclk = (sclk * 2) / sdiv;
			diff = khz - oclk;
			if (!pll || (diff >= -2000 && diff < 3000)) {
				reg->clk = (((sdiv - 2) << 16) | 0x00003100);
				return oclk;
			}
		}
		break;
	}

	ret = get_pll_limits(dev, pll, &limits);
	if (ret)
		return ret;

	limits.refclk = read_clk(dev, clk - 0x10, true);
	if (!limits.refclk)
		return -EINVAL;

	ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
	if (ret >= 0) {
		reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
		reg->pll = (P << 16) | (N << 8) | M;
	}
	return ret;
}

int
nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	perflvl->core   = read_pll(dev, 0x4200, 0);
	perflvl->shader = read_pll(dev, 0x4220, 1);
	perflvl->memory = read_pll(dev, 0x4000, 2);
	return 0;
}

struct nva3_pm_state {
	struct creg nclk;
	struct creg sclk;
	struct creg mclk;
};

void *
nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	struct nva3_pm_state *info;
	int ret;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info)
		return ERR_PTR(-ENOMEM);

	ret = calc_clk(dev, 0x4200, 0x10, perflvl->core, &info->nclk);
	if (ret < 0)
		goto out;

	ret = calc_clk(dev, 0x4220, 0x11, perflvl->shader, &info->sclk);
	if (ret < 0)
		goto out;

	ret = calc_clk(dev, 0x4000, 0x12, perflvl->memory, &info->mclk);
	if (ret < 0)
		goto out;

out:
	if (ret < 0) {
		kfree(info);
		info = ERR_PTR(ret);
	}
	return info;
}

static void
prog_pll(struct drm_device *dev, u32 pll, int clk, struct creg *reg)
{
	const u32 src0 = 0x004120 + (clk * 4);
	const u32 src1 = 0x004160 + (clk * 4);
	const u32 ctrl = pll + 0;
	const u32 coef = pll + 4;
	u32 cntl;

	cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
	if (reg->pll) {
		nv_mask(dev, src0, 0x00000101, 0x00000101);
		nv_wr32(dev, coef, reg->pll);
		nv_wr32(dev, ctrl, cntl | 0x00000015);
		nv_mask(dev, src1, 0x00000100, 0x00000000);
		nv_mask(dev, src1, 0x00000001, 0x00000000);
	} else {
		nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
		nv_wr32(dev, ctrl, cntl | 0x0000001d);
		nv_mask(dev, ctrl, 0x00000001, 0x00000000);
		nv_mask(dev, src0, 0x00000100, 0x00000000);
		nv_mask(dev, src0, 0x00000001, 0x00000000);
	}
}

void
nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
{
	struct nva3_pm_state *info = pre_state;

	prog_pll(dev, 0x004200, 0, &info->nclk);
	prog_pll(dev, 0x004220, 1, &info->sclk);

	nv_wr32(dev, 0x100210, 0);
	nv_wr32(dev, 0x1002dc, 1);
	nv_wr32(dev, 0x004018, 0x00001000);
	prog_pll(dev, 0x004000, 2, &info->mclk);
	if (nv_rd32(dev, 0x4000) & 0x00000008)
		nv_wr32(dev, 0x004018, 0x1000d000);
	else
		nv_wr32(dev, 0x004018, 0x10005000);
	nv_wr32(dev, 0x1002dc, 0);
	nv_wr32(dev, 0x100210, 0x80000000);

	kfree(info);
}
Commit	Line	Data
fade7ad5 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
	27	#include "nouveau_bios.h"
	28	#include "nouveau_pm.h"
	29
ca94a71f BS	30	static u32 read_clk(struct drm_device *, int, bool);
ca94a71f BS	31	static u32 read_pll(struct drm_device *, u32, int);
3b0582d3 BS	32
3b0582d3 BS	33	static u32
ca94a71f BS	34	read_vco(struct drm_device *dev, int clk)
	35	{
	36	u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4));
	37	if ((sctl & 0x00000030) != 0x00000030)
	38	return read_pll(dev, 0x00e820, 0x41);
	39	return read_pll(dev, 0x00e8a0, 0x42);
	40	}
	41
	42	static u32
	43	read_clk(struct drm_device *dev, int clk, bool ignore_en)
3b0582d3 BS	44	{
	45	u32 sctl, sdiv, sclk;
	46
	47	if (clk >= 0x40)
	48	return 27000;
	49
	50	sctl = nv_rd32(dev, 0x4120 + (clk * 4));
ca94a71f BS	51	if (!ignore_en && !(sctl & 0x00000100))
	52	return 0;
	53
	54	switch (sctl & 0x00003000) {
	55	case 0x00000000:
3b0582d3	56	return 27000;
ca94a71f	57	case 0x00002000:
3b0582d3 BS	58	if (sctl & 0x00000040)
	59	return 108000;
	60	return 100000;
ca94a71f BS	61	case 0x00003000:
ca94a71f BS	62	sclk = read_vco(dev, clk);
3b0582d3	63	sdiv = ((sctl & 0x003f0000) >> 16) + 2;
3b0582d3 BS	64	return (sclk * 2) / sdiv;
	65	default:
	66	return 0;
	67	}
	68	}
	69
	70	static u32
	71	read_pll(struct drm_device *dev, u32 pll, int clk)
	72	{
	73	u32 ctrl = nv_rd32(dev, pll + 0);
	74	u32 sclk, P = 1, N = 1, M = 1;
	75
	76	if (!(ctrl & 0x00000008)) {
	77	u32 coef = nv_rd32(dev, pll + 4);
	78	M = (coef & 0x000000ff) >> 0;
	79	N = (coef & 0x0000ff00) >> 8;
	80	P = (coef & 0x003f0000) >> 16;
	81	if ((pll & 0x00ff00) == 0x00e800)
	82	P = 1;
	83
ca94a71f	84	sclk = read_clk(dev, 0x00 + clk, false);
3b0582d3	85	} else {
ca94a71f	86	sclk = read_clk(dev, 0x10 + clk, false);
3b0582d3 BS	87	}
	88
	89	return sclk * N / (M * P);
	90	}
fade7ad5	91
ca94a71f BS	92	struct creg {
	93	u32 clk;
	94	u32 pll;
fade7ad5 BS	95	};
fade7ad5 BS	96
215f902e	97	static int
ca94a71f	98	calc_clk(struct drm_device dev, u32 pll, int clk, u32 khz, struct creg reg)
215f902e	99	{
ca94a71f BS	100	struct pll_lims limits;
	101	u32 oclk, sclk, sdiv;
	102	int P, N, M, diff;
	103	int ret;
	104
	105	reg->pll = 0;
	106	reg->clk = 0;
	107
	108	switch (khz) {
	109	case 27000:
	110	reg->clk = 0x00000100;
	111	return khz;
	112	case 100000:
	113	reg->clk = 0x00002100;
	114	return khz;
	115	case 108000:
	116	reg->clk = 0x00002140;
	117	return khz;
	118	default:
	119	sclk = read_vco(dev, clk);
	120	sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
	121	if (sdiv > 4) {
	122	oclk = (sclk * 2) / sdiv;
	123	diff = khz - oclk;
	124	if (!pll \|\| (diff >= -2000 && diff < 3000)) {
	125	reg->clk = (((sdiv - 2) << 16) \| 0x00003100);
	126	return oclk;
	127	}
	128	}
	129	break;
215f902e BS	130	}
215f902e BS	131
ca94a71f BS	132	ret = get_pll_limits(dev, pll, &limits);
	133	if (ret)
	134	return ret;
	135
	136	limits.refclk = read_clk(dev, clk - 0x10, true);
	137	if (!limits.refclk)
	138	return -EINVAL;
	139
	140	ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
	141	if (ret >= 0) {
	142	reg->clk = nv_rd32(dev, 0x4120 + (clk * 4));
	143	reg->pll = (P << 16) \| (N << 8) \| M;
	144	}
	145	return ret;
215f902e BS	146	}
215f902e BS	147
fade7ad5	148	int
ca94a71f	149	nva3_pm_clocks_get(struct drm_device dev, struct nouveau_pm_level perflvl)
fade7ad5	150	{
ca94a71f BS	151	perflvl->core = read_pll(dev, 0x4200, 0);
	152	perflvl->shader = read_pll(dev, 0x4220, 1);
	153	perflvl->memory = read_pll(dev, 0x4000, 2);
	154	return 0;
fade7ad5 BS	155	}
fade7ad5 BS	156
ca94a71f BS	157	struct nva3_pm_state {
	158	struct creg nclk;
	159	struct creg sclk;
	160	struct creg mclk;
	161	};
	162
fade7ad5	163	void *
ca94a71f	164	nva3_pm_clocks_pre(struct drm_device dev, struct nouveau_pm_level perflvl)
fade7ad5	165	{
ca94a71f BS	166	struct nva3_pm_state *info;
ca94a71f BS	167	int ret;
fade7ad5	168
ca94a71f BS	169	info = kzalloc(sizeof(*info), GFP_KERNEL);
	170	if (!info)
	171	return ERR_PTR(-ENOMEM);
	172
	173	ret = calc_clk(dev, 0x4200, 0x10, perflvl->core, &info->nclk);
dac55b58	174	if (ret < 0)
ca94a71f	175	goto out;
dac55b58	176
ca94a71f BS	177	ret = calc_clk(dev, 0x4220, 0x11, perflvl->shader, &info->sclk);
	178	if (ret < 0)
	179	goto out;
dac55b58	180
ca94a71f BS	181	ret = calc_clk(dev, 0x4000, 0x12, perflvl->memory, &info->mclk);
	182	if (ret < 0)
	183	goto out;
dac55b58	184
ca94a71f BS	185	out:
	186	if (ret < 0) {
	187	kfree(info);
	188	info = ERR_PTR(ret);
fade7ad5	189	}
ca94a71f BS	190	return info;
ca94a71f BS	191	}
fade7ad5	192
ca94a71f BS	193	static void
	194	prog_pll(struct drm_device dev, u32 pll, int clk, struct creg reg)
	195	{
	196	const u32 src0 = 0x004120 + (clk * 4);
	197	const u32 src1 = 0x004160 + (clk * 4);
	198	const u32 ctrl = pll + 0;
	199	const u32 coef = pll + 4;
	200	u32 cntl;
	201
	202	cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
	203	if (reg->pll) {
	204	nv_mask(dev, src0, 0x00000101, 0x00000101);
	205	nv_wr32(dev, coef, reg->pll);
	206	nv_wr32(dev, ctrl, cntl \| 0x00000015);
	207	nv_mask(dev, src1, 0x00000100, 0x00000000);
	208	nv_mask(dev, src1, 0x00000001, 0x00000000);
dac55b58	209	} else {
ca94a71f BS	210	nv_mask(dev, src1, 0x003f3141, 0x00000101 \| reg->clk);
	211	nv_wr32(dev, ctrl, cntl \| 0x0000001d);
	212	nv_mask(dev, ctrl, 0x00000001, 0x00000000);
	213	nv_mask(dev, src0, 0x00000100, 0x00000000);
	214	nv_mask(dev, src0, 0x00000001, 0x00000000);
fade7ad5	215	}
fade7ad5 BS	216	}
	217
	218	void
ca94a71f	219	nva3_pm_clocks_set(struct drm_device dev, void pre_state)
fade7ad5	220	{
ca94a71f BS	221	struct nva3_pm_state *info = pre_state;
	222
	223	prog_pll(dev, 0x004200, 0, &info->nclk);
	224	prog_pll(dev, 0x004220, 1, &info->sclk);
	225
	226	nv_wr32(dev, 0x100210, 0);
	227	nv_wr32(dev, 0x1002dc, 1);
	228	nv_wr32(dev, 0x004018, 0x00001000);
	229	prog_pll(dev, 0x004000, 2, &info->mclk);
	230	if (nv_rd32(dev, 0x4000) & 0x00000008)
	231	nv_wr32(dev, 0x004018, 0x1000d000);
	232	else
	233	nv_wr32(dev, 0x004018, 0x10005000);
	234	nv_wr32(dev, 0x1002dc, 0);
	235	nv_wr32(dev, 0x100210, 0x80000000);
	236
	237	kfree(info);
fade7ad5	238	}